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translate.c
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/*
* m68k translation
*
* Copyright (c) 2005-2007 CodeSourcery
* Written by Paul Brook
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include "config.h"
#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-log.h"
#include "helpers.h"
#define GEN_HELPER 1
#include "helpers.h"
//#define DEBUG_DISPATCH 1
/* Fake floating point. */
#define tcg_gen_mov_f64 tcg_gen_mov_i64
#define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
#define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
#define DEFO32(name, offset) static TCGv QREG_##name;
#define DEFO64(name, offset) static TCGv_i64 QREG_##name;
#define DEFF64(name, offset) static TCGv_i64 QREG_##name;
#include "qregs.def"
#undef DEFO32
#undef DEFO64
#undef DEFF64
static TCGv_ptr cpu_env;
static char cpu_reg_names[3*8*3 + 5*4];
static TCGv cpu_dregs[8];
static TCGv cpu_aregs[8];
static TCGv_i64 cpu_fregs[8];
static TCGv_i64 cpu_macc[4];
#define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
#define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
#define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
#define MACREG(acc) cpu_macc[acc]
#define QREG_SP cpu_aregs[7]
static TCGv NULL_QREG;
#define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
/* Used to distinguish stores from bad addressing modes. */
static TCGv store_dummy;
#include "gen-icount.h"
void m68k_tcg_init(void)
{
char *p;
int i;
#define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, offset), #name);
#define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, offset), #name);
#define DEFF64(name, offset) DEFO64(name, offset)
#include "qregs.def"
#undef DEFO32
#undef DEFO64
#undef DEFF64
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
p = cpu_reg_names;
for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i);
cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUM68KState, dregs[i]), p);
p += 3;
sprintf(p, "A%d", i);
cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUM68KState, aregs[i]), p);
p += 3;
sprintf(p, "F%d", i);
cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUM68KState, fregs[i]), p);
p += 3;
}
for (i = 0; i < 4; i++) {
sprintf(p, "ACC%d", i);
cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUM68KState, macc[i]), p);
p += 5;
}
NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
#define GEN_HELPER 2
#include "helpers.h"
}
static inline void qemu_assert(int cond, const char *msg)
{
if (!cond) {
fprintf (stderr, "badness: %s\n", msg);
abort();
}
}
/* internal defines */
typedef struct DisasContext {
CPUM68KState *env;
target_ulong insn_pc; /* Start of the current instruction. */
target_ulong pc;
int is_jmp;
int cc_op;
int user;
uint32_t fpcr;
struct TranslationBlock *tb;
int singlestep_enabled;
int is_mem;
TCGv_i64 mactmp;
int done_mac;
} DisasContext;
#define DISAS_JUMP_NEXT 4
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
#else
#define IS_USER(s) s->user
#endif
/* XXX: move that elsewhere */
/* ??? Fix exceptions. */
static void *gen_throws_exception;
#define gen_last_qop NULL
#define OS_BYTE 0
#define OS_WORD 1
#define OS_LONG 2
#define OS_SINGLE 4
#define OS_DOUBLE 5
typedef void (*disas_proc)(DisasContext *, uint16_t);
#ifdef DEBUG_DISPATCH
#define DISAS_INSN(name) \
static void real_disas_##name (DisasContext *s, uint16_t insn); \
static void disas_##name (DisasContext *s, uint16_t insn) { \
qemu_log("Dispatch " #name "\n"); \
real_disas_##name(s, insn); } \
static void real_disas_##name (DisasContext *s, uint16_t insn)
#else
#define DISAS_INSN(name) \
static void disas_##name (DisasContext *s, uint16_t insn)
#endif
/* FIXME: Remove this. */
#define gen_im32(val) tcg_const_i32(val)
/* Generate a load from the specified address. Narrow values are
sign extended to full register width. */
static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
{
TCGv tmp;
int index = IS_USER(s);
s->is_mem = 1;
tmp = tcg_temp_new_i32();
switch(opsize) {
case OS_BYTE:
if (sign)
tcg_gen_qemu_ld8s(tmp, addr, index);
else
tcg_gen_qemu_ld8u(tmp, addr, index);
break;
case OS_WORD:
if (sign)
tcg_gen_qemu_ld16s(tmp, addr, index);
else
tcg_gen_qemu_ld16u(tmp, addr, index);
break;
case OS_LONG:
case OS_SINGLE:
tcg_gen_qemu_ld32u(tmp, addr, index);
break;
default:
qemu_assert(0, "bad load size");
}
gen_throws_exception = gen_last_qop;
return tmp;
}
static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
{
TCGv_i64 tmp;
int index = IS_USER(s);
s->is_mem = 1;
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ldf64(tmp, addr, index);
gen_throws_exception = gen_last_qop;
return tmp;
}
/* Generate a store. */
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
{
int index = IS_USER(s);
s->is_mem = 1;
switch(opsize) {
case OS_BYTE:
tcg_gen_qemu_st8(val, addr, index);
break;
case OS_WORD:
tcg_gen_qemu_st16(val, addr, index);
break;
case OS_LONG:
case OS_SINGLE:
tcg_gen_qemu_st32(val, addr, index);
break;
default:
qemu_assert(0, "bad store size");
}
gen_throws_exception = gen_last_qop;
}
static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
{
int index = IS_USER(s);
s->is_mem = 1;
tcg_gen_qemu_stf64(val, addr, index);
gen_throws_exception = gen_last_qop;
}
typedef enum {
EA_STORE,
EA_LOADU,
EA_LOADS
} ea_what;
/* Generate an unsigned load if VAL is 0 a signed load if val is -1,
otherwise generate a store. */
static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
ea_what what)
{
if (what == EA_STORE) {
gen_store(s, opsize, addr, val);
return store_dummy;
} else {
return gen_load(s, opsize, addr, what == EA_LOADS);
}
}
/* Read a 32-bit immediate constant. */
static inline uint32_t read_im32(DisasContext *s)
{
uint32_t im;
im = ((uint32_t)lduw_code(s->pc)) << 16;
s->pc += 2;
im |= lduw_code(s->pc);
s->pc += 2;
return im;
}
/* Calculate and address index. */
static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
{
TCGv add;
int scale;
add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
if ((ext & 0x800) == 0) {
tcg_gen_ext16s_i32(tmp, add);
add = tmp;
}
scale = (ext >> 9) & 3;
if (scale != 0) {
tcg_gen_shli_i32(tmp, add, scale);
add = tmp;
}
return add;
}
/* Handle a base + index + displacement effective addresss.
A NULL_QREG base means pc-relative. */
static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
{
uint32_t offset;
uint16_t ext;
TCGv add;
TCGv tmp;
uint32_t bd, od;
offset = s->pc;
ext = lduw_code(s->pc);
s->pc += 2;
if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
return NULL_QREG;
if (ext & 0x100) {
/* full extension word format */
if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
return NULL_QREG;
if ((ext & 0x30) > 0x10) {
/* base displacement */
if ((ext & 0x30) == 0x20) {
bd = (int16_t)lduw_code(s->pc);
s->pc += 2;
} else {
bd = read_im32(s);
}
} else {
bd = 0;
}
tmp = tcg_temp_new();
if ((ext & 0x44) == 0) {
/* pre-index */
add = gen_addr_index(ext, tmp);
} else {
add = NULL_QREG;
}
if ((ext & 0x80) == 0) {
/* base not suppressed */
if (IS_NULL_QREG(base)) {
base = gen_im32(offset + bd);
bd = 0;
}
if (!IS_NULL_QREG(add)) {
tcg_gen_add_i32(tmp, add, base);
add = tmp;
} else {
add = base;
}
}
if (!IS_NULL_QREG(add)) {
if (bd != 0) {
tcg_gen_addi_i32(tmp, add, bd);
add = tmp;
}
} else {
add = gen_im32(bd);
}
if ((ext & 3) != 0) {
/* memory indirect */
base = gen_load(s, OS_LONG, add, 0);
if ((ext & 0x44) == 4) {
add = gen_addr_index(ext, tmp);
tcg_gen_add_i32(tmp, add, base);
add = tmp;
} else {
add = base;
}
if ((ext & 3) > 1) {
/* outer displacement */
if ((ext & 3) == 2) {
od = (int16_t)lduw_code(s->pc);
s->pc += 2;
} else {
od = read_im32(s);
}
} else {
od = 0;
}
if (od != 0) {
tcg_gen_addi_i32(tmp, add, od);
add = tmp;
}
}
} else {
/* brief extension word format */
tmp = tcg_temp_new();
add = gen_addr_index(ext, tmp);
if (!IS_NULL_QREG(base)) {
tcg_gen_add_i32(tmp, add, base);
if ((int8_t)ext)
tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
} else {
tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
}
add = tmp;
}
return add;
}
/* Update the CPU env CC_OP state. */
static inline void gen_flush_cc_op(DisasContext *s)
{
if (s->cc_op != CC_OP_DYNAMIC)
tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
}
/* Evaluate all the CC flags. */
static inline void gen_flush_flags(DisasContext *s)
{
if (s->cc_op == CC_OP_FLAGS)
return;
gen_flush_cc_op(s);
gen_helper_flush_flags(cpu_env, QREG_CC_OP);
s->cc_op = CC_OP_FLAGS;
}
static void gen_logic_cc(DisasContext *s, TCGv val)
{
tcg_gen_mov_i32(QREG_CC_DEST, val);
s->cc_op = CC_OP_LOGIC;
}
static void gen_update_cc_add(TCGv dest, TCGv src)
{
tcg_gen_mov_i32(QREG_CC_DEST, dest);
tcg_gen_mov_i32(QREG_CC_SRC, src);
}
static inline int opsize_bytes(int opsize)
{
switch (opsize) {
case OS_BYTE: return 1;
case OS_WORD: return 2;
case OS_LONG: return 4;
case OS_SINGLE: return 4;
case OS_DOUBLE: return 8;
default:
qemu_assert(0, "bad operand size");
return 0;
}
}
/* Assign value to a register. If the width is less than the register width
only the low part of the register is set. */
static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
{
TCGv tmp;
switch (opsize) {
case OS_BYTE:
tcg_gen_andi_i32(reg, reg, 0xffffff00);
tmp = tcg_temp_new();
tcg_gen_ext8u_i32(tmp, val);
tcg_gen_or_i32(reg, reg, tmp);
break;
case OS_WORD:
tcg_gen_andi_i32(reg, reg, 0xffff0000);
tmp = tcg_temp_new();
tcg_gen_ext16u_i32(tmp, val);
tcg_gen_or_i32(reg, reg, tmp);
break;
case OS_LONG:
case OS_SINGLE:
tcg_gen_mov_i32(reg, val);
break;
default:
qemu_assert(0, "Bad operand size");
break;
}
}
/* Sign or zero extend a value. */
static inline TCGv gen_extend(TCGv val, int opsize, int sign)
{
TCGv tmp;
switch (opsize) {
case OS_BYTE:
tmp = tcg_temp_new();
if (sign)
tcg_gen_ext8s_i32(tmp, val);
else
tcg_gen_ext8u_i32(tmp, val);
break;
case OS_WORD:
tmp = tcg_temp_new();
if (sign)
tcg_gen_ext16s_i32(tmp, val);
else
tcg_gen_ext16u_i32(tmp, val);
break;
case OS_LONG:
case OS_SINGLE:
tmp = val;
break;
default:
qemu_assert(0, "Bad operand size");
}
return tmp;
}
/* Generate code for an "effective address". Does not adjust the base
register for autoincrement addressing modes. */
static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
{
TCGv reg;
TCGv tmp;
uint16_t ext;
uint32_t offset;
switch ((insn >> 3) & 7) {
case 0: /* Data register direct. */
case 1: /* Address register direct. */
return NULL_QREG;
case 2: /* Indirect register */
case 3: /* Indirect postincrement. */
return AREG(insn, 0);
case 4: /* Indirect predecrememnt. */
reg = AREG(insn, 0);
tmp = tcg_temp_new();
tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
return tmp;
case 5: /* Indirect displacement. */
reg = AREG(insn, 0);
tmp = tcg_temp_new();
ext = lduw_code(s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
return tmp;
case 6: /* Indirect index + displacement. */
reg = AREG(insn, 0);
return gen_lea_indexed(s, opsize, reg);
case 7: /* Other */
switch (insn & 7) {
case 0: /* Absolute short. */
offset = ldsw_code(s->pc);
s->pc += 2;
return gen_im32(offset);
case 1: /* Absolute long. */
offset = read_im32(s);
return gen_im32(offset);
case 2: /* pc displacement */
tmp = tcg_temp_new();
offset = s->pc;
offset += ldsw_code(s->pc);
s->pc += 2;
return gen_im32(offset);
case 3: /* pc index+displacement. */
return gen_lea_indexed(s, opsize, NULL_QREG);
case 4: /* Immediate. */
default:
return NULL_QREG;
}
}
/* Should never happen. */
return NULL_QREG;
}
/* Helper function for gen_ea. Reuse the computed address between the
for read/write operands. */
static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
TCGv val, TCGv *addrp, ea_what what)
{
TCGv tmp;
if (addrp && what == EA_STORE) {
tmp = *addrp;
} else {
tmp = gen_lea(s, insn, opsize);
if (IS_NULL_QREG(tmp))
return tmp;
if (addrp)
*addrp = tmp;
}
return gen_ldst(s, opsize, tmp, val, what);
}
/* Generate code to load/store a value ito/from an EA. If VAL > 0 this is
a write otherwise it is a read (0 == sign extend, -1 == zero extend).
ADDRP is non-null for readwrite operands. */
static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
TCGv *addrp, ea_what what)
{
TCGv reg;
TCGv result;
uint32_t offset;
switch ((insn >> 3) & 7) {
case 0: /* Data register direct. */
reg = DREG(insn, 0);
if (what == EA_STORE) {
gen_partset_reg(opsize, reg, val);
return store_dummy;
} else {
return gen_extend(reg, opsize, what == EA_LOADS);
}
case 1: /* Address register direct. */
reg = AREG(insn, 0);
if (what == EA_STORE) {
tcg_gen_mov_i32(reg, val);
return store_dummy;
} else {
return gen_extend(reg, opsize, what == EA_LOADS);
}
case 2: /* Indirect register */
reg = AREG(insn, 0);
return gen_ldst(s, opsize, reg, val, what);
case 3: /* Indirect postincrement. */
reg = AREG(insn, 0);
result = gen_ldst(s, opsize, reg, val, what);
/* ??? This is not exception safe. The instruction may still
fault after this point. */
if (what == EA_STORE || !addrp)
tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
return result;
case 4: /* Indirect predecrememnt. */
{
TCGv tmp;
if (addrp && what == EA_STORE) {
tmp = *addrp;
} else {
tmp = gen_lea(s, insn, opsize);
if (IS_NULL_QREG(tmp))
return tmp;
if (addrp)
*addrp = tmp;
}
result = gen_ldst(s, opsize, tmp, val, what);
/* ??? This is not exception safe. The instruction may still
fault after this point. */
if (what == EA_STORE || !addrp) {
reg = AREG(insn, 0);
tcg_gen_mov_i32(reg, tmp);
}
}
return result;
case 5: /* Indirect displacement. */
case 6: /* Indirect index + displacement. */
return gen_ea_once(s, insn, opsize, val, addrp, what);
case 7: /* Other */
switch (insn & 7) {
case 0: /* Absolute short. */
case 1: /* Absolute long. */
case 2: /* pc displacement */
case 3: /* pc index+displacement. */
return gen_ea_once(s, insn, opsize, val, addrp, what);
case 4: /* Immediate. */
/* Sign extend values for consistency. */
switch (opsize) {
case OS_BYTE:
if (what == EA_LOADS)
offset = ldsb_code(s->pc + 1);
else
offset = ldub_code(s->pc + 1);
s->pc += 2;
break;
case OS_WORD:
if (what == EA_LOADS)
offset = ldsw_code(s->pc);
else
offset = lduw_code(s->pc);
s->pc += 2;
break;
case OS_LONG:
offset = read_im32(s);
break;
default:
qemu_assert(0, "Bad immediate operand");
}
return tcg_const_i32(offset);
default:
return NULL_QREG;
}
}
/* Should never happen. */
return NULL_QREG;
}
/* This generates a conditional branch, clobbering all temporaries. */
static void gen_jmpcc(DisasContext *s, int cond, int l1)
{
TCGv tmp;
/* TODO: Optimize compare/branch pairs rather than always flushing
flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
switch (cond) {
case 0: /* T */
tcg_gen_br(l1);
break;
case 1: /* F */
break;
case 2: /* HI (!C && !Z) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 3: /* LS (C || Z) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
case 4: /* CC (!C) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 5: /* CS (C) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
case 6: /* NE (!Z) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 7: /* EQ (Z) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
case 8: /* VC (!V) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 9: /* VS (V) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
case 10: /* PL (!N) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 11: /* MI (N) */
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
case 12: /* GE (!(N ^ V)) */
tmp = tcg_temp_new();
assert(CCF_V == (CCF_N >> 2));
tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
tcg_gen_andi_i32(tmp, tmp, CCF_V);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 13: /* LT (N ^ V) */
tmp = tcg_temp_new();
assert(CCF_V == (CCF_N >> 2));
tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
tcg_gen_andi_i32(tmp, tmp, CCF_V);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
case 14: /* GT (!(Z || (N ^ V))) */
tmp = tcg_temp_new();
assert(CCF_V == (CCF_N >> 2));
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
tcg_gen_shri_i32(tmp, tmp, 2);
tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
break;
case 15: /* LE (Z || (N ^ V)) */
tmp = tcg_temp_new();
assert(CCF_V == (CCF_N >> 2));
tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
tcg_gen_shri_i32(tmp, tmp, 2);
tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
break;
default:
/* Should ever happen. */
abort();
}
}
DISAS_INSN(scc)
{
int l1;
int cond;
TCGv reg;
l1 = gen_new_label();
cond = (insn >> 8) & 0xf;
reg = DREG(insn, 0);
tcg_gen_andi_i32(reg, reg, 0xffffff00);
/* This is safe because we modify the reg directly, with no other values
live. */
gen_jmpcc(s, cond ^ 1, l1);
tcg_gen_ori_i32(reg, reg, 0xff);
gen_set_label(l1);
}
/* Force a TB lookup after an instruction that changes the CPU state. */
static void gen_lookup_tb(DisasContext *s)
{
gen_flush_cc_op(s);
tcg_gen_movi_i32(QREG_PC, s->pc);
s->is_jmp = DISAS_UPDATE;
}
/* Generate a jump to an immediate address. */
static void gen_jmp_im(DisasContext *s, uint32_t dest)
{
gen_flush_cc_op(s);
tcg_gen_movi_i32(QREG_PC, dest);
s->is_jmp = DISAS_JUMP;
}
/* Generate a jump to the address in qreg DEST. */
static void gen_jmp(DisasContext *s, TCGv dest)
{
gen_flush_cc_op(s);
tcg_gen_mov_i32(QREG_PC, dest);
s->is_jmp = DISAS_JUMP;
}
static void gen_exception(DisasContext *s, uint32_t where, int nr)
{
gen_flush_cc_op(s);
gen_jmp_im(s, where);
gen_helper_raise_exception(tcg_const_i32(nr));
}
static inline void gen_addr_fault(DisasContext *s)
{
gen_exception(s, s->insn_pc, EXCP_ADDRESS);
}
#define SRC_EA(result, opsize, op_sign, addrp) do { \
result = gen_ea(s, insn, opsize, NULL_QREG, addrp, op_sign ? EA_LOADS : EA_LOADU); \
if (IS_NULL_QREG(result)) { \
gen_addr_fault(s); \
return; \
} \
} while (0)
#define DEST_EA(insn, opsize, val, addrp) do { \
TCGv ea_result = gen_ea(s, insn, opsize, val, addrp, EA_STORE); \
if (IS_NULL_QREG(ea_result)) { \
gen_addr_fault(s); \
return; \
} \
} while (0)
/* Generate a jump to an immediate address. */
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
{
TranslationBlock *tb;
tb = s->tb;
if (unlikely(s->singlestep_enabled)) {
gen_exception(s, dest, EXCP_DEBUG);
} else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
(s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(QREG_PC, dest);
tcg_gen_exit_tb((long)tb + n);
} else {
gen_jmp_im(s, dest);
tcg_gen_exit_tb(0);
}
s->is_jmp = DISAS_TB_JUMP;
}
DISAS_INSN(undef_mac)
{
gen_exception(s, s->pc - 2, EXCP_LINEA);
}
DISAS_INSN(undef_fpu)
{
gen_exception(s, s->pc - 2, EXCP_LINEF);
}
DISAS_INSN(undef)
{
gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
insn, s->pc - 2);
}
DISAS_INSN(mulw)
{
TCGv reg;
TCGv tmp;
TCGv src;
int sign;
sign = (insn & 0x100) != 0;
reg = DREG(insn, 9);
tmp = tcg_temp_new();
if (sign)
tcg_gen_ext16s_i32(tmp, reg);
else
tcg_gen_ext16u_i32(tmp, reg);
SRC_EA(src, OS_WORD, sign, NULL);
tcg_gen_mul_i32(tmp, tmp, src);
tcg_gen_mov_i32(reg, tmp);
/* Unlike m68k, coldfire always clears the overflow bit. */
gen_logic_cc(s, tmp);
}
DISAS_INSN(divw)
{
TCGv reg;
TCGv tmp;
TCGv src;
int sign;
sign = (insn & 0x100) != 0;
reg = DREG(insn, 9);
if (sign) {
tcg_gen_ext16s_i32(QREG_DIV1, reg);
} else {
tcg_gen_ext16u_i32(QREG_DIV1, reg);
}
SRC_EA(src, OS_WORD, sign, NULL);
tcg_gen_mov_i32(QREG_DIV2, src);
if (sign) {
gen_helper_divs(cpu_env, tcg_const_i32(1));
} else {
gen_helper_divu(cpu_env, tcg_const_i32(1));
}
tmp = tcg_temp_new();
src = tcg_temp_new();
tcg_gen_ext16u_i32(tmp, QREG_DIV1);
tcg_gen_shli_i32(src, QREG_DIV2, 16);
tcg_gen_or_i32(reg, tmp, src);
s->cc_op = CC_OP_FLAGS;
}
DISAS_INSN(divl)
{
TCGv num;
TCGv den;
TCGv reg;
uint16_t ext;
ext = lduw_code(s->pc);
s->pc += 2;
if (ext & 0x87f8) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
return;
}
num = DREG(ext, 12);
reg = DREG(ext, 0);
tcg_gen_mov_i32(QREG_DIV1, num);
SRC_EA(den, OS_LONG, 0, NULL);
tcg_gen_mov_i32(QREG_DIV2, den);
if (ext & 0x0800) {
gen_helper_divs(cpu_env, tcg_const_i32(0));
} else {
gen_helper_divu(cpu_env, tcg_const_i32(0));
}
if ((ext & 7) == ((ext >> 12) & 7)) {
/* div */
tcg_gen_mov_i32 (reg, QREG_DIV1);
} else {
/* rem */
tcg_gen_mov_i32 (reg, QREG_DIV2);
}
s->cc_op = CC_OP_FLAGS;
}
DISAS_INSN(addsub)
{
TCGv reg;
TCGv dest;
TCGv src;
TCGv tmp;
TCGv addr;
int add;
add = (insn & 0x4000) != 0;
reg = DREG(insn, 9);
dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(tmp, OS_LONG, 0, &addr);
src = reg;
} else {
tmp = reg;
SRC_EA(src, OS_LONG, 0, NULL);
}
if (add) {
tcg_gen_add_i32(dest, tmp, src);
gen_helper_xflag_lt(QREG_CC_X, dest, src);
s->cc_op = CC_OP_ADD;
} else {
gen_helper_xflag_lt(QREG_CC_X, tmp, src);
tcg_gen_sub_i32(dest, tmp, src);
s->cc_op = CC_OP_SUB;