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translate-i386.c
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/*
* i386 translation
*
* Copyright (c) 2003 Fabrice Bellard
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <assert.h>
#define DEBUG_DISAS
#define IN_OP_I386
#include "cpu-i386.h"
/* dump all code */
#ifdef DEBUG_DISAS
#include "dis-asm.h"
#endif
static uint8_t *gen_code_ptr;
int __op_param1, __op_param2, __op_param3;
extern FILE *logfile;
extern int loglevel;
/* supress that */
static void error(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
fprintf(stderr, "\n");
vfprintf(stderr, fmt, ap);
fprintf(stderr, "\n");
va_end(ap);
exit(1);
}
#define PREFIX_REPZ 1
#define PREFIX_REPNZ 2
#define PREFIX_LOCK 4
#define PREFIX_CS 8
#define PREFIX_SS 0x10
#define PREFIX_DS 0x20
#define PREFIX_ES 0x40
#define PREFIX_FS 0x80
#define PREFIX_GS 0x100
#define PREFIX_DATA 0x200
#define PREFIX_ADR 0x400
#define PREFIX_FWAIT 0x800
typedef struct DisasContext {
/* current insn context */
int prefix;
int aflag, dflag;
uint8_t *pc; /* current pc */
int cc_op; /* current CC operation */
int f_st;
} DisasContext;
/* i386 arith/logic operations */
enum {
OP_ADDL,
OP_ORL,
OP_ADCL,
OP_SBBL,
OP_ANDL,
OP_SUBL,
OP_XORL,
OP_CMPL,
};
/* i386 shift ops */
enum {
OP_ROL,
OP_ROR,
OP_RCL,
OP_RCR,
OP_SHL,
OP_SHR,
OP_SHL1, /* undocumented */
OP_SAR = 7,
};
#include "op-i386.h"
/* operand size */
enum {
OT_BYTE = 0,
OT_WORD,
OT_LONG,
OT_QUAD,
};
enum {
/* I386 int registers */
OR_EAX, /* MUST be even numbered */
OR_ECX,
OR_EDX,
OR_EBX,
OR_ESP,
OR_EBP,
OR_ESI,
OR_EDI,
OR_TMP0, /* temporary operand register */
OR_TMP1,
OR_A0, /* temporary register used when doing address evaluation */
OR_ZERO, /* fixed zero register */
NB_OREGS,
};
typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
[OT_BYTE] = {
gen_op_movb_EAX_T0,
gen_op_movb_ECX_T0,
gen_op_movb_EDX_T0,
gen_op_movb_EBX_T0,
gen_op_movh_EAX_T0,
gen_op_movh_ECX_T0,
gen_op_movh_EDX_T0,
gen_op_movh_EBX_T0,
},
[OT_WORD] = {
gen_op_movw_EAX_T0,
gen_op_movw_ECX_T0,
gen_op_movw_EDX_T0,
gen_op_movw_EBX_T0,
gen_op_movw_ESP_T0,
gen_op_movw_EBP_T0,
gen_op_movw_ESI_T0,
gen_op_movw_EDI_T0,
},
[OT_LONG] = {
gen_op_movl_EAX_T0,
gen_op_movl_ECX_T0,
gen_op_movl_EDX_T0,
gen_op_movl_EBX_T0,
gen_op_movl_ESP_T0,
gen_op_movl_EBP_T0,
gen_op_movl_ESI_T0,
gen_op_movl_EDI_T0,
},
};
static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
[OT_BYTE] = {
gen_op_movb_EAX_T1,
gen_op_movb_ECX_T1,
gen_op_movb_EDX_T1,
gen_op_movb_EBX_T1,
gen_op_movh_EAX_T1,
gen_op_movh_ECX_T1,
gen_op_movh_EDX_T1,
gen_op_movh_EBX_T1,
},
[OT_WORD] = {
gen_op_movw_EAX_T1,
gen_op_movw_ECX_T1,
gen_op_movw_EDX_T1,
gen_op_movw_EBX_T1,
gen_op_movw_ESP_T1,
gen_op_movw_EBP_T1,
gen_op_movw_ESI_T1,
gen_op_movw_EDI_T1,
},
[OT_LONG] = {
gen_op_movl_EAX_T1,
gen_op_movl_ECX_T1,
gen_op_movl_EDX_T1,
gen_op_movl_EBX_T1,
gen_op_movl_ESP_T1,
gen_op_movl_EBP_T1,
gen_op_movl_ESI_T1,
gen_op_movl_EDI_T1,
},
};
static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
[0] = {
gen_op_movw_EAX_A0,
gen_op_movw_ECX_A0,
gen_op_movw_EDX_A0,
gen_op_movw_EBX_A0,
gen_op_movw_ESP_A0,
gen_op_movw_EBP_A0,
gen_op_movw_ESI_A0,
gen_op_movw_EDI_A0,
},
[1] = {
gen_op_movl_EAX_A0,
gen_op_movl_ECX_A0,
gen_op_movl_EDX_A0,
gen_op_movl_EBX_A0,
gen_op_movl_ESP_A0,
gen_op_movl_EBP_A0,
gen_op_movl_ESI_A0,
gen_op_movl_EDI_A0,
},
};
static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
{
[OT_BYTE] = {
{
gen_op_movl_T0_EAX,
gen_op_movl_T0_ECX,
gen_op_movl_T0_EDX,
gen_op_movl_T0_EBX,
gen_op_movh_T0_EAX,
gen_op_movh_T0_ECX,
gen_op_movh_T0_EDX,
gen_op_movh_T0_EBX,
},
{
gen_op_movl_T1_EAX,
gen_op_movl_T1_ECX,
gen_op_movl_T1_EDX,
gen_op_movl_T1_EBX,
gen_op_movh_T1_EAX,
gen_op_movh_T1_ECX,
gen_op_movh_T1_EDX,
gen_op_movh_T1_EBX,
},
},
[OT_WORD] = {
{
gen_op_movl_T0_EAX,
gen_op_movl_T0_ECX,
gen_op_movl_T0_EDX,
gen_op_movl_T0_EBX,
gen_op_movl_T0_ESP,
gen_op_movl_T0_EBP,
gen_op_movl_T0_ESI,
gen_op_movl_T0_EDI,
},
{
gen_op_movl_T1_EAX,
gen_op_movl_T1_ECX,
gen_op_movl_T1_EDX,
gen_op_movl_T1_EBX,
gen_op_movl_T1_ESP,
gen_op_movl_T1_EBP,
gen_op_movl_T1_ESI,
gen_op_movl_T1_EDI,
},
},
[OT_LONG] = {
{
gen_op_movl_T0_EAX,
gen_op_movl_T0_ECX,
gen_op_movl_T0_EDX,
gen_op_movl_T0_EBX,
gen_op_movl_T0_ESP,
gen_op_movl_T0_EBP,
gen_op_movl_T0_ESI,
gen_op_movl_T0_EDI,
},
{
gen_op_movl_T1_EAX,
gen_op_movl_T1_ECX,
gen_op_movl_T1_EDX,
gen_op_movl_T1_EBX,
gen_op_movl_T1_ESP,
gen_op_movl_T1_EBP,
gen_op_movl_T1_ESI,
gen_op_movl_T1_EDI,
},
},
};
static GenOpFunc *gen_op_movl_A0_reg[8] = {
gen_op_movl_A0_EAX,
gen_op_movl_A0_ECX,
gen_op_movl_A0_EDX,
gen_op_movl_A0_EBX,
gen_op_movl_A0_ESP,
gen_op_movl_A0_EBP,
gen_op_movl_A0_ESI,
gen_op_movl_A0_EDI,
};
static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
[0] = {
gen_op_addl_A0_EAX,
gen_op_addl_A0_ECX,
gen_op_addl_A0_EDX,
gen_op_addl_A0_EBX,
gen_op_addl_A0_ESP,
gen_op_addl_A0_EBP,
gen_op_addl_A0_ESI,
gen_op_addl_A0_EDI,
},
[1] = {
gen_op_addl_A0_EAX_s1,
gen_op_addl_A0_ECX_s1,
gen_op_addl_A0_EDX_s1,
gen_op_addl_A0_EBX_s1,
gen_op_addl_A0_ESP_s1,
gen_op_addl_A0_EBP_s1,
gen_op_addl_A0_ESI_s1,
gen_op_addl_A0_EDI_s1,
},
[2] = {
gen_op_addl_A0_EAX_s2,
gen_op_addl_A0_ECX_s2,
gen_op_addl_A0_EDX_s2,
gen_op_addl_A0_EBX_s2,
gen_op_addl_A0_ESP_s2,
gen_op_addl_A0_EBP_s2,
gen_op_addl_A0_ESI_s2,
gen_op_addl_A0_EDI_s2,
},
[3] = {
gen_op_addl_A0_EAX_s3,
gen_op_addl_A0_ECX_s3,
gen_op_addl_A0_EDX_s3,
gen_op_addl_A0_EBX_s3,
gen_op_addl_A0_ESP_s3,
gen_op_addl_A0_EBP_s3,
gen_op_addl_A0_ESI_s3,
gen_op_addl_A0_EDI_s3,
},
};
static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
gen_op_addl_T0_T1_cc,
gen_op_orl_T0_T1_cc,
NULL,
NULL,
gen_op_andl_T0_T1_cc,
gen_op_subl_T0_T1_cc,
gen_op_xorl_T0_T1_cc,
gen_op_cmpl_T0_T1_cc,
};
static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
[OT_BYTE] = {
gen_op_adcb_T0_T1_cc,
gen_op_sbbb_T0_T1_cc,
},
[OT_WORD] = {
gen_op_adcw_T0_T1_cc,
gen_op_sbbw_T0_T1_cc,
},
[OT_LONG] = {
gen_op_adcl_T0_T1_cc,
gen_op_sbbl_T0_T1_cc,
},
};
static const int cc_op_arithb[8] = {
CC_OP_ADDB,
CC_OP_LOGICB,
CC_OP_ADDB,
CC_OP_SUBB,
CC_OP_LOGICB,
CC_OP_SUBB,
CC_OP_LOGICB,
CC_OP_SUBB,
};
static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
[OT_BYTE] = {
gen_op_rolb_T0_T1_cc,
gen_op_rorb_T0_T1_cc,
gen_op_rclb_T0_T1_cc,
gen_op_rcrb_T0_T1_cc,
gen_op_shlb_T0_T1_cc,
gen_op_shrb_T0_T1_cc,
gen_op_shlb_T0_T1_cc,
gen_op_sarb_T0_T1_cc,
},
[OT_WORD] = {
gen_op_rolw_T0_T1_cc,
gen_op_rorw_T0_T1_cc,
gen_op_rclw_T0_T1_cc,
gen_op_rcrw_T0_T1_cc,
gen_op_shlw_T0_T1_cc,
gen_op_shrw_T0_T1_cc,
gen_op_shlw_T0_T1_cc,
gen_op_sarw_T0_T1_cc,
},
[OT_LONG] = {
gen_op_roll_T0_T1_cc,
gen_op_rorl_T0_T1_cc,
gen_op_rcll_T0_T1_cc,
gen_op_rcrl_T0_T1_cc,
gen_op_shll_T0_T1_cc,
gen_op_shrl_T0_T1_cc,
gen_op_shll_T0_T1_cc,
gen_op_sarl_T0_T1_cc,
},
};
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
[0] = {
gen_op_shldw_T0_T1_im_cc,
gen_op_shrdw_T0_T1_im_cc,
},
[1] = {
gen_op_shldl_T0_T1_im_cc,
gen_op_shrdl_T0_T1_im_cc,
},
};
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
[0] = {
gen_op_shldw_T0_T1_ECX_cc,
gen_op_shrdw_T0_T1_ECX_cc,
},
[1] = {
gen_op_shldl_T0_T1_ECX_cc,
gen_op_shrdl_T0_T1_ECX_cc,
},
};
static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
[0] = {
gen_op_btw_T0_T1_cc,
gen_op_btsw_T0_T1_cc,
gen_op_btrw_T0_T1_cc,
gen_op_btcw_T0_T1_cc,
},
[1] = {
gen_op_btl_T0_T1_cc,
gen_op_btsl_T0_T1_cc,
gen_op_btrl_T0_T1_cc,
gen_op_btcl_T0_T1_cc,
},
};
static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
[0] = {
gen_op_bsfw_T0_cc,
gen_op_bsrw_T0_cc,
},
[1] = {
gen_op_bsfl_T0_cc,
gen_op_bsrl_T0_cc,
},
};
static GenOpFunc *gen_op_lds_T0_A0[3] = {
gen_op_ldsb_T0_A0,
gen_op_ldsw_T0_A0,
};
static GenOpFunc *gen_op_ldu_T0_A0[3] = {
gen_op_ldub_T0_A0,
gen_op_lduw_T0_A0,
};
/* sign does not matter */
static GenOpFunc *gen_op_ld_T0_A0[3] = {
gen_op_ldub_T0_A0,
gen_op_lduw_T0_A0,
gen_op_ldl_T0_A0,
};
static GenOpFunc *gen_op_ld_T1_A0[3] = {
gen_op_ldub_T1_A0,
gen_op_lduw_T1_A0,
gen_op_ldl_T1_A0,
};
static GenOpFunc *gen_op_st_T0_A0[3] = {
gen_op_stb_T0_A0,
gen_op_stw_T0_A0,
gen_op_stl_T0_A0,
};
static GenOpFunc *gen_op_movs[6] = {
gen_op_movsb,
gen_op_movsw,
gen_op_movsl,
gen_op_rep_movsb,
gen_op_rep_movsw,
gen_op_rep_movsl,
};
static GenOpFunc *gen_op_stos[6] = {
gen_op_stosb,
gen_op_stosw,
gen_op_stosl,
gen_op_rep_stosb,
gen_op_rep_stosw,
gen_op_rep_stosl,
};
static GenOpFunc *gen_op_lods[6] = {
gen_op_lodsb,
gen_op_lodsw,
gen_op_lodsl,
gen_op_rep_lodsb,
gen_op_rep_lodsw,
gen_op_rep_lodsl,
};
static GenOpFunc *gen_op_scas[9] = {
gen_op_scasb,
gen_op_scasw,
gen_op_scasl,
gen_op_repz_scasb,
gen_op_repz_scasw,
gen_op_repz_scasl,
gen_op_repnz_scasb,
gen_op_repnz_scasw,
gen_op_repnz_scasl,
};
static GenOpFunc *gen_op_cmps[9] = {
gen_op_cmpsb,
gen_op_cmpsw,
gen_op_cmpsl,
gen_op_repz_cmpsb,
gen_op_repz_cmpsw,
gen_op_repz_cmpsl,
gen_op_repnz_cmpsb,
gen_op_repnz_cmpsw,
gen_op_repnz_cmpsl,
};
static GenOpFunc *gen_op_ins[6] = {
gen_op_insb,
gen_op_insw,
gen_op_insl,
gen_op_rep_insb,
gen_op_rep_insw,
gen_op_rep_insl,
};
static GenOpFunc *gen_op_outs[6] = {
gen_op_outsb,
gen_op_outsw,
gen_op_outsl,
gen_op_rep_outsb,
gen_op_rep_outsw,
gen_op_rep_outsl,
};
static GenOpFunc *gen_op_in[3] = {
gen_op_inb_T0_T1,
gen_op_inw_T0_T1,
gen_op_inl_T0_T1,
};
static GenOpFunc *gen_op_out[3] = {
gen_op_outb_T0_T1,
gen_op_outw_T0_T1,
gen_op_outl_T0_T1,
};
enum {
JCC_O,
JCC_B,
JCC_Z,
JCC_BE,
JCC_S,
JCC_P,
JCC_L,
JCC_LE,
};
static GenOpFunc2 *gen_jcc_slow[8] = {
gen_op_jo_cc,
gen_op_jb_cc,
gen_op_jz_cc,
gen_op_jbe_cc,
gen_op_js_cc,
gen_op_jp_cc,
gen_op_jl_cc,
gen_op_jle_cc,
};
static GenOpFunc2 *gen_jcc_sub[3][8] = {
[OT_BYTE] = {
NULL,
gen_op_jb_subb,
gen_op_jz_subb,
gen_op_jbe_subb,
gen_op_js_subb,
NULL,
gen_op_jl_subb,
gen_op_jle_subb,
},
[OT_WORD] = {
NULL,
gen_op_jb_subw,
gen_op_jz_subw,
gen_op_jbe_subw,
gen_op_js_subw,
NULL,
gen_op_jl_subw,
gen_op_jle_subw,
},
[OT_LONG] = {
NULL,
gen_op_jb_subl,
gen_op_jz_subl,
gen_op_jbe_subl,
gen_op_js_subl,
NULL,
gen_op_jl_subl,
gen_op_jle_subl,
},
};
static GenOpFunc *gen_setcc_slow[8] = {
gen_op_seto_T0_cc,
gen_op_setb_T0_cc,
gen_op_setz_T0_cc,
gen_op_setbe_T0_cc,
gen_op_sets_T0_cc,
gen_op_setp_T0_cc,
gen_op_setl_T0_cc,
gen_op_setle_T0_cc,
};
static GenOpFunc *gen_setcc_sub[3][8] = {
[OT_BYTE] = {
NULL,
gen_op_setb_T0_subb,
gen_op_setz_T0_subb,
gen_op_setbe_T0_subb,
gen_op_sets_T0_subb,
NULL,
gen_op_setl_T0_subb,
gen_op_setle_T0_subb,
},
[OT_WORD] = {
NULL,
gen_op_setb_T0_subw,
gen_op_setz_T0_subw,
gen_op_setbe_T0_subw,
gen_op_sets_T0_subw,
NULL,
gen_op_setl_T0_subw,
gen_op_setle_T0_subw,
},
[OT_LONG] = {
NULL,
gen_op_setb_T0_subl,
gen_op_setz_T0_subl,
gen_op_setbe_T0_subl,
gen_op_sets_T0_subl,
NULL,
gen_op_setl_T0_subl,
gen_op_setle_T0_subl,
},
};
static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
gen_op_fadd_ST0_FT0,
gen_op_fmul_ST0_FT0,
gen_op_fcom_ST0_FT0,
gen_op_fcom_ST0_FT0,
gen_op_fsub_ST0_FT0,
gen_op_fsubr_ST0_FT0,
gen_op_fdiv_ST0_FT0,
gen_op_fdivr_ST0_FT0,
};
/* NOTE the exception in "r" op ordering */
static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
gen_op_fadd_STN_ST0,
gen_op_fmul_STN_ST0,
NULL,
NULL,
gen_op_fsubr_STN_ST0,
gen_op_fsub_STN_ST0,
gen_op_fdivr_STN_ST0,
gen_op_fdiv_STN_ST0,
};
static void gen_op(DisasContext *s1, int op, int ot, int d, int s)
{
if (d != OR_TMP0)
gen_op_mov_TN_reg[ot][0][d]();
if (s != OR_TMP1)
gen_op_mov_TN_reg[ot][1][s]();
if (op == OP_ADCL || op == OP_SBBL) {
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
s1->cc_op = CC_OP_DYNAMIC;
} else {
gen_op_arith_T0_T1_cc[op]();
s1->cc_op = cc_op_arithb[op] + ot;
}
if (d != OR_TMP0 && op != OP_CMPL)
gen_op_mov_reg_T0[ot][d]();
}
static void gen_opi(DisasContext *s1, int op, int ot, int d, int c)
{
gen_op_movl_T1_im(c);
gen_op(s1, op, ot, d, OR_TMP1);
}
static void gen_inc(DisasContext *s1, int ot, int d, int c)
{
if (d != OR_TMP0)
gen_op_mov_TN_reg[ot][0][d]();
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
if (c > 0) {
gen_op_incl_T0_cc();
s1->cc_op = CC_OP_INCB + ot;
} else {
gen_op_decl_T0_cc();
s1->cc_op = CC_OP_DECB + ot;
}
if (d != OR_TMP0)
gen_op_mov_reg_T0[ot][d]();
}
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
{
if (d != OR_TMP0)
gen_op_mov_TN_reg[ot][0][d]();
if (s != OR_TMP1)
gen_op_mov_TN_reg[ot][1][s]();
/* for zero counts, flags are not updated, so must do it dynamically */
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
gen_op_shift_T0_T1_cc[ot][op]();
if (d != OR_TMP0)
gen_op_mov_reg_T0[ot][d]();
s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
}
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
{
/* currently not optimized */
gen_op_movl_T1_im(c);
gen_shift(s1, op, ot, d, OR_TMP1);
}
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
{
int havesib;
int havebase;
int base, disp;
int index = 0;
int scale = 0;
int reg1, reg2, opreg;
int mod, rm, code;
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (s->aflag) {
havesib = 0;
havebase = 1;
base = rm;
if (base == 4) {
havesib = 1;
code = ldub(s->pc++);
scale = (code >> 6) & 3;
index = (code >> 3) & 7;
base = code & 7;
}
switch (mod) {
case 0:
if (base == 5) {
havebase = 0;
disp = ldl(s->pc);
s->pc += 4;
} else {
disp = 0;
}
break;
case 1:
disp = (int8_t)ldub(s->pc++);
break;
default:
case 2:
disp = ldl(s->pc);
s->pc += 4;
break;
}
reg1 = OR_ZERO;
reg2 = OR_ZERO;
if (havebase || (havesib && (index != 4 || scale != 0))) {
if (havebase)
reg1 = OR_EAX + base;
if (havesib && index != 4) {
if (havebase)
reg2 = index + OR_EAX;
else
reg1 = index + OR_EAX;
}
}
/* XXX: disp only ? */
if (reg2 == OR_ZERO) {
/* op: disp + (reg1 << scale) */
if (reg1 == OR_ZERO) {
gen_op_movl_A0_im(disp);
} else if (scale == 0 && disp == 0) {
gen_op_movl_A0_reg[reg1]();
} else {
gen_op_movl_A0_im(disp);
gen_op_addl_A0_reg_sN[scale][reg1]();
}
} else {
/* op: disp + reg1 + (reg2 << scale) */
if (disp != 0) {
gen_op_movl_A0_im(disp);
gen_op_addl_A0_reg_sN[0][reg1]();
} else {
gen_op_movl_A0_reg[reg1]();
}
gen_op_addl_A0_reg_sN[scale][reg2]();
}
} else {
switch (mod) {
case 0:
if (rm == 6) {
disp = lduw(s->pc);
s->pc += 2;
gen_op_movl_A0_im(disp);
goto no_rm;
} else {
disp = 0;
}
break;
case 1:
disp = (int8_t)ldub(s->pc++);
break;
default:
case 2:
disp = lduw(s->pc);
s->pc += 2;
break;
}
switch(rm) {
case 0:
gen_op_movl_A0_reg[R_EBX]();
gen_op_addl_A0_reg_sN[0][R_ESI]();
break;
case 1:
gen_op_movl_A0_reg[R_EBX]();
gen_op_addl_A0_reg_sN[0][R_EDI]();
break;
case 2:
gen_op_movl_A0_reg[R_EBP]();
gen_op_addl_A0_reg_sN[0][R_ESI]();
break;
case 3:
gen_op_movl_A0_reg[R_EBP]();
gen_op_addl_A0_reg_sN[0][R_EDI]();
break;
case 4:
gen_op_movl_A0_reg[R_ESI]();
break;
case 5:
gen_op_movl_A0_reg[R_EDI]();
break;
case 6:
gen_op_movl_A0_reg[R_EBP]();
break;
default:
case 7:
gen_op_movl_A0_reg[R_EBX]();
break;
}
if (disp != 0)
gen_op_addl_A0_im(disp);
gen_op_andl_A0_ffff();
no_rm: ;
}
opreg = OR_A0;
disp = 0;
*reg_ptr = opreg;
*offset_ptr = disp;
}
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
OR_TMP0 */
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
{
int mod, rm, opreg, disp;
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg[ot][0][reg]();
gen_op_mov_reg_T0[ot][rm]();
} else {
gen_op_mov_TN_reg[ot][0][rm]();
if (reg != OR_TMP0)
gen_op_mov_reg_T0[ot][reg]();
}
} else {
gen_lea_modrm(s, modrm, &opreg, &disp);
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg[ot][0][reg]();
gen_op_st_T0_A0[ot]();
} else {
gen_op_ld_T0_A0[ot]();
if (reg != OR_TMP0)
gen_op_mov_reg_T0[ot][reg]();
}
}
}
static inline uint32_t insn_get(DisasContext *s, int ot)
{
uint32_t ret;
switch(ot) {
case OT_BYTE:
ret = ldub(s->pc);
s->pc++;
break;
case OT_WORD:
ret = lduw(s->pc);
s->pc += 2;
break;
default:
case OT_LONG:
ret = ldl(s->pc);
s->pc += 4;
break;
}
return ret;
}
static void gen_jcc(DisasContext *s, int b, int val)
{
int inv, jcc_op;
GenOpFunc2 *func;
inv = b & 1;
jcc_op = (b >> 1) & 7;
switch(s->cc_op) {
/* we optimize the cmp/jcc case */
case CC_OP_SUBB:
case CC_OP_SUBW:
case CC_OP_SUBL:
func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
if (!func)
goto slow_jcc;
break;
/* some jumps are easy to compute */
case CC_OP_ADDB:
case CC_OP_ADDW:
case CC_OP_ADDL:
case CC_OP_ADCB:
case CC_OP_ADCW:
case CC_OP_ADCL:
case CC_OP_SBBB:
case CC_OP_SBBW:
case CC_OP_SBBL:
case CC_OP_LOGICB:
case CC_OP_LOGICW:
case CC_OP_LOGICL:
case CC_OP_INCB:
case CC_OP_INCW:
case CC_OP_INCL:
case CC_OP_DECB:
case CC_OP_DECW:
case CC_OP_DECL:
case CC_OP_SHLB:
case CC_OP_SHLW:
case CC_OP_SHLL:
case CC_OP_SARB: