forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathtxx9dmac.c
1314 lines (1123 loc) · 33.8 KB
/
txx9dmac.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Driver for the TXx9 SoC DMA Controller
*
* Copyright (C) 2009 Atsushi Nemoto
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/scatterlist.h>
#include "dmaengine.h"
#include "txx9dmac.h"
static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
{
return container_of(chan, struct txx9dmac_chan, chan);
}
static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
{
return dc->ch_regs;
}
static struct txx9dmac_cregs32 __iomem *__dma_regs32(
const struct txx9dmac_chan *dc)
{
return dc->ch_regs;
}
#define channel64_readq(dc, name) \
__raw_readq(&(__dma_regs(dc)->name))
#define channel64_writeq(dc, name, val) \
__raw_writeq((val), &(__dma_regs(dc)->name))
#define channel64_readl(dc, name) \
__raw_readl(&(__dma_regs(dc)->name))
#define channel64_writel(dc, name, val) \
__raw_writel((val), &(__dma_regs(dc)->name))
#define channel32_readl(dc, name) \
__raw_readl(&(__dma_regs32(dc)->name))
#define channel32_writel(dc, name, val) \
__raw_writel((val), &(__dma_regs32(dc)->name))
#define channel_readq(dc, name) channel64_readq(dc, name)
#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
#define channel_readl(dc, name) \
(is_dmac64(dc) ? \
channel64_readl(dc, name) : channel32_readl(dc, name))
#define channel_writel(dc, name, val) \
(is_dmac64(dc) ? \
channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
{
if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
return channel64_readq(dc, CHAR);
else
return channel64_readl(dc, CHAR);
}
static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
{
if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
channel64_writeq(dc, CHAR, val);
else
channel64_writel(dc, CHAR, val);
}
static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
{
#if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
channel64_writel(dc, CHAR, 0);
channel64_writel(dc, __pad_CHAR, 0);
#else
channel64_writeq(dc, CHAR, 0);
#endif
}
static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
{
if (is_dmac64(dc))
return channel64_read_CHAR(dc);
else
return channel32_readl(dc, CHAR);
}
static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
{
if (is_dmac64(dc))
channel64_write_CHAR(dc, val);
else
channel32_writel(dc, CHAR, val);
}
static struct txx9dmac_regs __iomem *__txx9dmac_regs(
const struct txx9dmac_dev *ddev)
{
return ddev->regs;
}
static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
const struct txx9dmac_dev *ddev)
{
return ddev->regs;
}
#define dma64_readl(ddev, name) \
__raw_readl(&(__txx9dmac_regs(ddev)->name))
#define dma64_writel(ddev, name, val) \
__raw_writel((val), &(__txx9dmac_regs(ddev)->name))
#define dma32_readl(ddev, name) \
__raw_readl(&(__txx9dmac_regs32(ddev)->name))
#define dma32_writel(ddev, name, val) \
__raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
#define dma_readl(ddev, name) \
(__is_dmac64(ddev) ? \
dma64_readl(ddev, name) : dma32_readl(ddev, name))
#define dma_writel(ddev, name, val) \
(__is_dmac64(ddev) ? \
dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
static struct device *chan2dev(struct dma_chan *chan)
{
return &chan->dev->device;
}
static struct device *chan2parent(struct dma_chan *chan)
{
return chan->dev->device.parent;
}
static struct txx9dmac_desc *
txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
{
return container_of(txd, struct txx9dmac_desc, txd);
}
static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
const struct txx9dmac_desc *desc)
{
return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
}
static void desc_write_CHAR(const struct txx9dmac_chan *dc,
struct txx9dmac_desc *desc, dma_addr_t val)
{
if (is_dmac64(dc))
desc->hwdesc.CHAR = val;
else
desc->hwdesc32.CHAR = val;
}
#define TXX9_DMA_MAX_COUNT 0x04000000
#define TXX9_DMA_INITIAL_DESC_COUNT 64
static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
{
return list_entry(dc->active_list.next,
struct txx9dmac_desc, desc_node);
}
static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
{
return list_entry(dc->active_list.prev,
struct txx9dmac_desc, desc_node);
}
static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
{
return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
}
static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
{
if (!list_empty(&desc->tx_list))
desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
return desc;
}
static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
gfp_t flags)
{
struct txx9dmac_dev *ddev = dc->ddev;
struct txx9dmac_desc *desc;
desc = kzalloc(sizeof(*desc), flags);
if (!desc)
return NULL;
INIT_LIST_HEAD(&desc->tx_list);
dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
desc->txd.tx_submit = txx9dmac_tx_submit;
/* txd.flags will be overwritten in prep funcs */
desc->txd.flags = DMA_CTRL_ACK;
desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
ddev->descsize, DMA_TO_DEVICE);
return desc;
}
static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
{
struct txx9dmac_desc *desc, *_desc;
struct txx9dmac_desc *ret = NULL;
unsigned int i = 0;
spin_lock_bh(&dc->lock);
list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
if (async_tx_test_ack(&desc->txd)) {
list_del(&desc->desc_node);
ret = desc;
break;
}
dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
i++;
}
spin_unlock_bh(&dc->lock);
dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
i);
if (!ret) {
ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
if (ret) {
spin_lock_bh(&dc->lock);
dc->descs_allocated++;
spin_unlock_bh(&dc->lock);
} else
dev_err(chan2dev(&dc->chan),
"not enough descriptors available\n");
}
return ret;
}
static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
struct txx9dmac_desc *desc)
{
struct txx9dmac_dev *ddev = dc->ddev;
struct txx9dmac_desc *child;
list_for_each_entry(child, &desc->tx_list, desc_node)
dma_sync_single_for_cpu(chan2parent(&dc->chan),
child->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
dma_sync_single_for_cpu(chan2parent(&dc->chan),
desc->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
}
/*
* Move a descriptor, including any children, to the free list.
* `desc' must not be on any lists.
*/
static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
struct txx9dmac_desc *desc)
{
if (desc) {
struct txx9dmac_desc *child;
txx9dmac_sync_desc_for_cpu(dc, desc);
spin_lock_bh(&dc->lock);
list_for_each_entry(child, &desc->tx_list, desc_node)
dev_vdbg(chan2dev(&dc->chan),
"moving child desc %p to freelist\n",
child);
list_splice_init(&desc->tx_list, &dc->free_list);
dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
desc);
list_add(&desc->desc_node, &dc->free_list);
spin_unlock_bh(&dc->lock);
}
}
/*----------------------------------------------------------------------*/
static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
{
if (is_dmac64(dc))
dev_err(chan2dev(&dc->chan),
" CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
" SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
(u64)channel64_read_CHAR(dc),
channel64_readq(dc, SAR),
channel64_readq(dc, DAR),
channel64_readl(dc, CNTR),
channel64_readl(dc, SAIR),
channel64_readl(dc, DAIR),
channel64_readl(dc, CCR),
channel64_readl(dc, CSR));
else
dev_err(chan2dev(&dc->chan),
" CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
" SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
channel32_readl(dc, CHAR),
channel32_readl(dc, SAR),
channel32_readl(dc, DAR),
channel32_readl(dc, CNTR),
channel32_readl(dc, SAIR),
channel32_readl(dc, DAIR),
channel32_readl(dc, CCR),
channel32_readl(dc, CSR));
}
static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
{
channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
if (is_dmac64(dc)) {
channel64_clear_CHAR(dc);
channel_writeq(dc, SAR, 0);
channel_writeq(dc, DAR, 0);
} else {
channel_writel(dc, CHAR, 0);
channel_writel(dc, SAR, 0);
channel_writel(dc, DAR, 0);
}
channel_writel(dc, CNTR, 0);
channel_writel(dc, SAIR, 0);
channel_writel(dc, DAIR, 0);
channel_writel(dc, CCR, 0);
mmiowb();
}
/* Called with dc->lock held and bh disabled */
static void txx9dmac_dostart(struct txx9dmac_chan *dc,
struct txx9dmac_desc *first)
{
struct txx9dmac_slave *ds = dc->chan.private;
u32 sai, dai;
dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
first->txd.cookie, first);
/* ASSERT: channel is idle */
if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
dev_err(chan2dev(&dc->chan),
"BUG: Attempted to start non-idle channel\n");
txx9dmac_dump_regs(dc);
/* The tasklet will hopefully advance the queue... */
return;
}
if (is_dmac64(dc)) {
channel64_writel(dc, CNTR, 0);
channel64_writel(dc, CSR, 0xffffffff);
if (ds) {
if (ds->tx_reg) {
sai = ds->reg_width;
dai = 0;
} else {
sai = 0;
dai = ds->reg_width;
}
} else {
sai = 8;
dai = 8;
}
channel64_writel(dc, SAIR, sai);
channel64_writel(dc, DAIR, dai);
/* All 64-bit DMAC supports SMPCHN */
channel64_writel(dc, CCR, dc->ccr);
/* Writing a non zero value to CHAR will assert XFACT */
channel64_write_CHAR(dc, first->txd.phys);
} else {
channel32_writel(dc, CNTR, 0);
channel32_writel(dc, CSR, 0xffffffff);
if (ds) {
if (ds->tx_reg) {
sai = ds->reg_width;
dai = 0;
} else {
sai = 0;
dai = ds->reg_width;
}
} else {
sai = 4;
dai = 4;
}
channel32_writel(dc, SAIR, sai);
channel32_writel(dc, DAIR, dai);
if (txx9_dma_have_SMPCHN()) {
channel32_writel(dc, CCR, dc->ccr);
/* Writing a non zero value to CHAR will assert XFACT */
channel32_writel(dc, CHAR, first->txd.phys);
} else {
channel32_writel(dc, CHAR, first->txd.phys);
channel32_writel(dc, CCR, dc->ccr);
}
}
}
/*----------------------------------------------------------------------*/
static void
txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
struct txx9dmac_desc *desc)
{
dma_async_tx_callback callback;
void *param;
struct dma_async_tx_descriptor *txd = &desc->txd;
dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
txd->cookie, desc);
dma_cookie_complete(txd);
callback = txd->callback;
param = txd->callback_param;
txx9dmac_sync_desc_for_cpu(dc, desc);
list_splice_init(&desc->tx_list, &dc->free_list);
list_move(&desc->desc_node, &dc->free_list);
dma_descriptor_unmap(txd);
/*
* The API requires that no submissions are done from a
* callback, so we don't need to drop the lock here
*/
if (callback)
callback(param);
dma_run_dependencies(txd);
}
static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
{
struct txx9dmac_dev *ddev = dc->ddev;
struct txx9dmac_desc *desc;
struct txx9dmac_desc *prev = NULL;
BUG_ON(!list_empty(list));
do {
desc = txx9dmac_first_queued(dc);
if (prev) {
desc_write_CHAR(dc, prev, desc->txd.phys);
dma_sync_single_for_device(chan2parent(&dc->chan),
prev->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
}
prev = txx9dmac_last_child(desc);
list_move_tail(&desc->desc_node, list);
/* Make chain-completion interrupt happen */
if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
!txx9dmac_chan_INTENT(dc))
break;
} while (!list_empty(&dc->queue));
}
static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
{
struct txx9dmac_desc *desc, *_desc;
LIST_HEAD(list);
/*
* Submit queued descriptors ASAP, i.e. before we go through
* the completed ones.
*/
list_splice_init(&dc->active_list, &list);
if (!list_empty(&dc->queue)) {
txx9dmac_dequeue(dc, &dc->active_list);
txx9dmac_dostart(dc, txx9dmac_first_active(dc));
}
list_for_each_entry_safe(desc, _desc, &list, desc_node)
txx9dmac_descriptor_complete(dc, desc);
}
static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
struct txx9dmac_hwdesc *desc)
{
if (is_dmac64(dc)) {
#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
dev_crit(chan2dev(&dc->chan),
" desc: ch%#llx s%#llx d%#llx c%#x\n",
(u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
#else
dev_crit(chan2dev(&dc->chan),
" desc: ch%#llx s%#llx d%#llx c%#x"
" si%#x di%#x cc%#x cs%#x\n",
(u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
#endif
} else {
struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
dev_crit(chan2dev(&dc->chan),
" desc: ch%#x s%#x d%#x c%#x\n",
d->CHAR, d->SAR, d->DAR, d->CNTR);
#else
dev_crit(chan2dev(&dc->chan),
" desc: ch%#x s%#x d%#x c%#x"
" si%#x di%#x cc%#x cs%#x\n",
d->CHAR, d->SAR, d->DAR, d->CNTR,
d->SAIR, d->DAIR, d->CCR, d->CSR);
#endif
}
}
static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
{
struct txx9dmac_desc *bad_desc;
struct txx9dmac_desc *child;
u32 errors;
/*
* The descriptor currently at the head of the active list is
* borked. Since we don't have any way to report errors, we'll
* just have to scream loudly and try to carry on.
*/
dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
txx9dmac_dump_regs(dc);
bad_desc = txx9dmac_first_active(dc);
list_del_init(&bad_desc->desc_node);
/* Clear all error flags and try to restart the controller */
errors = csr & (TXX9_DMA_CSR_ABCHC |
TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
channel_writel(dc, CSR, errors);
if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
txx9dmac_dequeue(dc, &dc->active_list);
if (!list_empty(&dc->active_list))
txx9dmac_dostart(dc, txx9dmac_first_active(dc));
dev_crit(chan2dev(&dc->chan),
"Bad descriptor submitted for DMA! (cookie: %d)\n",
bad_desc->txd.cookie);
txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
list_for_each_entry(child, &bad_desc->tx_list, desc_node)
txx9dmac_dump_desc(dc, &child->hwdesc);
/* Pretend the descriptor completed successfully */
txx9dmac_descriptor_complete(dc, bad_desc);
}
static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
{
dma_addr_t chain;
struct txx9dmac_desc *desc, *_desc;
struct txx9dmac_desc *child;
u32 csr;
if (is_dmac64(dc)) {
chain = channel64_read_CHAR(dc);
csr = channel64_readl(dc, CSR);
channel64_writel(dc, CSR, csr);
} else {
chain = channel32_readl(dc, CHAR);
csr = channel32_readl(dc, CSR);
channel32_writel(dc, CSR, csr);
}
/* For dynamic chain, we should look at XFACT instead of NCHNC */
if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
/* Everything we've submitted is done */
txx9dmac_complete_all(dc);
return;
}
if (!(csr & TXX9_DMA_CSR_CHNEN))
chain = 0; /* last descriptor of this chain */
dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
(u64)chain);
list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
if (desc_read_CHAR(dc, desc) == chain) {
/* This one is currently in progress */
if (csr & TXX9_DMA_CSR_ABCHC)
goto scan_done;
return;
}
list_for_each_entry(child, &desc->tx_list, desc_node)
if (desc_read_CHAR(dc, child) == chain) {
/* Currently in progress */
if (csr & TXX9_DMA_CSR_ABCHC)
goto scan_done;
return;
}
/*
* No descriptors so far seem to be in progress, i.e.
* this one must be done.
*/
txx9dmac_descriptor_complete(dc, desc);
}
scan_done:
if (csr & TXX9_DMA_CSR_ABCHC) {
txx9dmac_handle_error(dc, csr);
return;
}
dev_err(chan2dev(&dc->chan),
"BUG: All descriptors done, but channel not idle!\n");
/* Try to continue after resetting the channel... */
txx9dmac_reset_chan(dc);
if (!list_empty(&dc->queue)) {
txx9dmac_dequeue(dc, &dc->active_list);
txx9dmac_dostart(dc, txx9dmac_first_active(dc));
}
}
static void txx9dmac_chan_tasklet(unsigned long data)
{
int irq;
u32 csr;
struct txx9dmac_chan *dc;
dc = (struct txx9dmac_chan *)data;
csr = channel_readl(dc, CSR);
dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
spin_lock(&dc->lock);
if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
TXX9_DMA_CSR_NTRNFC))
txx9dmac_scan_descriptors(dc);
spin_unlock(&dc->lock);
irq = dc->irq;
enable_irq(irq);
}
static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
{
struct txx9dmac_chan *dc = dev_id;
dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
channel_readl(dc, CSR));
tasklet_schedule(&dc->tasklet);
/*
* Just disable the interrupts. We'll turn them back on in the
* softirq handler.
*/
disable_irq_nosync(irq);
return IRQ_HANDLED;
}
static void txx9dmac_tasklet(unsigned long data)
{
int irq;
u32 csr;
struct txx9dmac_chan *dc;
struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
u32 mcr;
int i;
mcr = dma_readl(ddev, MCR);
dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
if ((mcr >> (24 + i)) & 0x11) {
dc = ddev->chan[i];
csr = channel_readl(dc, CSR);
dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
csr);
spin_lock(&dc->lock);
if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
TXX9_DMA_CSR_NTRNFC))
txx9dmac_scan_descriptors(dc);
spin_unlock(&dc->lock);
}
}
irq = ddev->irq;
enable_irq(irq);
}
static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
{
struct txx9dmac_dev *ddev = dev_id;
dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
dma_readl(ddev, MCR));
tasklet_schedule(&ddev->tasklet);
/*
* Just disable the interrupts. We'll turn them back on in the
* softirq handler.
*/
disable_irq_nosync(irq);
return IRQ_HANDLED;
}
/*----------------------------------------------------------------------*/
static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
dma_cookie_t cookie;
spin_lock_bh(&dc->lock);
cookie = dma_cookie_assign(tx);
dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
desc->txd.cookie, desc);
list_add_tail(&desc->desc_node, &dc->queue);
spin_unlock_bh(&dc->lock);
return cookie;
}
static struct dma_async_tx_descriptor *
txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
size_t len, unsigned long flags)
{
struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
struct txx9dmac_dev *ddev = dc->ddev;
struct txx9dmac_desc *desc;
struct txx9dmac_desc *first;
struct txx9dmac_desc *prev;
size_t xfer_count;
size_t offset;
dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
(u64)dest, (u64)src, len, flags);
if (unlikely(!len)) {
dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
return NULL;
}
prev = first = NULL;
for (offset = 0; offset < len; offset += xfer_count) {
xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
/*
* Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
* ERT-TX49H4-016 (slightly conservative)
*/
if (__is_dmac64(ddev)) {
if (xfer_count > 0x100 &&
(xfer_count & 0xff) >= 0xfa &&
(xfer_count & 0xff) <= 0xff)
xfer_count -= 0x20;
} else {
if (xfer_count > 0x80 &&
(xfer_count & 0x7f) >= 0x7e &&
(xfer_count & 0x7f) <= 0x7f)
xfer_count -= 0x20;
}
desc = txx9dmac_desc_get(dc);
if (!desc) {
txx9dmac_desc_put(dc, first);
return NULL;
}
if (__is_dmac64(ddev)) {
desc->hwdesc.SAR = src + offset;
desc->hwdesc.DAR = dest + offset;
desc->hwdesc.CNTR = xfer_count;
txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
dc->ccr | TXX9_DMA_CCR_XFACT);
} else {
desc->hwdesc32.SAR = src + offset;
desc->hwdesc32.DAR = dest + offset;
desc->hwdesc32.CNTR = xfer_count;
txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
dc->ccr | TXX9_DMA_CCR_XFACT);
}
/*
* The descriptors on tx_list are not reachable from
* the dc->queue list or dc->active_list after a
* submit. If we put all descriptors on active_list,
* calling of callback on the completion will be more
* complex.
*/
if (!first) {
first = desc;
} else {
desc_write_CHAR(dc, prev, desc->txd.phys);
dma_sync_single_for_device(chan2parent(&dc->chan),
prev->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
list_add_tail(&desc->desc_node, &first->tx_list);
}
prev = desc;
}
/* Trigger interrupt after last block */
if (flags & DMA_PREP_INTERRUPT)
txx9dmac_desc_set_INTENT(ddev, prev);
desc_write_CHAR(dc, prev, 0);
dma_sync_single_for_device(chan2parent(&dc->chan),
prev->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
first->txd.flags = flags;
first->len = len;
return &first->txd;
}
static struct dma_async_tx_descriptor *
txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
unsigned int sg_len, enum dma_transfer_direction direction,
unsigned long flags, void *context)
{
struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
struct txx9dmac_dev *ddev = dc->ddev;
struct txx9dmac_slave *ds = chan->private;
struct txx9dmac_desc *prev;
struct txx9dmac_desc *first;
unsigned int i;
struct scatterlist *sg;
dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
BUG_ON(!ds || !ds->reg_width);
if (ds->tx_reg)
BUG_ON(direction != DMA_MEM_TO_DEV);
else
BUG_ON(direction != DMA_DEV_TO_MEM);
if (unlikely(!sg_len))
return NULL;
prev = first = NULL;
for_each_sg(sgl, sg, sg_len, i) {
struct txx9dmac_desc *desc;
dma_addr_t mem;
u32 sai, dai;
desc = txx9dmac_desc_get(dc);
if (!desc) {
txx9dmac_desc_put(dc, first);
return NULL;
}
mem = sg_dma_address(sg);
if (__is_dmac64(ddev)) {
if (direction == DMA_MEM_TO_DEV) {
desc->hwdesc.SAR = mem;
desc->hwdesc.DAR = ds->tx_reg;
} else {
desc->hwdesc.SAR = ds->rx_reg;
desc->hwdesc.DAR = mem;
}
desc->hwdesc.CNTR = sg_dma_len(sg);
} else {
if (direction == DMA_MEM_TO_DEV) {
desc->hwdesc32.SAR = mem;
desc->hwdesc32.DAR = ds->tx_reg;
} else {
desc->hwdesc32.SAR = ds->rx_reg;
desc->hwdesc32.DAR = mem;
}
desc->hwdesc32.CNTR = sg_dma_len(sg);
}
if (direction == DMA_MEM_TO_DEV) {
sai = ds->reg_width;
dai = 0;
} else {
sai = 0;
dai = ds->reg_width;
}
txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
dc->ccr | TXX9_DMA_CCR_XFACT);
if (!first) {
first = desc;
} else {
desc_write_CHAR(dc, prev, desc->txd.phys);
dma_sync_single_for_device(chan2parent(&dc->chan),
prev->txd.phys,
ddev->descsize,
DMA_TO_DEVICE);
list_add_tail(&desc->desc_node, &first->tx_list);
}
prev = desc;
}
/* Trigger interrupt after last block */
if (flags & DMA_PREP_INTERRUPT)
txx9dmac_desc_set_INTENT(ddev, prev);
desc_write_CHAR(dc, prev, 0);
dma_sync_single_for_device(chan2parent(&dc->chan),
prev->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
first->txd.flags = flags;
first->len = 0;
return &first->txd;
}
static int txx9dmac_terminate_all(struct dma_chan *chan)
{
struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
struct txx9dmac_desc *desc, *_desc;
LIST_HEAD(list);
dev_vdbg(chan2dev(chan), "terminate_all\n");
spin_lock_bh(&dc->lock);
txx9dmac_reset_chan(dc);
/* active_list entries will end up before queued entries */
list_splice_init(&dc->queue, &list);
list_splice_init(&dc->active_list, &list);
spin_unlock_bh(&dc->lock);
/* Flush all pending and queued descriptors */
list_for_each_entry_safe(desc, _desc, &list, desc_node)
txx9dmac_descriptor_complete(dc, desc);
return 0;
}
static enum dma_status
txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
enum dma_status ret;
ret = dma_cookie_status(chan, cookie, txstate);
if (ret == DMA_COMPLETE)
return DMA_COMPLETE;
spin_lock_bh(&dc->lock);
txx9dmac_scan_descriptors(dc);
spin_unlock_bh(&dc->lock);
return dma_cookie_status(chan, cookie, txstate);
}
static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
struct txx9dmac_desc *prev)
{
struct txx9dmac_dev *ddev = dc->ddev;
struct txx9dmac_desc *desc;
LIST_HEAD(list);
prev = txx9dmac_last_child(prev);
txx9dmac_dequeue(dc, &list);
desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
desc_write_CHAR(dc, prev, desc->txd.phys);
dma_sync_single_for_device(chan2parent(&dc->chan),
prev->txd.phys, ddev->descsize,
DMA_TO_DEVICE);
mmiowb();
if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
channel_read_CHAR(dc) == prev->txd.phys)
/* Restart chain DMA */
channel_write_CHAR(dc, desc->txd.phys);
list_splice_tail(&list, &dc->active_list);
}
static void txx9dmac_issue_pending(struct dma_chan *chan)
{
struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
spin_lock_bh(&dc->lock);
if (!list_empty(&dc->active_list))
txx9dmac_scan_descriptors(dc);
if (!list_empty(&dc->queue)) {
if (list_empty(&dc->active_list)) {
txx9dmac_dequeue(dc, &dc->active_list);
txx9dmac_dostart(dc, txx9dmac_first_active(dc));
} else if (txx9_dma_have_SMPCHN()) {
struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
txx9dmac_chan_INTENT(dc))
txx9dmac_chain_dynamic(dc, prev);
}
}
spin_unlock_bh(&dc->lock);
}
static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
{
struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
struct txx9dmac_slave *ds = chan->private;
struct txx9dmac_desc *desc;
int i;
dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");