@@ -36,7 +36,7 @@ asm volatile( \
3636" cp %A[len], r1 ; check len > 0, return immediately if it is\n" \
3737" cpc %B[len], r1\n" \
3838" brne 1f\n" \
39- " rjmp 16f \n" \
39+ " rjmp 18f \n" \
4040"1: ld r18, Z+ ; load in first red byte to be output\n" \
4141" ld r19, Z+ ; load in first green byte to be output\n" \
4242" ld r20, Z+ ; load in first blue byte to be output\n" \
@@ -50,7 +50,7 @@ asm volatile( \
5050" cbi %[port], %[pin] ; false, pin hi -> lo\n" \
5151"3: sbrc r19, 7 ; equalise delay of both code paths\n" \
5252" rjmp 4f\n" \
53- "4: nop ; pulse timing delay \n" \
53+ "4: nop\n" \
5454" nop\n" \
5555" nop\n" \
5656" nop\n" \
@@ -68,7 +68,7 @@ asm volatile( \
6868" cbi %[port], %[pin] ; false, pin hi -> lo\n" \
6969"6: sbrc r18, 7 ; equalise delay of both code paths\n" \
7070" rjmp 7f\n" \
71- "7: nop ; pulse timing delay \n" \
71+ "7: nop\n" \
7272" nop\n" \
7373" nop\n" \
7474" nop\n" \
@@ -79,30 +79,31 @@ asm volatile( \
7979" cbi %[port], %[pin] ; pin hi -> lo\n" \
8080" brne 5b ; inner loop, if required\n" \
8181" nop ; equalise delay of both code paths\n" \
82- /* red, 8th bit - output & fetch next values */ \
82+ /* red, 8th bit - output & check for end of outer loop */ \
8383" sbi %[port], %[pin] ; pin lo -> hi\n" \
8484" sbrc r18, 7 ; test hi bit clear\n" \
8585" rjmp 8f ; true, skip pin hi -> lo\n" \
8686" cbi %[port], %[pin] ; false, pin hi -> lo\n" \
8787"8: sbrc r18, 7 ; equalise delay of both code paths\n" \
8888" rjmp 9f\n" \
89- "9: nop ; pulse timing delay\n" \
89+ "9: sbiw %A[len], 1 ; decrement outer loop counter\n" \
90+ " in r0, __SREG__ ; save status register\n" \
91+ " breq 10f ; skip if zero\n" \
92+ " ld r18, Z+ ; load next red byte\n" \
93+ "10: brne 11f ; equalise delay of both code paths\n" \
9094" nop\n" \
9195" nop\n" \
92- " ld r18, Z+ ; load next red byte\n" \
93- " ld r19, Z+ ; load next green byte\n" \
96+ "11: cbi %[port], %[pin] ; pin hi -> lo\n" \
9497" ldi r27, 7 ; reload inner loop counter\n" \
95- " cbi %[port], %[pin] ; pin hi -> lo\n" \
96- " nop ; pulse timing delay\n" \
9798" nop\n" \
9899/* blue - loop over first 7 bits */ \
99- "10: sbi %[port], %[pin] ; pin lo -> hi\n" \
100+ "12: sbi %[port], %[pin] ; pin lo -> hi\n" \
100101" sbrc r20, 7 ; test hi bit clear\n" \
101- " rjmp 11f ; true, skip pin hi -> lo\n" \
102+ " rjmp 13f ; true, skip pin hi -> lo\n" \
102103" cbi %[port], %[pin] ; false, pin hi -> lo\n" \
103- "11 : sbrc r20, 7 ; equalise delay of both code paths\n" \
104- " rjmp 12f \n" \
105- "12 : nop ; pulse timing delay \n" \
104+ "13 : sbrc r20, 7 ; equalise delay of both code paths\n" \
105+ " rjmp 14f \n" \
106+ "14 : nop\n" \
106107" nop\n" \
107108" nop\n" \
108109" nop\n" \
@@ -111,35 +112,37 @@ asm volatile( \
111112" lsl r20 ; shift to next bit\n" \
112113" dec r27 ; decrement inner loop counter\n" \
113114" cbi %[port], %[pin] ; pin hi -> lo\n" \
114- " brne 10b ; inner loop, if required\n" \
115+ " brne 12b ; inner loop, if required\n" \
115116" nop ; equalise delay of both code paths\n" \
116117/* blue, 8th bit - output & handle outer loop */ \
117118" sbi %[port], %[pin] ; pin lo -> hi\n" \
118119" sbrc r20, 7 ; test hi bit clear\n" \
119- " rjmp 13f ; true, skip pin hi -> lo\n" \
120+ " rjmp 15f ; true, skip pin hi -> lo\n" \
120121" cbi %[port], %[pin] ; false, pin hi -> lo\n" \
121- "13: sbrc r20, 7 ; equalise delay of both code paths\n" \
122- " rjmp 14f\n" \
123- "14: nop ; pulse timing delay\n" \
124- " nop\n" \
122+ "15: sbrc r20, 7 ; equalise delay of both code paths\n" \
123+ " rjmp 16f\n" \
124+ "16: nop\n" \
125125" ldi r27, 8 ; reload inner loop counter\n" \
126- " sbiw %A[len], 1 ; decrement outer loop counter\n" \
127- " breq 15f ; exit outer loop if zero\n" \
128- " ld r20, Z+ ; load in next blue byte\n" \
126+ " out __SREG__, r0 ; restore status register\n" \
127+ " breq 17f ; exit outer loop if zero\n" \
128+ " ld r19, Z+ ; load next green byte\n" \
129+ " ld r20, Z+ ; load next blue byte\n" \
129130" cbi %[port], %[pin] ; pin hi -> lo\n" \
130131" rjmp 2b ; outer loop, if required\n" \
131- "15: nop ; pulse timing delay\n" \
132+ "17: nop\n" \
133+ " nop\n" \
134+ " nop\n" \
132135" cbi %[port], %[pin] ; pin hi -> lo\n" \
133- " nop ; pulse timing delay \n" \
136+ " nop\n" \
134137" nop\n" \
135138" out __SREG__, r26 ; reenable interrupts\n" \
136- "16 :\n" \
139+ "18 :\n" \
137140: \
138141: [rgb ] "z" (RGB ), \
139142 [len ] "w " (LEN), \
140143 [port] " I " (_SFR_IO_ADDR(PORT)), \
141144 [pin] " I " (PIN) \
142- : " r18 ", " r19 ", " r20 ", " r26 ", " r27 ", " cc ", " memory " \
145+ : " r0 ", " r18 ", " r19 ", " r20 ", " r26 ", " r27 ", " cc ", " memory " \
143146)
144147
145148/*
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