This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic
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Arda Baran
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32-bit arithmetic and logic operations
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One 32-bit full adder for efficient design
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Modular design using multiplexers for operation selection
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Zero-detection output