expropt.conf

#------------------------------------------------------------------------
#
# ACT expropt configuration file
#
#------------------------------------------------------------------------

# the expropt lib namespace
begin expropt

# if syntesis files and logs are removed after being done (for debugging) - defaults to 1 (TRUE)
# int clean_tmp_files 1

# make size-1 input/output ports arrays, instead of single bool: default 0 
# for eg. bool in -> bool in[1] 
# int vectorize_all_ports 0

# use abc constraints: default 0
# int abc_use_constraints 0

# the liberty file used for mapping ans syntesis
string liberty_tt_typtemp "${ACT_HOME}/act/syn/liberty/osu018_stdcells.lib"

# the matching cell librarties for converting back for QDI
string act_cell_lib_qdi "${ACT_HOME}/act/syn/qdi/stdcells.act"
# the namespace they sit in for QDI - default syn
# string act_cell_lib_qdi_namespace "syn"
# the wire type they are using for QDI - default r1of2
# string act_cell_lib_qdi_wire_type "dualrail"

# the matching cell librarties for converting back for BD
string act_cell_lib_bd "${ACT_HOME}/act/syn/bdopt/stdcells.act"
# the namespace they sit in for BD - default syn
# string act_cell_lib_bd_namespace "syn"
# the wire type they are using for BD - default bool
# string act_cell_lib_bd_wire_type "bool"


# the captable for the tech (optional) - white space to seperate files inside string
# string captable
# the lef file for the tech + lib  (optional) - white space to seperate files inside string
# if the techlef is seperate it has to be the first file!
# string lef 

# Logic synthesis tools report dynamic power assuming
# a certain clock frequency. This is the clock period.
# Default is 100 MHz, or 10ns
real dynamic_power_period 10e-9

# the sdf for genus to load (needed for genus corner analysis)
# string timing_constraint_sdf

# the corner setup (genus + yosys):
# corner max power liberty file
# string liberty_ff_hightemp

# corner min delay liberty file
# string liberty_ff_lowtemp

# corner max delay liberty file
# string liberty_ss_hightemp

# genus only qrc extraction libraries
# string qrc_rcmin
# string qrc_rctyp
# string qrc_rcmax

# genus only corner temperature used for the qrc extractiuon
# int hightemp 125
# typical temperature - default 25
# int typtemp 27
# int lowtemp -40

# print what is executed 0 nothing 1 dots 2 full comands - default 1
# int verbose 1

# for speeding things up during development you can skip verification, dont use it for production chips - default 0
# int skip_verification 0

# define the syntesis effort 0 = low, 1 = medium, 2 = high - default 2
# int syntesis_effort 2

end