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make.sh
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make.sh
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#!/usr/bin/bash
set -u
### Generates output files, simulation and logs for the 9 combinations of
### microarchitectures and processor extensions
# Colors
RED='\033[0;31m'
GRN='\033[0;32m'
NOC='\033[0m'
# Compile project
full_compilation (){
[[ -f output_files/fpga_top.sof ]] && rm output_files/fpga_top.sof
[[ -f output_files/fpga_top.flow.rpt ]] && rm output_files/fpga_top.flow.rpt
[[ -f output_files/rv"$1"_make.log ]] && rm output_files/rv"$1"_make.log
[[ -f output_files/rv"$1"_make.report ]] && rm output_files/rv"$1"_make.report
[[ -f ../../test/sof_library/rv"$1".sof ]] && rm ../../test/sof_library/rv"$1".sof
printf "${GRN}Sintetizando versão ${1}:${NOC}\n...\n"
quartus_sh --flow compile fpga_top > output_files/rv"$1"_make.log
if [[ $? -eq 0 ]]; then
printf "${GRN}[SUCESSO]${NOC}\n\n"
cp output_files/fpga_top.sof ../../test/sof_library/rv"$1".sof
cp output_files/fpga_top.flow.rpt output_files/rv"$1"_make.report
else
printf "${RED}[FALHA]${NOC}\n\n"
fi
}
# Simulation
simulate (){
[[ -d ../../test/simulation/output/waveforms ]] || mkdir -p ../../test/simulation/output/waveforms
[[ -d ../../test/simulation/output/logs ]] || mkdir -p ../../test/simulation/output/logs
[[ -f ../../test/simulation/output/waveforms/rv"$1".vcd ]] && rm ../../test/simulation/output/waveforms/rv"$1".vcd
[[ -f ../../test/simulation/output/logs/rv"$1"_sim.log ]] && rm ../../test/simulation/output/logs/rv"$1"_sim.log
[[ -f ../../test/simulation/default_data.mif ]] && rm ../../test/simulation/default_data.mif
[[ -f ../../test/simulation/default_text.mif ]] && rm ../../test/simulation/default_text.mif
full_compilation "$1"
if [[ $? -eq 0 ]]; then
printf "${GRN}Simulando versão ${1}:${NOC}\n...\n"
cp output_files/rv"$1"_make.log ../../test/simulation/output/logs/rv"$1"_sim.log
quartus_fit --read_settings_files=off --write_settings_files=off fpga_top -c fpga_top >> ../../test/simulation/output/logs/rv"$1"_sim.log \
&& quartus_asm --read_settings_files=off --write_settings_files=off fpga_top -c fpga_top >> ../../test/simulation/output/logs/rv"$1"_sim.log \
&& quartus_sta fpga_top -c fpga_top >> ../../test/simulation/output/logs/rv"$1"_sim.log \
&& quartus_eda --read_settings_files=off --write_settings_files=off fpga_top -c fpga_top >> ../../test/simulation/output/logs/rv"$1"_sim.log \
&& quartus_sh -t "$QUARTUS_PATH/common/tcl/internal/nativelink/qnativesim.tcl" fpga_top fpga_top >> ../../test/simulation/output/logs/rv"$1"_sim.log
if [[ $? -eq 0 ]]; then
printf "${GRN}[SUCESSO]${NOC}\n\n"
cp ../../test/simulation/simulation_output.vcd ../../test/simulation/output/waveforms/rv"$1".vcd
cat ../../test/simulation/msim_transcript >> ../../test/simulation/output/logs/rv"$1"_sim.log
else
printf "${RED}[FALHA]${NOC}\n\n"
fi
fi
}
# Analysis and synthesis only
analysis_and_synthesis (){
[[ -d output_files/partial_logs ]] || mkdir -p output_files/partial_logs
[[ -f output_files/partial_logs/rv"$1".log ]] && rm output_files/partial_logs/rv"$1".log
printf "${GRN}Analisando versão ${1}:${NOC}\n...\n"
quartus_map fpga_top > output_files/partial_logs/rv"$1".log
if [[ $? -eq 0 ]]; then
printf "${GRN}[SUCESSO]${NOC}\n\n"
else
printf "$[FALHA]${NOC}\n\n"
return 1
fi
}
select_uarch (){
# Comment out all microarchitectures defines
sed -i 's/^\s*`define UNICICLO$/\/\/ `define UNICICLO/' ../../core/config.v
sed -i 's/^\s*`define MULTICICLO$/\/\/ `define MULTICICLO/' ../../core/config.v
sed -i 's/^\s*`define PIPELINE$/\/\/ `define PIPELINE/' ../../core/config.v
if [[ "$1" == "uni" ]]; then
sed -i 's/^\/\/\s*`define UNICICLO$/`define UNICICLO/' ../../core/config.v
sed -i "s/switch\s*<=.*$/switch <= 10\'b0000011111;/" ../../test/verilog_testbench/fpga_top_tb.v
elif [[ "$1" == "multi" ]]; then
sed -i 's/^\/\/\s*`define MULTICICLO$/`define MULTICICLO/' ../../core/config.v
sed -i "s/switch\s*<=.*$/switch <= 10\'b0000000111;/" ../../test/verilog_testbench/fpga_top_tb.v
elif [[ "$1" == "pipe" ]]; then
sed -i 's/^\/\/\s*`define PIPELINE$/`define PIPELINE/' ../../core/config.v
sed -i "s/switch\s*<=.*$/switch <= 10\'b0000000011;/" ../../test/verilog_testbench/fpga_top_tb.v
fi
}
select_extensions (){
# Comment out all extensions defines
sed -i 's/^\s*`define RV32I$/\/\/ `define RV32I/' ../../core/config.v
sed -i 's/^\s*`define RV32IM$/\/\/ `define RV32IM/' ../../core/config.v
sed -i 's/^\s*`define RV32IMF$/\/\/ `define RV32IMF/' ../../core/config.v
# Remove .ver memory files generated by ModelSim
rm ../../core/*.ver > /dev/null 2>&1
if [[ "$1" == "32i" ]]; then
sed -i 's/^\/\/ `define RV32I$/`define RV32I/' ../../core/config.v
rm ../../core/default_data.mif
rm ../../core/default_text.mif
cp ../../test/mif_library/RV32I/default_data.mif ../../core/
cp ../../test/mif_library/RV32I/default_text.mif ../../core/
elif [[ "$1" == "32im" ]]; then
sed -i 's/^\/\/ `define RV32IM$/`define RV32IM/' ../../core/config.v
rm ../../core/default_data.mif
rm ../../core/default_text.mif
cp ../../test/mif_library/RV32IM/default_data.mif ../../core/
cp ../../test/mif_library/RV32IM/default_text.mif ../../core/
elif [[ "$1" == "32imf" ]]; then
sed -i 's/^\/\/ `define RV32IMF$/`define RV32IMF/' ../../core/config.v
rm ../../core/default_data.mif
rm ../../core/default_text.mif
cp ../../test/mif_library/RV32IMF/default_data.mif ../../core/
cp ../../test/mif_library/RV32IMF/default_text.mif ../../core/
fi
}
# Make a full compilation of all variants
compile_all_variants (){
ARCH=('uni' 'multi' 'pipe')
EXTENSION=('32i' '32im' '32imf')
for i in "${ARCH[@]}"; do
select_uarch "$i"
for j in "${EXTENSION[@]}"; do
select_extensions "$j"
full_compilation "$j""_$i"
done
done
}
# Simulate all variants
simulate_all_variants (){
QUARTUS_PATH=$(echo $PATH | grep -Po "([A-Za-z0-9\./_]*quartus)")
ARCH=('uni' 'multi' 'pipe')
EXTENSION=('32i' '32im' '32imf')
#ARCH=('pipe')
#EXTENSION=('32imf')
for i in "${ARCH[@]}"; do
select_uarch "$i"
for j in "${EXTENSION[@]}"; do
select_extensions "$j"
simulate "$j""_$i"
done
done
}
# Make a partial compilation of all variants
analysis_and_synthesis_all_variants (){
ARCH=('uni' 'multi' 'pipe')
EXTENSION=('32i' '32im' '32imf')
for i in "${ARCH[@]}"; do
select_uarch "$i"
for j in "${EXTENSION[@]}"; do
select_extensions "$j"
analysis_and_synthesis "$j""_$i"
done
done
}
#########################################################################
cd ./project/de1_soc
[[ -d ./output_files ]] || mkdir output_files
if [[ $# -ne 0 ]]; then
case "$1" in
--full )
compile_all_variants
;;
--analyse )
analysis_and_synthesis_all_variants
;;
--simulate )
simulate_all_variants
;;
* )
echo "Choose --full, --analyse or --simulate"
esac
else
echo "Choose --full, --analyse or --simulate"
fi