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| 1 | +// Copyright 2017 Google LLC |
| 2 | +// |
| 3 | +// Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | +// you may not use this file except in compliance with the License. |
| 5 | +// You may obtain a copy of the License at |
| 6 | +// |
| 7 | +// http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | +// |
| 9 | +// Unless required by applicable law or agreed to in writing, software |
| 10 | +// distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | +// See the License for the specific language governing permissions and |
| 13 | +// limitations under the License. |
| 14 | + |
| 15 | +#include "cpu_features_macros.h" |
| 16 | + |
| 17 | +#ifdef CPU_FEATURES_ARCH_AARCH64 |
| 18 | +#if defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) || \ |
| 19 | + defined(CPU_FEATURES_OS_MACOS) |
| 20 | + |
| 21 | +#include "cpuinfo_aarch64.h" |
| 22 | + |
| 23 | +//////////////////////////////////////////////////////////////////////////////// |
| 24 | +// Definitions for introspection. |
| 25 | +//////////////////////////////////////////////////////////////////////////////// |
| 26 | +#define INTROSPECTION_TABLE \ |
| 27 | + LINE(AARCH64_FP, fp, "fp", AARCH64_HWCAP_FP, 0) \ |
| 28 | + LINE(AARCH64_ASIMD, asimd, "asimd", AARCH64_HWCAP_ASIMD, 0) \ |
| 29 | + LINE(AARCH64_EVTSTRM, evtstrm, "evtstrm", AARCH64_HWCAP_EVTSTRM, 0) \ |
| 30 | + LINE(AARCH64_AES, aes, "aes", AARCH64_HWCAP_AES, 0) \ |
| 31 | + LINE(AARCH64_PMULL, pmull, "pmull", AARCH64_HWCAP_PMULL, 0) \ |
| 32 | + LINE(AARCH64_SHA1, sha1, "sha1", AARCH64_HWCAP_SHA1, 0) \ |
| 33 | + LINE(AARCH64_SHA2, sha2, "sha2", AARCH64_HWCAP_SHA2, 0) \ |
| 34 | + LINE(AARCH64_CRC32, crc32, "crc32", AARCH64_HWCAP_CRC32, 0) \ |
| 35 | + LINE(AARCH64_ATOMICS, atomics, "atomics", AARCH64_HWCAP_ATOMICS, 0) \ |
| 36 | + LINE(AARCH64_FPHP, fphp, "fphp", AARCH64_HWCAP_FPHP, 0) \ |
| 37 | + LINE(AARCH64_ASIMDHP, asimdhp, "asimdhp", AARCH64_HWCAP_ASIMDHP, 0) \ |
| 38 | + LINE(AARCH64_CPUID, cpuid, "cpuid", AARCH64_HWCAP_CPUID, 0) \ |
| 39 | + LINE(AARCH64_ASIMDRDM, asimdrdm, "asimdrdm", AARCH64_HWCAP_ASIMDRDM, 0) \ |
| 40 | + LINE(AARCH64_JSCVT, jscvt, "jscvt", AARCH64_HWCAP_JSCVT, 0) \ |
| 41 | + LINE(AARCH64_FCMA, fcma, "fcma", AARCH64_HWCAP_FCMA, 0) \ |
| 42 | + LINE(AARCH64_LRCPC, lrcpc, "lrcpc", AARCH64_HWCAP_LRCPC, 0) \ |
| 43 | + LINE(AARCH64_DCPOP, dcpop, "dcpop", AARCH64_HWCAP_DCPOP, 0) \ |
| 44 | + LINE(AARCH64_SHA3, sha3, "sha3", AARCH64_HWCAP_SHA3, 0) \ |
| 45 | + LINE(AARCH64_SM3, sm3, "sm3", AARCH64_HWCAP_SM3, 0) \ |
| 46 | + LINE(AARCH64_SM4, sm4, "sm4", AARCH64_HWCAP_SM4, 0) \ |
| 47 | + LINE(AARCH64_ASIMDDP, asimddp, "asimddp", AARCH64_HWCAP_ASIMDDP, 0) \ |
| 48 | + LINE(AARCH64_SHA512, sha512, "sha512", AARCH64_HWCAP_SHA512, 0) \ |
| 49 | + LINE(AARCH64_SVE, sve, "sve", AARCH64_HWCAP_SVE, 0) \ |
| 50 | + LINE(AARCH64_ASIMDFHM, asimdfhm, "asimdfhm", AARCH64_HWCAP_ASIMDFHM, 0) \ |
| 51 | + LINE(AARCH64_DIT, dit, "dit", AARCH64_HWCAP_DIT, 0) \ |
| 52 | + LINE(AARCH64_USCAT, uscat, "uscat", AARCH64_HWCAP_USCAT, 0) \ |
| 53 | + LINE(AARCH64_ILRCPC, ilrcpc, "ilrcpc", AARCH64_HWCAP_ILRCPC, 0) \ |
| 54 | + LINE(AARCH64_FLAGM, flagm, "flagm", AARCH64_HWCAP_FLAGM, 0) \ |
| 55 | + LINE(AARCH64_SSBS, ssbs, "ssbs", AARCH64_HWCAP_SSBS, 0) \ |
| 56 | + LINE(AARCH64_SB, sb, "sb", AARCH64_HWCAP_SB, 0) \ |
| 57 | + LINE(AARCH64_PACA, paca, "paca", AARCH64_HWCAP_PACA, 0) \ |
| 58 | + LINE(AARCH64_PACG, pacg, "pacg", AARCH64_HWCAP_PACG, 0) \ |
| 59 | + LINE(AARCH64_DCPODP, dcpodp, "dcpodp", 0, AARCH64_HWCAP2_DCPODP) \ |
| 60 | + LINE(AARCH64_SVE2, sve2, "sve2", 0, AARCH64_HWCAP2_SVE2) \ |
| 61 | + LINE(AARCH64_SVEAES, sveaes, "sveaes", 0, AARCH64_HWCAP2_SVEAES) \ |
| 62 | + LINE(AARCH64_SVEPMULL, svepmull, "svepmull", 0, AARCH64_HWCAP2_SVEPMULL) \ |
| 63 | + LINE(AARCH64_SVEBITPERM, svebitperm, "svebitperm", 0, \ |
| 64 | + AARCH64_HWCAP2_SVEBITPERM) \ |
| 65 | + LINE(AARCH64_SVESHA3, svesha3, "svesha3", 0, AARCH64_HWCAP2_SVESHA3) \ |
| 66 | + LINE(AARCH64_SVESM4, svesm4, "svesm4", 0, AARCH64_HWCAP2_SVESM4) \ |
| 67 | + LINE(AARCH64_FLAGM2, flagm2, "flagm2", 0, AARCH64_HWCAP2_FLAGM2) \ |
| 68 | + LINE(AARCH64_FRINT, frint, "frint", 0, AARCH64_HWCAP2_FRINT) \ |
| 69 | + LINE(AARCH64_SVEI8MM, svei8mm, "svei8mm", 0, AARCH64_HWCAP2_SVEI8MM) \ |
| 70 | + LINE(AARCH64_SVEF32MM, svef32mm, "svef32mm", 0, AARCH64_HWCAP2_SVEF32MM) \ |
| 71 | + LINE(AARCH64_SVEF64MM, svef64mm, "svef64mm", 0, AARCH64_HWCAP2_SVEF64MM) \ |
| 72 | + LINE(AARCH64_SVEBF16, svebf16, "svebf16", 0, AARCH64_HWCAP2_SVEBF16) \ |
| 73 | + LINE(AARCH64_I8MM, i8mm, "i8mm", 0, AARCH64_HWCAP2_I8MM) \ |
| 74 | + LINE(AARCH64_BF16, bf16, "bf16", 0, AARCH64_HWCAP2_BF16) \ |
| 75 | + LINE(AARCH64_DGH, dgh, "dgh", 0, AARCH64_HWCAP2_DGH) \ |
| 76 | + LINE(AARCH64_RNG, rng, "rng", 0, AARCH64_HWCAP2_RNG) \ |
| 77 | + LINE(AARCH64_BTI, bti, "bti", 0, AARCH64_HWCAP2_BTI) \ |
| 78 | + LINE(AARCH64_MTE, mte, "mte", 0, AARCH64_HWCAP2_MTE) |
| 79 | +#define INTROSPECTION_PREFIX Aarch64 |
| 80 | +#define INTROSPECTION_ENUM_PREFIX AARCH64 |
| 81 | +#include "define_introspection_and_hwcaps.inl" |
| 82 | + |
| 83 | +//////////////////////////////////////////////////////////////////////////////// |
| 84 | +// Implementation. |
| 85 | +//////////////////////////////////////////////////////////////////////////////// |
| 86 | + |
| 87 | +#include <stdbool.h> |
| 88 | + |
| 89 | +#include "internal/bit_utils.h" |
| 90 | +#include "internal/filesystem.h" |
| 91 | +#include "internal/stack_line_reader.h" |
| 92 | +#include "internal/string_view.h" |
| 93 | + |
| 94 | +static bool HandleAarch64Line(const LineResult result, Aarch64Info* const info); |
| 95 | + |
| 96 | +static void FillProcCpuInfoData(Aarch64Info* const info); |
| 97 | + |
| 98 | +#endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) || |
| 99 | + // defined(CPU_FEATURES_OS_MACOS) |
| 100 | +#endif // CPU_FEATURES_ARCH_AARCH64 |
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