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deanm1278deanm1278
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DM: actually fixed warnings
1 parent 7018f51 commit c6fc946

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ac.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/adc.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/aes.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/ccl.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/cmcc.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dac.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dmac.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/dsu.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/eic.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/evsys.h

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‎CMSIS-Atmel/CMSIS/Device/ATMEL/samd51/include/component/freqm.h

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -51,13 +51,13 @@ typedef union {
5151
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
5252

5353
#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
54-
#define FREQM_CTRLA_RESETVALUE _U(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
54+
#define FREQM_CTRLA_RESETVALUE _Ul(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
5555

5656
#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
57-
#define FREQM_CTRLA_SWRST (_U(0x1) << FREQM_CTRLA_SWRST_Pos)
57+
#define FREQM_CTRLA_SWRST (_Ul(0x1) << FREQM_CTRLA_SWRST_Pos)
5858
#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
59-
#define FREQM_CTRLA_ENABLE (_U(0x1) << FREQM_CTRLA_ENABLE_Pos)
60-
#define FREQM_CTRLA_MASK _U(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
59+
#define FREQM_CTRLA_ENABLE (_Ul(0x1) << FREQM_CTRLA_ENABLE_Pos)
60+
#define FREQM_CTRLA_MASK _Ul(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
6161

6262
/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
6363
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -71,11 +71,11 @@ typedef union {
7171
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
7272

7373
#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
74-
#define FREQM_CTRLB_RESETVALUE _U(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
74+
#define FREQM_CTRLB_RESETVALUE _Ul(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
7575

7676
#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
77-
#define FREQM_CTRLB_START (_U(0x1) << FREQM_CTRLB_START_Pos)
78-
#define FREQM_CTRLB_MASK _U(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
77+
#define FREQM_CTRLB_START (_Ul(0x1) << FREQM_CTRLB_START_Pos)
78+
#define FREQM_CTRLB_MASK _Ul(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
7979

8080
/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
8181
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -89,12 +89,12 @@ typedef union {
8989
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
9090

9191
#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
92-
#define FREQM_CFGA_RESETVALUE _U(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
92+
#define FREQM_CFGA_RESETVALUE _Ul(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
9393

9494
#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
95-
#define FREQM_CFGA_REFNUM_Msk (_U(0xFF) << FREQM_CFGA_REFNUM_Pos)
95+
#define FREQM_CFGA_REFNUM_Msk (_Ul(0xFF) << FREQM_CFGA_REFNUM_Pos)
9696
#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
97-
#define FREQM_CFGA_MASK _U(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
97+
#define FREQM_CFGA_MASK _Ul(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
9898

9999
/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
100100
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -108,11 +108,11 @@ typedef union {
108108
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
109109

110110
#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
111-
#define FREQM_INTENCLR_RESETVALUE _U(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
111+
#define FREQM_INTENCLR_RESETVALUE _Ul(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
112112

113113
#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
114-
#define FREQM_INTENCLR_DONE (_U(0x1) << FREQM_INTENCLR_DONE_Pos)
115-
#define FREQM_INTENCLR_MASK _U(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
114+
#define FREQM_INTENCLR_DONE (_Ul(0x1) << FREQM_INTENCLR_DONE_Pos)
115+
#define FREQM_INTENCLR_MASK _Ul(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
116116

117117
/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
118118
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -126,11 +126,11 @@ typedef union {
126126
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
127127

128128
#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
129-
#define FREQM_INTENSET_RESETVALUE _U(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
129+
#define FREQM_INTENSET_RESETVALUE _Ul(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
130130

131131
#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
132-
#define FREQM_INTENSET_DONE (_U(0x1) << FREQM_INTENSET_DONE_Pos)
133-
#define FREQM_INTENSET_MASK _U(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
132+
#define FREQM_INTENSET_DONE (_Ul(0x1) << FREQM_INTENSET_DONE_Pos)
133+
#define FREQM_INTENSET_MASK _Ul(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
134134

135135
/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
136136
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -144,11 +144,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
144144
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
145145

146146
#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
147-
#define FREQM_INTFLAG_RESETVALUE _U(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
147+
#define FREQM_INTFLAG_RESETVALUE _Ul(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
148148

149149
#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
150-
#define FREQM_INTFLAG_DONE (_U(0x1) << FREQM_INTFLAG_DONE_Pos)
151-
#define FREQM_INTFLAG_MASK _U(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
150+
#define FREQM_INTFLAG_DONE (_Ul(0x1) << FREQM_INTFLAG_DONE_Pos)
151+
#define FREQM_INTFLAG_MASK _Ul(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
152152

153153
/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
154154
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -163,13 +163,13 @@ typedef union {
163163
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
164164

165165
#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
166-
#define FREQM_STATUS_RESETVALUE _U(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
166+
#define FREQM_STATUS_RESETVALUE _Ul(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
167167

168168
#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
169-
#define FREQM_STATUS_BUSY (_U(0x1) << FREQM_STATUS_BUSY_Pos)
169+
#define FREQM_STATUS_BUSY (_Ul(0x1) << FREQM_STATUS_BUSY_Pos)
170170
#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
171-
#define FREQM_STATUS_OVF (_U(0x1) << FREQM_STATUS_OVF_Pos)
172-
#define FREQM_STATUS_MASK _U(0x03) /**< \brief (FREQM_STATUS) MASK Register */
171+
#define FREQM_STATUS_OVF (_Ul(0x1) << FREQM_STATUS_OVF_Pos)
172+
#define FREQM_STATUS_MASK _Ul(0x03) /**< \brief (FREQM_STATUS) MASK Register */
173173

174174
/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
175175
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -184,13 +184,13 @@ typedef union {
184184
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
185185

186186
#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
187-
#define FREQM_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
187+
#define FREQM_SYNCBUSY_RESETVALUE _Ul(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
188188

189189
#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
190-
#define FREQM_SYNCBUSY_SWRST (_U(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
190+
#define FREQM_SYNCBUSY_SWRST (_Ul(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
191191
#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
192-
#define FREQM_SYNCBUSY_ENABLE (_U(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
193-
#define FREQM_SYNCBUSY_MASK _U(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
192+
#define FREQM_SYNCBUSY_ENABLE (_Ul(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
193+
#define FREQM_SYNCBUSY_MASK _Ul(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
194194

195195
/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
196196
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -204,12 +204,12 @@ typedef union {
204204
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
205205

206206
#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
207-
#define FREQM_VALUE_RESETVALUE _U(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
207+
#define FREQM_VALUE_RESETVALUE _Ul(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
208208

209209
#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
210-
#define FREQM_VALUE_VALUE_Msk (_U(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
210+
#define FREQM_VALUE_VALUE_Msk (_Ul(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
211211
#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
212-
#define FREQM_VALUE_MASK _U(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
212+
#define FREQM_VALUE_MASK _Ul(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
213213

214214
/** \brief FREQM hardware registers */
215215
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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