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tq-steinaShawn Guo
tq-steina
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Shawn Guo
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arm64: dts: freescale: add initial device tree for TQMa8MQML with i.MX8MM
This adds support for TQMa8MQML module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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‎arch/arm64/boot/dts/freescale/Makefile‎

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@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb

‎arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts‎

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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright 2020-2021 TQ-Systems GmbH
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*/
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/dts-v1/;
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#include "imx8mm-tqma8mqml.dtsi"
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#include "mba8mx.dtsi"
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/ {
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model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
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compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
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aliases {
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eeprom0 = &eeprom3;
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mmc0 = &usdhc3;
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mmc1 = &usdhc2;
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mmc2 = &usdhc1;
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rtc0 = &pcf85063;
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rtc1 = &snvs_rtc;
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};
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reg_usdhc2_vmmc: regulator-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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extcon_usbotg1: extcon-usbotg1 {
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compatible = "linux,extcon-usb-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_extcon>;
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id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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};
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&i2c1 {
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expander2: gpio@27 {
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compatible = "nxp,pca9555";
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reg = <0x27>;
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gpio-controller;
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#gpio-cells = <2>;
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vcc-supply = <&reg_vcc_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_expander>;
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interrupt-parent = <&gpio1>;
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interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&sai3 {
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assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
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clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
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<&clk IMX8MM_AUDIO_PLL2_OUT>;
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};
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&tlv320aic3x04 {
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clock-names = "mclk";
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clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
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};
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&uart1 {
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assigned-clocks = <&clk IMX8MM_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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};
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&uart2 {
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assigned-clocks = <&clk IMX8MM_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1>;
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dr_mode = "otg";
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extcon = <&extcon_usbotg1>;
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srp-disable;
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hnp-disable;
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adp-disable;
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power-active-high;
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over-current-active-low;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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vbus-supply = <&reg_hub_vbus>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>,
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<MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x00000006>,
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<MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x00000006>,
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<MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00000006>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000006>,
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<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x00000006>,
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<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x00000006>,
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<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000006>;
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};
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pinctrl_expander: expandergrp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>,
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<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002>,
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<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14>,
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<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14>,
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<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14>,
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<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14>,
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<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90>,
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<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90>,
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<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90>,
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<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90>,
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<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14>,
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<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90>,
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<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>,
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<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>;
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};
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pinctrl_gpiobutton: gpiobuttongrp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>,
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<MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x84>,
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<MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x84>;
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};
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pinctrl_gpioled: gpioledgrp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>,
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<MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x84>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000004>,
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<MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000004>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000004>,
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<MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000004>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000004>,
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<MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000004>;
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};
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pinctrl_i2c3_gpio: i2c3gpiogrp {
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fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000004>,
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<MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000004>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>;
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};
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pinctrl_pwm4: pwm4grp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>,
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<MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x94>,
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<MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x94>,
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<MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x94>,
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<MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x94>,
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<MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x94>,
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<MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x94>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>,
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<MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x16>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>,
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<MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x16>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>,
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<MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x16>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>,
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<MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x16>;
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};
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pinctrl_usbotg1: usbotg1grp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
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<MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>;
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};
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pinctrl_usb1_extcon: usb1-extcongrp {
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fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
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fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
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<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
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<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
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<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
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<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
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<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
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<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
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<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
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};
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};

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