Assembled boards now available! get one here :)
Eurorack PMOD makes it easy for you to combine the world of FPGAs and hardware electronic music synthesis. It is an expansion board for FPGA development boards that allows them to interface with a Eurorack hardware synthesizer. This board exposes 8 (4 in + 4 out) DC-coupled audio channels, 192KHz / 32bit sampling supported, at a -8V to +8V swing, amongst many more features. R3.1 hardware looks like this:
For a high-level overview on R2.2 hardware, see my FOSDEM '23 talk on this project. Production hardware is named R3+ and has a few improvements (LEDs fully programmable, jack detection, calibration EEPROM).
Want one?. More photos can be found below.
- The design for a Eurorack-compatible PCB and front-panel, including a PMOD connector (compatible with most FPGA dev boards). PCB designed in KiCAD. Design is certified open hardware.
- Various example cores (and calibration / driver cores for the audio CODEC) initially targeting an iCEBreaker FPGA (iCE40 part) but many more boards are supported (see below). Examples include calibration, sampling, effects, synthesis sources and so on. The design files can be synthesized to a bitstream using Yosys' oss-cad-suite.
- A VCV Rack plugin so you can simulate your Verilog designs in a completely virtual modular system, no hardware required.
This repository contains a bunch of example DSP cores which are continuously being updated:
- Bitcrusher
- Filter (high pass / low pass / band pass)
- Clock divider
- .wav sampler
- Pitch shifter
- Sequential routing switch
- Echo/delay effect
- VCA (voltage controlled amplifier)
- VCO (voltage controlled oscillator)
These examples can all run out of the box on the development boards listed below.
An FPGA development board itself is NOT included! Essentially anything iCE40 or ECP5 based that has a PMOD connector will support the open-source tools and the examples in this project. Just make sure you have enough LUTS, >3K is enough to do interesting things.
The following development boards have been tested with eurorack-pmod
and are supported by the examples in the github repository
- iCEbreaker (iCE40 based)
- ECPIX-5 (ECP5 based)
- Colorlight i5 (ECP5 based)
- Colorlight i9 (ECP5 based)
- pico-ice from TinyVision (iCE40 based)
- 3HP module compatible with modular synthesizer systems.
- Module depth is 47mm with both ribbon cables attached
- This fits nicely in e.g. a 4MS POD 48X (pictured below).
- PMOD connector compatible with most FPGA development boards.
- 8 (4 in + 4 out) DC-coupled audio channels, 192KHz / 32bit sampling supported.
- PWM-controlled, user-programmable red/green LEDs on each output channel.
- Jack insertion detection on input & output jacks.
- Calibration EEPROM for unique ID and storing calibration data.
- I/O is about +/- 8V capable, wider is possible with a resistor change.
The PMOD pinout is on the silkscreen on the back side of the board. Details are below. Note that Pin 1 is the SQUARE pad.
- SDI (AK4619VN SDIN1)
- SCL (I2C SCL for AK4619VN CODEC, EEPROM, LED + JACK IO expanders)
- SDO (AK4619VN SDOUT1)
- SDA (I2C SDA)
- LRCK (CODEC clock line)
- PDN (CODEC power down, also connected to LED output enable and JACK reset line -- HIGH means everything is on)
- BICK (CODEC clock line)
- MCLK (CODEC clock line)
- GND
- GND
- 3V3 IN
- 3V3 IN
- Examples based on iCE40 and ECP5 based FPGAs supported by open-source tools.
- User-defined DSP logic is decoupled from rest of system (see
gateware/cores
directory)
For now, I have tested builds on Linux and Windows (under MSYS2). Both are tested in CI.
-
Install the OSS FPGA CAD flow.
- You may be able to get yosys / verilator from other package managers but I recommend using the releases from YosysHQ so you're using the same binaries that CI is using.
- On Linux, once the YosysHQ suite is installed and in PATH, you should be able to just use
make
in the gateware directory. - On Windows, CI is using MSYS2 with MINGW64 shell. Install MSYS2, MINGW64, extract the oss-cad-suite from YosysHQ and add it to PATH. Then you should be able to use
make
in the gateware directory. - Note: The gateware is automatically built and tested in CI, so for either platform it may be helpful to look at
.github/workflows/main.yml
.
-
Build or obtain
eurorack-pmod
hardware and connect it to your FPGA development board using a ribbon cable or similar. (Double check that the pin mappings are correct, some ribbon cables will swap them on you! Default pinmaps are for the ribbon cables I shipped with hardware, you need to flip the pinmaps for a direct connection PMOD -> FPGA) -
Try some of the examples. From the
gateware
directory, typemake
to see valid commands. By default if you do not select a CORE it will compile a bitstream with the 'mirror' core, which just sends inputs to outputs. Note, you'll need to rungit submodule update --init --recursive
from the repo root after checkout. -
Calibrate your hardware using the process described in
gateware/cal/cal.py
. Use this to create your owngateware/cal/cal_mem.hex
to compensate for any DC biases in the ADCs/DACs. (this step is only necessary if you need sub-50mV accuracy on your inputs/outputs, which is the case if you are tuning oscillators, not so much if you are creating rhythm pulses.
The project is split into 2 directories, hardware
for the PCB/panel and gateware
for the FPGA source. Some interesting directories:
gateware/cores
: example user core implementations (i.e sequential switch, bitcrusher, filter, vco, vca, sampler etc).gateware/top.sv
: top-level gateware with defines for selecting features.gateware/cal/cal.py
: tool used to calibrate the hardware after assembly, generating calibration memory.gateware/drivers
: driver for CODEC and I2C devices used on this board.hardware/eurorack-pmod-r3
: KiCAD design files for PCB and front panel.hardware/fab
: gerber files and BOM for manufacturing the hardware.
Assembled boards now available! get one here :)
Update: R3.1 (first production release) is fully functional with 1 rework, see github issues for up-to-date information.
Note: I gave some R3.0 (preproduction) units out at Hackaday Berlin '23. These are tested but NOT calibrated. They had 2 hacks applied. Some inductors are shorted with 0 ohm resistors as the wrong inductor was populated (means the board is a bit noiser than it should be - but still definitely useable). Also the reset line of the jack detect IO expander was routed incorrectly, so I manually shorted 2 pins of that chip. Functionally these boards are the same as R3.1, which fixes these issues.
- Moved to github issues
Hardware and gateware are released under the CERN Open-Hardware License V2 CERN-OHL-S
, mirrored in the LICENSE text in this repository.
If you wish to license parts of this design in a commercial product without a reciprocal open-source license, or you have a ground-breaking idea for a module we could work on together, feel free to contact me directly. See sebholzapfel.com.
Copyright (C) 2022,2023 Sebastian Holzapfel
The above LICENSE and copyright notice does NOT apply to imported artifacts in this repository (i.e datasheets, third-party footprints).