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jnikulajnikula
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Merge tag 'gvt-next-2020-11-23' of https://github.com/intel/gvt-linux into drm-intel-next-queued
gvt-next-2020-11-23 - Fix host suspend/resume with vGPU (Colin) - optimize idr init (Varma) - Change intel_gvt_mpt as const (Julian) - One comment error fix (Yan) Signed-off-by: Jani Nikula <jani.nikula@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201123090517.GC16939@zhen-hp.sh.intel.com
2 parents f287c53 + 9a3a238 commit 69d5c4b

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14 files changed

+338
-10
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14 files changed

+338
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lines changed

‎drivers/gpu/drm/i915/gvt/display.c‎

Lines changed: 179 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -173,22 +173,162 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
173173
int pipe;
174174

175175
if (IS_BROXTON(dev_priv)) {
176+
enum transcoder trans;
177+
enum port port;
178+
179+
/* Clear PIPE, DDI, PHY, HPD before setting new */
176180
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
177181
~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
178182
GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
179183
GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
180184

185+
for_each_pipe(dev_priv, pipe) {
186+
vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
187+
~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
188+
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
189+
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
190+
vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
191+
vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
192+
}
193+
194+
for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
195+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
196+
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
197+
TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
198+
}
199+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
200+
~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
201+
TRANS_DDI_PORT_MASK);
202+
203+
for (port = PORT_A; port <= PORT_C; port++) {
204+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
205+
~BXT_PHY_LANE_ENABLED;
206+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
207+
(BXT_PHY_CMNLANE_POWERDOWN_ACK |
208+
BXT_PHY_LANE_POWERDOWN_ACK);
209+
210+
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
211+
~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
212+
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
213+
PORT_PLL_ENABLE);
214+
215+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
216+
~(DDI_INIT_DISPLAY_DETECTED |
217+
DDI_BUF_CTL_ENABLE);
218+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
219+
}
220+
221+
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
222+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
223+
~PHY_POWER_GOOD;
224+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
225+
~PHY_POWER_GOOD;
226+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
227+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
228+
229+
vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
230+
vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
231+
232+
/*
233+
* Only 1 PIPE enabled in current vGPU display and PIPE_A is
234+
* tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
235+
* TRANSCODER_A can be enabled. PORT_x depends on the input of
236+
* setup_virtual_dp_monitor.
237+
*/
238+
vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
239+
vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
240+
241+
/*
242+
* Golden M/N are calculated based on:
243+
* 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
244+
* DP link clk 1620 MHz and non-constant_n.
245+
* TODO: calculate DP link symbol clk and stream clk m/n.
246+
*/
247+
vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
248+
vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
249+
vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
250+
vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
251+
vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
252+
253+
/* Enable per-DDI/PORT vreg */
181254
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
255+
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
256+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
257+
PHY_POWER_GOOD;
258+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
259+
BIT(30);
260+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
261+
BXT_PHY_LANE_ENABLED;
262+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
263+
~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
264+
BXT_PHY_LANE_POWERDOWN_ACK);
265+
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
266+
(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
267+
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
268+
PORT_PLL_ENABLE);
269+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
270+
(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
271+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
272+
~DDI_BUF_IS_IDLE;
273+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
274+
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
275+
TRANS_DDI_FUNC_ENABLE);
182276
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
183277
GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
184278
}
185279

186280
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
281+
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
282+
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
283+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
284+
PHY_POWER_GOOD;
285+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
286+
BIT(30);
287+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
288+
BXT_PHY_LANE_ENABLED;
289+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
290+
~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
291+
BXT_PHY_LANE_POWERDOWN_ACK);
292+
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
293+
(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
294+
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
295+
PORT_PLL_ENABLE);
296+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
297+
DDI_BUF_CTL_ENABLE;
298+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
299+
~DDI_BUF_IS_IDLE;
300+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
301+
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
302+
(PORT_B << TRANS_DDI_PORT_SHIFT) |
303+
TRANS_DDI_FUNC_ENABLE);
187304
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
188305
GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
189306
}
190307

191308
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
309+
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
310+
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
311+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
312+
PHY_POWER_GOOD;
313+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
314+
BIT(30);
315+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
316+
BXT_PHY_LANE_ENABLED;
317+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
318+
~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
319+
BXT_PHY_LANE_POWERDOWN_ACK);
320+
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
321+
(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
322+
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
323+
PORT_PLL_ENABLE);
324+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
325+
DDI_BUF_CTL_ENABLE;
326+
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
327+
~DDI_BUF_IS_IDLE;
328+
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
329+
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
330+
(PORT_B << TRANS_DDI_PORT_SHIFT) |
331+
TRANS_DDI_FUNC_ENABLE);
192332
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
193333
GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
194334
}
@@ -520,6 +660,45 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
520660
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
521661
PORTD_HOTPLUG_STATUS_MASK;
522662
intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
663+
} else if (IS_BROXTON(i915)) {
664+
if (connected) {
665+
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
666+
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
667+
GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
668+
}
669+
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
670+
vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
671+
SFUSE_STRAP_DDIB_DETECTED;
672+
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
673+
GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
674+
}
675+
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
676+
vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
677+
SFUSE_STRAP_DDIC_DETECTED;
678+
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
679+
GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
680+
}
681+
} else {
682+
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
683+
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
684+
~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
685+
}
686+
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
687+
vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
688+
~SFUSE_STRAP_DDIB_DETECTED;
689+
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
690+
~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
691+
}
692+
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
693+
vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
694+
~SFUSE_STRAP_DDIC_DETECTED;
695+
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
696+
~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
697+
}
698+
}
699+
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
700+
PORTB_HOTPLUG_STATUS_MASK;
701+
intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
523702
}
524703
}
525704

‎drivers/gpu/drm/i915/gvt/gtt.c‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -636,9 +636,18 @@ static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
636636
struct intel_gvt_gtt_entry *entry, unsigned long index)
637637
{
638638
struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
639+
unsigned long offset = index;
639640

640641
GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
641642

643+
if (vgpu_gmadr_is_aperture(mm->vgpu, index << I915_GTT_PAGE_SHIFT)) {
644+
offset -= (vgpu_aperture_gmadr_base(mm->vgpu) >> PAGE_SHIFT);
645+
mm->ggtt_mm.host_ggtt_aperture[offset] = entry->val64;
646+
} else if (vgpu_gmadr_is_hidden(mm->vgpu, index << I915_GTT_PAGE_SHIFT)) {
647+
offset -= (vgpu_hidden_gmadr_base(mm->vgpu) >> PAGE_SHIFT);
648+
mm->ggtt_mm.host_ggtt_hidden[offset] = entry->val64;
649+
}
650+
642651
pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
643652
}
644653

@@ -1944,6 +1953,21 @@ static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
19441953
return ERR_PTR(-ENOMEM);
19451954
}
19461955

1956+
mm->ggtt_mm.host_ggtt_aperture = vzalloc((vgpu_aperture_sz(vgpu) >> PAGE_SHIFT) * sizeof(u64));
1957+
if (!mm->ggtt_mm.host_ggtt_aperture) {
1958+
vfree(mm->ggtt_mm.virtual_ggtt);
1959+
vgpu_free_mm(mm);
1960+
return ERR_PTR(-ENOMEM);
1961+
}
1962+
1963+
mm->ggtt_mm.host_ggtt_hidden = vzalloc((vgpu_hidden_sz(vgpu) >> PAGE_SHIFT) * sizeof(u64));
1964+
if (!mm->ggtt_mm.host_ggtt_hidden) {
1965+
vfree(mm->ggtt_mm.host_ggtt_aperture);
1966+
vfree(mm->ggtt_mm.virtual_ggtt);
1967+
vgpu_free_mm(mm);
1968+
return ERR_PTR(-ENOMEM);
1969+
}
1970+
19471971
return mm;
19481972
}
19491973

@@ -1971,6 +1995,8 @@ void _intel_vgpu_mm_release(struct kref *mm_ref)
19711995
invalidate_ppgtt_mm(mm);
19721996
} else {
19731997
vfree(mm->ggtt_mm.virtual_ggtt);
1998+
vfree(mm->ggtt_mm.host_ggtt_aperture);
1999+
vfree(mm->ggtt_mm.host_ggtt_hidden);
19742000
}
19752001

19762002
vgpu_free_mm(mm);
@@ -2852,3 +2878,41 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
28522878
intel_vgpu_destroy_all_ppgtt_mm(vgpu);
28532879
intel_vgpu_reset_ggtt(vgpu, true);
28542880
}
2881+
2882+
/**
2883+
* intel_gvt_restore_ggtt - restore all vGPU's ggtt entries
2884+
* @gvt: intel gvt device
2885+
*
2886+
* This function is called at driver resume stage to restore
2887+
* GGTT entries of every vGPU.
2888+
*
2889+
*/
2890+
void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
2891+
{
2892+
struct intel_vgpu *vgpu;
2893+
struct intel_vgpu_mm *mm;
2894+
int id;
2895+
gen8_pte_t pte;
2896+
u32 idx, num_low, num_hi, offset;
2897+
2898+
/* Restore dirty host ggtt for all vGPUs */
2899+
idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
2900+
mm = vgpu->gtt.ggtt_mm;
2901+
2902+
num_low = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2903+
offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2904+
for (idx = 0; idx < num_low; idx++) {
2905+
pte = mm->ggtt_mm.host_ggtt_aperture[idx];
2906+
if (pte & _PAGE_PRESENT)
2907+
write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
2908+
}
2909+
2910+
num_hi = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2911+
offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2912+
for (idx = 0; idx < num_hi; idx++) {
2913+
pte = mm->ggtt_mm.host_ggtt_hidden[idx];
2914+
if (pte & _PAGE_PRESENT)
2915+
write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
2916+
}
2917+
}
2918+
}

‎drivers/gpu/drm/i915/gvt/gtt.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,9 @@ struct intel_vgpu_mm {
164164
} ppgtt_mm;
165165
struct {
166166
void *virtual_ggtt;
167+
/* Save/restore for PM */
168+
u64 *host_ggtt_aperture;
169+
u64 *host_ggtt_hidden;
167170
struct list_head partial_pte_list;
168171
} ggtt_mm;
169172
};
@@ -280,5 +283,6 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
280283
unsigned int off, void *p_data, unsigned int bytes);
281284

282285
void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu);
286+
void intel_gvt_restore_ggtt(struct intel_gvt *gvt);
283287

284288
#endif /* _GVT_GTT_H_ */

‎drivers/gpu/drm/i915/gvt/gvt.c‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,7 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
312312

313313
gvt_dbg_core("init gvt device\n");
314314

315-
idr_init(&gvt->vgpu_idr);
315+
idr_init_base(&gvt->vgpu_idr, 1);
316316
spin_lock_init(&gvt->scheduler.mmio_context_lock);
317317
mutex_init(&gvt->lock);
318318
mutex_init(&gvt->sched_lock);
@@ -406,7 +406,16 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
406406
}
407407

408408
int
409-
intel_gvt_register_hypervisor(struct intel_gvt_mpt *m)
409+
intel_gvt_pm_resume(struct intel_gvt *gvt)
410+
{
411+
intel_gvt_restore_fence(gvt);
412+
intel_gvt_restore_mmio(gvt);
413+
intel_gvt_restore_ggtt(gvt);
414+
return 0;
415+
}
416+
417+
int
418+
intel_gvt_register_hypervisor(const struct intel_gvt_mpt *m)
410419
{
411420
int ret;
412421
void *gvt;

‎drivers/gpu/drm/i915/gvt/gvt.h‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ struct intel_gvt_host {
5656
struct device *dev;
5757
bool initialized;
5858
int hypervisor_type;
59-
struct intel_gvt_mpt *mpt;
59+
const struct intel_gvt_mpt *mpt;
6060
};
6161

6262
extern struct intel_gvt_host intel_gvt_host;
@@ -255,7 +255,9 @@ struct intel_gvt_mmio {
255255
#define F_CMD_ACCESS (1 << 3)
256256
/* This reg has been accessed by a VM */
257257
#define F_ACCESSED (1 << 4)
258-
/* This reg has been accessed through GPU commands */
258+
/* This reg requires save & restore during host PM suspend/resume */
259+
#define F_PM_SAVE (1 << 5)
260+
/* This reg could be accessed by unaligned address */
259261
#define F_UNALIGN (1 << 6)
260262
/* This reg is in GVT's mmio save-restor list and in hardware
261263
* logical context image
@@ -685,6 +687,7 @@ void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
685687
void intel_gvt_debugfs_init(struct intel_gvt *gvt);
686688
void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
687689

690+
int intel_gvt_pm_resume(struct intel_gvt *gvt);
688691

689692
#include "trace.h"
690693
#include "mpt.h"

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