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// ===----------------------------------------------------------------------===//
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#include " Common/CodeGenTarget.h"
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+ #include " llvm/Support/FormatVariadic.h"
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#include " llvm/Support/InterleavedRange.h"
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#include " llvm/TableGen/Error.h"
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#include " llvm/TableGen/Record.h"
@@ -126,6 +127,56 @@ void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
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void CallingConvEmitter::emitAction (const Record *Action, indent Indent,
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raw_ostream &O) {
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+
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+ auto EmitRegList = [&](const ListInit *RL, const StringRef RLName) {
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+ O << Indent << " static const MCPhysReg " << RLName << " [] = {\n " ;
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+ O << Indent << " " ;
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+ ListSeparator LS;
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+ for (const Init *V : RL->getValues ())
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+ O << LS << getQualifiedName (cast<DefInit>(V)->getDef ());
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+ O << " \n " << Indent << " };\n " ;
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+ };
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+
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+ auto EmitAllocateReg = [&](ArrayRef<const ListInit *> RegLists,
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+ ArrayRef<std::string> RLNames) {
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+ SmallVector<std::string> Parms;
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+ if (RegLists[0 ]->size () == 1 ) {
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+ for (const ListInit *LI : RegLists)
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+ Parms.push_back (getQualifiedName (LI->getElementAsRecord (0 )));
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+ } else {
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+ for (const std::string &S : RLNames)
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+ Parms.push_back (S + utostr (++Counter));
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+ for (const auto [Idx, LI] : enumerate(RegLists))
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+ EmitRegList (LI, Parms[Idx]);
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+ }
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+ O << formatv (" {0}if (MCRegister Reg = State.AllocateReg({1})) {{\n " , Indent,
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+ make_range (Parms.begin (), Parms.end ()));
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+ O << Indent << " State.addLoc(CCValAssign::getReg(ValNo, ValVT, "
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+ << " Reg, LocVT, LocInfo));\n " ;
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+ };
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+
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+ auto EmitAllocateStack = [&](bool EmitOffset = false ) {
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+ int Size = Action->getValueAsInt (" Size" );
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+ int Align = Action->getValueAsInt (" Align" );
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+ if (EmitOffset)
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+ O << Indent << " int64_t Offset" << ++Counter << " = " ;
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+ else
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+ O << Indent << " (void)" ;
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+ O << " State.AllocateStack(" ;
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+
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+ const char *Fmt = " State.getMachineFunction().getDataLayout()."
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+ " {0}(EVT(LocVT).getTypeForEVT(State.getContext()))" ;
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+ if (Size)
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+ O << Size << " , " ;
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+ else
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+ O << " \n " << Indent << formatv (Fmt, " getTypeAllocSize" ) << " , " ;
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+ if (Align)
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+ O << " Align(" << Align << " )" ;
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+ else
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+ O << " \n " << Indent << formatv (Fmt, " getABITypeAlign" );
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+ O << " );\n " ;
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+ };
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+
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if (Action->isSubClassOf (" CCPredicateAction" )) {
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O << Indent << " if (" ;
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@@ -158,55 +209,18 @@ void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
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} else if (Action->isSubClassOf (" CCAssignToReg" ) ||
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Action->isSubClassOf (" CCAssignToRegAndStack" )) {
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const ListInit *RegList = Action->getValueAsListInit (" RegList" );
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- if (RegList->size () == 1 ) {
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- std::string Name = getQualifiedName (RegList->getElementAsRecord (0 ));
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- O << Indent << " if (MCRegister Reg = State.AllocateReg(" << Name
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- << " )) {\n " ;
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+ for (unsigned I = 0 , E = RegList->size (); I != E; ++I) {
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+ std::string Name = getQualifiedName (RegList->getElementAsRecord (I));
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if (SwiftAction)
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AssignedSwiftRegsMap[CurrentAction].insert (std::move (Name));
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else
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AssignedRegsMap[CurrentAction].insert (std::move (Name));
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- } else {
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- O << Indent << " static const MCPhysReg RegList" << ++Counter
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- << " [] = {\n " ;
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- O << Indent << " " ;
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- ListSeparator LS;
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- for (unsigned I = 0 , E = RegList->size (); I != E; ++I) {
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- std::string Name = getQualifiedName (RegList->getElementAsRecord (I));
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- if (SwiftAction)
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- AssignedSwiftRegsMap[CurrentAction].insert (Name);
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- else
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- AssignedRegsMap[CurrentAction].insert (Name);
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- O << LS << Name;
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- }
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- O << " \n " << Indent << " };\n " ;
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- O << Indent << " if (MCRegister Reg = State.AllocateReg(RegList"
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- << Counter << " )) {\n " ;
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- }
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- O << Indent << " State.addLoc(CCValAssign::getReg(ValNo, ValVT, "
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- << " Reg, LocVT, LocInfo));\n " ;
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- if (Action->isSubClassOf (" CCAssignToRegAndStack" )) {
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- int Size = Action->getValueAsInt (" Size" );
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- int Align = Action->getValueAsInt (" Align" );
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- O << Indent << " (void)State.AllocateStack(" ;
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- if (Size)
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- O << Size << " , " ;
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- else
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- O << " \n "
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- << Indent
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- << " State.getMachineFunction().getDataLayout()."
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- " getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),"
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- " " ;
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- if (Align)
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- O << " Align(" << Align << " )" ;
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- else
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- O << " \n "
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- << Indent
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- << " State.getMachineFunction().getDataLayout()."
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- " getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()"
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- " ))" ;
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- O << " );\n " ;
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}
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+ EmitAllocateReg ({RegList}, {" RegList" });
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+
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+ if (Action->isSubClassOf (" CCAssignToRegAndStack" ))
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+ EmitAllocateStack ();
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+
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O << Indent << " return false;\n " ;
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O << Indent << " }\n " ;
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} else if (Action->isSubClassOf (" CCAssignToRegWithShadow" )) {
@@ -217,62 +231,13 @@ void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
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PrintFatalError (Action->getLoc (),
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" Invalid length of list of shadowed registers" );
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- if (RegList->size () == 1 ) {
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- O << Indent << " if (MCRegister Reg = State.AllocateReg(" ;
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- O << getQualifiedName (RegList->getElementAsRecord (0 ));
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- O << " , " << getQualifiedName (ShadowRegList->getElementAsRecord (0 ));
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- O << " )) {\n " ;
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- } else {
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- unsigned RegListNumber = ++Counter;
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- unsigned ShadowRegListNumber = ++Counter;
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-
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- O << Indent << " static const MCPhysReg RegList" << RegListNumber
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- << " [] = {\n " ;
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- O << Indent << " " ;
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- ListSeparator LS;
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- for (unsigned I = 0 , E = RegList->size (); I != E; ++I)
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- O << LS << getQualifiedName (RegList->getElementAsRecord (I));
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- O << " \n " << Indent << " };\n " ;
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-
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- O << Indent << " static const MCPhysReg RegList" << ShadowRegListNumber
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- << " [] = {\n " ;
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- O << Indent << " " ;
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- ListSeparator LSS;
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- for (unsigned I = 0 , E = ShadowRegList->size (); I != E; ++I)
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- O << LSS << getQualifiedName (ShadowRegList->getElementAsRecord (I));
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- O << " \n " << Indent << " };\n " ;
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-
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- O << Indent << " if (MCRegister Reg = State.AllocateReg(RegList"
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- << RegListNumber << " , "
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- << " RegList" << ShadowRegListNumber << " )) {\n " ;
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- }
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- O << Indent << " State.addLoc(CCValAssign::getReg(ValNo, ValVT, "
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- << " Reg, LocVT, LocInfo));\n " ;
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+ EmitAllocateReg ({RegList, ShadowRegList}, {" RegList" , " RegList" });
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+
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O << Indent << " return false;\n " ;
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O << Indent << " }\n " ;
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} else if (Action->isSubClassOf (" CCAssignToStack" )) {
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- int Size = Action->getValueAsInt (" Size" );
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- int Align = Action->getValueAsInt (" Align" );
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-
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- O << Indent << " int64_t Offset" << ++Counter << " = State.AllocateStack(" ;
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- if (Size)
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- O << Size << " , " ;
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- else
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- O << " \n "
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- << Indent
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- << " State.getMachineFunction().getDataLayout()."
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- " getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())),"
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- " " ;
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- if (Align)
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- O << " Align(" << Align << " )" ;
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- else
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- O << " \n "
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- << Indent
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- << " State.getMachineFunction().getDataLayout()."
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- " getABITypeAlign(EVT(LocVT).getTypeForEVT(State.getContext()"
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- " ))" ;
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- O << " );\n "
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- << Indent << " State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset"
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+ EmitAllocateStack (/* EmitOffset=*/ true );
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+ O << Indent << " State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset"
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<< Counter << " , LocVT, LocInfo));\n " ;
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O << Indent << " return false;\n " ;
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} else if (Action->isSubClassOf (" CCAssignToStackWithShadow" )) {
@@ -282,14 +247,7 @@ void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
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Action->getValueAsListInit (" ShadowRegList" );
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unsigned ShadowRegListNumber = ++Counter;
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-
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- O << Indent << " static const MCPhysReg ShadowRegList"
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- << ShadowRegListNumber << " [] = {\n " ;
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- O << Indent << " " ;
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- ListSeparator LS;
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- for (unsigned I = 0 , E = ShadowRegList->size (); I != E; ++I)
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- O << LS << getQualifiedName (ShadowRegList->getElementAsRecord (I));
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- O << " \n " << Indent << " };\n " ;
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+ EmitRegList (ShadowRegList, " ShadowRegList" + utostr (ShadowRegListNumber));
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O << Indent << " int64_t Offset" << ++Counter << " = State.AllocateStack("
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<< Size << " , Align(" << Align << " ), "
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