riscv: andes: trigger_module: Add Andes trigge moduler support for ptrace single-step (torvalds#198)

Reformed from the following patches on ast-v5_4_0-branch:
- (7fca221)	riscv: andes: fix make failure with riscv generic defconfig (torvalds#206)

Signed-off-by: charles <dminus@andestech.com>
Reviewed-on: https://gitea.andestech.com/RD-SW/linux/pulls/198
Reviewed-by: Tim Shih-Ting OuYang <tim609@andestech.com>
Reviewed-by: Ben Zong-You Xie <ben717@andestech.com>
Co-authored-by: charles <dminus@andestech.com>
Co-committed-by: charles <dminus@andestech.com>

Author: CharlesWu465

arch/riscv/include/asm/entry-common.h

@@ -6,6 +6,8 @@
 #include <asm/stacktrace.h>
 #include <asm/thread_info.h>
 #include <asm/vector.h>
+#include <linux/soc/andes/csr.h>
+#include <linux/soc/andes/trigger_module.h>
 
 static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
 						  unsigned long ti_work)
@@ -39,4 +41,19 @@ static inline int handle_misaligned_store(struct pt_regs *regs)
 }
 #endif
 
+#ifdef CONFIG_ARCH_ANDES
+static __always_inline void arch_exit_to_user_mode_work(struct pt_regs *regs,
+							unsigned long ti_work)
+{
+	if (static_branch_unlikely(&trigger_module_single_step_key)) {
+		if (ti_work & _TIF_SINGLESTEP) {
+			sbi_andes_set_trigger(TRIGGER_TYPE_ICOUNT, ICOUNT, 1);
+			csr_write(CSR_SCONTEXT, 1);
+		} else {
+			csr_write(CSR_SCONTEXT, 0);
+		}
+	}
+}
+#define arch_exit_to_user_mode_work arch_exit_to_user_mode_work
+#endif /* CONFIG_ARCH_ANDES */
 #endif /* _ASM_RISCV_ENTRY_COMMON_H */

arch/riscv/include/asm/ptrace.h

@@ -67,6 +67,11 @@ struct pt_regs {
 #define REG_FMT "%08lx"
 #endif
 
+#ifdef CONFIG_ARCH_ANDES
+/* Andes use trigger module to implement the ptrace single step. */
+#define arch_has_single_step() (1)
+#endif
+
 #define user_mode(regs) (((regs)->status & SR_PP) == 0)
 
 #define MAX_REG_OFFSET offsetof(struct pt_regs, orig_a0)

arch/riscv/include/asm/thread_info.h

@@ -112,6 +112,7 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 #define TIF_NEED_RESCHED	3	/* rescheduling necessary */
 #define TIF_RESTORE_SIGMASK	4	/* restore signal mask in do_signal() */
 #define TIF_MEMDIE		5	/* is terminating due to OOM killer */
+#define TIF_SINGLESTEP		6	/* Andes trigger module support ptrace single step */
 #define TIF_NOTIFY_SIGNAL	9	/* signal notifications exist */
 #define TIF_UPROBE		10	/* uprobe breakpoint or singlestep */
 #define TIF_32BIT		11	/* compat-mode 32bit process */
@@ -123,5 +124,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 #define _TIF_NOTIFY_SIGNAL	(1 << TIF_NOTIFY_SIGNAL)
 #define _TIF_UPROBE		(1 << TIF_UPROBE)
 #define _TIF_RISCV_V_DEFER_RESTORE	(1 << TIF_RISCV_V_DEFER_RESTORE)
+#define _TIF_SINGLESTEP		(1 << TIF_SINGLESTEP)
 
 #endif /* _ASM_RISCV_THREAD_INFO_H */

drivers/soc/andes/Makefile

@@ -4,5 +4,6 @@
 obj-y	+= andes_sbi.o
 obj-y	+= inject_init.o
 obj-y	+= dcause.o
+obj-y	+= trigger_module.o
 obj-$(CONFIG_ANDES_PPMA)	+= ppma.o
 obj-$(CONFIG_ANDES_ATCSMU)	+= atcsmu.o

drivers/soc/andes/andes_sbi.c

@@ -47,3 +47,11 @@ long sbi_andes_read_powerbrake(void)
 	return ret.value;
 }
 EXPORT_SYMBOL(sbi_andes_read_powerbrake);
+
+/* trigger module support debug application with gdbserver */
+void sbi_andes_set_trigger(unsigned int type, uintptr_t data, int enable)
+{
+	sbi_ecall(ANDES_SBI_EXT_ANDES, SBI_EXT_ANDES_TRIGGER_SET,
+		  type, data, enable, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_andes_set_trigger);

drivers/soc/andes/trigger_module.c

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 Andes Technology Corporation.
+ */
+#include <asm/cacheflush.h>
+#include <linux/soc/andes/csr.h>
+#include <linux/soc/andes/trigger_module.h>
+
+DEFINE_STATIC_KEY_FALSE(trigger_module_single_step_key);
+
+void user_enable_single_step(struct task_struct *child)
+{
+	if (static_branch_unlikely(&trigger_module_single_step_key)) {
+		if (!test_tsk_thread_flag(child, TIF_SINGLESTEP))
+			static_branch_disable(&trigger_module_single_step_key);
+	} else {
+		static_branch_enable(&trigger_module_single_step_key);
+	}
+
+	set_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+void user_disable_single_step(struct task_struct *child)
+{
+	if (static_branch_unlikely(&trigger_module_single_step_key) &&
+	    test_tsk_thread_flag(child, TIF_SINGLESTEP))
+		clear_tsk_thread_flag(child, TIF_SINGLESTEP);
+}

include/linux/soc/andes/sbi.h

@@ -50,4 +50,13 @@ long sbi_andes_probe_ppma(void);
 void sbi_andes_write_powerbrake(unsigned int val);
 long sbi_andes_read_powerbrake(void);
 
+#ifdef CONFIG_ARCH_ANDES
+/* Trigger module support debug application with gdbserver */
+void sbi_andes_set_trigger(unsigned int type, uintptr_t data, int enable);
+#else
+static inline void sbi_andes_set_trigger(unsigned int type,
+					 uintptr_t data,
+					 int enable) {}
+#endif /* !CONFIG_ARCH_ANDES */
+
 #endif /* !__LINUX_SOC_ANDES_SBI_H */

include/linux/soc/andes/trigger_module.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation.
+ */
+
+#ifndef __LINUX_SOC_ANDES_TRIGGER_MODULE_H
+#define __LINUX_SOC_ANDES_TRIGGER_MODULE_H
+
+#include <linux/soc/andes/sbi.h>
+
+#define TRIGGER_TYPE_ICOUNT 3
+#define ICOUNT 1
+
+DECLARE_STATIC_KEY_FALSE(trigger_module_single_step_key);
+
+void user_enable_single_step(struct task_struct *);
+void user_disable_single_step(struct task_struct *);
+
+#endif /* !__LINUX_SOC_ANDES_TRIGGER_MODULE_H */