irq_handler: Initial commit (#176)

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

Author: IstvanZsSzekely

library/includes/Makeinclude_common.mk

@@ -6,16 +6,22 @@
 include $(ADI_TB_DIR)/library/includes/Makeinclude_axi.mk
 
 # All test-bench dependencies except test programs
+
 SV_DEPS += $(ADI_TB_DIR)/library/utilities/utils.svh
 SV_DEPS += $(ADI_TB_DIR)/library/utilities/logger_pkg.sv
 SV_DEPS += $(ADI_TB_DIR)/library/utilities/adi_common_pkg.sv
 SV_DEPS += $(ADI_TB_DIR)/library/utilities/adi_vip_pkg.sv
 SV_DEPS += $(ADI_TB_DIR)/library/utilities/adi_environment_pkg.sv
 SV_DEPS += $(ADI_TB_DIR)/library/utilities/test_harness_env.sv
 SV_DEPS += $(ADI_TB_DIR)/library/drivers/common/watchdog.sv
+SV_DEPS += $(ADI_TB_DIR)/library/utilities/adi_api_pkg.sv
+SV_DEPS += $(ADI_TB_DIR)/library/utilities/irq_handler_pkg.sv
+SV_DEPS += $(ADI_TB_DIR)/library/vip/adi/io_vip/io_vip_if_base_pkg.sv
 
 SV_DEPS += system_tb.sv
 
+SIM_LIB_DEPS += io_vip
+
 ENV_DEPS += system_project.tcl
 ENV_DEPS += system_bd.tcl
 ENV_DEPS += $(ADI_TB_DIR)/scripts/adi_sim.tcl

library/includes/sp_include_common.tcl

@@ -41,8 +41,11 @@ adi_sim_project_files [list \
   "$ad_tb_dir/library/utilities/logger_pkg.sv" \
   "$ad_tb_dir/library/utilities/adi_common_pkg.sv" \
   "$ad_tb_dir/library/utilities/adi_vip_pkg.sv" \
+  "$ad_tb_dir/library/utilities/adi_api_pkg.sv" \
   "$ad_tb_dir/library/utilities/adi_environment_pkg.sv" \
   "$ad_tb_dir/library/utilities/test_harness_env.sv" \
+  "$ad_tb_dir/library/utilities/irq_handler_pkg.sv" \
   "$ad_tb_dir/library/drivers/common/watchdog.sv" \
+  "$ad_tb_dir/library/vip/adi/io_vip/io_vip_if_base_pkg.sv" \
   "system_tb.sv" \
 ]

library/utilities/adi_api_pkg.sv

@@ -72,24 +72,27 @@ package adi_api_pkg;
     endtask
 
     task axi_read(
-      input  [31:0] addr,
-      output [31:0] data);
+      input  bit [31:0] addr,
+      output bit [31:0] data,
+      input bit priority_packet = 0);
 
-      this.bus.RegRead32(this.base_address + addr, data);
+      this.bus.RegRead32(this.base_address + addr, data, priority_packet);
     endtask: axi_read
 
     task axi_write(
-      input [31:0] addr,
-      input [31:0] data);
+      input bit [31:0] addr,
+      input bit [31:0] data,
+      input bit priority_packet = 0);
 
-      this.bus.RegWrite32(this.base_address + addr, data);
+      this.bus.RegWrite32(this.base_address + addr, data, priority_packet);
     endtask: axi_write
 
     task axi_verify(
-      input [31:0] addr,
-      input [31:0] data);
+      input bit [31:0] addr,
+      input bit [31:0] data,
+      input bit priority_packet = 0);
 
-      this.bus.RegReadVerify32(this.base_address + addr, data);
+      this.bus.RegReadVerify32(this.base_address + addr, data, priority_packet);
     endtask: axi_verify
 
   endclass: adi_api

library/utilities/irq_handler_pkg.sv

@@ -0,0 +1,143 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`include "utils.svh"
+
+package irq_handler_pkg;
+
+  import logger_pkg::*;
+  import adi_common_pkg::*;
+  import adi_api_pkg::*;
+  import m_axi_sequencer_pkg::*;
+  import io_vip_if_base_pkg::*;
+  
+  class irq_handler_class extends adi_api;
+
+    protected io_vip_if_base irq_vip_if;
+
+    protected event irq_event_list [31:0];
+    protected bit [31:0] irq_valid_list;
+
+    protected bit software_testing;
+  
+    // constructor
+    function new(
+      input string name,
+      input m_axi_sequencer_base bus,
+      input bit [31:0] base_address,
+      input io_vip_if_base irq_vip_if,
+      input adi_component parent = null);
+      
+      super.new(name, bus, base_address, parent);
+
+      this.irq_vip_if = irq_vip_if;
+      this.irq_valid_list = 'h0;
+      this.software_testing = 1'b0;
+    endfunction: new
+
+    // enable software testing at startup
+    function void enable_software_testing();
+      this.software_testing = 1'b1;
+    endfunction: enable_software_testing
+
+    // software IRQ test-phase
+    task software_irq_testing();
+      logic [31:0] enable_irq = 'h0;
+
+      for (int i=0; i<32; ++i) begin
+        enable_irq = enable_irq | (this.irq_valid_list[i] << i);
+      end
+      this.info($sformatf("Enables: %d", enable_irq), ADI_VERBOSITY_HIGH);
+      this.axi_write('h00, enable_irq, 1); // software trigger IRQ
+
+      // negative edge detection
+      if (this.irq_vip_if.get_io() == 1'b0) begin
+        this.irq_vip_if.wait_io_change();
+      end
+      this.irq_vip_if.wait_io_change();
+    endtask: software_irq_testing
+
+    // IRQ event handler
+    task start();
+      logic [31:0] irq_triggered;
+      logic [31:0] enable_irq = 'h0;
+
+      for (int i=0; i<32; ++i) begin
+        enable_irq = enable_irq | (this.irq_valid_list[i] << i);
+      end
+
+      this.axi_write('h10, enable_irq, 1); // enable all IRQ handles
+      this.axi_write('h1C, 'b01, 1); // enable IRQ controller / software interrupt disabled
+
+      fork forever begin
+        if (this.irq_vip_if.get_io() == 1'b0) begin
+          this.irq_vip_if.wait_io_change();
+        end
+
+        this.info($sformatf("IRQ controller triggered"), ADI_VERBOSITY_HIGH);
+
+        this.axi_read('h04, irq_triggered, 1); // check pending IRQ (status + enable)
+
+        for (int i=0; i<32; ++i) begin
+          if (irq_triggered[i]) begin
+            if (this.irq_valid_list[i] == 1'b0) begin
+              this.fatal($sformatf("IRQ triggered on a non-registered device!"));
+            end
+            ->this.irq_event_list[i];
+            @(this.irq_event_list[i]);
+            this.axi_write('h0C, 'h1 << i, 1); // acknowledge IRQ
+          end
+        end
+      end join_none
+
+      if (this.software_testing) begin
+        this.software_irq_testing();
+      end
+
+      this.axi_write('h1C, 'b11, 1); // enable IRQ controller + software interrupt enabled
+    endtask: start
+
+    // register IRQ device
+    function event register_device(input int position);
+      if (this.irq_valid_list[position]) begin
+        this.fatal($sformatf("An interrupt handler is already assigned to position %0d!", position));
+      end
+      this.irq_valid_list[position] = 1'b1;
+      return this.irq_event_list[position];
+    endfunction: register_device
+
+  endclass: irq_handler_class
+
+endpackage: irq_handler_pkg

library/utilities/test_harness_env.sv

@@ -42,13 +42,17 @@ package test_harness_env_pkg;
   import adi_environment_pkg::*;
   import adi_axi_agent_pkg::*;
   import watchdog_pkg::*;
+  import irq_handler_pkg::*;
+  import io_vip_if_base_pkg::*;
+  import vip_agent_typedef_pkg::*;
 
-
-  class test_harness_env #(`AXI_VIP_PARAM_DECL(mng), `AXI_VIP_PARAM_DECL(ddr)) extends adi_environment;
+  class test_harness_env extends adi_environment;
 
     // Agents
-    adi_axi_master_agent #(`AXI_VIP_PARAM_ORDER(mng)) mng;
-    adi_axi_slave_mem_agent #(`AXI_VIP_PARAM_ORDER(ddr)) ddr;
+    adi_axi_agent_base mng;
+    adi_axi_agent_base ddr;
+
+    irq_handler_class irq_handler;
 
     virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if;
     virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if;
@@ -58,22 +62,23 @@ package test_harness_env_pkg;
 
     watchdog simulation_watchdog;
 
+    local bit [31:0] irq_base_address;
+    local io_vip_if_base irq_vip_if;
+
     //============================================================================
     // Constructor
     //============================================================================
     function new(
       input string name,
+      input virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if,
+      input virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if,
+      input virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if,
+      input virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if,
+      input bit [31:0] irq_base_address,
+      input io_vip_if_base irq_vip_if,
+      input adi_environment parent = null);
 
-      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if,
-      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if,
-      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if,
-
-      virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if,
-
-      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(mng)) mng_vip_if,
-      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(ddr)) ddr_vip_if);
-
-      super.new(name);
+      super.new(name, parent);
 
       this.simulation_watchdog = new("Simulation watchdog", 10**6, "Simulation might be hanging!");
 
@@ -82,9 +87,12 @@ package test_harness_env_pkg;
       this.ddr_clk_vip_if = ddr_clk_vip_if;
       this.sys_rst_vip_if = sys_rst_vip_if;
 
+      this.irq_base_address = irq_base_address;
+      this.irq_vip_if = irq_vip_if;
+
       // Creating the agents
-      this.mng = new("AXI Manager agent", mng_vip_if, this);
-      this.ddr = new("AXI DDR stub agent", ddr_vip_if, this);
+      this.mng = new("AXI Manager agent", MASTER, this);
+      this.ddr = new("AXI DDR stub agent", SLAVE, this);
     endfunction
 
     //============================================================================
@@ -93,14 +101,16 @@ package test_harness_env_pkg;
     //   - Start the agents
     //============================================================================
     task start();
-      this.simulation_watchdog.start();
+      this.irq_handler = new("IRQ handler", this.mng.master_sequencer, this.irq_base_address, this.irq_vip_if, this);
 
-      this.mng.start_master();
-      this.ddr.start_slave();
+      this.simulation_watchdog.start();
 
       this.sys_clk_vip_if.start_clock();
       this.dma_clk_vip_if.start_clock();
       this.ddr_clk_vip_if.start_clock();
+
+      this.mng.start_master();
+      this.ddr.start_slave();
     endtask
 
     //============================================================================

library/utilities/test_harness_system_bd.tcl

@@ -49,6 +49,13 @@ ad_ip_instance axi_intc axi_intc [list \
   C_HAS_FAST 0 \
 ]
 
+# create IRQ VIP
+ad_ip_instance io_vip irq_vip [ list \
+  ASYNC {true} \
+  MODE {0} \
+]
+adi_sim_add_define "IRQ=irq_vip"
+
 ad_ip_instance xlconcat sys_concat_intc
 ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
 
@@ -63,7 +70,6 @@ ad_ip_instance clk_vip sys_clk_vip [ list \
 ]
 adi_sim_add_define "SYS_CLK=sys_clk_vip"
 
-
 # DMA clock
 ad_ip_instance clk_vip dma_clk_vip [ list \
   INTERFACE_MODE {MASTER} \
@@ -160,7 +166,9 @@ ad_connect sys_concat_intc/In15   GND
 
 # interconnect - processor
 
-ad_cpu_interconnect 0x41200000 axi_intc
+set IRQ_C_BASE 0x41200000
+ad_cpu_interconnect $IRQ_C_BASE axi_intc
+adi_sim_add_define "IRQ_C_BA=[format "%d" ${IRQ_C_BASE}]"
 
 # interconnect - memory
 
@@ -189,10 +197,8 @@ incr sys_cpu_interconnect_index
 global sys_mem_interconnect_index
 incr sys_mem_interconnect_index
 
-# create external port for IRQ
-create_bd_port -dir O -type intr irq
-
-ad_connect irq axi_intc/irq
+# connect the IRQ controller to the IRQ VIP
+ad_connect axi_intc/irq irq_vip/i
 
 # Set DDR VIP to a range of 2G
 set DDR_BASE 0x80000000

library/vip/adi/io_vip/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (C) 2018-2024 Analog Devices, Inc.
+## Copyright (C) 2018-2025 Analog Devices, Inc.
 ## Auto-generated, do not modify!
 ####################################################################################
 
@@ -9,9 +9,10 @@ include ../../../../scripts/make_tb_path.mk
 LIBRARY_NAME := io_vip
 
 GENERIC_DEPS += io_vip.sv
+GENERIC_DEPS += io_vip_top.v
 GENERIC_DEPS += io_vip_if.sv
+GENERIC_DEPS += io_vip_if_base_pkg.sv
 
 XILINX_DEPS += io_vip_ip.tcl
-XILINX_DEPS += io_vip_pkg.ttcl
 
 include $(ADI_HDL_DIR)/library//scripts/library.mk