General updates (#165)

* General updates

- Added/Updated licensce headers
- Updated testbench dependencies
- Updated class hierarchy
- Updated VIP clocking and reset calls
- Change while(1) calls to forever
- Remove trailing spaces and tabs

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

* SPI VIP: Updated to use class-based interface as proxy

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

* library/drivers/jesd/adi_jesd204_pkg: Added a TODO

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

* hbm: Removed testing of empty simulation

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

---------

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

Author: IstvanZsSzekely

README.md

@@ -17,27 +17,27 @@
 
 This repository contains testbenches and verification components for system level projects or components connected at block level from the [hdl](https://github.com/analogdevicesinc/hdl) repository.
 
-This repository is not a stand alone one. It must be cloned or linked as a submodule inside the [hdl](https://github.com/analogdevicesinc/hdl) repository you want to test. 
+This repository is not a stand alone one. It must be cloned or linked as a submodule inside the [hdl](https://github.com/analogdevicesinc/hdl) repository you want to test.
 
 The folder structure of the hdl will look as follows:
 
 hdl
   - projects
   - library
   - testbenches
-  
+
 ## Setup
-The testbenches are built around Xilinx verification IPs so it requires Vivado to be set up according to the hdl repository requirenments. 
+The testbenches are built around Xilinx verification IPs so it requires Vivado to be set up according to the hdl repository requirenments.
 Running the testbenches relies on the build mechanism from the hdl repository,  make sure you have a proper setup for Xilinx flow described [here](https://wiki.analog.com/resources/fpga/docs/build)
 
 ## Running a testbench:
 
-Change the workig directory to the testbench you want to run: 
+Change the workig directory to the testbench you want to run:
 
 	cd testbenches/fmcomms2
 
-The scripts first will build all components used from the hdl library, build the block design environment based on a configuration file that describes parameters of under test block, then will actually run the test. 
-These steps are separated in ordrer to be able to run multiple tests on the same configuration without rebuilding the block desing every time. 
+The scripts first will build all components used from the hdl library, build the block design environment based on a configuration file that describes parameters of under test block, then will actually run the test.
+These steps are separated in ordrer to be able to run multiple tests on the same configuration without rebuilding the block desing every time.
 
 ### Run all tests in batch mode:
 

docs/library/drivers/common/watchdog/index.rst

@@ -103,6 +103,6 @@ Other use-cases for the watchdog timer:
   system hanging. In this case it is more advisable have a watchdog timer
   stopped and started or reset each time a repetitive task is completed. This
   allows for a stricter watchdog timer value, which may stop a hanging
-  simulation sooner without waiting for the whole process to finish. 
+  simulation sooner without waiting for the whole process to finish.
 
 .. include:: ../../../../common/support.rst

docs/library/index.rst

@@ -2,7 +2,7 @@
 
 Library
 ===============================================================================
-  
+
 Drivers
 -------------------------------------------------------------------------------
 
@@ -34,4 +34,4 @@ VIPs
    :maxdepth: 1
 
    vip/index
-   
+

docs/library/vip/amd/axi_vip/adi_axi_agent.rst

@@ -6,7 +6,7 @@ ADI AXI Agent (VIP)
 Overview
 -------------------------------------------------------------------------------
 
-The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added 
+The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added
 sequencer, monitor and wrapper class. Has a master, slave and passthrough
 variant. Provides functions to start, stop and run the classes within. Its
 purpose is to create and contain everything under a single construct and not

docs/library/vip/amd/axi_vip/index.rst

@@ -14,7 +14,7 @@ Xilinx AXI Verification IP (VIP)
 Overview
 -------------------------------------------------------------------------------
 
-The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added 
+The ADI AXI Agent uses the AMD (Xilinx) AXI VIP at its core with added
 sequencer, monitor and wrapper class.
 `[1] <https://docs.amd.com/r/en-US/pg267-axi-vip>`__
 

docs/library/vip/amd/axis_vip/adi_axis_agent.rst

@@ -6,7 +6,7 @@ ADI AXIS Agent (VIP)
 Overview
 -------------------------------------------------------------------------------
 
-The ADI AXIS Agent uses the AMD (Xilinx) AXIS VIP at its core with added 
+The ADI AXIS Agent uses the AMD (Xilinx) AXIS VIP at its core with added
 sequencer, monitor and wrapper class. Has a master, slave and passthrough
 variant. Provides functions to start, stop and run the classes within. Its
 purpose is to create and contain everything under a single construct and not

docs/library/vip/amd/axis_vip/index.rst

@@ -14,7 +14,7 @@ Xilinx AXIS Stream Verification IP (VIP)
 Overview
 --------------------------------------------------------------------------------
 
-The ADI AXIS Agent VIP uses the AMD (Xilinx) AXIS VIP at its core with added 
+The ADI AXIS Agent VIP uses the AMD (Xilinx) AXIS VIP at its core with added
 sequencer, monitor and wrapper class.
 `[1] <https://docs.amd.com/v/u/en-US/pg277-axi4stream-vip>`__
 

docs/testbenches/common/dependency_common.rst

@@ -3,7 +3,7 @@ Common with most testbenches:
 .. list-table::
    :widths: 30 45 25
    :header-rows: 1
-   
+
    * - SV dependency name
      - Source code link
      - Documentation link

docs/testbenches/ip_based/util_pack/index.rst

@@ -51,7 +51,7 @@ The following parameters of this project that can be configured:
 .. note::
 
    The max width is calculated with: CHANNELS*SAMPLES*WIDTH and it cannot
-   exceed 2048. 
+   exceed 2048.
 
 Build parameters
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

docs/testbenches/project_based/ad463x/index.rst

@@ -48,18 +48,18 @@ The following parameters of this project that can be configured:
 
 Build parameters
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- 
+
 The parameters mentioned above can be configured when starting the build, like in
 the following example:
 
 .. shell::
    :showuser:
 
    $make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=1 DDR_EN=0
-   
+
 but we recommend using the already tested build configuration modes, that can be
 found in the ``cfg`` section.
- 
+
 Configuration files
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -167,7 +167,7 @@ Sanity test
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 This test is used to check the communication with the AXI REGMAP module of the
-AD463X SPI Engine interface, by reading the core VERSION register, along with 
+AD463X SPI Engine interface, by reading the core VERSION register, along with
 writing and reading the SCRATCH register.
 
 FIFO SPI test
@@ -322,7 +322,7 @@ Testbench specific dependencies:
 .. list-table::
    :widths: 30 45 25
    :header-rows: 1
-   
+
    * - SV dependency name
      - Source code link
      - Documentation link