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docs/cn0577: Add doc
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‎docs/testbenches/project_based/cn0577/index.rst‎

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.. _cn0577:
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CN0577
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================================================================================
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Overview
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-------------------------------------------------------------------------------
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The purpose of this testbench is to validate the of the
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:git-hdl:`projects/cn0577` reference design.
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The entire HDL documentation can be found here
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:external+hdl:ref:`CN0577 HDL project <cn0577>`.
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Block design
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-------------------------------------------------------------------------------
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The testbench block design includes part of the CN0577 HDL reference design,
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along with VIPs used for clocking, reset, PS and DDR simulations.
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagram:
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CN0577 parallel interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ./cn0577_tb.svg
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:width: 800
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:align: center
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:alt: CN0577/Testbench block diagram
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Configuration parameters and modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The following parameter of this project that can be configured:
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- TWOLANES: defines the device's number of data lanes:
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Options: 0 - One lane, 1 - Two lanes
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- ADC_RES: defines the device's resolution in bits:
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Options: 16 - 16 bits, 18 - 18 bits
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Configuration files
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following configuration files are available:
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+-----------------------+--------------------+
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| Configuration mode | Parameters |
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| +--------------------+
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| | TWOLANES | ADC_RES |
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+=======================+==========+=========+
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| cfg_1lane_16b | 0 | 16 |
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+-----------------------+----------+---------+
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| cfg_1lane_18b | 0 | 18 |
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+-----------------------+----------+---------+
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| cfg_2lanes_16b | 1 | 16 |
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+-----------------------+----------+---------+
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| cfg_2lanes_18b | 1 | 18 |
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+-----------------------+----------+---------+
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Tests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following test program files are available:
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============ =====================================
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Test program Usage
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============ =====================================
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test_program Tests the cn0577 design capabilities.
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============ =====================================
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Available configurations & tests combinations
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The above test program is compatible with all the configurations.
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CPU/Memory interconnect addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the CPU/Memory interconnect addresses used in this project:
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======================== ===========
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Instance Address
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======================== ===========
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axi_intc 0x4120_0000
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axi_ltc2387 0x44A0_0000
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axi_ltc2387_dma 0x44A3_0000
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axi_pwm_gen 0x44A6_0000
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ddr_axi_vip 0x8000_0000
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======================== ===========
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project:
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=============== ===
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Instance name HDL
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=============== ===
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axi_ltc2387_dma 13
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=============== ===
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Test stimulus
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-------------------------------------------------------------------------------
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Parallel test program
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The test program is structured into several tests as follows:
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Environment bringup
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The steps of the environment bringup are:
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* Create the environment
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* Start the environment
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* Start the clocks
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* Assert the resets
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Sanity tests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This set of sanity tests for the common ADC API, axi_dmac and axi_pwm_gen
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IPs verifies the *version* and *scratch* registers.
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Data acquisition test
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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* Enable all ADC channels
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* Configure the PWM generator (axi_pwmgen)
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* Configure the DMA
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* Configure the axi_ltc2387 IP
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* Submit a DMA transfer
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* Stop the PWM generator
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* Configure axi_ltc2387 IP
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* ADC common core out of reset
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* Set static data setup in device's reg 0x21
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* Read last config result
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* Send WR request
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* Read last config result
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* Set default control value (no RD/WR request)
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* Read last config result
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* Set exit from register mode sequence
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* Send WR request
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* Set default control value (no RD/WR request)
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* Set HDL config mode - default
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* Capture and compare the data
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Stop the environment
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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* Stop the clocks
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Building the testbench
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-------------------------------------------------------------------------------
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The testbench is built upon ADI's generic HDL reference design framework.
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ADI does not distribute compiled files of these projects so they must be built
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from the sources available :git-hdl:`here </>` and :git-testbenches:`here </>`,
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with the specified hierarchy described :ref:`build_tb set_up_tb_repo`.
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To get the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:.
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**Linux/Cygwin/WSL**
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*Example 1*
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Build all the possible combinations of tests and configurations, using only the
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command line.
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.. shell::
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:showuser:
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$cd testbenches/project/cn0577
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$make
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*Example 2*
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Build all the possible combinations of tests and configurations, using the
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Vivado GUI. This command will launch Vivado, will run the simulation and display
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the waveforms.
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.. shell::
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:showuser:
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$cd testbenches/project/cn0577
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$make MODE=gui
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*Example 3*
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Build a particular combination of test and configuration, using the Vivado GUI.
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This command will launch Vivado, will run the simulation and display the
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waveforms.
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.. shell::
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:showuser:
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$cd testbenches/project/cn0577
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$make MODE=gui CFG=cfg_2lanes_18b TST=test_program
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The built projects can be found in the ``runs`` folder, where each configuration
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specific build has it's own folder named after the configuration file's name.
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Example: if the following command was run for a single configuration in the
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clean folder (no runs folder available):
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``make CFG=cfg_2lanes_18b``
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Then the subfolder under ``runs`` name will be:
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``cfg_2lanes_18b``
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Resources
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-------------------------------------------------------------------------------
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HDL related dependencies forming the DUT
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 30 45 25
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_LTC2387
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- :git-hdl:`library/axi_ltc2387`
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- :external+hdl:ref:`axi_ltc2387`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac`
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- :external+hdl:ref:`axi_dmac`
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* - AXI_PWM_GEN
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- :git-hdl:`library/axi_pwm_gen`
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- :external+hdl:ref:`axi_pwm_gen`
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Testbenches related dependencies
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. include:: ../../common/dependency_common.rst
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Testbench specific dependencies:
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.. list-table::
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:widths: 30 45 25
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:header-rows: 1
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* - SV dependency name
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- Source code link
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- Documentation link
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* - ADC_API_PKG
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- :git-testbenches:`library/drivers/adc_api_pkg.sv`
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- ---
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* - AXI_VIP_PKG
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- ---
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- :ref:`xilinx_axi_vip`
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* - AXI4STREAM_VIP_PKG
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- ---
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- :xilinx:`AXI Stream Verification IP (VIP) <products/intellectual-property/axi-stream-vip.html>`
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* - COMMON_API_PKG
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- :git-testbenches:`library/drivers/common_api_pkg.sv`
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- ---
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* - DMA_TRANS
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- :git-testbenches:`library/drivers/dmac/dma_trans.sv`
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- ---
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* - DMAC_API
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- :git-testbenches:`library/drivers/dmac/dmac_api.sv`
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- :ref:`dmac`
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* - LOGGER_PKG
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- :git-testbenches:`library/utilities/logger_pkg.sv`
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- ---
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* - M_AXIS_SEQUENCER
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- :git-testbenches:`library/vip/amd/m_axis_sequencer.sv`
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- ---
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* - PWM_GEN_API_PKG
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- :git-testbenches:`library/drivers/pwm_gen_api_pkg.sv`
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- ---
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* - S_AXIS_SEQUENCER
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- :git-testbenches:`library/vip/amd/s_axis_sequencer.sv`
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- ---
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* - TEST_HARNESS_ENV_PKG
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- :git-testbenches:`library/utilities/test_harness_eng_pkg.sv`
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- :ref:`test_harness`
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.. include:: ../../../common/more_information.rst
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.. include:: ../../../common/support.rst

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