Minor updates

- Updated some classes to virtual
- Updated some virtual methods to pure virtual
- Updated naming scheme for some methods

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

Author: IstvanZsSzekely

library/vip/amd/axi/m_axi_sequencer.sv

@@ -43,7 +43,7 @@ package m_axi_sequencer_pkg;
   import adi_vip_pkg::*;
 
 
-  class m_axi_sequencer_base extends adi_sequencer;
+  virtual class m_axi_sequencer_base extends adi_sequencer;
 
     function new(
       input string name,
@@ -52,27 +52,18 @@ package m_axi_sequencer_pkg;
       super.new(name, parent);
     endfunction: new
 
-    virtual task automatic RegWrite32(
+    pure virtual task automatic RegWrite32(
       input xil_axi_ulong addr =0,
       input bit [31:0]    data);
 
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: RegWrite32
-
-    virtual task automatic RegRead32(
+    pure virtual task automatic RegRead32(
       input xil_axi_ulong  addr =0,
       output bit [31:0]    data);
 
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: RegRead32
-
-    virtual task automatic RegReadVerify32(
+    pure virtual task automatic RegReadVerify32(
       input xil_axi_ulong  addr =0,
       input bit [31:0]     data);
 
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: RegReadVerify32
-
   endclass: m_axi_sequencer_base
 
 

library/vip/amd/axi/s_axi_sequencer.sv

@@ -43,7 +43,7 @@ package s_axi_sequencer_pkg;
   import logger_pkg::*;
 
 
-  class s_axi_sequencer_base extends adi_sequencer;
+  virtual class s_axi_sequencer_base extends adi_sequencer;
 
     function new(
       input string name,
@@ -52,14 +52,12 @@ package s_axi_sequencer_pkg;
       super.new(name, parent);
     endfunction: new
 
-    virtual function logic [31:0] get_reg_data_from_mem(input xil_axi_ulong addr);
-    endfunction: get_reg_data_from_mem
+    pure virtual function logic [31:0] BackdoorRead32(input xil_axi_ulong addr);
 
-    virtual function void set_reg_data_in_mem(
+    pure virtual function void BackdoorWrite32(
       input xil_axi_ulong addr,
       input logic [31:0] data,
       input bit [3:0] strb);
-    endfunction: set_reg_data_in_mem
 
   endclass: s_axi_sequencer_base
 
@@ -78,11 +76,11 @@ package s_axi_sequencer_pkg;
       this.mem_model = mem_model;
     endfunction: new
 
-    virtual function logic [31:0] get_reg_data_from_mem(input xil_axi_ulong addr);
+    virtual function logic [31:0] BackdoorRead32(input xil_axi_ulong addr);
       return this.mem_model.backdoor_memory_read_4byte(addr);
-    endfunction: get_reg_data_from_mem
+    endfunction: BackdoorRead32
 
-    virtual function void set_reg_data_in_mem(
+    virtual function void BackdoorWrite32(
       input xil_axi_ulong addr,
       input logic [31:0] data,
       input bit [3:0] strb);
@@ -91,7 +89,7 @@ package s_axi_sequencer_pkg;
         .addr(addr),
         .payload(data),
         .strb(strb));
-    endfunction: set_reg_data_in_mem
+    endfunction: BackdoorWrite32
 
   endclass: s_axi_sequencer
 

library/vip/amd/axis/m_axis_sequencer.sv

@@ -57,7 +57,7 @@ package m_axis_sequencer_pkg;
   } stop_policy_t;
 
 
-  class m_axis_sequencer_base extends adi_sequencer;
+  virtual class m_axis_sequencer_base extends adi_sequencer;
 
     protected bit enabled;
     protected bit generator_running;
@@ -120,47 +120,30 @@ package m_axis_sequencer_pkg;
     endfunction: new
 
     // set vif proxy to drive outputs with 0 when inactive
-    virtual task set_inactive_drive_output_0();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: set_inactive_drive_output_0
+    pure virtual task set_inactive_drive_output_0();
 
     // check if ready is asserted
-    virtual function bit check_ready_asserted();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endfunction: check_ready_asserted
+    pure virtual function bit check_ready_asserted();
 
     // wait for set amount of clock cycles
-    virtual task wait_clk_count(input int wait_clocks);
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: wait_clk_count
+    pure virtual task wait_clk_count(input int wait_clocks);
 
     // pack the byte stream into transfers(beats) then in packets by setting the tlast
-    virtual protected task packetize();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: packetize
+    pure virtual protected task packetize();
 
-    virtual protected task sender();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: sender
+    pure virtual protected task sender();
 
     // create transfer based on data beats per packet
-    virtual function void add_xfer_descriptor_sample_count(
+    pure virtual function void add_xfer_descriptor_sample_count(
       input int data_beats_per_packet,
       input int gen_tlast = 1,
       input int gen_sync = 1);
 
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endfunction: add_xfer_descriptor_sample_count
-
     // wait until data beat is sent
-    virtual task beat_sent();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: beat_sent
+    pure virtual task beat_sent();
 
     // wait until packet is sent
-    virtual task packet_sent();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: packet_sent
+    pure virtual task packet_sent();
 
     // set disable policy
     function void set_stop_policy(input stop_policy_t stop_policy);

library/vip/amd/axis/s_axis_sequencer.sv

@@ -42,7 +42,7 @@ package s_axis_sequencer_pkg;
   import adi_vip_pkg::*;
   import logger_pkg::*;
 
-  class s_axis_sequencer_base extends adi_sequencer;
+  virtual class s_axis_sequencer_base extends adi_sequencer;
 
     protected xil_axi4stream_data_byte byte_stream [$];
     protected xil_axi4stream_ready_gen_policy_t mode;
@@ -130,13 +130,9 @@ package s_axis_sequencer_pkg;
     endfunction: set_low_time_range
 
     // virtual tasks to be implemented
-    virtual task start();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: start
+    pure virtual task start();
 
-    virtual task stop();
-      this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
-    endtask: stop
+    pure virtual task stop();
 
   endclass: s_axis_sequencer_base
 

testbenches/ip/data_offload/tests/test_program.sv

@@ -198,7 +198,7 @@ program test_program;
     input int byte_length);
     `INFO(("Initial address: %x", addr), ADI_VERBOSITY_LOW);
     for (int i=0; i<byte_length; i=i+8) begin
-      base_env.ddr.slave_sequencer.set_reg_data_in_mem(addr + i*8, i, 255);
+      base_env.ddr.slave_sequencer.BackdoorWrite32(addr + i*8, i, 255);
     end
     `INFO(("Final address: %x", addr + byte_length*8), ADI_VERBOSITY_LOW);
   endtask

testbenches/ip/dma_loopback/tests/test_program.sv

@@ -87,7 +87,7 @@ program test_program;
 
     // Init test data
     for (int i=0;i<2048*2 ;i=i+2) begin
-      base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
+      base_env.ddr.slave_sequencer.BackdoorWrite32(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
     end
 
     do_transfer(
@@ -159,8 +159,8 @@ program test_program;
     for (int i=0;i<length/4;i=i+4) begin
       current_src_address = src_addr+i;
       current_dest_address = dest_addr+i;
-      captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
-      reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
+      captured_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_dest_address);
+      reference_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_src_address);
 
       if (captured_word !== reference_word) begin
         `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

testbenches/ip/dma_sg/tests/test_program_1d.sv

@@ -88,7 +88,7 @@ program test_program_1d;
 
     // Init test data with incrementing 16-bit value from 0 up to address 'h8000
     for (int i=0;i<'h4000;i=i+2) begin
-      base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
+      base_env.ddr.slave_sequencer.BackdoorWrite32(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
     end
 
     // TX BLOCK
@@ -169,18 +169,18 @@ program test_program_1d;
                         bit [31:0] src_stride,
                         bit [31:0] dst_stride);
 
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h00, flags, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h04, id, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h08, dest_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h0C, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h10, src_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h14, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h18, next_desc_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h1C, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h20, y_len, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h24, x_len, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h28, src_stride, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h2C, dst_stride, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h00, flags, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h04, id, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h08, dest_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h0C, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h10, src_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h14, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h18, next_desc_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h1C, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h20, y_len, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h24, x_len, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h28, src_stride, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h2C, dst_stride, 'hF);
 
   endtask : write_descriptor
 
@@ -232,8 +232,8 @@ program test_program_1d;
     for (int i=0;i<length;i=i+4) begin
       current_src_address = src_addr+i;
       current_dest_address = dest_addr+i;
-      captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
-      reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
+      captured_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_dest_address);
+      reference_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_src_address);
 
       if (captured_word !== reference_word) begin
         `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

testbenches/ip/dma_sg/tests/test_program_2d.sv

@@ -91,13 +91,13 @@ program test_program_2d;
 
       // Incremental data
       for (int j=0;j<'h800;j=j+2) begin
-        base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+offset+j*2),(((j+1+'h1000*i)) << 16) | (j+'h1000*i) ,'hF);
+        base_env.ddr.slave_sequencer.BackdoorWrite32(xil_axi_uint'(`DDR_BA+offset+j*2),(((j+1+'h1000*i)) << 16) | (j+'h1000*i) ,'hF);
       end
       offset = offset + 'h1000;
 
       // Buffer filled with 0
       for (int k=0;k<'h80;k=k+1) begin
-        base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+offset+k*4), 32'h0,'hF);
+        base_env.ddr.slave_sequencer.BackdoorWrite32(xil_axi_uint'(`DDR_BA+offset+k*4), 32'h0,'hF);
       end
       offset = offset + 'h200;
 
@@ -163,18 +163,18 @@ program test_program_2d;
                         bit [31:0] src_stride,
                         bit [31:0] dst_stride);
 
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h00, flags, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h04, id, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h08, dest_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h0C, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h10, src_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h14, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h18, next_desc_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h1C, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h20, y_len, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h24, x_len, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h28, src_stride, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h2C, dst_stride, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h00, flags, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h04, id, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h08, dest_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h0C, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h10, src_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h14, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h18, next_desc_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h1C, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h20, y_len, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h24, x_len, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h28, src_stride, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h2C, dst_stride, 'hF);
 
   endtask : write_descriptor
 
@@ -226,8 +226,8 @@ program test_program_2d;
     for (int i=0;i<length;i=i+4) begin
       current_src_address = src_addr+i+(i/'h1000)*'h200;
       current_dest_address = dest_addr+i;
-      captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
-      reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
+      captured_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_dest_address);
+      reference_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_src_address);
 
       if (captured_word !== reference_word) begin
         `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

testbenches/ip/dma_sg/tests/test_program_tr_queue.sv

@@ -88,7 +88,7 @@ program test_program_tr_queue;
 
     // Init test data
     for (int i=0;i<'h4000;i=i+2) begin
-      base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
+      base_env.ddr.slave_sequencer.BackdoorWrite32(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
     end
 
     // TX BLOCK
@@ -175,18 +175,18 @@ program test_program_tr_queue;
                         bit [31:0] src_stride,
                         bit [31:0] dst_stride);
 
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h00, flags, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h04, id, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h08, dest_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h0C, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h10, src_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h14, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h18, next_desc_addr, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h1C, 0, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h20, y_len, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h24, x_len, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h28, src_stride, 'hF);
-    base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h2C, dst_stride, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h00, flags, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h04, id, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h08, dest_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h0C, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h10, src_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h14, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h18, next_desc_addr, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h1C, 0, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h20, y_len, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h24, x_len, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h28, src_stride, 'hF);
+    base_env.ddr.slave_sequencer.BackdoorWrite32(desc_addr+'h2C, dst_stride, 'hF);
 
   endtask : write_descriptor
 
@@ -250,8 +250,8 @@ program test_program_tr_queue;
     for (int i=0;i<length;i=i+4) begin
       current_src_address = src_addr+i;
       current_dest_address = dest_addr+i;
-      captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
-      reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
+      captured_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_dest_address);
+      reference_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_src_address);
 
       if (captured_word !== reference_word) begin
         `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

testbenches/ip/hbm/tests/test_program.sv

@@ -82,7 +82,7 @@ program test_program;
 //
 //    // Init test data
 //    for (int i=0;i<2048*2 ;i=i+2) begin
-//      base_env.ddr.slave_sequencer.set_reg_data_in_mem(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF);
+//      base_env.ddr.slave_sequencer.BackdoorWrite32(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF);
 //    end
 //
 //    do_transfer(
@@ -150,8 +150,8 @@ program test_program;
 //    for (int i=0;i<length/4;i=i+4) begin
 //      current_src_address = src_addr+i;
 //      current_dest_address = dest_addr+i;
-//      captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
-//      reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
+//      captured_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_dest_address);
+//      reference_word = base_env.ddr.slave_sequencer.BackdoorRead32(current_src_address);
 //
 //      if (captured_word !== reference_word) begin
 //        `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));