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| 1 | +// *************************************************************************** |
| 2 | +// *************************************************************************** |
| 3 | +// Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. |
| 4 | +// |
| 5 | +// In this HDL repository, there are many different and unique modules, consisting |
| 6 | +// of various HDL (Verilog or VHDL) components. The individual modules are |
| 7 | +// developed independently, and may be accompanied by separate and unique license |
| 8 | +// terms. |
| 9 | +// |
| 10 | +// The user should read each of these license terms, and understand the |
| 11 | +// freedoms and responsibilities that he or she has by using this source/core. |
| 12 | +// |
| 13 | +// This core is distributed in the hope that it will be useful, but WITHOUT ANY |
| 14 | +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR |
| 15 | +// A PARTICULAR PURPOSE. |
| 16 | +// |
| 17 | +// Redistribution and use of source or resulting binaries, with or without modification |
| 18 | +// of this file, are permitted under one of the following two license terms: |
| 19 | +// |
| 20 | +// 1. The GNU General Public License version 2 as published by the |
| 21 | +// Free Software Foundation, which can be found in the top level directory |
| 22 | +// of this repository (LICENSE_GPL2), and also online at: |
| 23 | +// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html> |
| 24 | +// |
| 25 | +// OR |
| 26 | +// |
| 27 | +// 2. An ADI specific BSD license, which can be found in the top level directory |
| 28 | +// of this repository (LICENSE_ADIBSD), and also on-line at: |
| 29 | +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD |
| 30 | +// This will allow to generate bit files and not release the source code, |
| 31 | +// as long as it attaches to an ADI device. |
| 32 | +// |
| 33 | +// *************************************************************************** |
| 34 | +// *************************************************************************** |
| 35 | + |
| 36 | +`timescale 1ns/100ps |
| 37 | + |
| 38 | +module system_top ( |
| 39 | + |
| 40 | + input [12:0] gpio_bd_i, |
| 41 | + output [ 7:0] gpio_bd_o, |
| 42 | + |
| 43 | + input adc_clk_in_n, |
| 44 | + input adc_clk_in_p, |
| 45 | + input [ 7:0] adc_data_in_n, |
| 46 | + input [ 7:0] adc_data_in_p, |
| 47 | + input adc_data_or_n, |
| 48 | + input adc_data_or_p, |
| 49 | + output spi_clk, |
| 50 | + output spi_csn_adc, |
| 51 | + output spi_csn_clk, |
| 52 | + inout spi_sdio |
| 53 | +); |
| 54 | + |
| 55 | + // internal signals |
| 56 | + wire [94:0] gpio_i; |
| 57 | + wire [94:0] gpio_o; |
| 58 | + |
| 59 | + assign gpio_bd_o = gpio_o[7:0]; |
| 60 | + |
| 61 | + assign gpio_i[94:21] = gpio_o[94:21]; |
| 62 | + assign gpio_i[20: 8] = gpio_bd_i; |
| 63 | + assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; |
| 64 | + |
| 65 | + wire [ 1:0] spi_csn; |
| 66 | + wire spi_miso; |
| 67 | + wire spi_mosi; |
| 68 | + |
| 69 | + assign spi_csn_adc = spi_csn[0]; |
| 70 | + assign spi_csn_clk = spi_csn[1]; |
| 71 | + |
| 72 | + // instantiations |
| 73 | + |
| 74 | + ad9467_spi i_spi ( |
| 75 | + .spi_csn(spi_csn), |
| 76 | + .spi_clk(spi_clk), |
| 77 | + .spi_mosi(spi_mosi), |
| 78 | + .spi_miso(spi_miso), |
| 79 | + .spi_sdio(spi_sdio)); |
| 80 | + |
| 81 | + system_wrapper i_system_wrapper ( |
| 82 | + .gpio_i (gpio_i), |
| 83 | + .gpio_o (gpio_o), |
| 84 | + .gpio_t (), |
| 85 | + |
| 86 | + .adc_clk_in_n(adc_clk_in_n), |
| 87 | + .adc_clk_in_p(adc_clk_in_p), |
| 88 | + .adc_data_in_n(adc_data_in_n), |
| 89 | + .adc_data_in_p(adc_data_in_p), |
| 90 | + .adc_data_or_n(adc_data_or_n), |
| 91 | + .adc_data_or_p(adc_data_or_p), |
| 92 | + |
| 93 | + .spi0_csn (spi_csn), |
| 94 | + .spi0_miso (spi_miso), |
| 95 | + .spi0_mosi (spi_mosi), |
| 96 | + .spi0_sclk (spi_clk), |
| 97 | + .spi1_csn (1'b1), |
| 98 | + .spi1_miso (1'b0), |
| 99 | + .spi1_mosi (), |
| 100 | + .spi1_sclk ()); |
| 101 | + |
| 102 | +endmodule |
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