|
| 1 | +// *************************************************************************** |
| 2 | +// *************************************************************************** |
| 3 | +// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved. |
| 4 | +// |
| 5 | +// In this HDL repository, there are many different and unique modules, consisting |
| 6 | +// of various HDL (Verilog or VHDL) components. The individual modules are |
| 7 | +// developed independently, and may be accompanied by separate and unique license |
| 8 | +// terms. |
| 9 | +// |
| 10 | +// The user should read each of these license terms, and understand the |
| 11 | +// freedoms and responsibilities that he or she has by using this source/core. |
| 12 | +// |
| 13 | +// This core is distributed in the hope that it will be useful, but WITHOUT ANY |
| 14 | +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR |
| 15 | +// A PARTICULAR PURPOSE. |
| 16 | +// |
| 17 | +// Redistribution and use of source or resulting binaries, with or without modification |
| 18 | +// of this file, are permitted under one of the following two license terms: |
| 19 | +// |
| 20 | +// 1. The GNU General Public License version 2 as published by the |
| 21 | +// Free Software Foundation, which can be found in the top level directory |
| 22 | +// of this repository (LICENSE_GPL2), and also online at: |
| 23 | +// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html> |
| 24 | +// |
| 25 | +// OR |
| 26 | +// |
| 27 | +// 2. An ADI specific BSD license, which can be found in the top level directory |
| 28 | +// of this repository (LICENSE_ADIBSD), and also on-line at: |
| 29 | +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD |
| 30 | +// This will allow to generate bit files and not release the source code, |
| 31 | +// as long as it attaches to an ADI device. |
| 32 | +// |
| 33 | +// *************************************************************************** |
| 34 | +// *************************************************************************** |
| 35 | + |
| 36 | +`timescale 1ns/100ps |
| 37 | + |
| 38 | +module system_top ( |
| 39 | + |
| 40 | + inout [14:0] ddr_addr, |
| 41 | + inout [ 2:0] ddr_ba, |
| 42 | + inout ddr_cas_n, |
| 43 | + inout ddr_ck_n, |
| 44 | + inout ddr_ck_p, |
| 45 | + inout ddr_cke, |
| 46 | + inout ddr_cs_n, |
| 47 | + inout [ 3:0] ddr_dm, |
| 48 | + inout [31:0] ddr_dq, |
| 49 | + inout [ 3:0] ddr_dqs_n, |
| 50 | + inout [ 3:0] ddr_dqs_p, |
| 51 | + inout ddr_odt, |
| 52 | + inout ddr_ras_n, |
| 53 | + inout ddr_reset_n, |
| 54 | + inout ddr_we_n, |
| 55 | + |
| 56 | + inout fixed_io_ddr_vrn, |
| 57 | + inout fixed_io_ddr_vrp, |
| 58 | + inout [53:0] fixed_io_mio, |
| 59 | + inout fixed_io_ps_clk, |
| 60 | + inout fixed_io_ps_porb, |
| 61 | + inout fixed_io_ps_srstb, |
| 62 | + |
| 63 | + inout [31:0] gpio_bd, |
| 64 | + |
| 65 | + output hdmi_out_clk, |
| 66 | + output hdmi_vsync, |
| 67 | + output hdmi_hsync, |
| 68 | + output hdmi_data_e, |
| 69 | + output [15:0] hdmi_data, |
| 70 | + |
| 71 | + output spdif, |
| 72 | + |
| 73 | + output i2s_mclk, |
| 74 | + output i2s_bclk, |
| 75 | + output i2s_lrclk, |
| 76 | + output i2s_sdata_out, |
| 77 | + input i2s_sdata_in, |
| 78 | + |
| 79 | + inout iic_scl, |
| 80 | + inout iic_sda, |
| 81 | + inout [ 1:0] iic_mux_scl, |
| 82 | + inout [ 1:0] iic_mux_sda, |
| 83 | + |
| 84 | + input otg_vbusoc, |
| 85 | + |
| 86 | + input admx100x_sync_mode, |
| 87 | + input admx100x_en, |
| 88 | + input admx100x_cal, |
| 89 | + input admx100x_trig, |
| 90 | + inout admx100x_dac_ldac, |
| 91 | + inout admx100x_reset, |
| 92 | + output admx100x_ready, |
| 93 | + output admx100x_valid, |
| 94 | + output admx100x_ot, |
| 95 | + |
| 96 | + input admx100x_spi_miso, |
| 97 | + output admx100x_spi_mosi, |
| 98 | + output admx100x_spi_sclk, |
| 99 | + output admx100x_spi_cs_0, |
| 100 | + output admx100x_spi_cs_1 |
| 101 | +); |
| 102 | + |
| 103 | + // internal signals |
| 104 | + |
| 105 | + wire [63:0] gpio_i; |
| 106 | + wire [63:0] gpio_o; |
| 107 | + wire [63:0] gpio_t; |
| 108 | + wire [ 1:0] iic_mux_scl_i_s; |
| 109 | + wire [ 1:0] iic_mux_scl_o_s; |
| 110 | + wire iic_mux_scl_t_s; |
| 111 | + wire [ 1:0] iic_mux_sda_i_s; |
| 112 | + wire [ 1:0] iic_mux_sda_o_s; |
| 113 | + wire iic_mux_sda_t_s; |
| 114 | + |
| 115 | + // gpio assign |
| 116 | + |
| 117 | + assign admx100x_sync_mode = gpio_o[34]; |
| 118 | + assign admx100x_en = gpio_o[35]; |
| 119 | + assign admx100x_cal = gpio_o[38]; |
| 120 | + assign admx100x_trig = gpio_o[40]; |
| 121 | + assign admx100x_dac_ldac = gpio_o[39]; |
| 122 | + assign admx100x_reset = gpio_o[33]; |
| 123 | + assign gpio_i[36] = admx100x_ready; |
| 124 | + assign gpio_i[37] = admx100x_valid; |
| 125 | + assign gpio_i[32] = admx100x_ot; |
| 126 | + |
| 127 | + assign gpio_i[63:41] = gpio_o[63:41]; |
| 128 | + |
| 129 | + // instantiations |
| 130 | + |
| 131 | + ad_iobuf #( |
| 132 | + .DATA_WIDTH (32) |
| 133 | + ) i_iobuf ( |
| 134 | + .dio_t (gpio_t[31:0]), |
| 135 | + .dio_i (gpio_o[31:0]), |
| 136 | + .dio_o (gpio_i[31:0]), |
| 137 | + .dio_p (gpio_bd)); |
| 138 | + |
| 139 | + ad_iobuf #( |
| 140 | + .DATA_WIDTH (2) |
| 141 | + ) i_iic_mux_scl ( |
| 142 | + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), |
| 143 | + .dio_i (iic_mux_scl_o_s), |
| 144 | + .dio_o (iic_mux_scl_i_s), |
| 145 | + .dio_p (iic_mux_scl)); |
| 146 | + |
| 147 | + ad_iobuf #( |
| 148 | + .DATA_WIDTH (2) |
| 149 | + ) i_iic_mux_sda ( |
| 150 | + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), |
| 151 | + .dio_i (iic_mux_sda_o_s), |
| 152 | + .dio_o (iic_mux_sda_i_s), |
| 153 | + .dio_p (iic_mux_sda)); |
| 154 | + |
| 155 | + system_wrapper i_system_wrapper ( |
| 156 | + .ddr_addr (ddr_addr), |
| 157 | + .ddr_ba (ddr_ba), |
| 158 | + .ddr_cas_n (ddr_cas_n), |
| 159 | + .ddr_ck_n (ddr_ck_n), |
| 160 | + .ddr_ck_p (ddr_ck_p), |
| 161 | + .ddr_cke (ddr_cke), |
| 162 | + .ddr_cs_n (ddr_cs_n), |
| 163 | + .ddr_dm (ddr_dm), |
| 164 | + .ddr_dq (ddr_dq), |
| 165 | + .ddr_dqs_n (ddr_dqs_n), |
| 166 | + .ddr_dqs_p (ddr_dqs_p), |
| 167 | + .ddr_odt (ddr_odt), |
| 168 | + .ddr_ras_n (ddr_ras_n), |
| 169 | + .ddr_reset_n (ddr_reset_n), |
| 170 | + .ddr_we_n (ddr_we_n), |
| 171 | + |
| 172 | + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), |
| 173 | + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), |
| 174 | + .fixed_io_mio (fixed_io_mio), |
| 175 | + .fixed_io_ps_clk (fixed_io_ps_clk), |
| 176 | + .fixed_io_ps_porb (fixed_io_ps_porb), |
| 177 | + .fixed_io_ps_srstb (fixed_io_ps_srstb), |
| 178 | + |
| 179 | + .gpio_i (gpio_i), |
| 180 | + .gpio_o (gpio_o), |
| 181 | + .gpio_t (gpio_t), |
| 182 | + |
| 183 | + .hdmi_data (hdmi_data), |
| 184 | + .hdmi_data_e (hdmi_data_e), |
| 185 | + .hdmi_hsync (hdmi_hsync), |
| 186 | + .hdmi_out_clk (hdmi_out_clk), |
| 187 | + .hdmi_vsync (hdmi_vsync), |
| 188 | + |
| 189 | + .spdif (spdif), |
| 190 | + |
| 191 | + .i2s_bclk (i2s_bclk), |
| 192 | + .i2s_lrclk (i2s_lrclk), |
| 193 | + .i2s_mclk (i2s_mclk), |
| 194 | + .i2s_sdata_in (i2s_sdata_in), |
| 195 | + .i2s_sdata_out (i2s_sdata_out), |
| 196 | + .iic_fmc_scl_io (iic_scl), |
| 197 | + .iic_fmc_sda_io (iic_sda), |
| 198 | + .iic_mux_scl_i (iic_mux_scl_i_s), |
| 199 | + .iic_mux_scl_o (iic_mux_scl_o_s), |
| 200 | + .iic_mux_scl_t (iic_mux_scl_t_s), |
| 201 | + .iic_mux_sda_i (iic_mux_sda_i_s), |
| 202 | + .iic_mux_sda_o (iic_mux_sda_o_s), |
| 203 | + .iic_mux_sda_t (iic_mux_sda_t_s), |
| 204 | + |
| 205 | + .otg_vbusoc (otg_vbusoc), |
| 206 | + |
| 207 | + .spi0_clk_i (1'b0), |
| 208 | + .spi0_clk_o (admx100x_spi_sclk), |
| 209 | + .spi0_csn_0_o (admx100x_spi_cs_0), |
| 210 | + .spi0_csn_1_o (admx100x_spi_cs_1), |
| 211 | + .spi0_csn_2_o (), |
| 212 | + .spi0_csn_i (1'b1), |
| 213 | + .spi0_sdi_i (admx100x_spi_miso), |
| 214 | + .spi0_sdo_i (1'b0), |
| 215 | + .spi0_sdo_o (admx100x_spi_mosi), |
| 216 | + .spi1_clk_i (1'b0), |
| 217 | + .spi1_clk_o (), |
| 218 | + .spi1_csn_0_o (), |
| 219 | + .spi1_csn_1_o (), |
| 220 | + .spi1_csn_2_o (), |
| 221 | + .spi1_csn_i (1'b1), |
| 222 | + .spi1_sdi_i (1'b0), |
| 223 | + .spi1_sdo_i (1'b0), |
| 224 | + .spi1_sdo_o ()); |
| 225 | + |
| 226 | +endmodule |
0 commit comments