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Filip.Gherman
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library/axi_hsci: Add HSCI IP core
Signed-off-by: Filip Gherman <filip.gherman@analog.com>
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‎library/axi_hsci/Makefile‎

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####################################################################################
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## Copyright (c) 2018 - 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_hsci
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += axi4_lite.sv
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GENERIC_DEPS += axi_hsci.sv
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GENERIC_DEPS += hsci_master_axi_slave.sv
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GENERIC_DEPS += hsci_master_logic.sv
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GENERIC_DEPS += hsci_master_regs_defs.vh
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GENERIC_DEPS += hsci_master_regs_regs.sv
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GENERIC_DEPS += hsci_master_top.sv
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GENERIC_DEPS += hsci_mcore.v
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GENERIC_DEPS += hsci_mdec.sv
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GENERIC_DEPS += hsci_menc.sv
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GENERIC_DEPS += hsci_mfrm_det.v
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GENERIC_DEPS += hsci_mlink_ctrl.sv
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GENERIC_DEPS += lfsr15_8.v
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GENERIC_DEPS += pulse_sync.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += axi_hsci_ip.tcl
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include ../scripts/library.mk

‎library/axi_hsci/axi4_lite.sv‎

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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interface axi4_lite #(
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DATA_WIDTH = 32,
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ADDR_WIDTH = 32
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);
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localparam WSTRB_WIDTH = DATA_WIDTH/8;
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// Write address channel
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logic awvalid;
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logic awready;
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logic [2:0] awprot;
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logic [ADDR_WIDTH-1:0] awaddr;
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// Write data channel
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logic wvalid;
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logic wready;
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logic [WSTRB_WIDTH-1:0] wstrb;
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logic [DATA_WIDTH-1:0] wdata;
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// Write response channel
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logic bvalid;
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logic bready;
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logic [1:0] bresp;
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// Read address channel
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logic arvalid;
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logic arready;
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logic [2:0] arprot;
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logic [ADDR_WIDTH-1:0] araddr;
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// Read response channel
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logic rvalid;
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logic rready;
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logic [1:0] rresp;
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logic [DATA_WIDTH-1:0] rdata;
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modport master (
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output awvalid, awprot, awaddr, wvalid, wstrb, wdata, bready, arvalid, arprot, araddr, rready,
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input awready, wready, bvalid, bresp, arready, rvalid, rresp, rdata
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);
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modport slave (
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output awready, wready, bvalid, bresp, arready, rvalid, rresp, rdata,
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input awvalid, awprot, awaddr, wvalid, wstrb, wdata, bready, arvalid, arprot, araddr, rready
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);
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endinterface

‎library/axi_hsci/axi_hsci.sv‎

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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import hsci_master_regs_pkg::*;
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module axi_hsci #(
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parameter AXI_ADDR_WIDTH = 15,
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parameter AXI_DATA_WIDTH = 32,
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parameter REGMAP_ADDR_WIDTH = 16,
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parameter S_AXI_ADDR_WIDTH = 18
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) (
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire [S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [2:0] s_axi_awprot,
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input wire s_axi_awvalid,
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input wire s_axi_bready,
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input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
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input wire s_axi_wvalid,
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input wire s_axi_rready,
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input wire [(AXI_DATA_WIDTH/8)-1 : 0] s_axi_wstrb,
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input wire [S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [2:0] s_axi_arprot,
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input wire s_axi_arvalid,
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output wire s_axi_wready,
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output wire s_axi_arready,
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output wire [1:0] s_axi_rresp,
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output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
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output wire s_axi_rvalid,
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output wire s_axi_awready,
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output wire [1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire hsci_pclk,
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output [7:0] hsci_menc_clk,
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output [7:0] hsci_mosi_data,
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input wire [7:0] hsci_miso_data,
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output wire hsci_pll_reset,
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input wire hsci_rst_seq_done,
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input wire hsci_pll_locked,
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input wire hsci_vtc_rdy_bsc_tx,
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input wire hsci_dly_rdy_bsc_tx,
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input wire hsci_vtc_rdy_bsc_rx,
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input wire hsci_dly_rdy_bsc_rx
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);
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axi4_lite #(32,18) axi();
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assign axi.awaddr = s_axi_awaddr;
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assign axi.awprot = s_axi_awprot;
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assign axi.awvalid = s_axi_awvalid;
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assign axi.bready = s_axi_bready;
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assign axi.wdata = s_axi_wdata;
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assign axi.wvalid = s_axi_wvalid;
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assign axi.rready = s_axi_rready;
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assign axi.wstrb = s_axi_wstrb;
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assign axi.araddr = s_axi_araddr;
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assign axi.arprot = s_axi_arprot;
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assign axi.arvalid = s_axi_arvalid;
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assign s_axi_wready = axi.wready;
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assign s_axi_arready = axi.arready;
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assign s_axi_rresp = axi.rresp;
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assign s_axi_rdata = axi.rdata;
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assign s_axi_rvalid = axi.rvalid ;
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assign s_axi_awready = axi.awready;
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assign s_axi_bresp = axi.bresp;
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assign s_axi_bvalid = axi.bvalid;
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hsci_master_top #(
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.REGMAP_ADDR_WIDTH (REGMAP_ADDR_WIDTH),
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.S_AXI_ADDR_WIDTH (S_AXI_ADDR_WIDTH)
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) hsci_master_top (
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.axi_clk (s_axi_aclk),
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.axi_resetn (s_axi_aresetn),
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.axi (axi),
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.hsci_pclk (hsci_pclk),
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.hsci_menc_clk (hsci_menc_clk),
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.hsci_mosi_data (hsci_mosi_data),
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.hsci_miso_data (hsci_miso_data),
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.hsci_pll_reset (hsci_pll_reset),
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.hsci_rst_seq_done (hsci_rst_seq_done),
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.hsci_pll_locked (hsci_pll_locked),
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.hsci_vtc_rdy_bsc_tx (hsci_vtc_rdy_bsc_tx),
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.hsci_dly_rdy_bsc_tx (hsci_dly_rdy_bsc_tx),
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.hsci_vtc_rdy_bsc_rx (hsci_vtc_rdy_bsc_rx),
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.hsci_dly_rdy_bsc_rx (hsci_dly_rdy_bsc_rx));
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endmodule

‎library/axi_hsci/axi_hsci_constr.ttcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_master_logic/hsci_master_regs_regs/O_reg[hsci_bram_start_address][data][*]/C}] \
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-to [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_mcore/enc0/enc_addr_reg[*]/D}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_master_logic/hsci_master_regs_regs/O_reg[hsci_xfer_num][data][*]/C}] \
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-to [get_cells -hierarchical * -filter {NAME=~*hsci_master_top/hsci_mcore/enc0/m_xfer_num_reg[*]/D}]
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set_false_path -from [get_cells -filter IS_SEQUENTIAL -hierarchical -regexp ".*O_reg.*"] -to [get_clocks -of_objects [get_ports {hsci_pclk}]]

‎library/axi_hsci/axi_hsci_ip.tcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ip
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source ../../scripts/adi_env.tcl
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source ../scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_hsci
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adi_ip_files axi_hsci [list \
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"../common/ad_rst.v" \
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"../xilinx/common/ad_rst_constr.xdc" \
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"axi_hsci.sv" \
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"hsci_master_axi_slave.sv" \
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"hsci_master_logic.sv" \
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"hsci_master_regs_defs.vh" \
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"hsci_master_regs_regs.sv" \
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"hsci_master_top.sv" \
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"hsci_mcore.v" \
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"hsci_mdec.sv" \
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"hsci_menc.sv" \
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"hsci_mfrm_det.v" \
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"hsci_mlink_ctrl.sv" \
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"lfsr15_8.v" \
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"pulse_sync.v" \
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"axi4_lite.sv" ]
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adi_ip_properties axi_hsci
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adi_ip_ttcl axi_hsci "axi_hsci_constr.ttcl"
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set_property display_name "ADI AXI HSCI" [ipx::current_core]
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set_property description "ADI AXI HSCI" [ipx::current_core]
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# set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_hsci} [ipx::current_core]
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adi_init_bd_tcl
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proc add_reset {name polarity} {
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set reset_intf [ipx::infer_bus_interface $name xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
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set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
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set_property value $polarity $reset_polarity
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}
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ipx::infer_bus_interface hsci_pclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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# ipx::infer_bus_interface hsci_data_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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# ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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add_reset s_axi_aresetn ACTIVE_LOW
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ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]
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set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
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adi_add_auto_fpga_spec_params
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ipx::create_xgui_files [ipx::current_core]
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ipx::save_core [ipx::current_core]

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