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slicoss.c
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/**************************************************************************
*
* Copyright 2000-2006 Alacritech, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slicoss.c
*
* The SLICOSS driver for Alacritech's IS-NIC products.
*
* This driver is supposed to support:
*
* Mojave cards (single port PCI Gigabit) both copper and fiber
* Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
* Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
*
* The driver was acutally tested on Oasis and Kalahari cards.
*
*
* NOTE: This is the standard, non-accelerated version of Alacritech's
* IS-NIC driver.
*/
#define KLUDGE_FOR_4GB_BOUNDARY 1
#define DEBUG_MICROCODE 1
#define DBG 1
#define SLIC_INTERRUPT_PROCESS_LIMIT 1
#define SLIC_OFFLOAD_IP_CHECKSUM 1
#define STATS_TIMER_INTERVAL 2
#define PING_TIMER_INTERVAL 1
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/timer.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/firmware.h>
#include <linux/types.h>
#include <linux/dma-mapping.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <asm/unaligned.h>
#include <linux/ethtool.h>
#include <linux/uaccess.h>
#include "slichw.h"
#include "slic.h"
static uint slic_first_init = 1;
static char *slic_banner = "Alacritech SLIC Technology(tm) Server "\
"and Storage Accelerator (Non-Accelerated)";
static char *slic_proc_version = "2.0.351 2006/07/14 12:26:00";
static char *slic_product_name = "SLIC Technology(tm) Server "\
"and Storage Accelerator (Non-Accelerated)";
static char *slic_vendor = "Alacritech, Inc.";
static int slic_debug = 1;
static int debug = -1;
static struct net_device *head_netdevice;
static struct base_driver slic_global = { {}, 0, 0, 0, 1, NULL, NULL };
static int intagg_delay = 100;
static u32 dynamic_intagg;
static unsigned int rcv_count;
static struct dentry *slic_debugfs;
#define DRV_NAME "slicoss"
#define DRV_VERSION "2.0.1"
#define DRV_AUTHOR "Alacritech, Inc. Engineering"
#define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) "\
"Non-Accelerated Driver"
#define DRV_COPYRIGHT "Copyright 2000-2006 Alacritech, Inc. "\
"All rights reserved."
#define PFX DRV_NAME " "
MODULE_AUTHOR(DRV_AUTHOR);
MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_LICENSE("Dual BSD/GPL");
module_param(dynamic_intagg, int, 0);
MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
module_param(intagg_delay, int, 0);
MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
static DEFINE_PCI_DEVICE_TABLE(slic_pci_tbl) = {
{ PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_1GB_DEVICE_ID) },
{ PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_2GB_DEVICE_ID) },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, slic_pci_tbl);
#ifdef ASSERT
#undef ASSERT
#endif
static void slic_assert_fail(void)
{
u32 cpuid;
u32 curr_pid;
cpuid = smp_processor_id();
curr_pid = current->pid;
printk(KERN_ERR "%s CPU # %d ---- PID # %d\n",
__func__, cpuid, curr_pid);
}
#ifndef ASSERT
#define ASSERT(a) do { \
if (!(a)) { \
printk(KERN_ERR "slicoss ASSERT() Failure: function %s" \
"line %d\n", __func__, __LINE__); \
slic_assert_fail(); \
} \
} while (0)
#endif
#define SLIC_GET_SLIC_HANDLE(_adapter, _pslic_handle) \
{ \
spin_lock_irqsave(&_adapter->handle_lock.lock, \
_adapter->handle_lock.flags); \
_pslic_handle = _adapter->pfree_slic_handles; \
if (_pslic_handle) { \
ASSERT(_pslic_handle->type == SLIC_HANDLE_FREE); \
_adapter->pfree_slic_handles = _pslic_handle->next; \
} \
spin_unlock_irqrestore(&_adapter->handle_lock.lock, \
_adapter->handle_lock.flags); \
}
#define SLIC_FREE_SLIC_HANDLE(_adapter, _pslic_handle) \
{ \
_pslic_handle->type = SLIC_HANDLE_FREE; \
spin_lock_irqsave(&_adapter->handle_lock.lock, \
_adapter->handle_lock.flags); \
_pslic_handle->next = _adapter->pfree_slic_handles; \
_adapter->pfree_slic_handles = _pslic_handle; \
spin_unlock_irqrestore(&_adapter->handle_lock.lock, \
_adapter->handle_lock.flags); \
}
static inline void slic_reg32_write(void __iomem *reg, u32 value, bool flush)
{
writel(value, reg);
if (flush)
mb();
}
static inline void slic_reg64_write(struct adapter *adapter, void __iomem *reg,
u32 value, void __iomem *regh, u32 paddrh,
bool flush)
{
spin_lock_irqsave(&adapter->bit64reglock.lock,
adapter->bit64reglock.flags);
if (paddrh != adapter->curaddrupper) {
adapter->curaddrupper = paddrh;
writel(paddrh, regh);
}
writel(value, reg);
if (flush)
mb();
spin_unlock_irqrestore(&adapter->bit64reglock.lock,
adapter->bit64reglock.flags);
}
/*
* Functions to obtain the CRC corresponding to the destination mac address.
* This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using
* the polynomial:
* x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 +
* x^4 + x^2 + x^1.
*
* After the CRC for the 6 bytes is generated (but before the value is
* complemented),
* we must then transpose the value and return bits 30-23.
*
*/
static u32 slic_crc_table[256]; /* Table of CRCs for all possible byte values */
static u32 slic_crc_init; /* Is table initialized */
/*
* Contruct the CRC32 table
*/
static void slic_mcast_init_crc32(void)
{
u32 c; /* CRC shit reg */
u32 e = 0; /* Poly X-or pattern */
int i; /* counter */
int k; /* byte being shifted into crc */
static int p[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 };
for (i = 0; i < ARRAY_SIZE(p); i++)
e |= 1L << (31 - p[i]);
for (i = 1; i < 256; i++) {
c = i;
for (k = 8; k; k--)
c = c & 1 ? (c >> 1) ^ e : c >> 1;
slic_crc_table[i] = c;
}
}
/*
* Return the MAC hast as described above.
*/
static unsigned char slic_mcast_get_mac_hash(char *macaddr)
{
u32 crc;
char *p;
int i;
unsigned char machash = 0;
if (!slic_crc_init) {
slic_mcast_init_crc32();
slic_crc_init = 1;
}
crc = 0xFFFFFFFF; /* Preload shift register, per crc-32 spec */
for (i = 0, p = macaddr; i < 6; ++p, ++i)
crc = (crc >> 8) ^ slic_crc_table[(crc ^ *p) & 0xFF];
/* Return bits 1-8, transposed */
for (i = 1; i < 9; i++)
machash |= (((crc >> i) & 1) << (8 - i));
return machash;
}
static void slic_mcast_set_bit(struct adapter *adapter, char *address)
{
unsigned char crcpoly;
/* Get the CRC polynomial for the mac address */
crcpoly = slic_mcast_get_mac_hash(address);
/* We only have space on the SLIC for 64 entries. Lop
* off the top two bits. (2^6 = 64)
*/
crcpoly &= 0x3F;
/* OR in the new bit into our 64 bit mask. */
adapter->mcastmask |= (u64) 1 << crcpoly;
}
static void slic_mcast_set_mask(struct adapter *adapter)
{
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
if (adapter->macopts & (MAC_ALLMCAST | MAC_PROMISC)) {
/* Turn on all multicast addresses. We have to do this for
* promiscuous mode as well as ALLMCAST mode. It saves the
* Microcode from having to keep state about the MAC
* configuration.
*/
slic_reg32_write(&slic_regs->slic_mcastlow, 0xFFFFFFFF, FLUSH);
slic_reg32_write(&slic_regs->slic_mcasthigh, 0xFFFFFFFF,
FLUSH);
} else {
/* Commit our multicast mast to the SLIC by writing to the
* multicast address mask registers
*/
slic_reg32_write(&slic_regs->slic_mcastlow,
(u32)(adapter->mcastmask & 0xFFFFFFFF), FLUSH);
slic_reg32_write(&slic_regs->slic_mcasthigh,
(u32)((adapter->mcastmask >> 32) & 0xFFFFFFFF), FLUSH);
}
}
static void slic_timer_ping(ulong dev)
{
struct adapter *adapter;
struct sliccard *card;
ASSERT(dev);
adapter = netdev_priv((struct net_device *)dev);
ASSERT(adapter);
card = adapter->card;
ASSERT(card);
adapter->pingtimer.expires = jiffies + (PING_TIMER_INTERVAL * HZ);
add_timer(&adapter->pingtimer);
}
static void slic_unmap_mmio_space(struct adapter *adapter)
{
if (adapter->slic_regs)
iounmap(adapter->slic_regs);
adapter->slic_regs = NULL;
}
/*
* slic_link_config
*
* Write phy control to configure link duplex/speed
*
*/
static void slic_link_config(struct adapter *adapter,
u32 linkspeed, u32 linkduplex)
{
u32 __iomem *wphy;
u32 speed;
u32 duplex;
u32 phy_config;
u32 phy_advreg;
u32 phy_gctlreg;
if (adapter->state != ADAPT_UP)
return;
ASSERT((adapter->devid == SLIC_1GB_DEVICE_ID)
|| (adapter->devid == SLIC_2GB_DEVICE_ID));
if (linkspeed > LINK_1000MB)
linkspeed = LINK_AUTOSPEED;
if (linkduplex > LINK_AUTOD)
linkduplex = LINK_AUTOD;
wphy = &adapter->slic_regs->slic_wphy;
if ((linkspeed == LINK_AUTOSPEED) || (linkspeed == LINK_1000MB)) {
if (adapter->flags & ADAPT_FLAGS_FIBERMEDIA) {
/* We've got a fiber gigabit interface, and register
* 4 is different in fiber mode than in copper mode
*/
/* advertise FD only @1000 Mb */
phy_advreg = (MIICR_REG_4 | (PAR_ADV1000XFD));
/* enable PAUSE frames */
phy_advreg |= PAR_ASYMPAUSE_FIBER;
slic_reg32_write(wphy, phy_advreg, FLUSH);
if (linkspeed == LINK_AUTOSPEED) {
/* reset phy, enable auto-neg */
phy_config =
(MIICR_REG_PCR |
(PCR_RESET | PCR_AUTONEG |
PCR_AUTONEG_RST));
slic_reg32_write(wphy, phy_config, FLUSH);
} else { /* forced 1000 Mb FD*/
/* power down phy to break link
this may not work) */
phy_config = (MIICR_REG_PCR | PCR_POWERDOWN);
slic_reg32_write(wphy, phy_config, FLUSH);
/* wait, Marvell says 1 sec,
try to get away with 10 ms */
mdelay(10);
/* disable auto-neg, set speed/duplex,
soft reset phy, powerup */
phy_config =
(MIICR_REG_PCR |
(PCR_RESET | PCR_SPEED_1000 |
PCR_DUPLEX_FULL));
slic_reg32_write(wphy, phy_config, FLUSH);
}
} else { /* copper gigabit */
/* Auto-Negotiate or 1000 Mb must be auto negotiated
* We've got a copper gigabit interface, and
* register 4 is different in copper mode than
* in fiber mode
*/
if (linkspeed == LINK_AUTOSPEED) {
/* advertise 10/100 Mb modes */
phy_advreg =
(MIICR_REG_4 |
(PAR_ADV100FD | PAR_ADV100HD | PAR_ADV10FD
| PAR_ADV10HD));
} else {
/* linkspeed == LINK_1000MB -
don't advertise 10/100 Mb modes */
phy_advreg = MIICR_REG_4;
}
/* enable PAUSE frames */
phy_advreg |= PAR_ASYMPAUSE;
/* required by the Cicada PHY */
phy_advreg |= PAR_802_3;
slic_reg32_write(wphy, phy_advreg, FLUSH);
/* advertise FD only @1000 Mb */
phy_gctlreg = (MIICR_REG_9 | (PGC_ADV1000FD));
slic_reg32_write(wphy, phy_gctlreg, FLUSH);
if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
/* if a Marvell PHY
enable auto crossover */
phy_config =
(MIICR_REG_16 | (MRV_REG16_XOVERON));
slic_reg32_write(wphy, phy_config, FLUSH);
/* reset phy, enable auto-neg */
phy_config =
(MIICR_REG_PCR |
(PCR_RESET | PCR_AUTONEG |
PCR_AUTONEG_RST));
slic_reg32_write(wphy, phy_config, FLUSH);
} else { /* it's a Cicada PHY */
/* enable and restart auto-neg (don't reset) */
phy_config =
(MIICR_REG_PCR |
(PCR_AUTONEG | PCR_AUTONEG_RST));
slic_reg32_write(wphy, phy_config, FLUSH);
}
}
} else {
/* Forced 10/100 */
if (linkspeed == LINK_10MB)
speed = 0;
else
speed = PCR_SPEED_100;
if (linkduplex == LINK_HALFD)
duplex = 0;
else
duplex = PCR_DUPLEX_FULL;
if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
/* if a Marvell PHY
disable auto crossover */
phy_config = (MIICR_REG_16 | (MRV_REG16_XOVEROFF));
slic_reg32_write(wphy, phy_config, FLUSH);
}
/* power down phy to break link (this may not work) */
phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN | speed | duplex));
slic_reg32_write(wphy, phy_config, FLUSH);
/* wait, Marvell says 1 sec, try to get away with 10 ms */
mdelay(10);
if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
/* if a Marvell PHY
disable auto-neg, set speed,
soft reset phy, powerup */
phy_config =
(MIICR_REG_PCR | (PCR_RESET | speed | duplex));
slic_reg32_write(wphy, phy_config, FLUSH);
} else { /* it's a Cicada PHY */
/* disable auto-neg, set speed, powerup */
phy_config = (MIICR_REG_PCR | (speed | duplex));
slic_reg32_write(wphy, phy_config, FLUSH);
}
}
}
static int slic_card_download_gbrcv(struct adapter *adapter)
{
const struct firmware *fw;
const char *file = "";
int ret;
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
u32 codeaddr;
u32 instruction;
int index = 0;
u32 rcvucodelen = 0;
switch (adapter->devid) {
case SLIC_2GB_DEVICE_ID:
file = "slicoss/oasisrcvucode.sys";
break;
case SLIC_1GB_DEVICE_ID:
file = "slicoss/gbrcvucode.sys";
break;
default:
ASSERT(0);
break;
}
ret = request_firmware(&fw, file, &adapter->pcidev->dev);
if (ret) {
dev_err(&adapter->pcidev->dev,
"SLICOSS: Failed to load firmware %s\n", file);
return ret;
}
rcvucodelen = *(u32 *)(fw->data + index);
index += 4;
switch (adapter->devid) {
case SLIC_2GB_DEVICE_ID:
if (rcvucodelen != OasisRcvUCodeLen)
return -EINVAL;
break;
case SLIC_1GB_DEVICE_ID:
if (rcvucodelen != GBRcvUCodeLen)
return -EINVAL;
break;
default:
ASSERT(0);
break;
}
/* start download */
slic_reg32_write(&slic_regs->slic_rcv_wcs, SLIC_RCVWCS_BEGIN, FLUSH);
/* download the rcv sequencer ucode */
for (codeaddr = 0; codeaddr < rcvucodelen; codeaddr++) {
/* write out instruction address */
slic_reg32_write(&slic_regs->slic_rcv_wcs, codeaddr, FLUSH);
instruction = *(u32 *)(fw->data + index);
index += 4;
/* write out the instruction data low addr */
slic_reg32_write(&slic_regs->slic_rcv_wcs, instruction, FLUSH);
instruction = *(u8 *)(fw->data + index);
index++;
/* write out the instruction data high addr */
slic_reg32_write(&slic_regs->slic_rcv_wcs, (u8)instruction,
FLUSH);
}
/* download finished */
release_firmware(fw);
slic_reg32_write(&slic_regs->slic_rcv_wcs, SLIC_RCVWCS_FINISH, FLUSH);
return 0;
}
MODULE_FIRMWARE("slicoss/oasisrcvucode.sys");
MODULE_FIRMWARE("slicoss/gbrcvucode.sys");
static int slic_card_download(struct adapter *adapter)
{
const struct firmware *fw;
const char *file = "";
int ret;
u32 section;
int thissectionsize;
int codeaddr;
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
u32 instruction;
u32 baseaddress;
u32 i;
u32 numsects = 0;
u32 sectsize[3];
u32 sectstart[3];
int ucode_start, index = 0;
switch (adapter->devid) {
case SLIC_2GB_DEVICE_ID:
file = "slicoss/oasisdownload.sys";
break;
case SLIC_1GB_DEVICE_ID:
file = "slicoss/gbdownload.sys";
break;
default:
ASSERT(0);
break;
}
ret = request_firmware(&fw, file, &adapter->pcidev->dev);
if (ret) {
dev_err(&adapter->pcidev->dev,
"SLICOSS: Failed to load firmware %s\n", file);
return ret;
}
numsects = *(u32 *)(fw->data + index);
index += 4;
ASSERT(numsects <= 3);
for (i = 0; i < numsects; i++) {
sectsize[i] = *(u32 *)(fw->data + index);
index += 4;
}
for (i = 0; i < numsects; i++) {
sectstart[i] = *(u32 *)(fw->data + index);
index += 4;
}
ucode_start = index;
instruction = *(u32 *)(fw->data + index);
index += 4;
for (section = 0; section < numsects; section++) {
baseaddress = sectstart[section];
thissectionsize = sectsize[section] >> 3;
for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
/* Write out instruction address */
slic_reg32_write(&slic_regs->slic_wcs,
baseaddress + codeaddr, FLUSH);
/* Write out instruction to low addr */
slic_reg32_write(&slic_regs->slic_wcs, instruction, FLUSH);
instruction = *(u32 *)(fw->data + index);
index += 4;
/* Write out instruction to high addr */
slic_reg32_write(&slic_regs->slic_wcs, instruction, FLUSH);
instruction = *(u32 *)(fw->data + index);
index += 4;
}
}
index = ucode_start;
for (section = 0; section < numsects; section++) {
instruction = *(u32 *)(fw->data + index);
baseaddress = sectstart[section];
if (baseaddress < 0x8000)
continue;
thissectionsize = sectsize[section] >> 3;
for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
/* Write out instruction address */
slic_reg32_write(&slic_regs->slic_wcs,
SLIC_WCS_COMPARE | (baseaddress + codeaddr),
FLUSH);
/* Write out instruction to low addr */
slic_reg32_write(&slic_regs->slic_wcs, instruction,
FLUSH);
instruction = *(u32 *)(fw->data + index);
index += 4;
/* Write out instruction to high addr */
slic_reg32_write(&slic_regs->slic_wcs, instruction,
FLUSH);
instruction = *(u32 *)(fw->data + index);
index += 4;
/* Check SRAM location zero. If it is non-zero. Abort.*/
/* failure = readl((u32 __iomem *)&slic_regs->slic_reset);
if (failure) {
release_firmware(fw);
return -EIO;
}*/
}
}
release_firmware(fw);
/* Everything OK, kick off the card */
mdelay(10);
slic_reg32_write(&slic_regs->slic_wcs, SLIC_WCS_START, FLUSH);
/* stall for 20 ms, long enough for ucode to init card
and reach mainloop */
mdelay(20);
return 0;
}
MODULE_FIRMWARE("slicoss/oasisdownload.sys");
MODULE_FIRMWARE("slicoss/gbdownload.sys");
static void slic_adapter_set_hwaddr(struct adapter *adapter)
{
struct sliccard *card = adapter->card;
if ((adapter->card) && (card->config_set)) {
memcpy(adapter->macaddr,
card->config.MacInfo[adapter->functionnumber].macaddrA,
sizeof(struct slic_config_mac));
if (!(adapter->currmacaddr[0] || adapter->currmacaddr[1] ||
adapter->currmacaddr[2] || adapter->currmacaddr[3] ||
adapter->currmacaddr[4] || adapter->currmacaddr[5])) {
memcpy(adapter->currmacaddr, adapter->macaddr, 6);
}
if (adapter->netdev) {
memcpy(adapter->netdev->dev_addr, adapter->currmacaddr,
6);
}
}
}
static void slic_intagg_set(struct adapter *adapter, u32 value)
{
slic_reg32_write(&adapter->slic_regs->slic_intagg, value, FLUSH);
adapter->card->loadlevel_current = value;
}
static void slic_soft_reset(struct adapter *adapter)
{
if (adapter->card->state == CARD_UP) {
slic_reg32_write(&adapter->slic_regs->slic_quiesce, 0, FLUSH);
mdelay(1);
}
slic_reg32_write(&adapter->slic_regs->slic_reset, SLIC_RESET_MAGIC,
FLUSH);
mdelay(1);
}
static void slic_mac_address_config(struct adapter *adapter)
{
u32 value;
u32 value2;
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
value = *(u32 *) &adapter->currmacaddr[2];
value = ntohl(value);
slic_reg32_write(&slic_regs->slic_wraddral, value, FLUSH);
slic_reg32_write(&slic_regs->slic_wraddrbl, value, FLUSH);
value2 = (u32) ((adapter->currmacaddr[0] << 8 |
adapter->currmacaddr[1]) & 0xFFFF);
slic_reg32_write(&slic_regs->slic_wraddrah, value2, FLUSH);
slic_reg32_write(&slic_regs->slic_wraddrbh, value2, FLUSH);
/* Write our multicast mask out to the card. This is done */
/* here in addition to the slic_mcast_addr_set routine */
/* because ALL_MCAST may have been enabled or disabled */
slic_mcast_set_mask(adapter);
}
static void slic_mac_config(struct adapter *adapter)
{
u32 value;
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
/* Setup GMAC gaps */
if (adapter->linkspeed == LINK_1000MB) {
value = ((GMCR_GAPBB_1000 << GMCR_GAPBB_SHIFT) |
(GMCR_GAPR1_1000 << GMCR_GAPR1_SHIFT) |
(GMCR_GAPR2_1000 << GMCR_GAPR2_SHIFT));
} else {
value = ((GMCR_GAPBB_100 << GMCR_GAPBB_SHIFT) |
(GMCR_GAPR1_100 << GMCR_GAPR1_SHIFT) |
(GMCR_GAPR2_100 << GMCR_GAPR2_SHIFT));
}
/* enable GMII */
if (adapter->linkspeed == LINK_1000MB)
value |= GMCR_GBIT;
/* enable fullduplex */
if ((adapter->linkduplex == LINK_FULLD)
|| (adapter->macopts & MAC_LOOPBACK)) {
value |= GMCR_FULLD;
}
/* write mac config */
slic_reg32_write(&slic_regs->slic_wmcfg, value, FLUSH);
/* setup mac addresses */
slic_mac_address_config(adapter);
}
static void slic_config_set(struct adapter *adapter, bool linkchange)
{
u32 value;
u32 RcrReset;
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
if (linkchange) {
/* Setup MAC */
slic_mac_config(adapter);
RcrReset = GRCR_RESET;
} else {
slic_mac_address_config(adapter);
RcrReset = 0;
}
if (adapter->linkduplex == LINK_FULLD) {
/* setup xmtcfg */
value = (GXCR_RESET | /* Always reset */
GXCR_XMTEN | /* Enable transmit */
GXCR_PAUSEEN); /* Enable pause */
slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
/* Setup rcvcfg last */
value = (RcrReset | /* Reset, if linkchange */
GRCR_CTLEN | /* Enable CTL frames */
GRCR_ADDRAEN | /* Address A enable */
GRCR_RCVBAD | /* Rcv bad frames */
(GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
} else {
/* setup xmtcfg */
value = (GXCR_RESET | /* Always reset */
GXCR_XMTEN); /* Enable transmit */
slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
/* Setup rcvcfg last */
value = (RcrReset | /* Reset, if linkchange */
GRCR_ADDRAEN | /* Address A enable */
GRCR_RCVBAD | /* Rcv bad frames */
(GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
}
if (adapter->state != ADAPT_DOWN) {
/* Only enable receive if we are restarting or running */
value |= GRCR_RCVEN;
}
if (adapter->macopts & MAC_PROMISC)
value |= GRCR_RCVALL;
slic_reg32_write(&slic_regs->slic_wrcfg, value, FLUSH);
}
/*
* Turn off RCV and XMT, power down PHY
*/
static void slic_config_clear(struct adapter *adapter)
{
u32 value;
u32 phy_config;
__iomem struct slic_regs *slic_regs = adapter->slic_regs;
/* Setup xmtcfg */
value = (GXCR_RESET | /* Always reset */
GXCR_PAUSEEN); /* Enable pause */
slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
value = (GRCR_RESET | /* Always reset */
GRCR_CTLEN | /* Enable CTL frames */
GRCR_ADDRAEN | /* Address A enable */
(GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
slic_reg32_write(&slic_regs->slic_wrcfg, value, FLUSH);
/* power down phy */
phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN));
slic_reg32_write(&slic_regs->slic_wphy, phy_config, FLUSH);
}
static bool slic_mac_filter(struct adapter *adapter,
struct ether_header *ether_frame)
{
struct net_device *netdev = adapter->netdev;
u32 opts = adapter->macopts;
u32 *dhost4 = (u32 *)ðer_frame->ether_dhost[0];
u16 *dhost2 = (u16 *)ðer_frame->ether_dhost[4];
if (opts & MAC_PROMISC)
return true;
if ((*dhost4 == 0xFFFFFFFF) && (*dhost2 == 0xFFFF)) {
if (opts & MAC_BCAST) {
adapter->rcv_broadcasts++;
return true;
} else {
return false;
}
}
if (ether_frame->ether_dhost[0] & 0x01) {
if (opts & MAC_ALLMCAST) {
adapter->rcv_multicasts++;
netdev->stats.multicast++;
return true;
}
if (opts & MAC_MCAST) {
struct mcast_address *mcaddr = adapter->mcastaddrs;
while (mcaddr) {
if (!compare_ether_addr(mcaddr->address,
ether_frame->ether_dhost)) {
adapter->rcv_multicasts++;
netdev->stats.multicast++;
return true;
}
mcaddr = mcaddr->next;
}
return false;
} else {
return false;
}
}
if (opts & MAC_DIRECTED) {
adapter->rcv_unicasts++;
return true;
}
return false;
}
static int slic_mac_set_address(struct net_device *dev, void *ptr)
{
struct adapter *adapter = netdev_priv(dev);
struct sockaddr *addr = ptr;
if (netif_running(dev))
return -EBUSY;
if (!adapter)
return -EBUSY;
if (!is_valid_ether_addr(addr->sa_data))
return -EINVAL;
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
slic_config_set(adapter, true);
return 0;
}
static void slic_timer_load_check(ulong cardaddr)
{
struct sliccard *card = (struct sliccard *)cardaddr;
struct adapter *adapter = card->master;
u32 __iomem *intagg;
u32 load = card->events;
u32 level = 0;
intagg = &adapter->slic_regs->slic_intagg;
if ((adapter) && (adapter->state == ADAPT_UP) &&
(card->state == CARD_UP) && (slic_global.dynamic_intagg)) {
if (adapter->devid == SLIC_1GB_DEVICE_ID) {
if (adapter->linkspeed == LINK_1000MB)
level = 100;
else {
if (load > SLIC_LOAD_5)
level = SLIC_INTAGG_5;
else if (load > SLIC_LOAD_4)
level = SLIC_INTAGG_4;
else if (load > SLIC_LOAD_3)
level = SLIC_INTAGG_3;
else if (load > SLIC_LOAD_2)
level = SLIC_INTAGG_2;
else if (load > SLIC_LOAD_1)
level = SLIC_INTAGG_1;
else
level = SLIC_INTAGG_0;
}
if (card->loadlevel_current != level) {
card->loadlevel_current = level;
slic_reg32_write(intagg, level, FLUSH);
}
} else {
if (load > SLIC_LOAD_5)
level = SLIC_INTAGG_5;
else if (load > SLIC_LOAD_4)
level = SLIC_INTAGG_4;
else if (load > SLIC_LOAD_3)
level = SLIC_INTAGG_3;
else if (load > SLIC_LOAD_2)
level = SLIC_INTAGG_2;
else if (load > SLIC_LOAD_1)
level = SLIC_INTAGG_1;
else
level = SLIC_INTAGG_0;
if (card->loadlevel_current != level) {
card->loadlevel_current = level;
slic_reg32_write(intagg, level, FLUSH);
}
}
}
card->events = 0;
card->loadtimer.expires = jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
add_timer(&card->loadtimer);
}
static int slic_upr_queue_request(struct adapter *adapter,
u32 upr_request,
u32 upr_data,
u32 upr_data_h,
u32 upr_buffer, u32 upr_buffer_h)
{
struct slic_upr *upr;
struct slic_upr *uprqueue;
upr = kmalloc(sizeof(struct slic_upr), GFP_ATOMIC);
if (!upr)
return -ENOMEM;