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8250_pci.c
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/*
* linux/drivers/char/8250_pci.c
*
* Probe module for 8250/16550-type PCI serial ports.
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/8250_pci.h>
#include <linux/bitops.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include "8250.h"
#undef SERIAL_DEBUG_PCI
/*
* init function returns:
* > 0 - number of ports
* = 0 - use board->num_ports
* < 0 - error
*/
struct pci_serial_quirk {
u32 vendor;
u32 device;
u32 subvendor;
u32 subdevice;
int (*init)(struct pci_dev *dev);
int (*setup)(struct serial_private *,
const struct pciserial_board *,
struct uart_port *, int);
void (*exit)(struct pci_dev *dev);
};
#define PCI_NUM_BAR_RESOURCES 6
struct serial_private {
struct pci_dev *dev;
unsigned int nr;
void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
struct pci_serial_quirk *quirk;
int line[0];
};
static void moan_device(const char *str, struct pci_dev *dev)
{
printk(KERN_WARNING
"%s: %s\n"
"Please send the output of lspci -vv, this\n"
"message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
"manufacturer and name of serial board or\n"
"modem board to rmk+serial@arm.linux.org.uk.\n",
pci_name(dev), str, dev->vendor, dev->device,
dev->subsystem_vendor, dev->subsystem_device);
}
static int
setup_port(struct serial_private *priv, struct uart_port *port,
int bar, int offset, int regshift)
{
struct pci_dev *dev = priv->dev;
unsigned long base, len;
if (bar >= PCI_NUM_BAR_RESOURCES)
return -EINVAL;
base = pci_resource_start(dev, bar);
if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
len = pci_resource_len(dev, bar);
if (!priv->remapped_bar[bar])
priv->remapped_bar[bar] = ioremap_nocache(base, len);
if (!priv->remapped_bar[bar])
return -ENOMEM;
port->iotype = UPIO_MEM;
port->iobase = 0;
port->mapbase = base + offset;
port->membase = priv->remapped_bar[bar] + offset;
port->regshift = regshift;
} else {
port->iotype = UPIO_PORT;
port->iobase = base + offset;
port->mapbase = 0;
port->membase = NULL;
port->regshift = 0;
}
return 0;
}
/*
* ADDI-DATA GmbH communication cards <info@addi-data.com>
*/
static int addidata_apci7800_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar = 0, offset = board->first_offset;
bar = FL_GET_BASE(board->flags);
if (idx < 2) {
offset += idx * board->uart_offset;
} else if ((idx >= 2) && (idx < 4)) {
bar += 1;
offset += ((idx - 2) * board->uart_offset);
} else if ((idx >= 4) && (idx < 6)) {
bar += 2;
offset += ((idx - 4) * board->uart_offset);
} else if (idx >= 6) {
bar += 3;
offset += ((idx - 6) * board->uart_offset);
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* AFAVLAB uses a different mixture of BARs and offsets
* Not that ugly ;) -- HW
*/
static int
afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
bar = FL_GET_BASE(board->flags);
if (idx < 4)
bar += idx;
else {
bar = 4;
offset += (idx - 4) * board->uart_offset;
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* HP's Remote Management Console. The Diva chip came in several
* different versions. N-class, L2000 and A500 have two Diva chips, each
* with 3 UARTs (the third UART on the second chip is unused). Superdome
* and Keystone have one Diva chip with 3 UARTs. Some later machines have
* one Diva chip, but it has been expanded to 5 UARTs.
*/
static int pci_hp_diva_init(struct pci_dev *dev)
{
int rc = 0;
switch (dev->subsystem_device) {
case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
case PCI_DEVICE_ID_HP_DIVA_EVEREST:
rc = 3;
break;
case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
rc = 2;
break;
case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
rc = 4;
break;
case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
rc = 1;
break;
}
return rc;
}
/*
* HP's Diva chip puts the 4th/5th serial port further out, and
* some serial ports are supposed to be hidden on certain models.
*/
static int
pci_hp_diva_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int offset = board->first_offset;
unsigned int bar = FL_GET_BASE(board->flags);
switch (priv->dev->subsystem_device) {
case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
if (idx == 3)
idx++;
break;
case PCI_DEVICE_ID_HP_DIVA_EVEREST:
if (idx > 0)
idx++;
if (idx > 2)
idx++;
break;
}
if (idx > 2)
offset = 0x18;
offset += idx * board->uart_offset;
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* Added for EKF Intel i960 serial boards
*/
static int pci_inteli960ni_init(struct pci_dev *dev)
{
unsigned long oldval;
if (!(dev->subsystem_device & 0x1000))
return -ENODEV;
/* is firmware started? */
pci_read_config_dword(dev, 0x44, (void *)&oldval);
if (oldval == 0x00001000L) { /* RESET value */
printk(KERN_DEBUG "Local i960 firmware missing");
return -ENODEV;
}
return 0;
}
/*
* Some PCI serial cards using the PLX 9050 PCI interface chip require
* that the card interrupt be explicitly enabled or disabled. This
* seems to be mainly needed on card using the PLX which also use I/O
* mapped memory.
*/
static int pci_plx9050_init(struct pci_dev *dev)
{
u8 irq_config;
void __iomem *p;
if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar 0", dev);
return 0;
}
irq_config = 0x41;
if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
irq_config = 0x43;
if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
(dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
/*
* As the megawolf cards have the int pins active
* high, and have 2 UART chips, both ints must be
* enabled on the 9050. Also, the UARTS are set in
* 16450 mode by default, so we have to enable the
* 16C950 'enhanced' mode so that we can use the
* deep FIFOs
*/
irq_config = 0x5b;
/*
* enable/disable interrupts
*/
p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
if (p == NULL)
return -ENOMEM;
writel(irq_config, p + 0x4c);
/*
* Read the register back to ensure that it took effect.
*/
readl(p + 0x4c);
iounmap(p);
return 0;
}
static void __devexit pci_plx9050_exit(struct pci_dev *dev)
{
u8 __iomem *p;
if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
return;
/*
* disable interrupts
*/
p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
if (p != NULL) {
writel(0, p + 0x4c);
/*
* Read the register back to ensure that it took effect.
*/
readl(p + 0x4c);
iounmap(p);
}
}
#define NI8420_INT_ENABLE_REG 0x38
#define NI8420_INT_ENABLE_BIT 0x2000
static void __devexit pci_ni8420_exit(struct pci_dev *dev)
{
void __iomem *p;
unsigned long base, len;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return;
}
base = pci_resource_start(dev, bar);
len = pci_resource_len(dev, bar);
p = ioremap_nocache(base, len);
if (p == NULL)
return;
/* Disable the CPU Interrupt */
writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
p + NI8420_INT_ENABLE_REG);
iounmap(p);
}
/* MITE registers */
#define MITE_IOWBSR1 0xc4
#define MITE_IOWCR1 0xf4
#define MITE_LCIMR1 0x08
#define MITE_LCIMR2 0x10
#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
static void __devexit pci_ni8430_exit(struct pci_dev *dev)
{
void __iomem *p;
unsigned long base, len;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return;
}
base = pci_resource_start(dev, bar);
len = pci_resource_len(dev, bar);
p = ioremap_nocache(base, len);
if (p == NULL)
return;
/* Disable the CPU Interrupt */
writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
iounmap(p);
}
/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
static int
sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
bar = 0;
if (idx < 4) {
/* first four channels map to 0, 0x100, 0x200, 0x300 */
offset += idx * board->uart_offset;
} else if (idx < 8) {
/* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
offset += idx * board->uart_offset + 0xC00;
} else /* we have only 8 ports on PMC-OCTALPRO */
return 1;
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* This does initialization for PMC OCTALPRO cards:
* maps the device memory, resets the UARTs (needed, bc
* if the module is removed and inserted again, the card
* is in the sleep mode) and enables global interrupt.
*/
/* global control register offset for SBS PMC-OctalPro */
#define OCT_REG_CR_OFF 0x500
static int sbs_init(struct pci_dev *dev)
{
u8 __iomem *p;
p = pci_ioremap_bar(dev, 0);
if (p == NULL)
return -ENOMEM;
/* Set bit-4 Control Register (UART RESET) in to reset the uarts */
writeb(0x10, p + OCT_REG_CR_OFF);
udelay(50);
writeb(0x0, p + OCT_REG_CR_OFF);
/* Set bit-2 (INTENABLE) of Control Register */
writeb(0x4, p + OCT_REG_CR_OFF);
iounmap(p);
return 0;
}
/*
* Disables the global interrupt of PMC-OctalPro
*/
static void __devexit sbs_exit(struct pci_dev *dev)
{
u8 __iomem *p;
p = pci_ioremap_bar(dev, 0);
/* FIXME: What if resource_len < OCT_REG_CR_OFF */
if (p != NULL)
writeb(0, p + OCT_REG_CR_OFF);
iounmap(p);
}
/*
* SIIG serial cards have an PCI interface chip which also controls
* the UART clocking frequency. Each UART can be clocked independently
* (except cards equiped with 4 UARTs) and initial clocking settings
* are stored in the EEPROM chip. It can cause problems because this
* version of serial driver doesn't support differently clocked UART's
* on single PCI card. To prevent this, initialization functions set
* high frequency clocking for all UART's on given card. It is safe (I
* hope) because it doesn't touch EEPROM settings to prevent conflicts
* with other OSes (like M$ DOS).
*
* SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
*
* There is two family of SIIG serial cards with different PCI
* interface chip and different configuration methods:
* - 10x cards have control registers in IO and/or memory space;
* - 20x cards have control registers in standard PCI configuration space.
*
* Note: all 10x cards have PCI device ids 0x10..
* all 20x cards have PCI device ids 0x20..
*
* There are also Quartet Serial cards which use Oxford Semiconductor
* 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
*
* Note: some SIIG cards are probed by the parport_serial object.
*/
#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
static int pci_siig10x_init(struct pci_dev *dev)
{
u16 data;
void __iomem *p;
switch (dev->device & 0xfff8) {
case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
data = 0xffdf;
break;
case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
data = 0xf7ff;
break;
default: /* 1S1P, 4S */
data = 0xfffb;
break;
}
p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
if (p == NULL)
return -ENOMEM;
writew(readw(p + 0x28) & data, p + 0x28);
readw(p + 0x28);
iounmap(p);
return 0;
}
#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
static int pci_siig20x_init(struct pci_dev *dev)
{
u8 data;
/* Change clock frequency for the first UART. */
pci_read_config_byte(dev, 0x6f, &data);
pci_write_config_byte(dev, 0x6f, data & 0xef);
/* If this card has 2 UART, we have to do the same with second UART. */
if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
pci_read_config_byte(dev, 0x73, &data);
pci_write_config_byte(dev, 0x73, data & 0xef);
}
return 0;
}
static int pci_siig_init(struct pci_dev *dev)
{
unsigned int type = dev->device & 0xff00;
if (type == 0x1000)
return pci_siig10x_init(dev);
else if (type == 0x2000)
return pci_siig20x_init(dev);
moan_device("Unknown SIIG card", dev);
return -ENODEV;
}
static int pci_siig_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
if (idx > 3) {
bar = 4;
offset = (idx - 4) * 8;
}
return setup_port(priv, port, bar, offset, 0);
}
/*
* Timedia has an explosion of boards, and to avoid the PCI table from
* growing *huge*, we use this function to collapse some 70 entries
* in the PCI table into one, for sanity's and compactness's sake.
*/
static const unsigned short timedia_single_port[] = {
0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
};
static const unsigned short timedia_dual_port[] = {
0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
0xD079, 0
};
static const unsigned short timedia_quad_port[] = {
0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
0xB157, 0
};
static const unsigned short timedia_eight_port[] = {
0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
};
static const struct timedia_struct {
int num;
const unsigned short *ids;
} timedia_data[] = {
{ 1, timedia_single_port },
{ 2, timedia_dual_port },
{ 4, timedia_quad_port },
{ 8, timedia_eight_port }
};
static int pci_timedia_init(struct pci_dev *dev)
{
const unsigned short *ids;
int i, j;
for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
ids = timedia_data[i].ids;
for (j = 0; ids[j]; j++)
if (dev->subsystem_device == ids[j])
return timedia_data[i].num;
}
return 0;
}
/*
* Timedia/SUNIX uses a mixture of BARs and offsets
* Ugh, this is ugly as all hell --- TYT
*/
static int
pci_timedia_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar = 0, offset = board->first_offset;
switch (idx) {
case 0:
bar = 0;
break;
case 1:
offset = board->uart_offset;
bar = 0;
break;
case 2:
bar = 1;
break;
case 3:
offset = board->uart_offset;
/* FALLTHROUGH */
case 4: /* BAR 2 */
case 5: /* BAR 3 */
case 6: /* BAR 4 */
case 7: /* BAR 5 */
bar = idx - 2;
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* Some Titan cards are also a little weird
*/
static int
titan_400l_800l_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
switch (idx) {
case 0:
bar = 1;
break;
case 1:
bar = 2;
break;
default:
bar = 4;
offset = (idx - 2) * board->uart_offset;
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
static int pci_xircom_init(struct pci_dev *dev)
{
msleep(100);
return 0;
}
static int pci_ni8420_init(struct pci_dev *dev)
{
void __iomem *p;
unsigned long base, len;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return 0;
}
base = pci_resource_start(dev, bar);
len = pci_resource_len(dev, bar);
p = ioremap_nocache(base, len);
if (p == NULL)
return -ENOMEM;
/* Enable CPU Interrupt */
writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
p + NI8420_INT_ENABLE_REG);
iounmap(p);
return 0;
}
#define MITE_IOWBSR1_WSIZE 0xa
#define MITE_IOWBSR1_WIN_OFFSET 0x800
#define MITE_IOWBSR1_WENAB (1 << 7)
#define MITE_LCIMR1_IO_IE_0 (1 << 24)
#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
static int pci_ni8430_init(struct pci_dev *dev)
{
void __iomem *p;
unsigned long base, len;
u32 device_window;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return 0;
}
base = pci_resource_start(dev, bar);
len = pci_resource_len(dev, bar);
p = ioremap_nocache(base, len);
if (p == NULL)
return -ENOMEM;
/* Set device window address and size in BAR0 */
device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
| MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
writel(device_window, p + MITE_IOWBSR1);
/* Set window access to go to RAMSEL IO address space */
writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
p + MITE_IOWCR1);
/* Enable IO Bus Interrupt 0 */
writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
/* Enable CPU Interrupt */
writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
iounmap(p);
return 0;
}
/* UART Port Control Register */
#define NI8430_PORTCON 0x0f
#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
static int
pci_ni8430_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
void __iomem *p;
unsigned long base, len;
unsigned int bar, offset = board->first_offset;
if (idx >= board->num_ports)
return 1;
bar = FL_GET_BASE(board->flags);
offset += idx * board->uart_offset;
base = pci_resource_start(priv->dev, bar);
len = pci_resource_len(priv->dev, bar);
p = ioremap_nocache(base, len);
/* enable the transciever */
writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
p + offset + NI8430_PORTCON);
iounmap(p);
return setup_port(priv, port, bar, offset, board->reg_shift);
}
static int pci_netmos_init(struct pci_dev *dev)
{
/* subdevice 0x00PS means <P> parallel, <S> serial */
unsigned int num_serial = dev->subsystem_device & 0xf;
if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
(dev->device == PCI_DEVICE_ID_NETMOS_9865))
return 0;
if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
dev->subsystem_device == 0x0299)
return 0;
if (num_serial == 0)
return -ENODEV;
return num_serial;
}
/*
* These chips are available with optionally one parallel port and up to
* two serial ports. Unfortunately they all have the same product id.
*
* Basic configuration is done over a region of 32 I/O ports. The base
* ioport is called INTA or INTC, depending on docs/other drivers.
*
* The region of the 32 I/O ports is configured in POSIO0R...
*/
/* registers */
#define ITE_887x_MISCR 0x9c
#define ITE_887x_INTCBAR 0x78
#define ITE_887x_UARTBAR 0x7c
#define ITE_887x_PS0BAR 0x10
#define ITE_887x_POSIO0 0x60
/* I/O space size */
#define ITE_887x_IOSIZE 32
/* I/O space size (bits 26-24; 8 bytes = 011b) */
#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
/* I/O space size (bits 26-24; 32 bytes = 101b) */
#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
#define ITE_887x_POSIO_SPEED (3 << 29)
/* enable IO_Space bit */
#define ITE_887x_POSIO_ENABLE (1 << 31)
static int pci_ite887x_init(struct pci_dev *dev)
{
/* inta_addr are the configuration addresses of the ITE */
static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
0x200, 0x280, 0 };
int ret, i, type;
struct resource *iobase = NULL;
u32 miscr, uartbar, ioport;
/* search for the base-ioport */
i = 0;
while (inta_addr[i] && iobase == NULL) {
iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
"ite887x");
if (iobase != NULL) {
/* write POSIO0R - speed | size | ioport */
pci_write_config_dword(dev, ITE_887x_POSIO0,
ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
/* write INTCBAR - ioport */
pci_write_config_dword(dev, ITE_887x_INTCBAR,
inta_addr[i]);
ret = inb(inta_addr[i]);
if (ret != 0xff) {
/* ioport connected */
break;
}
release_region(iobase->start, ITE_887x_IOSIZE);
iobase = NULL;
}
i++;
}
if (!inta_addr[i]) {
printk(KERN_ERR "ite887x: could not find iobase\n");
return -ENODEV;
}
/* start of undocumented type checking (see parport_pc.c) */
type = inb(iobase->start + 0x18) & 0x0f;
switch (type) {
case 0x2: /* ITE8871 (1P) */
case 0xa: /* ITE8875 (1P) */
ret = 0;
break;
case 0xe: /* ITE8872 (2S1P) */
ret = 2;
break;
case 0x6: /* ITE8873 (1S) */
ret = 1;
break;
case 0x8: /* ITE8874 (2S) */
ret = 2;
break;
default:
moan_device("Unknown ITE887x", dev);
ret = -ENODEV;
}
/* configure all serial ports */
for (i = 0; i < ret; i++) {
/* read the I/O port from the device */
pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
&ioport);
ioport &= 0x0000FF00; /* the actual base address */
pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
ITE_887x_POSIO_IOSIZE_8 | ioport);
/* write the ioport to the UARTBAR */
pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
uartbar |= (ioport << (16 * i)); /* set the ioport */
pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
/* get current config */
pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
/* disable interrupts (UARTx_Routing[3:0]) */
miscr &= ~(0xf << (12 - 4 * i));
/* activate the UART (UARTx_En) */
miscr |= 1 << (23 - i);
/* write new config with activated UART */
pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
}
if (ret <= 0) {
/* the device has no UARTs if we get here */
release_region(iobase->start, ITE_887x_IOSIZE);
}
return ret;
}
static void __devexit pci_ite887x_exit(struct pci_dev *dev)
{
u32 ioport;
/* the ioport is bit 0-15 in POSIO0R */
pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
ioport &= 0xffff;
release_region(ioport, ITE_887x_IOSIZE);
}
/*
* Oxford Semiconductor Inc.
* Check that device is part of the Tornado range of devices, then determine
* the number of ports available on the device.
*/
static int pci_oxsemi_tornado_init(struct pci_dev *dev)
{
u8 __iomem *p;
unsigned long deviceID;
unsigned int number_uarts = 0;
/* OxSemi Tornado devices are all 0xCxxx */
if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
(dev->device & 0xF000) != 0xC000)
return 0;
p = pci_iomap(dev, 0, 5);
if (p == NULL)
return -ENOMEM;
deviceID = ioread32(p);
/* Tornado device */
if (deviceID == 0x07000200) {
number_uarts = ioread8(p + 4);
printk(KERN_DEBUG
"%d ports detected on Oxford PCI Express device\n",
number_uarts);
}
pci_iounmap(dev, p);
return number_uarts;
}
static int
pci_default_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
unsigned int bar, offset = board->first_offset, maxnr;
bar = FL_GET_BASE(board->flags);
if (board->flags & FL_BASE_BARS)
bar += idx;
else
offset += idx * board->uart_offset;
maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
(board->reg_shift + 3);
if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
return 1;
return setup_port(priv, port, bar, offset, board->reg_shift);
}
static int skip_tx_en_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
{
port->flags |= UPF_NO_TXEN_TEST;
printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
"[%04x:%04x] subsystem [%04x:%04x]\n",
priv->dev->vendor,
priv->dev->device,
priv->dev->subsystem_vendor,
priv->dev->subsystem_device);
return pci_default_setup(priv, board, port, idx);
}
/* This should be in linux/pci_ids.h */
#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
#define PCI_DEVICE_ID_OCTPRO 0x0001
#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
#define PCI_VENDOR_ID_ADVANTECH 0x13fe
#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
/*
* Master list of serial port init/setup/exit quirks.
* This does not describe the general nature of the port.
* (ie, baud base, number and location of ports, etc)
*
* This list is ordered alphabetically by vendor then device.
* Specific entries must come before more generic entries.
*/
static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
/*
* ADDI-DATA GmbH communication cards <info@addi-data.com>
*/