- Also, indicates the test coverage .
- SBSA L3 rules which are common in BSA and SBSA checklist covered by BSA-ACS.
- For details on test algorithm,unimplemented rule coverage refer Test Scenario document.
Test Number | Component | Level | Rule ID | Test Description | Verified by ACS | Test Environment |
---|---|---|---|---|---|---|
1 | PE | L3 | S_L3PE_01 | Check PE Granule Support | yes | UEFI App |
2 | PE | L3 | S_L3PE_02 | Check for 16-bit ASID support | yes | UEFI App |
3 | PE | L3 | S_L3PE_03 | Check AARCH64 implementation | yes | UEFI App |
4 | PE | L3 | S_L3PE_04 | Check FEAT_LPA Requirements | yes | UEFI App |
5 | PE | L4 | S_L4PE_01 | Check for RAS extension | yes | UEFI App |
6 | PE | L4 | S_L4PE_02 | Check DC CVAP support | yes | UEFI App |
7 | PE | L4 | S_L4PE_03 | Check for 16-Bit VMID | yes | UEFI App |
8 | PE | L4 | S_L4PE_04 | Check for Virtual host extensions | yes | UEFI App |
9 | PE | L5 | S_L5PE_01 | Support Page table map size change | yes | UEFI App |
10 | PE | L5 | S_L5PE_02 | Check for pointer signing | yes | UEFI App |
11 | PE | L5 | S_L5PE_04 | Check Activity monitors extension | yes | UEFI App |
12 | PE | L5 | S_L5PE_05 | Check for SHA3 and SHA512 support | yes | UEFI App |
13 | PE | L5 | S_L5PE_06 | Stage 2 control of mem and cache | yes | UEFI App |
14 | PE | L5 | S_L5PE_07 | Check for nested virtualization | yes | UEFI App |
15 | PE | L5 | S_MPAM_PE | Check MPAM PE Requirements | yes | UEFI App |
16 | PE | L5 | S_MPAM_PE | Check MPAM LLC Requirements | yes | UEFI App |
17 | PE | L6 | B_PE_17 | Check SPE if implemented | no | UEFI App |
18 | PE | L6 | S_L6PE_02 | Check Branch Target Support | yes | UEFI App |
19 | PE | L6 | S_L6PE_03 | Check Protect Against Timing Fault | yes | UEFI App |
20 | PE | L6 | S_L6PE_04 | Check PMU Version Support | yes | UEFI App |
21 | PE | L6 | S_L6PE_05 | Check AccessFlag DirtyState Update | yes | UEFI App |
22 | PE | L6 | S_L6PE_06 | Check Enhanced Virtualization Tra | yes | UEFI App |
23 | PE | L6 | B_SEC_01 | Check Speculation Restriction | yes | UEFI App |
24 | PE | L6 | B_SEC_02 | Check Speculative Str Bypass Safe | yes | UEFI App |
25 | PE | L6 | B_SEC_03 | Check PEs Impl CSDB,SSBB,PSSBB | yes | UEFI App |
26 | PE | L6 | B_SEC_04 | Check PEs Implement SB Barrier | yes | UEFI App |
27 | PE | L6 | B_SEC_05 | Check PE Impl CFP,DVP,CPP RCTX | yes | UEFI App |
28 | PE | L7 | S_L7PE_01 | Check Fine Grain Trap Support | yes | UEFI App |
29 | PE | L7 | S_L7PE_02 | Check for ECV support | yes | UEFI App |
30 | PE | L7 | S_L7PE_03 | Check for AMU Support | yes | UEFI App |
31 | PE | L7 | S_L7PE_04 | Checks ASIMD Int8 matrix multiplc | yes | UEFI App |
32 | PE | L7 | S_L7PE_05 | Check for BFLOAT16 extension | yes | UEFI App |
33 | PE | L7 | S_L7PE_06 | Check for EnhancedPAC2 and FPAC | yes | UEFI App |
34 | PE | L7 | S_L7PE_07 | Check for SVE Int8 matrix multiplc | yes | UEFI App |
35 | PE | L7 | S_L7PE_08 | Check for data gathering hint | yes | UEFI App |
36 | PE | L7 | S_L7PE_09 | Check WFE Fine tune delay feature | yes | UEFI App |
37 | PE | L7 | S_L7PE_10 | Check for enhanced PAN feature | yes | UEFI App |
101 | MEMORY | L3 | S_L3MM_01, S_L3MM_02 | Check peripherals addr 64Kb apart | yes | UEFI App |
201 | GICv3 | L3 | S_L3GI_01 | Check GIC version | yes | UEFI App |
202 | GICv3 | L5 | S_L5PP_01 | Check Reserved PPI Assignments | yes | UEFI App |
301 | SMMU | L3 | S_L3SM_01 | SMMU Version Check | yes | UEFI App |
302 | SMMU | L4 | S_L4SM_01, S_L4SM_02, S_L5SM_01, S_L5SM_02 | SMMU Compatibility Check | yes | UEFI App |
302 | SMMU | L5 | S_L5SM_01, S_L5SM_02 | SMMU Compatibility Check | yes | UEFI App |
303 | SMMU | L5 | B_SMMU_09 | SMMU revision and S-EL2 support | yes | UEFI App |
304 | SMMU | L5 | B_SMMU_20 | SMMU Revision,S-EL2 support Hyp | yes | UEFI App |
305 | SMMU | L6 | S_L6SM_01 | Check SMMU Coherent Access Support | yes | UEFI App |
306 | SMMU | L6 | S_L6SM_02 | Check SMMU HTTU Support | yes | UEFI App |
307 | SMMU | L6 | S_L6SM_03 | Check SMMU MSI Support | yes | UEFI App |
308 | SMMU | L6 | B_SMMU_23 | Check SMMU 16 Bit VMID Support | yes | UEFI App |
309 | SMMU | L6 | B_SMMU_03 | Check Large Virtual Addr Support | yes | UEFI App |
310 | SMMU | L6 | B_SMMU_04, B_SMMU_05 | Check TLB Range Invalidation | yes | UEFI App |
311 | SMMU | L6 | B_SMMU_13 | Check SMMU 16 Bit ASID Support | yes | UEFI App |
312 | SMMU | L6 | B_SMMU_14 | Check SMMU Endianess Support | yes | UEFI App |
313 | SMMU | L7 | S_L7SM_01 | Check if all DMA reqs behind SMMU | yes | UEFI App |
314 | SMMU | L7 | S_L7SM_03, S_L7SM_04 | Check SMMUv3 PMU Extension | yes | UEFI App |
315 | SMMU | L7 | S_L7SM_11, S_L7SM_22 | Check system for MPAM support | yes | UEFI App |
316 | SMMU | L7 | S_L7SM_02 | Check for SMMU/CATU in ETR Path | yes | Linux App |
701 | Watchdog | L6 | S_L6WD_01 | Check NS Watchdog Revision | yes | UEFI App |
801 | PCIe | L6 | PCI_IN_01 | Check ECAM Presence | yes | UEFI App |
803 | PCIe | L6 | PCI_IN_02 | Check ECAM Memory accessibility | yes | UEFI App |
805 | PCIe | L6 | PCI_MM_01, PCI_MM_02, PCI_MM_03, RE_BAR_2 | PCIe Unaligned access, Norm mem | yes | Linux App |
809 | GICv3 | L6 | S_L3GI_02 | Check all MSI(X) vectors are LPIs | yes | Linux App |
820 | PCIe | L6 | RE_REG_1, RE_REC_1, RE_REC_2 | heck Type 0/1 common config rules | yes | UEFI App |
821 | PCIe | L6 | RE_REG_1, RE_REC_1, RE_REC_2 | Check Type 0 config header rules | yes | UEFI App |
822 | PCIe | L6 | RE_REC_1, RE_REC_2 | heck Type 1 config header rules | yes | UEFI App |
823 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check PCIe capability rules | yes | UEFI App |
824 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device capabilites reg rules | yes | UEFI App |
825 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device Control register rule | yes | UEFI App |
826 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device cap 2 register rules | yes | UEFI App |
827 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device control 2 reg rules | yes | UEFI App |
828 | PCIe | L6 | RE_REG_2, RE_REC_1, RE_REC_2 | Check Power management cap rules | yes | UEFI App |
829 | PCIe | L6 | RE_REG_2, RE_REC_1, RE_REC_2 | Check Power management/status rule | yes | UEFI App |
830 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check Cmd Reg memory space enable | yes | UEFI App |
831 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check Type0/1 BIST Register rule | yes | UEFI App |
832 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check HDR CapPtr Register rule | yes | UEFI App |
833 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check Max payload size supported | yes | UEFI App |
834 | PCIe | L6 | RE_BAR_3 | Check BAR memory space & Type rule | yes | UEFI App |
835 | PCIe | L6 | RE_RST_1, PCI_SM_02 | Check Function level reset rule | yes | UEFI App |
836 | PCIe | L6 | PCI_IN_17 | Check ARI forwarding support rule | yes | UEFI App |
837 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check OBFF supported rule | yes | UEFI App |
838 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check CTRS and CTDS rule | yes | UEFI App |
839 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check i-EP atomicop rule | yes | UEFI App |
841 | PCIe | L6 | RE_INT_1, IE_INT_1 | Check MSI and MSI-X support rule | yes | UEFI App |
842 | PCIe | L6 | RE_PWR_1 | Check Power Management rules | yes | UEFI App |
843 | PCIe | L6 | PCI_IN_17 | Check ARI forwarding enable rule | yes | UEFI App |
844 | PCIe | L6 | PCI_IN_04 | Check device under RP in same ECAM | yes | UEFI App |
845 | PCIe | L6 | PCI_IN_03 | Check all RP in HB is in same ECAM | yes | UEFI App |
846 | PCIe | L6 | PCI_IN_18 | Check RP Byte Enable Rules | yes | UEFI App |
847 | PCIe | L6 | PCI_IN_12 | Check Config Txn for RP in HB | yes | UEFI App |
848 | PCIe | L6 | PCI_IN_13 | Check RootPort NP Memory Access | yes | UEFI App |
849 | PCIe | L6 | PCI_IN_13 | Check RootPort P Memory Access | yes | UEFI App |
850 | PCIe | L6 | PCI_LI_01, PCI_LI_03 | Check L-Intr SPI Level-Sensitive | yes | UEFI App |
851 | PCIe | L6 | IE_RST_2 | Check Sec Bus Reset For iEP_RP | yes | UEFI App |
852 | PCIe | L6 | RE_SMU_2 | Check ATS Support Rule | yes | UEFI App |
856 | PCIe | L6 | IE_ACS_2 | Check iEP-RootPort P2P Support | yes | UEFI App |
857 | PCIe | L6 | IE_ACS_1 | Check RCiEP, iEP_EP P2P Supp | yes | UEFI App |
858 | PCIe | L6 | RE_BAR_1 | Read and write to RCiEP BAR reg | yes | UEFI App |
859 | PCIe | L6 | RE_PCI_2 | Check RCEC Class code and Ext Cap | yes | UEFI App |
860 | PCIe | L6 | RE_PCI_1 | Check RCiEP Hdr type & link Cap | yes | UEFI App |
861 | PCIe | L7 | S_PCIe_02 | Check RootPort P & NP Memory Access | no | UEFI App |
862 | PCIe | L4 | S_L4PCI_2 | Check EA Capability | yes | UEFI App |
863 | PCIe | L6 | IE_REG_4 | Slot Cap, Control and Status register rules | yes | UEFI App |
902 | PCIe | L4 | PCI_MM_01, PCI_MM_02, PCI_MM_03 | PCIe Memory access check | yes | UEFI App |
903 | PCIe | L4 | RE_SMU_2 | PCIe Address translation check | yes | UEFI App |
904 | PCIe | L4 | PCI_PAS_1, RE_SMU_4 | Generate PASID PCIe transactions | yes | UEFI App |
905 | PCIe | L4 | IE_REG_3, PCI_IN_05 | Check BME functionality of RP | yes | UEFI App |
906 | PCIe | L4 | RE_SMU_2 | ATS Functionality Check | yes | UEFI App |
907 | PCIe | L4 | RE_ORD_1, RE_ORD_2 | Arrival order & Gathering Check | yes | UEFI App |
908 | PCIe | L7 | S_PCIe_03 | PE 2/4/8B writes tp PCIe as 2/4/8B | yes | UEFI App |
909 | PCIe | L7 | PCI_ER_01, PCI_ER_02, PCI_ER_03 | RP's must support AER feature | yes | UEFI App |
910 | PCIe | L7 | PCI_ER_05, PCI_ER_06 | RP's must support DPC | yes | UEFI App |
911 | PCIe | L7 | S_PCIe_04 | Check 2/4/8 Bytes targeted writes | yes | UEFI App |
1001 | MPAM | L7 | S_L7MP_01, S_L7MP_02 | Check for MPAM extension | yes | UEFI App |
1002 | MPAM | L7 | S_L7MP_03, S_L7MP_04 | Check for MPAM LLC CSU | yes | UEFI App |
1003 | MPAM | L7 | S_L7MP_05, S_L7MP_06 | Check for MPAM MBWUs Monitor func | yes | UEFI App |
1004 | MPAM | L7 | S_L7MP_07 | Check for MBWU counter size | yes | UEFI App |
1005 | MPAM | L7 | S_L7MP_08 | Check for MPAM MSC address overlap | yes | UEFI App |
1006 | MPAM | L7 | S_L7MP_03 | Check PMG storage by CPOR nodes | yes | UEFI App |
1101 | PMU | L7 | PMU_PE_02 | Check PMU Overflow signal | yes | UEFI App |
1102 | PMU | L7 | PMU_PE_03 | Check number of PMU counters | yes | UEFI App |
1103 | PMU | L7 | PMU_EV_11 | Check for multi-threaded PMU ext | yes | UEFI App |
1104 | PMU | L7 | PMU_BM_1, PMU_SYS_1, PMU_SYS_2 | Check memory bandwidth monitors | yes | UEFI App |
1105 | PMU | L7 | PMU_MEM_1, PMU_SYS_1, PMU_SYS_2 | Check memory latency monitors | yes | UEFI App |
1106 | PMU | L7 | PMU_SPE | Check for PMU SPE Requirements | yes | UEFI App |
1107 | PMU | L7 | PMU_BM_2, PMU_SYS_1, PMU_SYS_2 | Check PCIe bandwidth monitors | yes | UEFI App |
1108 | PMU | L7 | PMU_SYS_5 | Check System PMU for NUMA systems | yes | |
1109 | PMU | L7 | PMU_SYS_6 | Check multiple types of traffic measurement | yes | |
1201 | RAS | L7 | RAS_01 | Check Error Counter | yes | UEFI App |
1202 | RAS | L7 | RAS_02 | Check CFI, DUI, UI Controls | yes | UEFI App |
1203 | RAS | L7 | RAS_03 | Check FHI in Error Record Group | yes | UEFI App |
1204 | RAS | L7 | RAS_04 | Check ERI in Error Record Group | yes | UEFI App |
1205 | RAS | L7 | RAS_06 | Check ERI/FHI Connected to GIC | yes | UEFI App |
1206 | RAS | L7 | RAS_07 | RAS ERRADDR.AI bit status check | yes | UEFI App |
1207 | RAS | L7 | RAS_08 | Check Error Group Status | yes | UEFI App |
1208 | RAS | L7 | RAS_11, RAS_12 | Software Fault Error Check | yes | UEFI App |
1209 | RAS | L7 | S_L7RAS_1 | Data abort on Containable err | yes | UEFI App |
1210 | RAS | L7 | SYS_RAS_1 | Check for patrol scrubbing support | yes | UEFI App |
1211 | RAS | L7 | SYS_RAS_2,SYS_RAS_3 | Check Poison Storage & Forwarding | yes | UEFI App |
1212 | RAS | L7 | SYS_RAS_2 | Check Pseudo Fault Injection | yes | UEFI App |
1301 | Entropy | L7 | S_L7ENT_1 | To support key and nonce generation, a system must have a hardware entropy source. This source must be a true random number generator that is visible to PE software and meets the requirements that are specified in the NIST SP 800-90 series of specifications | yes | UEFI App |
PE | L6 | B_PE_16 | Check for MTE support | yes | Linux App | |
PMU app | PMU | L7 | PMU_EV_01 | PMU PE IPC events | yes | Linux App |
PMU app | PMU | L7 | PMU_EV_02 | PMU PE cache effectiveness events | yes | Linux App |
PMU app | PMU | L7 | PMU_EV_03 | PMU PE TLB effectiveness events | yes | Linux App |
PMU | L7 | PMU_EV_04 | PMU PE demand accesses events | no | ||
PMU app | PMU | L7 | PMU_EV_05 | PMU PE cycle counting events | yes | Linux App |
PMU app | PMU | L7 | PMU_EV_06 | PMU PE top-down accounting events | yes | Linux App |
PMU | L7 | PMU_EV_07 | PMU PE workload events | no | ||
PMU app | PMU | L7 | PMU_EV_08 | PMU PE branch predictor effectiveness events | yes | Linux App |
PMU app | PMU | L7 | PMU_EV_09 | PMU PE BR_RETRIED event | yes | Linux App |
PMU app | PMU | L7 | PMU_EV_09 | PMU PE BR_RETRIED event | yes | Linux App |
PMU app | PMU | L7 | PMU_EV_09 | PMU PE Latency event | yes | Linux App |
BSA acs | GIC | L3 | S_L3PP_01 | The Interrupt IDs must be the same as the recommended values mentioned in Arm BSA | yes | |
SMMU | L3 | S_L3SM_01 | If PEs that are used by the base system support TLB range instructions, then all OS visible requesters that contain a TLB must support range invalidates | no | ||
SMMU | L4 | S_L4SM_03 | The integration of the System MMUs is compliant with the rules in SMMUv3 integration appendix in Arm BSA | no | ||
PCIe | L4 | S_L4PCI_1 | All peripherals that are intended for assignment to a virtual machine or a user space device driver must be based on PCI Express | no | Manual | |
PE | L5 | S_L5PE_03 | PEs that are based on Armv8.4 must implement the requirements of the CS-BSA combination C | no | ||
GIC | L5 | S_L5GI_01 | Only a GIC v3, or higher, interrupt controller will be visible to operating system software. Other forms of interrupt controller, for example interrupt combining or forwarding engines, are not permissible, if they require a platform specific kernel driver | no | ||
TIMER | L5 | S_L5TI_01 | A system that is compatible with level 5 will implement a generic counter which counts in nanosecond units. This means that, to the operating system, the reported frequency will be 1GHz | |||
RAS | L6 | S_RAS_01 | PEs and other system components that implement the Armv8 RAS extension Use Private Peripheral Interrupts for ERI or FHI if the only interface available for a RAS node is System register based | no | ||
PCI | L6 | B_REP_1 | BSA Section F describes the rules required for an RCiEP device | no | ||
PCI | L6 | B_IEP_1 | BSA Section G describes the rules to implement for an i-EP device | no | ||
PE RAS | L7 | S_L7RAS_2 | PE speculative access not result in abort | no | ||
PE TME | L7 | S_L7TME_1 | PEs must implement the MPAM extension. See FEAT_MPAM | no | ||
PE TME | L7 | S_L7TME_2 | PEs must implement a minimum of 16 physical partition IDs | no | ||
PE TME | L7 | S_L7TME_3 | The implementation must provide MPAM Cache Storage Usage monitors for the last-level cache | no | ||
PE TME | L7 | S_L7TME_4 | Last-level cache must provide a minimum of 16 Cache Storage Usage monitors | no | ||
PE TME | L7 | S_L7TME_5 | The implementation must provide MPAM Memory Bandwidth Usage monitors (MBWUs) for the interfaces that provide general purpose memory | no | ||
PCIe | L7 | S_PCIe_01 | The system must support the translation of PE writes with all byte enable patterns to PCIe write requests. The translation must be done in compliance with PCIe byte enable rules | no | ||
PMU | L7 | PMU_BM_3 | base server system must implement bandwidth monitors for External accelerator interface | no | ||
PMU | L7 | PMU_BM_4 | base server system must implement bandwidth monitors for Chip-to-chip interface | no | ||
PMU app | PMU | L7 | PMU_SYS_7 | Each significant cache in the base server system must be capable of measuring cache effectiveness | yes | |
PMU | L7 | PMU_SEC_1 | When deployed in production systems, performance monitors must not expose Secure data to untrusted software | no | ||
RAS | L7 | RAS_05 | If any error record in an error record group is capable of generating a critical error interrupt, the group implements a single critical error interrupt for all the records contained in the group | no | ||
Covered by PCIe tests | RAS | L7 | RAS_10 | Where the PCIe standard [1], Arm architecture[2], or other standard defines a rule or sets a convention for a software fault at a device, that rule or convention must be followed | yes |
Arm SBSA ACS is distributed under Apache v2.0 License.
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