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ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
Both clocks and clock-names are missing (a lot of) entries: add all the used audio clocks and their description and also fix the example node. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: c861af7 ("ASoC: dt-bindings: mediatek: mt8192: re-add audio afe document") Link: https://patch.msgid.link/20260115125624.73598-3-angelogioacchino.delregno@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
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‎Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml‎

Lines changed: 162 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -47,16 +47,118 @@ properties:
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- description: AFE clock
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- description: ADDA DAC clock
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- description: ADDA DAC pre-distortion clock
50-
- description: audio infra sys clock
51-
- description: audio infra 26M clock
50+
- description: ADDA ADC clock
51+
- description: ADDA6 ADC clock
52+
- description: Audio low-jitter 22.5792m clock
53+
- description: Audio low-jitter 24.576m clock
54+
- description: Audio PLL1 tuner clock
55+
- description: Audio PLL2 tuner clock
56+
- description: Audio Time-Division Multiplexing interface clock
57+
- description: ADDA ADC Sine Generator clock
58+
- description: audio Non-LE clock
59+
- description: Audio DAC High-Resolution clock
60+
- description: Audio High-Resolution ADC clock
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- description: Audio High-Resolution ADC SineGen clock
62+
- description: Audio ADDA6 High-Resolution ADC clock
63+
- description: Tertiary ADDA DAC clock
64+
- description: Tertiary ADDA DAC pre-distortion clock
65+
- description: Tertiary ADDA DAC Sine Generator clock
66+
- description: Tertiary ADDA DAC High-Resolution clock
67+
- description: Audio infra sys clock
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- description: Audio infra 26M clock
69+
- description: Mux for audio clock
70+
- description: Mux for audio internal bus clock
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- description: Mux main divider by 4
72+
- description: Primary audio mux
73+
- description: Primary audio PLL
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- description: Secondary audio mux
75+
- description: Secondary audio PLL
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- description: Primary audio en-generator clock
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- description: Primary PLL divider by 4 for IEC
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- description: Secondary audio en-generator clock
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- description: Secondary PLL divider by 4 for IEC
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- description: Mux selector for I2S port 0
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- description: Mux selector for I2S port 1
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- description: Mux selector for I2S port 2
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- description: Mux selector for I2S port 3
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- description: Mux selector for I2S port 4
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- description: Mux selector for I2S port 5
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- description: Mux selector for I2S port 6
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- description: Mux selector for I2S port 7
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- description: Mux selector for I2S port 8
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- description: Mux selector for I2S port 9
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- description: APLL1 and APLL2 divider for I2S port 0
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- description: APLL1 and APLL2 divider for I2S port 1
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- description: APLL1 and APLL2 divider for I2S port 2
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- description: APLL1 and APLL2 divider for I2S port 3
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- description: APLL1 and APLL2 divider for I2S port 4
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- description: APLL1 and APLL2 divider for IEC
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- description: APLL1 and APLL2 divider for I2S port 5
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- description: APLL1 and APLL2 divider for I2S port 6
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- description: APLL1 and APLL2 divider for I2S port 7
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- description: APLL1 and APLL2 divider for I2S port 8
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- description: APLL1 and APLL2 divider for I2S port 9
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- description: Top mux for audio subsystem
102+
- description: 26MHz clock for audio subsystem
52103

53104
clock-names:
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items:
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- const: aud_afe_clk
56107
- const: aud_dac_clk
57108
- const: aud_dac_predis_clk
109+
- const: aud_adc_clk
110+
- const: aud_adda6_adc_clk
111+
- const: aud_apll22m_clk
112+
- const: aud_apll24m_clk
113+
- const: aud_apll1_tuner_clk
114+
- const: aud_apll2_tuner_clk
115+
- const: aud_tdm_clk
116+
- const: aud_tml_clk
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- const: aud_nle
118+
- const: aud_dac_hires_clk
119+
- const: aud_adc_hires_clk
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- const: aud_adc_hires_tml
121+
- const: aud_adda6_adc_hires_clk
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- const: aud_3rd_dac_clk
123+
- const: aud_3rd_dac_predis_clk
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- const: aud_3rd_dac_tml
125+
- const: aud_3rd_dac_hires_clk
58126
- const: aud_infra_clk
59127
- const: aud_infra_26m_clk
128+
- const: top_mux_audio
129+
- const: top_mux_audio_int
130+
- const: top_mainpll_d4_d4
131+
- const: top_mux_aud_1
132+
- const: top_apll1_ck
133+
- const: top_mux_aud_2
134+
- const: top_apll2_ck
135+
- const: top_mux_aud_eng1
136+
- const: top_apll1_d4
137+
- const: top_mux_aud_eng2
138+
- const: top_apll2_d4
139+
- const: top_i2s0_m_sel
140+
- const: top_i2s1_m_sel
141+
- const: top_i2s2_m_sel
142+
- const: top_i2s3_m_sel
143+
- const: top_i2s4_m_sel
144+
- const: top_i2s5_m_sel
145+
- const: top_i2s6_m_sel
146+
- const: top_i2s7_m_sel
147+
- const: top_i2s8_m_sel
148+
- const: top_i2s9_m_sel
149+
- const: top_apll12_div0
150+
- const: top_apll12_div1
151+
- const: top_apll12_div2
152+
- const: top_apll12_div3
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- const: top_apll12_div4
154+
- const: top_apll12_divb
155+
- const: top_apll12_div5
156+
- const: top_apll12_div6
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- const: top_apll12_div7
158+
- const: top_apll12_div8
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- const: top_apll12_div9
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- const: top_mux_audio_h
161+
- const: top_clk26m_clk
60162

61163
required:
62164
- compatible
@@ -83,23 +185,69 @@ examples:
83185
afe: mt8192-afe-pcm {
84186
compatible = "mediatek,mt8192-audio";
85187
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
188+
clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
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<&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
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<&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
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<&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
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<&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
193+
<&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
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<&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
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<&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
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<&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
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<&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
198+
<&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
199+
<&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
200+
<&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
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<&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
202+
<&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
203+
<&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
204+
<&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
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<&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
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<&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
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<&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
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<&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
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<&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
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<&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
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<&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
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<&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
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<&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
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<&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
215+
<&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
216+
clock-names = "aud_afe_clk", "aud_dac_clk",
217+
"aud_dac_predis_clk", "aud_adc_clk",
218+
"aud_adda6_adc_clk", "aud_apll22m_clk",
219+
"aud_apll24m_clk", "aud_apll1_tuner_clk",
220+
"aud_apll2_tuner_clk", "aud_tdm_clk",
221+
"aud_tml_clk", "aud_nle",
222+
"aud_dac_hires_clk", "aud_adc_hires_clk",
223+
"aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
224+
"aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
225+
"aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
226+
"aud_infra_clk", "aud_infra_26m_clk",
227+
"top_mux_audio", "top_mux_audio_int",
228+
"top_mainpll_d4_d4", "top_mux_aud_1",
229+
"top_apll1_ck", "top_mux_aud_2",
230+
"top_apll2_ck", "top_mux_aud_eng1",
231+
"top_apll1_d4", "top_mux_aud_eng2",
232+
"top_apll2_d4", "top_i2s0_m_sel",
233+
"top_i2s1_m_sel", "top_i2s2_m_sel",
234+
"top_i2s3_m_sel", "top_i2s4_m_sel",
235+
"top_i2s5_m_sel", "top_i2s6_m_sel",
236+
"top_i2s7_m_sel", "top_i2s8_m_sel",
237+
"top_i2s9_m_sel", "top_apll12_div0",
238+
"top_apll12_div1", "top_apll12_div2",
239+
"top_apll12_div3", "top_apll12_div4",
240+
"top_apll12_divb", "top_apll12_div5",
241+
"top_apll12_div6", "top_apll12_div7",
242+
"top_apll12_div8", "top_apll12_div9",
243+
"top_mux_audio_h", "top_clk26m_clk";
244+
memory-region = <&afe_dma_mem>;
245+
power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
86246
resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
87247
reset-names = "audiosys";
88248
mediatek,apmixedsys = <&apmixedsys>;
89249
mediatek,infracfg = <&infracfg>;
90250
mediatek,topckgen = <&topckgen>;
91-
power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
92-
clocks = <&audsys CLK_AUD_AFE>,
93-
<&audsys CLK_AUD_DAC>,
94-
<&audsys CLK_AUD_DAC_PREDIS>,
95-
<&infracfg CLK_INFRA_AUDIO>,
96-
<&infracfg CLK_INFRA_AUDIO_26M_B>;
97-
clock-names = "aud_afe_clk",
98-
"aud_dac_clk",
99-
"aud_dac_predis_clk",
100-
"aud_infra_clk",
101-
"aud_infra_26m_clk";
102-
memory-region = <&afe_dma_mem>;
103251
};
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105253
...

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