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Try this: first = Signal(1)
second = Signal(1)
Cat(first, second) |
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My question is, how can we make a "Signal(2)" with 2 "Signal(1)"
EXEMPLE :
CONTEXT :
inside a class Module()
we have :
definition of param
instanciate Verilog_module
now i want to take the output of 2 gate_and (verilog module),
for plug on input of a third gate_and.
For that how can we do ? did we need to agregate the am.Signal() returned in "o_out" ?
here a schematic.
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