hdl._nir, back.rtlil: use Format.* to emit enum attributes and wires for fields.

Author: wanda-phi

amaranth/back/rtlil.py

@@ -3,6 +3,7 @@
 import io
 
 from ..utils import bits_for
+from .._utils import to_binary
 from ..lib import wiring
 from ..hdl import _repr, _ast, _ir, _nir
 
@@ -421,6 +422,7 @@ def emit(self):
         self.emit_cell_wires()
         self.emit_submodule_wires()
         self.emit_connects()
+        self.emit_signal_details()
         self.emit_submodules()
         self.emit_cells()
 
@@ -491,12 +493,13 @@ def emit_signal_wires(self):
             attrs.update(signal.attrs)
             self.value_src_loc[value] = signal.src_loc
 
-            for repr in signal._value_repr:
-                if repr.path == () and isinstance(repr.format, _repr.FormatEnum):
-                    enum = repr.format.enum
-                    attrs["enum_base_type"] = enum.__name__
-                    for enum_value in enum:
-                        attrs["enum_value_{:0{}b}".format(enum_value.value, len(signal))] = enum_value.name
+            _value, _signed, enum = self.netlist.signal_details[signal][()]
+            if enum is not None:
+                enum_name, variants = enum
+                if enum_name is not None:
+                    attrs["enum_base_type"] = enum_name
+                for var_val, var_name in variants.items():
+                    attrs["enum_value_" + to_binary(var_val, len(signal))] = var_name
 
             if name in self.module.ports:
                 port_value, _flow = self.module.ports[name]
@@ -666,6 +669,32 @@ def emit_connects(self):
             if name not in self.driven_sigports:
                 self.builder.connect(wire.name, self.sigspec(value))
 
+    def emit_signal_details(self):
+        for signal, name in self.module.signal_names.items():
+            details = self.netlist.signal_details[signal]
+            for path, (value, signed, enum) in details.items():
+                if path == ():
+                    continue
+                name_parts = [name]
+                for comp in path:
+                    if isinstance(comp, str):
+                        name_parts.append(f".{comp}")
+                    elif isinstance(comp, int):
+                        name_parts.append(f"[{comp}]")
+                    else:
+                        assert False # :nocov:
+                attrs = {}
+                if enum is not None:
+                    enum_name, variants = enum
+                    if enum_name is not None:
+                        attrs["enum_base_type"] = enum_name
+                    for var_val, var_name in variants.items():
+                        attrs["enum_value_" + to_binary(var_val, len(value))] = var_name
+                wire = self.builder.wire(width=len(value), signed=signed, attrs=attrs,
+                                         name="".join(name_parts),
+                                         src_loc=signal.src_loc)
+                self.builder.connect(wire.name, self.sigspec(value))
+
     def emit_submodules(self):
         for submodule_idx in self.module.submodules:
             submodule = self.netlist.modules[submodule_idx]

amaranth/hdl/_ast.py

@@ -2095,6 +2095,11 @@ def __init__(self, shape=None, *, name=None, init=None, reset=None, reset_less=F
 
         self._attrs = OrderedDict(() if attrs is None else attrs)
 
+        if isinstance(orig_shape, ShapeCastable):
+            self._format = orig_shape.format(orig_shape(self), "")
+        else:
+            self._format = Format("{}", self)
+
         if decoder is not None:
             # The value representation is specified explicitly. Since we do not expose `hdl._repr`,
             # this is the only way to add a custom filter to the signal right now.

amaranth/hdl/_ir.py

@@ -690,7 +690,7 @@ def emit_value(self, builder):
 
 
 class NetlistEmitter:
-    def __init__(self, netlist: _nir.Netlist, design, *, all_undef_to_ff=False):
+    def __init__(self, netlist: _nir.Netlist, design: Design, *, all_undef_to_ff=False):
         self.netlist = netlist
         self.design = design
         self.all_undef_to_ff = all_undef_to_ff
@@ -776,7 +776,7 @@ def extend(self, value: _nir.Value, signed: bool, width: int):
     def emit_operator(self, module_idx: int, operator: str, *inputs: _nir.Value, src_loc):
         op = _nir.Operator(module_idx, operator=operator, inputs=inputs, src_loc=src_loc)
         return self.netlist.add_value_cell(op.width, op)
-    
+
     def emit_matches(self, module_idx: int, value: _nir.Value, patterns, *, src_loc):
         key = module_idx, value, patterns, src_loc
         try:
@@ -1334,6 +1334,40 @@ def emit_top_ports(self, fragment: _ir.Fragment):
             else:
                 raise ValueError(f"Invalid port direction {dir!r}")
 
+    def emit_signal_details(self):
+        for signal, fragment in self.design.signal_lca.items():
+            module_idx = self.fragment_module_idx[fragment]
+            details = {}
+            def emit_format(path, fmt):
+                if isinstance(fmt, _ast.Format):
+                    specs = [
+                        chunk[0]
+                        for chunk in fmt._chunks
+                        if not isinstance(chunk, str)
+                    ]
+                    if len(specs) != 1:
+                        return
+                    val, signed = self.emit_rhs(module_idx, specs[0])
+                    details[path] = (val, signed, None)
+                elif isinstance(fmt, _ast.Format.Enum):
+                    val, signed = self.emit_rhs(module_idx, fmt._value)
+                    details[path] = (val, signed, (fmt._name, fmt._variants))
+                elif isinstance(fmt, _ast.Format.Struct):
+                    val, signed = self.emit_rhs(module_idx, fmt._value)
+                    details[path] = (val, signed, None)
+                    for name, subfmt in fmt._fields.items():
+                        emit_format(path + (name,), subfmt)
+                elif isinstance(fmt, _ast.Format.Array):
+                    val, signed = self.emit_rhs(module_idx, fmt._value)
+                    details[path] = (val, signed, None)
+                    for idx, subfmt in enumerate(fmt._fields):
+                        emit_format(path + (idx,), subfmt)
+            emit_format((), signal._format)
+            val, signed = self.emit_rhs(module_idx, signal)
+            if () not in details or details[()][0] != val:
+                details[()] = (val, signed, None)
+            self.netlist.signal_details[signal] = details
+
     def emit_drivers(self):
         for driver in self.drivers.values():
             if (driver.domain is not None and
@@ -1452,6 +1486,7 @@ def emit_fragment(self, fragment: _ir.Fragment, parent_module_idx: 'int | None',
             for subfragment, _name, sub_src_loc in fragment.subfragments:
                 self.emit_fragment(subfragment, module_idx, cell_src_loc=sub_src_loc)
             if parent_module_idx is None:
+                self.emit_signal_details()
                 self.emit_drivers()
                 self.emit_top_ports(fragment)
                 if self.all_undef_to_ff:

amaranth/hdl/_nir.py

@@ -329,6 +329,7 @@ def __init__(self):
         self.connections: dict[Net, Net] = {}
         self.io_ports: list[_ast.IOPort] = []
         self.signals = SignalDict()
+        self.signal_details = SignalDict()
         self.last_late_net = 0
 
     def resolve_net(self, net: Net):
@@ -345,6 +346,11 @@ def resolve_all_nets(self):
             cell.resolve_nets(self)
         for sig in self.signals:
             self.signals[sig] = self.resolve_value(self.signals[sig])
+        for signal in self.signals:
+            self.signal_details[signal] = {
+                path: (self.resolve_value(value), signed, enum)
+                for path, (value, signed, enum) in self.signal_details[signal].items()
+            }
 
     def __repr__(self):
         result = ["("]

tests/test_back_rtlil.py

@@ -4,7 +4,7 @@
 from amaranth.back import rtlil
 from amaranth.hdl import *
 from amaranth.hdl._ast import *
-from amaranth.lib import memory, wiring
+from amaranth.lib import memory, wiring, data, enum
 
 from .utils import *
 
@@ -2010,6 +2010,67 @@ def test_print_align(self):
         """)
 
 
+class DetailTestCase(RTLILTestCase):
+    def test_enum(self):
+        class MyEnum(enum.Enum, shape=unsigned(2)):
+            A = 0
+            B = 1
+            C = 2
+
+        sig = Signal(MyEnum)
+        m = Module()
+        m.d.comb += sig.eq(MyEnum.A)
+        self.assertRTLIL(m, [sig.as_value()], R"""
+        attribute \generator "Amaranth"
+        attribute \top 1
+        module \top
+            attribute \enum_base_type "MyEnum"
+            attribute \enum_value_00 "A"
+            attribute \enum_value_01 "B"
+            attribute \enum_value_10 "C"
+            wire width 2 output 0 \sig
+            connect \sig 2'00
+        end
+        """)
+
+    def test_struct(self):
+        class MyEnum(enum.Enum, shape=unsigned(2)):
+            A = 0
+            B = 1
+            C = 2
+
+        class Meow(data.Struct):
+            a: MyEnum
+            b: 3
+            c: signed(4)
+            d: data.ArrayLayout(2, 2)
+
+        sig = Signal(Meow)
+        m = Module()
+        self.assertRTLIL(m, [sig.as_value()], R"""
+        attribute \generator "Amaranth"
+        attribute \top 1
+        module \top
+            wire width 13 input 0 \sig
+            attribute \enum_base_type "MyEnum"
+            attribute \enum_value_00 "A"
+            attribute \enum_value_01 "B"
+            attribute \enum_value_10 "C"
+            wire width 2 \sig.a
+            wire width 3 \sig.b
+            wire width 4 signed \sig.c
+            wire width 4 \sig.d
+            wire width 2 \sig.d[0]
+            wire width 2 \sig.d[1]
+            connect \sig.a \sig [1:0]
+            connect \sig.b \sig [4:2]
+            connect \sig.c \sig [8:5]
+            connect \sig.d \sig [12:9]
+            connect \sig.d[0] \sig [10:9]
+            connect \sig.d[1] \sig [12:11]
+        end
+        """)
+
 class ComponentTestCase(RTLILTestCase):
     def test_component(self):
         class MyComponent(wiring.Component):

tests/test_hdl_ir.py

@@ -8,6 +8,8 @@
 from amaranth.hdl._ir import *
 from amaranth.hdl._mem import *
 
+from amaranth.lib import enum, data
+
 from .utils import *
 
 
@@ -3501,3 +3503,41 @@ def test_undef_to_ff_partial(self):
             (cell 3 0 (flipflop 3.0:5 10 pos 0 0))
         )
         """)
+
+
+class DetailsTestCase(FHDLTestCase):
+    def test_details(self):
+        class MyEnum(enum.Enum, shape=unsigned(2)):
+            A = 0
+            B = 1
+            C = 2
+        l = data.StructLayout({"a": MyEnum, "b": signed(3)})
+        s1 = Signal(l)
+        s2 = Signal(MyEnum)
+        s3 = Signal(signed(3))
+        s4 = Signal(unsigned(4))
+        nl = build_netlist(Fragment.get(Module(), None), [
+            s1.as_value(), s2.as_value(), s3, s4,
+        ])
+        self.assertEqual(nl.signal_details[s1.as_value()], {
+            (): (nl.signals[s1.as_value()], False, None),
+            ('a',): (nl.signals[s1.as_value()][0:2], False, ("MyEnum", {
+                0: "A",
+                1: "B",
+                2: "C",
+            })),
+            ('b',): (nl.signals[s1.as_value()][2:5], True, None)
+        })
+        self.assertEqual(nl.signal_details[s2.as_value()], {
+            (): (nl.signals[s2.as_value()], False, ("MyEnum", {
+                0: "A",
+                1: "B",
+                2: "C",
+            })),
+        })
+        self.assertEqual(nl.signal_details[s3], {
+            (): (nl.signals[s3], True, None),
+        })
+        self.assertEqual(nl.signal_details[s4], {
+            (): (nl.signals[s4], False, None),
+        })

tests/test_lib_data.py

@@ -647,6 +647,9 @@ def const(self, init):
             def from_bits(self, bits):
                 return bits
 
+            def format(self, value, spec):
+                return Format("")
+
         v = Signal(data.StructLayout({
             "f": WrongCastable()
         }))