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wanda-phiwhitequark
wanda-phi
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whitequark
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examples: convert to wiring.Component.
1 parent a0750b8 commit 362b450

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14 files changed

+115
-140
lines changed

14 files changed

+115
-140
lines changed

‎amaranth/cli.py

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -43,9 +43,8 @@ def main_parser(parser=None):
4343
return parser
4444

4545

46-
def main_runner(parser, args, design, platform=None, name="top", ports=()):
46+
def main_runner(parser, args, design, platform=None, name="top", ports=None):
4747
if args.action == "generate":
48-
fragment = Fragment.get(design, platform)
4948
generate_type = args.generate_type
5049
if generate_type is None and args.generate_file:
5150
if args.generate_file.name.endswith(".il"):
@@ -57,11 +56,11 @@ def main_runner(parser, args, design, platform=None, name="top", ports=()):
5756
if generate_type is None:
5857
parser.error("Unable to auto-detect language, specify explicitly with -t/--type")
5958
if generate_type == "il":
60-
output = rtlil.convert(fragment, name=name, ports=ports, emit_src=args.emit_src)
59+
output = rtlil.convert(design, platform=platform, name=name, ports=ports, emit_src=args.emit_src)
6160
if generate_type == "cc":
62-
output = cxxrtl.convert(fragment, name=name, ports=ports, emit_src=args.emit_src)
61+
output = cxxrtl.convert(design, platform=platform, name=name, ports=ports, emit_src=args.emit_src)
6362
if generate_type == "v":
64-
output = verilog.convert(fragment, name=name, ports=ports, emit_src=args.emit_src)
63+
output = verilog.convert(design, platform=platform, name=name, ports=ports, emit_src=args.emit_src)
6564
if args.generate_file:
6665
args.generate_file.write(output)
6766
else:

‎examples/basic/alu.py

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,17 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

4-
5-
class ALU(Elaboratable):
6+
class ALU(wiring.Component):
67
def __init__(self, width):
7-
self.sel = Signal(2)
8-
self.a = Signal(width)
9-
self.b = Signal(width)
10-
self.o = Signal(width)
11-
self.co = Signal()
8+
super().__init__({
9+
"sel": In(2),
10+
"a": In(width),
11+
"b": In(width),
12+
"o": Out(width),
13+
"co": Out(1),
14+
})
1215

1316
def elaborate(self, platform):
1417
m = Module()
@@ -25,4 +28,4 @@ def elaborate(self, platform):
2528

2629
if __name__ == "__main__":
2730
alu = ALU(width=16)
28-
main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co])
31+
main(alu)

‎examples/basic/alu_hier.py

Lines changed: 22 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,38 +1,45 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

46

5-
class Adder(Elaboratable):
7+
class Adder(wiring.Component):
68
def __init__(self, width):
7-
self.a = Signal(width)
8-
self.b = Signal(width)
9-
self.o = Signal(width)
9+
super().__init__({
10+
"a": In(width),
11+
"b": In(width),
12+
"o": Out(width),
13+
})
1014

1115
def elaborate(self, platform):
1216
m = Module()
1317
m.d.comb += self.o.eq(self.a + self.b)
1418
return m
1519

1620

17-
class Subtractor(Elaboratable):
21+
class Subtractor(wiring.Component):
1822
def __init__(self, width):
19-
self.a = Signal(width)
20-
self.b = Signal(width)
21-
self.o = Signal(width)
23+
super().__init__({
24+
"a": In(width),
25+
"b": In(width),
26+
"o": Out(width),
27+
})
2228

2329
def elaborate(self, platform):
2430
m = Module()
2531
m.d.comb += self.o.eq(self.a - self.b)
2632
return m
2733

2834

29-
class ALU(Elaboratable):
35+
class ALU(wiring.Component):
3036
def __init__(self, width):
31-
self.op = Signal()
32-
self.a = Signal(width)
33-
self.b = Signal(width)
34-
self.o = Signal(width)
35-
37+
super().__init__({
38+
"op": In(1),
39+
"a": In(width),
40+
"b": In(width),
41+
"o": Out(width),
42+
})
3643
self.add = Adder(width)
3744
self.sub = Subtractor(width)
3845

@@ -55,4 +62,4 @@ def elaborate(self, platform):
5562

5663
if __name__ == "__main__":
5764
alu = ALU(width=16)
58-
main(alu, ports=[alu.op, alu.a, alu.b, alu.o])
65+
main(alu)

‎examples/basic/arst.py

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,15 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

46

5-
class ClockDivisor(Elaboratable):
7+
class ClockDivisor(wiring.Component):
8+
o: Out(1)
9+
610
def __init__(self, factor):
11+
super().__init__()
712
self.v = Signal(factor)
8-
self.o = Signal()
913

1014
def elaborate(self, platform):
1115
m = Module()

‎examples/basic/ctr.py

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,15 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

46

5-
class Counter(Elaboratable):
7+
class Counter(wiring.Component):
8+
o: Out(1)
9+
610
def __init__(self, width):
11+
super().__init__()
712
self.v = Signal(width, init=2**width-1)
8-
self.o = Signal()
913

1014
def elaborate(self, platform):
1115
m = Module()
@@ -16,4 +20,4 @@ def elaborate(self, platform):
1620

1721
ctr = Counter(width=16)
1822
if __name__ == "__main__":
19-
main(ctr, ports=[ctr.o])
23+
main(ctr)

‎examples/basic/ctr_en.py

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,17 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.sim import *
35
from amaranth.back import verilog
46

57

6-
class Counter(Elaboratable):
8+
class Counter(wiring.Component):
9+
o: Out(1)
10+
en: In(1)
11+
712
def __init__(self, width):
13+
super().__init__()
814
self.v = Signal(width, init=2**width-1)
9-
self.o = Signal()
10-
self.en = Signal()
1115

1216
def elaborate(self, platform):
1317
m = Module()
@@ -18,7 +22,7 @@ def elaborate(self, platform):
1822

1923
ctr = Counter(width=16)
2024

21-
print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
25+
print(verilog.convert(ctr))
2226

2327
sim = Simulator(ctr)
2428
sim.add_clock(1e-6)

‎examples/basic/fsm.py

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,20 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

46

5-
class UARTReceiver(Elaboratable):
7+
class UARTReceiver(wiring.Component):
8+
i: In(1)
9+
data: Out(8)
10+
rdy: Out(1)
11+
ack: In(1)
12+
err: Out(1)
13+
614
def __init__(self, divisor):
15+
super().__init__()
716
self.divisor = divisor
817

9-
self.i = Signal()
10-
self.data = Signal(8)
11-
self.rdy = Signal()
12-
self.ack = Signal()
13-
self.err = Signal()
14-
1518
def elaborate(self, platform):
1619
m = Module()
1720

@@ -61,4 +64,4 @@ def elaborate(self, platform):
6164

6265
if __name__ == "__main__":
6366
rx = UARTReceiver(20)
64-
main(rx, ports=[rx.i, rx.data, rx.rdy, rx.ack, rx.err])
67+
main(rx)

‎examples/basic/gpio.py

Lines changed: 0 additions & 27 deletions
This file was deleted.

‎examples/basic/inst.py

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,14 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

46

5-
class System(Elaboratable):
6-
def __init__(self):
7-
self.adr = Signal(16)
8-
self.dat_r = Signal(8)
9-
self.dat_w = Signal(8)
10-
self.we = Signal()
7+
class System(wiring.Component):
8+
adr: In(16)
9+
dat_r: In(8)
10+
dat_w: Out(8)
11+
we: In(1)
1112

1213
def elaborate(self, platform):
1314
m = Module()
@@ -23,4 +24,4 @@ def elaborate(self, platform):
2324

2425
if __name__ == "__main__":
2526
sys = System()
26-
main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we])
27+
main(sys)

‎examples/basic/mem.py

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,19 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.lib.memory import Memory
35
from amaranth.cli import main
46

57

6-
class RegisterFile(Elaboratable):
8+
class RegisterFile(wiring.Component):
9+
adr: In(4)
10+
dat_r: Out(8)
11+
dat_w: In(8)
12+
we: In(1)
13+
714
def __init__(self):
8-
self.adr = Signal(4)
9-
self.dat_r = Signal(8)
10-
self.dat_w = Signal(8)
11-
self.we = Signal()
12-
self.mem = Memory(shape=8, depth=16, init=[0xaa, 0x55])
15+
super().__init__()
16+
self.mem = Memory(shape=8, depth=16, init=[0xaa, 0x55])
1317

1418
def elaborate(self, platform):
1519
m = Module()
@@ -28,4 +32,4 @@ def elaborate(self, platform):
2832

2933
if __name__ == "__main__":
3034
rf = RegisterFile()
31-
main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we])
35+
main(rf)

‎examples/basic/pmux.py

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,18 @@
11
from amaranth import *
2+
from amaranth.lib import wiring
3+
from amaranth.lib.wiring import In, Out
24
from amaranth.cli import main
35

46

5-
class ParMux(Elaboratable):
7+
class ParMux(wiring.Component):
68
def __init__(self, width):
7-
self.s = Signal(3)
8-
self.a = Signal(width)
9-
self.b = Signal(width)
10-
self.c = Signal(width)
11-
self.o = Signal(width)
9+
super().__init__({
10+
"s": In(3),
11+
"a": In(width),
12+
"b": In(width),
13+
"c": In(width),
14+
"o": Out(width),
15+
})
1216

1317
def elaborate(self, platform):
1418
m = Module()
@@ -26,4 +30,4 @@ def elaborate(self, platform):
2630

2731
if __name__ == "__main__":
2832
pmux = ParMux(width=16)
29-
main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o])
33+
main(pmux)

‎examples/basic/sel.py

Lines changed: 0 additions & 29 deletions
This file was deleted.

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