Socfpga 3.16

Documentation/devicetree/bindings/arm/altera/fpga-dma.txt

@@ -0,0 +1,25 @@
+Altera FPGA DMA FIFO driver
+
+Required properties:
+- compatible : "altr,fpga-dma";
+
+- reg : CSR and DATA register resource definitions (address and length).
+
+- reg-names : Names of the register resources.  Should be "csr", "data".
+
+- dmas : DMA request lines.  Should be <&pdma 0 &pdma 1>
+
+- dma-names : Names of DMA request lines. Should be "tx", "rx".
+
+Example:
+
+	fpgadma: fifo {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "altr,fpga-dma";
+		reg = <0xff230000 0x20>, <0xc0011000 0x400>;
+		reg-names = "csr", "data";
+		dmas = <&pdma 0 &pdma 1>;
+		dma-names = "tx", "rx";
+	};
+

Documentation/devicetree/bindings/arm/altera/socfpga-l2-ecc.txt

@@ -0,0 +1,15 @@
+Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
+
+Required Properties:
+- compatible : Should be "altr,l2-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt. Note the rising edge type.
+
+Example:
+
+	l2edac@xffd08140 {
+		compatible = "altr,l2-edac";
+		reg = <0xffd08140 0x4>;
+		interrupts = <0 36 1>, <0 37 1>;
+	};

Documentation/devicetree/bindings/arm/altera/socfpga-l3.txt

@@ -0,0 +1,14 @@
+Altera SOCFPGA L3 Interconnect (NIC-301)
+
+Required properties:
+- compatible : "altr,l3regs", "syscon";
+                Note that syscon is invoked for this device to support the FPGA
+		bridge driver and possibly other devices in the future.  See
+		also Documentation/devicetree/bindings/mfd/syscon.txt
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+	l3regs@0xff800000 {
+		compatible = "altr,l3regs", "syscon";
+		reg = <0xff800000 0x1000>;
+	};

Documentation/devicetree/bindings/arm/altera/socfpga-ocram-ecc.txt

@@ -0,0 +1,16 @@
+Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
+
+OCRAM ECC Required Properties:
+- compatible : Should be "altr,ocram-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt. Note the rising edge type.
+
+Example:
+	ocramedac@ffd08144 {
+		compatible = "altr,ocram-edac";
+		reg = <0xffd08144 0x4>;
+		iram = <&ocram>;
+		interrupts = <0 178 1>, <0 179 1>;
+	};

Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

@@ -0,0 +1,12 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdr-edac";
+- interrupts : Should contain the SDRAM ECC IRQ in the
+	appropriate format for the IRQ controller.
+
+Example:
+	sdramedac@0 {
+		compatible = "altr,sdram-edac";
+		interrupts = <0 39 4>;
+	};

Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

@@ -0,0 +1,14 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl", "syscon";
+                Note that syscon is invoked for this device to support the FPGA
+		bridge driver and possibly other devices in the future.  See
+		also Documentation/devicetree/bindings/mfd/syscon.txt
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+	sdrctl@0xffc25000 {
+		compatible = "altr,sdr-ctl", "syscon";
+		reg = <0xffc25000 0x1000>;
+	};

Documentation/devicetree/bindings/arm/altera/socfpga-system.txt

@@ -1,13 +1,16 @@
 Altera SOCFPGA System Manager
 
 Required properties:
-- compatible : "altr,sys-mgr"
+- compatible : "altr,sys-mgr", "syscon";
+
 - reg : Should contain 1 register ranges(address and length)
+                Note that syscon is invoked for this device. See
+		also Documentation/devicetree/bindings/mfd/syscon.txt
 - cpu1-start-addr : CPU1 start address in hex.
 
 Example:
 	 sysmgr@ffd08000 {
-		compatible = "altr,sys-mgr";
+		compatible = "altr,sys-mgr", "syscon";
 		reg = <0xffd08000 0x1000>;
 		cpu1-start-addr = <0xffd080c4>;
 	};

Documentation/devicetree/bindings/fpga/altera-fpga-mgr.txt

@@ -0,0 +1,25 @@
+Altera FPGA Manager
+
+Required properties:
+
+  - compatible : should be "<manufacturer>,<type>"
+                 "altr,fpga-mgr-1.0", "altr,fpga-mgr";
+
+  - transport  : the interface for register and configuration data.
+                 Currently only memory mapped io is supported, so must be "mmio"
+
+  - reg        : base address for memory mapped io.
+                  - The first index is for FPGA manager register access.
+                  - The second index is for writing FPGA configuration data.
+
+  - interrupts : interrupts for the FPGA Manager device.
+
+Example:
+
+	hps_0_fpgamgr: fpgamgr@0xff706000 {
+		compatible = "altr,fpga-mgr-1.0", "altr,fpga-mgr";
+		transport = "mmio";
+		reg = <0xFF706000 0x1000
+		       0xFFB90000 0x1000>;
+		interrupts = <0 175 4>;
+	};

Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt

@@ -0,0 +1,53 @@
+Altera FPGA To SDRAM Bridge Driver
+
+    This driver manages a bridge between an FPGA and the SDRAM used by an
+    host processor system (HPS). The bridge contains a number read ports,
+    write ports, and command ports.  Reconfiguring these ports requires
+    that no SDRAM transactions occur during reconfiguration.  In other words,
+    the code reconfiguring the ports cannot be run out of SDRAM nor can the
+    FPGA access the SDRAM during the reconfiguration.  This driver does not
+    support reconfiguring the ports.  Typcially, the ports are configured by
+    code running out of onchip ram before Linux is started.
+
+    This driver supports enabling and disabling of the configured ports all
+    at once, which allows for safe reprogramming of the FPGA from user space,
+    provided the new FPGA image uses the same port configuration.
+    User space can enable/disable the bridge by writing a "1" or a "0",
+    respectively, to its enable file under bridge's entry in
+    /sys/class/fpga-bridge. Typically, one disables the bridges before
+    reprogramming the FPGA.  Once the FPGA is reprogrammed, the bridges
+    are reenabled.
+
+Required properties:
+
+    - compatible : "altr,socfpga-fpga2sdram-bridge"
+
+    - read-ports-mask : Bits 0 to 3 corresponds read ports 0 to 3. A
+	bit set to 1 indicates the corresponding read port should be enabled.
+
+    - write-ports-mask : Bits 0 to 3 corresponds write ports 0 to 3. A
+	bit set to 1 indicates the corresponding write port should be enabled.
+
+    - cmd-ports-mask : Bits 0 to 5 correspond to command ports 0 to 5. A
+	bit set to 1 indicates the corresponding command port should be enabled.
+
+Optional properties:
+
+    - label : name that you want this bridge to show up as under
+	/sys/class/fpga-bridge.
+	Default is br<device#> if this is not specified
+
+    - init-val :0 if driver should disable bridge at startup
+		1 if driver should enable bridge at startup
+		driver leaves bridge in current state if property not specified
+
+
+Example:
+	fpga2sdram_br: fpgabridge@3 {
+		compatible = "altr,socfpga-fpga2sdram-bridge";
+		label = "fpga2sdram";
+		read-ports-mask = <3>;
+		write-ports-mask = <3>;
+		cmd-ports-mask = <0xd>;
+		init-val = <0>;
+	};

Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt

@@ -0,0 +1,45 @@
+Altera FPGA/HPS  Bridge Driver
+
+    This driver manages a bridge between a FPGA and a host processor system
+    (HPS).  User space can enable/disable the bridge by writing a "1" or a "0",
+    respectively, to its enable file under bridge's entry in
+    /sys/class/fpga-bridge.  Typically, one disables the bridges before
+    reprogramming the FPGA.  Once the FPGA is reprogrammed, the bridges
+    are reenabled.
+
+Required properties:
+
+  - compatible : "altr,socfpga-hps2fpga-bridge"
+		 "altr,socfpga-lwhps2fpga-bridge"
+		 "altr,socfpga-fpga2hps-bridge"
+
+  - clocks : clocks used by this module
+
+Optional properties:
+  - label : name that you want this bridge to show up as under
+	/sys/class/fpga-bridge.  Default is br<device#> if this is not specified
+
+  - init-val : 	0 if driver should disable bridge at startup
+		1 if driver should enable bridge at startup
+		driver leaves bridge in current state if property not specified
+
+Example:
+	hps_fpgabridge0: fpgabridge@0 {
+		compatible = "altr,socfpga-hps2fpga-bridge";
+		label = "hps2fpga";
+		clocks = <&l4_main_clk>;
+		init-val = <1>;
+	};
+
+	hps_fpgabridge1: fpgabridge@1 {
+		compatible = "altr,socfpga-lwhps2fpga-bridge";
+		label = "lwhps2fpga";
+		clocks = <&l4_main_clk>;
+		init-val = <0>;
+	};
+
+	hps_fpgabridge2: fpgabridge@2 {
+		compatible = "altr,socfpga-fpga2hps-bridge";
+		label = "fpga2hps";
+		clocks = <&l4_main_clk>;
+	};

Documentation/devicetree/bindings/gpio/gpio-altera.txt

@@ -0,0 +1,44 @@
+Altera GPIO controller bindings
+
+Required properties:
+- compatible:
+  - "altr,pio-1.0"
+- reg: Physical base address and length of the controller's registers.
+- #gpio-cells : Should be 1
+  - The first cell is the gpio offset number
+- gpio-controller : Marks the device node as a GPIO controller.
+- #interrupt-cells : Should be 1.
+  - The first cell is the GPIO offset number within the GPIO controller.
+- interrupts: Specify the interrupt.
+- interrupt-controller: Mark the device node as an interrupt controller
+
+Altera GPIO specific required properties:
+- altr,interrupt_trigger: Specifies the interrupt trigger type the GPIO
+  hardware is synthesized. This field is required if the Altera GPIO controller
+  used has IRQ enabled as the interrupt type is not software controlled,
+  but hardware synthesized. Required if GPIO is used as an interrupt
+  controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
+  Only the following flags are supported:
+    IRQ_TYPE_EDGE_RISING
+    IRQ_TYPE_EDGE_FALLING
+    IRQ_TYPE_EDGE_BOTH
+    IRQ_TYPE_LEVEL_HIGH
+
+Altera GPIO specific optional properties:
+- altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the
+  GPIO device has. Ranges between 1-32. Optional and defaults to 32 is not
+  specified.
+
+Example:
+
+gpio_altr: gpio@40000 {
+    compatible = "altr,pio-1.0";
+    reg = <0xff200000 0x10>;
+    interrupts = <0 45 4>;
+    altr,gpio-bank-width = <32>;
+    altr,interrupt_trigger = <IRQ_TYPE_EDGE_RISING>;
+    #gpio-cells = <1>;
+    gpio-controller;
+    #interrupt-cells = <1>;
+    interrupt-controller;
+};

Documentation/devicetree/bindings/i2c/i2c-designware.txt

@@ -9,6 +9,8 @@ Required properties :
 Recommended properties :
 
  - clock-frequency : desired I2C bus clock frequency in Hz.
+ - speed-mode      : 0 = standard (0 - 100Kb/s)
+                   : 1 = fast (<= 400Kb/s) <== default
 
 Optional properties :
  - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
@@ -29,6 +31,7 @@ Example :
 		reg = <0xf0000 0x1000>;
 		interrupts = <11>;
 		clock-frequency = <400000>;
+		speed-mode = <1>;
 	};
 
 	i2c@1120000 {

Documentation/devicetree/bindings/mailbox/mailbox-altera.txt

@@ -0,0 +1,32 @@
+Altera mailbox (simple) soft IP
+
+Required properties:
+- compatible : "altr,mailbox-1.0".
+- reg : physical base address of the mailbox and length of memory mapped
+     region.
+- linux,mailbox-name : Mailbox instance name
+
+Optional properties:
+- interrupt-parent : interrupt source phandle.
+- interrupts : interrupt number. The interrupt specifier format depends on the
+	       interrupt controller parent.
+
+The property of "linux,mailbox-name" must be unique. This name will be used as
+controller name in driver to identify the controller and the mailbox client will
+use this name when requesting a mailbox channel.
+
+Example:
+	mailbox0: mailbox0@0x100 {
+		compatible = "altr,mailbox-1.0";
+		reg = <0x100 0x8>;
+		interrupt-parent = < &gic_0 >;
+		interrupts = <5>;
+		linux,mailbox-name = "mailbox0";
+	};
+
+Example of mailbox's client node that includes mailbox phandle.
+	mclient0: mclient0@0x200 {
+		compatible = "client-1.0";
+		reg = <0x200 0x10>;
+		mailbox = <&mailbox0>;
+	};

Documentation/devicetree/bindings/misc/altera-hwmutex.txt

@@ -0,0 +1,22 @@
+Altera hardware mutex
+Altera hardware mutex can provide hardware assistance for synchronization and
+mutual exclusion between processors in asymmetric/symmetric multiprocessing
+(AMP/SMP) system or multi processes/threads in uniprocessor system.
+
+Required properties:
+- compatible : "altr,mutex-1.0".
+- reg : physical base address of the mutex and length of memory mapped
+     region.
+
+Example:
+	mutex0: mutex0@0x100 {
+		compatible = "altr,hwmutex-1.0";
+		reg = <0x100 0x8>;
+	};
+
+Example of mutex's client node that includes mutex phandle.
+	mclient0: mclient0@0x200 {
+		compatible = "client-1.0";
+		reg = <0x200 0x10>;
+		mutex = <&mutex0>;
+	};