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Is there any possibility that the reception module (uart_rx) is not working?

Status: Open.

#11 In alexforencich/verilog-uart;

· AlexPop09 opened on Feb 22, 2024

Hello, what's the difference between ready and busy in practice(usart_tx.rbl)

Status: Open.

#10 In alexforencich/verilog-uart;

· jinbangju opened on Oct 16, 2023

AttributeError: 'HierarchyObject' object has no attribute '_entity'

Status: Open.

#9 In alexforencich/verilog-uart;

· dattran96 opened on Mar 19, 2023

No CDC synchronizers at the RX input

Status: Open.

#8 In alexforencich/verilog-uart;

· OVGN opened on Jan 6, 2022

cnt bits in uart_tx.v and uart_rx.v

Status: Open.

#7 In alexforencich/verilog-uart;

· makararasi opened on Sep 29, 2021

Can I break the max speed limited by clk frequency?

Status: Open.

#6 In alexforencich/verilog-uart;

· rliangcn opened on Jul 9, 2021

create IP from verilog in vivado

Status: Open.

#4 In alexforencich/verilog-uart;

· mhanuel26 opened on Mar 1, 2018

max bir rate?

Status: Open.

#3 In alexforencich/verilog-uart;

· Washix opened on May 14, 2017

Could you explain why the prescale should be set to Fclk / (baud * 8) according to verilog code?

Status: Open.

#2 In alexforencich/verilog-uart;

· wuzh07 opened on Apr 11, 2017

Testing the uart rx and tx using PuttY

Status: Open.

#1 In alexforencich/verilog-uart;

· 108anup opened on Mar 25, 2017