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Add TX underrun and error tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
1 parent 915f4c2 commit e24f887

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10 files changed

+885
-3
lines changed

10 files changed

+885
-3
lines changed

‎tb/axis_baser_tx_64/test_axis_baser_tx_64.py

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,82 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
216216
await RisingEdge(dut.clk)
217217

218218

219+
async def run_test_underrun(dut, ifg=12):
220+
221+
tb = TB(dut)
222+
223+
tb.dut.cfg_ifg.value = ifg
224+
tb.dut.cfg_tx_enable.value = 1
225+
226+
await tb.reset()
227+
228+
test_data = bytes(x for x in range(60))
229+
230+
for k in range(3):
231+
test_frame = AxiStreamFrame(test_data)
232+
await tb.source.send(test_frame)
233+
234+
for k in range(16):
235+
await RisingEdge(dut.clk)
236+
237+
tb.source.pause = True
238+
239+
for k in range(4):
240+
await RisingEdge(dut.clk)
241+
242+
tb.source.pause = False
243+
244+
for k in range(3):
245+
rx_frame = await tb.sink.recv()
246+
247+
if k == 1:
248+
assert rx_frame.data[-1] == 0xFE
249+
assert rx_frame.ctrl[-1] == 1
250+
else:
251+
assert rx_frame.get_payload() == test_data
252+
assert rx_frame.check_fcs()
253+
assert rx_frame.ctrl is None
254+
255+
assert tb.sink.empty()
256+
257+
await RisingEdge(dut.clk)
258+
await RisingEdge(dut.clk)
259+
260+
261+
async def run_test_error(dut, ifg=12):
262+
263+
tb = TB(dut)
264+
265+
tb.dut.cfg_ifg.value = ifg
266+
tb.dut.cfg_tx_enable.value = 1
267+
268+
await tb.reset()
269+
270+
test_data = bytes(x for x in range(60))
271+
272+
for k in range(3):
273+
test_frame = AxiStreamFrame(test_data)
274+
if k == 1:
275+
test_frame.tuser = 1
276+
await tb.source.send(test_frame)
277+
278+
for k in range(3):
279+
rx_frame = await tb.sink.recv()
280+
281+
if k == 1:
282+
assert rx_frame.data[-1] == 0xFE
283+
assert rx_frame.ctrl[-1] == 1
284+
else:
285+
assert rx_frame.get_payload() == test_data
286+
assert rx_frame.check_fcs()
287+
assert rx_frame.ctrl is None
288+
289+
assert tb.sink.empty()
290+
291+
await RisingEdge(dut.clk)
292+
await RisingEdge(dut.clk)
293+
294+
219295
def size_list():
220296
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
221297

@@ -241,6 +317,12 @@ def cycle_en():
241317
factory.add_option("ifg", [12])
242318
factory.generate_tests()
243319

320+
for test in [run_test_underrun, run_test_error]:
321+
322+
factory = TestFactory(test)
323+
factory.add_option("ifg", [12])
324+
factory.generate_tests()
325+
244326

245327
# cocotb-test
246328

‎tb/axis_gmii_tx/test_axis_gmii_tx.py

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,94 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
141141
await RisingEdge(dut.clk)
142142

143143

144+
async def run_test_underrun(dut, ifg=12, enable_gen=None, mii_sel=False):
145+
146+
tb = TB(dut)
147+
148+
tb.dut.cfg_ifg.value = ifg
149+
tb.dut.cfg_tx_enable.value = 1
150+
tb.dut.mii_select.value = mii_sel
151+
152+
if enable_gen is not None:
153+
tb.set_enable_generator(enable_gen())
154+
155+
await tb.reset()
156+
157+
test_data = bytes(x for x in range(60))
158+
159+
for k in range(3):
160+
test_frame = AxiStreamFrame(test_data)
161+
await tb.source.send(test_frame)
162+
163+
for k in range(200 if mii_sel else 100):
164+
while True:
165+
await RisingEdge(dut.clk)
166+
if dut.clk_enable.value.integer:
167+
break
168+
169+
tb.source.pause = True
170+
171+
for k in range(10):
172+
while True:
173+
await RisingEdge(dut.clk)
174+
if dut.clk_enable.value.integer:
175+
break
176+
177+
tb.source.pause = False
178+
179+
for k in range(3):
180+
rx_frame = await tb.sink.recv()
181+
182+
if k == 1:
183+
assert rx_frame.error[-1] == 1
184+
else:
185+
assert rx_frame.get_payload() == test_data
186+
assert rx_frame.check_fcs()
187+
assert rx_frame.error is None
188+
189+
assert tb.sink.empty()
190+
191+
await RisingEdge(dut.clk)
192+
await RisingEdge(dut.clk)
193+
194+
195+
async def run_test_error(dut, ifg=12, enable_gen=None, mii_sel=False):
196+
197+
tb = TB(dut)
198+
199+
tb.dut.cfg_ifg.value = ifg
200+
tb.dut.cfg_tx_enable.value = 1
201+
tb.dut.mii_select.value = mii_sel
202+
203+
if enable_gen is not None:
204+
tb.set_enable_generator(enable_gen())
205+
206+
await tb.reset()
207+
208+
test_data = bytes(x for x in range(60))
209+
210+
for k in range(3):
211+
test_frame = AxiStreamFrame(test_data)
212+
if k == 1:
213+
test_frame.tuser = 1
214+
await tb.source.send(test_frame)
215+
216+
for k in range(3):
217+
rx_frame = await tb.sink.recv()
218+
219+
if k == 1:
220+
assert rx_frame.error[-1] == 1
221+
else:
222+
assert rx_frame.get_payload() == test_data
223+
assert rx_frame.check_fcs()
224+
assert rx_frame.error is None
225+
226+
assert tb.sink.empty()
227+
228+
await RisingEdge(dut.clk)
229+
await RisingEdge(dut.clk)
230+
231+
144232
def size_list():
145233
return list(range(60, 128)) + [512, 1514] + [60]*10
146234

@@ -163,6 +251,14 @@ def cycle_en():
163251
factory.add_option("mii_sel", [False, True])
164252
factory.generate_tests()
165253

254+
for test in [run_test_underrun, run_test_error]:
255+
256+
factory = TestFactory(test)
257+
factory.add_option("ifg", [12])
258+
factory.add_option("enable_gen", [None, cycle_en])
259+
factory.add_option("mii_sel", [False, True])
260+
factory.generate_tests()
261+
166262

167263
# cocotb-test
168264

‎tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,82 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
197197
await RisingEdge(dut.clk)
198198

199199

200+
async def run_test_underrun(dut, ifg=12):
201+
202+
tb = TB(dut)
203+
204+
tb.dut.cfg_ifg.value = ifg
205+
tb.dut.cfg_tx_enable.value = 1
206+
207+
await tb.reset()
208+
209+
test_data = bytes(x for x in range(60))
210+
211+
for k in range(3):
212+
test_frame = AxiStreamFrame(test_data)
213+
await tb.source.send(test_frame)
214+
215+
for k in range(32):
216+
await RisingEdge(dut.clk)
217+
218+
tb.source.pause = True
219+
220+
for k in range(4):
221+
await RisingEdge(dut.clk)
222+
223+
tb.source.pause = False
224+
225+
for k in range(3):
226+
rx_frame = await tb.sink.recv()
227+
228+
if k == 1:
229+
assert rx_frame.data[-1] == 0xFE
230+
assert rx_frame.ctrl[-1] == 1
231+
else:
232+
assert rx_frame.get_payload() == test_data
233+
assert rx_frame.check_fcs()
234+
assert rx_frame.ctrl is None
235+
236+
assert tb.sink.empty()
237+
238+
await RisingEdge(dut.clk)
239+
await RisingEdge(dut.clk)
240+
241+
242+
async def run_test_error(dut, ifg=12):
243+
244+
tb = TB(dut)
245+
246+
tb.dut.cfg_ifg.value = ifg
247+
tb.dut.cfg_tx_enable.value = 1
248+
249+
await tb.reset()
250+
251+
test_data = bytes(x for x in range(60))
252+
253+
for k in range(3):
254+
test_frame = AxiStreamFrame(test_data)
255+
if k == 1:
256+
test_frame.tuser = 1
257+
await tb.source.send(test_frame)
258+
259+
for k in range(3):
260+
rx_frame = await tb.sink.recv()
261+
262+
if k == 1:
263+
assert rx_frame.data[-1] == 0xFE
264+
assert rx_frame.ctrl[-1] == 1
265+
else:
266+
assert rx_frame.get_payload() == test_data
267+
assert rx_frame.check_fcs()
268+
assert rx_frame.ctrl is None
269+
270+
assert tb.sink.empty()
271+
272+
await RisingEdge(dut.clk)
273+
await RisingEdge(dut.clk)
274+
275+
200276
def size_list():
201277
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
202278

@@ -222,6 +298,12 @@ def cycle_en():
222298
factory.add_option("ifg", [12])
223299
factory.generate_tests()
224300

301+
for test in [run_test_underrun, run_test_error]:
302+
303+
factory = TestFactory(test)
304+
factory.add_option("ifg", [12])
305+
factory.generate_tests()
306+
225307

226308
# cocotb-test
227309

‎tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,82 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
205205
await RisingEdge(dut.clk)
206206

207207

208+
async def run_test_underrun(dut, ifg=12):
209+
210+
tb = TB(dut)
211+
212+
tb.dut.cfg_ifg.value = ifg
213+
tb.dut.cfg_tx_enable.value = 1
214+
215+
await tb.reset()
216+
217+
test_data = bytes(x for x in range(60))
218+
219+
for k in range(3):
220+
test_frame = AxiStreamFrame(test_data)
221+
await tb.source.send(test_frame)
222+
223+
for k in range(16):
224+
await RisingEdge(dut.clk)
225+
226+
tb.source.pause = True
227+
228+
for k in range(4):
229+
await RisingEdge(dut.clk)
230+
231+
tb.source.pause = False
232+
233+
for k in range(3):
234+
rx_frame = await tb.sink.recv()
235+
236+
if k == 1:
237+
assert rx_frame.data[-1] == 0xFE
238+
assert rx_frame.ctrl[-1] == 1
239+
else:
240+
assert rx_frame.get_payload() == test_data
241+
assert rx_frame.check_fcs()
242+
assert rx_frame.ctrl is None
243+
244+
assert tb.sink.empty()
245+
246+
await RisingEdge(dut.clk)
247+
await RisingEdge(dut.clk)
248+
249+
250+
async def run_test_error(dut, ifg=12):
251+
252+
tb = TB(dut)
253+
254+
tb.dut.cfg_ifg.value = ifg
255+
tb.dut.cfg_tx_enable.value = 1
256+
257+
await tb.reset()
258+
259+
test_data = bytes(x for x in range(60))
260+
261+
for k in range(3):
262+
test_frame = AxiStreamFrame(test_data)
263+
if k == 1:
264+
test_frame.tuser = 1
265+
await tb.source.send(test_frame)
266+
267+
for k in range(3):
268+
rx_frame = await tb.sink.recv()
269+
270+
if k == 1:
271+
assert rx_frame.data[-1] == 0xFE
272+
assert rx_frame.ctrl[-1] == 1
273+
else:
274+
assert rx_frame.get_payload() == test_data
275+
assert rx_frame.check_fcs()
276+
assert rx_frame.ctrl is None
277+
278+
assert tb.sink.empty()
279+
280+
await RisingEdge(dut.clk)
281+
await RisingEdge(dut.clk)
282+
283+
208284
def size_list():
209285
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
210286

@@ -230,6 +306,12 @@ def cycle_en():
230306
factory.add_option("ifg", [12])
231307
factory.generate_tests()
232308

309+
for test in [run_test_underrun, run_test_error]:
310+
311+
factory = TestFactory(test)
312+
factory.add_option("ifg", [12])
313+
factory.generate_tests()
314+
233315

234316
# cocotb-test
235317

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