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alexforencichalexforencich
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Rewrite gain scheduling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
1 parent 89ee44d commit a2294c5

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2 files changed

+37
-39
lines changed

2 files changed

+37
-39
lines changed

‎rtl/ptp_clock_cdc.v

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -674,19 +674,19 @@ always @* begin
674674
// PI control
675675

676676
// gain scheduling
677-
if (!ts_ns_diff_reg[8+CMP_FNS_WIDTH]) begin
678-
if (ts_ns_diff_reg[4+CMP_FNS_WIDTH +: 4]) begin
679-
gain_sel_next = 1'b1;
680-
end else begin
681-
gain_sel_next = 1'b0;
682-
end
683-
end else begin
684-
if (~ts_ns_diff_reg[4+CMP_FNS_WIDTH +: 4]) begin
685-
gain_sel_next = 1'b1;
686-
end else begin
687-
gain_sel_next = 1'b0;
688-
end
689-
end
677+
casez (ts_ns_diff_reg[9+CMP_FNS_WIDTH-5 +: 5])
678+
5'b01zzz: gain_sel_next = 1'b1;
679+
5'b001zz: gain_sel_next = 1'b1;
680+
5'b0001z: gain_sel_next = 1'b1;
681+
5'b00001: gain_sel_next = 1'b1;
682+
5'b00000: gain_sel_next = 1'b0;
683+
5'b11111: gain_sel_next = 1'b0;
684+
5'b11110: gain_sel_next = 1'b1;
685+
5'b1110z: gain_sel_next = 1'b1;
686+
5'b110zz: gain_sel_next = 1'b1;
687+
5'b10zzz: gain_sel_next = 1'b1;
688+
default: gain_sel_next = 1'b0;
689+
endcase
690690

691691
// time integral of error
692692
case (gain_sel_reg)

‎rtl/ptp_td_leaf.v

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -426,19 +426,17 @@ always @* begin
426426
// updated sampled dst_phase error
427427

428428
// gain scheduling
429-
if (!sample_acc_sync_reg[SAMPLE_ACC_W-1]) begin
430-
if (sample_acc_sync_reg[SAMPLE_ACC_W-4 +: 3]) begin
431-
dst_gain_sel_next = 1'b1;
432-
end else begin
433-
dst_gain_sel_next = 1'b0;
434-
end
435-
end else begin
436-
if (~sample_acc_sync_reg[SAMPLE_ACC_W-4 +: 3]) begin
437-
dst_gain_sel_next = 1'b1;
438-
end else begin
439-
dst_gain_sel_next = 1'b0;
440-
end
441-
end
429+
casez (sample_acc_sync_reg[SAMPLE_ACC_W-4 +: 4])
430+
4'b01zz: dst_gain_sel_next = 1'b1;
431+
4'b001z: dst_gain_sel_next = 1'b1;
432+
4'b0001: dst_gain_sel_next = 1'b1;
433+
4'b0000: dst_gain_sel_next = 1'b0;
434+
4'b1111: dst_gain_sel_next = 1'b0;
435+
4'b1110: dst_gain_sel_next = 1'b1;
436+
4'b110z: dst_gain_sel_next = 1'b1;
437+
4'b10zz: dst_gain_sel_next = 1'b1;
438+
default: dst_gain_sel_next = 1'b0;
439+
endcase
442440

443441
// time integral of error
444442
case (dst_gain_sel_reg)
@@ -850,19 +848,19 @@ always @* begin
850848
// PI control
851849

852850
// gain scheduling
853-
if (!ts_ns_diff_reg[8+CMP_FNS_W]) begin
854-
if (ts_ns_diff_reg[4+CMP_FNS_W +: 4]) begin
855-
gain_sel_next = 1'b1;
856-
end else begin
857-
gain_sel_next = 1'b0;
858-
end
859-
end else begin
860-
if (~ts_ns_diff_reg[4+CMP_FNS_W +: 4]) begin
861-
gain_sel_next = 1'b1;
862-
end else begin
863-
gain_sel_next = 1'b0;
864-
end
865-
end
851+
casez (ts_ns_diff_reg[9+CMP_FNS_W-5 +: 5])
852+
5'b01zzz: gain_sel_next = 1'b1;
853+
5'b001zz: gain_sel_next = 1'b1;
854+
5'b0001z: gain_sel_next = 1'b1;
855+
5'b00001: gain_sel_next = 1'b1;
856+
5'b00000: gain_sel_next = 1'b0;
857+
5'b11111: gain_sel_next = 1'b0;
858+
5'b11110: gain_sel_next = 1'b1;
859+
5'b1110z: gain_sel_next = 1'b1;
860+
5'b110zz: gain_sel_next = 1'b1;
861+
5'b10zzz: gain_sel_next = 1'b1;
862+
default: gain_sel_next = 1'b0;
863+
endcase
866864

867865
// time integral of error
868866
case (gain_sel_reg)

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