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Implement simulation models for PIPE for operation with PCIe IP cores. Requires #3 and #4.
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FYI - @ktemkin & @ECP5-PCIe & @litghost
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Just FYI, this is a rather long-term goal that's not on any critical paths at the moment.
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Implement simulation models for PIPE for operation with PCIe IP cores. Requires #3 and #4.
The text was updated successfully, but these errors were encountered: