RISC-V assembler for the University of Warwick FPGA RISC-V core

Hello!

This is dcsembler, a basic assembler for the DCS’s (Department of Computer Science) FPGA soft-core RISC-V project in 2022.

This forms part of the software tooling for the project.

Build instructions

The project is built using CMake, so you’ll need that.

Then, there are handy scripts to help you configure and build and run/test the project.

You can use configure.sh to run CMake automatically, or configure-gui.sh to get a terminal interface for the same.

Then, you’re free to build.sh and run.sh away!

License

MIT licensed - feel free to use for fun or profit!