MIPS: Ci20: Increase MMC0 max-frequency in DT node

The closest clockspeed to 48Mhz that the MSC supports is 50Mhz. However, as
this is greater than 48Mhz the MSC clock divider is increased - causing the
clock speed to  become 25Mhz.

Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>

Author: HarveyHunt

arch/mips/boot/dts/ci20.dts

@@ -125,7 +125,7 @@
 
 &msc0 {
 	bus-width = <4>;
-	max-frequency = <48000000>;
+	max-frequency = <50000000>;
 	cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
 
 	pinctrl-names = "default";