Add addCache and revert setState functions, also allow invalidated cache to go through the bus

Author: tttyyzzz

bus.hpp

@@ -15,7 +15,7 @@ class Bus {
     virtual void attachProcessor(shared_ptr<Processor> proc) = 0;
     virtual void pushRequestToBus(shared_ptr<Request> request) = 0;
     virtual void pushRequestToMemory(shared_ptr<Request> request) = 0;
-    virtual void issueInvalidation(unsigned int address) = 0;
+    virtual void issueInvalidation(unsigned int pid,unsigned int address) = 0;
     virtual void executeCycle() = 0;
     virtual bool isCurrentRequestDone(int pid) = 0;
     virtual void printProgress() = 0;

bus_impl.cpp

@@ -53,17 +53,26 @@ bool BusImpl::isCurrentRequestDone(int pid) {
     return currentRequests[pid]->done;
 }
 
-void BusImpl::issueInvalidation(unsigned int pid) {
+void BusImpl::issueInvalidation(unsigned int pid,unsigned int address) {
+    cout << "invalidating cache! " << endl;
     for (auto processor : this->processors) {
         if (processor->getPID() == pid) {
             continue;
         }
-        processor->invalidateCache(); // Not sure if this will send through the bus
+        processor->invalidateCache(address); // Not sure if this will send through the bus
     }
 }
 
 void BusImpl::processBusRd(shared_ptr<Request> request) {
     if (bus_debug) cout << "processing BusRd" << endl;
+
+    // if processor is -1 then just pass it through the bus and disappear
+    if (request-> pid == -1){
+        // countdown of passing through the bus only
+        request->countdown = 2 * wordsPerBlock;
+        request->isToMemOrCache = false;
+        return;
+    }
     // check if any other processor has it in M state
     // sanity check : if there exists the block in M state then they need to flush it
     // otherwise, everyone who has the block MUST match memory. so 100 + 2n

bus_impl.hpp

@@ -26,7 +26,7 @@ class BusImpl : public Bus {
   public:
     BusImpl(int wordsPerBlock) : wordsPerBlock(wordsPerBlock){};
     void attachProcessor(shared_ptr<Processor> proc) override;
-    void issueInvalidation(unsigned int pid) override;
+    void issueInvalidation(unsigned int pid,unsigned int address) override;
     void pushRequestToBus(shared_ptr<Request> request) override;
     void pushRequestToMemory(shared_ptr<Request> request) override;
     bool isCurrentRequestDone(int pid) override;

cache.cpp

@@ -12,13 +12,16 @@ size_t Cache::getIndex(size_t address) {
     // this returns the index of the memory
     return (address / blockSize) % cacheSize;
 }
+size_t Cache::getTag(size_t address) { return (address / (blockSize * cacheSize)); }
 
 size_t Cache::getIndexWithTag(size_t address) {
     // this returns the index of the memory
     return address / cacheSize;
 }
 
-size_t Cache::getTag(size_t address) { return (address / (blockSize * cacheSize)); }
+size_t Cache::reverseGeneralAddress(size_t tag, size_t index){
+    return ((tag*(blockSize * cacheSize)) + (index)) * blockSize;
+}
 
 bool Cache::checkCacheLine(size_t address) {
     // get the respective address
@@ -40,7 +43,9 @@ void Cache::addCacheLine(size_t address, State state) {
     // performs a addCacheLine
     size_t index = getIndex(address);
     size_t tag = getTag(address);
+    // this will only give the tag, need to add in the address and then pad with the block size
     cache[index].addCacheLine(tag, state);
+
 }
 
 bool Cache::readCacheLine(size_t address) {
@@ -64,10 +69,10 @@ State Cache::getCacheLineState(size_t address) {
     return cache[index].checkCacheLineState(tag);
 }
 
-void Cache::setCacheLineState(size_t address, State state) {
+bool Cache::setCacheLineState(size_t address, State state) {
     size_t index = getIndex(address);
     size_t tag = getTag(address);
-    cache[index].setCacheLineState(tag, state);
+    return cache[index].setCacheLineState(tag, state);
 }
 
 State Cache::getLRUCacheLineState(size_t address) {
@@ -78,3 +83,15 @@ State Cache::getLRUCacheLineState(size_t address) {
     }
     return I;
 }
+
+bool Cache::checkCacheLineFull(size_t address){
+    size_t index = getIndex(address);
+    return associativity == cache[index].size();
+}
+
+
+unsigned int Cache::getLRUCacheLineAddress(size_t address){
+    size_t index = getIndex(address);
+    unsigned int tag = cache[index].getFirst().getTag();
+    return reverseGeneralAddress(tag,index);
+}

cache.hpp

@@ -29,6 +29,8 @@ class Cache {
 
     size_t getIndexWithTag(size_t address);
 
+    size_t reverseGeneralAddress(size_t tag,size_t index);
+
     bool checkCacheLine(size_t address);
 
     void invalidateCacheLine(size_t address);
@@ -41,7 +43,12 @@ class Cache {
 
     State getCacheLineState(size_t address);
 
-    void setCacheLineState(size_t address, State state);
+    bool setCacheLineState(size_t address, State state);
 
     State getLRUCacheLineState(size_t address);
+
+    bool checkCacheLineFull(size_t address);
+
+    unsigned int getLRUCacheLineAddress(size_t address);
+
 };

cache_line.cpp

@@ -5,4 +5,7 @@ CacheLine::CacheLine(unsigned int tag, State state) : tag(tag), state(state){};
 
 State CacheLine::getState() { return state; };
 
+unsigned int CacheLine::getTag() { return tag; };
+
 void CacheLine::setState(State state) { this->state = state; }
+

cache_line.hpp

@@ -4,6 +4,7 @@
 #include <cstddef>
 
 class CacheLine {
+  public:
     State state; // The states currently will corresponds to 0,1,2,3
     // M -- 0, E -- 1, S -- 2, I -- 3 or M -- 0 E -- 1 Sc -- 2 Sm -- 3
     unsigned int tag;
@@ -12,5 +13,6 @@ class CacheLine {
   public:
     CacheLine(unsigned int tag, State state);
     State getState();
+    unsigned int getTag();
     void setState(State state);
 };

cache_set.cpp

@@ -79,12 +79,14 @@ State CacheSet::checkCacheLineState(size_t tag) {
     return I; // this will be similar to invalid state
 }
 
-void CacheSet::setCacheLineState(size_t tag, State state) {
+bool CacheSet::setCacheLineState(size_t tag, State state) {
     for (auto &cacheLine : cacheSet) {
         if (cacheLine.tag == tag) {
             cacheLine.setState(state);
+            return true;
         }
     }
+    return false;
 }
 
 bool CacheSet::checkCacheSetFull() { return cacheSet.size() == maxSize; }

cache_set.hpp

@@ -28,12 +28,14 @@ class CacheSet {
 
     State checkCacheLineState(size_t tag);
 
-    void setCacheLineState(size_t tag, State state);
+    bool setCacheLineState(size_t tag, State state);
 
     bool checkCacheSetFull();
 
     bool isEmpty();
 
+    unsigned int size(){return cacheSet.size();}
+
     CacheLine getFirst();
 
     friend class Cache;

dragon.cpp

@@ -52,7 +52,7 @@ CacheResultType DragonProtocol::onStore(int pid,unsigned int address, shared_ptr
             if (dragon_debug) cout << "Sc: store hit" << endl;
             cache->updateCacheLine(address,Sm);
 
-            shared_ptr<Request> busRdRequest = make_shared<Request>(pid, BusUpd, address);
+            shared_ptr<Request> busRdRequest = make_shared<Request>(-1, BusUpd, address);
             bus->pushRequestToBus(busRdRequest);
             // TODO: use bus command to change the state of other caches
             bus->updateOtherCachesToSc(address,pid);

processor.hpp

@@ -5,10 +5,11 @@
 class Processor {
   public:
     virtual void executeCycle() = 0;
-    virtual void invalidateCache() = 0;
+    virtual void invalidateCache(unsigned int address) = 0;
     virtual State getState(unsigned int address) = 0;
     virtual bool isDone() = 0;
     virtual void setState(unsigned int address, State state) = 0;
+    virtual void addCacheLine(unsigned int address, State state) = 0;
     virtual int getPID() = 0;
     virtual void printProgressInline() = 0;
 };

processor_impl.cpp

@@ -110,14 +110,32 @@ bool ProcessorImpl::execute(unsigned int type, unsigned int value) {
     return true;
 }
 
-void ProcessorImpl::invalidateCache() {}
+void ProcessorImpl::invalidateCache(unsigned int address) {cache->invalidateCacheLine(address);}
 
 State ProcessorImpl::getState(unsigned int address) { return cache->getCacheLineState(address); }
 
 bool ProcessorImpl::isDone() { return done; }
 
 void ProcessorImpl::setState(unsigned int address, State state) {
-    cache->setCacheLineState(address, state);
+    cache->setCacheLineState(address,state);
+}
+
+void ProcessorImpl::addCacheLine(unsigned int address, State state){
+    //TODO: this function suppose to update cache if it exist else do other things
+    bool isStateSet = cache->setCacheLineState(address, state);
+    if (!isStateSet){
+        // this means that cache is not inside the cacheline
+        if (cache->checkCacheLineFull(address)){// if address is full, then will need to invalidate cache
+            //get the cacheline and then add it to the bus // TODO: ask adam
+            unsigned int old_cache_address = cache->getLRUCacheLineAddress(address);
+            // put into the bus to send to cache
+            // create a request
+            shared_ptr<Request> invalidateRequest = make_shared<Request>(-1,BusRd,address);
+            // put it into the bus
+            bus->pushRequestToBus(invalidateRequest);
+        }
+        cache->addCacheLine(address,state); // will automatically remove LRU cache
+    }
 }
 
 void ProcessorImpl::printProgressInline() {

processor_impl.hpp

@@ -39,10 +39,11 @@ class ProcessorImpl : public Processor {
     ProcessorImpl(int pid, string filepath, unsigned int cacheSize, unsigned int associativity,
                   unsigned int blockSize, shared_ptr<Bus> bus, shared_ptr<Protocol> protocol);
     void executeCycle() override;
-    void invalidateCache() override;
+    void invalidateCache(unsigned int address) override;
     State getState(unsigned int address) override;
     bool isDone() override;
     void setState(unsigned int address, State state) override;
+    void addCacheLine(unsigned int address, State state) override;
     int getPID() override { return pid; };
     void printProgressInline() override;
 };