Fix circular dependency

Author: adamozh

bus.cpp

@@ -1,22 +1,17 @@
 #pragma once
 
 #include "processor.hpp"
-#include "request.hpp"
 #include <memory>
-#include <queue>
+#include <vector>
 
 using namespace std;
 
 class Bus {
   private:
     vector<shared_ptr<Processor>> processors;
-    shared_ptr<Request> currReq;
-    vector<Request> memRequests;
-    queue<Request> busQueue;
 
   public:
     virtual void attachProcessor(shared_ptr<Processor> proc) = 0;
     virtual void issueInvalidation() = 0;
     virtual void executeCycle() = 0;
-    virtual ~Bus(){};
 };

bus.hpp

@@ -0,0 +1,28 @@
+#include "bus_impl.hpp"
+#include "processor.hpp"
+#include "request.cpp"
+#include <memory>
+#include <queue>
+#include <vector>
+
+using namespace std;
+
+void BusImpl::attachProcessor(shared_ptr<Processor> proc) { this->processors.push_back(proc); }
+
+void BusImpl::issueInvalidation() {
+    for (auto processor : this->processors) {
+        processor->invalidateCache();
+    }
+}
+
+void BusImpl::executeCycle() {
+    if (currReq == nullptr) {
+        currReq = busQueue.front();
+        busQueue.pop();
+    }
+    currReq->decrement();
+    if (currReq->isDone()) {
+        /* current bus transaction is done */
+    }
+    /* handle memory */
+}

bus_impl.cpp

@@ -0,0 +1,22 @@
+#pragma once
+
+#include "bus.hpp"
+#include "processor.hpp"
+#include "request.hpp"
+#include <memory>
+#include <queue>
+
+using namespace std;
+
+class BusImpl : public Bus {
+  private:
+    vector<shared_ptr<Processor>> processors;
+    shared_ptr<Request> currReq = nullptr;
+    vector<Request> memRequests;
+    queue<shared_ptr<Request>> busQueue;
+
+  public:
+    void attachProcessor(shared_ptr<Processor> proc);
+    void issueInvalidation();
+    void executeCycle();
+};

bus_impl.hpp

@@ -1,6 +1,7 @@
-#include "bus.cpp"
+#include "bus.hpp"
+#include "bus_impl.hpp"
 #include "memory.cpp"
-#include "processor.cpp"
+#include "processor.hpp"
 #include <iostream>
 #include <memory>
 #include <string>
@@ -45,9 +46,10 @@ int main(int argc, char *argv[]) {
     // Your logic here for implementing the cache coherence protocols
 
     int numProcessors;
-    // TODO: Initialize a shared bus
-    // shared_ptr<Bus> bus = make_shared();
+    shared_ptr<Bus> bus = make_shared<BusImpl>();
     // TODO: Initialize processors with bus
+    for (int i = 0; i < numProcessors; i++) {
+    }
 
     unsigned int clock = 0;
     /*

main.cpp

@@ -1,5 +1,7 @@
 #include "mesi.hpp"
 
+using namespace std;
+
 void MESIProtocol::onLoad(unsigned int address, shared_ptr<Bus> bus, shared_ptr<Cache> cache) {
     // MESI-specific logic
     /*

mesi.cpp

@@ -2,6 +2,8 @@
 #include "protocol.hpp"
 #include <memory>
 
+using namespace std;
+
 class MESIProtocol : public Protocol {
   public:
     void onLoad(unsigned int address, shared_ptr<Bus> bus, shared_ptr<Cache> cache) override;

mesi.hpp

@@ -1,34 +1,8 @@
 #pragma once
 
-#include "cache.hpp"
-#include "protocol.hpp"
-#include "request.hpp"
-#include <memory>
-#include <vector>
-
-using namespace std;
-
-enum ProcessorState { FREE, LOAD, STORE, NON_MEMORY, MEM_ACCESS };
-
 class Processor {
-  private:
-    shared_ptr<Protocol> protocol;
-    shared_ptr<Cache> l1Data;
-    shared_ptr<Bus> bus;
-
-    ProcessorState state;
-    shared_ptr<Request> currRequest;
-    unsigned int cycles = 0;
-
-    unsigned int memCounter = 0;
-    unsigned int nonMemCounter = 0;
-
-    void execute(unsigned int type, unsigned int value);
-    void issueBusTransaction();
-
   public:
-    Processor(unsigned int cacheSize, unsigned int associativity, unsigned int blockSize,
-              shared_ptr<Bus> bus, shared_ptr<Protocol> protocol);
-    void executeCycle();
-    void invalidateCache();
+    virtual void executeCycle() = 0;
+    virtual void invalidateCache() = 0;
+    virtual bool isDone() = 0;
 };

processor.hpp

@@ -1,4 +1,4 @@
-#include "processor.hpp"
+#include "processor_impl.hpp"
 #include "protocol.hpp"
 #include <iostream>
 #include <memory>
@@ -7,26 +7,27 @@
 
 using namespace std;
 
-Processor::Processor(unsigned int cacheSize, unsigned int associativity, unsigned int blockSize,
-                     shared_ptr<Bus> bus, shared_ptr<Protocol> protocol)
-    : state(FREE), protocol(protocol), bus(bus) {
+ProcessorImpl::ProcessorImpl(unsigned int cacheSize, unsigned int associativity,
+                             unsigned int blockSize, shared_ptr<Bus> bus,
+                             shared_ptr<Protocol> protocol)
+    : protocol(protocol), bus(bus) {
     l1Data = make_shared<Cache>(cacheSize, associativity, blockSize);
 }
 
-void Processor::executeCycle() {
+void ProcessorImpl::executeCycle() {
     // TODO: read instructions line by line here
     switch (state) {
     case FREE:
         // call execute(); with instruction type and value
         break;
     case STORE:
-        if (currRequest->isDone) {
+        if (currRequest->isDone()) {
             state = FREE;
         }
         cycles++;
         break;
     case LOAD:
-        if (currRequest->isDone) {
+        if (currRequest->isDone()) {
             state = FREE;
         }
         cycles++;
@@ -37,10 +38,12 @@ void Processor::executeCycle() {
         }
         cycles++;
         break;
+    case MEM_ACCESS:
+        break;
     }
 }
 
-void Processor::execute(unsigned int type, unsigned int value) {
+void ProcessorImpl::execute(unsigned int type, unsigned int value) {
     switch (type) {
     case 0: // load
         protocol->onLoad(value, bus, l1Data);
@@ -57,6 +60,6 @@ void Processor::execute(unsigned int type, unsigned int value) {
     }
 }
 
-void Processor::issueBusTransaction() {}
+void ProcessorImpl::invalidateCache() {}
 
-void Processor::invalidateCache() {}
+bool ProcessorImpl::isDone() { return done; }

processor.cpp renamed to processor_impl.cpp

@@ -0,0 +1,38 @@
+#pragma once
+
+#include "bus.hpp"
+#include "cache.hpp"
+#include "processor.hpp"
+#include "protocol.hpp"
+#include "request.hpp"
+#include <memory>
+#include <vector>
+
+using namespace std;
+
+enum ProcessorState { FREE, LOAD, STORE, NON_MEMORY, MEM_ACCESS };
+
+class ProcessorImpl : public Processor {
+  private:
+    shared_ptr<Protocol> protocol;
+    shared_ptr<Cache> l1Data;
+    shared_ptr<Bus> bus;
+
+    ProcessorState state = FREE;
+    shared_ptr<Request> currRequest = nullptr;
+    unsigned int cycles = 0;
+
+    unsigned int memCounter = 0;
+    unsigned int nonMemCounter = 0;
+
+    bool done = false;
+
+    void execute(unsigned int type, unsigned int value);
+
+  public:
+    ProcessorImpl(unsigned int cacheSize, unsigned int associativity, unsigned int blockSize,
+                  shared_ptr<Bus> bus, shared_ptr<Protocol> protocol);
+    void executeCycle();
+    void invalidateCache();
+    bool isDone();
+};

processor_impl.hpp

@@ -1,9 +1,10 @@
 #pragma once
-
 #include "bus.hpp"
 #include "cache.hpp"
 #include <memory>
 
+using namespace std;
+
 class Protocol {
   public:
     virtual void onLoad(unsigned int address, shared_ptr<Bus> bus, shared_ptr<Cache> cache) = 0;

protocol.hpp

@@ -1,7 +1,11 @@
 #pragma once
 
 class Request {
-  public:
-    bool isDone = false;
+  private:
+    bool done = false;
     unsigned int countdown = 0;
+
+  public:
+    bool isDone() { return done; };
+    void decrement() { countdown--; }
 };