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Unlike many common ISAs, MIPS has a branch delay slot (see this blog post for a better explanation in a MIPS specific context).
The MIPS docs omits any mention of branch delay slots, and the MIPS example code is written as if the branch delay slot didn't exist. This makes the example code very misleading (and, needless to say, incorrect).
The text was updated successfully, but these errors were encountered:
Unlike many common ISAs, MIPS has a branch delay slot (see this blog post for a better explanation in a MIPS specific context).
The MIPS docs omits any mention of branch delay slots, and the MIPS example code is written as if the branch delay slot didn't exist. This makes the example code very misleading (and, needless to say, incorrect).
The text was updated successfully, but these errors were encountered: