Enable deep sleep on all ESP chips

[tannewt]

Features of each chip is documented in this spreadsheet: https://docs.google.com/spreadsheets/d/1NyKzHOWeWMb8UttDDugeeOANZ4m-idMHM6kiTlUUVIg/edit?usp=sharing

Fixes #9056

[tannewt]

This CI will need #9325. I didn't realize esp_sleep_enable_ext1_wakeup_io was introduced in 5.2.2.

[tannewt]

Tested on Feather ESP32-S3 No PSRAM and it works. (I thought it didn't because I hadn't set pull.)

[dhalbert]

Thanks for fixing this, and doing the detailed differences between the chips. This might be docuumented in shared-bindings in a Limitations: section, but we don't have to do that now.

[linuxhuskarl]

Hey, I am currently trying to get XIAO ESP32C3 board to go into deep sleep. I don't fully understand why alarm is unavailable for its port. This PR explicitly says that all ESP boards should have it available. I think most ESP32C3 ports don't have it. See for example my board:

https://circuitpython.org/board/seeed_xiao_esp32c3/

alarm module is unavailable for both CirPy v9 and v10.

Can you help me understand the issue? Is it possible to build a version of FW with alarm module available?

[Neradoc]

Hi, it's disabled by default on some boards with 4MB of flash or less, but will be added in Circuitpython 10 once we change the partition scheme (which will be relatively painless on C3 boards if you are used to save your files before updating Circuitpython with esptool).

circuitpython/ports/espressif/mpconfigport.mk

Lines 280 to 288 in ad73d0b

	# We used to default to OTA partition layout but are moving away from it so that
	# BLE and alarm can be included. This setting prevents the partition layout from
	# changing.
	ifeq ($(CIRCUITPY_LEGACY_4MB_FLASH_LAYOUT), 1)
	ifeq ($(IDF_TARGET_ARCH), xtensa)
	CIRCUITPY_ALARM ?= 1
	else
	CIRCUITPY_ALARM = 0
	endif

Currently building with it would require modifying this file and disabling other modules to make some space.

[linuxhuskarl]

Hey, thanks for the quick response!

Hi, it's disabled by default on some boards with 4MB of flash or less, but will be added in Circuitpython 10 once we change the partition scheme

Is there a ETA for this?

Currently building with it would require modifying this file and disabling other modules to make some space.

I will look into that in the meantime. Thanks for the suggestion!

[dhalbert]

Is there a ETA for this?

We don't give ETA's but it's actively being worked on. We need new bootloaders first.

[tannewt]

Is there a ETA for this?

We don't give ETA's but it's actively being worked on. We need new bootloaders first.

C3 doesn't have a UF2 bootloader. We can do non-Sx now.