@@ -164,24 +164,24 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
164164 // 0x1: TX pad 2; no RTS/CTS
165165 // 0x2: TX pad 0; RTS: pad 2, CTS: pad 3 (not used by us right now)
166166 // So divide by 2 to map pad to value.
167- hri_sercomusart_write_CTRLA_TXPO_bf (sercom , tx_pad / 2 );
168167 // RXPO:
169168 // 0x0: RX pad 0
170169 // 0x1: RX pad 1
171170 // 0x2: RX pad 2
172171 // 0x3: RX pad 3
173- hri_sercomusart_write_CTRLA_RXPO_bf (sercom , rx_pad );
172+ sercom -> USART .CTRLA .reg = SERCOM_USART_CTRLA_TXPO (tx_pad / 2 ) |
173+ SERCOM_USART_CTRLA_RXPO (rx_pad ) |
174+ (parity == PARITY_NONE ? 0 : SERCOM_USART_CTRLA_FORM (1 ));
174175
175176 // Enable tx and/or rx based on whether the pins were specified.
176- hri_sercomusart_write_CTRLB_TXEN_bit (sercom , have_tx );
177- hri_sercomusart_write_CTRLB_RXEN_bit (sercom , have_rx );
178-
179- // Set parity, baud rate, stop bits, etc. 9-bit bytes not supported.
180- usart_async_set_parity (usart_desc_p , parity == PARITY_NONE ? USART_PARITY_NONE :
181- (parity == PARITY_ODD ? USART_PARITY_ODD : USART_PARITY_EVEN ));
182- usart_async_set_stopbits (usart_desc_p , stop == 1 ? USART_STOP_BITS_ONE : USART_STOP_BITS_TWO );
183- // This field is 0 for 8 bits, 5, 6, 7 for 5, 6, 7 bits. 1 for 9 bits, but we don't support that.
184- usart_async_set_character_size (usart_desc_p , bits % 8 );
177+ // CHSIZE is 0 for 8 bits, 5, 6, 7 for 5, 6, 7 bits. 1 for 9 bits, but we don't support that.
178+ sercom -> USART .CTRLB .reg = (have_tx ? SERCOM_USART_CTRLB_TXEN : 0 ) |
179+ (have_rx ? SERCOM_USART_CTRLB_RXEN : 0 ) |
180+ (parity == PARITY_ODD ? SERCOM_USART_CTRLB_PMODE : 0 ) |
181+ (stop > 1 ? SERCOM_USART_CTRLB_SBMODE : 0 ) |
182+ SERCOM_USART_CTRLB_CHSIZE (bits % 8 );
183+
184+ // Set baud rate
185185 common_hal_busio_uart_set_baudrate (self , baudrate );
186186
187187 // Turn on rx interrupt handling. The UART async driver has its own set of internal callbacks,
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