interfacer

Extract bus interfaces from Verilog source files, including AXI Full/Lite/Stream, I2C, Clocks, Reset and more.

Docs

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
.github/workflows		.github/workflows
docs		docs
examples		examples
interfacer		interfacer
scripts		scripts
tests		tests
.gitignore		.gitignore
CHANGELOG.md		CHANGELOG.md
README.md		README.md
VERSION		VERSION
__init__.py		__init__.py
mkdocs.yml		mkdocs.yml
repo.yml		repo.yml
requirements.txt		requirements.txt
setup.py		setup.py