From 33394e801216d81c4c901c0ee9fc511af1329daf Mon Sep 17 00:00:00 2001 From: Po-Yi Tsai Date: Sat, 18 Mar 2023 21:06:36 +0800 Subject: [PATCH] First versions --- .github/workflows/check.yml | 26 + .gitmodules | 4 + README.md | 49 +- crates/bcm2711-lpa/.gitignore | 2 + crates/bcm2711-lpa/Cargo.toml | 19 + crates/bcm2711-lpa/README.md | 16 + crates/bcm2711-lpa/src/aux.rs | 16 + crates/bcm2711-lpa/src/aux/enables.rs | 110 ++ crates/bcm2711-lpa/src/aux/irq.rs | 110 ++ crates/bcm2711-lpa/src/bsc0.rs | 52 + crates/bcm2711-lpa/src/bsc0/a.rs | 80 + crates/bcm2711-lpa/src/bsc0/c.rs | 170 ++ crates/bcm2711-lpa/src/bsc0/clkt.rs | 80 + crates/bcm2711-lpa/src/bsc0/del.rs | 95 ++ crates/bcm2711-lpa/src/bsc0/div.rs | 80 + crates/bcm2711-lpa/src/bsc0/dlen.rs | 80 + crates/bcm2711-lpa/src/bsc0/fifo.rs | 80 + crates/bcm2711-lpa/src/bsc0/s.rs | 159 ++ crates/bcm2711-lpa/src/cm_pcm.rs | 16 + crates/bcm2711-lpa/src/cm_pcm/cs.rs | 288 ++++ crates/bcm2711-lpa/src/cm_pcm/div.rs | 123 ++ crates/bcm2711-lpa/src/emmc.rs | 165 ++ crates/bcm2711-lpa/src/emmc/arg1.rs | 63 + crates/bcm2711-lpa/src/emmc/arg2.rs | 63 + crates/bcm2711-lpa/src/emmc/blksizecnt.rs | 95 ++ crates/bcm2711-lpa/src/emmc/boot_timeout.rs | 63 + crates/bcm2711-lpa/src/emmc/cmdtm.rs | 520 ++++++ crates/bcm2711-lpa/src/emmc/control0.rs | 215 +++ crates/bcm2711-lpa/src/emmc/control1.rs | 253 +++ crates/bcm2711-lpa/src/emmc/control2.rs | 240 +++ crates/bcm2711-lpa/src/emmc/data.rs | 63 + crates/bcm2711-lpa/src/emmc/dbg_sel.rs | 126 ++ crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs | 80 + crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs | 80 + crates/bcm2711-lpa/src/emmc/force_irpt.rs | 320 ++++ crates/bcm2711-lpa/src/emmc/interrupt.rs | 327 ++++ crates/bcm2711-lpa/src/emmc/irpt_en.rs | 320 ++++ crates/bcm2711-lpa/src/emmc/irpt_mask.rs | 320 ++++ crates/bcm2711-lpa/src/emmc/resp0.rs | 63 + crates/bcm2711-lpa/src/emmc/resp1.rs | 63 + crates/bcm2711-lpa/src/emmc/resp2.rs | 63 + crates/bcm2711-lpa/src/emmc/resp3.rs | 63 + crates/bcm2711-lpa/src/emmc/slotisr_ver.rs | 111 ++ crates/bcm2711-lpa/src/emmc/spi_int_spt.rs | 80 + crates/bcm2711-lpa/src/emmc/status.rs | 215 +++ crates/bcm2711-lpa/src/emmc/tune_step.rs | 80 + crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs | 80 + crates/bcm2711-lpa/src/emmc/tune_steps_std.rs | 80 + crates/bcm2711-lpa/src/generic.rs | 695 ++++++++ crates/bcm2711-lpa/src/generic/atomic.rs | 27 + crates/bcm2711-lpa/src/gic_cpu.rs | 98 ++ crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs | 81 + crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs | 61 + crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs | 44 + crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs | 44 + crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs | 63 + crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs | 80 + crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs | 230 +++ crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs | 44 + crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs | 61 + crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs | 96 ++ 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+++++++++++++++++ crates/bcm2711-lpa/src/gpio/gpfsel3.rs | 1481 +++++++++++++++++ crates/bcm2711-lpa/src/gpio/gpfsel4.rs | 1481 +++++++++++++++++ crates/bcm2711-lpa/src/gpio/gpfsel5.rs | 1197 +++++++++++++ crates/bcm2711-lpa/src/gpio/gphen0.rs | 541 ++++++ crates/bcm2711-lpa/src/gpio/gphen1.rs | 451 +++++ .../src/gpio/gpio_pup_pdn_cntrl_reg0.rs | 363 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg1.rs | 319 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg2.rs | 319 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg3.rs | 223 +++ crates/bcm2711-lpa/src/gpio/gplen0.rs | 541 ++++++ crates/bcm2711-lpa/src/gpio/gplen1.rs | 451 +++++ crates/bcm2711-lpa/src/gpio/gplev0.rs | 250 +++ crates/bcm2711-lpa/src/gpio/gplev1.rs | 208 +++ crates/bcm2711-lpa/src/gpio/gpren0.rs | 541 ++++++ crates/bcm2711-lpa/src/gpio/gpren1.rs | 451 +++++ crates/bcm2711-lpa/src/gpio/gpset0.rs | 296 ++++ crates/bcm2711-lpa/src/gpio/gpset1.rs | 248 +++ crates/bcm2711-lpa/src/interrupt.rs | 107 ++ crates/bcm2711-lpa/src/lib.rs | 1248 ++++++++++++++ crates/bcm2711-lpa/src/lic.rs | 65 + crates/bcm2711-lpa/src/lic/basic_pending.rs | 177 ++ crates/bcm2711-lpa/src/lic/disable_1.rs | 545 ++++++ crates/bcm2711-lpa/src/lic/disable_2.rs | 545 ++++++ crates/bcm2711-lpa/src/lic/disable_basic.rs | 187 +++ crates/bcm2711-lpa/src/lic/enable_1.rs | 545 ++++++ crates/bcm2711-lpa/src/lic/enable_2.rs | 545 ++++++ crates/bcm2711-lpa/src/lic/enable_basic.rs | 186 +++ crates/bcm2711-lpa/src/lic/fiq_control.rs | 1054 ++++++++++++ crates/bcm2711-lpa/src/lic/pending_1.rs | 254 +++ crates/bcm2711-lpa/src/lic/pending_2.rs | 254 +++ crates/bcm2711-lpa/src/pactl.rs | 10 + crates/bcm2711-lpa/src/pactl/cs.rs | 365 ++++ crates/bcm2711-lpa/src/pwm0.rs | 54 + crates/bcm2711-lpa/src/pwm0/ctl.rs | 382 +++++ crates/bcm2711-lpa/src/pwm0/dat1.rs | 63 + crates/bcm2711-lpa/src/pwm0/dat2.rs | 63 + crates/bcm2711-lpa/src/pwm0/dmac.rs | 110 ++ crates/bcm2711-lpa/src/pwm0/fif1.rs | 44 + crates/bcm2711-lpa/src/pwm0/rng1.rs | 63 + crates/bcm2711-lpa/src/pwm0/rng2.rs | 63 + crates/bcm2711-lpa/src/pwm0/sta.rs | 260 +++ crates/bcm2711-lpa/src/spi0.rs | 40 + crates/bcm2711-lpa/src/spi0/clk.rs | 80 + crates/bcm2711-lpa/src/spi0/cs.rs | 446 +++++ crates/bcm2711-lpa/src/spi0/dc.rs | 125 ++ crates/bcm2711-lpa/src/spi0/dlen.rs | 80 + crates/bcm2711-lpa/src/spi0/fifo.rs | 80 + crates/bcm2711-lpa/src/spi0/ltoh.rs | 80 + crates/bcm2711-lpa/src/spi1.rs | 40 + crates/bcm2711-lpa/src/spi1/cntl0.rs | 335 ++++ crates/bcm2711-lpa/src/spi1/cntl1.rs | 140 ++ crates/bcm2711-lpa/src/spi1/io.rs | 80 + crates/bcm2711-lpa/src/spi1/peek.rs | 37 + crates/bcm2711-lpa/src/spi1/stat.rs | 185 ++ crates/bcm2711-lpa/src/spi1/txhold.rs | 80 + crates/bcm2711-lpa/src/systmr.rs | 46 + crates/bcm2711-lpa/src/systmr/c0.rs | 63 + crates/bcm2711-lpa/src/systmr/c1.rs | 63 + crates/bcm2711-lpa/src/systmr/c2.rs | 63 + crates/bcm2711-lpa/src/systmr/c3.rs | 63 + crates/bcm2711-lpa/src/systmr/chi.rs | 28 + crates/bcm2711-lpa/src/systmr/clo.rs | 28 + crates/bcm2711-lpa/src/systmr/cs.rs | 125 ++ crates/bcm2711-lpa/src/uart0.rs | 99 ++ crates/bcm2711-lpa/src/uart0/cr.rs | 200 +++ crates/bcm2711-lpa/src/uart0/dmacr.rs | 110 ++ crates/bcm2711-lpa/src/uart0/dr.rs | 140 ++ crates/bcm2711-lpa/src/uart0/ecr.rs | 76 + crates/bcm2711-lpa/src/uart0/fbrd.rs | 80 + crates/bcm2711-lpa/src/uart0/fr.rs | 200 +++ crates/bcm2711-lpa/src/uart0/ibrd.rs | 80 + crates/bcm2711-lpa/src/uart0/icr.rs | 132 ++ crates/bcm2711-lpa/src/uart0/ifls.rs | 95 ++ crates/bcm2711-lpa/src/uart0/imsc.rs | 230 +++ crates/bcm2711-lpa/src/uart0/lcr_h.rs | 170 ++ crates/bcm2711-lpa/src/uart0/mis.rs | 107 ++ crates/bcm2711-lpa/src/uart0/ris.rs | 107 ++ crates/bcm2711-lpa/src/uart0/rsr.rs | 58 + crates/bcm2711-lpa/src/uart1.rs | 99 ++ crates/bcm2711-lpa/src/uart1/baud.rs | 63 + crates/bcm2711-lpa/src/uart1/baudh.rs | 63 + crates/bcm2711-lpa/src/uart1/baudl.rs | 63 + crates/bcm2711-lpa/src/uart1/cntl.rs | 291 ++++ crates/bcm2711-lpa/src/uart1/ier.rs | 95 ++ crates/bcm2711-lpa/src/uart1/iir.rs | 110 ++ crates/bcm2711-lpa/src/uart1/io.rs | 80 + crates/bcm2711-lpa/src/uart1/lcr.rs | 158 ++ crates/bcm2711-lpa/src/uart1/lsr.rs | 125 ++ crates/bcm2711-lpa/src/uart1/mcr.rs | 80 + crates/bcm2711-lpa/src/uart1/msr.rs | 80 + crates/bcm2711-lpa/src/uart1/scratch.rs | 63 + crates/bcm2711-lpa/src/uart1/stat.rs | 245 +++ crates/bcm2711-lpa/src/usb_otg_device.rs | 179 ++ .../bcm2711-lpa/src/usb_otg_device/daint.rs | 44 + .../src/usb_otg_device/daintmsk.rs | 95 ++ crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs | 140 ++ crates/bcm2711-lpa/src/usb_otg_device/dctl.rs | 171 ++ .../src/usb_otg_device/deachint.rs | 95 ++ .../src/usb_otg_device/deachintmsk.rs | 95 ++ .../src/usb_otg_device/diepeachmsk1.rs | 200 +++ .../src/usb_otg_device/diepempmsk.rs | 81 + .../bcm2711-lpa/src/usb_otg_device/diepmsk.rs | 185 ++ .../src/usb_otg_device/doepeachmsk1.rs | 230 +++ .../bcm2711-lpa/src/usb_otg_device/doepmsk.rs | 170 ++ crates/bcm2711-lpa/src/usb_otg_device/dsts.rs | 58 + .../bcm2711-lpa/src/usb_otg_device/dthrctl.rs | 155 ++ .../src/usb_otg_device/dvbusdis.rs | 80 + .../src/usb_otg_device/dvbuspulse.rs | 80 + .../src/usb_otg_device/in_endpoint.rs | 36 + .../usb_otg_device/in_endpoint/diepctl0.rs | 216 +++ .../src/usb_otg_device/in_endpoint/diepdma.rs | 80 + .../src/usb_otg_device/in_endpoint/diepint.rs | 222 +++ .../usb_otg_device/in_endpoint/dieptsiz.rs | 95 ++ .../src/usb_otg_device/in_endpoint/dtxfsts.rs | 37 + .../src/usb_otg_device/out_endpoint.rs | 30 + .../usb_otg_device/out_endpoint/doepctl.rs | 154 ++ .../usb_otg_device/out_endpoint/doepdma.rs | 80 + .../usb_otg_device/out_endpoint/doepint.rs | 155 ++ .../usb_otg_device/out_endpoint/doeptsiz.rs | 110 ++ crates/bcm2711-lpa/src/usb_otg_global.rs | 198 +++ crates/bcm2711-lpa/src/usb_otg_global/cid.rs | 80 + .../src/usb_otg_global/dieptxf1.rs | 95 ++ .../src/usb_otg_global/dieptxf2.rs | 95 ++ .../src/usb_otg_global/dieptxf3.rs | 95 ++ .../src/usb_otg_global/dieptxf4.rs | 95 ++ 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348 ++++ .../src/usb_otg_global/hw_direction.rs | 157 ++ .../src/usb_otg_global/tx0fsiz_peripheral.rs | 97 ++ crates/bcm2711-lpa/src/usb_otg_global/vid.rs | 24 + crates/bcm2711-lpa/src/usb_otg_host.rs | 89 + crates/bcm2711-lpa/src/usb_otg_host/haint.rs | 37 + .../bcm2711-lpa/src/usb_otg_host/haintmsk.rs | 80 + crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs | 87 + crates/bcm2711-lpa/src/usb_otg_host/hfir.rs | 80 + crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs | 44 + .../src/usb_otg_host/host_channel.rs | 40 + .../src/usb_otg_host/host_channel/hcchar.rs | 215 +++ .../src/usb_otg_host/host_channel/hcdma.rs | 80 + .../src/usb_otg_host/host_channel/hcint.rs | 230 +++ .../src/usb_otg_host/host_channel/hcintmsk.rs | 230 +++ .../src/usb_otg_host/host_channel/hcsplt.rs | 140 ++ .../src/usb_otg_host/host_channel/hctsiz.rs | 110 ++ crates/bcm2711-lpa/src/usb_otg_host/hprt.rs | 228 +++ .../bcm2711-lpa/src/usb_otg_host/hptxsts.rs | 94 ++ crates/bcm2711-lpa/src/usb_otg_pwrclk.rs | 10 + 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crates/bcm2835-lpa/src/emmc/force_irpt.rs | 320 ++++ crates/bcm2835-lpa/src/emmc/interrupt.rs | 327 ++++ crates/bcm2835-lpa/src/emmc/irpt_en.rs | 320 ++++ crates/bcm2835-lpa/src/emmc/irpt_mask.rs | 320 ++++ crates/bcm2835-lpa/src/emmc/resp0.rs | 63 + crates/bcm2835-lpa/src/emmc/resp1.rs | 63 + crates/bcm2835-lpa/src/emmc/resp2.rs | 63 + crates/bcm2835-lpa/src/emmc/resp3.rs | 63 + crates/bcm2835-lpa/src/emmc/slotisr_ver.rs | 111 ++ crates/bcm2835-lpa/src/emmc/spi_int_spt.rs | 80 + crates/bcm2835-lpa/src/emmc/status.rs | 215 +++ crates/bcm2835-lpa/src/emmc/tune_step.rs | 80 + crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs | 80 + crates/bcm2835-lpa/src/emmc/tune_steps_std.rs | 80 + crates/bcm2835-lpa/src/generic.rs | 695 ++++++++ crates/bcm2835-lpa/src/generic/atomic.rs | 27 + crates/bcm2835-lpa/src/gpio.rs | 206 +++ crates/bcm2835-lpa/src/gpio/extra_mux.rs | 122 ++ crates/bcm2835-lpa/src/gpio/gpafen0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gpafen1.rs | 391 +++++ crates/bcm2835-lpa/src/gpio/gparen0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gparen1.rs | 391 +++++ crates/bcm2835-lpa/src/gpio/gpclr0.rs | 296 ++++ crates/bcm2835-lpa/src/gpio/gpclr1.rs | 216 +++ crates/bcm2835-lpa/src/gpio/gpeds0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gpeds1.rs | 391 +++++ crates/bcm2835-lpa/src/gpio/gpfen0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gpfen1.rs | 391 +++++ crates/bcm2835-lpa/src/gpio/gpfsel0.rs | 1481 +++++++++++++++++ crates/bcm2835-lpa/src/gpio/gpfsel1.rs | 1481 +++++++++++++++++ crates/bcm2835-lpa/src/gpio/gpfsel2.rs | 1481 +++++++++++++++++ crates/bcm2835-lpa/src/gpio/gpfsel3.rs | 1481 +++++++++++++++++ crates/bcm2835-lpa/src/gpio/gpfsel4.rs | 1481 +++++++++++++++++ crates/bcm2835-lpa/src/gpio/gpfsel5.rs | 629 +++++++ crates/bcm2835-lpa/src/gpio/gphen0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gphen1.rs | 391 +++++ .../src/gpio/gpio_pup_pdn_cntrl_reg0.rs | 363 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg1.rs | 319 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg2.rs | 319 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg3.rs | 159 ++ crates/bcm2835-lpa/src/gpio/gplen0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gplen1.rs | 391 +++++ crates/bcm2835-lpa/src/gpio/gplev0.rs | 250 +++ crates/bcm2835-lpa/src/gpio/gplev1.rs | 180 ++ crates/bcm2835-lpa/src/gpio/gpren0.rs | 541 ++++++ crates/bcm2835-lpa/src/gpio/gpren1.rs | 391 +++++ crates/bcm2835-lpa/src/gpio/gpset0.rs | 296 ++++ crates/bcm2835-lpa/src/gpio/gpset1.rs | 216 +++ crates/bcm2835-lpa/src/interrupt.rs | 59 + crates/bcm2835-lpa/src/lib.rs | 786 +++++++++ crates/bcm2835-lpa/src/lic.rs | 65 + crates/bcm2835-lpa/src/lic/basic_pending.rs | 177 ++ crates/bcm2835-lpa/src/lic/disable_1.rs | 545 ++++++ crates/bcm2835-lpa/src/lic/disable_2.rs | 545 ++++++ crates/bcm2835-lpa/src/lic/disable_basic.rs | 187 +++ crates/bcm2835-lpa/src/lic/enable_1.rs | 545 ++++++ crates/bcm2835-lpa/src/lic/enable_2.rs | 545 ++++++ crates/bcm2835-lpa/src/lic/enable_basic.rs | 186 +++ crates/bcm2835-lpa/src/lic/fiq_control.rs | 1054 ++++++++++++ crates/bcm2835-lpa/src/lic/pending_1.rs | 254 +++ crates/bcm2835-lpa/src/lic/pending_2.rs | 254 +++ crates/bcm2835-lpa/src/pm.rs | 18 + crates/bcm2835-lpa/src/pm/rstc.rs | 143 ++ crates/bcm2835-lpa/src/pm/wdog.rs | 108 ++ crates/bcm2835-lpa/src/pwm0.rs | 54 + crates/bcm2835-lpa/src/pwm0/ctl.rs | 382 +++++ crates/bcm2835-lpa/src/pwm0/dat1.rs | 63 + crates/bcm2835-lpa/src/pwm0/dat2.rs | 63 + crates/bcm2835-lpa/src/pwm0/dmac.rs | 110 ++ crates/bcm2835-lpa/src/pwm0/fif1.rs | 44 + crates/bcm2835-lpa/src/pwm0/rng1.rs | 63 + crates/bcm2835-lpa/src/pwm0/rng2.rs | 63 + crates/bcm2835-lpa/src/pwm0/sta.rs | 260 +++ crates/bcm2835-lpa/src/spi0.rs | 40 + crates/bcm2835-lpa/src/spi0/clk.rs | 80 + crates/bcm2835-lpa/src/spi0/cs.rs | 446 +++++ crates/bcm2835-lpa/src/spi0/dc.rs | 125 ++ crates/bcm2835-lpa/src/spi0/dlen.rs | 80 + crates/bcm2835-lpa/src/spi0/fifo.rs | 80 + crates/bcm2835-lpa/src/spi0/ltoh.rs | 80 + crates/bcm2835-lpa/src/spi1.rs | 40 + crates/bcm2835-lpa/src/spi1/cntl0.rs | 335 ++++ crates/bcm2835-lpa/src/spi1/cntl1.rs | 140 ++ crates/bcm2835-lpa/src/spi1/io.rs | 80 + crates/bcm2835-lpa/src/spi1/peek.rs | 37 + crates/bcm2835-lpa/src/spi1/stat.rs | 185 ++ crates/bcm2835-lpa/src/spi1/txhold.rs | 80 + crates/bcm2835-lpa/src/systmr.rs | 46 + crates/bcm2835-lpa/src/systmr/c0.rs | 63 + crates/bcm2835-lpa/src/systmr/c1.rs | 63 + crates/bcm2835-lpa/src/systmr/c2.rs | 63 + crates/bcm2835-lpa/src/systmr/c3.rs | 63 + crates/bcm2835-lpa/src/systmr/chi.rs | 28 + crates/bcm2835-lpa/src/systmr/clo.rs | 28 + crates/bcm2835-lpa/src/systmr/cs.rs | 125 ++ crates/bcm2835-lpa/src/uart0.rs | 99 ++ crates/bcm2835-lpa/src/uart0/cr.rs | 200 +++ crates/bcm2835-lpa/src/uart0/dmacr.rs | 110 ++ crates/bcm2835-lpa/src/uart0/dr.rs | 140 ++ crates/bcm2835-lpa/src/uart0/ecr.rs | 76 + crates/bcm2835-lpa/src/uart0/fbrd.rs | 80 + crates/bcm2835-lpa/src/uart0/fr.rs | 200 +++ crates/bcm2835-lpa/src/uart0/ibrd.rs | 80 + crates/bcm2835-lpa/src/uart0/icr.rs | 132 ++ crates/bcm2835-lpa/src/uart0/ifls.rs | 95 ++ crates/bcm2835-lpa/src/uart0/imsc.rs | 230 +++ crates/bcm2835-lpa/src/uart0/lcr_h.rs | 170 ++ crates/bcm2835-lpa/src/uart0/mis.rs | 107 ++ crates/bcm2835-lpa/src/uart0/ris.rs | 107 ++ crates/bcm2835-lpa/src/uart0/rsr.rs | 58 + crates/bcm2835-lpa/src/uart1.rs | 99 ++ crates/bcm2835-lpa/src/uart1/baud.rs | 63 + crates/bcm2835-lpa/src/uart1/baudh.rs | 63 + crates/bcm2835-lpa/src/uart1/baudl.rs | 63 + crates/bcm2835-lpa/src/uart1/cntl.rs | 291 ++++ crates/bcm2835-lpa/src/uart1/ier.rs | 95 ++ crates/bcm2835-lpa/src/uart1/iir.rs | 110 ++ crates/bcm2835-lpa/src/uart1/io.rs | 80 + crates/bcm2835-lpa/src/uart1/lcr.rs | 158 ++ crates/bcm2835-lpa/src/uart1/lsr.rs | 125 ++ crates/bcm2835-lpa/src/uart1/mcr.rs | 80 + crates/bcm2835-lpa/src/uart1/msr.rs | 80 + crates/bcm2835-lpa/src/uart1/scratch.rs | 63 + crates/bcm2835-lpa/src/uart1/stat.rs | 245 +++ crates/bcm2835-lpa/src/usb_otg_device.rs | 179 ++ .../bcm2835-lpa/src/usb_otg_device/daint.rs | 44 + .../src/usb_otg_device/daintmsk.rs | 95 ++ crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs | 140 ++ crates/bcm2835-lpa/src/usb_otg_device/dctl.rs | 171 ++ .../src/usb_otg_device/deachint.rs | 95 ++ .../src/usb_otg_device/deachintmsk.rs | 95 ++ .../src/usb_otg_device/diepeachmsk1.rs | 200 +++ .../src/usb_otg_device/diepempmsk.rs | 81 + .../bcm2835-lpa/src/usb_otg_device/diepmsk.rs | 185 ++ .../src/usb_otg_device/doepeachmsk1.rs | 230 +++ .../bcm2835-lpa/src/usb_otg_device/doepmsk.rs | 170 ++ crates/bcm2835-lpa/src/usb_otg_device/dsts.rs | 58 + .../bcm2835-lpa/src/usb_otg_device/dthrctl.rs | 155 ++ .../src/usb_otg_device/dvbusdis.rs | 80 + .../src/usb_otg_device/dvbuspulse.rs | 80 + .../src/usb_otg_device/in_endpoint.rs | 36 + .../usb_otg_device/in_endpoint/diepctl0.rs | 216 +++ .../src/usb_otg_device/in_endpoint/diepdma.rs | 80 + .../src/usb_otg_device/in_endpoint/diepint.rs | 222 +++ .../usb_otg_device/in_endpoint/dieptsiz.rs | 95 ++ .../src/usb_otg_device/in_endpoint/dtxfsts.rs | 37 + .../src/usb_otg_device/out_endpoint.rs | 30 + .../usb_otg_device/out_endpoint/doepctl.rs | 154 ++ .../usb_otg_device/out_endpoint/doepdma.rs | 80 + .../usb_otg_device/out_endpoint/doepint.rs | 155 ++ .../usb_otg_device/out_endpoint/doeptsiz.rs | 110 ++ crates/bcm2835-lpa/src/usb_otg_global.rs | 198 +++ crates/bcm2835-lpa/src/usb_otg_global/cid.rs | 80 + .../src/usb_otg_global/dieptxf1.rs | 95 ++ .../src/usb_otg_global/dieptxf2.rs | 95 ++ .../src/usb_otg_global/dieptxf3.rs | 95 ++ .../src/usb_otg_global/dieptxf4.rs | 95 ++ .../src/usb_otg_global/dieptxf5.rs | 95 ++ .../src/usb_otg_global/dieptxf6.rs | 95 ++ .../src/usb_otg_global/dieptxf7.rs | 95 ++ .../bcm2835-lpa/src/usb_otg_global/gahbcfg.rs | 230 +++ .../bcm2835-lpa/src/usb_otg_global/gccfg.rs | 155 ++ .../bcm2835-lpa/src/usb_otg_global/gintmsk.rs | 447 +++++ .../bcm2835-lpa/src/usb_otg_global/gintsts.rs | 367 ++++ .../src/usb_otg_global/gnptxfsiz_host.rs | 97 ++ .../src/usb_otg_global/gnptxsts.rs | 51 + .../bcm2835-lpa/src/usb_otg_global/gotgctl.rs | 167 ++ .../bcm2835-lpa/src/usb_otg_global/gotgint.rs | 155 ++ .../bcm2835-lpa/src/usb_otg_global/grstctl.rs | 169 ++ .../bcm2835-lpa/src/usb_otg_global/grxfsiz.rs | 80 + .../src/usb_otg_global/grxstsp_host.rs | 58 + .../src/usb_otg_global/grxstsp_peripheral.rs | 65 + .../src/usb_otg_global/grxstsr_host.rs | 58 + .../src/usb_otg_global/grxstsr_peripheral.rs | 65 + .../bcm2835-lpa/src/usb_otg_global/gusbcfg.rs | 625 +++++++ .../src/usb_otg_global/hptxfsiz.rs | 95 ++ .../src/usb_otg_global/hw_config0.rs | 348 ++++ .../src/usb_otg_global/hw_direction.rs | 157 ++ .../src/usb_otg_global/tx0fsiz_peripheral.rs | 97 ++ crates/bcm2835-lpa/src/usb_otg_global/vid.rs | 24 + crates/bcm2835-lpa/src/usb_otg_host.rs | 89 + crates/bcm2835-lpa/src/usb_otg_host/haint.rs | 37 + .../bcm2835-lpa/src/usb_otg_host/haintmsk.rs | 80 + crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs | 87 + crates/bcm2835-lpa/src/usb_otg_host/hfir.rs | 80 + crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs | 44 + .../src/usb_otg_host/host_channel.rs | 40 + .../src/usb_otg_host/host_channel/hcchar.rs | 215 +++ .../src/usb_otg_host/host_channel/hcdma.rs | 80 + .../src/usb_otg_host/host_channel/hcint.rs | 230 +++ .../src/usb_otg_host/host_channel/hcintmsk.rs | 230 +++ .../src/usb_otg_host/host_channel/hcsplt.rs | 140 ++ .../src/usb_otg_host/host_channel/hctsiz.rs | 110 ++ crates/bcm2835-lpa/src/usb_otg_host/hprt.rs | 228 +++ .../bcm2835-lpa/src/usb_otg_host/hptxsts.rs | 94 ++ crates/bcm2835-lpa/src/usb_otg_pwrclk.rs | 10 + .../bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs | 293 ++++ crates/bcm2835-lpa/src/vcmailbox.rs | 66 + crates/bcm2835-lpa/src/vcmailbox/config0.rs | 76 + crates/bcm2835-lpa/src/vcmailbox/config1.rs | 59 + crates/bcm2835-lpa/src/vcmailbox/peek0.rs | 59 + crates/bcm2835-lpa/src/vcmailbox/peek1.rs | 59 + crates/bcm2835-lpa/src/vcmailbox/read.rs | 24 + crates/bcm2835-lpa/src/vcmailbox/sender0.rs | 59 + crates/bcm2835-lpa/src/vcmailbox/sender1.rs | 59 + crates/bcm2835-lpa/src/vcmailbox/status0.rs | 40 + crates/bcm2835-lpa/src/vcmailbox/status1.rs | 59 + crates/bcm2835-lpa/src/vcmailbox/write.rs | 40 + crates/bcm2837-lpa/.gitignore | 2 + crates/bcm2837-lpa/Cargo.toml | 19 + crates/bcm2837-lpa/README.md | 16 + crates/bcm2837-lpa/src/aux.rs | 16 + crates/bcm2837-lpa/src/aux/enables.rs | 110 ++ crates/bcm2837-lpa/src/aux/irq.rs | 110 ++ crates/bcm2837-lpa/src/bsc0.rs | 52 + crates/bcm2837-lpa/src/bsc0/a.rs | 80 + crates/bcm2837-lpa/src/bsc0/c.rs | 170 ++ crates/bcm2837-lpa/src/bsc0/clkt.rs | 80 + crates/bcm2837-lpa/src/bsc0/del.rs | 95 ++ crates/bcm2837-lpa/src/bsc0/div.rs | 80 + crates/bcm2837-lpa/src/bsc0/dlen.rs | 80 + crates/bcm2837-lpa/src/bsc0/fifo.rs | 80 + crates/bcm2837-lpa/src/bsc0/s.rs | 159 ++ crates/bcm2837-lpa/src/cm_pcm.rs | 16 + crates/bcm2837-lpa/src/cm_pcm/cs.rs | 288 ++++ crates/bcm2837-lpa/src/cm_pcm/div.rs | 123 ++ crates/bcm2837-lpa/src/emmc.rs | 165 ++ crates/bcm2837-lpa/src/emmc/arg1.rs | 63 + crates/bcm2837-lpa/src/emmc/arg2.rs | 63 + crates/bcm2837-lpa/src/emmc/blksizecnt.rs | 95 ++ crates/bcm2837-lpa/src/emmc/boot_timeout.rs | 63 + crates/bcm2837-lpa/src/emmc/cmdtm.rs | 520 ++++++ crates/bcm2837-lpa/src/emmc/control0.rs | 215 +++ crates/bcm2837-lpa/src/emmc/control1.rs | 253 +++ crates/bcm2837-lpa/src/emmc/control2.rs | 240 +++ crates/bcm2837-lpa/src/emmc/data.rs | 63 + crates/bcm2837-lpa/src/emmc/dbg_sel.rs | 126 ++ crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs | 80 + crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs | 80 + crates/bcm2837-lpa/src/emmc/force_irpt.rs | 320 ++++ crates/bcm2837-lpa/src/emmc/interrupt.rs | 327 ++++ crates/bcm2837-lpa/src/emmc/irpt_en.rs | 320 ++++ crates/bcm2837-lpa/src/emmc/irpt_mask.rs | 320 ++++ crates/bcm2837-lpa/src/emmc/resp0.rs | 63 + crates/bcm2837-lpa/src/emmc/resp1.rs | 63 + crates/bcm2837-lpa/src/emmc/resp2.rs | 63 + crates/bcm2837-lpa/src/emmc/resp3.rs | 63 + crates/bcm2837-lpa/src/emmc/slotisr_ver.rs | 111 ++ crates/bcm2837-lpa/src/emmc/spi_int_spt.rs | 80 + crates/bcm2837-lpa/src/emmc/status.rs | 215 +++ crates/bcm2837-lpa/src/emmc/tune_step.rs | 80 + crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs | 80 + crates/bcm2837-lpa/src/emmc/tune_steps_std.rs | 80 + crates/bcm2837-lpa/src/generic.rs | 695 ++++++++ crates/bcm2837-lpa/src/generic/atomic.rs | 27 + crates/bcm2837-lpa/src/gpio.rs | 206 +++ crates/bcm2837-lpa/src/gpio/extra_mux.rs | 122 ++ crates/bcm2837-lpa/src/gpio/gpafen0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gpafen1.rs | 391 +++++ crates/bcm2837-lpa/src/gpio/gparen0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gparen1.rs | 391 +++++ crates/bcm2837-lpa/src/gpio/gpclr0.rs | 296 ++++ crates/bcm2837-lpa/src/gpio/gpclr1.rs | 216 +++ crates/bcm2837-lpa/src/gpio/gpeds0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gpeds1.rs | 391 +++++ crates/bcm2837-lpa/src/gpio/gpfen0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gpfen1.rs | 391 +++++ crates/bcm2837-lpa/src/gpio/gpfsel0.rs | 1481 +++++++++++++++++ crates/bcm2837-lpa/src/gpio/gpfsel1.rs | 1481 +++++++++++++++++ crates/bcm2837-lpa/src/gpio/gpfsel2.rs | 1481 +++++++++++++++++ crates/bcm2837-lpa/src/gpio/gpfsel3.rs | 1481 +++++++++++++++++ crates/bcm2837-lpa/src/gpio/gpfsel4.rs | 1481 +++++++++++++++++ crates/bcm2837-lpa/src/gpio/gpfsel5.rs | 629 +++++++ crates/bcm2837-lpa/src/gpio/gphen0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gphen1.rs | 391 +++++ .../src/gpio/gpio_pup_pdn_cntrl_reg0.rs | 363 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg1.rs | 319 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg2.rs | 319 ++++ .../src/gpio/gpio_pup_pdn_cntrl_reg3.rs | 159 ++ crates/bcm2837-lpa/src/gpio/gplen0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gplen1.rs | 391 +++++ crates/bcm2837-lpa/src/gpio/gplev0.rs | 250 +++ crates/bcm2837-lpa/src/gpio/gplev1.rs | 180 ++ crates/bcm2837-lpa/src/gpio/gpren0.rs | 541 ++++++ crates/bcm2837-lpa/src/gpio/gpren1.rs | 391 +++++ crates/bcm2837-lpa/src/gpio/gpset0.rs | 296 ++++ crates/bcm2837-lpa/src/gpio/gpset1.rs | 216 +++ crates/bcm2837-lpa/src/interrupt.rs | 59 + crates/bcm2837-lpa/src/lib.rs | 753 +++++++++ crates/bcm2837-lpa/src/lic.rs | 65 + crates/bcm2837-lpa/src/lic/basic_pending.rs | 177 ++ crates/bcm2837-lpa/src/lic/disable_1.rs | 545 ++++++ crates/bcm2837-lpa/src/lic/disable_2.rs | 545 ++++++ crates/bcm2837-lpa/src/lic/disable_basic.rs | 187 +++ crates/bcm2837-lpa/src/lic/enable_1.rs | 545 ++++++ crates/bcm2837-lpa/src/lic/enable_2.rs | 545 ++++++ crates/bcm2837-lpa/src/lic/enable_basic.rs | 186 +++ crates/bcm2837-lpa/src/lic/fiq_control.rs | 1054 ++++++++++++ crates/bcm2837-lpa/src/lic/pending_1.rs | 254 +++ crates/bcm2837-lpa/src/lic/pending_2.rs | 254 +++ crates/bcm2837-lpa/src/pwm0.rs | 54 + crates/bcm2837-lpa/src/pwm0/ctl.rs | 382 +++++ crates/bcm2837-lpa/src/pwm0/dat1.rs | 63 + crates/bcm2837-lpa/src/pwm0/dat2.rs | 63 + crates/bcm2837-lpa/src/pwm0/dmac.rs | 110 ++ crates/bcm2837-lpa/src/pwm0/fif1.rs | 44 + crates/bcm2837-lpa/src/pwm0/rng1.rs | 63 + crates/bcm2837-lpa/src/pwm0/rng2.rs | 63 + crates/bcm2837-lpa/src/pwm0/sta.rs | 260 +++ crates/bcm2837-lpa/src/spi0.rs | 40 + crates/bcm2837-lpa/src/spi0/clk.rs | 80 + crates/bcm2837-lpa/src/spi0/cs.rs | 446 +++++ crates/bcm2837-lpa/src/spi0/dc.rs | 125 ++ crates/bcm2837-lpa/src/spi0/dlen.rs | 80 + crates/bcm2837-lpa/src/spi0/fifo.rs | 80 + crates/bcm2837-lpa/src/spi0/ltoh.rs | 80 + crates/bcm2837-lpa/src/spi1.rs | 40 + crates/bcm2837-lpa/src/spi1/cntl0.rs | 335 ++++ crates/bcm2837-lpa/src/spi1/cntl1.rs | 140 ++ crates/bcm2837-lpa/src/spi1/io.rs | 80 + crates/bcm2837-lpa/src/spi1/peek.rs | 37 + crates/bcm2837-lpa/src/spi1/stat.rs | 185 ++ crates/bcm2837-lpa/src/spi1/txhold.rs | 80 + crates/bcm2837-lpa/src/systmr.rs | 46 + crates/bcm2837-lpa/src/systmr/c0.rs | 63 + crates/bcm2837-lpa/src/systmr/c1.rs | 63 + crates/bcm2837-lpa/src/systmr/c2.rs | 63 + crates/bcm2837-lpa/src/systmr/c3.rs | 63 + crates/bcm2837-lpa/src/systmr/chi.rs | 28 + crates/bcm2837-lpa/src/systmr/clo.rs | 28 + crates/bcm2837-lpa/src/systmr/cs.rs | 125 ++ crates/bcm2837-lpa/src/uart0.rs | 99 ++ crates/bcm2837-lpa/src/uart0/cr.rs | 200 +++ crates/bcm2837-lpa/src/uart0/dmacr.rs | 110 ++ crates/bcm2837-lpa/src/uart0/dr.rs | 140 ++ crates/bcm2837-lpa/src/uart0/ecr.rs | 76 + crates/bcm2837-lpa/src/uart0/fbrd.rs | 80 + crates/bcm2837-lpa/src/uart0/fr.rs | 200 +++ crates/bcm2837-lpa/src/uart0/ibrd.rs | 80 + crates/bcm2837-lpa/src/uart0/icr.rs | 132 ++ crates/bcm2837-lpa/src/uart0/ifls.rs | 95 ++ crates/bcm2837-lpa/src/uart0/imsc.rs | 230 +++ crates/bcm2837-lpa/src/uart0/lcr_h.rs | 170 ++ crates/bcm2837-lpa/src/uart0/mis.rs | 107 ++ crates/bcm2837-lpa/src/uart0/ris.rs | 107 ++ crates/bcm2837-lpa/src/uart0/rsr.rs | 58 + crates/bcm2837-lpa/src/uart1.rs | 99 ++ crates/bcm2837-lpa/src/uart1/baud.rs | 63 + crates/bcm2837-lpa/src/uart1/baudh.rs | 63 + crates/bcm2837-lpa/src/uart1/baudl.rs | 63 + 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crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_global/vid.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/haint.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/hfir.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/hprt.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_pwrclk.rs create mode 100644 crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/config0.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/config1.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/peek0.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/peek1.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/read.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/sender0.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/sender1.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/status0.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/status1.rs create mode 100644 crates/bcm2837-lpa/src/vcmailbox/write.rs create mode 100755 gen.sh create mode 160000 peripherals diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml new file mode 100644 index 0000000..6a67375 --- /dev/null +++ b/.github/workflows/check.yml @@ -0,0 +1,26 @@ +name: Check + +on: [push, pull_request] + +jobs: + + check: + + strategy: + matrix: + mcu: [bcm2835, bcm2837, bcm2711] + rust-version: [1.61.0, 1.62.1, 1.63.0, 1.64.0, 1.65.0, 1.66.1, 1.67.1, 1.68.0] + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v3 + + - name: Install Rust + run: rustup default ${{ matrix.rust-version }} + + - name: Check crate + working-directory: crates/${{ matrix.mcu }}-lpa + run: | + cargo check + cargo check --all-features diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..b997735 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,4 @@ +[submodule "peripherals"] + path = peripherals + url = https://github.com/abt8601/broadcom-peripherals.git + branch = main-build diff --git a/README.md b/README.md index c8511fd..4b13369 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,49 @@ # raspi-pacs -Peripheral access crates for the Broadcom microprocessors used in the Raspberry Pi boards + +[![crates.io](https://img.shields.io/crates/v/bcm2835-lpa.svg?label=crates.io%20%28bcm2835-lpa%29)](https://crates.io/crates/bcm2835-lpa) +[![docs.rs](https://img.shields.io/docsrs/bcm2835-lpa?label=docs%20%28bcm2835-lpa%29)](https://docs.rs/bcm2835-lpa) + +[![crates.io](https://img.shields.io/crates/v/bcm2837-lpa.svg?label=crates.io%20%28bcm2837-lpa%29)](https://crates.io/crates/bcm2837-lpa) +[![docs.rs](https://img.shields.io/docsrs/bcm2837-lpa?label=docs%20%28bcm2837-lpa%29)](https://docs.rs/bcm2837-lpa) + +[![crates.io](https://img.shields.io/crates/v/bcm2711-lpa.svg?label=crates.io%20%28bcm2711-lpa%29)](https://crates.io/crates/bcm2711-lpa) +[![docs.rs](https://img.shields.io/docsrs/bcm2711-lpa?label=docs%20%28bcm2711-lpa%29)](https://docs.rs/bcm2711-lpa) + +Peripheral access crates +for the Broadcom microprocessors used in the Raspberry Pi boards. + +This repository contains the PACs for the following MCUs: + +- [BCM2835](crates/bcm2835-lpa/) +- [BCM2837](crates/bcm2837-lpa/) +- [BCM2711](crates/bcm2711-lpa/) + +These crates are generated by [`svd2rust`](https://crates.io/crates/svd2rust) +from the +[SVD files](https://github.com/abt8601/broadcom-peripherals/tree/main-build/svd/gen) +in +[`abt8601/broadcom-peripherals`](https://github.com/abt8601/broadcom-peripherals/tree/main-build), +which are based on those in +[`adafruit/broadcom-peripherals`](https://github.com/adafruit/broadcom-peripherals/tree/main-build). +(The SVD files in these two repositories are identical, +save that those in the former has the missing tags required by `svd2rust`.) + +## Generating the Crates + +### Prerequisites + +- Rust toolchain with `cargo` and `rustfmt` +- [`svd2rust`](https://crates.io/crates/svd2rust) +- [`form`](https://crates.io/crates/form) + +Also, the submodule `peripherals` must be checked out. + +### Generating + +To generate the PAC for a particular MCU, run: + +```sh +./gen.sh +``` + +where `` is one of `bcm2835`, `bcm2837`, or `bcm2711`. diff --git a/crates/bcm2711-lpa/.gitignore b/crates/bcm2711-lpa/.gitignore new file mode 100644 index 0000000..4fffb2f --- /dev/null +++ b/crates/bcm2711-lpa/.gitignore @@ -0,0 +1,2 @@ +/target +/Cargo.lock diff --git a/crates/bcm2711-lpa/Cargo.toml b/crates/bcm2711-lpa/Cargo.toml new file mode 100644 index 0000000..9c22170 --- /dev/null +++ b/crates/bcm2711-lpa/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "bcm2711-lpa" +version = "0.1.0" +authors = ["Po-Yi Tsai "] +edition = "2021" +rust-version = "1.61.0" +description = "Peripheral access crate for BCM2711 found in the Raspberry Pi 4." +repository = "https://github.com/abt8601/raspi-pacs" +license = "Unlicense" +keywords = ["raspberrypi", "bcm2711", "pac"] +categories = ["embedded", "hardware-support", "no-std", "no-std::no-alloc"] + +[dependencies] +critical-section = { version = "1.0", optional = true } +vcell = "0.1.0" +portable-atomic = { version = "0.3.16", default-features = false } + +[features] +rt = [] diff --git a/crates/bcm2711-lpa/README.md b/crates/bcm2711-lpa/README.md new file mode 100644 index 0000000..03be82a --- /dev/null +++ b/crates/bcm2711-lpa/README.md @@ -0,0 +1,16 @@ +# bcm2711-lpa + +[![crates.io](https://img.shields.io/crates/v/bcm2711-lpa.svg)](https://crates.io/crates/bcm2711-lpa) +[![docs.rs](https://img.shields.io/docsrs/bcm2711-lpa)](https://docs.rs/bcm2711-lpa) + +Peripheral access crate for BCM2711 found in the Raspberry Pi 4. + +This crate is generated by [`svd2rust`](https://crates.io/crates/svd2rust) +from the +[SVD file](https://github.com/abt8601/broadcom-peripherals/blob/6bc44a4fd5c956249b9d8815f66a9df41b5791b1/svd/gen/bcm2711_lpa.svd) +in +[`abt8601/broadcom-peripherals@6bc44a4`](https://github.com/abt8601/broadcom-peripherals/tree/6bc44a4fd5c956249b9d8815f66a9df41b5791b1), +which is based on that in +[`adafruit/broadcom-peripherals@d3a6b50`](https://github.com/adafruit/broadcom-peripherals/tree/d3a6b50a21e7dd49ba4bfa0374da3407594caa50). +(The SVD files in these two repositories are identical, +save that that in the former has the missing tags required by `svd2rust`.) diff --git a/crates/bcm2711-lpa/src/aux.rs b/crates/bcm2711-lpa/src/aux.rs new file mode 100644 index 0000000..5380cb2 --- /dev/null +++ b/crates/bcm2711-lpa/src/aux.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt status"] + pub irq: IRQ, + #[doc = "0x04 - Enable sub-peripherals"] + pub enables: ENABLES, +} +#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +pub type IRQ = crate::Reg; +#[doc = "Interrupt status"] +pub mod irq; +#[doc = "ENABLES (rw) register accessor: an alias for `Reg`"] +pub type ENABLES = crate::Reg; +#[doc = "Enable sub-peripherals"] +pub mod enables; diff --git a/crates/bcm2711-lpa/src/aux/enables.rs b/crates/bcm2711-lpa/src/aux/enables.rs new file mode 100644 index 0000000..eb9fc6d --- /dev/null +++ b/crates/bcm2711-lpa/src/aux/enables.rs @@ -0,0 +1,110 @@ +#[doc = "Register `ENABLES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLES` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UART_1` reader - UART1 enabled"] +pub type UART_1_R = crate::BitReader; +#[doc = "Field `UART_1` writer - UART1 enabled"] +pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 enabled"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 enabled"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 enabled"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 enabled"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UART1 enabled"] + #[inline(always)] + pub fn uart_1(&self) -> UART_1_R { + UART_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 enabled"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 enabled"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART1 enabled"] + #[inline(always)] + #[must_use] + pub fn uart_1(&mut self) -> UART_1_W<0> { + UART_1_W::new(self) + } + #[doc = "Bit 1 - SPI1 enabled"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 enabled"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"] +pub struct ENABLES_SPEC; +impl crate::RegisterSpec for ENABLES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enables::R](R) reader structure"] +impl crate::Readable for ENABLES_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"] +impl crate::Writable for ENABLES_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLES to value 0"] +impl crate::Resettable for ENABLES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/aux/irq.rs b/crates/bcm2711-lpa/src/aux/irq.rs new file mode 100644 index 0000000..a59c319 --- /dev/null +++ b/crates/bcm2711-lpa/src/aux/irq.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IRQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UART_1` reader - UART1 interrupt active"] +pub type UART_1_R = crate::BitReader; +#[doc = "Field `UART_1` writer - UART1 interrupt active"] +pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 interrupt active"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 interrupt active"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 interrupt active"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 interrupt active"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UART1 interrupt active"] + #[inline(always)] + pub fn uart_1(&self) -> UART_1_R { + UART_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_1(&mut self) -> UART_1_W<0> { + UART_1_W::new(self) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"] +pub struct IRQ_SPEC; +impl crate::RegisterSpec for IRQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq::R](R) reader structure"] +impl crate::Readable for IRQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +impl crate::Writable for IRQ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRQ to value 0"] +impl crate::Resettable for IRQ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/bsc0.rs b/crates/bcm2711-lpa/src/bsc0.rs new file mode 100644 index 0000000..8ccfb52 --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub c: C, + #[doc = "0x04 - Status"] + pub s: S, + #[doc = "0x08 - Data length"] + pub dlen: DLEN, + #[doc = "0x0c - Slave address"] + pub a: A, + #[doc = "0x10 - Data FIFO"] + pub fifo: FIFO, + #[doc = "0x14 - Clock divider"] + pub div: DIV, + #[doc = "0x18 - Data delay (Values must be under CDIV / 2)"] + pub del: DEL, + #[doc = "0x1c - Clock stretch timeout (broken on 283x)"] + pub clkt: CLKT, +} +#[doc = "C (rw) register accessor: an alias for `Reg`"] +pub type C = crate::Reg; +#[doc = "Control"] +pub mod c; +#[doc = "S (rw) register accessor: an alias for `Reg`"] +pub type S = crate::Reg; +#[doc = "Status"] +pub mod s; +#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +pub type DLEN = crate::Reg; +#[doc = "Data length"] +pub mod dlen; +#[doc = "A (rw) register accessor: an alias for `Reg`"] +pub type A = crate::Reg; +#[doc = "Slave address"] +pub mod a; +#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +pub type FIFO = crate::Reg; +#[doc = "Data FIFO"] +pub mod fifo; +#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +pub type DIV = crate::Reg; +#[doc = "Clock divider"] +pub mod div; +#[doc = "DEL (rw) register accessor: an alias for `Reg`"] +pub type DEL = crate::Reg; +#[doc = "Data delay (Values must be under CDIV / 2)"] +pub mod del; +#[doc = "CLKT (rw) register accessor: an alias for `Reg`"] +pub type CLKT = crate::Reg; +#[doc = "Clock stretch timeout (broken on 283x)"] +pub mod clkt; diff --git a/crates/bcm2711-lpa/src/bsc0/a.rs b/crates/bcm2711-lpa/src/bsc0/a.rs new file mode 100644 index 0000000..d98d147 --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/a.rs @@ -0,0 +1,80 @@ +#[doc = "Register `A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Slave address"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Slave address"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, A_SPEC, u8, u8, 7, O>; +impl R { + #[doc = "Bits 0:6 - Slave address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Slave address"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<0> { + ADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [a](index.html) module"] +pub struct A_SPEC; +impl crate::RegisterSpec for A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [a::R](R) reader structure"] +impl crate::Readable for A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [a::W](W) writer structure"] +impl crate::Writable for A_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A to value 0"] +impl crate::Resettable for A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/bsc0/c.rs b/crates/bcm2711-lpa/src/bsc0/c.rs new file mode 100644 index 0000000..f62d48d --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/c.rs @@ -0,0 +1,170 @@ +#[doc = "Register `C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READ` reader - Transfer is read"] +pub type READ_R = crate::BitReader; +#[doc = "Field `READ` writer - Transfer is read"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `CLEAR` reader - Clear the FIFO"] +pub type CLEAR_R = crate::FieldReader; +#[doc = "Field `CLEAR` writer - Clear the FIFO"] +pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, C_SPEC, u8, u8, 2, O>; +#[doc = "Field `ST` reader - Start transfer"] +pub type ST_R = crate::BitReader; +#[doc = "Field `ST` writer - Start transfer"] +pub type ST_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTD` reader - Interrupt on done"] +pub type INTD_R = crate::BitReader; +#[doc = "Field `INTD` writer - Interrupt on done"] +pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTT` reader - Interrupt on TX"] +pub type INTT_R = crate::BitReader; +#[doc = "Field `INTT` writer - Interrupt on TX"] +pub type INTT_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTR` reader - Interrupt on RX"] +pub type INTR_R = crate::BitReader; +#[doc = "Field `INTR` writer - Interrupt on RX"] +pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `I2CEN` reader - I2C Enable"] +pub type I2CEN_R = crate::BitReader; +#[doc = "Field `I2CEN` writer - I2C Enable"] +pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer is read"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:5 - Clear the FIFO"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Start transfer"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt on done"] + #[inline(always)] + pub fn intd(&self) -> INTD_R { + INTD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on TX"] + #[inline(always)] + pub fn intt(&self) -> INTT_R { + INTT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 15 - I2C Enable"] + #[inline(always)] + pub fn i2cen(&self) -> I2CEN_R { + I2CEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer is read"] + #[inline(always)] + #[must_use] + pub fn read(&mut self) -> READ_W<0> { + READ_W::new(self) + } + #[doc = "Bits 4:5 - Clear the FIFO"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<4> { + CLEAR_W::new(self) + } + #[doc = "Bit 7 - Start transfer"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> ST_W<7> { + ST_W::new(self) + } + #[doc = "Bit 8 - Interrupt on done"] + #[inline(always)] + #[must_use] + pub fn intd(&mut self) -> INTD_W<8> { + INTD_W::new(self) + } + #[doc = "Bit 9 - Interrupt on TX"] + #[inline(always)] + #[must_use] + pub fn intt(&mut self) -> INTT_W<9> { + INTT_W::new(self) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W<10> { + INTR_W::new(self) + } + #[doc = "Bit 15 - I2C Enable"] + #[inline(always)] + #[must_use] + pub fn i2cen(&mut self) -> I2CEN_W<15> { + I2CEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c](index.html) module"] +pub struct C_SPEC; +impl crate::RegisterSpec for C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c::R](R) reader structure"] +impl crate::Readable for C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c::W](W) writer structure"] +impl crate::Writable for C_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C to value 0"] +impl crate::Resettable for C_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/bsc0/clkt.rs b/crates/bcm2711-lpa/src/bsc0/clkt.rs new file mode 100644 index 0000000..15bc5c4 --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/clkt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CLKT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"] +pub type TOUT_R = crate::FieldReader; +#[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"] +pub type TOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] + #[inline(always)] + pub fn tout(&self) -> TOUT_R { + TOUT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] + #[inline(always)] + #[must_use] + pub fn tout(&mut self) -> TOUT_W<0> { + TOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock stretch timeout (broken on 283x)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkt](index.html) module"] +pub struct CLKT_SPEC; +impl crate::RegisterSpec for CLKT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkt::R](R) reader structure"] +impl crate::Readable for CLKT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkt::W](W) writer structure"] +impl crate::Writable for CLKT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKT to value 0"] +impl crate::Resettable for CLKT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/bsc0/del.rs b/crates/bcm2711-lpa/src/bsc0/del.rs new file mode 100644 index 0000000..c39336b --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/del.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REDL` reader - Delay before reading after a rising edge"] +pub type REDL_R = crate::FieldReader; +#[doc = "Field `REDL` writer - Delay before reading after a rising edge"] +pub type REDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +#[doc = "Field `FEDL` reader - Delay before reading after a falling edge"] +pub type FEDL_R = crate::FieldReader; +#[doc = "Field `FEDL` writer - Delay before reading after a falling edge"] +pub type FEDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Delay before reading after a rising edge"] + #[inline(always)] + pub fn redl(&self) -> REDL_R { + REDL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Delay before reading after a falling edge"] + #[inline(always)] + pub fn fedl(&self) -> FEDL_R { + FEDL_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Delay before reading after a rising edge"] + #[inline(always)] + #[must_use] + pub fn redl(&mut self) -> REDL_W<0> { + REDL_W::new(self) + } + #[doc = "Bits 16:31 - Delay before reading after a falling edge"] + #[inline(always)] + #[must_use] + pub fn fedl(&mut self) -> FEDL_W<16> { + FEDL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data delay (Values must be under CDIV / 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [del](index.html) module"] +pub struct DEL_SPEC; +impl crate::RegisterSpec for DEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [del::R](R) reader structure"] +impl crate::Readable for DEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [del::W](W) writer structure"] +impl crate::Writable for DEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEL to value 0x0030_0030"] +impl crate::Resettable for DEL_SPEC { + const RESET_VALUE: Self::Ux = 0x0030_0030; +} diff --git a/crates/bcm2711-lpa/src/bsc0/div.rs b/crates/bcm2711-lpa/src/bsc0/div.rs new file mode 100644 index 0000000..ce0aa5a --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/div.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CDIV` reader - Divide the source clock"] +pub type CDIV_R = crate::FieldReader; +#[doc = "Field `CDIV` writer - Divide the source clock"] +pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Divide the source clock"] + #[inline(always)] + pub fn cdiv(&self) -> CDIV_R { + CDIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Divide the source clock"] + #[inline(always)] + #[must_use] + pub fn cdiv(&mut self) -> CDIV_W<0> { + CDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [div::R](R) reader structure"] +impl crate::Readable for DIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIV to value 0x05dc"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: Self::Ux = 0x05dc; +} diff --git a/crates/bcm2711-lpa/src/bsc0/dlen.rs b/crates/bcm2711-lpa/src/bsc0/dlen.rs new file mode 100644 index 0000000..25e2771 --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/dlen.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLEN` reader - Data length"] +pub type DLEN_R = crate::FieldReader; +#[doc = "Field `DLEN` writer - Data length"] +pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + pub fn dlen(&self) -> DLEN_R { + DLEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + #[must_use] + pub fn dlen(&mut self) -> DLEN_W<0> { + DLEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +pub struct DLEN_SPEC; +impl crate::RegisterSpec for DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dlen::R](R) reader structure"] +impl crate::Readable for DLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +impl crate::Writable for DLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLEN to value 0"] +impl crate::Resettable for DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/bsc0/fifo.rs b/crates/bcm2711-lpa/src/bsc0/fifo.rs new file mode 100644 index 0000000..f85912b --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/fifo.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FIFO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Access the FIFO"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Access the FIFO"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Access the FIFO"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Access the FIFO"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo::R](R) reader structure"] +impl crate::Readable for FIFO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/bsc0/s.rs b/crates/bcm2711-lpa/src/bsc0/s.rs new file mode 100644 index 0000000..45f365b --- /dev/null +++ b/crates/bcm2711-lpa/src/bsc0/s.rs @@ -0,0 +1,159 @@ +#[doc = "Register `S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TA` reader - Transfer active"] +pub type TA_R = crate::BitReader; +#[doc = "Field `DONE` reader - Transfer done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Transfer done"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +#[doc = "Field `TXW` reader - FIFO needs to be written"] +pub type TXW_R = crate::BitReader; +#[doc = "Field `RXR` reader - FIFO needs to be read"] +pub type RXR_R = crate::BitReader; +#[doc = "Field `TXD` reader - FIFO has space for at least one byte"] +pub type TXD_R = crate::BitReader; +#[doc = "Field `RXD` reader - FIFO contains at least one byte"] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXE` reader - FIFO is empty. Nothing to transmit"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `RXF` reader - FIFO is full. Can't receive anything else"] +pub type RXF_R = crate::BitReader; +#[doc = "Field `ERR` reader - Error: No ack"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Error: No ack"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +#[doc = "Field `CLKT` reader - Clock stretch timeout"] +pub type CLKT_R = crate::BitReader; +#[doc = "Field `CLKT` writer - Clock stretch timeout"] +pub type CLKT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer active"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO needs to be written"] + #[inline(always)] + pub fn txw(&self) -> TXW_R { + TXW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO needs to be read"] + #[inline(always)] + pub fn rxr(&self) -> RXR_R { + RXR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - FIFO has space for at least one byte"] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - FIFO contains at least one byte"] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - FIFO is empty. Nothing to transmit"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FIFO is full. Can't receive anything else"] + #[inline(always)] + pub fn rxf(&self) -> RXF_R { + RXF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Error: No ack"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Clock stretch timeout"] + #[inline(always)] + pub fn clkt(&self) -> CLKT_R { + CLKT_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<1> { + DONE_W::new(self) + } + #[doc = "Bit 8 - Error: No ack"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<8> { + ERR_W::new(self) + } + #[doc = "Bit 9 - Clock stretch timeout"] + #[inline(always)] + #[must_use] + pub fn clkt(&mut self) -> CLKT_W<9> { + CLKT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s](index.html) module"] +pub struct S_SPEC; +impl crate::RegisterSpec for S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s::R](R) reader structure"] +impl crate::Readable for S_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s::W](W) writer structure"] +impl crate::Writable for S_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0302; +} +#[doc = "`reset()` method sets S to value 0x50"] +impl crate::Resettable for S_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/crates/bcm2711-lpa/src/cm_pcm.rs b/crates/bcm2711-lpa/src/cm_pcm.rs new file mode 100644 index 0000000..0c60fcd --- /dev/null +++ b/crates/bcm2711-lpa/src/cm_pcm.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control / Status"] + pub cs: CS, + #[doc = "0x04 - Clock divisor"] + pub div: DIV, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control / Status"] +pub mod cs; +#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +pub type DIV = crate::Reg; +#[doc = "Clock divisor"] +pub mod div; diff --git a/crates/bcm2711-lpa/src/cm_pcm/cs.rs b/crates/bcm2711-lpa/src/cm_pcm/cs.rs new file mode 100644 index 0000000..67ddd60 --- /dev/null +++ b/crates/bcm2711-lpa/src/cm_pcm/cs.rs @@ -0,0 +1,288 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Clock source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "1: `1`"] + XOSC = 1, + #[doc = "2: `10`"] + TEST0 = 2, + #[doc = "3: `11`"] + TEST1 = 3, + #[doc = "4: `100`"] + PLLA = 4, + #[doc = "5: `101`"] + PLLB = 5, + #[doc = "6: `110`"] + PLLC = 6, + #[doc = "7: `111`"] + HDMI = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(SRC_A::XOSC), + 2 => Some(SRC_A::TEST0), + 3 => Some(SRC_A::TEST1), + 4 => Some(SRC_A::PLLA), + 5 => Some(SRC_A::PLLB), + 6 => Some(SRC_A::PLLC), + 7 => Some(SRC_A::HDMI), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + *self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `TEST0`"] + #[inline(always)] + pub fn is_test0(&self) -> bool { + *self == SRC_A::TEST0 + } + #[doc = "Checks if the value of the field is `TEST1`"] + #[inline(always)] + pub fn is_test1(&self) -> bool { + *self == SRC_A::TEST1 + } + #[doc = "Checks if the value of the field is `PLLA`"] + #[inline(always)] + pub fn is_plla(&self) -> bool { + *self == SRC_A::PLLA + } + #[doc = "Checks if the value of the field is `PLLB`"] + #[inline(always)] + pub fn is_pllb(&self) -> bool { + *self == SRC_A::PLLB + } + #[doc = "Checks if the value of the field is `PLLC`"] + #[inline(always)] + pub fn is_pllc(&self) -> bool { + *self == SRC_A::PLLC + } + #[doc = "Checks if the value of the field is `HDMI`"] + #[inline(always)] + pub fn is_hdmi(&self) -> bool { + *self == SRC_A::HDMI + } +} +#[doc = "Field `SRC` writer - Clock source"] +pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, SRC_A, 4, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "`1`"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "`10`"] + #[inline(always)] + pub fn test0(self) -> &'a mut W { + self.variant(SRC_A::TEST0) + } + #[doc = "`11`"] + #[inline(always)] + pub fn test1(self) -> &'a mut W { + self.variant(SRC_A::TEST1) + } + #[doc = "`100`"] + #[inline(always)] + pub fn plla(self) -> &'a mut W { + self.variant(SRC_A::PLLA) + } + #[doc = "`101`"] + #[inline(always)] + pub fn pllb(self) -> &'a mut W { + self.variant(SRC_A::PLLB) + } + #[doc = "`110`"] + #[inline(always)] + pub fn pllc(self) -> &'a mut W { + self.variant(SRC_A::PLLC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn hdmi(self) -> &'a mut W { + self.variant(SRC_A::HDMI) + } +} +#[doc = "Field `ENAB` reader - Enable the clock generator. (Switch SRC first.)"] +pub type ENAB_R = crate::BitReader; +#[doc = "Field `ENAB` writer - Enable the clock generator. (Switch SRC first.)"] +pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `KILL` reader - Stop and reset the generator"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Stop and reset the generator"] +pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `BUSY` reader - Indicates the clock generator is running"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `FLIP` reader - Generate an edge on output. (For testing)"] +pub type FLIP_R = crate::BitReader; +#[doc = "Field `FLIP` writer - Generate an edge on output. (For testing)"] +pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `MASH` reader - MASH control, stage count"] +pub type MASH_R = crate::FieldReader; +#[doc = "Field `MASH` writer - MASH control, stage count"] +pub type MASH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:3 - Clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] + #[inline(always)] + pub fn enab(&self) -> ENAB_R { + ENAB_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stop and reset the generator"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Indicates the clock generator is running"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Generate an edge on output. (For testing)"] + #[inline(always)] + pub fn flip(&self) -> FLIP_R { + FLIP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:10 - MASH control, stage count"] + #[inline(always)] + pub fn mash(&self) -> MASH_R { + MASH_R::new(((self.bits >> 9) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Clock source"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] + #[inline(always)] + #[must_use] + pub fn enab(&mut self) -> ENAB_W<4> { + ENAB_W::new(self) + } + #[doc = "Bit 5 - Stop and reset the generator"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W<5> { + KILL_W::new(self) + } + #[doc = "Bit 8 - Generate an edge on output. (For testing)"] + #[inline(always)] + #[must_use] + pub fn flip(&mut self) -> FLIP_W<8> { + FLIP_W::new(self) + } + #[doc = "Bits 9:10 - MASH control, stage count"] + #[inline(always)] + #[must_use] + pub fn mash(&mut self) -> MASH_W<9> { + MASH_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/cm_pcm/div.rs b/crates/bcm2711-lpa/src/cm_pcm/div.rs new file mode 100644 index 0000000..a0c99f8 --- /dev/null +++ b/crates/bcm2711-lpa/src/cm_pcm/div.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVF` reader - Fractional part of divisor"] +pub type DIVF_R = crate::FieldReader; +#[doc = "Field `DIVF` writer - Fractional part of divisor"] +pub type DIVF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +#[doc = "Field `DIVI` reader - Integer part of divisor"] +pub type DIVI_R = crate::FieldReader; +#[doc = "Field `DIVI` writer - Integer part of divisor"] +pub type DIVI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:11 - Fractional part of divisor"] + #[inline(always)] + pub fn divf(&self) -> DIVF_R { + DIVF_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - Integer part of divisor"] + #[inline(always)] + pub fn divi(&self) -> DIVI_R { + DIVI_R::new(((self.bits >> 12) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Fractional part of divisor"] + #[inline(always)] + #[must_use] + pub fn divf(&mut self) -> DIVF_W<0> { + DIVF_W::new(self) + } + #[doc = "Bits 12:23 - Integer part of divisor"] + #[inline(always)] + #[must_use] + pub fn divi(&mut self) -> DIVI_W<12> { + DIVI_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [div::R](R) reader structure"] +impl crate::Readable for DIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIV to value 0"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc.rs b/crates/bcm2711-lpa/src/emmc.rs new file mode 100644 index 0000000..e4be2cf --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc.rs @@ -0,0 +1,165 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Argument for ACMD23 command"] + pub arg2: ARG2, + #[doc = "0x04 - Numer and size in bytes for data block to be transferred"] + pub blksizecnt: BLKSIZECNT, + #[doc = "0x08 - Argument for everything but ACMD23"] + pub arg1: ARG1, + #[doc = "0x0c - Issue commands to the card"] + pub cmdtm: CMDTM, + #[doc = "0x10 - Status bits of the response"] + pub resp0: RESP0, + #[doc = "0x14 - Bits 63:32 of CMD2 and CMD10 responses"] + pub resp1: RESP1, + #[doc = "0x18 - Bits 95:64 of CMD2 and CMD10 responses"] + pub resp2: RESP2, + #[doc = "0x1c - Bits 127:96 of CMD2 and CMD10 responses"] + pub resp3: RESP3, + #[doc = "0x20 - Data to/from the card"] + pub data: DATA, + #[doc = "0x24 - Status info for debugging"] + pub status: STATUS, + #[doc = "0x28 - Control"] + pub control0: CONTROL0, + #[doc = "0x2c - Configure"] + pub control1: CONTROL1, + #[doc = "0x30 - Interrupt flags"] + pub interrupt: INTERRUPT, + #[doc = "0x34 - Mask interrupts that change in INTERRUPT"] + pub irpt_mask: IRPT_MASK, + #[doc = "0x38 - Enable interrupt to core"] + pub irpt_en: IRPT_EN, + #[doc = "0x3c - Control 2"] + pub control2: CONTROL2, + _reserved16: [u8; 0x10], + #[doc = "0x50 - Force an interrupt"] + pub force_irpt: FORCE_IRPT, + _reserved17: [u8; 0x1c], + #[doc = "0x70 - Number of SD clock cycles to wait for boot"] + pub boot_timeout: BOOT_TIMEOUT, + #[doc = "0x74 - What submodules are accessed by the debug bus"] + pub dbg_sel: DBG_SEL, + _reserved19: [u8; 0x08], + #[doc = "0x80 - Fine tune DMA request generation"] + pub exrdfifo_cfg: EXRDFIFO_CFG, + #[doc = "0x84 - Enable the extension data register"] + pub exrdfifo_en: EXRDFIFO_EN, + #[doc = "0x88 - Sample clock delay step duration"] + pub tune_step: TUNE_STEP, + #[doc = "0x8c - Sample clock delay step count for SDR"] + pub tune_steps_std: TUNE_STEPS_STD, + #[doc = "0x90 - Sample clock delay step count for DDR"] + pub tune_steps_ddr: TUNE_STEPS_DDR, + _reserved24: [u8; 0x5c], + #[doc = "0xf0 - Interrupts in SPI mode depend on CS"] + pub spi_int_spt: SPI_INT_SPT, + _reserved25: [u8; 0x08], + #[doc = "0xfc - Version information and slot interrupt status"] + pub slotisr_ver: SLOTISR_VER, +} +#[doc = "ARG2 (rw) register accessor: an alias for `Reg`"] +pub type ARG2 = crate::Reg; +#[doc = "Argument for ACMD23 command"] +pub mod arg2; +#[doc = "BLKSIZECNT (rw) register accessor: an alias for `Reg`"] +pub type BLKSIZECNT = crate::Reg; +#[doc = "Numer and size in bytes for data block to be transferred"] +pub mod blksizecnt; +#[doc = "ARG1 (rw) register accessor: an alias for `Reg`"] +pub type ARG1 = crate::Reg; +#[doc = "Argument for everything but ACMD23"] +pub mod arg1; +#[doc = "CMDTM (rw) register accessor: an alias for `Reg`"] +pub type CMDTM = crate::Reg; +#[doc = "Issue commands to the card"] +pub mod cmdtm; +#[doc = "RESP0 (rw) register accessor: an alias for `Reg`"] +pub type RESP0 = crate::Reg; +#[doc = "Status bits of the response"] +pub mod resp0; +#[doc = "RESP1 (rw) register accessor: an alias for `Reg`"] +pub type RESP1 = crate::Reg; +#[doc = "Bits 63:32 of CMD2 and CMD10 responses"] +pub mod resp1; +#[doc = "RESP2 (rw) register accessor: an alias for `Reg`"] +pub type RESP2 = crate::Reg; +#[doc = "Bits 95:64 of CMD2 and CMD10 responses"] +pub mod resp2; +#[doc = "RESP3 (rw) register accessor: an alias for `Reg`"] +pub type RESP3 = crate::Reg; +#[doc = "Bits 127:96 of CMD2 and CMD10 responses"] +pub mod resp3; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data to/from the card"] +pub mod data; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status info for debugging"] +pub mod status; +#[doc = "CONTROL0 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL0 = crate::Reg; +#[doc = "Control"] +pub mod control0; +#[doc = "CONTROL1 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL1 = crate::Reg; +#[doc = "Configure"] +pub mod control1; +#[doc = "INTERRUPT (rw) register accessor: an alias for `Reg`"] +pub type INTERRUPT = crate::Reg; +#[doc = "Interrupt flags"] +pub mod interrupt; +#[doc = "IRPT_MASK (rw) register accessor: an alias for `Reg`"] +pub type IRPT_MASK = crate::Reg; +#[doc = "Mask interrupts that change in INTERRUPT"] +pub mod irpt_mask; +#[doc = "IRPT_EN (rw) register accessor: an alias for `Reg`"] +pub type IRPT_EN = crate::Reg; +#[doc = "Enable interrupt to core"] +pub mod irpt_en; +#[doc = "CONTROL2 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL2 = crate::Reg; +#[doc = "Control 2"] +pub mod control2; +#[doc = "FORCE_IRPT (rw) register accessor: an alias for `Reg`"] +pub type FORCE_IRPT = crate::Reg; +#[doc = "Force an interrupt"] +pub mod force_irpt; +#[doc = "BOOT_TIMEOUT (rw) register accessor: an alias for `Reg`"] +pub type BOOT_TIMEOUT = crate::Reg; +#[doc = "Number of SD clock cycles to wait for boot"] +pub mod boot_timeout; +#[doc = "DBG_SEL (rw) register accessor: an alias for `Reg`"] +pub type DBG_SEL = crate::Reg; +#[doc = "What submodules are accessed by the debug bus"] +pub mod dbg_sel; +#[doc = "EXRDFIFO_CFG (rw) register accessor: an alias for `Reg`"] +pub type EXRDFIFO_CFG = crate::Reg; +#[doc = "Fine tune DMA request generation"] +pub mod exrdfifo_cfg; +#[doc = "EXRDFIFO_EN (rw) register accessor: an alias for `Reg`"] +pub type EXRDFIFO_EN = crate::Reg; +#[doc = "Enable the extension data register"] +pub mod exrdfifo_en; +#[doc = "TUNE_STEP (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEP = crate::Reg; +#[doc = "Sample clock delay step duration"] +pub mod tune_step; +#[doc = "TUNE_STEPS_STD (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEPS_STD = crate::Reg; +#[doc = "Sample clock delay step count for SDR"] +pub mod tune_steps_std; +#[doc = "TUNE_STEPS_DDR (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEPS_DDR = crate::Reg; +#[doc = "Sample clock delay step count for DDR"] +pub mod tune_steps_ddr; +#[doc = "SPI_INT_SPT (rw) register accessor: an alias for `Reg`"] +pub type SPI_INT_SPT = crate::Reg; +#[doc = "Interrupts in SPI mode depend on CS"] +pub mod spi_int_spt; +#[doc = "SLOTISR_VER (rw) register accessor: an alias for `Reg`"] +pub type SLOTISR_VER = crate::Reg; +#[doc = "Version information and slot interrupt status"] +pub mod slotisr_ver; diff --git a/crates/bcm2711-lpa/src/emmc/arg1.rs b/crates/bcm2711-lpa/src/emmc/arg1.rs new file mode 100644 index 0000000..4a25300 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/arg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ARG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ARG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Argument for everything but ACMD23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg1](index.html) module"] +pub struct ARG1_SPEC; +impl crate::RegisterSpec for ARG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [arg1::R](R) reader structure"] +impl crate::Readable for ARG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [arg1::W](W) writer structure"] +impl crate::Writable for ARG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARG1 to value 0"] +impl crate::Resettable for ARG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/arg2.rs b/crates/bcm2711-lpa/src/emmc/arg2.rs new file mode 100644 index 0000000..b295b35 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/arg2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ARG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ARG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Argument for ACMD23 command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg2](index.html) module"] +pub struct ARG2_SPEC; +impl crate::RegisterSpec for ARG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [arg2::R](R) reader structure"] +impl crate::Readable for ARG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [arg2::W](W) writer structure"] +impl crate::Writable for ARG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARG2 to value 0"] +impl crate::Resettable for ARG2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/blksizecnt.rs b/crates/bcm2711-lpa/src/emmc/blksizecnt.rs new file mode 100644 index 0000000..f3dabd8 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/blksizecnt.rs @@ -0,0 +1,95 @@ +#[doc = "Register `BLKSIZECNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BLKSIZECNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BLKSIZE` reader - Block size in bytes"] +pub type BLKSIZE_R = crate::FieldReader; +#[doc = "Field `BLKSIZE` writer - Block size in bytes"] +pub type BLKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 10, O>; +#[doc = "Field `BLKCNT` reader - Number of blocks to be transferred"] +pub type BLKCNT_R = crate::FieldReader; +#[doc = "Field `BLKCNT` writer - Number of blocks to be transferred"] +pub type BLKCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:9 - Block size in bytes"] + #[inline(always)] + pub fn blksize(&self) -> BLKSIZE_R { + BLKSIZE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:31 - Number of blocks to be transferred"] + #[inline(always)] + pub fn blkcnt(&self) -> BLKCNT_R { + BLKCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Block size in bytes"] + #[inline(always)] + #[must_use] + pub fn blksize(&mut self) -> BLKSIZE_W<0> { + BLKSIZE_W::new(self) + } + #[doc = "Bits 16:31 - Number of blocks to be transferred"] + #[inline(always)] + #[must_use] + pub fn blkcnt(&mut self) -> BLKCNT_W<16> { + BLKCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Numer and size in bytes for data block to be transferred\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blksizecnt](index.html) module"] +pub struct BLKSIZECNT_SPEC; +impl crate::RegisterSpec for BLKSIZECNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [blksizecnt::R](R) reader structure"] +impl crate::Readable for BLKSIZECNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [blksizecnt::W](W) writer structure"] +impl crate::Writable for BLKSIZECNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLKSIZECNT to value 0"] +impl crate::Resettable for BLKSIZECNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/boot_timeout.rs b/crates/bcm2711-lpa/src/emmc/boot_timeout.rs new file mode 100644 index 0000000..5a9943a --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/boot_timeout.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BOOT_TIMEOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOOT_TIMEOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Number of SD clock cycles to wait for boot\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_timeout](index.html) module"] +pub struct BOOT_TIMEOUT_SPEC; +impl crate::RegisterSpec for BOOT_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [boot_timeout::R](R) reader structure"] +impl crate::Readable for BOOT_TIMEOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [boot_timeout::W](W) writer structure"] +impl crate::Writable for BOOT_TIMEOUT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOOT_TIMEOUT to value 0"] +impl crate::Resettable for BOOT_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/cmdtm.rs b/crates/bcm2711-lpa/src/emmc/cmdtm.rs new file mode 100644 index 0000000..e30a873 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/cmdtm.rs @@ -0,0 +1,520 @@ +#[doc = "Register `CMDTM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMDTM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TM_BLKCNT_EN` reader - Enable block counter"] +pub type TM_BLKCNT_EN_R = crate::BitReader; +#[doc = "Field `TM_BLKCNT_EN` writer - Enable block counter"] +pub type TM_BLKCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `TM_AUTO_CMD_EN` reader - Command after completion"] +pub type TM_AUTO_CMD_EN_R = crate::FieldReader; +#[doc = "Command after completion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TM_AUTO_CMD_EN_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + CMD12 = 1, + #[doc = "2: `10`"] + CMD23 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TM_AUTO_CMD_EN_A) -> Self { + variant as _ + } +} +impl TM_AUTO_CMD_EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TM_AUTO_CMD_EN_A::NONE), + 1 => Some(TM_AUTO_CMD_EN_A::CMD12), + 2 => Some(TM_AUTO_CMD_EN_A::CMD23), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::NONE + } + #[doc = "Checks if the value of the field is `CMD12`"] + #[inline(always)] + pub fn is_cmd12(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::CMD12 + } + #[doc = "Checks if the value of the field is `CMD23`"] + #[inline(always)] + pub fn is_cmd23(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::CMD23 + } +} +#[doc = "Field `TM_AUTO_CMD_EN` writer - Command after completion"] +pub type TM_AUTO_CMD_EN_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, TM_AUTO_CMD_EN_A, 2, O>; +impl<'a, const O: u8> TM_AUTO_CMD_EN_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::NONE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn cmd12(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::CMD12) + } + #[doc = "`10`"] + #[inline(always)] + pub fn cmd23(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::CMD23) + } +} +#[doc = "Field `TM_DAT_DIR` reader - Direction of data transfer"] +pub type TM_DAT_DIR_R = crate::BitReader; +#[doc = "Direction of data transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TM_DAT_DIR_A { + #[doc = "0: `0`"] + HOST_TO_CARD = 0, + #[doc = "1: `1`"] + CARD_TO_HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TM_DAT_DIR_A) -> Self { + variant as u8 != 0 + } +} +impl TM_DAT_DIR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TM_DAT_DIR_A { + match self.bits { + false => TM_DAT_DIR_A::HOST_TO_CARD, + true => TM_DAT_DIR_A::CARD_TO_HOST, + } + } + #[doc = "Checks if the value of the field is `HOST_TO_CARD`"] + #[inline(always)] + pub fn is_host_to_card(&self) -> bool { + *self == TM_DAT_DIR_A::HOST_TO_CARD + } + #[doc = "Checks if the value of the field is `CARD_TO_HOST`"] + #[inline(always)] + pub fn is_card_to_host(&self) -> bool { + *self == TM_DAT_DIR_A::CARD_TO_HOST + } +} +#[doc = "Field `TM_DAT_DIR` writer - Direction of data transfer"] +pub type TM_DAT_DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, TM_DAT_DIR_A, O>; +impl<'a, const O: u8> TM_DAT_DIR_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn host_to_card(self) -> &'a mut W { + self.variant(TM_DAT_DIR_A::HOST_TO_CARD) + } + #[doc = "`1`"] + #[inline(always)] + pub fn card_to_host(self) -> &'a mut W { + self.variant(TM_DAT_DIR_A::CARD_TO_HOST) + } +} +#[doc = "Field `TM_MULTI_BLOCK` reader - Type of data transfer"] +pub type TM_MULTI_BLOCK_R = crate::BitReader; +#[doc = "Type of data transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TM_MULTI_BLOCK_A { + #[doc = "0: `0`"] + SINGLE = 0, + #[doc = "1: `1`"] + MULTIPLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TM_MULTI_BLOCK_A) -> Self { + variant as u8 != 0 + } +} +impl TM_MULTI_BLOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TM_MULTI_BLOCK_A { + match self.bits { + false => TM_MULTI_BLOCK_A::SINGLE, + true => TM_MULTI_BLOCK_A::MULTIPLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == TM_MULTI_BLOCK_A::SINGLE + } + #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[inline(always)] + pub fn is_multiple(&self) -> bool { + *self == TM_MULTI_BLOCK_A::MULTIPLE + } +} +#[doc = "Field `TM_MULTI_BLOCK` writer - Type of data transfer"] +pub type TM_MULTI_BLOCK_W<'a, const O: u8> = + crate::BitWriter<'a, u32, CMDTM_SPEC, TM_MULTI_BLOCK_A, O>; +impl<'a, const O: u8> TM_MULTI_BLOCK_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(TM_MULTI_BLOCK_A::SINGLE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn multiple(self) -> &'a mut W { + self.variant(TM_MULTI_BLOCK_A::MULTIPLE) + } +} +#[doc = "Field `CMD_RSPNS_TYPE` reader - Type of expected response"] +pub type CMD_RSPNS_TYPE_R = crate::FieldReader; +#[doc = "Type of expected response\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RESPONSE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _136BITS = 1, + #[doc = "2: `10`"] + _48BITS = 2, + #[doc = "3: `11`"] + _48BITS_USING_BUSY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESPONSE_A) -> Self { + variant as _ + } +} +impl CMD_RSPNS_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESPONSE_A { + match self.bits { + 0 => RESPONSE_A::NONE, + 1 => RESPONSE_A::_136BITS, + 2 => RESPONSE_A::_48BITS, + 3 => RESPONSE_A::_48BITS_USING_BUSY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == RESPONSE_A::NONE + } + #[doc = "Checks if the value of the field is `_136BITS`"] + #[inline(always)] + pub fn is_136bits(&self) -> bool { + *self == RESPONSE_A::_136BITS + } + #[doc = "Checks if the value of the field is `_48BITS`"] + #[inline(always)] + pub fn is_48bits(&self) -> bool { + *self == RESPONSE_A::_48BITS + } + #[doc = "Checks if the value of the field is `_48BITS_USING_BUSY`"] + #[inline(always)] + pub fn is_48bits_using_busy(&self) -> bool { + *self == RESPONSE_A::_48BITS_USING_BUSY + } +} +#[doc = "Field `CMD_RSPNS_TYPE` writer - Type of expected response"] +pub type CMD_RSPNS_TYPE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, RESPONSE_A, 2, O>; +impl<'a, const O: u8> CMD_RSPNS_TYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESPONSE_A::NONE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _136bits(self) -> &'a mut W { + self.variant(RESPONSE_A::_136BITS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _48bits(self) -> &'a mut W { + self.variant(RESPONSE_A::_48BITS) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _48bits_using_busy(self) -> &'a mut W { + self.variant(RESPONSE_A::_48BITS_USING_BUSY) + } +} +#[doc = "Field `CMD_CRCCHK_EN` reader - Check the responses CRC"] +pub type CMD_CRCCHK_EN_R = crate::BitReader; +#[doc = "Field `CMD_CRCCHK_EN` writer - Check the responses CRC"] +pub type CMD_CRCCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_IXCHK_EN` reader - Check that the response has the same command index"] +pub type CMD_IXCHK_EN_R = crate::BitReader; +#[doc = "Field `CMD_IXCHK_EN` writer - Check that the response has the same command index"] +pub type CMD_IXCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_ISDATA` reader - Command involves data"] +pub type CMD_ISDATA_R = crate::BitReader; +#[doc = "Field `CMD_ISDATA` writer - Command involves data"] +pub type CMD_ISDATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_TYPE` reader - Type of command to be issued"] +pub type CMD_TYPE_R = crate::FieldReader; +#[doc = "Type of command to be issued\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMD_TYPE_A { + #[doc = "0: `0`"] + NORMAL = 0, + #[doc = "1: `1`"] + SUSPEND = 1, + #[doc = "2: `10`"] + RESUME = 2, + #[doc = "3: `11`"] + ABORT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_TYPE_A) -> Self { + variant as _ + } +} +impl CMD_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMD_TYPE_A { + match self.bits { + 0 => CMD_TYPE_A::NORMAL, + 1 => CMD_TYPE_A::SUSPEND, + 2 => CMD_TYPE_A::RESUME, + 3 => CMD_TYPE_A::ABORT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NORMAL`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CMD_TYPE_A::NORMAL + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == CMD_TYPE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + *self == CMD_TYPE_A::RESUME + } + #[doc = "Checks if the value of the field is `ABORT`"] + #[inline(always)] + pub fn is_abort(&self) -> bool { + *self == CMD_TYPE_A::ABORT + } +} +#[doc = "Field `CMD_TYPE` writer - Type of command to be issued"] +pub type CMD_TYPE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, CMD_TYPE_A, 2, O>; +impl<'a, const O: u8> CMD_TYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn normal(self) -> &'a mut W { + self.variant(CMD_TYPE_A::NORMAL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_TYPE_A::SUSPEND) + } + #[doc = "`10`"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_TYPE_A::RESUME) + } + #[doc = "`11`"] + #[inline(always)] + pub fn abort(self) -> &'a mut W { + self.variant(CMD_TYPE_A::ABORT) + } +} +#[doc = "Field `CMD_INDEX` reader - Command index to be issued"] +pub type CMD_INDEX_R = crate::FieldReader; +#[doc = "Field `CMD_INDEX` writer - Command index to be issued"] +pub type CMD_INDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bit 1 - Enable block counter"] + #[inline(always)] + pub fn tm_blkcnt_en(&self) -> TM_BLKCNT_EN_R { + TM_BLKCNT_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Command after completion"] + #[inline(always)] + pub fn tm_auto_cmd_en(&self) -> TM_AUTO_CMD_EN_R { + TM_AUTO_CMD_EN_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Direction of data transfer"] + #[inline(always)] + pub fn tm_dat_dir(&self) -> TM_DAT_DIR_R { + TM_DAT_DIR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Type of data transfer"] + #[inline(always)] + pub fn tm_multi_block(&self) -> TM_MULTI_BLOCK_R { + TM_MULTI_BLOCK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 16:17 - Type of expected response"] + #[inline(always)] + pub fn cmd_rspns_type(&self) -> CMD_RSPNS_TYPE_R { + CMD_RSPNS_TYPE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 19 - Check the responses CRC"] + #[inline(always)] + pub fn cmd_crcchk_en(&self) -> CMD_CRCCHK_EN_R { + CMD_CRCCHK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Check that the response has the same command index"] + #[inline(always)] + pub fn cmd_ixchk_en(&self) -> CMD_IXCHK_EN_R { + CMD_IXCHK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Command involves data"] + #[inline(always)] + pub fn cmd_isdata(&self) -> CMD_ISDATA_R { + CMD_ISDATA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:23 - Type of command to be issued"] + #[inline(always)] + pub fn cmd_type(&self) -> CMD_TYPE_R { + CMD_TYPE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:29 - Command index to be issued"] + #[inline(always)] + pub fn cmd_index(&self) -> CMD_INDEX_R { + CMD_INDEX_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable block counter"] + #[inline(always)] + #[must_use] + pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W<1> { + TM_BLKCNT_EN_W::new(self) + } + #[doc = "Bits 2:3 - Command after completion"] + #[inline(always)] + #[must_use] + pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W<2> { + TM_AUTO_CMD_EN_W::new(self) + } + #[doc = "Bit 4 - Direction of data transfer"] + #[inline(always)] + #[must_use] + pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W<4> { + TM_DAT_DIR_W::new(self) + } + #[doc = "Bit 5 - Type of data transfer"] + #[inline(always)] + #[must_use] + pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W<5> { + TM_MULTI_BLOCK_W::new(self) + } + #[doc = "Bits 16:17 - Type of expected response"] + #[inline(always)] + #[must_use] + pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W<16> { + CMD_RSPNS_TYPE_W::new(self) + } + #[doc = "Bit 19 - Check the responses CRC"] + #[inline(always)] + #[must_use] + pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W<19> { + CMD_CRCCHK_EN_W::new(self) + } + #[doc = "Bit 20 - Check that the response has the same command index"] + #[inline(always)] + #[must_use] + pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W<20> { + CMD_IXCHK_EN_W::new(self) + } + #[doc = "Bit 21 - Command involves data"] + #[inline(always)] + #[must_use] + pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W<21> { + CMD_ISDATA_W::new(self) + } + #[doc = "Bits 22:23 - Type of command to be issued"] + #[inline(always)] + #[must_use] + pub fn cmd_type(&mut self) -> CMD_TYPE_W<22> { + CMD_TYPE_W::new(self) + } + #[doc = "Bits 24:29 - Command index to be issued"] + #[inline(always)] + #[must_use] + pub fn cmd_index(&mut self) -> CMD_INDEX_W<24> { + CMD_INDEX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Issue commands to the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdtm](index.html) module"] +pub struct CMDTM_SPEC; +impl crate::RegisterSpec for CMDTM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cmdtm::R](R) reader structure"] +impl crate::Readable for CMDTM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmdtm::W](W) writer structure"] +impl crate::Writable for CMDTM_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMDTM to value 0"] +impl crate::Resettable for CMDTM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/control0.rs b/crates/bcm2711-lpa/src/emmc/control0.rs new file mode 100644 index 0000000..948b94b --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/control0.rs @@ -0,0 +1,215 @@ +#[doc = "Register `CONTROL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HCTL_DWIDTH` reader - Use 4 data lines"] +pub type HCTL_DWIDTH_R = crate::BitReader; +#[doc = "Field `HCTL_DWIDTH` writer - Use 4 data lines"] +pub type HCTL_DWIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `HCTL_HS_EN` reader - Enable high speed mode"] +pub type HCTL_HS_EN_R = crate::BitReader; +#[doc = "Field `HCTL_HS_EN` writer - Enable high speed mode"] +pub type HCTL_HS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `HCTL_8BIT` reader - Use 8 data lines"] +pub type HCTL_8BIT_R = crate::BitReader; +#[doc = "Field `HCTL_8BIT` writer - Use 8 data lines"] +pub type HCTL_8BIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_STOP` reader - Stop the current transaction at the next block gap"] +pub type GAP_STOP_R = crate::BitReader; +#[doc = "Field `GAP_STOP` writer - Stop the current transaction at the next block gap"] +pub type GAP_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_RESTART` reader - Restart a transaction stopped by GAP_STOP"] +pub type GAP_RESTART_R = crate::BitReader; +#[doc = "Field `GAP_RESTART` writer - Restart a transaction stopped by GAP_STOP"] +pub type GAP_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `READWAIT_EN` reader - Use DAT2 read/wait protocol"] +pub type READWAIT_EN_R = crate::BitReader; +#[doc = "Field `READWAIT_EN` writer - Use DAT2 read/wait protocol"] +pub type READWAIT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_IEN` reader - Enable interrupt on block gap"] +pub type GAP_IEN_R = crate::BitReader; +#[doc = "Field `GAP_IEN` writer - Enable interrupt on block gap"] +pub type GAP_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `SPI_MODE` reader - Enable SPI mode"] +pub type SPI_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MODE` writer - Enable SPI mode"] +pub type SPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `BOOT_EN` reader - Boot mode enabled"] +pub type BOOT_EN_R = crate::BitReader; +#[doc = "Field `BOOT_EN` writer - Boot mode enabled"] +pub type BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `ALT_BOOT_EN` reader - Enable alternate boot mode"] +pub type ALT_BOOT_EN_R = crate::BitReader; +#[doc = "Field `ALT_BOOT_EN` writer - Enable alternate boot mode"] +pub type ALT_BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Use 4 data lines"] + #[inline(always)] + pub fn hctl_dwidth(&self) -> HCTL_DWIDTH_R { + HCTL_DWIDTH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable high speed mode"] + #[inline(always)] + pub fn hctl_hs_en(&self) -> HCTL_HS_EN_R { + HCTL_HS_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Use 8 data lines"] + #[inline(always)] + pub fn hctl_8bit(&self) -> HCTL_8BIT_R { + HCTL_8BIT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - Stop the current transaction at the next block gap"] + #[inline(always)] + pub fn gap_stop(&self) -> GAP_STOP_R { + GAP_STOP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] + #[inline(always)] + pub fn gap_restart(&self) -> GAP_RESTART_R { + GAP_RESTART_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Use DAT2 read/wait protocol"] + #[inline(always)] + pub fn readwait_en(&self) -> READWAIT_EN_R { + READWAIT_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable interrupt on block gap"] + #[inline(always)] + pub fn gap_ien(&self) -> GAP_IEN_R { + GAP_IEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable SPI mode"] + #[inline(always)] + pub fn spi_mode(&self) -> SPI_MODE_R { + SPI_MODE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Boot mode enabled"] + #[inline(always)] + pub fn boot_en(&self) -> BOOT_EN_R { + BOOT_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enable alternate boot mode"] + #[inline(always)] + pub fn alt_boot_en(&self) -> ALT_BOOT_EN_R { + ALT_BOOT_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Use 4 data lines"] + #[inline(always)] + #[must_use] + pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W<1> { + HCTL_DWIDTH_W::new(self) + } + #[doc = "Bit 2 - Enable high speed mode"] + #[inline(always)] + #[must_use] + pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W<2> { + HCTL_HS_EN_W::new(self) + } + #[doc = "Bit 5 - Use 8 data lines"] + #[inline(always)] + #[must_use] + pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W<5> { + HCTL_8BIT_W::new(self) + } + #[doc = "Bit 16 - Stop the current transaction at the next block gap"] + #[inline(always)] + #[must_use] + pub fn gap_stop(&mut self) -> GAP_STOP_W<16> { + GAP_STOP_W::new(self) + } + #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] + #[inline(always)] + #[must_use] + pub fn gap_restart(&mut self) -> GAP_RESTART_W<17> { + GAP_RESTART_W::new(self) + } + #[doc = "Bit 18 - Use DAT2 read/wait protocol"] + #[inline(always)] + #[must_use] + pub fn readwait_en(&mut self) -> READWAIT_EN_W<18> { + READWAIT_EN_W::new(self) + } + #[doc = "Bit 19 - Enable interrupt on block gap"] + #[inline(always)] + #[must_use] + pub fn gap_ien(&mut self) -> GAP_IEN_W<19> { + GAP_IEN_W::new(self) + } + #[doc = "Bit 20 - Enable SPI mode"] + #[inline(always)] + #[must_use] + pub fn spi_mode(&mut self) -> SPI_MODE_W<20> { + SPI_MODE_W::new(self) + } + #[doc = "Bit 21 - Boot mode enabled"] + #[inline(always)] + #[must_use] + pub fn boot_en(&mut self) -> BOOT_EN_W<21> { + BOOT_EN_W::new(self) + } + #[doc = "Bit 22 - Enable alternate boot mode"] + #[inline(always)] + #[must_use] + pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W<22> { + ALT_BOOT_EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control0](index.html) module"] +pub struct CONTROL0_SPEC; +impl crate::RegisterSpec for CONTROL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control0::R](R) reader structure"] +impl crate::Readable for CONTROL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control0::W](W) writer structure"] +impl crate::Writable for CONTROL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL0 to value 0"] +impl crate::Resettable for CONTROL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/control1.rs b/crates/bcm2711-lpa/src/emmc/control1.rs new file mode 100644 index 0000000..1dc7cb3 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/control1.rs @@ -0,0 +1,253 @@ +#[doc = "Register `CONTROL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLK_INTLEN` reader - Enable internal clock"] +pub type CLK_INTLEN_R = crate::BitReader; +#[doc = "Field `CLK_INTLEN` writer - Enable internal clock"] +pub type CLK_INTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `CLK_STABLE` reader - SD Clock stable"] +pub type CLK_STABLE_R = crate::BitReader; +#[doc = "Field `CLK_EN` reader - SD Clock enable"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - SD Clock enable"] +pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `CLK_GENSEL` reader - Mode of clock generation"] +pub type CLK_GENSEL_R = crate::BitReader; +#[doc = "Mode of clock generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CLK_GENSEL_A { + #[doc = "0: `0`"] + DIVIDED = 0, + #[doc = "1: `1`"] + PROGRAMMABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLK_GENSEL_A) -> Self { + variant as u8 != 0 + } +} +impl CLK_GENSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLK_GENSEL_A { + match self.bits { + false => CLK_GENSEL_A::DIVIDED, + true => CLK_GENSEL_A::PROGRAMMABLE, + } + } + #[doc = "Checks if the value of the field is `DIVIDED`"] + #[inline(always)] + pub fn is_divided(&self) -> bool { + *self == CLK_GENSEL_A::DIVIDED + } + #[doc = "Checks if the value of the field is `PROGRAMMABLE`"] + #[inline(always)] + pub fn is_programmable(&self) -> bool { + *self == CLK_GENSEL_A::PROGRAMMABLE + } +} +#[doc = "Field `CLK_GENSEL` writer - Mode of clock generation"] +pub type CLK_GENSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, CLK_GENSEL_A, O>; +impl<'a, const O: u8> CLK_GENSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn divided(self) -> &'a mut W { + self.variant(CLK_GENSEL_A::DIVIDED) + } + #[doc = "`1`"] + #[inline(always)] + pub fn programmable(self) -> &'a mut W { + self.variant(CLK_GENSEL_A::PROGRAMMABLE) + } +} +#[doc = "Field `CLK_FREQ_MS2` reader - Clock base divider MSBs"] +pub type CLK_FREQ_MS2_R = crate::FieldReader; +#[doc = "Field `CLK_FREQ_MS2` writer - Clock base divider MSBs"] +pub type CLK_FREQ_MS2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 2, O>; +#[doc = "Field `CLK_FREQ8` reader - Clock base divider LSB"] +pub type CLK_FREQ8_R = crate::FieldReader; +#[doc = "Field `CLK_FREQ8` writer - Clock base divider LSB"] +pub type CLK_FREQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 8, O>; +#[doc = "Field `DATA_TOUNIT` reader - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] +pub type DATA_TOUNIT_R = crate::FieldReader; +#[doc = "Field `DATA_TOUNIT` writer - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] +pub type DATA_TOUNIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 4, O>; +#[doc = "Field `SRST_HC` reader - Reset the complete host circuit"] +pub type SRST_HC_R = crate::BitReader; +#[doc = "Field `SRST_HC` writer - Reset the complete host circuit"] +pub type SRST_HC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `SRST_CMD` reader - Reset the command handling circuit"] +pub type SRST_CMD_R = crate::BitReader; +#[doc = "Field `SRST_CMD` writer - Reset the command handling circuit"] +pub type SRST_CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `SRST_DATA` reader - Reset the data handling circuit"] +pub type SRST_DATA_R = crate::BitReader; +#[doc = "Field `SRST_DATA` writer - Reset the data handling circuit"] +pub type SRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable internal clock"] + #[inline(always)] + pub fn clk_intlen(&self) -> CLK_INTLEN_R { + CLK_INTLEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SD Clock stable"] + #[inline(always)] + pub fn clk_stable(&self) -> CLK_STABLE_R { + CLK_STABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SD Clock enable"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Mode of clock generation"] + #[inline(always)] + pub fn clk_gensel(&self) -> CLK_GENSEL_R { + CLK_GENSEL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Clock base divider MSBs"] + #[inline(always)] + pub fn clk_freq_ms2(&self) -> CLK_FREQ_MS2_R { + CLK_FREQ_MS2_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:15 - Clock base divider LSB"] + #[inline(always)] + pub fn clk_freq8(&self) -> CLK_FREQ8_R { + CLK_FREQ8_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] + #[inline(always)] + pub fn data_tounit(&self) -> DATA_TOUNIT_R { + DATA_TOUNIT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 24 - Reset the complete host circuit"] + #[inline(always)] + pub fn srst_hc(&self) -> SRST_HC_R { + SRST_HC_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reset the command handling circuit"] + #[inline(always)] + pub fn srst_cmd(&self) -> SRST_CMD_R { + SRST_CMD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reset the data handling circuit"] + #[inline(always)] + pub fn srst_data(&self) -> SRST_DATA_R { + SRST_DATA_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable internal clock"] + #[inline(always)] + #[must_use] + pub fn clk_intlen(&mut self) -> CLK_INTLEN_W<0> { + CLK_INTLEN_W::new(self) + } + #[doc = "Bit 2 - SD Clock enable"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W<2> { + CLK_EN_W::new(self) + } + #[doc = "Bit 5 - Mode of clock generation"] + #[inline(always)] + #[must_use] + pub fn clk_gensel(&mut self) -> CLK_GENSEL_W<5> { + CLK_GENSEL_W::new(self) + } + #[doc = "Bits 6:7 - Clock base divider MSBs"] + #[inline(always)] + #[must_use] + pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W<6> { + CLK_FREQ_MS2_W::new(self) + } + #[doc = "Bits 8:15 - Clock base divider LSB"] + #[inline(always)] + #[must_use] + pub fn clk_freq8(&mut self) -> CLK_FREQ8_W<8> { + CLK_FREQ8_W::new(self) + } + #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] + #[inline(always)] + #[must_use] + pub fn data_tounit(&mut self) -> DATA_TOUNIT_W<16> { + DATA_TOUNIT_W::new(self) + } + #[doc = "Bit 24 - Reset the complete host circuit"] + #[inline(always)] + #[must_use] + pub fn srst_hc(&mut self) -> SRST_HC_W<24> { + SRST_HC_W::new(self) + } + #[doc = "Bit 25 - Reset the command handling circuit"] + #[inline(always)] + #[must_use] + pub fn srst_cmd(&mut self) -> SRST_CMD_W<25> { + SRST_CMD_W::new(self) + } + #[doc = "Bit 26 - Reset the data handling circuit"] + #[inline(always)] + #[must_use] + pub fn srst_data(&mut self) -> SRST_DATA_W<26> { + SRST_DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configure\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control1](index.html) module"] +pub struct CONTROL1_SPEC; +impl crate::RegisterSpec for CONTROL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control1::R](R) reader structure"] +impl crate::Readable for CONTROL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control1::W](W) writer structure"] +impl crate::Writable for CONTROL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL1 to value 0"] +impl crate::Resettable for CONTROL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/control2.rs b/crates/bcm2711-lpa/src/emmc/control2.rs new file mode 100644 index 0000000..1bc9076 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/control2.rs @@ -0,0 +1,240 @@ +#[doc = "Register `CONTROL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ACNOX_ERR` reader - Auto command not executed due to an error"] +pub type ACNOX_ERR_R = crate::BitReader; +#[doc = "Field `ACTO_ERR` reader - Auto command timeout"] +pub type ACTO_ERR_R = crate::BitReader; +#[doc = "Field `ACCRC_ERR` reader - Command CRC error during auto command"] +pub type ACCRC_ERR_R = crate::BitReader; +#[doc = "Field `ACEND_ERR` reader - End bit is not 1 during auto command"] +pub type ACEND_ERR_R = crate::BitReader; +#[doc = "Field `ACBAD_ERR` reader - Command index error during auto command"] +pub type ACBAD_ERR_R = crate::BitReader; +#[doc = "Field `NOTC12_ERR` reader - Error during auto CMD12"] +pub type NOTC12_ERR_R = crate::BitReader; +#[doc = "Field `UHSMODE` reader - Select the speed of the SD card"] +pub type UHSMODE_R = crate::FieldReader; +#[doc = "Select the speed of the SD card\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum UHSMODE_A { + #[doc = "0: `0`"] + SDR12 = 0, + #[doc = "1: `1`"] + SDR25 = 1, + #[doc = "2: `10`"] + SDR50 = 2, + #[doc = "3: `11`"] + SDR104 = 3, + #[doc = "4: `100`"] + DDR50 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: UHSMODE_A) -> Self { + variant as _ + } +} +impl UHSMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(UHSMODE_A::SDR12), + 1 => Some(UHSMODE_A::SDR25), + 2 => Some(UHSMODE_A::SDR50), + 3 => Some(UHSMODE_A::SDR104), + 4 => Some(UHSMODE_A::DDR50), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SDR12`"] + #[inline(always)] + pub fn is_sdr12(&self) -> bool { + *self == UHSMODE_A::SDR12 + } + #[doc = "Checks if the value of the field is `SDR25`"] + #[inline(always)] + pub fn is_sdr25(&self) -> bool { + *self == UHSMODE_A::SDR25 + } + #[doc = "Checks if the value of the field is `SDR50`"] + #[inline(always)] + pub fn is_sdr50(&self) -> bool { + *self == UHSMODE_A::SDR50 + } + #[doc = "Checks if the value of the field is `SDR104`"] + #[inline(always)] + pub fn is_sdr104(&self) -> bool { + *self == UHSMODE_A::SDR104 + } + #[doc = "Checks if the value of the field is `DDR50`"] + #[inline(always)] + pub fn is_ddr50(&self) -> bool { + *self == UHSMODE_A::DDR50 + } +} +#[doc = "Field `UHSMODE` writer - Select the speed of the SD card"] +pub type UHSMODE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONTROL2_SPEC, u8, UHSMODE_A, 3, O>; +impl<'a, const O: u8> UHSMODE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn sdr12(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR12) + } + #[doc = "`1`"] + #[inline(always)] + pub fn sdr25(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR25) + } + #[doc = "`10`"] + #[inline(always)] + pub fn sdr50(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR50) + } + #[doc = "`11`"] + #[inline(always)] + pub fn sdr104(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR104) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ddr50(self) -> &'a mut W { + self.variant(UHSMODE_A::DDR50) + } +} +#[doc = "Field `TUNEON` reader - SD Clock tune in progress"] +pub type TUNEON_R = crate::BitReader; +#[doc = "Field `TUNEON` writer - SD Clock tune in progress"] +pub type TUNEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +#[doc = "Field `TUNED` reader - Tuned clock is used for sampling data"] +pub type TUNED_R = crate::BitReader; +#[doc = "Field `TUNED` writer - Tuned clock is used for sampling data"] +pub type TUNED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Auto command not executed due to an error"] + #[inline(always)] + pub fn acnox_err(&self) -> ACNOX_ERR_R { + ACNOX_ERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Auto command timeout"] + #[inline(always)] + pub fn acto_err(&self) -> ACTO_ERR_R { + ACTO_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Command CRC error during auto command"] + #[inline(always)] + pub fn accrc_err(&self) -> ACCRC_ERR_R { + ACCRC_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End bit is not 1 during auto command"] + #[inline(always)] + pub fn acend_err(&self) -> ACEND_ERR_R { + ACEND_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Command index error during auto command"] + #[inline(always)] + pub fn acbad_err(&self) -> ACBAD_ERR_R { + ACBAD_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - Error during auto CMD12"] + #[inline(always)] + pub fn notc12_err(&self) -> NOTC12_ERR_R { + NOTC12_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 16:18 - Select the speed of the SD card"] + #[inline(always)] + pub fn uhsmode(&self) -> UHSMODE_R { + UHSMODE_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 22 - SD Clock tune in progress"] + #[inline(always)] + pub fn tuneon(&self) -> TUNEON_R { + TUNEON_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Tuned clock is used for sampling data"] + #[inline(always)] + pub fn tuned(&self) -> TUNED_R { + TUNED_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bits 16:18 - Select the speed of the SD card"] + #[inline(always)] + #[must_use] + pub fn uhsmode(&mut self) -> UHSMODE_W<16> { + UHSMODE_W::new(self) + } + #[doc = "Bit 22 - SD Clock tune in progress"] + #[inline(always)] + #[must_use] + pub fn tuneon(&mut self) -> TUNEON_W<22> { + TUNEON_W::new(self) + } + #[doc = "Bit 23 - Tuned clock is used for sampling data"] + #[inline(always)] + #[must_use] + pub fn tuned(&mut self) -> TUNED_W<23> { + TUNED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control2](index.html) module"] +pub struct CONTROL2_SPEC; +impl crate::RegisterSpec for CONTROL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control2::R](R) reader structure"] +impl crate::Readable for CONTROL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control2::W](W) writer structure"] +impl crate::Writable for CONTROL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL2 to value 0"] +impl crate::Resettable for CONTROL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/data.rs b/crates/bcm2711-lpa/src/emmc/data.rs new file mode 100644 index 0000000..8c082b8 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/data.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data to/from the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/dbg_sel.rs b/crates/bcm2711-lpa/src/emmc/dbg_sel.rs new file mode 100644 index 0000000..c489a27 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/dbg_sel.rs @@ -0,0 +1,126 @@ +#[doc = "Register `DBG_SEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBG_SEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SELECT` reader - "] +pub type SELECT_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SELECT_A { + #[doc = "0: `0`"] + RECEIVER_FIFO = 0, + #[doc = "1: `1`"] + OTHERS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl SELECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SELECT_A { + match self.bits { + false => SELECT_A::RECEIVER_FIFO, + true => SELECT_A::OTHERS, + } + } + #[doc = "Checks if the value of the field is `RECEIVER_FIFO`"] + #[inline(always)] + pub fn is_receiver_fifo(&self) -> bool { + *self == SELECT_A::RECEIVER_FIFO + } + #[doc = "Checks if the value of the field is `OTHERS`"] + #[inline(always)] + pub fn is_others(&self) -> bool { + *self == SELECT_A::OTHERS + } +} +#[doc = "Field `SELECT` writer - "] +pub type SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DBG_SEL_SPEC, SELECT_A, O>; +impl<'a, const O: u8> SELECT_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn receiver_fifo(self) -> &'a mut W { + self.variant(SELECT_A::RECEIVER_FIFO) + } + #[doc = "`1`"] + #[inline(always)] + pub fn others(self) -> &'a mut W { + self.variant(SELECT_A::OTHERS) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W<0> { + SELECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "What submodules are accessed by the debug bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbg_sel](index.html) module"] +pub struct DBG_SEL_SPEC; +impl crate::RegisterSpec for DBG_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbg_sel::R](R) reader structure"] +impl crate::Readable for DBG_SEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbg_sel::W](W) writer structure"] +impl crate::Writable for DBG_SEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBG_SEL to value 0"] +impl crate::Resettable for DBG_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs b/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs new file mode 100644 index 0000000..1c7e3be --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EXRDFIFO_CFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXRDFIFO_CFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RD_THRSH` reader - Read threshold in 32 bit words"] +pub type RD_THRSH_R = crate::FieldReader; +#[doc = "Field `RD_THRSH` writer - Read threshold in 32 bit words"] +pub type RD_THRSH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXRDFIFO_CFG_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Read threshold in 32 bit words"] + #[inline(always)] + pub fn rd_thrsh(&self) -> RD_THRSH_R { + RD_THRSH_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Read threshold in 32 bit words"] + #[inline(always)] + #[must_use] + pub fn rd_thrsh(&mut self) -> RD_THRSH_W<0> { + RD_THRSH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fine tune DMA request generation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_cfg](index.html) module"] +pub struct EXRDFIFO_CFG_SPEC; +impl crate::RegisterSpec for EXRDFIFO_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [exrdfifo_cfg::R](R) reader structure"] +impl crate::Readable for EXRDFIFO_CFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [exrdfifo_cfg::W](W) writer structure"] +impl crate::Writable for EXRDFIFO_CFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXRDFIFO_CFG to value 0"] +impl crate::Resettable for EXRDFIFO_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs b/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs new file mode 100644 index 0000000..26c7adc --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EXRDFIFO_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXRDFIFO_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable the extension FIFO"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable the extension FIFO"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXRDFIFO_EN_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable the extension FIFO"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the extension FIFO"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable the extension data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_en](index.html) module"] +pub struct EXRDFIFO_EN_SPEC; +impl crate::RegisterSpec for EXRDFIFO_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [exrdfifo_en::R](R) reader structure"] +impl crate::Readable for EXRDFIFO_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [exrdfifo_en::W](W) writer structure"] +impl crate::Writable for EXRDFIFO_EN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXRDFIFO_EN to value 0"] +impl crate::Resettable for EXRDFIFO_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/force_irpt.rs b/crates/bcm2711-lpa/src/emmc/force_irpt.rs new file mode 100644 index 0000000..eca9ec6 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/force_irpt.rs @@ -0,0 +1,320 @@ +#[doc = "Register `FORCE_IRPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORCE_IRPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Force an interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [force_irpt](index.html) module"] +pub struct FORCE_IRPT_SPEC; +impl crate::RegisterSpec for FORCE_IRPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [force_irpt::R](R) reader structure"] +impl crate::Readable for FORCE_IRPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [force_irpt::W](W) writer structure"] +impl crate::Writable for FORCE_IRPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FORCE_IRPT to value 0"] +impl crate::Resettable for FORCE_IRPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/interrupt.rs b/crates/bcm2711-lpa/src/emmc/interrupt.rs new file mode 100644 index 0000000..c687814 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/interrupt.rs @@ -0,0 +1,327 @@ +#[doc = "Register `INTERRUPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTERRUPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ERR` reader - An error has occured"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - An error has occured"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt flags\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"] +pub struct INTERRUPT_SPEC; +impl crate::RegisterSpec for INTERRUPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [interrupt::R](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"] +impl crate::Writable for INTERRUPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTERRUPT to value 0"] +impl crate::Resettable for INTERRUPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/irpt_en.rs b/crates/bcm2711-lpa/src/emmc/irpt_en.rs new file mode 100644 index 0000000..0e71317 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/irpt_en.rs @@ -0,0 +1,320 @@ +#[doc = "Register `IRPT_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRPT_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt to core\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_en](index.html) module"] +pub struct IRPT_EN_SPEC; +impl crate::RegisterSpec for IRPT_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irpt_en::R](R) reader structure"] +impl crate::Readable for IRPT_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irpt_en::W](W) writer structure"] +impl crate::Writable for IRPT_EN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRPT_EN to value 0"] +impl crate::Resettable for IRPT_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/irpt_mask.rs b/crates/bcm2711-lpa/src/emmc/irpt_mask.rs new file mode 100644 index 0000000..87a9fdd --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/irpt_mask.rs @@ -0,0 +1,320 @@ +#[doc = "Register `IRPT_MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRPT_MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Mask interrupts that change in INTERRUPT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_mask](index.html) module"] +pub struct IRPT_MASK_SPEC; +impl crate::RegisterSpec for IRPT_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irpt_mask::R](R) reader structure"] +impl crate::Readable for IRPT_MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irpt_mask::W](W) writer structure"] +impl crate::Writable for IRPT_MASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRPT_MASK to value 0"] +impl crate::Resettable for IRPT_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/resp0.rs b/crates/bcm2711-lpa/src/emmc/resp0.rs new file mode 100644 index 0000000..1022d1a --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/resp0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status bits of the response\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp0](index.html) module"] +pub struct RESP0_SPEC; +impl crate::RegisterSpec for RESP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp0::R](R) reader structure"] +impl crate::Readable for RESP0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp0::W](W) writer structure"] +impl crate::Writable for RESP0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP0 to value 0"] +impl crate::Resettable for RESP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/resp1.rs b/crates/bcm2711-lpa/src/emmc/resp1.rs new file mode 100644 index 0000000..d1e9b42 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/resp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp1](index.html) module"] +pub struct RESP1_SPEC; +impl crate::RegisterSpec for RESP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp1::R](R) reader structure"] +impl crate::Readable for RESP1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp1::W](W) writer structure"] +impl crate::Writable for RESP1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP1 to value 0"] +impl crate::Resettable for RESP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/resp2.rs b/crates/bcm2711-lpa/src/emmc/resp2.rs new file mode 100644 index 0000000..418942a --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/resp2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp2](index.html) module"] +pub struct RESP2_SPEC; +impl crate::RegisterSpec for RESP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp2::R](R) reader structure"] +impl crate::Readable for RESP2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp2::W](W) writer structure"] +impl crate::Writable for RESP2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP2 to value 0"] +impl crate::Resettable for RESP2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/resp3.rs b/crates/bcm2711-lpa/src/emmc/resp3.rs new file mode 100644 index 0000000..36b2c80 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/resp3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp3](index.html) module"] +pub struct RESP3_SPEC; +impl crate::RegisterSpec for RESP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp3::R](R) reader structure"] +impl crate::Readable for RESP3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp3::W](W) writer structure"] +impl crate::Writable for RESP3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP3 to value 0"] +impl crate::Resettable for RESP3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs b/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs new file mode 100644 index 0000000..6016436 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SLOTISR_VER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLOTISR_VER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_STATUS` reader - OR of interrupt and wakeup signals for each slot"] +pub type SLOT_STATUS_R = crate::FieldReader; +#[doc = "Field `SLOT_STATUS` writer - OR of interrupt and wakeup signals for each slot"] +pub type SLOT_STATUS_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +#[doc = "Field `SDVERSION` reader - Host controller specification version"] +pub type SDVERSION_R = crate::FieldReader; +#[doc = "Field `SDVERSION` writer - Host controller specification version"] +pub type SDVERSION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +#[doc = "Field `VENDOR` reader - Vendor version number"] +pub type VENDOR_R = crate::FieldReader; +#[doc = "Field `VENDOR` writer - Vendor version number"] +pub type VENDOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] + #[inline(always)] + pub fn slot_status(&self) -> SLOT_STATUS_R { + SLOT_STATUS_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Host controller specification version"] + #[inline(always)] + pub fn sdversion(&self) -> SDVERSION_R { + SDVERSION_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Vendor version number"] + #[inline(always)] + pub fn vendor(&self) -> VENDOR_R { + VENDOR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] + #[inline(always)] + #[must_use] + pub fn slot_status(&mut self) -> SLOT_STATUS_W<0> { + SLOT_STATUS_W::new(self) + } + #[doc = "Bits 16:23 - Host controller specification version"] + #[inline(always)] + #[must_use] + pub fn sdversion(&mut self) -> SDVERSION_W<16> { + SDVERSION_W::new(self) + } + #[doc = "Bits 24:31 - Vendor version number"] + #[inline(always)] + #[must_use] + pub fn vendor(&mut self) -> VENDOR_W<24> { + VENDOR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Version information and slot interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slotisr_ver](index.html) module"] +pub struct SLOTISR_VER_SPEC; +impl crate::RegisterSpec for SLOTISR_VER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [slotisr_ver::R](R) reader structure"] +impl crate::Readable for SLOTISR_VER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [slotisr_ver::W](W) writer structure"] +impl crate::Writable for SLOTISR_VER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLOTISR_VER to value 0"] +impl crate::Resettable for SLOTISR_VER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs b/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs new file mode 100644 index 0000000..bce7edc --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SPI_INT_SPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SPI_INT_SPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SELECT` reader - "] +pub type SELECT_R = crate::FieldReader; +#[doc = "Field `SELECT` writer - "] +pub type SELECT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_INT_SPT_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W<0> { + SELECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupts in SPI mode depend on CS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_int_spt](index.html) module"] +pub struct SPI_INT_SPT_SPEC; +impl crate::RegisterSpec for SPI_INT_SPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [spi_int_spt::R](R) reader structure"] +impl crate::Readable for SPI_INT_SPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [spi_int_spt::W](W) writer structure"] +impl crate::Writable for SPI_INT_SPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_INT_SPT to value 0"] +impl crate::Resettable for SPI_INT_SPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/status.rs b/crates/bcm2711-lpa/src/emmc/status.rs new file mode 100644 index 0000000..0b86ab0 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/status.rs @@ -0,0 +1,215 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_INHIBIT` reader - Command line still in use"] +pub type CMD_INHIBIT_R = crate::BitReader; +#[doc = "Field `CMD_INHIBIT` writer - Command line still in use"] +pub type CMD_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_INHIBIT` reader - Data lines still in use"] +pub type DAT_INHIBIT_R = crate::BitReader; +#[doc = "Field `DAT_INHIBIT` writer - Data lines still in use"] +pub type DAT_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_ACTIVE` reader - At least one data line is active"] +pub type DAT_ACTIVE_R = crate::BitReader; +#[doc = "Field `DAT_ACTIVE` writer - At least one data line is active"] +pub type DAT_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `WRITE_TRANSFER` reader - Write transfer is active"] +pub type WRITE_TRANSFER_R = crate::BitReader; +#[doc = "Field `WRITE_TRANSFER` writer - Write transfer is active"] +pub type WRITE_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `READ_TRANSFER` reader - Read transfer is active"] +pub type READ_TRANSFER_R = crate::BitReader; +#[doc = "Field `READ_TRANSFER` writer - Read transfer is active"] +pub type READ_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFFER_WRITE_ENABLE` reader - The buffer has space for new data"] +pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; +#[doc = "Field `BUFFER_WRITE_ENABLE` writer - The buffer has space for new data"] +pub type BUFFER_WRITE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFFER_READ_ENABLE` reader - New data is available to read"] +pub type BUFFER_READ_ENABLE_R = crate::BitReader; +#[doc = "Field `BUFFER_READ_ENABLE` writer - New data is available to read"] +pub type BUFFER_READ_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_LEVEL0` reader - Value of DAT\\[3:0\\]"] +pub type DAT_LEVEL0_R = crate::FieldReader; +#[doc = "Field `DAT_LEVEL0` writer - Value of DAT\\[3:0\\]"] +pub type DAT_LEVEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +#[doc = "Field `CMD_LEVEL` reader - Value of CMD"] +pub type CMD_LEVEL_R = crate::BitReader; +#[doc = "Field `CMD_LEVEL` writer - Value of CMD"] +pub type CMD_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_LEVEL1` reader - Value of DAT\\[7:4\\]"] +pub type DAT_LEVEL1_R = crate::FieldReader; +#[doc = "Field `DAT_LEVEL1` writer - Value of DAT\\[7:4\\]"] +pub type DAT_LEVEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Command line still in use"] + #[inline(always)] + pub fn cmd_inhibit(&self) -> CMD_INHIBIT_R { + CMD_INHIBIT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data lines still in use"] + #[inline(always)] + pub fn dat_inhibit(&self) -> DAT_INHIBIT_R { + DAT_INHIBIT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - At least one data line is active"] + #[inline(always)] + pub fn dat_active(&self) -> DAT_ACTIVE_R { + DAT_ACTIVE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Write transfer is active"] + #[inline(always)] + pub fn write_transfer(&self) -> WRITE_TRANSFER_R { + WRITE_TRANSFER_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Read transfer is active"] + #[inline(always)] + pub fn read_transfer(&self) -> READ_TRANSFER_R { + READ_TRANSFER_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The buffer has space for new data"] + #[inline(always)] + pub fn buffer_write_enable(&self) -> BUFFER_WRITE_ENABLE_R { + BUFFER_WRITE_ENABLE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - New data is available to read"] + #[inline(always)] + pub fn buffer_read_enable(&self) -> BUFFER_READ_ENABLE_R { + BUFFER_READ_ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] + #[inline(always)] + pub fn dat_level0(&self) -> DAT_LEVEL0_R { + DAT_LEVEL0_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - Value of CMD"] + #[inline(always)] + pub fn cmd_level(&self) -> CMD_LEVEL_R { + CMD_LEVEL_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] + #[inline(always)] + pub fn dat_level1(&self) -> DAT_LEVEL1_R { + DAT_LEVEL1_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Command line still in use"] + #[inline(always)] + #[must_use] + pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W<0> { + CMD_INHIBIT_W::new(self) + } + #[doc = "Bit 1 - Data lines still in use"] + #[inline(always)] + #[must_use] + pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W<1> { + DAT_INHIBIT_W::new(self) + } + #[doc = "Bit 2 - At least one data line is active"] + #[inline(always)] + #[must_use] + pub fn dat_active(&mut self) -> DAT_ACTIVE_W<2> { + DAT_ACTIVE_W::new(self) + } + #[doc = "Bit 8 - Write transfer is active"] + #[inline(always)] + #[must_use] + pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W<8> { + WRITE_TRANSFER_W::new(self) + } + #[doc = "Bit 9 - Read transfer is active"] + #[inline(always)] + #[must_use] + pub fn read_transfer(&mut self) -> READ_TRANSFER_W<9> { + READ_TRANSFER_W::new(self) + } + #[doc = "Bit 10 - The buffer has space for new data"] + #[inline(always)] + #[must_use] + pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W<10> { + BUFFER_WRITE_ENABLE_W::new(self) + } + #[doc = "Bit 11 - New data is available to read"] + #[inline(always)] + #[must_use] + pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W<11> { + BUFFER_READ_ENABLE_W::new(self) + } + #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn dat_level0(&mut self) -> DAT_LEVEL0_W<20> { + DAT_LEVEL0_W::new(self) + } + #[doc = "Bit 24 - Value of CMD"] + #[inline(always)] + #[must_use] + pub fn cmd_level(&mut self) -> CMD_LEVEL_W<24> { + CMD_LEVEL_W::new(self) + } + #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] + #[inline(always)] + #[must_use] + pub fn dat_level1(&mut self) -> DAT_LEVEL1_W<25> { + DAT_LEVEL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status info for debugging\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/tune_step.rs b/crates/bcm2711-lpa/src/emmc/tune_step.rs new file mode 100644 index 0000000..2f0169b --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/tune_step.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DELAY` reader - "] +pub type DELAY_R = crate::FieldReader; +#[doc = "Field `DELAY` writer - "] +pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEP_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn delay(&self) -> DELAY_R { + DELAY_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2"] + #[inline(always)] + #[must_use] + pub fn delay(&mut self) -> DELAY_W<0> { + DELAY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step duration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_step](index.html) module"] +pub struct TUNE_STEP_SPEC; +impl crate::RegisterSpec for TUNE_STEP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_step::R](R) reader structure"] +impl crate::Readable for TUNE_STEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_step::W](W) writer structure"] +impl crate::Writable for TUNE_STEP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEP to value 0"] +impl crate::Resettable for TUNE_STEP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs b/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs new file mode 100644 index 0000000..a8fea76 --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEPS_DDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEPS_DDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STEPS` reader - "] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - "] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_DDR_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<0> { + STEPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step count for DDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_ddr](index.html) module"] +pub struct TUNE_STEPS_DDR_SPEC; +impl crate::RegisterSpec for TUNE_STEPS_DDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_steps_ddr::R](R) reader structure"] +impl crate::Readable for TUNE_STEPS_DDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_steps_ddr::W](W) writer structure"] +impl crate::Writable for TUNE_STEPS_DDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEPS_DDR to value 0"] +impl crate::Resettable for TUNE_STEPS_DDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs b/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs new file mode 100644 index 0000000..c04740c --- /dev/null +++ b/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEPS_STD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEPS_STD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STEPS` reader - "] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - "] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_STD_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<0> { + STEPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step count for SDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_std](index.html) module"] +pub struct TUNE_STEPS_STD_SPEC; +impl crate::RegisterSpec for TUNE_STEPS_STD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_steps_std::R](R) reader structure"] +impl crate::Readable for TUNE_STEPS_STD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_steps_std::W](W) writer structure"] +impl crate::Writable for TUNE_STEPS_STD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEPS_STD to value 0"] +impl crate::Resettable for TUNE_STEPS_STD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/generic.rs b/crates/bcm2711-lpa/src/generic.rs new file mode 100644 index 0000000..f10ca73 --- /dev/null +++ b/crates/bcm2711-lpa/src/generic.rs @@ -0,0 +1,695 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc(hidden)] +pub struct FieldReaderRaw { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReaderRaw +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitReaderRaw { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReaderRaw { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = FieldReaderRaw; +#[doc = " Bit-wise field reader"] +pub type BitReader = BitReaderRaw; +impl FieldReader +where + U: Copy, +{ + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy, + U: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&U::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc(hidden)] +pub struct Safe; +#[doc(hidden)] +pub struct Unsafe; +#[doc(hidden)] +pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> +where + REG: Writable + RegisterSpec, + N: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(N, FI, Safety)>, +} +impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> + FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + } + }; +} +macro_rules! impl_bit_proxy { + ($ writer : ident) => { + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, + { + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w.bits |= (U::from(value) & U::one()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + unsafe { self.bits(N::from(variant)) } + } +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bits(N::from(variant)) + } +} +impl_bit_proxy!(BitWriter); +impl_bit_proxy!(BitWriter1S); +impl_bit_proxy!(BitWriter0C); +impl_bit_proxy!(BitWriter1C); +impl_bit_proxy!(BitWriter0S); +impl_bit_proxy!(BitWriter1T); +impl_bit_proxy!(BitWriter0T); +impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +mod atomic; +use atomic::AtomicOperations; +impl Reg +where + REG::Ux: AtomicOperations + Default + core::ops::Not, +{ + #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn set_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: Default::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_or(self.register.as_ptr(), bits); + } + #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn clear_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: !REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_and(self.register.as_ptr(), bits); + } + #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn toggle_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: Default::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_xor(self.register.as_ptr(), bits); + } +} diff --git a/crates/bcm2711-lpa/src/generic/atomic.rs b/crates/bcm2711-lpa/src/generic/atomic.rs new file mode 100644 index 0000000..acee997 --- /dev/null +++ b/crates/bcm2711-lpa/src/generic/atomic.rs @@ -0,0 +1,27 @@ +use portable_atomic::Ordering; +pub trait AtomicOperations { + unsafe fn atomic_or(ptr: *mut Self, val: Self); + unsafe fn atomic_and(ptr: *mut Self, val: Self); + unsafe fn atomic_xor(ptr: *mut Self, val: Self); +} +macro_rules! impl_atomics { + ($ U : ty , $ Atomic : ty) => { + impl AtomicOperations for $U { + unsafe fn atomic_or(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).or(val, Ordering::SeqCst); + } + unsafe fn atomic_and(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).and(val, Ordering::SeqCst); + } + unsafe fn atomic_xor(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).xor(val, Ordering::SeqCst); + } + } + }; +} +impl_atomics!(u8, portable_atomic::AtomicU8); +impl_atomics!(u16, portable_atomic::AtomicU16); +#[cfg(not(target_pointer_width = "16"))] +impl_atomics!(u32, portable_atomic::AtomicU32); +#[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))] +impl_atomics!(u64, portable_atomic::AtomicU64); diff --git a/crates/bcm2711-lpa/src/gic_cpu.rs b/crates/bcm2711-lpa/src/gic_cpu.rs new file mode 100644 index 0000000..4034a7d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu.rs @@ -0,0 +1,98 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - CPU Interface Control"] + pub gicc_ctlr: GICC_CTLR, + #[doc = "0x04 - Interrupt Priority Mask"] + pub gicc_pmr: GICC_PMR, + #[doc = "0x08 - Binary Point"] + pub gicc_bpr: GICC_BPR, + #[doc = "0x0c - Interrupt Acknowledge"] + pub gicc_iar: GICC_IAR, + #[doc = "0x10 - End of Interrupt"] + pub gicc_eoir: GICC_EOIR, + #[doc = "0x14 - Running Priority"] + pub gicc_rpr: GICC_RPR, + #[doc = "0x18 - Highest Priority Pending Interrupt"] + pub gicc_hppir: GICC_HPPIR, + #[doc = "0x1c - Aliased Binary Point"] + pub gicc_abpr: GICC_ABPR, + #[doc = "0x20 - Aliased Interrupt Acknowledge"] + pub gicc_aiar: GICC_AIAR, + #[doc = "0x24 - Aliased End of Interrupt"] + pub gicc_aeoir: GICC_AEOIR, + #[doc = "0x28 - Aliased Highest Priority Pending Interrupt"] + pub gicc_ahppir: GICC_AHPPIR, + _reserved11: [u8; 0xa4], + #[doc = "0xd0 - Active Priority"] + pub gicc_apr0: GICC_APR0, + _reserved12: [u8; 0x0c], + #[doc = "0xe0 - Non-Secure Active Priority"] + pub gicc_nsapr0: GICC_NSAPR0, + _reserved13: [u8; 0x18], + #[doc = "0xfc - CPU Interface Identification Register"] + pub gicc_iidr: GICC_IIDR, + _reserved14: [u8; 0x0f00], + #[doc = "0x1000 - Deactivate Interrupt"] + pub gicc_dir: GICC_DIR, +} +#[doc = "GICC_CTLR (rw) register accessor: an alias for `Reg`"] +pub type GICC_CTLR = crate::Reg; +#[doc = "CPU Interface Control"] +pub mod gicc_ctlr; +#[doc = "GICC_PMR (rw) register accessor: an alias for `Reg`"] +pub type GICC_PMR = crate::Reg; +#[doc = "Interrupt Priority Mask"] +pub mod gicc_pmr; +#[doc = "GICC_BPR (rw) register accessor: an alias for `Reg`"] +pub type GICC_BPR = crate::Reg; +#[doc = "Binary Point"] +pub mod gicc_bpr; +#[doc = "GICC_IAR (r) register accessor: an alias for `Reg`"] +pub type GICC_IAR = crate::Reg; +#[doc = "Interrupt Acknowledge"] +pub mod gicc_iar; +#[doc = "GICC_EOIR (w) register accessor: an alias for `Reg`"] +pub type GICC_EOIR = crate::Reg; +#[doc = "End of Interrupt"] +pub mod gicc_eoir; +#[doc = "GICC_RPR (r) register accessor: an alias for `Reg`"] +pub type GICC_RPR = crate::Reg; +#[doc = "Running Priority"] +pub mod gicc_rpr; +#[doc = "GICC_HPPIR (rw) register accessor: an alias for `Reg`"] +pub type GICC_HPPIR = crate::Reg; +#[doc = "Highest Priority Pending Interrupt"] +pub mod gicc_hppir; +#[doc = "GICC_ABPR (rw) register accessor: an alias for `Reg`"] +pub type GICC_ABPR = crate::Reg; +#[doc = "Aliased Binary Point"] +pub mod gicc_abpr; +#[doc = "GICC_AIAR (r) register accessor: an alias for `Reg`"] +pub type GICC_AIAR = crate::Reg; +#[doc = "Aliased Interrupt Acknowledge"] +pub mod gicc_aiar; +#[doc = "GICC_AEOIR (w) register accessor: an alias for `Reg`"] +pub type GICC_AEOIR = crate::Reg; +#[doc = "Aliased End of Interrupt"] +pub mod gicc_aeoir; +#[doc = "GICC_AHPPIR (r) register accessor: an alias for `Reg`"] +pub type GICC_AHPPIR = crate::Reg; +#[doc = "Aliased Highest Priority Pending Interrupt"] +pub mod gicc_ahppir; +#[doc = "GICC_APR0 (rw) register accessor: an alias for `Reg`"] +pub type GICC_APR0 = crate::Reg; +#[doc = "Active Priority"] +pub mod gicc_apr0; +#[doc = "GICC_NSAPR0 (rw) register accessor: an alias for `Reg`"] +pub type GICC_NSAPR0 = crate::Reg; +#[doc = "Non-Secure Active Priority"] +pub mod gicc_nsapr0; +#[doc = "GICC_IIDR (rw) register accessor: an alias for `Reg`"] +pub type GICC_IIDR = crate::Reg; +#[doc = "CPU Interface Identification Register"] +pub mod gicc_iidr; +#[doc = "GICC_DIR (w) register accessor: an alias for `Reg`"] +pub type GICC_DIR = crate::Reg; +#[doc = "Deactivate Interrupt"] +pub mod gicc_dir; diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs new file mode 100644 index 0000000..3975333 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs @@ -0,0 +1,81 @@ +#[doc = "Register `GICC_ABPR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_ABPR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BINARY_POINT` reader - Split point between group priority and subpriority"] +pub type BINARY_POINT_R = crate::FieldReader; +#[doc = "Field `BINARY_POINT` writer - Split point between group priority and subpriority"] +pub type BINARY_POINT_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICC_ABPR_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Split point between group priority and subpriority"] + #[inline(always)] + pub fn binary_point(&self) -> BINARY_POINT_R { + BINARY_POINT_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Split point between group priority and subpriority"] + #[inline(always)] + #[must_use] + pub fn binary_point(&mut self) -> BINARY_POINT_W<0> { + BINARY_POINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Aliased Binary Point\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_abpr](index.html) module"] +pub struct GICC_ABPR_SPEC; +impl crate::RegisterSpec for GICC_ABPR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_abpr::R](R) reader structure"] +impl crate::Readable for GICC_ABPR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_abpr::W](W) writer structure"] +impl crate::Writable for GICC_ABPR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_ABPR to value 0"] +impl crate::Resettable for GICC_ABPR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs new file mode 100644 index 0000000..96afcae --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs @@ -0,0 +1,61 @@ +#[doc = "Register `GICC_AEOIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INTERRUPT_ID` writer - Interrupt ID"] +pub type INTERRUPT_ID_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICC_AEOIR_SPEC, u16, u16, 10, O>; +#[doc = "Field `CPUID` writer - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_AEOIR_SPEC, u8, u8, 3, O>; +impl W { + #[doc = "Bits 0:9 - Interrupt ID"] + #[inline(always)] + #[must_use] + pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<0> { + INTERRUPT_ID_W::new(self) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + #[must_use] + pub fn cpuid(&mut self) -> CPUID_W<10> { + CPUID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Aliased End of Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_aeoir](index.html) module"] +pub struct GICC_AEOIR_SPEC; +impl crate::RegisterSpec for GICC_AEOIR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gicc_aeoir::W](W) writer structure"] +impl crate::Writable for GICC_AEOIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_AEOIR to value 0"] +impl crate::Resettable for GICC_AEOIR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs new file mode 100644 index 0000000..bb21049 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs @@ -0,0 +1,44 @@ +#[doc = "Register `GICC_AHPPIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INTERRUPT_ID` reader - Pending Interrupt ID"] +pub type INTERRUPT_ID_R = crate::FieldReader; +#[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Pending Interrupt ID"] + #[inline(always)] + pub fn interrupt_id(&self) -> INTERRUPT_ID_R { + INTERRUPT_ID_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + pub fn cpuid(&self) -> CPUID_R { + CPUID_R::new(((self.bits >> 10) & 7) as u8) + } +} +#[doc = "Aliased Highest Priority Pending Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_ahppir](index.html) module"] +pub struct GICC_AHPPIR_SPEC; +impl crate::RegisterSpec for GICC_AHPPIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_ahppir::R](R) reader structure"] +impl crate::Readable for GICC_AHPPIR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICC_AHPPIR to value 0"] +impl crate::Resettable for GICC_AHPPIR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs new file mode 100644 index 0000000..03c5d81 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs @@ -0,0 +1,44 @@ +#[doc = "Register `GICC_AIAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INTERRUPT_ID` reader - Interrupt ID"] +pub type INTERRUPT_ID_R = crate::FieldReader; +#[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Interrupt ID"] + #[inline(always)] + pub fn interrupt_id(&self) -> INTERRUPT_ID_R { + INTERRUPT_ID_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + pub fn cpuid(&self) -> CPUID_R { + CPUID_R::new(((self.bits >> 10) & 7) as u8) + } +} +#[doc = "Aliased Interrupt Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_aiar](index.html) module"] +pub struct GICC_AIAR_SPEC; +impl crate::RegisterSpec for GICC_AIAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_aiar::R](R) reader structure"] +impl crate::Readable for GICC_AIAR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICC_AIAR to value 0"] +impl crate::Resettable for GICC_AIAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs new file mode 100644 index 0000000..27ab9b0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GICC_APR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_APR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Active Priority\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_apr0](index.html) module"] +pub struct GICC_APR0_SPEC; +impl crate::RegisterSpec for GICC_APR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_apr0::R](R) reader structure"] +impl crate::Readable for GICC_APR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_apr0::W](W) writer structure"] +impl crate::Writable for GICC_APR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_APR0 to value 0"] +impl crate::Resettable for GICC_APR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs new file mode 100644 index 0000000..17bad97 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GICC_BPR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_BPR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BINARY_POINT` reader - Split point between group priority and subpriority"] +pub type BINARY_POINT_R = crate::FieldReader; +#[doc = "Field `BINARY_POINT` writer - Split point between group priority and subpriority"] +pub type BINARY_POINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_BPR_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Split point between group priority and subpriority"] + #[inline(always)] + pub fn binary_point(&self) -> BINARY_POINT_R { + BINARY_POINT_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Split point between group priority and subpriority"] + #[inline(always)] + #[must_use] + pub fn binary_point(&mut self) -> BINARY_POINT_W<0> { + BINARY_POINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Binary Point\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_bpr](index.html) module"] +pub struct GICC_BPR_SPEC; +impl crate::RegisterSpec for GICC_BPR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_bpr::R](R) reader structure"] +impl crate::Readable for GICC_BPR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_bpr::W](W) writer structure"] +impl crate::Writable for GICC_BPR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_BPR to value 0"] +impl crate::Resettable for GICC_BPR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs new file mode 100644 index 0000000..97be545 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs @@ -0,0 +1,230 @@ +#[doc = "Register `GICC_CTLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_CTLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE_GROUP_0` reader - Enable signaling of group 0"] +pub type ENABLE_GROUP_0_R = crate::BitReader; +#[doc = "Field `ENABLE_GROUP_0` writer - Enable signaling of group 0"] +pub type ENABLE_GROUP_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `ENABLE_GROUP_1` reader - Enable signaling of group 1"] +pub type ENABLE_GROUP_1_R = crate::BitReader; +#[doc = "Field `ENABLE_GROUP_1` writer - Enable signaling of group 1"] +pub type ENABLE_GROUP_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `ACKCTL` reader - Whether a read of IAR acknowledges the interrupt"] +pub type ACKCTL_R = crate::BitReader; +#[doc = "Field `ACKCTL` writer - Whether a read of IAR acknowledges the interrupt"] +pub type ACKCTL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `FIQEN` reader - Group 0 triggers FIQ"] +pub type FIQEN_R = crate::BitReader; +#[doc = "Field `FIQEN` writer - Group 0 triggers FIQ"] +pub type FIQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `CBPR` reader - Common control of interrupts through GICC_BPR"] +pub type CBPR_R = crate::BitReader; +#[doc = "Field `CBPR` writer - Common control of interrupts through GICC_BPR"] +pub type CBPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `FIQBYPDISGRP0` reader - Bypass FIQ is not signaled to processor"] +pub type FIQBYPDISGRP0_R = crate::BitReader; +#[doc = "Field `FIQBYPDISGRP0` writer - Bypass FIQ is not signaled to processor"] +pub type FIQBYPDISGRP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `IRQBYPDISGRP0` reader - Bypass IRQ is not signaled to processor"] +pub type IRQBYPDISGRP0_R = crate::BitReader; +#[doc = "Field `IRQBYPDISGRP0` writer - Bypass IRQ is not signaled to processor"] +pub type IRQBYPDISGRP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `FIQBYPDISGRP1` reader - Alias of group 1 FIQ bypass disable"] +pub type FIQBYPDISGRP1_R = crate::BitReader; +#[doc = "Field `FIQBYPDISGRP1` writer - Alias of group 1 FIQ bypass disable"] +pub type FIQBYPDISGRP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `IRQBYPDISGRP1` reader - Alias of group 1 IRQ bypass disable"] +pub type IRQBYPDISGRP1_R = crate::BitReader; +#[doc = "Field `IRQBYPDISGRP1` writer - Alias of group 1 IRQ bypass disable"] +pub type IRQBYPDISGRP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `EOIMODES` reader - Secure EOIR does priority drop. DIR does deactivate."] +pub type EOIMODES_R = crate::BitReader; +#[doc = "Field `EOIMODES` writer - Secure EOIR does priority drop. DIR does deactivate."] +pub type EOIMODES_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +#[doc = "Field `EOIMODENS` reader - Non-Secure EOIR does priority drop. DIR does deactivate."] +pub type EOIMODENS_R = crate::BitReader; +#[doc = "Field `EOIMODENS` writer - Non-Secure EOIR does priority drop. DIR does deactivate."] +pub type EOIMODENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable signaling of group 0"] + #[inline(always)] + pub fn enable_group_0(&self) -> ENABLE_GROUP_0_R { + ENABLE_GROUP_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable signaling of group 1"] + #[inline(always)] + pub fn enable_group_1(&self) -> ENABLE_GROUP_1_R { + ENABLE_GROUP_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Whether a read of IAR acknowledges the interrupt"] + #[inline(always)] + pub fn ackctl(&self) -> ACKCTL_R { + ACKCTL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Group 0 triggers FIQ"] + #[inline(always)] + pub fn fiqen(&self) -> FIQEN_R { + FIQEN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Common control of interrupts through GICC_BPR"] + #[inline(always)] + pub fn cbpr(&self) -> CBPR_R { + CBPR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Bypass FIQ is not signaled to processor"] + #[inline(always)] + pub fn fiqbypdisgrp0(&self) -> FIQBYPDISGRP0_R { + FIQBYPDISGRP0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Bypass IRQ is not signaled to processor"] + #[inline(always)] + pub fn irqbypdisgrp0(&self) -> IRQBYPDISGRP0_R { + IRQBYPDISGRP0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Alias of group 1 FIQ bypass disable"] + #[inline(always)] + pub fn fiqbypdisgrp1(&self) -> FIQBYPDISGRP1_R { + FIQBYPDISGRP1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Alias of group 1 IRQ bypass disable"] + #[inline(always)] + pub fn irqbypdisgrp1(&self) -> IRQBYPDISGRP1_R { + IRQBYPDISGRP1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Secure EOIR does priority drop. DIR does deactivate."] + #[inline(always)] + pub fn eoimodes(&self) -> EOIMODES_R { + EOIMODES_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Non-Secure EOIR does priority drop. DIR does deactivate."] + #[inline(always)] + pub fn eoimodens(&self) -> EOIMODENS_R { + EOIMODENS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable signaling of group 0"] + #[inline(always)] + #[must_use] + pub fn enable_group_0(&mut self) -> ENABLE_GROUP_0_W<0> { + ENABLE_GROUP_0_W::new(self) + } + #[doc = "Bit 1 - Enable signaling of group 1"] + #[inline(always)] + #[must_use] + pub fn enable_group_1(&mut self) -> ENABLE_GROUP_1_W<1> { + ENABLE_GROUP_1_W::new(self) + } + #[doc = "Bit 2 - Whether a read of IAR acknowledges the interrupt"] + #[inline(always)] + #[must_use] + pub fn ackctl(&mut self) -> ACKCTL_W<2> { + ACKCTL_W::new(self) + } + #[doc = "Bit 3 - Group 0 triggers FIQ"] + #[inline(always)] + #[must_use] + pub fn fiqen(&mut self) -> FIQEN_W<3> { + FIQEN_W::new(self) + } + #[doc = "Bit 4 - Common control of interrupts through GICC_BPR"] + #[inline(always)] + #[must_use] + pub fn cbpr(&mut self) -> CBPR_W<4> { + CBPR_W::new(self) + } + #[doc = "Bit 5 - Bypass FIQ is not signaled to processor"] + #[inline(always)] + #[must_use] + pub fn fiqbypdisgrp0(&mut self) -> FIQBYPDISGRP0_W<5> { + FIQBYPDISGRP0_W::new(self) + } + #[doc = "Bit 6 - Bypass IRQ is not signaled to processor"] + #[inline(always)] + #[must_use] + pub fn irqbypdisgrp0(&mut self) -> IRQBYPDISGRP0_W<6> { + IRQBYPDISGRP0_W::new(self) + } + #[doc = "Bit 7 - Alias of group 1 FIQ bypass disable"] + #[inline(always)] + #[must_use] + pub fn fiqbypdisgrp1(&mut self) -> FIQBYPDISGRP1_W<7> { + FIQBYPDISGRP1_W::new(self) + } + #[doc = "Bit 8 - Alias of group 1 IRQ bypass disable"] + #[inline(always)] + #[must_use] + pub fn irqbypdisgrp1(&mut self) -> IRQBYPDISGRP1_W<8> { + IRQBYPDISGRP1_W::new(self) + } + #[doc = "Bit 9 - Secure EOIR does priority drop. DIR does deactivate."] + #[inline(always)] + #[must_use] + pub fn eoimodes(&mut self) -> EOIMODES_W<9> { + EOIMODES_W::new(self) + } + #[doc = "Bit 10 - Non-Secure EOIR does priority drop. DIR does deactivate."] + #[inline(always)] + #[must_use] + pub fn eoimodens(&mut self) -> EOIMODENS_W<10> { + EOIMODENS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Interface Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_ctlr](index.html) module"] +pub struct GICC_CTLR_SPEC; +impl crate::RegisterSpec for GICC_CTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_ctlr::R](R) reader structure"] +impl crate::Readable for GICC_CTLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_ctlr::W](W) writer structure"] +impl crate::Writable for GICC_CTLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_CTLR to value 0"] +impl crate::Resettable for GICC_CTLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs new file mode 100644 index 0000000..085fb08 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs @@ -0,0 +1,44 @@ +#[doc = "Register `GICC_DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Deactivate Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_dir](index.html) module"] +pub struct GICC_DIR_SPEC; +impl crate::RegisterSpec for GICC_DIR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gicc_dir::W](W) writer structure"] +impl crate::Writable for GICC_DIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_DIR to value 0"] +impl crate::Resettable for GICC_DIR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs new file mode 100644 index 0000000..3b01bd6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs @@ -0,0 +1,61 @@ +#[doc = "Register `GICC_EOIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INTERRUPT_ID` writer - Interrupt ID"] +pub type INTERRUPT_ID_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICC_EOIR_SPEC, u16, u16, 10, O>; +#[doc = "Field `CPUID` writer - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_EOIR_SPEC, u8, u8, 3, O>; +impl W { + #[doc = "Bits 0:9 - Interrupt ID"] + #[inline(always)] + #[must_use] + pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<0> { + INTERRUPT_ID_W::new(self) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + #[must_use] + pub fn cpuid(&mut self) -> CPUID_W<10> { + CPUID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "End of Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_eoir](index.html) module"] +pub struct GICC_EOIR_SPEC; +impl crate::RegisterSpec for GICC_EOIR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gicc_eoir::W](W) writer structure"] +impl crate::Writable for GICC_EOIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_EOIR to value 0"] +impl crate::Resettable for GICC_EOIR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs new file mode 100644 index 0000000..ac14818 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs @@ -0,0 +1,96 @@ +#[doc = "Register `GICC_HPPIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_HPPIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INTERRUPT_ID` reader - Pending Interrupt ID"] +pub type INTERRUPT_ID_R = crate::FieldReader; +#[doc = "Field `INTERRUPT_ID` writer - Pending Interrupt ID"] +pub type INTERRUPT_ID_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICC_HPPIR_SPEC, u16, u16, 10, O>; +#[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_R = crate::FieldReader; +#[doc = "Field `CPUID` writer - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_HPPIR_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:9 - Pending Interrupt ID"] + #[inline(always)] + pub fn interrupt_id(&self) -> INTERRUPT_ID_R { + INTERRUPT_ID_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + pub fn cpuid(&self) -> CPUID_R { + CPUID_R::new(((self.bits >> 10) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:9 - Pending Interrupt ID"] + #[inline(always)] + #[must_use] + pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<0> { + INTERRUPT_ID_W::new(self) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + #[must_use] + pub fn cpuid(&mut self) -> CPUID_W<10> { + CPUID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Highest Priority Pending Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_hppir](index.html) module"] +pub struct GICC_HPPIR_SPEC; +impl crate::RegisterSpec for GICC_HPPIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_hppir::R](R) reader structure"] +impl crate::Readable for GICC_HPPIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_hppir::W](W) writer structure"] +impl crate::Writable for GICC_HPPIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_HPPIR to value 0"] +impl crate::Resettable for GICC_HPPIR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs new file mode 100644 index 0000000..5df4c51 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs @@ -0,0 +1,44 @@ +#[doc = "Register `GICC_IAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INTERRUPT_ID` reader - Interrupt ID"] +pub type INTERRUPT_ID_R = crate::FieldReader; +#[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] +pub type CPUID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Interrupt ID"] + #[inline(always)] + pub fn interrupt_id(&self) -> INTERRUPT_ID_R { + INTERRUPT_ID_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] + #[inline(always)] + pub fn cpuid(&self) -> CPUID_R { + CPUID_R::new(((self.bits >> 10) & 7) as u8) + } +} +#[doc = "Interrupt Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_iar](index.html) module"] +pub struct GICC_IAR_SPEC; +impl crate::RegisterSpec for GICC_IAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_iar::R](R) reader structure"] +impl crate::Readable for GICC_IAR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICC_IAR to value 0"] +impl crate::Resettable for GICC_IAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs new file mode 100644 index 0000000..58d00e8 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs @@ -0,0 +1,115 @@ +#[doc = "Register `GICC_IIDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_IIDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - ID"] +pub type ID_R = crate::FieldReader; +#[doc = "ID\n\nValue on reset: 33690683"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum ID_A { + #[doc = "33690683: ID is valid"] + VALID = 33690683, +} +impl From for u32 { + #[inline(always)] + fn from(variant: ID_A) -> Self { + variant as _ + } +} +impl ID_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 33690683 => Some(ID_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == ID_A::VALID + } +} +#[doc = "Field `ID` writer - ID"] +pub type ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_IIDR_SPEC, u32, ID_A, 32, O>; +impl<'a, const O: u8> ID_W<'a, O> { + #[doc = "ID is valid"] + #[inline(always)] + pub fn valid(self) -> &'a mut W { + self.variant(ID_A::VALID) + } +} +impl R { + #[doc = "Bits 0:31 - ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - ID"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W<0> { + ID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Interface Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_iidr](index.html) module"] +pub struct GICC_IIDR_SPEC; +impl crate::RegisterSpec for GICC_IIDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_iidr::R](R) reader structure"] +impl crate::Readable for GICC_IIDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_iidr::W](W) writer structure"] +impl crate::Writable for GICC_IIDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_IIDR to value 0x0202_143b"] +impl crate::Resettable for GICC_IIDR_SPEC { + const RESET_VALUE: Self::Ux = 0x0202_143b; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs new file mode 100644 index 0000000..516f769 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GICC_NSAPR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_NSAPR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Secure Active Priority\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_nsapr0](index.html) module"] +pub struct GICC_NSAPR0_SPEC; +impl crate::RegisterSpec for GICC_NSAPR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_nsapr0::R](R) reader structure"] +impl crate::Readable for GICC_NSAPR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_nsapr0::W](W) writer structure"] +impl crate::Writable for GICC_NSAPR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_NSAPR0 to value 0"] +impl crate::Resettable for GICC_NSAPR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs new file mode 100644 index 0000000..826676d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GICC_PMR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICC_PMR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRIORITY` reader - Interrupts with a higher number are not signaled"] +pub type PRIORITY_R = crate::FieldReader; +#[doc = "Field `PRIORITY` writer - Interrupts with a higher number are not signaled"] +pub type PRIORITY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_PMR_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupts with a higher number are not signaled"] + #[inline(always)] + pub fn priority(&self) -> PRIORITY_R { + PRIORITY_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupts with a higher number are not signaled"] + #[inline(always)] + #[must_use] + pub fn priority(&mut self) -> PRIORITY_W<0> { + PRIORITY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_pmr](index.html) module"] +pub struct GICC_PMR_SPEC; +impl crate::RegisterSpec for GICC_PMR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_pmr::R](R) reader structure"] +impl crate::Readable for GICC_PMR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicc_pmr::W](W) writer structure"] +impl crate::Writable for GICC_PMR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICC_PMR to value 0"] +impl crate::Resettable for GICC_PMR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs new file mode 100644 index 0000000..0fd4ff9 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs @@ -0,0 +1,37 @@ +#[doc = "Register `GICC_RPR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PRIORITY` reader - Current running priority"] +pub type PRIORITY_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Current running priority"] + #[inline(always)] + pub fn priority(&self) -> PRIORITY_R { + PRIORITY_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Running Priority\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_rpr](index.html) module"] +pub struct GICC_RPR_SPEC; +impl crate::RegisterSpec for GICC_RPR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicc_rpr::R](R) reader structure"] +impl crate::Readable for GICC_RPR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICC_RPR to value 0"] +impl crate::Resettable for GICC_RPR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist.rs b/crates/bcm2711-lpa/src/gic_dist.rs new file mode 100644 index 0000000..d461b3d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist.rs @@ -0,0 +1,239 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Distributor Control Register"] + pub gicd_ctlr: GICD_CTLR, + #[doc = "0x04 - Interrupt Controller Type Register"] + pub gicd_typer: GICD_TYPER, + #[doc = "0x08 - Distributor Implementer Identification Register"] + pub gicd_iidr: GICD_IIDR, + _reserved3: [u8; 0x74], + #[doc = "0x80..0x9c - Interrupt Group Registers"] + pub gicd_igroupr: GICD_IGROUPR, + _reserved4: [u8; 0x64], + #[doc = "0x100..0x11c - Interrupt Set-Enable Registers"] + pub gicd_isenabler: GICD_ISENABLER, + _reserved5: [u8; 0x64], + #[doc = "0x180..0x19c - Interrupt Clear-Enable Registers"] + pub gicd_icenabler: GICD_ICENABLER, + _reserved6: [u8; 0x64], + #[doc = "0x200..0x21c - Interrupt Set-Pending Registers"] + pub gicd_ispendr: GICD_ISPENDR, + _reserved7: [u8; 0x64], + #[doc = "0x280..0x29c - Interrupt Clear-Pending Registers"] + pub gicd_icpendr: GICD_ICPENDR, + _reserved8: [u8; 0x64], + #[doc = "0x300..0x31c - Interrupt Set-Active Registers"] + pub gicd_isactiver: GICD_ISACTIVER, + _reserved9: [u8; 0x64], + #[doc = "0x380..0x39c - Interrupt Clear-Active Registers"] + pub gicd_icactiver: GICD_ICACTIVER, + _reserved10: [u8; 0x64], + #[doc = "0x400..0x4e0 - Interrupt Priority"] + pub gicd_ipriorityr: GICD_IPRIORITYR, + _reserved11: [u8; 0x0320], + #[doc = "0x800..0x8e0 - Interrupt Processor Targets"] + pub gicd_itargetsr: GICD_ITARGETSR, + _reserved12: [u8; 0x0320], + #[doc = "0xc00..0xc38 - Interrupt Configuration"] + pub gicd_icfgr: GICD_ICFGR, + _reserved13: [u8; 0xc8], + #[doc = "0xd00 - Private Peripheral Interrupt Status Register"] + pub gicd_ppisr: GICD_PPISR, + #[doc = "0xd04 - Shared Peripheral Interrupt Status Registers"] + pub gicd_spisr0: GICD_SPISR0, + #[doc = "0xd08 - Shared Peripheral Interrupt Status Registers"] + pub gicd_spisr1: GICD_SPISR1, + #[doc = "0xd0c - Shared Peripheral Interrupt Status Registers"] + pub gicd_spisr2: GICD_SPISR2, + #[doc = "0xd10 - Shared Peripheral Interrupt Status Registers"] + pub gicd_spisr3: GICD_SPISR3, + #[doc = "0xd14 - Shared Peripheral Interrupt Status Registers"] + pub gicd_spisr4: GICD_SPISR4, + #[doc = "0xd18 - Shared Peripheral Interrupt Status Registers"] + pub gicd_spisr5: GICD_SPISR5, + _reserved20: [u8; 0x01e4], + #[doc = "0xf00 - Software Generated Interrupt Register"] + pub gicd_sgir: GICD_SGIR, + _reserved21: [u8; 0x0c], + #[doc = "0xf10 - SGI Clear-Pending Registers"] + pub gicd_cpendsgirn: GICD_CPENDSGIRN, + _reserved22: [u8; 0x0c], + #[doc = "0xf20 - SGI Set-Pending Registers"] + pub gicd_spendsgirn: GICD_SPENDSGIRN, + _reserved23: [u8; 0xac], + #[doc = "0xfd0 - Peripheral ID 4"] + pub gicd_pidr4: GICD_PIDR4, + #[doc = "0xfd4 - Peripheral ID 5"] + pub gicd_pidr5: GICD_PIDR5, + #[doc = "0xfd8 - Peripheral ID 6"] + pub gicd_pidr6: GICD_PIDR6, + #[doc = "0xfdc - Peripheral ID 7"] + pub gicd_pidr7: GICD_PIDR7, + #[doc = "0xfe0 - Peripheral ID 0"] + pub gicd_pidr0: GICD_PIDR0, + #[doc = "0xfe4 - Peripheral ID 1"] + pub gicd_pidr1: GICD_PIDR1, + #[doc = "0xfe8 - Peripheral ID 2"] + pub gicd_pidr2: GICD_PIDR2, + #[doc = "0xfec - Peripheral ID 3"] + pub gicd_pidr3: GICD_PIDR3, + #[doc = "0xff0 - Component ID 0"] + pub gicd_cidr0: GICD_CIDR0, + #[doc = "0xff4 - Component ID 1"] + pub gicd_cidr1: GICD_CIDR1, + #[doc = "0xff8 - Component ID 2"] + pub gicd_cidr2: GICD_CIDR2, + #[doc = "0xffc - Component ID 3"] + pub gicd_cidr3: GICD_CIDR3, +} +#[doc = "GICD_CTLR (rw) register accessor: an alias for `Reg`"] +pub type GICD_CTLR = crate::Reg; +#[doc = "Distributor Control Register"] +pub mod gicd_ctlr; +#[doc = "GICD_TYPER (r) register accessor: an alias for `Reg`"] +pub type GICD_TYPER = crate::Reg; +#[doc = "Interrupt Controller Type Register"] +pub mod gicd_typer; +#[doc = "GICD_IIDR (r) register accessor: an alias for `Reg`"] +pub type GICD_IIDR = crate::Reg; +#[doc = "Distributor Implementer Identification Register"] +pub mod gicd_iidr; +#[doc = "Interrupt Group Registers"] +pub use self::gicd_igroupr::GICD_IGROUPR; +#[doc = r"Cluster"] +#[doc = "Interrupt Group Registers"] +pub mod gicd_igroupr; +#[doc = "Interrupt Set-Enable Registers"] +pub use self::gicd_isenabler::GICD_ISENABLER; +#[doc = r"Cluster"] +#[doc = "Interrupt Set-Enable Registers"] +pub mod gicd_isenabler; +#[doc = "Interrupt Clear-Enable Registers"] +pub use self::gicd_icenabler::GICD_ICENABLER; +#[doc = r"Cluster"] +#[doc = "Interrupt Clear-Enable Registers"] +pub mod gicd_icenabler; +#[doc = "Interrupt Set-Pending Registers"] +pub use self::gicd_ispendr::GICD_ISPENDR; +#[doc = r"Cluster"] +#[doc = "Interrupt Set-Pending Registers"] +pub mod gicd_ispendr; +#[doc = "Interrupt Clear-Pending Registers"] +pub use self::gicd_icpendr::GICD_ICPENDR; +#[doc = r"Cluster"] +#[doc = "Interrupt Clear-Pending Registers"] +pub mod gicd_icpendr; +#[doc = "Interrupt Set-Active Registers"] +pub use self::gicd_isactiver::GICD_ISACTIVER; +#[doc = r"Cluster"] +#[doc = "Interrupt Set-Active Registers"] +pub mod gicd_isactiver; +#[doc = "Interrupt Clear-Active Registers"] +pub use self::gicd_icactiver::GICD_ICACTIVER; +#[doc = r"Cluster"] +#[doc = "Interrupt Clear-Active Registers"] +pub mod gicd_icactiver; +#[doc = "Interrupt Priority"] +pub use self::gicd_ipriorityr::GICD_IPRIORITYR; +#[doc = r"Cluster"] +#[doc = "Interrupt Priority"] +pub mod gicd_ipriorityr; +#[doc = "Interrupt Processor Targets"] +pub use self::gicd_itargetsr::GICD_ITARGETSR; +#[doc = r"Cluster"] +#[doc = "Interrupt Processor Targets"] +pub mod gicd_itargetsr; +#[doc = "Interrupt Configuration"] +pub use self::gicd_icfgr::GICD_ICFGR; +#[doc = r"Cluster"] +#[doc = "Interrupt Configuration"] +pub mod gicd_icfgr; +#[doc = "GICD_PPISR (rw) register accessor: an alias for `Reg`"] +pub type GICD_PPISR = crate::Reg; +#[doc = "Private Peripheral Interrupt Status Register"] +pub mod gicd_ppisr; +#[doc = "GICD_SPISR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPISR0 = crate::Reg; +#[doc = "Shared Peripheral Interrupt Status Registers"] +pub mod gicd_spisr0; +#[doc = "GICD_SPISR1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPISR1 = crate::Reg; +#[doc = "Shared Peripheral Interrupt Status Registers"] +pub mod gicd_spisr1; +#[doc = "GICD_SPISR2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPISR2 = crate::Reg; +#[doc = "Shared Peripheral Interrupt Status Registers"] +pub mod gicd_spisr2; +#[doc = "GICD_SPISR3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPISR3 = crate::Reg; +#[doc = "Shared Peripheral Interrupt Status Registers"] +pub mod gicd_spisr3; +#[doc = "GICD_SPISR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPISR4 = crate::Reg; +#[doc = "Shared Peripheral Interrupt Status Registers"] +pub mod gicd_spisr4; +#[doc = "GICD_SPISR5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPISR5 = crate::Reg; +#[doc = "Shared Peripheral Interrupt Status Registers"] +pub mod gicd_spisr5; +#[doc = "GICD_SGIR (w) register accessor: an alias for `Reg`"] +pub type GICD_SGIR = crate::Reg; +#[doc = "Software Generated Interrupt Register"] +pub mod gicd_sgir; +#[doc = "GICD_CPENDSGIRn (rw) register accessor: an alias for `Reg`"] +pub type GICD_CPENDSGIRN = crate::Reg; +#[doc = "SGI Clear-Pending Registers"] +pub mod gicd_cpendsgirn; +#[doc = "GICD_SPENDSGIRn (rw) register accessor: an alias for `Reg`"] +pub type GICD_SPENDSGIRN = crate::Reg; +#[doc = "SGI Set-Pending Registers"] +pub mod gicd_spendsgirn; +#[doc = "GICD_PIDR4 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR4 = crate::Reg; +#[doc = "Peripheral ID 4"] +pub mod gicd_pidr4; +#[doc = "GICD_PIDR5 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR5 = crate::Reg; +#[doc = "Peripheral ID 5"] +pub mod gicd_pidr5; +#[doc = "GICD_PIDR6 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR6 = crate::Reg; +#[doc = "Peripheral ID 6"] +pub mod gicd_pidr6; +#[doc = "GICD_PIDR7 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR7 = crate::Reg; +#[doc = "Peripheral ID 7"] +pub mod gicd_pidr7; +#[doc = "GICD_PIDR0 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR0 = crate::Reg; +#[doc = "Peripheral ID 0"] +pub mod gicd_pidr0; +#[doc = "GICD_PIDR1 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR1 = crate::Reg; +#[doc = "Peripheral ID 1"] +pub mod gicd_pidr1; +#[doc = "GICD_PIDR2 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR2 = crate::Reg; +#[doc = "Peripheral ID 2"] +pub mod gicd_pidr2; +#[doc = "GICD_PIDR3 (r) register accessor: an alias for `Reg`"] +pub type GICD_PIDR3 = crate::Reg; +#[doc = "Peripheral ID 3"] +pub mod gicd_pidr3; +#[doc = "GICD_CIDR0 (r) register accessor: an alias for `Reg`"] +pub type GICD_CIDR0 = crate::Reg; +#[doc = "Component ID 0"] +pub mod gicd_cidr0; +#[doc = "GICD_CIDR1 (r) register accessor: an alias for `Reg`"] +pub type GICD_CIDR1 = crate::Reg; +#[doc = "Component ID 1"] +pub mod gicd_cidr1; +#[doc = "GICD_CIDR2 (r) register accessor: an alias for `Reg`"] +pub type GICD_CIDR2 = crate::Reg; +#[doc = "Component ID 2"] +pub mod gicd_cidr2; +#[doc = "GICD_CIDR3 (r) register accessor: an alias for `Reg`"] +pub type GICD_CIDR3 = crate::Reg; +#[doc = "Component ID 3"] +pub mod gicd_cidr3; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs new file mode 100644 index 0000000..3ba16b0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_CIDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_CIDR0` reader - Component ID 0"] +pub type GICD_CIDR0_R = crate::FieldReader; +#[doc = "Component ID 0\n\nValue on reset: 13"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_CIDR0_A { + #[doc = "13: Valid"] + VALID = 13, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_CIDR0_A) -> Self { + variant as _ + } +} +impl GICD_CIDR0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 13 => Some(GICD_CIDR0_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_CIDR0_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Component ID 0"] + #[inline(always)] + pub fn gicd_cidr0(&self) -> GICD_CIDR0_R { + GICD_CIDR0_R::new(self.bits) + } +} +#[doc = "Component ID 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr0](index.html) module"] +pub struct GICD_CIDR0_SPEC; +impl crate::RegisterSpec for GICD_CIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_cidr0::R](R) reader structure"] +impl crate::Readable for GICD_CIDR0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_CIDR0 to value 0x0d"] +impl crate::Resettable for GICD_CIDR0_SPEC { + const RESET_VALUE: Self::Ux = 0x0d; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs new file mode 100644 index 0000000..f1bd600 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_CIDR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_CIDR1` reader - Component ID 1"] +pub type GICD_CIDR1_R = crate::FieldReader; +#[doc = "Component ID 1\n\nValue on reset: 240"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_CIDR1_A { + #[doc = "240: Valid"] + VALID = 240, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_CIDR1_A) -> Self { + variant as _ + } +} +impl GICD_CIDR1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 240 => Some(GICD_CIDR1_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_CIDR1_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Component ID 1"] + #[inline(always)] + pub fn gicd_cidr1(&self) -> GICD_CIDR1_R { + GICD_CIDR1_R::new(self.bits) + } +} +#[doc = "Component ID 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr1](index.html) module"] +pub struct GICD_CIDR1_SPEC; +impl crate::RegisterSpec for GICD_CIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_cidr1::R](R) reader structure"] +impl crate::Readable for GICD_CIDR1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_CIDR1 to value 0xf0"] +impl crate::Resettable for GICD_CIDR1_SPEC { + const RESET_VALUE: Self::Ux = 0xf0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs new file mode 100644 index 0000000..54897e6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_CIDR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_CIDR2` reader - Component ID 2"] +pub type GICD_CIDR2_R = crate::FieldReader; +#[doc = "Component ID 2\n\nValue on reset: 5"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_CIDR2_A { + #[doc = "5: Valid"] + VALID = 5, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_CIDR2_A) -> Self { + variant as _ + } +} +impl GICD_CIDR2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 5 => Some(GICD_CIDR2_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_CIDR2_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Component ID 2"] + #[inline(always)] + pub fn gicd_cidr2(&self) -> GICD_CIDR2_R { + GICD_CIDR2_R::new(self.bits) + } +} +#[doc = "Component ID 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr2](index.html) module"] +pub struct GICD_CIDR2_SPEC; +impl crate::RegisterSpec for GICD_CIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_cidr2::R](R) reader structure"] +impl crate::Readable for GICD_CIDR2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_CIDR2 to value 0x05"] +impl crate::Resettable for GICD_CIDR2_SPEC { + const RESET_VALUE: Self::Ux = 0x05; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs new file mode 100644 index 0000000..f70dd88 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_CIDR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_CIDR3` reader - Component ID 3"] +pub type GICD_CIDR3_R = crate::FieldReader; +#[doc = "Component ID 3\n\nValue on reset: 177"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_CIDR3_A { + #[doc = "177: Valid"] + VALID = 177, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_CIDR3_A) -> Self { + variant as _ + } +} +impl GICD_CIDR3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 177 => Some(GICD_CIDR3_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_CIDR3_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Component ID 3"] + #[inline(always)] + pub fn gicd_cidr3(&self) -> GICD_CIDR3_R { + GICD_CIDR3_R::new(self.bits) + } +} +#[doc = "Component ID 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr3](index.html) module"] +pub struct GICD_CIDR3_SPEC; +impl crate::RegisterSpec for GICD_CIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_cidr3::R](R) reader structure"] +impl crate::Readable for GICD_CIDR3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_CIDR3 to value 0xb1"] +impl crate::Resettable for GICD_CIDR3_SPEC { + const RESET_VALUE: Self::Ux = 0xb1; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs new file mode 100644 index 0000000..5490c9c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GICD_CPENDSGIRn` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_CPENDSGIRn` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SGI Clear-Pending Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cpendsgirn](index.html) module"] +pub struct GICD_CPENDSGIRN_SPEC; +impl crate::RegisterSpec for GICD_CPENDSGIRN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_cpendsgirn::R](R) reader structure"] +impl crate::Readable for GICD_CPENDSGIRN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_cpendsgirn::W](W) writer structure"] +impl crate::Writable for GICD_CPENDSGIRN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_CPENDSGIRn to value 0"] +impl crate::Resettable for GICD_CPENDSGIRN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs new file mode 100644 index 0000000..b9d2e83 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `GICD_CTLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_CTLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE_GROUP0` reader - Enable group 0 interrupts"] +pub type ENABLE_GROUP0_R = crate::BitReader; +#[doc = "Field `ENABLE_GROUP0` writer - Enable group 0 interrupts"] +pub type ENABLE_GROUP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_CTLR_SPEC, bool, O>; +#[doc = "Field `ENABLE_GROUP1` reader - Enable group 1 interrupts"] +pub type ENABLE_GROUP1_R = crate::BitReader; +#[doc = "Field `ENABLE_GROUP1` writer - Enable group 1 interrupts"] +pub type ENABLE_GROUP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_CTLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable group 0 interrupts"] + #[inline(always)] + pub fn enable_group0(&self) -> ENABLE_GROUP0_R { + ENABLE_GROUP0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable group 1 interrupts"] + #[inline(always)] + pub fn enable_group1(&self) -> ENABLE_GROUP1_R { + ENABLE_GROUP1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable group 0 interrupts"] + #[inline(always)] + #[must_use] + pub fn enable_group0(&mut self) -> ENABLE_GROUP0_W<0> { + ENABLE_GROUP0_W::new(self) + } + #[doc = "Bit 1 - Enable group 1 interrupts"] + #[inline(always)] + #[must_use] + pub fn enable_group1(&mut self) -> ENABLE_GROUP1_W<1> { + ENABLE_GROUP1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Distributor Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ctlr](index.html) module"] +pub struct GICD_CTLR_SPEC; +impl crate::RegisterSpec for GICD_CTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ctlr::R](R) reader structure"] +impl crate::Readable for GICD_CTLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ctlr::W](W) writer structure"] +impl crate::Writable for GICD_CTLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_CTLR to value 0"] +impl crate::Resettable for GICD_CTLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs new file mode 100644 index 0000000..31547ed --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ICACTIVER { + #[doc = "0x00 - Interrupt Clear-Active"] + pub gicd_icactiver0: GICD_ICACTIVER0, + #[doc = "0x04 - Interrupt Clear-Active"] + pub gicd_icactiver1: GICD_ICACTIVER1, + #[doc = "0x08 - Interrupt Clear-Active"] + pub gicd_icactiver2: GICD_ICACTIVER2, + #[doc = "0x0c - Interrupt Clear-Active"] + pub gicd_icactiver3: GICD_ICACTIVER3, + #[doc = "0x10 - Interrupt Clear-Active"] + pub gicd_icactiver4: GICD_ICACTIVER4, + #[doc = "0x14 - Interrupt Clear-Active"] + pub gicd_icactiver5: GICD_ICACTIVER5, + #[doc = "0x18 - Interrupt Clear-Active"] + pub gicd_icactiver6: GICD_ICACTIVER6, +} +#[doc = "GICD_ICACTIVER0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER0 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver0; +#[doc = "GICD_ICACTIVER1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER1 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver1; +#[doc = "GICD_ICACTIVER2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER2 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver2; +#[doc = "GICD_ICACTIVER3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER3 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver3; +#[doc = "GICD_ICACTIVER4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER4 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver4; +#[doc = "GICD_ICACTIVER5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER5 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver5; +#[doc = "GICD_ICACTIVER6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICACTIVER6 = crate::Reg; +#[doc = "Interrupt Clear-Active"] +pub mod gicd_icactiver6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs new file mode 100644 index 0000000..e6ed1e9 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICACTIVER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver0](index.html) module"] +pub struct GICD_ICACTIVER0_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver0::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver0::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER0 to value 0"] +impl crate::Resettable for GICD_ICACTIVER0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs new file mode 100644 index 0000000..f5e8549 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICACTIVER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver1](index.html) module"] +pub struct GICD_ICACTIVER1_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver1::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver1::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER1 to value 0"] +impl crate::Resettable for GICD_ICACTIVER1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs new file mode 100644 index 0000000..7c0da7f --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ICACTIVER2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver2](index.html) module"] +pub struct GICD_ICACTIVER2_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver2::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver2::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER2 to value 0"] +impl crate::Resettable for GICD_ICACTIVER2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs new file mode 100644 index 0000000..d3d5939 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ICACTIVER3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver3](index.html) module"] +pub struct GICD_ICACTIVER3_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver3::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver3::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER3 to value 0"] +impl crate::Resettable for GICD_ICACTIVER3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs new file mode 100644 index 0000000..29c4093 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs @@ -0,0 +1,551 @@ +#[doc = "Register `GICD_ICACTIVER4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver4](index.html) module"] +pub struct GICD_ICACTIVER4_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver4::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver4::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER4 to value 0"] +impl crate::Resettable for GICD_ICACTIVER4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs new file mode 100644 index 0000000..ed5553e --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICACTIVER5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver5](index.html) module"] +pub struct GICD_ICACTIVER5_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver5::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver5::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER5 to value 0"] +impl crate::Resettable for GICD_ICACTIVER5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs new file mode 100644 index 0000000..98912c7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICACTIVER6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICACTIVER6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver6](index.html) module"] +pub struct GICD_ICACTIVER6_SPEC; +impl crate::RegisterSpec for GICD_ICACTIVER6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icactiver6::R](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icactiver6::W](W) writer structure"] +impl crate::Writable for GICD_ICACTIVER6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICACTIVER6 to value 0"] +impl crate::Resettable for GICD_ICACTIVER6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs new file mode 100644 index 0000000..fd334cd --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ICENABLER { + #[doc = "0x00 - Interrupt Clear-Enable"] + pub gicd_icenabler0: GICD_ICENABLER0, + #[doc = "0x04 - Interrupt Clear-Enable"] + pub gicd_icenabler1: GICD_ICENABLER1, + #[doc = "0x08 - Interrupt Clear-Enable"] + pub gicd_icenabler2: GICD_ICENABLER2, + #[doc = "0x0c - Interrupt Clear-Enable"] + pub gicd_icenabler3: GICD_ICENABLER3, + #[doc = "0x10 - Interrupt Clear-Enable"] + pub gicd_icenabler4: GICD_ICENABLER4, + #[doc = "0x14 - Interrupt Clear-Enable"] + pub gicd_icenabler5: GICD_ICENABLER5, + #[doc = "0x18 - Interrupt Clear-Enable"] + pub gicd_icenabler6: GICD_ICENABLER6, +} +#[doc = "GICD_ICENABLER0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER0 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler0; +#[doc = "GICD_ICENABLER1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER1 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler1; +#[doc = "GICD_ICENABLER2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER2 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler2; +#[doc = "GICD_ICENABLER3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER3 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler3; +#[doc = "GICD_ICENABLER4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER4 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler4; +#[doc = "GICD_ICENABLER5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER5 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler5; +#[doc = "GICD_ICENABLER6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICENABLER6 = crate::Reg; +#[doc = "Interrupt Clear-Enable"] +pub mod gicd_icenabler6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs new file mode 100644 index 0000000..1ffa08c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICENABLER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler0](index.html) module"] +pub struct GICD_ICENABLER0_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler0::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler0::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER0 to value 0"] +impl crate::Resettable for GICD_ICENABLER0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs new file mode 100644 index 0000000..d070bb5 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICENABLER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler1](index.html) module"] +pub struct GICD_ICENABLER1_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler1::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler1::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER1 to value 0"] +impl crate::Resettable for GICD_ICENABLER1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs new file mode 100644 index 0000000..3428c57 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ICENABLER2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler2](index.html) module"] +pub struct GICD_ICENABLER2_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler2::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler2::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER2 to value 0"] +impl crate::Resettable for GICD_ICENABLER2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs new file mode 100644 index 0000000..c043ac0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ICENABLER3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler3](index.html) module"] +pub struct GICD_ICENABLER3_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler3::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler3::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER3 to value 0"] +impl crate::Resettable for GICD_ICENABLER3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs new file mode 100644 index 0000000..dbcf304 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs @@ -0,0 +1,551 @@ +#[doc = "Register `GICD_ICENABLER4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler4](index.html) module"] +pub struct GICD_ICENABLER4_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler4::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler4::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER4 to value 0"] +impl crate::Resettable for GICD_ICENABLER4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs new file mode 100644 index 0000000..bcd5f42 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICENABLER5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler5](index.html) module"] +pub struct GICD_ICENABLER5_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler5::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler5::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER5 to value 0"] +impl crate::Resettable for GICD_ICENABLER5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs new file mode 100644 index 0000000..89efc95 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICENABLER6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICENABLER6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler6](index.html) module"] +pub struct GICD_ICENABLER6_SPEC; +impl crate::RegisterSpec for GICD_ICENABLER6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icenabler6::R](R) reader structure"] +impl crate::Readable for GICD_ICENABLER6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icenabler6::W](W) writer structure"] +impl crate::Writable for GICD_ICENABLER6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICENABLER6 to value 0"] +impl crate::Resettable for GICD_ICENABLER6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs new file mode 100644 index 0000000..d60c5c5 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs @@ -0,0 +1,88 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ICFGR { + #[doc = "0x00 - Interrupt Configuration 0 - 15"] + pub gicd_icfgr0: GICD_ICFGR0, + #[doc = "0x04 - Interrupt Configuration 16 - 31"] + pub gicd_icfgr4: GICD_ICFGR4, + #[doc = "0x08 - Interrupt Configuration 32 - 47"] + pub gicd_icfgr8: GICD_ICFGR8, + #[doc = "0x0c - Interrupt Configuration 48 - 63"] + pub gicd_icfgr12: GICD_ICFGR12, + #[doc = "0x10 - Interrupt Configuration 64 - 79"] + pub gicd_icfgr16: GICD_ICFGR16, + #[doc = "0x14 - Interrupt Configuration 80 - 95"] + pub gicd_icfgr20: GICD_ICFGR20, + #[doc = "0x18 - Interrupt Configuration 96 - 111"] + pub gicd_icfgr24: GICD_ICFGR24, + #[doc = "0x1c - Interrupt Configuration 112 - 127"] + pub gicd_icfgr28: GICD_ICFGR28, + #[doc = "0x20 - Interrupt Configuration 128 - 143"] + pub gicd_icfgr32: GICD_ICFGR32, + #[doc = "0x24 - Interrupt Configuration 144 - 159"] + pub gicd_icfgr36: GICD_ICFGR36, + #[doc = "0x28 - Interrupt Configuration 160 - 175"] + pub gicd_icfgr40: GICD_ICFGR40, + #[doc = "0x2c - Interrupt Configuration 176 - 191"] + pub gicd_icfgr44: GICD_ICFGR44, + #[doc = "0x30 - Interrupt Configuration 192 - 207"] + pub gicd_icfgr48: GICD_ICFGR48, + #[doc = "0x34 - Interrupt Configuration 208 - 223"] + pub gicd_icfgr52: GICD_ICFGR52, +} +#[doc = "GICD_ICFGR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR0 = crate::Reg; +#[doc = "Interrupt Configuration 0 - 15"] +pub mod gicd_icfgr0; +#[doc = "GICD_ICFGR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR4 = crate::Reg; +#[doc = "Interrupt Configuration 16 - 31"] +pub mod gicd_icfgr4; +#[doc = "GICD_ICFGR8 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR8 = crate::Reg; +#[doc = "Interrupt Configuration 32 - 47"] +pub mod gicd_icfgr8; +#[doc = "GICD_ICFGR12 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR12 = crate::Reg; +#[doc = "Interrupt Configuration 48 - 63"] +pub mod gicd_icfgr12; +#[doc = "GICD_ICFGR16 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR16 = crate::Reg; +#[doc = "Interrupt Configuration 64 - 79"] +pub mod gicd_icfgr16; +#[doc = "GICD_ICFGR20 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR20 = crate::Reg; +#[doc = "Interrupt Configuration 80 - 95"] +pub mod gicd_icfgr20; +#[doc = "GICD_ICFGR24 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR24 = crate::Reg; +#[doc = "Interrupt Configuration 96 - 111"] +pub mod gicd_icfgr24; +#[doc = "GICD_ICFGR28 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR28 = crate::Reg; +#[doc = "Interrupt Configuration 112 - 127"] +pub mod gicd_icfgr28; +#[doc = "GICD_ICFGR32 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR32 = crate::Reg; +#[doc = "Interrupt Configuration 128 - 143"] +pub mod gicd_icfgr32; +#[doc = "GICD_ICFGR36 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR36 = crate::Reg; +#[doc = "Interrupt Configuration 144 - 159"] +pub mod gicd_icfgr36; +#[doc = "GICD_ICFGR40 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR40 = crate::Reg; +#[doc = "Interrupt Configuration 160 - 175"] +pub mod gicd_icfgr40; +#[doc = "GICD_ICFGR44 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR44 = crate::Reg; +#[doc = "Interrupt Configuration 176 - 191"] +pub mod gicd_icfgr44; +#[doc = "GICD_ICFGR48 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR48 = crate::Reg; +#[doc = "Interrupt Configuration 192 - 207"] +pub mod gicd_icfgr48; +#[doc = "GICD_ICFGR52 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICFGR52 = crate::Reg; +#[doc = "Interrupt Configuration 208 - 223"] +pub mod gicd_icfgr52; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs new file mode 100644 index 0000000..4603c16 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Interrupt 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT0_A) -> Self { + variant as u8 != 0 + } +} +impl INT0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT0_A { + match self.bits { + false => INT0_A::LEVEL, + true => INT0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT0_A::EDGE + } +} +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT0_A, O>; +impl<'a, const O: u8> INT0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT0_A::EDGE) + } +} +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Interrupt 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT1_A) -> Self { + variant as u8 != 0 + } +} +impl INT1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT1_A { + match self.bits { + false => INT1_A::LEVEL, + true => INT1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT1_A::EDGE + } +} +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT1_A, O>; +impl<'a, const O: u8> INT1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT1_A::EDGE) + } +} +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Interrupt 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT2_A) -> Self { + variant as u8 != 0 + } +} +impl INT2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT2_A { + match self.bits { + false => INT2_A::LEVEL, + true => INT2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT2_A::EDGE + } +} +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT2_A, O>; +impl<'a, const O: u8> INT2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT2_A::EDGE) + } +} +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Interrupt 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT3_A) -> Self { + variant as u8 != 0 + } +} +impl INT3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT3_A { + match self.bits { + false => INT3_A::LEVEL, + true => INT3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT3_A::EDGE + } +} +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT3_A, O>; +impl<'a, const O: u8> INT3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT3_A::EDGE) + } +} +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Interrupt 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT4_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT4_A) -> Self { + variant as u8 != 0 + } +} +impl INT4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT4_A { + match self.bits { + false => INT4_A::LEVEL, + true => INT4_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT4_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT4_A::EDGE + } +} +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT4_A, O>; +impl<'a, const O: u8> INT4_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT4_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT4_A::EDGE) + } +} +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Interrupt 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT5_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT5_A) -> Self { + variant as u8 != 0 + } +} +impl INT5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT5_A { + match self.bits { + false => INT5_A::LEVEL, + true => INT5_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT5_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT5_A::EDGE + } +} +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT5_A, O>; +impl<'a, const O: u8> INT5_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT5_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT5_A::EDGE) + } +} +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Interrupt 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT6_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT6_A) -> Self { + variant as u8 != 0 + } +} +impl INT6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT6_A { + match self.bits { + false => INT6_A::LEVEL, + true => INT6_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT6_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT6_A::EDGE + } +} +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT6_A, O>; +impl<'a, const O: u8> INT6_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT6_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT6_A::EDGE) + } +} +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Interrupt 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT7_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT7_A) -> Self { + variant as u8 != 0 + } +} +impl INT7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT7_A { + match self.bits { + false => INT7_A::LEVEL, + true => INT7_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT7_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT7_A::EDGE + } +} +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT7_A, O>; +impl<'a, const O: u8> INT7_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT7_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT7_A::EDGE) + } +} +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Interrupt 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT8_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT8_A) -> Self { + variant as u8 != 0 + } +} +impl INT8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT8_A { + match self.bits { + false => INT8_A::LEVEL, + true => INT8_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT8_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT8_A::EDGE + } +} +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT8_A, O>; +impl<'a, const O: u8> INT8_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT8_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT8_A::EDGE) + } +} +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Interrupt 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT9_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT9_A) -> Self { + variant as u8 != 0 + } +} +impl INT9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT9_A { + match self.bits { + false => INT9_A::LEVEL, + true => INT9_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT9_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT9_A::EDGE + } +} +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT9_A, O>; +impl<'a, const O: u8> INT9_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT9_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT9_A::EDGE) + } +} +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Interrupt 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT10_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT10_A) -> Self { + variant as u8 != 0 + } +} +impl INT10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT10_A { + match self.bits { + false => INT10_A::LEVEL, + true => INT10_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT10_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT10_A::EDGE + } +} +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT10_A, O>; +impl<'a, const O: u8> INT10_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT10_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT10_A::EDGE) + } +} +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Interrupt 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT11_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT11_A) -> Self { + variant as u8 != 0 + } +} +impl INT11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT11_A { + match self.bits { + false => INT11_A::LEVEL, + true => INT11_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT11_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT11_A::EDGE + } +} +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT11_A, O>; +impl<'a, const O: u8> INT11_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT11_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT11_A::EDGE) + } +} +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Interrupt 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT12_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT12_A) -> Self { + variant as u8 != 0 + } +} +impl INT12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT12_A { + match self.bits { + false => INT12_A::LEVEL, + true => INT12_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT12_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT12_A::EDGE + } +} +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT12_A, O>; +impl<'a, const O: u8> INT12_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT12_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT12_A::EDGE) + } +} +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Interrupt 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT13_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT13_A) -> Self { + variant as u8 != 0 + } +} +impl INT13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT13_A { + match self.bits { + false => INT13_A::LEVEL, + true => INT13_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT13_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT13_A::EDGE + } +} +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT13_A, O>; +impl<'a, const O: u8> INT13_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT13_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT13_A::EDGE) + } +} +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Interrupt 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT14_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT14_A) -> Self { + variant as u8 != 0 + } +} +impl INT14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT14_A { + match self.bits { + false => INT14_A::LEVEL, + true => INT14_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT14_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT14_A::EDGE + } +} +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT14_A, O>; +impl<'a, const O: u8> INT14_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT14_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT14_A::EDGE) + } +} +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Interrupt 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT15_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT15_A) -> Self { + variant as u8 != 0 + } +} +impl INT15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT15_A { + match self.bits { + false => INT15_A::LEVEL, + true => INT15_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT15_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT15_A::EDGE + } +} +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT15_A, O>; +impl<'a, const O: u8> INT15_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT15_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT15_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<1> { + INT0_W::new(self) + } + #[doc = "Bit 3 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<3> { + INT1_W::new(self) + } + #[doc = "Bit 5 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<5> { + INT2_W::new(self) + } + #[doc = "Bit 7 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<7> { + INT3_W::new(self) + } + #[doc = "Bit 9 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<9> { + INT4_W::new(self) + } + #[doc = "Bit 11 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<11> { + INT5_W::new(self) + } + #[doc = "Bit 13 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<13> { + INT6_W::new(self) + } + #[doc = "Bit 15 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<15> { + INT7_W::new(self) + } + #[doc = "Bit 17 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<17> { + INT8_W::new(self) + } + #[doc = "Bit 19 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<19> { + INT9_W::new(self) + } + #[doc = "Bit 21 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<21> { + INT10_W::new(self) + } + #[doc = "Bit 23 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<23> { + INT11_W::new(self) + } + #[doc = "Bit 25 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<25> { + INT12_W::new(self) + } + #[doc = "Bit 27 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<27> { + INT13_W::new(self) + } + #[doc = "Bit 29 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<29> { + INT14_W::new(self) + } + #[doc = "Bit 31 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<31> { + INT15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 0 - 15\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr0](index.html) module"] +pub struct GICD_ICFGR0_SPEC; +impl crate::RegisterSpec for GICD_ICFGR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr0::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr0::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR0 to value 0"] +impl crate::Resettable for GICD_ICFGR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs new file mode 100644 index 0000000..7cdc4e5 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Interrupt 48\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT48_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT48_A) -> Self { + variant as u8 != 0 + } +} +impl INT48_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT48_A { + match self.bits { + false => INT48_A::LEVEL, + true => INT48_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT48_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT48_A::EDGE + } +} +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT48_A, O>; +impl<'a, const O: u8> INT48_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT48_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT48_A::EDGE) + } +} +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Interrupt 49\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT49_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT49_A) -> Self { + variant as u8 != 0 + } +} +impl INT49_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT49_A { + match self.bits { + false => INT49_A::LEVEL, + true => INT49_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT49_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT49_A::EDGE + } +} +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT49_A, O>; +impl<'a, const O: u8> INT49_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT49_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT49_A::EDGE) + } +} +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Interrupt 50\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT50_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT50_A) -> Self { + variant as u8 != 0 + } +} +impl INT50_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT50_A { + match self.bits { + false => INT50_A::LEVEL, + true => INT50_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT50_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT50_A::EDGE + } +} +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT50_A, O>; +impl<'a, const O: u8> INT50_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT50_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT50_A::EDGE) + } +} +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Interrupt 51\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT51_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT51_A) -> Self { + variant as u8 != 0 + } +} +impl INT51_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT51_A { + match self.bits { + false => INT51_A::LEVEL, + true => INT51_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT51_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT51_A::EDGE + } +} +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT51_A, O>; +impl<'a, const O: u8> INT51_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT51_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT51_A::EDGE) + } +} +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Interrupt 52\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT52_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT52_A) -> Self { + variant as u8 != 0 + } +} +impl INT52_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT52_A { + match self.bits { + false => INT52_A::LEVEL, + true => INT52_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT52_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT52_A::EDGE + } +} +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT52_A, O>; +impl<'a, const O: u8> INT52_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT52_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT52_A::EDGE) + } +} +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Interrupt 53\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT53_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT53_A) -> Self { + variant as u8 != 0 + } +} +impl INT53_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT53_A { + match self.bits { + false => INT53_A::LEVEL, + true => INT53_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT53_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT53_A::EDGE + } +} +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT53_A, O>; +impl<'a, const O: u8> INT53_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT53_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT53_A::EDGE) + } +} +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Interrupt 54\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT54_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT54_A) -> Self { + variant as u8 != 0 + } +} +impl INT54_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT54_A { + match self.bits { + false => INT54_A::LEVEL, + true => INT54_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT54_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT54_A::EDGE + } +} +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT54_A, O>; +impl<'a, const O: u8> INT54_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT54_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT54_A::EDGE) + } +} +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Interrupt 55\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT55_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT55_A) -> Self { + variant as u8 != 0 + } +} +impl INT55_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT55_A { + match self.bits { + false => INT55_A::LEVEL, + true => INT55_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT55_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT55_A::EDGE + } +} +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT55_A, O>; +impl<'a, const O: u8> INT55_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT55_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT55_A::EDGE) + } +} +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Interrupt 56\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT56_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT56_A) -> Self { + variant as u8 != 0 + } +} +impl INT56_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT56_A { + match self.bits { + false => INT56_A::LEVEL, + true => INT56_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT56_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT56_A::EDGE + } +} +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT56_A, O>; +impl<'a, const O: u8> INT56_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT56_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT56_A::EDGE) + } +} +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Interrupt 57\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT57_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT57_A) -> Self { + variant as u8 != 0 + } +} +impl INT57_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT57_A { + match self.bits { + false => INT57_A::LEVEL, + true => INT57_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT57_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT57_A::EDGE + } +} +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT57_A, O>; +impl<'a, const O: u8> INT57_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT57_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT57_A::EDGE) + } +} +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Interrupt 58\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT58_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT58_A) -> Self { + variant as u8 != 0 + } +} +impl INT58_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT58_A { + match self.bits { + false => INT58_A::LEVEL, + true => INT58_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT58_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT58_A::EDGE + } +} +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT58_A, O>; +impl<'a, const O: u8> INT58_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT58_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT58_A::EDGE) + } +} +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Interrupt 59\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT59_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT59_A) -> Self { + variant as u8 != 0 + } +} +impl INT59_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT59_A { + match self.bits { + false => INT59_A::LEVEL, + true => INT59_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT59_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT59_A::EDGE + } +} +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT59_A, O>; +impl<'a, const O: u8> INT59_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT59_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT59_A::EDGE) + } +} +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Interrupt 60\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT60_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT60_A) -> Self { + variant as u8 != 0 + } +} +impl INT60_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT60_A { + match self.bits { + false => INT60_A::LEVEL, + true => INT60_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT60_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT60_A::EDGE + } +} +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT60_A, O>; +impl<'a, const O: u8> INT60_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT60_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT60_A::EDGE) + } +} +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Interrupt 61\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT61_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT61_A) -> Self { + variant as u8 != 0 + } +} +impl INT61_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT61_A { + match self.bits { + false => INT61_A::LEVEL, + true => INT61_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT61_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT61_A::EDGE + } +} +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT61_A, O>; +impl<'a, const O: u8> INT61_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT61_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT61_A::EDGE) + } +} +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Interrupt 62\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT62_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT62_A) -> Self { + variant as u8 != 0 + } +} +impl INT62_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT62_A { + match self.bits { + false => INT62_A::LEVEL, + true => INT62_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT62_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT62_A::EDGE + } +} +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT62_A, O>; +impl<'a, const O: u8> INT62_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT62_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT62_A::EDGE) + } +} +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Interrupt 63\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT63_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT63_A) -> Self { + variant as u8 != 0 + } +} +impl INT63_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT63_A { + match self.bits { + false => INT63_A::LEVEL, + true => INT63_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT63_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT63_A::EDGE + } +} +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT63_A, O>; +impl<'a, const O: u8> INT63_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT63_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT63_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<1> { + INT48_W::new(self) + } + #[doc = "Bit 3 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<3> { + INT49_W::new(self) + } + #[doc = "Bit 5 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<5> { + INT50_W::new(self) + } + #[doc = "Bit 7 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<7> { + INT51_W::new(self) + } + #[doc = "Bit 9 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<9> { + INT52_W::new(self) + } + #[doc = "Bit 11 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<11> { + INT53_W::new(self) + } + #[doc = "Bit 13 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<13> { + INT54_W::new(self) + } + #[doc = "Bit 15 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<15> { + INT55_W::new(self) + } + #[doc = "Bit 17 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<17> { + INT56_W::new(self) + } + #[doc = "Bit 19 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<19> { + INT57_W::new(self) + } + #[doc = "Bit 21 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<21> { + INT58_W::new(self) + } + #[doc = "Bit 23 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<23> { + INT59_W::new(self) + } + #[doc = "Bit 25 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<25> { + INT60_W::new(self) + } + #[doc = "Bit 27 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<27> { + INT61_W::new(self) + } + #[doc = "Bit 29 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<29> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 48 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr12](index.html) module"] +pub struct GICD_ICFGR12_SPEC; +impl crate::RegisterSpec for GICD_ICFGR12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr12::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr12::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR12_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR12 to value 0"] +impl crate::Resettable for GICD_ICFGR12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs new file mode 100644 index 0000000..0131fb6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs @@ -0,0 +1,1047 @@ +#[doc = "Register `GICD_ICFGR16` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR16` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "ARMC Timer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TIMER_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMER_A) -> Self { + variant as u8 != 0 + } +} +impl TIMER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMER_A { + match self.bits { + false => TIMER_A::LEVEL, + true => TIMER_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == TIMER_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == TIMER_A::EDGE + } +} +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, TIMER_A, O>; +impl<'a, const O: u8> TIMER_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(TIMER_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(TIMER_A::EDGE) + } +} +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Mailbox\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MAILBOX_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MAILBOX_A) -> Self { + variant as u8 != 0 + } +} +impl MAILBOX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MAILBOX_A { + match self.bits { + false => MAILBOX_A::LEVEL, + true => MAILBOX_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MAILBOX_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MAILBOX_A::EDGE + } +} +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, MAILBOX_A, O>; +impl<'a, const O: u8> MAILBOX_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(MAILBOX_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(MAILBOX_A::EDGE) + } +} +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Doorbell 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DOORBELL0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DOORBELL0_A) -> Self { + variant as u8 != 0 + } +} +impl DOORBELL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOORBELL0_A { + match self.bits { + false => DOORBELL0_A::LEVEL, + true => DOORBELL0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DOORBELL0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DOORBELL0_A::EDGE + } +} +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, DOORBELL0_A, O>; +impl<'a, const O: u8> DOORBELL0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DOORBELL0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DOORBELL0_A::EDGE) + } +} +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Doorbell 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DOORBELL1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DOORBELL1_A) -> Self { + variant as u8 != 0 + } +} +impl DOORBELL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOORBELL1_A { + match self.bits { + false => DOORBELL1_A::LEVEL, + true => DOORBELL1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DOORBELL1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DOORBELL1_A::EDGE + } +} +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, DOORBELL1_A, O>; +impl<'a, const O: u8> DOORBELL1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DOORBELL1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DOORBELL1_A::EDGE) + } +} +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "VPU0 halted\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VPU0_HALTED_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VPU0_HALTED_A) -> Self { + variant as u8 != 0 + } +} +impl VPU0_HALTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> VPU0_HALTED_A { + match self.bits { + false => VPU0_HALTED_A::LEVEL, + true => VPU0_HALTED_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == VPU0_HALTED_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == VPU0_HALTED_A::EDGE + } +} +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, VPU0_HALTED_A, O>; +impl<'a, const O: u8> VPU0_HALTED_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(VPU0_HALTED_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(VPU0_HALTED_A::EDGE) + } +} +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "VPU1 halted\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VPU1_HALTED_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VPU1_HALTED_A) -> Self { + variant as u8 != 0 + } +} +impl VPU1_HALTED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> VPU1_HALTED_A { + match self.bits { + false => VPU1_HALTED_A::LEVEL, + true => VPU1_HALTED_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == VPU1_HALTED_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == VPU1_HALTED_A::EDGE + } +} +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, VPU1_HALTED_A, O>; +impl<'a, const O: u8> VPU1_HALTED_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(VPU1_HALTED_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(VPU1_HALTED_A::EDGE) + } +} +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "ARM address error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ARM_ADDRESS_ERROR_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARM_ADDRESS_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ARM_ADDRESS_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARM_ADDRESS_ERROR_A { + match self.bits { + false => ARM_ADDRESS_ERROR_A::LEVEL, + true => ARM_ADDRESS_ERROR_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == ARM_ADDRESS_ERROR_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == ARM_ADDRESS_ERROR_A::EDGE + } +} +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, ARM_ADDRESS_ERROR_A, O>; +impl<'a, const O: u8> ARM_ADDRESS_ERROR_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(ARM_ADDRESS_ERROR_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(ARM_ADDRESS_ERROR_A::EDGE) + } +} +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "ARM AXI error\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ARM_AXI_ERROR_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARM_AXI_ERROR_A) -> Self { + variant as u8 != 0 + } +} +impl ARM_AXI_ERROR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARM_AXI_ERROR_A { + match self.bits { + false => ARM_AXI_ERROR_A::LEVEL, + true => ARM_AXI_ERROR_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == ARM_AXI_ERROR_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == ARM_AXI_ERROR_A::EDGE + } +} +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, ARM_AXI_ERROR_A, O>; +impl<'a, const O: u8> ARM_AXI_ERROR_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(ARM_AXI_ERROR_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(ARM_AXI_ERROR_A::EDGE) + } +} +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Software interrupt 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI0_A) -> Self { + variant as u8 != 0 + } +} +impl SWI0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI0_A { + match self.bits { + false => SWI0_A::LEVEL, + true => SWI0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI0_A::EDGE + } +} +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI0_A, O>; +impl<'a, const O: u8> SWI0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI0_A::EDGE) + } +} +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Software interrupt 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI1_A) -> Self { + variant as u8 != 0 + } +} +impl SWI1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI1_A { + match self.bits { + false => SWI1_A::LEVEL, + true => SWI1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI1_A::EDGE + } +} +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI1_A, O>; +impl<'a, const O: u8> SWI1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI1_A::EDGE) + } +} +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Software interrupt 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI2_A) -> Self { + variant as u8 != 0 + } +} +impl SWI2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI2_A { + match self.bits { + false => SWI2_A::LEVEL, + true => SWI2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI2_A::EDGE + } +} +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI2_A, O>; +impl<'a, const O: u8> SWI2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI2_A::EDGE) + } +} +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Software interrupt 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI3_A) -> Self { + variant as u8 != 0 + } +} +impl SWI3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI3_A { + match self.bits { + false => SWI3_A::LEVEL, + true => SWI3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI3_A::EDGE + } +} +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI3_A, O>; +impl<'a, const O: u8> SWI3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI3_A::EDGE) + } +} +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Software interrupt 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI4_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI4_A) -> Self { + variant as u8 != 0 + } +} +impl SWI4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI4_A { + match self.bits { + false => SWI4_A::LEVEL, + true => SWI4_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI4_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI4_A::EDGE + } +} +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI4_A, O>; +impl<'a, const O: u8> SWI4_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI4_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI4_A::EDGE) + } +} +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Software interrupt 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI5_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI5_A) -> Self { + variant as u8 != 0 + } +} +impl SWI5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI5_A { + match self.bits { + false => SWI5_A::LEVEL, + true => SWI5_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI5_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI5_A::EDGE + } +} +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI5_A, O>; +impl<'a, const O: u8> SWI5_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI5_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI5_A::EDGE) + } +} +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Software interrupt 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI6_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI6_A) -> Self { + variant as u8 != 0 + } +} +impl SWI6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI6_A { + match self.bits { + false => SWI6_A::LEVEL, + true => SWI6_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI6_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI6_A::EDGE + } +} +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI6_A, O>; +impl<'a, const O: u8> SWI6_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI6_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI6_A::EDGE) + } +} +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Software interrupt 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SWI7_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SWI7_A) -> Self { + variant as u8 != 0 + } +} +impl SWI7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SWI7_A { + match self.bits { + false => SWI7_A::LEVEL, + true => SWI7_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SWI7_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SWI7_A::EDGE + } +} +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI7_A, O>; +impl<'a, const O: u8> SWI7_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SWI7_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SWI7_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<1> { + TIMER_W::new(self) + } + #[doc = "Bit 3 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<3> { + MAILBOX_W::new(self) + } + #[doc = "Bit 5 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<5> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 7 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<7> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 9 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<9> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 11 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<11> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 13 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<13> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 15 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<15> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 17 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<17> { + SWI0_W::new(self) + } + #[doc = "Bit 19 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<19> { + SWI1_W::new(self) + } + #[doc = "Bit 21 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<21> { + SWI2_W::new(self) + } + #[doc = "Bit 23 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<23> { + SWI3_W::new(self) + } + #[doc = "Bit 25 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<25> { + SWI4_W::new(self) + } + #[doc = "Bit 27 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<27> { + SWI5_W::new(self) + } + #[doc = "Bit 29 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<29> { + SWI6_W::new(self) + } + #[doc = "Bit 31 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<31> { + SWI7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 64 - 79\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr16](index.html) module"] +pub struct GICD_ICFGR16_SPEC; +impl crate::RegisterSpec for GICD_ICFGR16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr16::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR16_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr16::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR16_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR16 to value 0"] +impl crate::Resettable for GICD_ICFGR16_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs new file mode 100644 index 0000000..6cb9587 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR20` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR20` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Interrupt 80\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT80_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT80_A) -> Self { + variant as u8 != 0 + } +} +impl INT80_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT80_A { + match self.bits { + false => INT80_A::LEVEL, + true => INT80_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT80_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT80_A::EDGE + } +} +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT80_A, O>; +impl<'a, const O: u8> INT80_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT80_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT80_A::EDGE) + } +} +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Interrupt 81\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT81_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT81_A) -> Self { + variant as u8 != 0 + } +} +impl INT81_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT81_A { + match self.bits { + false => INT81_A::LEVEL, + true => INT81_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT81_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT81_A::EDGE + } +} +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT81_A, O>; +impl<'a, const O: u8> INT81_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT81_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT81_A::EDGE) + } +} +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Interrupt 82\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT82_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT82_A) -> Self { + variant as u8 != 0 + } +} +impl INT82_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT82_A { + match self.bits { + false => INT82_A::LEVEL, + true => INT82_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT82_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT82_A::EDGE + } +} +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT82_A, O>; +impl<'a, const O: u8> INT82_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT82_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT82_A::EDGE) + } +} +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Interrupt 83\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT83_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT83_A) -> Self { + variant as u8 != 0 + } +} +impl INT83_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT83_A { + match self.bits { + false => INT83_A::LEVEL, + true => INT83_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT83_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT83_A::EDGE + } +} +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT83_A, O>; +impl<'a, const O: u8> INT83_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT83_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT83_A::EDGE) + } +} +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Interrupt 84\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT84_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT84_A) -> Self { + variant as u8 != 0 + } +} +impl INT84_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT84_A { + match self.bits { + false => INT84_A::LEVEL, + true => INT84_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT84_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT84_A::EDGE + } +} +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT84_A, O>; +impl<'a, const O: u8> INT84_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT84_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT84_A::EDGE) + } +} +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Interrupt 85\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT85_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT85_A) -> Self { + variant as u8 != 0 + } +} +impl INT85_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT85_A { + match self.bits { + false => INT85_A::LEVEL, + true => INT85_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT85_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT85_A::EDGE + } +} +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT85_A, O>; +impl<'a, const O: u8> INT85_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT85_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT85_A::EDGE) + } +} +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Interrupt 86\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT86_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT86_A) -> Self { + variant as u8 != 0 + } +} +impl INT86_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT86_A { + match self.bits { + false => INT86_A::LEVEL, + true => INT86_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT86_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT86_A::EDGE + } +} +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT86_A, O>; +impl<'a, const O: u8> INT86_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT86_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT86_A::EDGE) + } +} +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Interrupt 87\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT87_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT87_A) -> Self { + variant as u8 != 0 + } +} +impl INT87_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT87_A { + match self.bits { + false => INT87_A::LEVEL, + true => INT87_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT87_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT87_A::EDGE + } +} +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT87_A, O>; +impl<'a, const O: u8> INT87_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT87_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT87_A::EDGE) + } +} +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Interrupt 88\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT88_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT88_A) -> Self { + variant as u8 != 0 + } +} +impl INT88_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT88_A { + match self.bits { + false => INT88_A::LEVEL, + true => INT88_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT88_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT88_A::EDGE + } +} +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT88_A, O>; +impl<'a, const O: u8> INT88_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT88_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT88_A::EDGE) + } +} +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Interrupt 89\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT89_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT89_A) -> Self { + variant as u8 != 0 + } +} +impl INT89_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT89_A { + match self.bits { + false => INT89_A::LEVEL, + true => INT89_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT89_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT89_A::EDGE + } +} +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT89_A, O>; +impl<'a, const O: u8> INT89_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT89_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT89_A::EDGE) + } +} +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Interrupt 90\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT90_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT90_A) -> Self { + variant as u8 != 0 + } +} +impl INT90_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT90_A { + match self.bits { + false => INT90_A::LEVEL, + true => INT90_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT90_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT90_A::EDGE + } +} +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT90_A, O>; +impl<'a, const O: u8> INT90_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT90_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT90_A::EDGE) + } +} +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Interrupt 91\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT91_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT91_A) -> Self { + variant as u8 != 0 + } +} +impl INT91_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT91_A { + match self.bits { + false => INT91_A::LEVEL, + true => INT91_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT91_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT91_A::EDGE + } +} +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT91_A, O>; +impl<'a, const O: u8> INT91_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT91_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT91_A::EDGE) + } +} +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Interrupt 92\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT92_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT92_A) -> Self { + variant as u8 != 0 + } +} +impl INT92_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT92_A { + match self.bits { + false => INT92_A::LEVEL, + true => INT92_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT92_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT92_A::EDGE + } +} +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT92_A, O>; +impl<'a, const O: u8> INT92_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT92_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT92_A::EDGE) + } +} +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Interrupt 93\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT93_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT93_A) -> Self { + variant as u8 != 0 + } +} +impl INT93_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT93_A { + match self.bits { + false => INT93_A::LEVEL, + true => INT93_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT93_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT93_A::EDGE + } +} +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT93_A, O>; +impl<'a, const O: u8> INT93_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT93_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT93_A::EDGE) + } +} +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Interrupt 94\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT94_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT94_A) -> Self { + variant as u8 != 0 + } +} +impl INT94_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT94_A { + match self.bits { + false => INT94_A::LEVEL, + true => INT94_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT94_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT94_A::EDGE + } +} +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT94_A, O>; +impl<'a, const O: u8> INT94_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT94_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT94_A::EDGE) + } +} +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Interrupt 95\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT95_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT95_A) -> Self { + variant as u8 != 0 + } +} +impl INT95_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT95_A { + match self.bits { + false => INT95_A::LEVEL, + true => INT95_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT95_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT95_A::EDGE + } +} +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT95_A, O>; +impl<'a, const O: u8> INT95_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT95_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT95_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<1> { + INT80_W::new(self) + } + #[doc = "Bit 3 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<3> { + INT81_W::new(self) + } + #[doc = "Bit 5 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<5> { + INT82_W::new(self) + } + #[doc = "Bit 7 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<7> { + INT83_W::new(self) + } + #[doc = "Bit 9 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<9> { + INT84_W::new(self) + } + #[doc = "Bit 11 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<11> { + INT85_W::new(self) + } + #[doc = "Bit 13 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<13> { + INT86_W::new(self) + } + #[doc = "Bit 15 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<15> { + INT87_W::new(self) + } + #[doc = "Bit 17 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<17> { + INT88_W::new(self) + } + #[doc = "Bit 19 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<19> { + INT89_W::new(self) + } + #[doc = "Bit 21 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<21> { + INT90_W::new(self) + } + #[doc = "Bit 23 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<23> { + INT91_W::new(self) + } + #[doc = "Bit 25 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<25> { + INT92_W::new(self) + } + #[doc = "Bit 27 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<27> { + INT93_W::new(self) + } + #[doc = "Bit 29 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<29> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 80 - 95\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr20](index.html) module"] +pub struct GICD_ICFGR20_SPEC; +impl crate::RegisterSpec for GICD_ICFGR20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr20::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR20_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr20::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR20_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR20 to value 0"] +impl crate::Resettable for GICD_ICFGR20_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs new file mode 100644 index 0000000..c06d1ba --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs @@ -0,0 +1,1046 @@ +#[doc = "Register `GICD_ICFGR24` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR24` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Timer 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TIMER_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMER_0_A) -> Self { + variant as u8 != 0 + } +} +impl TIMER_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMER_0_A { + match self.bits { + false => TIMER_0_A::LEVEL, + true => TIMER_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == TIMER_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == TIMER_0_A::EDGE + } +} +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_0_A, O>; +impl<'a, const O: u8> TIMER_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(TIMER_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(TIMER_0_A::EDGE) + } +} +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Timer 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TIMER_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMER_1_A) -> Self { + variant as u8 != 0 + } +} +impl TIMER_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMER_1_A { + match self.bits { + false => TIMER_1_A::LEVEL, + true => TIMER_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == TIMER_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == TIMER_1_A::EDGE + } +} +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_1_A, O>; +impl<'a, const O: u8> TIMER_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(TIMER_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(TIMER_1_A::EDGE) + } +} +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Timer 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TIMER_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMER_2_A) -> Self { + variant as u8 != 0 + } +} +impl TIMER_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMER_2_A { + match self.bits { + false => TIMER_2_A::LEVEL, + true => TIMER_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == TIMER_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == TIMER_2_A::EDGE + } +} +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_2_A, O>; +impl<'a, const O: u8> TIMER_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(TIMER_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(TIMER_2_A::EDGE) + } +} +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Timer 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TIMER_3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TIMER_3_A) -> Self { + variant as u8 != 0 + } +} +impl TIMER_3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TIMER_3_A { + match self.bits { + false => TIMER_3_A::LEVEL, + true => TIMER_3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == TIMER_3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == TIMER_3_A::EDGE + } +} +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_3_A, O>; +impl<'a, const O: u8> TIMER_3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(TIMER_3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(TIMER_3_A::EDGE) + } +} +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "H264 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum H264_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: H264_0_A) -> Self { + variant as u8 != 0 + } +} +impl H264_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> H264_0_A { + match self.bits { + false => H264_0_A::LEVEL, + true => H264_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == H264_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == H264_0_A::EDGE + } +} +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, H264_0_A, O>; +impl<'a, const O: u8> H264_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(H264_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(H264_0_A::EDGE) + } +} +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "H264 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum H264_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: H264_1_A) -> Self { + variant as u8 != 0 + } +} +impl H264_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> H264_1_A { + match self.bits { + false => H264_1_A::LEVEL, + true => H264_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == H264_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == H264_1_A::EDGE + } +} +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, H264_1_A, O>; +impl<'a, const O: u8> H264_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(H264_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(H264_1_A::EDGE) + } +} +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "H264 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum H264_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: H264_2_A) -> Self { + variant as u8 != 0 + } +} +impl H264_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> H264_2_A { + match self.bits { + false => H264_2_A::LEVEL, + true => H264_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == H264_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == H264_2_A::EDGE + } +} +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, H264_2_A, O>; +impl<'a, const O: u8> H264_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(H264_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(H264_2_A::EDGE) + } +} +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "JPEG\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum JPEG_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: JPEG_A) -> Self { + variant as u8 != 0 + } +} +impl JPEG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> JPEG_A { + match self.bits { + false => JPEG_A::LEVEL, + true => JPEG_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == JPEG_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == JPEG_A::EDGE + } +} +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, JPEG_A, O>; +impl<'a, const O: u8> JPEG_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(JPEG_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(JPEG_A::EDGE) + } +} +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "ISP\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ISP_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ISP_A) -> Self { + variant as u8 != 0 + } +} +impl ISP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ISP_A { + match self.bits { + false => ISP_A::LEVEL, + true => ISP_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == ISP_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == ISP_A::EDGE + } +} +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, ISP_A, O>; +impl<'a, const O: u8> ISP_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(ISP_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(ISP_A::EDGE) + } +} +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "USB\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum USB_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: USB_A) -> Self { + variant as u8 != 0 + } +} +impl USB_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> USB_A { + match self.bits { + false => USB_A::LEVEL, + true => USB_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == USB_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == USB_A::EDGE + } +} +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, USB_A, O>; +impl<'a, const O: u8> USB_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(USB_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(USB_A::EDGE) + } +} +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "V3D\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum V3D_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: V3D_A) -> Self { + variant as u8 != 0 + } +} +impl V3D_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> V3D_A { + match self.bits { + false => V3D_A::LEVEL, + true => V3D_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == V3D_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == V3D_A::EDGE + } +} +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, V3D_A, O>; +impl<'a, const O: u8> V3D_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(V3D_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(V3D_A::EDGE) + } +} +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Transposer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TRANSPOSER_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TRANSPOSER_A) -> Self { + variant as u8 != 0 + } +} +impl TRANSPOSER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TRANSPOSER_A { + match self.bits { + false => TRANSPOSER_A::LEVEL, + true => TRANSPOSER_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == TRANSPOSER_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == TRANSPOSER_A::EDGE + } +} +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TRANSPOSER_A, O>; +impl<'a, const O: u8> TRANSPOSER_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(TRANSPOSER_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(TRANSPOSER_A::EDGE) + } +} +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Multicore Sync 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MULTICORE_SYNC_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MULTICORE_SYNC_0_A) -> Self { + variant as u8 != 0 + } +} +impl MULTICORE_SYNC_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MULTICORE_SYNC_0_A { + match self.bits { + false => MULTICORE_SYNC_0_A::LEVEL, + true => MULTICORE_SYNC_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MULTICORE_SYNC_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MULTICORE_SYNC_0_A::EDGE + } +} +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_0_A, O>; +impl<'a, const O: u8> MULTICORE_SYNC_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_0_A::EDGE) + } +} +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Multicore Sync 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MULTICORE_SYNC_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MULTICORE_SYNC_1_A) -> Self { + variant as u8 != 0 + } +} +impl MULTICORE_SYNC_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MULTICORE_SYNC_1_A { + match self.bits { + false => MULTICORE_SYNC_1_A::LEVEL, + true => MULTICORE_SYNC_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MULTICORE_SYNC_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MULTICORE_SYNC_1_A::EDGE + } +} +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_1_A, O>; +impl<'a, const O: u8> MULTICORE_SYNC_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_1_A::EDGE) + } +} +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Multicore Sync 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MULTICORE_SYNC_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MULTICORE_SYNC_2_A) -> Self { + variant as u8 != 0 + } +} +impl MULTICORE_SYNC_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MULTICORE_SYNC_2_A { + match self.bits { + false => MULTICORE_SYNC_2_A::LEVEL, + true => MULTICORE_SYNC_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MULTICORE_SYNC_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MULTICORE_SYNC_2_A::EDGE + } +} +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_2_A, O>; +impl<'a, const O: u8> MULTICORE_SYNC_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_2_A::EDGE) + } +} +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Multicore Sync 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MULTICORE_SYNC_3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MULTICORE_SYNC_3_A) -> Self { + variant as u8 != 0 + } +} +impl MULTICORE_SYNC_3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MULTICORE_SYNC_3_A { + match self.bits { + false => MULTICORE_SYNC_3_A::LEVEL, + true => MULTICORE_SYNC_3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MULTICORE_SYNC_3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MULTICORE_SYNC_3_A::EDGE + } +} +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_3_A, O>; +impl<'a, const O: u8> MULTICORE_SYNC_3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(MULTICORE_SYNC_3_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<1> { + TIMER_0_W::new(self) + } + #[doc = "Bit 3 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<3> { + TIMER_1_W::new(self) + } + #[doc = "Bit 5 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<5> { + TIMER_2_W::new(self) + } + #[doc = "Bit 7 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<7> { + TIMER_3_W::new(self) + } + #[doc = "Bit 9 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<9> { + H264_0_W::new(self) + } + #[doc = "Bit 11 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<11> { + H264_1_W::new(self) + } + #[doc = "Bit 13 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<13> { + H264_2_W::new(self) + } + #[doc = "Bit 15 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<15> { + JPEG_W::new(self) + } + #[doc = "Bit 17 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<17> { + ISP_W::new(self) + } + #[doc = "Bit 19 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<19> { + USB_W::new(self) + } + #[doc = "Bit 21 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<21> { + V3D_W::new(self) + } + #[doc = "Bit 23 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<23> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 25 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<25> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 27 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<27> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 29 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<29> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 31 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<31> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 96 - 111\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr24](index.html) module"] +pub struct GICD_ICFGR24_SPEC; +impl crate::RegisterSpec for GICD_ICFGR24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr24::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR24_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr24::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR24_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR24 to value 0"] +impl crate::Resettable for GICD_ICFGR24_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs new file mode 100644 index 0000000..b2f01d2 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR28` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR28` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "DMA 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_0_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_0_A { + match self.bits { + false => DMA_0_A::LEVEL, + true => DMA_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_0_A::EDGE + } +} +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_0_A, O>; +impl<'a, const O: u8> DMA_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_0_A::EDGE) + } +} +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "DMA 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_1_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_1_A { + match self.bits { + false => DMA_1_A::LEVEL, + true => DMA_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_1_A::EDGE + } +} +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_1_A, O>; +impl<'a, const O: u8> DMA_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_1_A::EDGE) + } +} +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "DMA 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_2_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_2_A { + match self.bits { + false => DMA_2_A::LEVEL, + true => DMA_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_2_A::EDGE + } +} +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_2_A, O>; +impl<'a, const O: u8> DMA_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_2_A::EDGE) + } +} +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "DMA 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_3_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_3_A { + match self.bits { + false => DMA_3_A::LEVEL, + true => DMA_3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_3_A::EDGE + } +} +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_3_A, O>; +impl<'a, const O: u8> DMA_3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_3_A::EDGE) + } +} +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "DMA 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_4_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_4_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_4_A { + match self.bits { + false => DMA_4_A::LEVEL, + true => DMA_4_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_4_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_4_A::EDGE + } +} +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_4_A, O>; +impl<'a, const O: u8> DMA_4_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_4_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_4_A::EDGE) + } +} +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "DMA 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_5_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_5_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_5_A { + match self.bits { + false => DMA_5_A::LEVEL, + true => DMA_5_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_5_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_5_A::EDGE + } +} +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_5_A, O>; +impl<'a, const O: u8> DMA_5_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_5_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_5_A::EDGE) + } +} +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "DMA 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_6_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_6_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_6_A { + match self.bits { + false => DMA_6_A::LEVEL, + true => DMA_6_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_6_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_6_A::EDGE + } +} +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_6_A, O>; +impl<'a, const O: u8> DMA_6_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_6_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_6_A::EDGE) + } +} +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "OR of DMA 7 and 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_7_8_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_7_8_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_7_8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_7_8_A { + match self.bits { + false => DMA_7_8_A::LEVEL, + true => DMA_7_8_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_7_8_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_7_8_A::EDGE + } +} +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_7_8_A, O>; +impl<'a, const O: u8> DMA_7_8_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_7_8_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_7_8_A::EDGE) + } +} +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "OR of DMA 9 and 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_9_10_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_9_10_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_9_10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_9_10_A { + match self.bits { + false => DMA_9_10_A::LEVEL, + true => DMA_9_10_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_9_10_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_9_10_A::EDGE + } +} +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_9_10_A, O>; +impl<'a, const O: u8> DMA_9_10_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_9_10_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_9_10_A::EDGE) + } +} +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "DMA 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_11_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_11_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_11_A { + match self.bits { + false => DMA_11_A::LEVEL, + true => DMA_11_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_11_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_11_A::EDGE + } +} +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_11_A, O>; +impl<'a, const O: u8> DMA_11_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_11_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_11_A::EDGE) + } +} +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "DMA 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_12_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_12_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_12_A { + match self.bits { + false => DMA_12_A::LEVEL, + true => DMA_12_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_12_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_12_A::EDGE + } +} +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_12_A, O>; +impl<'a, const O: u8> DMA_12_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_12_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_12_A::EDGE) + } +} +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "DMA 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_13_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_13_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_13_A { + match self.bits { + false => DMA_13_A::LEVEL, + true => DMA_13_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_13_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_13_A::EDGE + } +} +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_13_A, O>; +impl<'a, const O: u8> DMA_13_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_13_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_13_A::EDGE) + } +} +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "DMA 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_14_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_14_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_14_A { + match self.bits { + false => DMA_14_A::LEVEL, + true => DMA_14_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_14_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_14_A::EDGE + } +} +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_14_A, O>; +impl<'a, const O: u8> DMA_14_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_14_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_14_A::EDGE) + } +} +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "OR of UART1, SPI1 and SPI2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AUX_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AUX_A) -> Self { + variant as u8 != 0 + } +} +impl AUX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> AUX_A { + match self.bits { + false => AUX_A::LEVEL, + true => AUX_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == AUX_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == AUX_A::EDGE + } +} +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, AUX_A, O>; +impl<'a, const O: u8> AUX_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(AUX_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(AUX_A::EDGE) + } +} +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "ARM\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ARM_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARM_A) -> Self { + variant as u8 != 0 + } +} +impl ARM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARM_A { + match self.bits { + false => ARM_A::LEVEL, + true => ARM_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == ARM_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == ARM_A::EDGE + } +} +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, ARM_A, O>; +impl<'a, const O: u8> ARM_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(ARM_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(ARM_A::EDGE) + } +} +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "DMA 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DMA_15_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DMA_15_A) -> Self { + variant as u8 != 0 + } +} +impl DMA_15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMA_15_A { + match self.bits { + false => DMA_15_A::LEVEL, + true => DMA_15_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DMA_15_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DMA_15_A::EDGE + } +} +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_15_A, O>; +impl<'a, const O: u8> DMA_15_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DMA_15_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DMA_15_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<1> { + DMA_0_W::new(self) + } + #[doc = "Bit 3 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<3> { + DMA_1_W::new(self) + } + #[doc = "Bit 5 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<5> { + DMA_2_W::new(self) + } + #[doc = "Bit 7 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<7> { + DMA_3_W::new(self) + } + #[doc = "Bit 9 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<9> { + DMA_4_W::new(self) + } + #[doc = "Bit 11 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<11> { + DMA_5_W::new(self) + } + #[doc = "Bit 13 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<13> { + DMA_6_W::new(self) + } + #[doc = "Bit 15 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<15> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 17 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<17> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 19 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<19> { + DMA_11_W::new(self) + } + #[doc = "Bit 21 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<21> { + DMA_12_W::new(self) + } + #[doc = "Bit 23 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<23> { + DMA_13_W::new(self) + } + #[doc = "Bit 25 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<25> { + DMA_14_W::new(self) + } + #[doc = "Bit 27 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<27> { + AUX_W::new(self) + } + #[doc = "Bit 29 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<29> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 112 - 127\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr28](index.html) module"] +pub struct GICD_ICFGR28_SPEC; +impl crate::RegisterSpec for GICD_ICFGR28_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr28::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR28_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr28::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR28_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR28 to value 0"] +impl crate::Resettable for GICD_ICFGR28_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs new file mode 100644 index 0000000..63dbc4d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs @@ -0,0 +1,1046 @@ +#[doc = "Register `GICD_ICFGR32` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR32` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "HDMI CEC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HDMI_CEC_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HDMI_CEC_A) -> Self { + variant as u8 != 0 + } +} +impl HDMI_CEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HDMI_CEC_A { + match self.bits { + false => HDMI_CEC_A::LEVEL, + true => HDMI_CEC_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == HDMI_CEC_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == HDMI_CEC_A::EDGE + } +} +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HDMI_CEC_A, O>; +impl<'a, const O: u8> HDMI_CEC_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(HDMI_CEC_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(HDMI_CEC_A::EDGE) + } +} +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "HVS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HVS_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HVS_A) -> Self { + variant as u8 != 0 + } +} +impl HVS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HVS_A { + match self.bits { + false => HVS_A::LEVEL, + true => HVS_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == HVS_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == HVS_A::EDGE + } +} +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HVS_A, O>; +impl<'a, const O: u8> HVS_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(HVS_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(HVS_A::EDGE) + } +} +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "RPIVID\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RPIVID_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RPIVID_A) -> Self { + variant as u8 != 0 + } +} +impl RPIVID_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RPIVID_A { + match self.bits { + false => RPIVID_A::LEVEL, + true => RPIVID_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == RPIVID_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == RPIVID_A::EDGE + } +} +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, RPIVID_A, O>; +impl<'a, const O: u8> RPIVID_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(RPIVID_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(RPIVID_A::EDGE) + } +} +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "SDC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SDC_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SDC_A) -> Self { + variant as u8 != 0 + } +} +impl SDC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDC_A { + match self.bits { + false => SDC_A::LEVEL, + true => SDC_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SDC_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SDC_A::EDGE + } +} +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, SDC_A, O>; +impl<'a, const O: u8> SDC_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SDC_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SDC_A::EDGE) + } +} +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "DSI 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DSI_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DSI_0_A) -> Self { + variant as u8 != 0 + } +} +impl DSI_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DSI_0_A { + match self.bits { + false => DSI_0_A::LEVEL, + true => DSI_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DSI_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DSI_0_A::EDGE + } +} +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, DSI_0_A, O>; +impl<'a, const O: u8> DSI_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DSI_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DSI_0_A::EDGE) + } +} +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Pixel Valve 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PIXEL_VALVE_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIXEL_VALVE_2_A) -> Self { + variant as u8 != 0 + } +} +impl PIXEL_VALVE_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIXEL_VALVE_2_A { + match self.bits { + false => PIXEL_VALVE_2_A::LEVEL, + true => PIXEL_VALVE_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == PIXEL_VALVE_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == PIXEL_VALVE_2_A::EDGE + } +} +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_2_A, O>; +impl<'a, const O: u8> PIXEL_VALVE_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(PIXEL_VALVE_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(PIXEL_VALVE_2_A::EDGE) + } +} +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Camera 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CAMERA_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CAMERA_0_A) -> Self { + variant as u8 != 0 + } +} +impl CAMERA_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAMERA_0_A { + match self.bits { + false => CAMERA_0_A::LEVEL, + true => CAMERA_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == CAMERA_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == CAMERA_0_A::EDGE + } +} +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, CAMERA_0_A, O>; +impl<'a, const O: u8> CAMERA_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(CAMERA_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(CAMERA_0_A::EDGE) + } +} +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Camera 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CAMERA_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CAMERA_1_A) -> Self { + variant as u8 != 0 + } +} +impl CAMERA_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAMERA_1_A { + match self.bits { + false => CAMERA_1_A::LEVEL, + true => CAMERA_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == CAMERA_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == CAMERA_1_A::EDGE + } +} +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, CAMERA_1_A, O>; +impl<'a, const O: u8> CAMERA_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(CAMERA_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(CAMERA_1_A::EDGE) + } +} +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "HDMI 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HDMI_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HDMI_0_A) -> Self { + variant as u8 != 0 + } +} +impl HDMI_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HDMI_0_A { + match self.bits { + false => HDMI_0_A::LEVEL, + true => HDMI_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == HDMI_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == HDMI_0_A::EDGE + } +} +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HDMI_0_A, O>; +impl<'a, const O: u8> HDMI_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(HDMI_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(HDMI_0_A::EDGE) + } +} +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "HDMI 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum HDMI_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: HDMI_1_A) -> Self { + variant as u8 != 0 + } +} +impl HDMI_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HDMI_1_A { + match self.bits { + false => HDMI_1_A::LEVEL, + true => HDMI_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == HDMI_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == HDMI_1_A::EDGE + } +} +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HDMI_1_A, O>; +impl<'a, const O: u8> HDMI_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(HDMI_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(HDMI_1_A::EDGE) + } +} +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Pixel Valve 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PIXEL_VALVE_3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIXEL_VALVE_3_A) -> Self { + variant as u8 != 0 + } +} +impl PIXEL_VALVE_3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIXEL_VALVE_3_A { + match self.bits { + false => PIXEL_VALVE_3_A::LEVEL, + true => PIXEL_VALVE_3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == PIXEL_VALVE_3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == PIXEL_VALVE_3_A::EDGE + } +} +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_3_A, O>; +impl<'a, const O: u8> PIXEL_VALVE_3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(PIXEL_VALVE_3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(PIXEL_VALVE_3_A::EDGE) + } +} +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "SPI/BSC Slave\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SPI_BSC_SLAVE_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SPI_BSC_SLAVE_A) -> Self { + variant as u8 != 0 + } +} +impl SPI_BSC_SLAVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPI_BSC_SLAVE_A { + match self.bits { + false => SPI_BSC_SLAVE_A::LEVEL, + true => SPI_BSC_SLAVE_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SPI_BSC_SLAVE_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SPI_BSC_SLAVE_A::EDGE + } +} +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, SPI_BSC_SLAVE_A, O>; +impl<'a, const O: u8> SPI_BSC_SLAVE_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SPI_BSC_SLAVE_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SPI_BSC_SLAVE_A::EDGE) + } +} +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "DSI 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DSI_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DSI_1_A) -> Self { + variant as u8 != 0 + } +} +impl DSI_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DSI_1_A { + match self.bits { + false => DSI_1_A::LEVEL, + true => DSI_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DSI_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == DSI_1_A::EDGE + } +} +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, DSI_1_A, O>; +impl<'a, const O: u8> DSI_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(DSI_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(DSI_1_A::EDGE) + } +} +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Pixel Valve 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PIXEL_VALVE_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIXEL_VALVE_0_A) -> Self { + variant as u8 != 0 + } +} +impl PIXEL_VALVE_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIXEL_VALVE_0_A { + match self.bits { + false => PIXEL_VALVE_0_A::LEVEL, + true => PIXEL_VALVE_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == PIXEL_VALVE_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == PIXEL_VALVE_0_A::EDGE + } +} +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_0_A, O>; +impl<'a, const O: u8> PIXEL_VALVE_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(PIXEL_VALVE_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(PIXEL_VALVE_0_A::EDGE) + } +} +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "OR of Pixel Valve 1 and 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PIXEL_VALVE_1_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PIXEL_VALVE_1_2_A) -> Self { + variant as u8 != 0 + } +} +impl PIXEL_VALVE_1_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PIXEL_VALVE_1_2_A { + match self.bits { + false => PIXEL_VALVE_1_2_A::LEVEL, + true => PIXEL_VALVE_1_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == PIXEL_VALVE_1_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == PIXEL_VALVE_1_2_A::EDGE + } +} +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_1_2_A, O>; +impl<'a, const O: u8> PIXEL_VALVE_1_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(PIXEL_VALVE_1_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(PIXEL_VALVE_1_2_A::EDGE) + } +} +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "CPR\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CPR_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPR_A) -> Self { + variant as u8 != 0 + } +} +impl CPR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPR_A { + match self.bits { + false => CPR_A::LEVEL, + true => CPR_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == CPR_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == CPR_A::EDGE + } +} +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, CPR_A, O>; +impl<'a, const O: u8> CPR_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(CPR_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(CPR_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<1> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 3 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<3> { + HVS_W::new(self) + } + #[doc = "Bit 5 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<5> { + RPIVID_W::new(self) + } + #[doc = "Bit 7 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<7> { + SDC_W::new(self) + } + #[doc = "Bit 9 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<9> { + DSI_0_W::new(self) + } + #[doc = "Bit 11 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<11> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 13 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<13> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 15 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<15> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 17 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<17> { + HDMI_0_W::new(self) + } + #[doc = "Bit 19 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<19> { + HDMI_1_W::new(self) + } + #[doc = "Bit 21 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<21> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 23 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<23> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 25 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<25> { + DSI_1_W::new(self) + } + #[doc = "Bit 27 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<27> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 29 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<29> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 31 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<31> { + CPR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 128 - 143\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr32](index.html) module"] +pub struct GICD_ICFGR32_SPEC; +impl crate::RegisterSpec for GICD_ICFGR32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr32::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR32_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr32::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR32_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR32 to value 0"] +impl crate::Resettable for GICD_ICFGR32_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs new file mode 100644 index 0000000..bc05ab7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs @@ -0,0 +1,1042 @@ +#[doc = "Register `GICD_ICFGR36` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR36` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "SMI\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SMI_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SMI_A) -> Self { + variant as u8 != 0 + } +} +impl SMI_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SMI_A { + match self.bits { + false => SMI_A::LEVEL, + true => SMI_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SMI_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SMI_A::EDGE + } +} +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, SMI_A, O>; +impl<'a, const O: u8> SMI_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SMI_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SMI_A::EDGE) + } +} +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "GPIO 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GPIO_0_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GPIO_0_A) -> Self { + variant as u8 != 0 + } +} +impl GPIO_0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> GPIO_0_A { + match self.bits { + false => GPIO_0_A::LEVEL, + true => GPIO_0_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == GPIO_0_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == GPIO_0_A::EDGE + } +} +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_0_A, O>; +impl<'a, const O: u8> GPIO_0_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(GPIO_0_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(GPIO_0_A::EDGE) + } +} +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "GPIO 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GPIO_1_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GPIO_1_A) -> Self { + variant as u8 != 0 + } +} +impl GPIO_1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> GPIO_1_A { + match self.bits { + false => GPIO_1_A::LEVEL, + true => GPIO_1_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == GPIO_1_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == GPIO_1_A::EDGE + } +} +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_1_A, O>; +impl<'a, const O: u8> GPIO_1_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(GPIO_1_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(GPIO_1_A::EDGE) + } +} +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "GPIO 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GPIO_2_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GPIO_2_A) -> Self { + variant as u8 != 0 + } +} +impl GPIO_2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> GPIO_2_A { + match self.bits { + false => GPIO_2_A::LEVEL, + true => GPIO_2_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == GPIO_2_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == GPIO_2_A::EDGE + } +} +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_2_A, O>; +impl<'a, const O: u8> GPIO_2_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(GPIO_2_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(GPIO_2_A::EDGE) + } +} +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "GPIO 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GPIO_3_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GPIO_3_A) -> Self { + variant as u8 != 0 + } +} +impl GPIO_3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> GPIO_3_A { + match self.bits { + false => GPIO_3_A::LEVEL, + true => GPIO_3_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == GPIO_3_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == GPIO_3_A::EDGE + } +} +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_3_A, O>; +impl<'a, const O: u8> GPIO_3_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(GPIO_3_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(GPIO_3_A::EDGE) + } +} +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "OR of all I2C\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I2C_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I2C_A) -> Self { + variant as u8 != 0 + } +} +impl I2C_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> I2C_A { + match self.bits { + false => I2C_A::LEVEL, + true => I2C_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == I2C_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == I2C_A::EDGE + } +} +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, I2C_A, O>; +impl<'a, const O: u8> I2C_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(I2C_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(I2C_A::EDGE) + } +} +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "OR of all SPI\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SPI_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SPI_A) -> Self { + variant as u8 != 0 + } +} +impl SPI_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPI_A { + match self.bits { + false => SPI_A::LEVEL, + true => SPI_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SPI_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SPI_A::EDGE + } +} +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, SPI_A, O>; +impl<'a, const O: u8> SPI_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SPI_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SPI_A::EDGE) + } +} +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "PCM/I2S\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PCM_I2S_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PCM_I2S_A) -> Self { + variant as u8 != 0 + } +} +impl PCM_I2S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PCM_I2S_A { + match self.bits { + false => PCM_I2S_A::LEVEL, + true => PCM_I2S_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == PCM_I2S_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == PCM_I2S_A::EDGE + } +} +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, PCM_I2S_A, O>; +impl<'a, const O: u8> PCM_I2S_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(PCM_I2S_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(PCM_I2S_A::EDGE) + } +} +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "SDHOST\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SDHOST_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SDHOST_A) -> Self { + variant as u8 != 0 + } +} +impl SDHOST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDHOST_A { + match self.bits { + false => SDHOST_A::LEVEL, + true => SDHOST_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == SDHOST_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == SDHOST_A::EDGE + } +} +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, SDHOST_A, O>; +impl<'a, const O: u8> SDHOST_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(SDHOST_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(SDHOST_A::EDGE) + } +} +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "OR of all PL011 UARTs\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum UART_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UART_A) -> Self { + variant as u8 != 0 + } +} +impl UART_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UART_A { + match self.bits { + false => UART_A::LEVEL, + true => UART_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == UART_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == UART_A::EDGE + } +} +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, UART_A, O>; +impl<'a, const O: u8> UART_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(UART_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(UART_A::EDGE) + } +} +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "OR of all ETH_PCIe L2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ETH_PCIE_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ETH_PCIE_A) -> Self { + variant as u8 != 0 + } +} +impl ETH_PCIE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ETH_PCIE_A { + match self.bits { + false => ETH_PCIE_A::LEVEL, + true => ETH_PCIE_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == ETH_PCIE_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == ETH_PCIE_A::EDGE + } +} +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, ETH_PCIE_A, O>; +impl<'a, const O: u8> ETH_PCIE_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(ETH_PCIE_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(ETH_PCIE_A::EDGE) + } +} +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "VEC\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VEC_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VEC_A) -> Self { + variant as u8 != 0 + } +} +impl VEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> VEC_A { + match self.bits { + false => VEC_A::LEVEL, + true => VEC_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == VEC_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == VEC_A::EDGE + } +} +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, VEC_A, O>; +impl<'a, const O: u8> VEC_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(VEC_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(VEC_A::EDGE) + } +} +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "CPG\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CPG_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPG_A) -> Self { + variant as u8 != 0 + } +} +impl CPG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPG_A { + match self.bits { + false => CPG_A::LEVEL, + true => CPG_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == CPG_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == CPG_A::EDGE + } +} +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, CPG_A, O>; +impl<'a, const O: u8> CPG_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(CPG_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(CPG_A::EDGE) + } +} +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "RNG\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RNG_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RNG_A) -> Self { + variant as u8 != 0 + } +} +impl RNG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RNG_A { + match self.bits { + false => RNG_A::LEVEL, + true => RNG_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == RNG_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == RNG_A::EDGE + } +} +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, RNG_A, O>; +impl<'a, const O: u8> RNG_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(RNG_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(RNG_A::EDGE) + } +} +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "OR of EMMC and EMMC2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EMMC_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EMMC_A) -> Self { + variant as u8 != 0 + } +} +impl EMMC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EMMC_A { + match self.bits { + false => EMMC_A::LEVEL, + true => EMMC_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == EMMC_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == EMMC_A::EDGE + } +} +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, EMMC_A, O>; +impl<'a, const O: u8> EMMC_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(EMMC_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(EMMC_A::EDGE) + } +} +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "ETH_PCIe secure\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ETH_PCIE_SECURE_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ETH_PCIE_SECURE_A) -> Self { + variant as u8 != 0 + } +} +impl ETH_PCIE_SECURE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ETH_PCIE_SECURE_A { + match self.bits { + false => ETH_PCIE_SECURE_A::LEVEL, + true => ETH_PCIE_SECURE_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == ETH_PCIE_SECURE_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == ETH_PCIE_SECURE_A::EDGE + } +} +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, ETH_PCIE_SECURE_A, O>; +impl<'a, const O: u8> ETH_PCIE_SECURE_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(ETH_PCIE_SECURE_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(ETH_PCIE_SECURE_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<1> { + SMI_W::new(self) + } + #[doc = "Bit 3 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<3> { + GPIO_0_W::new(self) + } + #[doc = "Bit 5 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<5> { + GPIO_1_W::new(self) + } + #[doc = "Bit 7 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<7> { + GPIO_2_W::new(self) + } + #[doc = "Bit 9 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<9> { + GPIO_3_W::new(self) + } + #[doc = "Bit 11 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<11> { + I2C_W::new(self) + } + #[doc = "Bit 13 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<13> { + SPI_W::new(self) + } + #[doc = "Bit 15 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<15> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 17 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<17> { + SDHOST_W::new(self) + } + #[doc = "Bit 19 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<19> { + UART_W::new(self) + } + #[doc = "Bit 21 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<21> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 23 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<23> { + VEC_W::new(self) + } + #[doc = "Bit 25 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<25> { + CPG_W::new(self) + } + #[doc = "Bit 27 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<27> { + RNG_W::new(self) + } + #[doc = "Bit 29 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<29> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 144 - 159\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr36](index.html) module"] +pub struct GICD_ICFGR36_SPEC; +impl crate::RegisterSpec for GICD_ICFGR36_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr36::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR36_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr36::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR36_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR36 to value 0"] +impl crate::Resettable for GICD_ICFGR36_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs new file mode 100644 index 0000000..f2835e9 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Interrupt 16\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT16_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT16_A) -> Self { + variant as u8 != 0 + } +} +impl INT16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT16_A { + match self.bits { + false => INT16_A::LEVEL, + true => INT16_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT16_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT16_A::EDGE + } +} +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT16_A, O>; +impl<'a, const O: u8> INT16_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT16_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT16_A::EDGE) + } +} +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Interrupt 17\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT17_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT17_A) -> Self { + variant as u8 != 0 + } +} +impl INT17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT17_A { + match self.bits { + false => INT17_A::LEVEL, + true => INT17_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT17_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT17_A::EDGE + } +} +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT17_A, O>; +impl<'a, const O: u8> INT17_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT17_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT17_A::EDGE) + } +} +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Interrupt 18\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT18_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT18_A) -> Self { + variant as u8 != 0 + } +} +impl INT18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT18_A { + match self.bits { + false => INT18_A::LEVEL, + true => INT18_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT18_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT18_A::EDGE + } +} +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT18_A, O>; +impl<'a, const O: u8> INT18_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT18_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT18_A::EDGE) + } +} +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Interrupt 19\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT19_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT19_A) -> Self { + variant as u8 != 0 + } +} +impl INT19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT19_A { + match self.bits { + false => INT19_A::LEVEL, + true => INT19_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT19_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT19_A::EDGE + } +} +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT19_A, O>; +impl<'a, const O: u8> INT19_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT19_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT19_A::EDGE) + } +} +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Interrupt 20\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT20_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT20_A) -> Self { + variant as u8 != 0 + } +} +impl INT20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT20_A { + match self.bits { + false => INT20_A::LEVEL, + true => INT20_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT20_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT20_A::EDGE + } +} +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT20_A, O>; +impl<'a, const O: u8> INT20_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT20_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT20_A::EDGE) + } +} +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Interrupt 21\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT21_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT21_A) -> Self { + variant as u8 != 0 + } +} +impl INT21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT21_A { + match self.bits { + false => INT21_A::LEVEL, + true => INT21_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT21_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT21_A::EDGE + } +} +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT21_A, O>; +impl<'a, const O: u8> INT21_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT21_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT21_A::EDGE) + } +} +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Interrupt 22\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT22_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT22_A) -> Self { + variant as u8 != 0 + } +} +impl INT22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT22_A { + match self.bits { + false => INT22_A::LEVEL, + true => INT22_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT22_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT22_A::EDGE + } +} +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT22_A, O>; +impl<'a, const O: u8> INT22_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT22_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT22_A::EDGE) + } +} +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Interrupt 23\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT23_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT23_A) -> Self { + variant as u8 != 0 + } +} +impl INT23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT23_A { + match self.bits { + false => INT23_A::LEVEL, + true => INT23_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT23_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT23_A::EDGE + } +} +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT23_A, O>; +impl<'a, const O: u8> INT23_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT23_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT23_A::EDGE) + } +} +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Interrupt 24\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT24_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT24_A) -> Self { + variant as u8 != 0 + } +} +impl INT24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT24_A { + match self.bits { + false => INT24_A::LEVEL, + true => INT24_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT24_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT24_A::EDGE + } +} +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT24_A, O>; +impl<'a, const O: u8> INT24_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT24_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT24_A::EDGE) + } +} +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Interrupt 25\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT25_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT25_A) -> Self { + variant as u8 != 0 + } +} +impl INT25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT25_A { + match self.bits { + false => INT25_A::LEVEL, + true => INT25_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT25_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT25_A::EDGE + } +} +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT25_A, O>; +impl<'a, const O: u8> INT25_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT25_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT25_A::EDGE) + } +} +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Interrupt 26\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT26_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT26_A) -> Self { + variant as u8 != 0 + } +} +impl INT26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT26_A { + match self.bits { + false => INT26_A::LEVEL, + true => INT26_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT26_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT26_A::EDGE + } +} +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT26_A, O>; +impl<'a, const O: u8> INT26_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT26_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT26_A::EDGE) + } +} +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Interrupt 27\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT27_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT27_A) -> Self { + variant as u8 != 0 + } +} +impl INT27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT27_A { + match self.bits { + false => INT27_A::LEVEL, + true => INT27_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT27_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT27_A::EDGE + } +} +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT27_A, O>; +impl<'a, const O: u8> INT27_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT27_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT27_A::EDGE) + } +} +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Interrupt 28\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT28_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT28_A) -> Self { + variant as u8 != 0 + } +} +impl INT28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT28_A { + match self.bits { + false => INT28_A::LEVEL, + true => INT28_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT28_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT28_A::EDGE + } +} +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT28_A, O>; +impl<'a, const O: u8> INT28_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT28_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT28_A::EDGE) + } +} +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Interrupt 29\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT29_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT29_A) -> Self { + variant as u8 != 0 + } +} +impl INT29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT29_A { + match self.bits { + false => INT29_A::LEVEL, + true => INT29_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT29_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT29_A::EDGE + } +} +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT29_A, O>; +impl<'a, const O: u8> INT29_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT29_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT29_A::EDGE) + } +} +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Interrupt 30\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT30_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT30_A) -> Self { + variant as u8 != 0 + } +} +impl INT30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT30_A { + match self.bits { + false => INT30_A::LEVEL, + true => INT30_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT30_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT30_A::EDGE + } +} +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT30_A, O>; +impl<'a, const O: u8> INT30_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT30_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT30_A::EDGE) + } +} +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Interrupt 31\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT31_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT31_A) -> Self { + variant as u8 != 0 + } +} +impl INT31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT31_A { + match self.bits { + false => INT31_A::LEVEL, + true => INT31_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT31_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT31_A::EDGE + } +} +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT31_A, O>; +impl<'a, const O: u8> INT31_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT31_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT31_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<1> { + INT16_W::new(self) + } + #[doc = "Bit 3 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<3> { + INT17_W::new(self) + } + #[doc = "Bit 5 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<5> { + INT18_W::new(self) + } + #[doc = "Bit 7 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<7> { + INT19_W::new(self) + } + #[doc = "Bit 9 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<9> { + INT20_W::new(self) + } + #[doc = "Bit 11 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<11> { + INT21_W::new(self) + } + #[doc = "Bit 13 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<13> { + INT22_W::new(self) + } + #[doc = "Bit 15 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<15> { + INT23_W::new(self) + } + #[doc = "Bit 17 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<17> { + INT24_W::new(self) + } + #[doc = "Bit 19 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<19> { + INT25_W::new(self) + } + #[doc = "Bit 21 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<21> { + INT26_W::new(self) + } + #[doc = "Bit 23 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<23> { + INT27_W::new(self) + } + #[doc = "Bit 25 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<25> { + INT28_W::new(self) + } + #[doc = "Bit 27 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<27> { + INT29_W::new(self) + } + #[doc = "Bit 29 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<29> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 16 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr4](index.html) module"] +pub struct GICD_ICFGR4_SPEC; +impl crate::RegisterSpec for GICD_ICFGR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr4::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr4::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR4 to value 0"] +impl crate::Resettable for GICD_ICFGR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs new file mode 100644 index 0000000..3bda818 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR40` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR40` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Interrupt 160\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT160_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT160_A) -> Self { + variant as u8 != 0 + } +} +impl INT160_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT160_A { + match self.bits { + false => INT160_A::LEVEL, + true => INT160_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT160_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT160_A::EDGE + } +} +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT160_A, O>; +impl<'a, const O: u8> INT160_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT160_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT160_A::EDGE) + } +} +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Interrupt 161\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT161_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT161_A) -> Self { + variant as u8 != 0 + } +} +impl INT161_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT161_A { + match self.bits { + false => INT161_A::LEVEL, + true => INT161_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT161_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT161_A::EDGE + } +} +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT161_A, O>; +impl<'a, const O: u8> INT161_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT161_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT161_A::EDGE) + } +} +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Interrupt 162\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT162_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT162_A) -> Self { + variant as u8 != 0 + } +} +impl INT162_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT162_A { + match self.bits { + false => INT162_A::LEVEL, + true => INT162_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT162_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT162_A::EDGE + } +} +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT162_A, O>; +impl<'a, const O: u8> INT162_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT162_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT162_A::EDGE) + } +} +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Interrupt 163\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT163_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT163_A) -> Self { + variant as u8 != 0 + } +} +impl INT163_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT163_A { + match self.bits { + false => INT163_A::LEVEL, + true => INT163_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT163_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT163_A::EDGE + } +} +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT163_A, O>; +impl<'a, const O: u8> INT163_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT163_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT163_A::EDGE) + } +} +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Interrupt 164\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT164_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT164_A) -> Self { + variant as u8 != 0 + } +} +impl INT164_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT164_A { + match self.bits { + false => INT164_A::LEVEL, + true => INT164_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT164_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT164_A::EDGE + } +} +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT164_A, O>; +impl<'a, const O: u8> INT164_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT164_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT164_A::EDGE) + } +} +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Interrupt 165\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT165_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT165_A) -> Self { + variant as u8 != 0 + } +} +impl INT165_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT165_A { + match self.bits { + false => INT165_A::LEVEL, + true => INT165_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT165_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT165_A::EDGE + } +} +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT165_A, O>; +impl<'a, const O: u8> INT165_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT165_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT165_A::EDGE) + } +} +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Interrupt 166\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT166_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT166_A) -> Self { + variant as u8 != 0 + } +} +impl INT166_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT166_A { + match self.bits { + false => INT166_A::LEVEL, + true => INT166_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT166_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT166_A::EDGE + } +} +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT166_A, O>; +impl<'a, const O: u8> INT166_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT166_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT166_A::EDGE) + } +} +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Interrupt 167\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT167_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT167_A) -> Self { + variant as u8 != 0 + } +} +impl INT167_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT167_A { + match self.bits { + false => INT167_A::LEVEL, + true => INT167_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT167_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT167_A::EDGE + } +} +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT167_A, O>; +impl<'a, const O: u8> INT167_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT167_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT167_A::EDGE) + } +} +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Interrupt 168\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT168_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT168_A) -> Self { + variant as u8 != 0 + } +} +impl INT168_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT168_A { + match self.bits { + false => INT168_A::LEVEL, + true => INT168_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT168_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT168_A::EDGE + } +} +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT168_A, O>; +impl<'a, const O: u8> INT168_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT168_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT168_A::EDGE) + } +} +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Interrupt 169\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT169_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT169_A) -> Self { + variant as u8 != 0 + } +} +impl INT169_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT169_A { + match self.bits { + false => INT169_A::LEVEL, + true => INT169_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT169_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT169_A::EDGE + } +} +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT169_A, O>; +impl<'a, const O: u8> INT169_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT169_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT169_A::EDGE) + } +} +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Interrupt 170\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT170_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT170_A) -> Self { + variant as u8 != 0 + } +} +impl INT170_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT170_A { + match self.bits { + false => INT170_A::LEVEL, + true => INT170_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT170_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT170_A::EDGE + } +} +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT170_A, O>; +impl<'a, const O: u8> INT170_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT170_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT170_A::EDGE) + } +} +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Interrupt 171\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT171_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT171_A) -> Self { + variant as u8 != 0 + } +} +impl INT171_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT171_A { + match self.bits { + false => INT171_A::LEVEL, + true => INT171_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT171_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT171_A::EDGE + } +} +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT171_A, O>; +impl<'a, const O: u8> INT171_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT171_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT171_A::EDGE) + } +} +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Interrupt 172\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT172_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT172_A) -> Self { + variant as u8 != 0 + } +} +impl INT172_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT172_A { + match self.bits { + false => INT172_A::LEVEL, + true => INT172_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT172_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT172_A::EDGE + } +} +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT172_A, O>; +impl<'a, const O: u8> INT172_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT172_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT172_A::EDGE) + } +} +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Interrupt 173\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT173_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT173_A) -> Self { + variant as u8 != 0 + } +} +impl INT173_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT173_A { + match self.bits { + false => INT173_A::LEVEL, + true => INT173_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT173_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT173_A::EDGE + } +} +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT173_A, O>; +impl<'a, const O: u8> INT173_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT173_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT173_A::EDGE) + } +} +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Interrupt 174\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT174_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT174_A) -> Self { + variant as u8 != 0 + } +} +impl INT174_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT174_A { + match self.bits { + false => INT174_A::LEVEL, + true => INT174_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT174_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT174_A::EDGE + } +} +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT174_A, O>; +impl<'a, const O: u8> INT174_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT174_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT174_A::EDGE) + } +} +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Interrupt 175\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT175_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT175_A) -> Self { + variant as u8 != 0 + } +} +impl INT175_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT175_A { + match self.bits { + false => INT175_A::LEVEL, + true => INT175_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT175_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT175_A::EDGE + } +} +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT175_A, O>; +impl<'a, const O: u8> INT175_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT175_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT175_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<1> { + INT160_W::new(self) + } + #[doc = "Bit 3 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<3> { + INT161_W::new(self) + } + #[doc = "Bit 5 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<5> { + INT162_W::new(self) + } + #[doc = "Bit 7 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<7> { + INT163_W::new(self) + } + #[doc = "Bit 9 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<9> { + INT164_W::new(self) + } + #[doc = "Bit 11 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<11> { + INT165_W::new(self) + } + #[doc = "Bit 13 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<13> { + INT166_W::new(self) + } + #[doc = "Bit 15 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<15> { + INT167_W::new(self) + } + #[doc = "Bit 17 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<17> { + INT168_W::new(self) + } + #[doc = "Bit 19 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<19> { + INT169_W::new(self) + } + #[doc = "Bit 21 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<21> { + INT170_W::new(self) + } + #[doc = "Bit 23 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<23> { + INT171_W::new(self) + } + #[doc = "Bit 25 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<25> { + INT172_W::new(self) + } + #[doc = "Bit 27 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<27> { + INT173_W::new(self) + } + #[doc = "Bit 29 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<29> { + INT174_W::new(self) + } + #[doc = "Bit 31 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<31> { + INT175_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 160 - 175\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr40](index.html) module"] +pub struct GICD_ICFGR40_SPEC; +impl crate::RegisterSpec for GICD_ICFGR40_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr40::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR40_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr40::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR40_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR40 to value 0"] +impl crate::Resettable for GICD_ICFGR40_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs new file mode 100644 index 0000000..9411024 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR44` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR44` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Interrupt 176\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT176_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT176_A) -> Self { + variant as u8 != 0 + } +} +impl INT176_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT176_A { + match self.bits { + false => INT176_A::LEVEL, + true => INT176_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT176_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT176_A::EDGE + } +} +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT176_A, O>; +impl<'a, const O: u8> INT176_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT176_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT176_A::EDGE) + } +} +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Interrupt 177\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT177_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT177_A) -> Self { + variant as u8 != 0 + } +} +impl INT177_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT177_A { + match self.bits { + false => INT177_A::LEVEL, + true => INT177_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT177_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT177_A::EDGE + } +} +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT177_A, O>; +impl<'a, const O: u8> INT177_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT177_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT177_A::EDGE) + } +} +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Interrupt 178\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT178_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT178_A) -> Self { + variant as u8 != 0 + } +} +impl INT178_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT178_A { + match self.bits { + false => INT178_A::LEVEL, + true => INT178_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT178_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT178_A::EDGE + } +} +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT178_A, O>; +impl<'a, const O: u8> INT178_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT178_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT178_A::EDGE) + } +} +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Interrupt 179\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT179_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT179_A) -> Self { + variant as u8 != 0 + } +} +impl INT179_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT179_A { + match self.bits { + false => INT179_A::LEVEL, + true => INT179_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT179_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT179_A::EDGE + } +} +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT179_A, O>; +impl<'a, const O: u8> INT179_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT179_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT179_A::EDGE) + } +} +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Interrupt 180\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT180_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT180_A) -> Self { + variant as u8 != 0 + } +} +impl INT180_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT180_A { + match self.bits { + false => INT180_A::LEVEL, + true => INT180_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT180_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT180_A::EDGE + } +} +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT180_A, O>; +impl<'a, const O: u8> INT180_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT180_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT180_A::EDGE) + } +} +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Interrupt 181\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT181_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT181_A) -> Self { + variant as u8 != 0 + } +} +impl INT181_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT181_A { + match self.bits { + false => INT181_A::LEVEL, + true => INT181_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT181_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT181_A::EDGE + } +} +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT181_A, O>; +impl<'a, const O: u8> INT181_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT181_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT181_A::EDGE) + } +} +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Interrupt 182\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT182_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT182_A) -> Self { + variant as u8 != 0 + } +} +impl INT182_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT182_A { + match self.bits { + false => INT182_A::LEVEL, + true => INT182_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT182_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT182_A::EDGE + } +} +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT182_A, O>; +impl<'a, const O: u8> INT182_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT182_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT182_A::EDGE) + } +} +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Interrupt 183\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT183_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT183_A) -> Self { + variant as u8 != 0 + } +} +impl INT183_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT183_A { + match self.bits { + false => INT183_A::LEVEL, + true => INT183_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT183_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT183_A::EDGE + } +} +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT183_A, O>; +impl<'a, const O: u8> INT183_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT183_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT183_A::EDGE) + } +} +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Interrupt 184\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT184_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT184_A) -> Self { + variant as u8 != 0 + } +} +impl INT184_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT184_A { + match self.bits { + false => INT184_A::LEVEL, + true => INT184_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT184_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT184_A::EDGE + } +} +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT184_A, O>; +impl<'a, const O: u8> INT184_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT184_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT184_A::EDGE) + } +} +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Interrupt 185\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT185_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT185_A) -> Self { + variant as u8 != 0 + } +} +impl INT185_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT185_A { + match self.bits { + false => INT185_A::LEVEL, + true => INT185_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT185_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT185_A::EDGE + } +} +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT185_A, O>; +impl<'a, const O: u8> INT185_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT185_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT185_A::EDGE) + } +} +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Interrupt 186\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT186_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT186_A) -> Self { + variant as u8 != 0 + } +} +impl INT186_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT186_A { + match self.bits { + false => INT186_A::LEVEL, + true => INT186_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT186_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT186_A::EDGE + } +} +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT186_A, O>; +impl<'a, const O: u8> INT186_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT186_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT186_A::EDGE) + } +} +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Interrupt 187\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT187_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT187_A) -> Self { + variant as u8 != 0 + } +} +impl INT187_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT187_A { + match self.bits { + false => INT187_A::LEVEL, + true => INT187_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT187_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT187_A::EDGE + } +} +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT187_A, O>; +impl<'a, const O: u8> INT187_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT187_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT187_A::EDGE) + } +} +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Interrupt 188\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT188_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT188_A) -> Self { + variant as u8 != 0 + } +} +impl INT188_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT188_A { + match self.bits { + false => INT188_A::LEVEL, + true => INT188_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT188_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT188_A::EDGE + } +} +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT188_A, O>; +impl<'a, const O: u8> INT188_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT188_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT188_A::EDGE) + } +} +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Interrupt 189\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT189_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT189_A) -> Self { + variant as u8 != 0 + } +} +impl INT189_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT189_A { + match self.bits { + false => INT189_A::LEVEL, + true => INT189_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT189_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT189_A::EDGE + } +} +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT189_A, O>; +impl<'a, const O: u8> INT189_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT189_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT189_A::EDGE) + } +} +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Interrupt 190\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT190_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT190_A) -> Self { + variant as u8 != 0 + } +} +impl INT190_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT190_A { + match self.bits { + false => INT190_A::LEVEL, + true => INT190_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT190_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT190_A::EDGE + } +} +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT190_A, O>; +impl<'a, const O: u8> INT190_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT190_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT190_A::EDGE) + } +} +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Interrupt 191\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT191_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT191_A) -> Self { + variant as u8 != 0 + } +} +impl INT191_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT191_A { + match self.bits { + false => INT191_A::LEVEL, + true => INT191_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT191_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT191_A::EDGE + } +} +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT191_A, O>; +impl<'a, const O: u8> INT191_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT191_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT191_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<1> { + INT176_W::new(self) + } + #[doc = "Bit 3 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<3> { + INT177_W::new(self) + } + #[doc = "Bit 5 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<5> { + INT178_W::new(self) + } + #[doc = "Bit 7 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<7> { + INT179_W::new(self) + } + #[doc = "Bit 9 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<9> { + INT180_W::new(self) + } + #[doc = "Bit 11 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<11> { + INT181_W::new(self) + } + #[doc = "Bit 13 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<13> { + INT182_W::new(self) + } + #[doc = "Bit 15 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<15> { + INT183_W::new(self) + } + #[doc = "Bit 17 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<17> { + INT184_W::new(self) + } + #[doc = "Bit 19 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<19> { + INT185_W::new(self) + } + #[doc = "Bit 21 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<21> { + INT186_W::new(self) + } + #[doc = "Bit 23 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<23> { + INT187_W::new(self) + } + #[doc = "Bit 25 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<25> { + INT188_W::new(self) + } + #[doc = "Bit 27 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<27> { + INT189_W::new(self) + } + #[doc = "Bit 29 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<29> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 176 - 191\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr44](index.html) module"] +pub struct GICD_ICFGR44_SPEC; +impl crate::RegisterSpec for GICD_ICFGR44_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr44::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR44_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr44::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR44_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR44 to value 0"] +impl crate::Resettable for GICD_ICFGR44_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs new file mode 100644 index 0000000..13e56f7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR48` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR48` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Interrupt 192\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT192_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT192_A) -> Self { + variant as u8 != 0 + } +} +impl INT192_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT192_A { + match self.bits { + false => INT192_A::LEVEL, + true => INT192_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT192_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT192_A::EDGE + } +} +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT192_A, O>; +impl<'a, const O: u8> INT192_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT192_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT192_A::EDGE) + } +} +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Interrupt 193\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT193_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT193_A) -> Self { + variant as u8 != 0 + } +} +impl INT193_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT193_A { + match self.bits { + false => INT193_A::LEVEL, + true => INT193_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT193_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT193_A::EDGE + } +} +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT193_A, O>; +impl<'a, const O: u8> INT193_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT193_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT193_A::EDGE) + } +} +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Interrupt 194\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT194_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT194_A) -> Self { + variant as u8 != 0 + } +} +impl INT194_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT194_A { + match self.bits { + false => INT194_A::LEVEL, + true => INT194_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT194_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT194_A::EDGE + } +} +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT194_A, O>; +impl<'a, const O: u8> INT194_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT194_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT194_A::EDGE) + } +} +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Interrupt 195\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT195_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT195_A) -> Self { + variant as u8 != 0 + } +} +impl INT195_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT195_A { + match self.bits { + false => INT195_A::LEVEL, + true => INT195_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT195_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT195_A::EDGE + } +} +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT195_A, O>; +impl<'a, const O: u8> INT195_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT195_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT195_A::EDGE) + } +} +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Interrupt 196\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT196_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT196_A) -> Self { + variant as u8 != 0 + } +} +impl INT196_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT196_A { + match self.bits { + false => INT196_A::LEVEL, + true => INT196_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT196_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT196_A::EDGE + } +} +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT196_A, O>; +impl<'a, const O: u8> INT196_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT196_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT196_A::EDGE) + } +} +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Interrupt 197\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT197_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT197_A) -> Self { + variant as u8 != 0 + } +} +impl INT197_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT197_A { + match self.bits { + false => INT197_A::LEVEL, + true => INT197_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT197_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT197_A::EDGE + } +} +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT197_A, O>; +impl<'a, const O: u8> INT197_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT197_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT197_A::EDGE) + } +} +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Interrupt 198\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT198_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT198_A) -> Self { + variant as u8 != 0 + } +} +impl INT198_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT198_A { + match self.bits { + false => INT198_A::LEVEL, + true => INT198_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT198_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT198_A::EDGE + } +} +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT198_A, O>; +impl<'a, const O: u8> INT198_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT198_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT198_A::EDGE) + } +} +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Interrupt 199\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT199_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT199_A) -> Self { + variant as u8 != 0 + } +} +impl INT199_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT199_A { + match self.bits { + false => INT199_A::LEVEL, + true => INT199_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT199_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT199_A::EDGE + } +} +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT199_A, O>; +impl<'a, const O: u8> INT199_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT199_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT199_A::EDGE) + } +} +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Interrupt 200\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT200_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT200_A) -> Self { + variant as u8 != 0 + } +} +impl INT200_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT200_A { + match self.bits { + false => INT200_A::LEVEL, + true => INT200_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT200_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT200_A::EDGE + } +} +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT200_A, O>; +impl<'a, const O: u8> INT200_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT200_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT200_A::EDGE) + } +} +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Interrupt 201\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT201_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT201_A) -> Self { + variant as u8 != 0 + } +} +impl INT201_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT201_A { + match self.bits { + false => INT201_A::LEVEL, + true => INT201_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT201_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT201_A::EDGE + } +} +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT201_A, O>; +impl<'a, const O: u8> INT201_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT201_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT201_A::EDGE) + } +} +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Interrupt 202\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT202_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT202_A) -> Self { + variant as u8 != 0 + } +} +impl INT202_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT202_A { + match self.bits { + false => INT202_A::LEVEL, + true => INT202_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT202_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT202_A::EDGE + } +} +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT202_A, O>; +impl<'a, const O: u8> INT202_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT202_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT202_A::EDGE) + } +} +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Interrupt 203\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT203_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT203_A) -> Self { + variant as u8 != 0 + } +} +impl INT203_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT203_A { + match self.bits { + false => INT203_A::LEVEL, + true => INT203_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT203_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT203_A::EDGE + } +} +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT203_A, O>; +impl<'a, const O: u8> INT203_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT203_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT203_A::EDGE) + } +} +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Interrupt 204\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT204_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT204_A) -> Self { + variant as u8 != 0 + } +} +impl INT204_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT204_A { + match self.bits { + false => INT204_A::LEVEL, + true => INT204_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT204_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT204_A::EDGE + } +} +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT204_A, O>; +impl<'a, const O: u8> INT204_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT204_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT204_A::EDGE) + } +} +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Interrupt 205\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT205_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT205_A) -> Self { + variant as u8 != 0 + } +} +impl INT205_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT205_A { + match self.bits { + false => INT205_A::LEVEL, + true => INT205_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT205_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT205_A::EDGE + } +} +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT205_A, O>; +impl<'a, const O: u8> INT205_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT205_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT205_A::EDGE) + } +} +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Interrupt 206\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT206_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT206_A) -> Self { + variant as u8 != 0 + } +} +impl INT206_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT206_A { + match self.bits { + false => INT206_A::LEVEL, + true => INT206_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT206_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT206_A::EDGE + } +} +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT206_A, O>; +impl<'a, const O: u8> INT206_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT206_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT206_A::EDGE) + } +} +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Interrupt 207\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT207_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT207_A) -> Self { + variant as u8 != 0 + } +} +impl INT207_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT207_A { + match self.bits { + false => INT207_A::LEVEL, + true => INT207_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT207_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT207_A::EDGE + } +} +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT207_A, O>; +impl<'a, const O: u8> INT207_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT207_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT207_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<1> { + INT192_W::new(self) + } + #[doc = "Bit 3 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<3> { + INT193_W::new(self) + } + #[doc = "Bit 5 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<5> { + INT194_W::new(self) + } + #[doc = "Bit 7 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<7> { + INT195_W::new(self) + } + #[doc = "Bit 9 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<9> { + INT196_W::new(self) + } + #[doc = "Bit 11 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<11> { + INT197_W::new(self) + } + #[doc = "Bit 13 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<13> { + INT198_W::new(self) + } + #[doc = "Bit 15 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<15> { + INT199_W::new(self) + } + #[doc = "Bit 17 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<17> { + INT200_W::new(self) + } + #[doc = "Bit 19 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<19> { + INT201_W::new(self) + } + #[doc = "Bit 21 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<21> { + INT202_W::new(self) + } + #[doc = "Bit 23 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<23> { + INT203_W::new(self) + } + #[doc = "Bit 25 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<25> { + INT204_W::new(self) + } + #[doc = "Bit 27 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<27> { + INT205_W::new(self) + } + #[doc = "Bit 29 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<29> { + INT206_W::new(self) + } + #[doc = "Bit 31 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<31> { + INT207_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 192 - 207\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr48](index.html) module"] +pub struct GICD_ICFGR48_SPEC; +impl crate::RegisterSpec for GICD_ICFGR48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr48::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR48_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr48::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR48_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR48 to value 0"] +impl crate::Resettable for GICD_ICFGR48_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs new file mode 100644 index 0000000..cb7b1b0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR52` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR52` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Interrupt 208\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT208_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT208_A) -> Self { + variant as u8 != 0 + } +} +impl INT208_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT208_A { + match self.bits { + false => INT208_A::LEVEL, + true => INT208_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT208_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT208_A::EDGE + } +} +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT208_A, O>; +impl<'a, const O: u8> INT208_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT208_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT208_A::EDGE) + } +} +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Interrupt 209\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT209_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT209_A) -> Self { + variant as u8 != 0 + } +} +impl INT209_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT209_A { + match self.bits { + false => INT209_A::LEVEL, + true => INT209_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT209_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT209_A::EDGE + } +} +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT209_A, O>; +impl<'a, const O: u8> INT209_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT209_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT209_A::EDGE) + } +} +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Interrupt 210\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT210_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT210_A) -> Self { + variant as u8 != 0 + } +} +impl INT210_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT210_A { + match self.bits { + false => INT210_A::LEVEL, + true => INT210_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT210_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT210_A::EDGE + } +} +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT210_A, O>; +impl<'a, const O: u8> INT210_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT210_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT210_A::EDGE) + } +} +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Interrupt 211\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT211_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT211_A) -> Self { + variant as u8 != 0 + } +} +impl INT211_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT211_A { + match self.bits { + false => INT211_A::LEVEL, + true => INT211_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT211_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT211_A::EDGE + } +} +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT211_A, O>; +impl<'a, const O: u8> INT211_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT211_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT211_A::EDGE) + } +} +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Interrupt 212\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT212_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT212_A) -> Self { + variant as u8 != 0 + } +} +impl INT212_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT212_A { + match self.bits { + false => INT212_A::LEVEL, + true => INT212_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT212_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT212_A::EDGE + } +} +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT212_A, O>; +impl<'a, const O: u8> INT212_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT212_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT212_A::EDGE) + } +} +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Interrupt 213\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT213_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT213_A) -> Self { + variant as u8 != 0 + } +} +impl INT213_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT213_A { + match self.bits { + false => INT213_A::LEVEL, + true => INT213_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT213_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT213_A::EDGE + } +} +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT213_A, O>; +impl<'a, const O: u8> INT213_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT213_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT213_A::EDGE) + } +} +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Interrupt 214\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT214_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT214_A) -> Self { + variant as u8 != 0 + } +} +impl INT214_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT214_A { + match self.bits { + false => INT214_A::LEVEL, + true => INT214_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT214_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT214_A::EDGE + } +} +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT214_A, O>; +impl<'a, const O: u8> INT214_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT214_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT214_A::EDGE) + } +} +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Interrupt 215\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT215_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT215_A) -> Self { + variant as u8 != 0 + } +} +impl INT215_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT215_A { + match self.bits { + false => INT215_A::LEVEL, + true => INT215_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT215_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT215_A::EDGE + } +} +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT215_A, O>; +impl<'a, const O: u8> INT215_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT215_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT215_A::EDGE) + } +} +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Interrupt 216\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT216_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT216_A) -> Self { + variant as u8 != 0 + } +} +impl INT216_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT216_A { + match self.bits { + false => INT216_A::LEVEL, + true => INT216_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT216_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT216_A::EDGE + } +} +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT216_A, O>; +impl<'a, const O: u8> INT216_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT216_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT216_A::EDGE) + } +} +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Interrupt 217\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT217_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT217_A) -> Self { + variant as u8 != 0 + } +} +impl INT217_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT217_A { + match self.bits { + false => INT217_A::LEVEL, + true => INT217_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT217_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT217_A::EDGE + } +} +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT217_A, O>; +impl<'a, const O: u8> INT217_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT217_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT217_A::EDGE) + } +} +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Interrupt 218\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT218_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT218_A) -> Self { + variant as u8 != 0 + } +} +impl INT218_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT218_A { + match self.bits { + false => INT218_A::LEVEL, + true => INT218_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT218_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT218_A::EDGE + } +} +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT218_A, O>; +impl<'a, const O: u8> INT218_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT218_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT218_A::EDGE) + } +} +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Interrupt 219\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT219_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT219_A) -> Self { + variant as u8 != 0 + } +} +impl INT219_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT219_A { + match self.bits { + false => INT219_A::LEVEL, + true => INT219_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT219_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT219_A::EDGE + } +} +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT219_A, O>; +impl<'a, const O: u8> INT219_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT219_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT219_A::EDGE) + } +} +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Interrupt 220\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT220_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT220_A) -> Self { + variant as u8 != 0 + } +} +impl INT220_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT220_A { + match self.bits { + false => INT220_A::LEVEL, + true => INT220_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT220_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT220_A::EDGE + } +} +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT220_A, O>; +impl<'a, const O: u8> INT220_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT220_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT220_A::EDGE) + } +} +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Interrupt 221\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT221_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT221_A) -> Self { + variant as u8 != 0 + } +} +impl INT221_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT221_A { + match self.bits { + false => INT221_A::LEVEL, + true => INT221_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT221_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT221_A::EDGE + } +} +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT221_A, O>; +impl<'a, const O: u8> INT221_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT221_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT221_A::EDGE) + } +} +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Interrupt 222\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT222_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT222_A) -> Self { + variant as u8 != 0 + } +} +impl INT222_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT222_A { + match self.bits { + false => INT222_A::LEVEL, + true => INT222_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT222_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT222_A::EDGE + } +} +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT222_A, O>; +impl<'a, const O: u8> INT222_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT222_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT222_A::EDGE) + } +} +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Interrupt 223\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT223_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT223_A) -> Self { + variant as u8 != 0 + } +} +impl INT223_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT223_A { + match self.bits { + false => INT223_A::LEVEL, + true => INT223_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT223_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT223_A::EDGE + } +} +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT223_A, O>; +impl<'a, const O: u8> INT223_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT223_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT223_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<1> { + INT208_W::new(self) + } + #[doc = "Bit 3 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<3> { + INT209_W::new(self) + } + #[doc = "Bit 5 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<5> { + INT210_W::new(self) + } + #[doc = "Bit 7 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<7> { + INT211_W::new(self) + } + #[doc = "Bit 9 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<9> { + INT212_W::new(self) + } + #[doc = "Bit 11 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<11> { + INT213_W::new(self) + } + #[doc = "Bit 13 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<13> { + INT214_W::new(self) + } + #[doc = "Bit 15 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<15> { + INT215_W::new(self) + } + #[doc = "Bit 17 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<17> { + INT216_W::new(self) + } + #[doc = "Bit 19 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<19> { + INT217_W::new(self) + } + #[doc = "Bit 21 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<21> { + INT218_W::new(self) + } + #[doc = "Bit 23 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<23> { + INT219_W::new(self) + } + #[doc = "Bit 25 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<25> { + INT220_W::new(self) + } + #[doc = "Bit 27 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<27> { + INT221_W::new(self) + } + #[doc = "Bit 29 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<29> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 208 - 223\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr52](index.html) module"] +pub struct GICD_ICFGR52_SPEC; +impl crate::RegisterSpec for GICD_ICFGR52_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr52::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR52_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr52::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR52_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR52 to value 0"] +impl crate::Resettable for GICD_ICFGR52_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs new file mode 100644 index 0000000..90c87a0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs @@ -0,0 +1,1041 @@ +#[doc = "Register `GICD_ICFGR8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICFGR8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Interrupt 32\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT32_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT32_A) -> Self { + variant as u8 != 0 + } +} +impl INT32_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT32_A { + match self.bits { + false => INT32_A::LEVEL, + true => INT32_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT32_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT32_A::EDGE + } +} +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT32_A, O>; +impl<'a, const O: u8> INT32_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT32_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT32_A::EDGE) + } +} +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Interrupt 33\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT33_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT33_A) -> Self { + variant as u8 != 0 + } +} +impl INT33_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT33_A { + match self.bits { + false => INT33_A::LEVEL, + true => INT33_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT33_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT33_A::EDGE + } +} +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT33_A, O>; +impl<'a, const O: u8> INT33_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT33_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT33_A::EDGE) + } +} +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Interrupt 34\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT34_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT34_A) -> Self { + variant as u8 != 0 + } +} +impl INT34_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT34_A { + match self.bits { + false => INT34_A::LEVEL, + true => INT34_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT34_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT34_A::EDGE + } +} +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT34_A, O>; +impl<'a, const O: u8> INT34_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT34_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT34_A::EDGE) + } +} +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Interrupt 35\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT35_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT35_A) -> Self { + variant as u8 != 0 + } +} +impl INT35_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT35_A { + match self.bits { + false => INT35_A::LEVEL, + true => INT35_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT35_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT35_A::EDGE + } +} +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT35_A, O>; +impl<'a, const O: u8> INT35_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT35_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT35_A::EDGE) + } +} +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Interrupt 36\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT36_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT36_A) -> Self { + variant as u8 != 0 + } +} +impl INT36_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT36_A { + match self.bits { + false => INT36_A::LEVEL, + true => INT36_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT36_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT36_A::EDGE + } +} +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT36_A, O>; +impl<'a, const O: u8> INT36_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT36_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT36_A::EDGE) + } +} +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Interrupt 37\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT37_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT37_A) -> Self { + variant as u8 != 0 + } +} +impl INT37_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT37_A { + match self.bits { + false => INT37_A::LEVEL, + true => INT37_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT37_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT37_A::EDGE + } +} +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT37_A, O>; +impl<'a, const O: u8> INT37_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT37_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT37_A::EDGE) + } +} +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Interrupt 38\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT38_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT38_A) -> Self { + variant as u8 != 0 + } +} +impl INT38_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT38_A { + match self.bits { + false => INT38_A::LEVEL, + true => INT38_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT38_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT38_A::EDGE + } +} +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT38_A, O>; +impl<'a, const O: u8> INT38_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT38_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT38_A::EDGE) + } +} +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Interrupt 39\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT39_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT39_A) -> Self { + variant as u8 != 0 + } +} +impl INT39_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT39_A { + match self.bits { + false => INT39_A::LEVEL, + true => INT39_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT39_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT39_A::EDGE + } +} +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT39_A, O>; +impl<'a, const O: u8> INT39_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT39_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT39_A::EDGE) + } +} +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Interrupt 40\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT40_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT40_A) -> Self { + variant as u8 != 0 + } +} +impl INT40_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT40_A { + match self.bits { + false => INT40_A::LEVEL, + true => INT40_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT40_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT40_A::EDGE + } +} +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT40_A, O>; +impl<'a, const O: u8> INT40_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT40_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT40_A::EDGE) + } +} +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Interrupt 41\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT41_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT41_A) -> Self { + variant as u8 != 0 + } +} +impl INT41_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT41_A { + match self.bits { + false => INT41_A::LEVEL, + true => INT41_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT41_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT41_A::EDGE + } +} +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT41_A, O>; +impl<'a, const O: u8> INT41_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT41_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT41_A::EDGE) + } +} +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Interrupt 42\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT42_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT42_A) -> Self { + variant as u8 != 0 + } +} +impl INT42_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT42_A { + match self.bits { + false => INT42_A::LEVEL, + true => INT42_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT42_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT42_A::EDGE + } +} +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT42_A, O>; +impl<'a, const O: u8> INT42_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT42_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT42_A::EDGE) + } +} +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Interrupt 43\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT43_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT43_A) -> Self { + variant as u8 != 0 + } +} +impl INT43_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT43_A { + match self.bits { + false => INT43_A::LEVEL, + true => INT43_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT43_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT43_A::EDGE + } +} +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT43_A, O>; +impl<'a, const O: u8> INT43_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT43_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT43_A::EDGE) + } +} +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Interrupt 44\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT44_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT44_A) -> Self { + variant as u8 != 0 + } +} +impl INT44_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT44_A { + match self.bits { + false => INT44_A::LEVEL, + true => INT44_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT44_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT44_A::EDGE + } +} +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT44_A, O>; +impl<'a, const O: u8> INT44_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT44_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT44_A::EDGE) + } +} +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Interrupt 45\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT45_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT45_A) -> Self { + variant as u8 != 0 + } +} +impl INT45_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT45_A { + match self.bits { + false => INT45_A::LEVEL, + true => INT45_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT45_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT45_A::EDGE + } +} +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT45_A, O>; +impl<'a, const O: u8> INT45_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT45_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT45_A::EDGE) + } +} +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Interrupt 46\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT46_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT46_A) -> Self { + variant as u8 != 0 + } +} +impl INT46_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT46_A { + match self.bits { + false => INT46_A::LEVEL, + true => INT46_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT46_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT46_A::EDGE + } +} +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT46_A, O>; +impl<'a, const O: u8> INT46_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT46_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT46_A::EDGE) + } +} +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Interrupt 47\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INT47_A { + #[doc = "0: Level sensitive"] + LEVEL = 0, + #[doc = "1: Edge triggered"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INT47_A) -> Self { + variant as u8 != 0 + } +} +impl INT47_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INT47_A { + match self.bits { + false => INT47_A::LEVEL, + true => INT47_A::EDGE, + } + } + #[doc = "Checks if the value of the field is `LEVEL`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == INT47_A::LEVEL + } + #[doc = "Checks if the value of the field is `EDGE`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == INT47_A::EDGE + } +} +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT47_A, O>; +impl<'a, const O: u8> INT47_W<'a, O> { + #[doc = "Level sensitive"] + #[inline(always)] + pub fn level(self) -> &'a mut W { + self.variant(INT47_A::LEVEL) + } + #[doc = "Edge triggered"] + #[inline(always)] + pub fn edge(self) -> &'a mut W { + self.variant(INT47_A::EDGE) + } +} +impl R { + #[doc = "Bit 1 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<1> { + INT32_W::new(self) + } + #[doc = "Bit 3 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<3> { + INT33_W::new(self) + } + #[doc = "Bit 5 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<5> { + INT34_W::new(self) + } + #[doc = "Bit 7 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<7> { + INT35_W::new(self) + } + #[doc = "Bit 9 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<9> { + INT36_W::new(self) + } + #[doc = "Bit 11 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<11> { + INT37_W::new(self) + } + #[doc = "Bit 13 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<13> { + INT38_W::new(self) + } + #[doc = "Bit 15 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<15> { + INT39_W::new(self) + } + #[doc = "Bit 17 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<17> { + INT40_W::new(self) + } + #[doc = "Bit 19 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<19> { + INT41_W::new(self) + } + #[doc = "Bit 21 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<21> { + INT42_W::new(self) + } + #[doc = "Bit 23 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<23> { + INT43_W::new(self) + } + #[doc = "Bit 25 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<25> { + INT44_W::new(self) + } + #[doc = "Bit 27 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<27> { + INT45_W::new(self) + } + #[doc = "Bit 29 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<29> { + INT46_W::new(self) + } + #[doc = "Bit 31 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<31> { + INT47_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Configuration 32 - 47\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr8](index.html) module"] +pub struct GICD_ICFGR8_SPEC; +impl crate::RegisterSpec for GICD_ICFGR8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icfgr8::R](R) reader structure"] +impl crate::Readable for GICD_ICFGR8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icfgr8::W](W) writer structure"] +impl crate::Writable for GICD_ICFGR8_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ICFGR8 to value 0"] +impl crate::Resettable for GICD_ICFGR8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs new file mode 100644 index 0000000..8a6748a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ICPENDR { + #[doc = "0x00 - Interrupt Clear-Pending"] + pub gicd_icpendr0: GICD_ICPENDR0, + #[doc = "0x04 - Interrupt Clear-Pending"] + pub gicd_icpendr1: GICD_ICPENDR1, + #[doc = "0x08 - Interrupt Clear-Pending"] + pub gicd_icpendr2: GICD_ICPENDR2, + #[doc = "0x0c - Interrupt Clear-Pending"] + pub gicd_icpendr3: GICD_ICPENDR3, + #[doc = "0x10 - Interrupt Clear-Pending"] + pub gicd_icpendr4: GICD_ICPENDR4, + #[doc = "0x14 - Interrupt Clear-Pending"] + pub gicd_icpendr5: GICD_ICPENDR5, + #[doc = "0x18 - Interrupt Clear-Pending"] + pub gicd_icpendr6: GICD_ICPENDR6, +} +#[doc = "GICD_ICPENDR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR0 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr0; +#[doc = "GICD_ICPENDR1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR1 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr1; +#[doc = "GICD_ICPENDR2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR2 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr2; +#[doc = "GICD_ICPENDR3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR3 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr3; +#[doc = "GICD_ICPENDR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR4 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr4; +#[doc = "GICD_ICPENDR5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR5 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr5; +#[doc = "GICD_ICPENDR6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ICPENDR6 = crate::Reg; +#[doc = "Interrupt Clear-Pending"] +pub mod gicd_icpendr6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs new file mode 100644 index 0000000..10f341b --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICPENDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr0](index.html) module"] +pub struct GICD_ICPENDR0_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr0::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr0::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR0 to value 0"] +impl crate::Resettable for GICD_ICPENDR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs new file mode 100644 index 0000000..1ed2815 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICPENDR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr1](index.html) module"] +pub struct GICD_ICPENDR1_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr1::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr1::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR1 to value 0"] +impl crate::Resettable for GICD_ICPENDR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs new file mode 100644 index 0000000..3df1ff7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs @@ -0,0 +1,547 @@ +#[doc = "Register `GICD_ICPENDR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr2](index.html) module"] +pub struct GICD_ICPENDR2_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr2::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr2::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR2 to value 0"] +impl crate::Resettable for GICD_ICPENDR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs new file mode 100644 index 0000000..bcd5e0e --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ICPENDR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr3](index.html) module"] +pub struct GICD_ICPENDR3_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr3::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr3::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR3 to value 0"] +impl crate::Resettable for GICD_ICPENDR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs new file mode 100644 index 0000000..d787e95 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs @@ -0,0 +1,551 @@ +#[doc = "Register `GICD_ICPENDR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr4](index.html) module"] +pub struct GICD_ICPENDR4_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr4::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr4::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR4 to value 0"] +impl crate::Resettable for GICD_ICPENDR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs new file mode 100644 index 0000000..120ad5f --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICPENDR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr5](index.html) module"] +pub struct GICD_ICPENDR5_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr5::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr5::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR5 to value 0"] +impl crate::Resettable for GICD_ICPENDR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs new file mode 100644 index 0000000..e918954 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ICPENDR6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ICPENDR6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr6](index.html) module"] +pub struct GICD_ICPENDR6_SPEC; +impl crate::RegisterSpec for GICD_ICPENDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_icpendr6::R](R) reader structure"] +impl crate::Readable for GICD_ICPENDR6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_icpendr6::W](W) writer structure"] +impl crate::Writable for GICD_ICPENDR6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ICPENDR6 to value 0"] +impl crate::Resettable for GICD_ICPENDR6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs new file mode 100644 index 0000000..11c8975 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_IGROUPR { + #[doc = "0x00 - Interrupt Group"] + pub gicd_igroupr0: GICD_IGROUPR0, + #[doc = "0x04 - Interrupt Group"] + pub gicd_igroupr1: GICD_IGROUPR1, + #[doc = "0x08 - Interrupt Group"] + pub gicd_igroupr2: GICD_IGROUPR2, + #[doc = "0x0c - Interrupt Group"] + pub gicd_igroupr3: GICD_IGROUPR3, + #[doc = "0x10 - Interrupt Group"] + pub gicd_igroupr4: GICD_IGROUPR4, + #[doc = "0x14 - Interrupt Group"] + pub gicd_igroupr5: GICD_IGROUPR5, + #[doc = "0x18 - Interrupt Group"] + pub gicd_igroupr6: GICD_IGROUPR6, +} +#[doc = "GICD_IGROUPR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR0 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr0; +#[doc = "GICD_IGROUPR1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR1 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr1; +#[doc = "GICD_IGROUPR2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR2 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr2; +#[doc = "GICD_IGROUPR3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR3 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr3; +#[doc = "GICD_IGROUPR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR4 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr4; +#[doc = "GICD_IGROUPR5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR5 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr5; +#[doc = "GICD_IGROUPR6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IGROUPR6 = crate::Reg; +#[doc = "Interrupt Group"] +pub mod gicd_igroupr6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs new file mode 100644 index 0000000..d68154b --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_IGROUPR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr0](index.html) module"] +pub struct GICD_IGROUPR0_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr0::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr0::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR0 to value 0"] +impl crate::Resettable for GICD_IGROUPR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs new file mode 100644 index 0000000..ad44459 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_IGROUPR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr1](index.html) module"] +pub struct GICD_IGROUPR1_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr1::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr1::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR1 to value 0"] +impl crate::Resettable for GICD_IGROUPR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs new file mode 100644 index 0000000..b5c50f4 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs @@ -0,0 +1,546 @@ +#[doc = "Register `GICD_IGROUPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr2](index.html) module"] +pub struct GICD_IGROUPR2_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr2::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr2::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR2 to value 0"] +impl crate::Resettable for GICD_IGROUPR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs new file mode 100644 index 0000000..61b2616 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_IGROUPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr3](index.html) module"] +pub struct GICD_IGROUPR3_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr3::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr3::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR3 to value 0"] +impl crate::Resettable for GICD_IGROUPR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs new file mode 100644 index 0000000..f2c5903 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs @@ -0,0 +1,547 @@ +#[doc = "Register `GICD_IGROUPR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr4](index.html) module"] +pub struct GICD_IGROUPR4_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr4::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr4::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR4 to value 0"] +impl crate::Resettable for GICD_IGROUPR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs new file mode 100644 index 0000000..1a56750 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_IGROUPR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr5](index.html) module"] +pub struct GICD_IGROUPR5_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr5::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr5::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR5 to value 0"] +impl crate::Resettable for GICD_IGROUPR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs new file mode 100644 index 0000000..093bad3 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_IGROUPR6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IGROUPR6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr6](index.html) module"] +pub struct GICD_IGROUPR6_SPEC; +impl crate::RegisterSpec for GICD_IGROUPR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_igroupr6::R](R) reader structure"] +impl crate::Readable for GICD_IGROUPR6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_igroupr6::W](W) writer structure"] +impl crate::Writable for GICD_IGROUPR6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IGROUPR6 to value 0"] +impl crate::Resettable for GICD_IGROUPR6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs new file mode 100644 index 0000000..681069e --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GICD_IIDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer"] +pub type IMPLEMENTER_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Revision"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `VARIANT` reader - Variant"] +pub type VARIANT_R = crate::FieldReader; +#[doc = "Field `PRODUCT_ID` reader - Product ID"] +pub type PRODUCT_ID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Implementer"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - Revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Variant"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Product ID"] + #[inline(always)] + pub fn product_id(&self) -> PRODUCT_ID_R { + PRODUCT_ID_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Distributor Implementer Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_iidr](index.html) module"] +pub struct GICD_IIDR_SPEC; +impl crate::RegisterSpec for GICD_IIDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_iidr::R](R) reader structure"] +impl crate::Readable for GICD_IIDR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_IIDR to value 0x0200_143b"] +impl crate::Resettable for GICD_IIDR_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_143b; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs new file mode 100644 index 0000000..85468af --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs @@ -0,0 +1,340 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_IPRIORITYR { + #[doc = "0x00 - Interrupt Priority 0 - 3 (Lower is first)"] + pub gicd_ipriorityr0: GICD_IPRIORITYR0, + #[doc = "0x04 - Interrupt Priority 4 - 7 (Lower is first)"] + pub gicd_ipriorityr1: GICD_IPRIORITYR1, + #[doc = "0x08 - Interrupt Priority 8 - 11 (Lower is first)"] + pub gicd_ipriorityr2: GICD_IPRIORITYR2, + #[doc = "0x0c - Interrupt Priority 12 - 15 (Lower is first)"] + pub gicd_ipriorityr3: GICD_IPRIORITYR3, + #[doc = "0x10 - Interrupt Priority 16 - 19 (Lower is first)"] + pub gicd_ipriorityr4: GICD_IPRIORITYR4, + #[doc = "0x14 - Interrupt Priority 20 - 23 (Lower is first)"] + pub gicd_ipriorityr5: GICD_IPRIORITYR5, + #[doc = "0x18 - Interrupt Priority 24 - 27 (Lower is first)"] + pub gicd_ipriorityr6: GICD_IPRIORITYR6, + #[doc = "0x1c - Interrupt Priority 28 - 31 (Lower is first)"] + pub gicd_ipriorityr7: GICD_IPRIORITYR7, + #[doc = "0x20 - Interrupt Priority 32 - 35 (Lower is first)"] + pub gicd_ipriorityr8: GICD_IPRIORITYR8, + #[doc = "0x24 - Interrupt Priority 36 - 39 (Lower is first)"] + pub gicd_ipriorityr9: GICD_IPRIORITYR9, + #[doc = "0x28 - Interrupt Priority 40 - 43 (Lower is first)"] + pub gicd_ipriorityr10: GICD_IPRIORITYR10, + #[doc = "0x2c - Interrupt Priority 44 - 47 (Lower is first)"] + pub gicd_ipriorityr11: GICD_IPRIORITYR11, + #[doc = "0x30 - Interrupt Priority 48 - 51 (Lower is first)"] + pub gicd_ipriorityr12: GICD_IPRIORITYR12, + #[doc = "0x34 - Interrupt Priority 52 - 55 (Lower is first)"] + pub gicd_ipriorityr13: GICD_IPRIORITYR13, + #[doc = "0x38 - Interrupt Priority 56 - 59 (Lower is first)"] + pub gicd_ipriorityr14: GICD_IPRIORITYR14, + #[doc = "0x3c - Interrupt Priority 60 - 63 (Lower is first)"] + pub gicd_ipriorityr15: GICD_IPRIORITYR15, + #[doc = "0x40 - Interrupt Priority 64 - 67 (Lower is first)"] + pub gicd_ipriorityr16: GICD_IPRIORITYR16, + #[doc = "0x44 - Interrupt Priority 68 - 71 (Lower is first)"] + pub gicd_ipriorityr17: GICD_IPRIORITYR17, + #[doc = "0x48 - Interrupt Priority 72 - 75 (Lower is first)"] + pub gicd_ipriorityr18: GICD_IPRIORITYR18, + #[doc = "0x4c - Interrupt Priority 76 - 79 (Lower is first)"] + pub gicd_ipriorityr19: GICD_IPRIORITYR19, + #[doc = "0x50 - Interrupt Priority 80 - 83 (Lower is first)"] + pub gicd_ipriorityr20: GICD_IPRIORITYR20, + #[doc = "0x54 - Interrupt Priority 84 - 87 (Lower is first)"] + pub gicd_ipriorityr21: GICD_IPRIORITYR21, + #[doc = "0x58 - Interrupt Priority 88 - 91 (Lower is first)"] + pub gicd_ipriorityr22: GICD_IPRIORITYR22, + #[doc = "0x5c - Interrupt Priority 92 - 95 (Lower is first)"] + pub gicd_ipriorityr23: GICD_IPRIORITYR23, + #[doc = "0x60 - Interrupt Priority 96 - 99 (Lower is first)"] + pub gicd_ipriorityr24: GICD_IPRIORITYR24, + #[doc = "0x64 - Interrupt Priority 100 - 103 (Lower is first)"] + pub gicd_ipriorityr25: GICD_IPRIORITYR25, + #[doc = "0x68 - Interrupt Priority 104 - 107 (Lower is first)"] + pub gicd_ipriorityr26: GICD_IPRIORITYR26, + #[doc = "0x6c - Interrupt Priority 108 - 111 (Lower is first)"] + pub gicd_ipriorityr27: GICD_IPRIORITYR27, + #[doc = "0x70 - Interrupt Priority 112 - 115 (Lower is first)"] + pub gicd_ipriorityr28: GICD_IPRIORITYR28, + #[doc = "0x74 - Interrupt Priority 116 - 119 (Lower is first)"] + pub gicd_ipriorityr29: GICD_IPRIORITYR29, + #[doc = "0x78 - Interrupt Priority 120 - 123 (Lower is first)"] + pub gicd_ipriorityr30: GICD_IPRIORITYR30, + #[doc = "0x7c - Interrupt Priority 124 - 127 (Lower is first)"] + pub gicd_ipriorityr31: GICD_IPRIORITYR31, + #[doc = "0x80 - Interrupt Priority 128 - 131 (Lower is first)"] + pub gicd_ipriorityr32: GICD_IPRIORITYR32, + #[doc = "0x84 - Interrupt Priority 132 - 135 (Lower is first)"] + pub gicd_ipriorityr33: GICD_IPRIORITYR33, + #[doc = "0x88 - Interrupt Priority 136 - 139 (Lower is first)"] + pub gicd_ipriorityr34: GICD_IPRIORITYR34, + #[doc = "0x8c - Interrupt Priority 140 - 143 (Lower is first)"] + pub gicd_ipriorityr35: GICD_IPRIORITYR35, + #[doc = "0x90 - Interrupt Priority 144 - 147 (Lower is first)"] + pub gicd_ipriorityr36: GICD_IPRIORITYR36, + #[doc = "0x94 - Interrupt Priority 148 - 151 (Lower is first)"] + pub gicd_ipriorityr37: GICD_IPRIORITYR37, + #[doc = "0x98 - Interrupt Priority 152 - 155 (Lower is first)"] + pub gicd_ipriorityr38: GICD_IPRIORITYR38, + #[doc = "0x9c - Interrupt Priority 156 - 159 (Lower is first)"] + pub gicd_ipriorityr39: GICD_IPRIORITYR39, + #[doc = "0xa0 - Interrupt Priority 160 - 163 (Lower is first)"] + pub gicd_ipriorityr40: GICD_IPRIORITYR40, + #[doc = "0xa4 - Interrupt Priority 164 - 167 (Lower is first)"] + pub gicd_ipriorityr41: GICD_IPRIORITYR41, + #[doc = "0xa8 - Interrupt Priority 168 - 171 (Lower is first)"] + pub gicd_ipriorityr42: GICD_IPRIORITYR42, + #[doc = "0xac - Interrupt Priority 172 - 175 (Lower is first)"] + pub gicd_ipriorityr43: GICD_IPRIORITYR43, + #[doc = "0xb0 - Interrupt Priority 176 - 179 (Lower is first)"] + pub gicd_ipriorityr44: GICD_IPRIORITYR44, + #[doc = "0xb4 - Interrupt Priority 180 - 183 (Lower is first)"] + pub gicd_ipriorityr45: GICD_IPRIORITYR45, + #[doc = "0xb8 - Interrupt Priority 184 - 187 (Lower is first)"] + pub gicd_ipriorityr46: GICD_IPRIORITYR46, + #[doc = "0xbc - Interrupt Priority 188 - 191 (Lower is first)"] + pub gicd_ipriorityr47: GICD_IPRIORITYR47, + #[doc = "0xc0 - Interrupt Priority 192 - 195 (Lower is first)"] + pub gicd_ipriorityr48: GICD_IPRIORITYR48, + #[doc = "0xc4 - Interrupt Priority 196 - 199 (Lower is first)"] + pub gicd_ipriorityr49: GICD_IPRIORITYR49, + #[doc = "0xc8 - Interrupt Priority 200 - 203 (Lower is first)"] + pub gicd_ipriorityr50: GICD_IPRIORITYR50, + #[doc = "0xcc - Interrupt Priority 204 - 207 (Lower is first)"] + pub gicd_ipriorityr51: GICD_IPRIORITYR51, + #[doc = "0xd0 - Interrupt Priority 208 - 211 (Lower is first)"] + pub gicd_ipriorityr52: GICD_IPRIORITYR52, + #[doc = "0xd4 - Interrupt Priority 212 - 215 (Lower is first)"] + pub gicd_ipriorityr53: GICD_IPRIORITYR53, + #[doc = "0xd8 - Interrupt Priority 216 - 219 (Lower is first)"] + pub gicd_ipriorityr54: GICD_IPRIORITYR54, + #[doc = "0xdc - Interrupt Priority 220 - 223 (Lower is first)"] + pub gicd_ipriorityr55: GICD_IPRIORITYR55, +} +#[doc = "GICD_IPRIORITYR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR0 = crate::Reg; +#[doc = "Interrupt Priority 0 - 3 (Lower is first)"] +pub mod gicd_ipriorityr0; +#[doc = "GICD_IPRIORITYR1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR1 = crate::Reg; +#[doc = "Interrupt Priority 4 - 7 (Lower is first)"] +pub mod gicd_ipriorityr1; +#[doc = "GICD_IPRIORITYR2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR2 = crate::Reg; +#[doc = "Interrupt Priority 8 - 11 (Lower is first)"] +pub mod gicd_ipriorityr2; +#[doc = "GICD_IPRIORITYR3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR3 = crate::Reg; +#[doc = "Interrupt Priority 12 - 15 (Lower is first)"] +pub mod gicd_ipriorityr3; +#[doc = "GICD_IPRIORITYR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR4 = crate::Reg; +#[doc = "Interrupt Priority 16 - 19 (Lower is first)"] +pub mod gicd_ipriorityr4; +#[doc = "GICD_IPRIORITYR5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR5 = crate::Reg; +#[doc = "Interrupt Priority 20 - 23 (Lower is first)"] +pub mod gicd_ipriorityr5; +#[doc = "GICD_IPRIORITYR6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR6 = crate::Reg; +#[doc = "Interrupt Priority 24 - 27 (Lower is first)"] +pub mod gicd_ipriorityr6; +#[doc = "GICD_IPRIORITYR7 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR7 = crate::Reg; +#[doc = "Interrupt Priority 28 - 31 (Lower is first)"] +pub mod gicd_ipriorityr7; +#[doc = "GICD_IPRIORITYR8 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR8 = crate::Reg; +#[doc = "Interrupt Priority 32 - 35 (Lower is first)"] +pub mod gicd_ipriorityr8; +#[doc = "GICD_IPRIORITYR9 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR9 = crate::Reg; +#[doc = "Interrupt Priority 36 - 39 (Lower is first)"] +pub mod gicd_ipriorityr9; +#[doc = "GICD_IPRIORITYR10 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR10 = crate::Reg; +#[doc = "Interrupt Priority 40 - 43 (Lower is first)"] +pub mod gicd_ipriorityr10; +#[doc = "GICD_IPRIORITYR11 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR11 = crate::Reg; +#[doc = "Interrupt Priority 44 - 47 (Lower is first)"] +pub mod gicd_ipriorityr11; +#[doc = "GICD_IPRIORITYR12 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR12 = crate::Reg; +#[doc = "Interrupt Priority 48 - 51 (Lower is first)"] +pub mod gicd_ipriorityr12; +#[doc = "GICD_IPRIORITYR13 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR13 = crate::Reg; +#[doc = "Interrupt Priority 52 - 55 (Lower is first)"] +pub mod gicd_ipriorityr13; +#[doc = "GICD_IPRIORITYR14 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR14 = crate::Reg; +#[doc = "Interrupt Priority 56 - 59 (Lower is first)"] +pub mod gicd_ipriorityr14; +#[doc = "GICD_IPRIORITYR15 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR15 = crate::Reg; +#[doc = "Interrupt Priority 60 - 63 (Lower is first)"] +pub mod gicd_ipriorityr15; +#[doc = "GICD_IPRIORITYR16 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR16 = crate::Reg; +#[doc = "Interrupt Priority 64 - 67 (Lower is first)"] +pub mod gicd_ipriorityr16; +#[doc = "GICD_IPRIORITYR17 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR17 = crate::Reg; +#[doc = "Interrupt Priority 68 - 71 (Lower is first)"] +pub mod gicd_ipriorityr17; +#[doc = "GICD_IPRIORITYR18 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR18 = crate::Reg; +#[doc = "Interrupt Priority 72 - 75 (Lower is first)"] +pub mod gicd_ipriorityr18; +#[doc = "GICD_IPRIORITYR19 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR19 = crate::Reg; +#[doc = "Interrupt Priority 76 - 79 (Lower is first)"] +pub mod gicd_ipriorityr19; +#[doc = "GICD_IPRIORITYR20 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR20 = crate::Reg; +#[doc = "Interrupt Priority 80 - 83 (Lower is first)"] +pub mod gicd_ipriorityr20; +#[doc = "GICD_IPRIORITYR21 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR21 = crate::Reg; +#[doc = "Interrupt Priority 84 - 87 (Lower is first)"] +pub mod gicd_ipriorityr21; +#[doc = "GICD_IPRIORITYR22 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR22 = crate::Reg; +#[doc = "Interrupt Priority 88 - 91 (Lower is first)"] +pub mod gicd_ipriorityr22; +#[doc = "GICD_IPRIORITYR23 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR23 = crate::Reg; +#[doc = "Interrupt Priority 92 - 95 (Lower is first)"] +pub mod gicd_ipriorityr23; +#[doc = "GICD_IPRIORITYR24 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR24 = crate::Reg; +#[doc = "Interrupt Priority 96 - 99 (Lower is first)"] +pub mod gicd_ipriorityr24; +#[doc = "GICD_IPRIORITYR25 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR25 = crate::Reg; +#[doc = "Interrupt Priority 100 - 103 (Lower is first)"] +pub mod gicd_ipriorityr25; +#[doc = "GICD_IPRIORITYR26 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR26 = crate::Reg; +#[doc = "Interrupt Priority 104 - 107 (Lower is first)"] +pub mod gicd_ipriorityr26; +#[doc = "GICD_IPRIORITYR27 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR27 = crate::Reg; +#[doc = "Interrupt Priority 108 - 111 (Lower is first)"] +pub mod gicd_ipriorityr27; +#[doc = "GICD_IPRIORITYR28 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR28 = crate::Reg; +#[doc = "Interrupt Priority 112 - 115 (Lower is first)"] +pub mod gicd_ipriorityr28; +#[doc = "GICD_IPRIORITYR29 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR29 = crate::Reg; +#[doc = "Interrupt Priority 116 - 119 (Lower is first)"] +pub mod gicd_ipriorityr29; +#[doc = "GICD_IPRIORITYR30 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR30 = crate::Reg; +#[doc = "Interrupt Priority 120 - 123 (Lower is first)"] +pub mod gicd_ipriorityr30; +#[doc = "GICD_IPRIORITYR31 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR31 = crate::Reg; +#[doc = "Interrupt Priority 124 - 127 (Lower is first)"] +pub mod gicd_ipriorityr31; +#[doc = "GICD_IPRIORITYR32 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR32 = crate::Reg; +#[doc = "Interrupt Priority 128 - 131 (Lower is first)"] +pub mod gicd_ipriorityr32; +#[doc = "GICD_IPRIORITYR33 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR33 = crate::Reg; +#[doc = "Interrupt Priority 132 - 135 (Lower is first)"] +pub mod gicd_ipriorityr33; +#[doc = "GICD_IPRIORITYR34 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR34 = crate::Reg; +#[doc = "Interrupt Priority 136 - 139 (Lower is first)"] +pub mod gicd_ipriorityr34; +#[doc = "GICD_IPRIORITYR35 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR35 = crate::Reg; +#[doc = "Interrupt Priority 140 - 143 (Lower is first)"] +pub mod gicd_ipriorityr35; +#[doc = "GICD_IPRIORITYR36 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR36 = crate::Reg; +#[doc = "Interrupt Priority 144 - 147 (Lower is first)"] +pub mod gicd_ipriorityr36; +#[doc = "GICD_IPRIORITYR37 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR37 = crate::Reg; +#[doc = "Interrupt Priority 148 - 151 (Lower is first)"] +pub mod gicd_ipriorityr37; +#[doc = "GICD_IPRIORITYR38 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR38 = crate::Reg; +#[doc = "Interrupt Priority 152 - 155 (Lower is first)"] +pub mod gicd_ipriorityr38; +#[doc = "GICD_IPRIORITYR39 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR39 = crate::Reg; +#[doc = "Interrupt Priority 156 - 159 (Lower is first)"] +pub mod gicd_ipriorityr39; +#[doc = "GICD_IPRIORITYR40 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR40 = crate::Reg; +#[doc = "Interrupt Priority 160 - 163 (Lower is first)"] +pub mod gicd_ipriorityr40; +#[doc = "GICD_IPRIORITYR41 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR41 = crate::Reg; +#[doc = "Interrupt Priority 164 - 167 (Lower is first)"] +pub mod gicd_ipriorityr41; +#[doc = "GICD_IPRIORITYR42 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR42 = crate::Reg; +#[doc = "Interrupt Priority 168 - 171 (Lower is first)"] +pub mod gicd_ipriorityr42; +#[doc = "GICD_IPRIORITYR43 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR43 = crate::Reg; +#[doc = "Interrupt Priority 172 - 175 (Lower is first)"] +pub mod gicd_ipriorityr43; +#[doc = "GICD_IPRIORITYR44 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR44 = crate::Reg; +#[doc = "Interrupt Priority 176 - 179 (Lower is first)"] +pub mod gicd_ipriorityr44; +#[doc = "GICD_IPRIORITYR45 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR45 = crate::Reg; +#[doc = "Interrupt Priority 180 - 183 (Lower is first)"] +pub mod gicd_ipriorityr45; +#[doc = "GICD_IPRIORITYR46 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR46 = crate::Reg; +#[doc = "Interrupt Priority 184 - 187 (Lower is first)"] +pub mod gicd_ipriorityr46; +#[doc = "GICD_IPRIORITYR47 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR47 = crate::Reg; +#[doc = "Interrupt Priority 188 - 191 (Lower is first)"] +pub mod gicd_ipriorityr47; +#[doc = "GICD_IPRIORITYR48 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR48 = crate::Reg; +#[doc = "Interrupt Priority 192 - 195 (Lower is first)"] +pub mod gicd_ipriorityr48; +#[doc = "GICD_IPRIORITYR49 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR49 = crate::Reg; +#[doc = "Interrupt Priority 196 - 199 (Lower is first)"] +pub mod gicd_ipriorityr49; +#[doc = "GICD_IPRIORITYR50 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR50 = crate::Reg; +#[doc = "Interrupt Priority 200 - 203 (Lower is first)"] +pub mod gicd_ipriorityr50; +#[doc = "GICD_IPRIORITYR51 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR51 = crate::Reg; +#[doc = "Interrupt Priority 204 - 207 (Lower is first)"] +pub mod gicd_ipriorityr51; +#[doc = "GICD_IPRIORITYR52 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR52 = crate::Reg; +#[doc = "Interrupt Priority 208 - 211 (Lower is first)"] +pub mod gicd_ipriorityr52; +#[doc = "GICD_IPRIORITYR53 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR53 = crate::Reg; +#[doc = "Interrupt Priority 212 - 215 (Lower is first)"] +pub mod gicd_ipriorityr53; +#[doc = "GICD_IPRIORITYR54 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR54 = crate::Reg; +#[doc = "Interrupt Priority 216 - 219 (Lower is first)"] +pub mod gicd_ipriorityr54; +#[doc = "GICD_IPRIORITYR55 (rw) register accessor: an alias for `Reg`"] +pub type GICD_IPRIORITYR55 = crate::Reg; +#[doc = "Interrupt Priority 220 - 223 (Lower is first)"] +pub mod gicd_ipriorityr55; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs new file mode 100644 index 0000000..739cf21 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_IPRIORITYR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::FieldReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::FieldReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::FieldReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::FieldReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<8> { + INT1_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<16> { + INT2_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<24> { + INT3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 0 - 3 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr0](index.html) module"] +pub struct GICD_IPRIORITYR0_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr0::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr0::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR0 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs new file mode 100644 index 0000000..368e075 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_IPRIORITYR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::FieldReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::FieldReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::FieldReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::FieldReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<0> { + INT4_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<8> { + INT5_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<16> { + INT6_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<24> { + INT7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 4 - 7 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr1](index.html) module"] +pub struct GICD_IPRIORITYR1_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr1::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr1::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR1 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs new file mode 100644 index 0000000..5447dfb --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::FieldReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::FieldReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::FieldReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::FieldReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<0> { + INT40_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<8> { + INT41_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<16> { + INT42_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<24> { + INT43_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 40 - 43 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr10](index.html) module"] +pub struct GICD_IPRIORITYR10_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr10::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr10::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR10_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR10 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs new file mode 100644 index 0000000..bc71e03 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::FieldReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::FieldReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::FieldReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::FieldReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<0> { + INT44_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<8> { + INT45_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<16> { + INT46_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<24> { + INT47_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 44 - 47 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr11](index.html) module"] +pub struct GICD_IPRIORITYR11_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr11::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr11::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR11_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR11 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs new file mode 100644 index 0000000..44785a0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::FieldReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::FieldReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::FieldReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::FieldReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<0> { + INT48_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<8> { + INT49_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<16> { + INT50_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<24> { + INT51_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 48 - 51 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr12](index.html) module"] +pub struct GICD_IPRIORITYR12_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr12::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr12::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR12_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR12 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs new file mode 100644 index 0000000..53f82e8 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::FieldReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::FieldReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::FieldReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::FieldReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<0> { + INT52_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<8> { + INT53_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<16> { + INT54_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<24> { + INT55_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 52 - 55 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr13](index.html) module"] +pub struct GICD_IPRIORITYR13_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr13::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr13::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR13_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR13 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs new file mode 100644 index 0000000..d45e8d4 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::FieldReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::FieldReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::FieldReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::FieldReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<0> { + INT56_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<8> { + INT57_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<16> { + INT58_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<24> { + INT59_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 56 - 59 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr14](index.html) module"] +pub struct GICD_IPRIORITYR14_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr14::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr14::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR14_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR14 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs new file mode 100644 index 0000000..8200e81 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR15` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR15` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::FieldReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::FieldReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::FieldReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::FieldReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<0> { + INT60_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<8> { + INT61_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<16> { + INT62_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<24> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 60 - 63 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr15](index.html) module"] +pub struct GICD_IPRIORITYR15_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr15::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR15_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr15::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR15_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR15 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs new file mode 100644 index 0000000..17c0f1d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR16` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR16` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::FieldReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::FieldReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::FieldReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::FieldReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bits 8:15 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<8> { + MAILBOX_W::new(self) + } + #[doc = "Bits 16:23 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<16> { + DOORBELL0_W::new(self) + } + #[doc = "Bits 24:31 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<24> { + DOORBELL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 64 - 67 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr16](index.html) module"] +pub struct GICD_IPRIORITYR16_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr16::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR16_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr16::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR16_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR16 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR16_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs new file mode 100644 index 0000000..e51048c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR17` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR17` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::FieldReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::FieldReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::FieldReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::FieldReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<0> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bits 8:15 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<8> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bits 16:23 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<16> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bits 24:31 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<24> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 68 - 71 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr17](index.html) module"] +pub struct GICD_IPRIORITYR17_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr17::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR17_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr17::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR17_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR17 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR17_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs new file mode 100644 index 0000000..46956b3 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR18` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR18` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::FieldReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::FieldReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::FieldReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::FieldReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<0> { + SWI0_W::new(self) + } + #[doc = "Bits 8:15 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<8> { + SWI1_W::new(self) + } + #[doc = "Bits 16:23 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<16> { + SWI2_W::new(self) + } + #[doc = "Bits 24:31 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<24> { + SWI3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 72 - 75 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr18](index.html) module"] +pub struct GICD_IPRIORITYR18_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR18_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr18::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR18_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr18::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR18_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR18 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR18_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs new file mode 100644 index 0000000..d2e13b4 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR19` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR19` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::FieldReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::FieldReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::FieldReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::FieldReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<0> { + SWI4_W::new(self) + } + #[doc = "Bits 8:15 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<8> { + SWI5_W::new(self) + } + #[doc = "Bits 16:23 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<16> { + SWI6_W::new(self) + } + #[doc = "Bits 24:31 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<24> { + SWI7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 76 - 79 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr19](index.html) module"] +pub struct GICD_IPRIORITYR19_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR19_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr19::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR19_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr19::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR19_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR19 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR19_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs new file mode 100644 index 0000000..0d60965 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_IPRIORITYR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::FieldReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::FieldReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::FieldReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::FieldReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<0> { + INT8_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<8> { + INT9_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<16> { + INT10_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<24> { + INT11_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 8 - 11 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr2](index.html) module"] +pub struct GICD_IPRIORITYR2_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr2::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr2::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR2 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs new file mode 100644 index 0000000..37a9dcc --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR20` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR20` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::FieldReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::FieldReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::FieldReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::FieldReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<0> { + INT80_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<8> { + INT81_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<16> { + INT82_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<24> { + INT83_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 80 - 83 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr20](index.html) module"] +pub struct GICD_IPRIORITYR20_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr20::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR20_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr20::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR20_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR20 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR20_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs new file mode 100644 index 0000000..7b48d2c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR21` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR21` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::FieldReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::FieldReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::FieldReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::FieldReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<0> { + INT84_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<8> { + INT85_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<16> { + INT86_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<24> { + INT87_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 84 - 87 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr21](index.html) module"] +pub struct GICD_IPRIORITYR21_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR21_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr21::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR21_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr21::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR21_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR21 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR21_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs new file mode 100644 index 0000000..f685300 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR22` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR22` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::FieldReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::FieldReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::FieldReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::FieldReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<0> { + INT88_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<8> { + INT89_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<16> { + INT90_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<24> { + INT91_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 88 - 91 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr22](index.html) module"] +pub struct GICD_IPRIORITYR22_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR22_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr22::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR22_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr22::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR22_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR22 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR22_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs new file mode 100644 index 0000000..8e51a9d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR23` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR23` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::FieldReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::FieldReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::FieldReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::FieldReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<0> { + INT92_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<8> { + INT93_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<16> { + INT94_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<24> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 92 - 95 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr23](index.html) module"] +pub struct GICD_IPRIORITYR23_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR23_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr23::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR23_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr23::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR23_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR23 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR23_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs new file mode 100644 index 0000000..50266ea --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR24` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR24` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::FieldReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::FieldReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::FieldReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::FieldReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bits 8:15 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<8> { + TIMER_1_W::new(self) + } + #[doc = "Bits 16:23 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<16> { + TIMER_2_W::new(self) + } + #[doc = "Bits 24:31 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<24> { + TIMER_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 96 - 99 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr24](index.html) module"] +pub struct GICD_IPRIORITYR24_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr24::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR24_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr24::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR24_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR24 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR24_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs new file mode 100644 index 0000000..4b641b7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR25` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR25` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::FieldReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::FieldReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::FieldReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::FieldReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<0> { + H264_0_W::new(self) + } + #[doc = "Bits 8:15 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<8> { + H264_1_W::new(self) + } + #[doc = "Bits 16:23 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<16> { + H264_2_W::new(self) + } + #[doc = "Bits 24:31 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<24> { + JPEG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 100 - 103 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr25](index.html) module"] +pub struct GICD_IPRIORITYR25_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR25_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr25::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR25_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr25::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR25_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR25 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR25_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs new file mode 100644 index 0000000..eb37a1c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs @@ -0,0 +1,126 @@ +#[doc = "Register `GICD_IPRIORITYR26` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR26` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::FieldReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::FieldReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::FieldReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::FieldReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<0> { + ISP_W::new(self) + } + #[doc = "Bits 8:15 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<8> { + USB_W::new(self) + } + #[doc = "Bits 16:23 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<16> { + V3D_W::new(self) + } + #[doc = "Bits 24:31 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<24> { + TRANSPOSER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 104 - 107 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr26](index.html) module"] +pub struct GICD_IPRIORITYR26_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR26_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr26::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR26_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr26::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR26_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR26 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR26_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs new file mode 100644 index 0000000..bc2edba --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR27` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR27` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<0> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bits 8:15 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<8> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bits 16:23 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<16> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bits 24:31 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<24> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 108 - 111 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr27](index.html) module"] +pub struct GICD_IPRIORITYR27_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR27_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr27::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR27_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr27::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR27_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR27 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR27_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs new file mode 100644 index 0000000..3d2a0de --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR28` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR28` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::FieldReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::FieldReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::FieldReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::FieldReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<0> { + DMA_0_W::new(self) + } + #[doc = "Bits 8:15 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<8> { + DMA_1_W::new(self) + } + #[doc = "Bits 16:23 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<16> { + DMA_2_W::new(self) + } + #[doc = "Bits 24:31 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<24> { + DMA_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 112 - 115 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr28](index.html) module"] +pub struct GICD_IPRIORITYR28_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR28_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr28::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR28_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr28::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR28_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR28 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR28_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs new file mode 100644 index 0000000..6af1747 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR29` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR29` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::FieldReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::FieldReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::FieldReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::FieldReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<0> { + DMA_4_W::new(self) + } + #[doc = "Bits 8:15 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<8> { + DMA_5_W::new(self) + } + #[doc = "Bits 16:23 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<16> { + DMA_6_W::new(self) + } + #[doc = "Bits 24:31 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<24> { + DMA_7_8_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 116 - 119 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr29](index.html) module"] +pub struct GICD_IPRIORITYR29_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR29_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr29::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR29_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr29::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR29_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR29 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR29_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs new file mode 100644 index 0000000..51f3ec6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::FieldReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::FieldReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::FieldReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::FieldReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<0> { + INT12_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<8> { + INT13_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<16> { + INT14_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<24> { + INT15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 12 - 15 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr3](index.html) module"] +pub struct GICD_IPRIORITYR3_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr3::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr3::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR3 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs new file mode 100644 index 0000000..033026a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR30` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR30` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::FieldReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::FieldReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::FieldReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::FieldReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<0> { + DMA_9_10_W::new(self) + } + #[doc = "Bits 8:15 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<8> { + DMA_11_W::new(self) + } + #[doc = "Bits 16:23 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<16> { + DMA_12_W::new(self) + } + #[doc = "Bits 24:31 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<24> { + DMA_13_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 120 - 123 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr30](index.html) module"] +pub struct GICD_IPRIORITYR30_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR30_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr30::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR30_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr30::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR30_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR30 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR30_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs new file mode 100644 index 0000000..1f826ee --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_IPRIORITYR31` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR31` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::FieldReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::FieldReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::FieldReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::FieldReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<0> { + DMA_14_W::new(self) + } + #[doc = "Bits 8:15 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<8> { + AUX_W::new(self) + } + #[doc = "Bits 16:23 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<16> { + ARM_W::new(self) + } + #[doc = "Bits 24:31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<24> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 124 - 127 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr31](index.html) module"] +pub struct GICD_IPRIORITYR31_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR31_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr31::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR31_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr31::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR31_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR31 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR31_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs new file mode 100644 index 0000000..48637f3 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_IPRIORITYR32` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR32` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::FieldReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::FieldReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::FieldReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::FieldReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bits 8:15 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<8> { + HVS_W::new(self) + } + #[doc = "Bits 16:23 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<16> { + RPIVID_W::new(self) + } + #[doc = "Bits 24:31 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<24> { + SDC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 128 - 131 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr32](index.html) module"] +pub struct GICD_IPRIORITYR32_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr32::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR32_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr32::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR32_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR32 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR32_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs new file mode 100644 index 0000000..ea20e5c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::FieldReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::FieldReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::FieldReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<0> { + DSI_0_W::new(self) + } + #[doc = "Bits 8:15 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<8> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bits 16:23 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<16> { + CAMERA_0_W::new(self) + } + #[doc = "Bits 24:31 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<24> { + CAMERA_1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 132 - 135 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr33](index.html) module"] +pub struct GICD_IPRIORITYR33_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr33::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr33::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR33_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR33 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR33_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs new file mode 100644 index 0000000..4f20607 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR34` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR34` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::FieldReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::FieldReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::FieldReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<0> { + HDMI_0_W::new(self) + } + #[doc = "Bits 8:15 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<8> { + HDMI_1_W::new(self) + } + #[doc = "Bits 16:23 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<16> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bits 24:31 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<24> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 136 - 139 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr34](index.html) module"] +pub struct GICD_IPRIORITYR34_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR34_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr34::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR34_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr34::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR34_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR34 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR34_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs new file mode 100644 index 0000000..39dabab --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs @@ -0,0 +1,128 @@ +#[doc = "Register `GICD_IPRIORITYR35` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR35` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::FieldReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::FieldReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<0> { + DSI_1_W::new(self) + } + #[doc = "Bits 8:15 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<8> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bits 16:23 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<16> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bits 24:31 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<24> { + CPR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 140 - 143 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr35](index.html) module"] +pub struct GICD_IPRIORITYR35_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR35_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr35::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR35_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr35::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR35_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR35 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR35_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs new file mode 100644 index 0000000..a371367 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs @@ -0,0 +1,128 @@ +#[doc = "Register `GICD_IPRIORITYR36` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR36` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::FieldReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::FieldReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::FieldReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::FieldReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<0> { + SMI_W::new(self) + } + #[doc = "Bits 8:15 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<8> { + GPIO_0_W::new(self) + } + #[doc = "Bits 16:23 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<16> { + GPIO_1_W::new(self) + } + #[doc = "Bits 24:31 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<24> { + GPIO_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 144 - 147 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr36](index.html) module"] +pub struct GICD_IPRIORITYR36_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR36_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr36::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR36_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr36::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR36_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR36 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR36_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs new file mode 100644 index 0000000..cac90f2 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_IPRIORITYR37` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR37` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::FieldReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::FieldReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::FieldReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::FieldReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<0> { + GPIO_3_W::new(self) + } + #[doc = "Bits 8:15 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<8> { + I2C_W::new(self) + } + #[doc = "Bits 16:23 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<16> { + SPI_W::new(self) + } + #[doc = "Bits 24:31 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<24> { + PCM_I2S_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 148 - 151 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr37](index.html) module"] +pub struct GICD_IPRIORITYR37_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR37_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr37::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR37_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr37::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR37_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR37 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR37_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs new file mode 100644 index 0000000..3e53e17 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs @@ -0,0 +1,128 @@ +#[doc = "Register `GICD_IPRIORITYR38` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR38` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::FieldReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::FieldReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::FieldReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::FieldReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<0> { + SDHOST_W::new(self) + } + #[doc = "Bits 8:15 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<8> { + UART_W::new(self) + } + #[doc = "Bits 16:23 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<16> { + ETH_PCIE_W::new(self) + } + #[doc = "Bits 24:31 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<24> { + VEC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 152 - 155 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr38](index.html) module"] +pub struct GICD_IPRIORITYR38_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR38_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr38::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR38_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr38::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR38_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR38 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR38_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs new file mode 100644 index 0000000..8f843ad --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_IPRIORITYR39` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR39` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::FieldReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::FieldReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::FieldReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::FieldReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<0> { + CPG_W::new(self) + } + #[doc = "Bits 8:15 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<8> { + RNG_W::new(self) + } + #[doc = "Bits 16:23 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<16> { + EMMC_W::new(self) + } + #[doc = "Bits 24:31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<24> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 156 - 159 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr39](index.html) module"] +pub struct GICD_IPRIORITYR39_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR39_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr39::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR39_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr39::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR39_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR39 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR39_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs new file mode 100644 index 0000000..b2f7304 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::FieldReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::FieldReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::FieldReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::FieldReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<0> { + INT16_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<8> { + INT17_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<16> { + INT18_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<24> { + INT19_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 16 - 19 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr4](index.html) module"] +pub struct GICD_IPRIORITYR4_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr4::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr4::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR4 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs new file mode 100644 index 0000000..38b1963 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR40` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR40` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::FieldReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::FieldReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::FieldReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::FieldReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<8> { + INT161_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<16> { + INT162_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<24> { + INT163_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 160 - 163 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr40](index.html) module"] +pub struct GICD_IPRIORITYR40_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR40_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr40::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR40_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr40::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR40_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR40 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR40_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs new file mode 100644 index 0000000..8ad3688 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR41` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR41` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::FieldReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::FieldReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::FieldReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::FieldReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<0> { + INT164_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<8> { + INT165_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<16> { + INT166_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<24> { + INT167_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 164 - 167 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr41](index.html) module"] +pub struct GICD_IPRIORITYR41_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR41_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr41::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR41_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr41::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR41_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR41 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR41_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs new file mode 100644 index 0000000..38fa882 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR42` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR42` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::FieldReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::FieldReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::FieldReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::FieldReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<0> { + INT168_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<8> { + INT169_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<16> { + INT170_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<24> { + INT171_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 168 - 171 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr42](index.html) module"] +pub struct GICD_IPRIORITYR42_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR42_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr42::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR42_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr42::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR42_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR42 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR42_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs new file mode 100644 index 0000000..126b6c7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR43` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR43` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::FieldReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::FieldReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::FieldReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::FieldReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<0> { + INT172_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<8> { + INT173_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<16> { + INT174_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<24> { + INT175_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 172 - 175 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr43](index.html) module"] +pub struct GICD_IPRIORITYR43_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR43_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr43::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR43_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr43::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR43_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR43 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR43_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs new file mode 100644 index 0000000..9698e94 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR44` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR44` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::FieldReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::FieldReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::FieldReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::FieldReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<0> { + INT176_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<8> { + INT177_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<16> { + INT178_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<24> { + INT179_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 176 - 179 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr44](index.html) module"] +pub struct GICD_IPRIORITYR44_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR44_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr44::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR44_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr44::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR44_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR44 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR44_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs new file mode 100644 index 0000000..b18c757 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR45` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR45` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::FieldReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::FieldReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::FieldReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::FieldReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<0> { + INT180_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<8> { + INT181_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<16> { + INT182_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<24> { + INT183_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 180 - 183 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr45](index.html) module"] +pub struct GICD_IPRIORITYR45_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR45_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr45::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR45_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr45::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR45_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR45 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR45_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs new file mode 100644 index 0000000..032ba0d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR46` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR46` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::FieldReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::FieldReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::FieldReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::FieldReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<0> { + INT184_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<8> { + INT185_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<16> { + INT186_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<24> { + INT187_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 184 - 187 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr46](index.html) module"] +pub struct GICD_IPRIORITYR46_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR46_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr46::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR46_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr46::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR46_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR46 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR46_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs new file mode 100644 index 0000000..4a437b0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR47` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR47` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::FieldReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::FieldReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::FieldReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::FieldReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<0> { + INT188_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<8> { + INT189_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<16> { + INT190_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<24> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 188 - 191 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr47](index.html) module"] +pub struct GICD_IPRIORITYR47_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR47_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr47::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR47_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr47::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR47_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR47 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR47_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs new file mode 100644 index 0000000..a95f478 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR48` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR48` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::FieldReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::FieldReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::FieldReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::FieldReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<8> { + INT193_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<16> { + INT194_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<24> { + INT195_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 192 - 195 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr48](index.html) module"] +pub struct GICD_IPRIORITYR48_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr48::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR48_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr48::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR48_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR48 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR48_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs new file mode 100644 index 0000000..6dd8f6b --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR49` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR49` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::FieldReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::FieldReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::FieldReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::FieldReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<0> { + INT196_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<8> { + INT197_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<16> { + INT198_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<24> { + INT199_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 196 - 199 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr49](index.html) module"] +pub struct GICD_IPRIORITYR49_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR49_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr49::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR49_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr49::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR49_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR49 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR49_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs new file mode 100644 index 0000000..65379a1 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::FieldReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::FieldReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::FieldReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::FieldReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<0> { + INT20_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<8> { + INT21_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<16> { + INT22_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<24> { + INT23_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 20 - 23 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr5](index.html) module"] +pub struct GICD_IPRIORITYR5_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr5::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr5::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR5 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs new file mode 100644 index 0000000..1f4dced --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR50` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR50` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::FieldReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::FieldReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::FieldReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::FieldReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<0> { + INT200_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<8> { + INT201_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<16> { + INT202_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<24> { + INT203_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 200 - 203 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr50](index.html) module"] +pub struct GICD_IPRIORITYR50_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR50_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr50::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR50_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr50::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR50_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR50 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR50_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs new file mode 100644 index 0000000..f274e33 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR51` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR51` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::FieldReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::FieldReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::FieldReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::FieldReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<0> { + INT204_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<8> { + INT205_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<16> { + INT206_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<24> { + INT207_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 204 - 207 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr51](index.html) module"] +pub struct GICD_IPRIORITYR51_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR51_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr51::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR51_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr51::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR51_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR51 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR51_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs new file mode 100644 index 0000000..3e721b6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR52` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR52` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::FieldReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::FieldReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::FieldReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::FieldReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<0> { + INT208_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<8> { + INT209_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<16> { + INT210_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<24> { + INT211_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 208 - 211 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr52](index.html) module"] +pub struct GICD_IPRIORITYR52_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR52_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr52::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR52_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr52::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR52_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR52 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR52_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs new file mode 100644 index 0000000..53d4aad --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR53` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR53` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::FieldReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::FieldReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::FieldReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::FieldReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<0> { + INT212_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<8> { + INT213_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<16> { + INT214_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<24> { + INT215_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 212 - 215 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr53](index.html) module"] +pub struct GICD_IPRIORITYR53_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR53_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr53::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR53_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr53::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR53_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR53 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR53_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs new file mode 100644 index 0000000..ed4595e --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR54` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR54` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::FieldReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::FieldReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::FieldReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::FieldReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<0> { + INT216_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<8> { + INT217_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<16> { + INT218_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<24> { + INT219_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 216 - 219 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr54](index.html) module"] +pub struct GICD_IPRIORITYR54_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR54_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr54::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR54_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr54::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR54_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR54 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR54_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs new file mode 100644 index 0000000..42135d7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR55` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR55` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::FieldReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::FieldReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::FieldReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::FieldReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<0> { + INT220_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<8> { + INT221_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<16> { + INT222_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<24> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 220 - 223 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr55](index.html) module"] +pub struct GICD_IPRIORITYR55_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR55_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr55::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR55_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr55::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR55_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR55 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR55_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs new file mode 100644 index 0000000..dd002ac --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::FieldReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::FieldReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::FieldReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::FieldReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<0> { + INT24_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<8> { + INT25_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<16> { + INT26_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<24> { + INT27_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 24 - 27 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr6](index.html) module"] +pub struct GICD_IPRIORITYR6_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr6::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr6::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR6 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs new file mode 100644 index 0000000..eae5948 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::FieldReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::FieldReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::FieldReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::FieldReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<0> { + INT28_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<8> { + INT29_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<16> { + INT30_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<24> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 28 - 31 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr7](index.html) module"] +pub struct GICD_IPRIORITYR7_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr7::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr7::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR7 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs new file mode 100644 index 0000000..67db183 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::FieldReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::FieldReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::FieldReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::FieldReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<8> { + INT33_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<16> { + INT34_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<24> { + INT35_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 32 - 35 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr8](index.html) module"] +pub struct GICD_IPRIORITYR8_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr8::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr8::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR8_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR8 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs new file mode 100644 index 0000000..e41150a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_IPRIORITYR9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_IPRIORITYR9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::FieldReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::FieldReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::FieldReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::FieldReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<0> { + INT36_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<8> { + INT37_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<16> { + INT38_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<24> { + INT39_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Priority 36 - 39 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr9](index.html) module"] +pub struct GICD_IPRIORITYR9_SPEC; +impl crate::RegisterSpec for GICD_IPRIORITYR9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ipriorityr9::R](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr9::W](W) writer structure"] +impl crate::Writable for GICD_IPRIORITYR9_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_IPRIORITYR9 to value 0"] +impl crate::Resettable for GICD_IPRIORITYR9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs new file mode 100644 index 0000000..6d1dd03 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ISACTIVER { + #[doc = "0x00 - Interrupt Set-Active"] + pub gicd_isactiver0: GICD_ISACTIVER0, + #[doc = "0x04 - Interrupt Set-Active"] + pub gicd_isactiver1: GICD_ISACTIVER1, + #[doc = "0x08 - Interrupt Set-Active"] + pub gicd_isactiver2: GICD_ISACTIVER2, + #[doc = "0x0c - Interrupt Set-Active"] + pub gicd_isactiver3: GICD_ISACTIVER3, + #[doc = "0x10 - Interrupt Set-Active"] + pub gicd_isactiver4: GICD_ISACTIVER4, + #[doc = "0x14 - Interrupt Set-Active"] + pub gicd_isactiver5: GICD_ISACTIVER5, + #[doc = "0x18 - Interrupt Set-Active"] + pub gicd_isactiver6: GICD_ISACTIVER6, +} +#[doc = "GICD_ISACTIVER0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER0 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver0; +#[doc = "GICD_ISACTIVER1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER1 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver1; +#[doc = "GICD_ISACTIVER2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER2 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver2; +#[doc = "GICD_ISACTIVER3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER3 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver3; +#[doc = "GICD_ISACTIVER4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER4 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver4; +#[doc = "GICD_ISACTIVER5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER5 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver5; +#[doc = "GICD_ISACTIVER6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISACTIVER6 = crate::Reg; +#[doc = "Interrupt Set-Active"] +pub mod gicd_isactiver6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs new file mode 100644 index 0000000..ba46247 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISACTIVER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver0](index.html) module"] +pub struct GICD_ISACTIVER0_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver0::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver0::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER0 to value 0"] +impl crate::Resettable for GICD_ISACTIVER0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs new file mode 100644 index 0000000..f5242d6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISACTIVER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver1](index.html) module"] +pub struct GICD_ISACTIVER1_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver1::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver1::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER1 to value 0"] +impl crate::Resettable for GICD_ISACTIVER1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs new file mode 100644 index 0000000..79def40 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ISACTIVER2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver2](index.html) module"] +pub struct GICD_ISACTIVER2_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver2::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver2::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER2 to value 0"] +impl crate::Resettable for GICD_ISACTIVER2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs new file mode 100644 index 0000000..6632953 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ISACTIVER3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver3](index.html) module"] +pub struct GICD_ISACTIVER3_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver3::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver3::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER3 to value 0"] +impl crate::Resettable for GICD_ISACTIVER3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs new file mode 100644 index 0000000..dbbe1e6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs @@ -0,0 +1,551 @@ +#[doc = "Register `GICD_ISACTIVER4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver4](index.html) module"] +pub struct GICD_ISACTIVER4_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver4::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver4::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER4 to value 0"] +impl crate::Resettable for GICD_ISACTIVER4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs new file mode 100644 index 0000000..0e275c0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISACTIVER5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver5](index.html) module"] +pub struct GICD_ISACTIVER5_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver5::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver5::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER5 to value 0"] +impl crate::Resettable for GICD_ISACTIVER5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs new file mode 100644 index 0000000..e048a3a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISACTIVER6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISACTIVER6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver6](index.html) module"] +pub struct GICD_ISACTIVER6_SPEC; +impl crate::RegisterSpec for GICD_ISACTIVER6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isactiver6::R](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isactiver6::W](W) writer structure"] +impl crate::Writable for GICD_ISACTIVER6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISACTIVER6 to value 0"] +impl crate::Resettable for GICD_ISACTIVER6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs new file mode 100644 index 0000000..b7b571a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ISENABLER { + #[doc = "0x00 - Interrupt Set-Enable"] + pub gicd_isenabler0: GICD_ISENABLER0, + #[doc = "0x04 - Interrupt Set-Enable"] + pub gicd_isenabler1: GICD_ISENABLER1, + #[doc = "0x08 - Interrupt Set-Enable"] + pub gicd_isenabler2: GICD_ISENABLER2, + #[doc = "0x0c - Interrupt Set-Enable"] + pub gicd_isenabler3: GICD_ISENABLER3, + #[doc = "0x10 - Interrupt Set-Enable"] + pub gicd_isenabler4: GICD_ISENABLER4, + #[doc = "0x14 - Interrupt Set-Enable"] + pub gicd_isenabler5: GICD_ISENABLER5, + #[doc = "0x18 - Interrupt Set-Enable"] + pub gicd_isenabler6: GICD_ISENABLER6, +} +#[doc = "GICD_ISENABLER0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER0 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler0; +#[doc = "GICD_ISENABLER1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER1 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler1; +#[doc = "GICD_ISENABLER2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER2 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler2; +#[doc = "GICD_ISENABLER3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER3 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler3; +#[doc = "GICD_ISENABLER4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER4 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler4; +#[doc = "GICD_ISENABLER5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER5 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler5; +#[doc = "GICD_ISENABLER6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISENABLER6 = crate::Reg; +#[doc = "Interrupt Set-Enable"] +pub mod gicd_isenabler6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs new file mode 100644 index 0000000..339c946 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISENABLER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler0](index.html) module"] +pub struct GICD_ISENABLER0_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler0::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler0::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER0 to value 0"] +impl crate::Resettable for GICD_ISENABLER0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs new file mode 100644 index 0000000..77e0e02 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISENABLER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler1](index.html) module"] +pub struct GICD_ISENABLER1_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler1::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler1::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER1 to value 0"] +impl crate::Resettable for GICD_ISENABLER1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs new file mode 100644 index 0000000..154b7f7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ISENABLER2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler2](index.html) module"] +pub struct GICD_ISENABLER2_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler2::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler2::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER2 to value 0"] +impl crate::Resettable for GICD_ISENABLER2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs new file mode 100644 index 0000000..a0f74d5 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ISENABLER3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler3](index.html) module"] +pub struct GICD_ISENABLER3_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler3::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler3::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER3 to value 0"] +impl crate::Resettable for GICD_ISENABLER3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs new file mode 100644 index 0000000..8df3d2a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs @@ -0,0 +1,551 @@ +#[doc = "Register `GICD_ISENABLER4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler4](index.html) module"] +pub struct GICD_ISENABLER4_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler4::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler4::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER4 to value 0"] +impl crate::Resettable for GICD_ISENABLER4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs new file mode 100644 index 0000000..70f96b0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISENABLER5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler5](index.html) module"] +pub struct GICD_ISENABLER5_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler5::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler5::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER5 to value 0"] +impl crate::Resettable for GICD_ISENABLER5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs new file mode 100644 index 0000000..3d95a3a --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISENABLER6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISENABLER6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler6](index.html) module"] +pub struct GICD_ISENABLER6_SPEC; +impl crate::RegisterSpec for GICD_ISENABLER6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_isenabler6::R](R) reader structure"] +impl crate::Readable for GICD_ISENABLER6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_isenabler6::W](W) writer structure"] +impl crate::Writable for GICD_ISENABLER6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISENABLER6 to value 0"] +impl crate::Resettable for GICD_ISENABLER6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs new file mode 100644 index 0000000..72a608b --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ISPENDR { + #[doc = "0x00 - Interrupt Set-Pending"] + pub gicd_ispendr0: GICD_ISPENDR0, + #[doc = "0x04 - Interrupt Set-Pending"] + pub gicd_ispendr1: GICD_ISPENDR1, + #[doc = "0x08 - Interrupt Set-Pending"] + pub gicd_ispendr2: GICD_ISPENDR2, + #[doc = "0x0c - Interrupt Set-Pending"] + pub gicd_ispendr3: GICD_ISPENDR3, + #[doc = "0x10 - Interrupt Set-Pending"] + pub gicd_ispendr4: GICD_ISPENDR4, + #[doc = "0x14 - Interrupt Set-Pending"] + pub gicd_ispendr5: GICD_ISPENDR5, + #[doc = "0x18 - Interrupt Set-Pending"] + pub gicd_ispendr6: GICD_ISPENDR6, +} +#[doc = "GICD_ISPENDR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR0 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr0; +#[doc = "GICD_ISPENDR1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR1 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr1; +#[doc = "GICD_ISPENDR2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR2 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr2; +#[doc = "GICD_ISPENDR3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR3 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr3; +#[doc = "GICD_ISPENDR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR4 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr4; +#[doc = "GICD_ISPENDR5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR5 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr5; +#[doc = "GICD_ISPENDR6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ISPENDR6 = crate::Reg; +#[doc = "Interrupt Set-Pending"] +pub mod gicd_ispendr6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs new file mode 100644 index 0000000..d8bdd51 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISPENDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr0](index.html) module"] +pub struct GICD_ISPENDR0_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr0::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr0::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR0 to value 0"] +impl crate::Resettable for GICD_ISPENDR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs new file mode 100644 index 0000000..115b2fa --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISPENDR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr1](index.html) module"] +pub struct GICD_ISPENDR1_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr1::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr1::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR1 to value 0"] +impl crate::Resettable for GICD_ISPENDR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs new file mode 100644 index 0000000..0b297a9 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs @@ -0,0 +1,547 @@ +#[doc = "Register `GICD_ISPENDR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::BitReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::BitReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::BitReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::BitReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::BitReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::BitReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::BitReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::BitReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::BitReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::BitReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::BitReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::BitReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::BitReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::BitReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::BitReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::BitReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<16> { + INT80_W::new(self) + } + #[doc = "Bit 17 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<17> { + INT81_W::new(self) + } + #[doc = "Bit 18 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<18> { + INT82_W::new(self) + } + #[doc = "Bit 19 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<19> { + INT83_W::new(self) + } + #[doc = "Bit 20 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<20> { + INT84_W::new(self) + } + #[doc = "Bit 21 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<21> { + INT85_W::new(self) + } + #[doc = "Bit 22 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<22> { + INT86_W::new(self) + } + #[doc = "Bit 23 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<23> { + INT87_W::new(self) + } + #[doc = "Bit 24 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<24> { + INT88_W::new(self) + } + #[doc = "Bit 25 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<25> { + INT89_W::new(self) + } + #[doc = "Bit 26 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<26> { + INT90_W::new(self) + } + #[doc = "Bit 27 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<27> { + INT91_W::new(self) + } + #[doc = "Bit 28 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<28> { + INT92_W::new(self) + } + #[doc = "Bit 29 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<29> { + INT93_W::new(self) + } + #[doc = "Bit 30 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<30> { + INT94_W::new(self) + } + #[doc = "Bit 31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<31> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr2](index.html) module"] +pub struct GICD_ISPENDR2_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr2::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr2::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR2 to value 0"] +impl crate::Resettable for GICD_ISPENDR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs new file mode 100644 index 0000000..57a445c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs @@ -0,0 +1,549 @@ +#[doc = "Register `GICD_ISPENDR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr3](index.html) module"] +pub struct GICD_ISPENDR3_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr3::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr3::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR3 to value 0"] +impl crate::Resettable for GICD_ISPENDR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs new file mode 100644 index 0000000..bd4613e --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs @@ -0,0 +1,551 @@ +#[doc = "Register `GICD_ISPENDR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr4](index.html) module"] +pub struct GICD_ISPENDR4_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr4::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr4::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR4 to value 0"] +impl crate::Resettable for GICD_ISPENDR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs new file mode 100644 index 0000000..09a9a25 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISPENDR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::BitReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::BitReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::BitReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::BitReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::BitReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::BitReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::BitReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::BitReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::BitReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::BitReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::BitReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::BitReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::BitReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::BitReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::BitReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::BitReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::BitReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::BitReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::BitReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::BitReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::BitReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::BitReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::BitReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::BitReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::BitReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::BitReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::BitReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::BitReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::BitReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::BitReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::BitReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::BitReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bit 1 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<1> { + INT161_W::new(self) + } + #[doc = "Bit 2 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<2> { + INT162_W::new(self) + } + #[doc = "Bit 3 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<3> { + INT163_W::new(self) + } + #[doc = "Bit 4 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<4> { + INT164_W::new(self) + } + #[doc = "Bit 5 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<5> { + INT165_W::new(self) + } + #[doc = "Bit 6 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<6> { + INT166_W::new(self) + } + #[doc = "Bit 7 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<7> { + INT167_W::new(self) + } + #[doc = "Bit 8 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<8> { + INT168_W::new(self) + } + #[doc = "Bit 9 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<9> { + INT169_W::new(self) + } + #[doc = "Bit 10 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<10> { + INT170_W::new(self) + } + #[doc = "Bit 11 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<11> { + INT171_W::new(self) + } + #[doc = "Bit 12 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<12> { + INT172_W::new(self) + } + #[doc = "Bit 13 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<13> { + INT173_W::new(self) + } + #[doc = "Bit 14 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<14> { + INT174_W::new(self) + } + #[doc = "Bit 15 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<15> { + INT175_W::new(self) + } + #[doc = "Bit 16 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<16> { + INT176_W::new(self) + } + #[doc = "Bit 17 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<17> { + INT177_W::new(self) + } + #[doc = "Bit 18 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<18> { + INT178_W::new(self) + } + #[doc = "Bit 19 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<19> { + INT179_W::new(self) + } + #[doc = "Bit 20 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<20> { + INT180_W::new(self) + } + #[doc = "Bit 21 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<21> { + INT181_W::new(self) + } + #[doc = "Bit 22 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<22> { + INT182_W::new(self) + } + #[doc = "Bit 23 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<23> { + INT183_W::new(self) + } + #[doc = "Bit 24 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<24> { + INT184_W::new(self) + } + #[doc = "Bit 25 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<25> { + INT185_W::new(self) + } + #[doc = "Bit 26 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<26> { + INT186_W::new(self) + } + #[doc = "Bit 27 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<27> { + INT187_W::new(self) + } + #[doc = "Bit 28 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<28> { + INT188_W::new(self) + } + #[doc = "Bit 29 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<29> { + INT189_W::new(self) + } + #[doc = "Bit 30 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<30> { + INT190_W::new(self) + } + #[doc = "Bit 31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<31> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr5](index.html) module"] +pub struct GICD_ISPENDR5_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr5::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr5::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR5 to value 0"] +impl crate::Resettable for GICD_ISPENDR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs new file mode 100644 index 0000000..61d1a24 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_ISPENDR6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ISPENDR6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::BitReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::BitReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::BitReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::BitReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::BitReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::BitReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::BitReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::BitReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::BitReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::BitReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::BitReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::BitReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::BitReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::BitReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::BitReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::BitReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::BitReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::BitReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::BitReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::BitReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::BitReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::BitReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::BitReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::BitReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::BitReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::BitReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::BitReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::BitReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::BitReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::BitReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::BitReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::BitReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bit 1 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<1> { + INT193_W::new(self) + } + #[doc = "Bit 2 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<2> { + INT194_W::new(self) + } + #[doc = "Bit 3 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<3> { + INT195_W::new(self) + } + #[doc = "Bit 4 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<4> { + INT196_W::new(self) + } + #[doc = "Bit 5 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<5> { + INT197_W::new(self) + } + #[doc = "Bit 6 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<6> { + INT198_W::new(self) + } + #[doc = "Bit 7 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<7> { + INT199_W::new(self) + } + #[doc = "Bit 8 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<8> { + INT200_W::new(self) + } + #[doc = "Bit 9 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<9> { + INT201_W::new(self) + } + #[doc = "Bit 10 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<10> { + INT202_W::new(self) + } + #[doc = "Bit 11 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<11> { + INT203_W::new(self) + } + #[doc = "Bit 12 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<12> { + INT204_W::new(self) + } + #[doc = "Bit 13 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<13> { + INT205_W::new(self) + } + #[doc = "Bit 14 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<14> { + INT206_W::new(self) + } + #[doc = "Bit 15 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<15> { + INT207_W::new(self) + } + #[doc = "Bit 16 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<16> { + INT208_W::new(self) + } + #[doc = "Bit 17 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<17> { + INT209_W::new(self) + } + #[doc = "Bit 18 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<18> { + INT210_W::new(self) + } + #[doc = "Bit 19 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<19> { + INT211_W::new(self) + } + #[doc = "Bit 20 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<20> { + INT212_W::new(self) + } + #[doc = "Bit 21 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<21> { + INT213_W::new(self) + } + #[doc = "Bit 22 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<22> { + INT214_W::new(self) + } + #[doc = "Bit 23 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<23> { + INT215_W::new(self) + } + #[doc = "Bit 24 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<24> { + INT216_W::new(self) + } + #[doc = "Bit 25 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<25> { + INT217_W::new(self) + } + #[doc = "Bit 26 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<26> { + INT218_W::new(self) + } + #[doc = "Bit 27 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<27> { + INT219_W::new(self) + } + #[doc = "Bit 28 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<28> { + INT220_W::new(self) + } + #[doc = "Bit 29 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<29> { + INT221_W::new(self) + } + #[doc = "Bit 30 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<30> { + INT222_W::new(self) + } + #[doc = "Bit 31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<31> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr6](index.html) module"] +pub struct GICD_ISPENDR6_SPEC; +impl crate::RegisterSpec for GICD_ISPENDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ispendr6::R](R) reader structure"] +impl crate::Readable for GICD_ISPENDR6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ispendr6::W](W) writer structure"] +impl crate::Writable for GICD_ISPENDR6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets GICD_ISPENDR6 to value 0"] +impl crate::Resettable for GICD_ISPENDR6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs new file mode 100644 index 0000000..22fe1fe --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs @@ -0,0 +1,340 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct GICD_ITARGETSR { + #[doc = "0x00 - Interrupt Processor Target 0 - 3"] + pub gicd_itargetsr0: GICD_ITARGETSR0, + #[doc = "0x04 - Interrupt Processor Target 4 - 7"] + pub gicd_itargetsr1: GICD_ITARGETSR1, + #[doc = "0x08 - Interrupt Processor Target 8 - 11"] + pub gicd_itargetsr2: GICD_ITARGETSR2, + #[doc = "0x0c - Interrupt Processor Target 12 - 15"] + pub gicd_itargetsr3: GICD_ITARGETSR3, + #[doc = "0x10 - Interrupt Processor Target 16 - 19"] + pub gicd_itargetsr4: GICD_ITARGETSR4, + #[doc = "0x14 - Interrupt Processor Target 20 - 23"] + pub gicd_itargetsr5: GICD_ITARGETSR5, + #[doc = "0x18 - Interrupt Processor Target 24 - 27"] + pub gicd_itargetsr6: GICD_ITARGETSR6, + #[doc = "0x1c - Interrupt Processor Target 28 - 31"] + pub gicd_itargetsr7: GICD_ITARGETSR7, + #[doc = "0x20 - Interrupt Processor Target 32 - 35"] + pub gicd_itargetsr8: GICD_ITARGETSR8, + #[doc = "0x24 - Interrupt Processor Target 36 - 39"] + pub gicd_itargetsr9: GICD_ITARGETSR9, + #[doc = "0x28 - Interrupt Processor Target 40 - 43"] + pub gicd_itargetsr10: GICD_ITARGETSR10, + #[doc = "0x2c - Interrupt Processor Target 44 - 47"] + pub gicd_itargetsr11: GICD_ITARGETSR11, + #[doc = "0x30 - Interrupt Processor Target 48 - 51"] + pub gicd_itargetsr12: GICD_ITARGETSR12, + #[doc = "0x34 - Interrupt Processor Target 52 - 55"] + pub gicd_itargetsr13: GICD_ITARGETSR13, + #[doc = "0x38 - Interrupt Processor Target 56 - 59"] + pub gicd_itargetsr14: GICD_ITARGETSR14, + #[doc = "0x3c - Interrupt Processor Target 60 - 63"] + pub gicd_itargetsr15: GICD_ITARGETSR15, + #[doc = "0x40 - Interrupt Processor Target 64 - 67"] + pub gicd_itargetsr16: GICD_ITARGETSR16, + #[doc = "0x44 - Interrupt Processor Target 68 - 71"] + pub gicd_itargetsr17: GICD_ITARGETSR17, + #[doc = "0x48 - Interrupt Processor Target 72 - 75"] + pub gicd_itargetsr18: GICD_ITARGETSR18, + #[doc = "0x4c - Interrupt Processor Target 76 - 79"] + pub gicd_itargetsr19: GICD_ITARGETSR19, + #[doc = "0x50 - Interrupt Processor Target 80 - 83"] + pub gicd_itargetsr20: GICD_ITARGETSR20, + #[doc = "0x54 - Interrupt Processor Target 84 - 87"] + pub gicd_itargetsr21: GICD_ITARGETSR21, + #[doc = "0x58 - Interrupt Processor Target 88 - 91"] + pub gicd_itargetsr22: GICD_ITARGETSR22, + #[doc = "0x5c - Interrupt Processor Target 92 - 95"] + pub gicd_itargetsr23: GICD_ITARGETSR23, + #[doc = "0x60 - Interrupt Processor Target 96 - 99"] + pub gicd_itargetsr24: GICD_ITARGETSR24, + #[doc = "0x64 - Interrupt Processor Target 100 - 103"] + pub gicd_itargetsr25: GICD_ITARGETSR25, + #[doc = "0x68 - Interrupt Processor Target 104 - 107"] + pub gicd_itargetsr26: GICD_ITARGETSR26, + #[doc = "0x6c - Interrupt Processor Target 108 - 111"] + pub gicd_itargetsr27: GICD_ITARGETSR27, + #[doc = "0x70 - Interrupt Processor Target 112 - 115"] + pub gicd_itargetsr28: GICD_ITARGETSR28, + #[doc = "0x74 - Interrupt Processor Target 116 - 119"] + pub gicd_itargetsr29: GICD_ITARGETSR29, + #[doc = "0x78 - Interrupt Processor Target 120 - 123"] + pub gicd_itargetsr30: GICD_ITARGETSR30, + #[doc = "0x7c - Interrupt Processor Target 124 - 127"] + pub gicd_itargetsr31: GICD_ITARGETSR31, + #[doc = "0x80 - Interrupt Processor Target 128 - 131"] + pub gicd_itargetsr32: GICD_ITARGETSR32, + #[doc = "0x84 - Interrupt Processor Target 132 - 135"] + pub gicd_itargetsr33: GICD_ITARGETSR33, + #[doc = "0x88 - Interrupt Processor Target 136 - 139"] + pub gicd_itargetsr34: GICD_ITARGETSR34, + #[doc = "0x8c - Interrupt Processor Target 140 - 143"] + pub gicd_itargetsr35: GICD_ITARGETSR35, + #[doc = "0x90 - Interrupt Processor Target 144 - 147"] + pub gicd_itargetsr36: GICD_ITARGETSR36, + #[doc = "0x94 - Interrupt Processor Target 148 - 151"] + pub gicd_itargetsr37: GICD_ITARGETSR37, + #[doc = "0x98 - Interrupt Processor Target 152 - 155"] + pub gicd_itargetsr38: GICD_ITARGETSR38, + #[doc = "0x9c - Interrupt Processor Target 156 - 159"] + pub gicd_itargetsr39: GICD_ITARGETSR39, + #[doc = "0xa0 - Interrupt Processor Target 160 - 163"] + pub gicd_itargetsr40: GICD_ITARGETSR40, + #[doc = "0xa4 - Interrupt Processor Target 164 - 167"] + pub gicd_itargetsr41: GICD_ITARGETSR41, + #[doc = "0xa8 - Interrupt Processor Target 168 - 171"] + pub gicd_itargetsr42: GICD_ITARGETSR42, + #[doc = "0xac - Interrupt Processor Target 172 - 175"] + pub gicd_itargetsr43: GICD_ITARGETSR43, + #[doc = "0xb0 - Interrupt Processor Target 176 - 179"] + pub gicd_itargetsr44: GICD_ITARGETSR44, + #[doc = "0xb4 - Interrupt Processor Target 180 - 183"] + pub gicd_itargetsr45: GICD_ITARGETSR45, + #[doc = "0xb8 - Interrupt Processor Target 184 - 187"] + pub gicd_itargetsr46: GICD_ITARGETSR46, + #[doc = "0xbc - Interrupt Processor Target 188 - 191"] + pub gicd_itargetsr47: GICD_ITARGETSR47, + #[doc = "0xc0 - Interrupt Processor Target 192 - 195"] + pub gicd_itargetsr48: GICD_ITARGETSR48, + #[doc = "0xc4 - Interrupt Processor Target 196 - 199"] + pub gicd_itargetsr49: GICD_ITARGETSR49, + #[doc = "0xc8 - Interrupt Processor Target 200 - 203"] + pub gicd_itargetsr50: GICD_ITARGETSR50, + #[doc = "0xcc - Interrupt Processor Target 204 - 207"] + pub gicd_itargetsr51: GICD_ITARGETSR51, + #[doc = "0xd0 - Interrupt Processor Target 208 - 211"] + pub gicd_itargetsr52: GICD_ITARGETSR52, + #[doc = "0xd4 - Interrupt Processor Target 212 - 215"] + pub gicd_itargetsr53: GICD_ITARGETSR53, + #[doc = "0xd8 - Interrupt Processor Target 216 - 219"] + pub gicd_itargetsr54: GICD_ITARGETSR54, + #[doc = "0xdc - Interrupt Processor Target 220 - 223"] + pub gicd_itargetsr55: GICD_ITARGETSR55, +} +#[doc = "GICD_ITARGETSR0 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR0 = crate::Reg; +#[doc = "Interrupt Processor Target 0 - 3"] +pub mod gicd_itargetsr0; +#[doc = "GICD_ITARGETSR1 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR1 = crate::Reg; +#[doc = "Interrupt Processor Target 4 - 7"] +pub mod gicd_itargetsr1; +#[doc = "GICD_ITARGETSR2 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR2 = crate::Reg; +#[doc = "Interrupt Processor Target 8 - 11"] +pub mod gicd_itargetsr2; +#[doc = "GICD_ITARGETSR3 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR3 = crate::Reg; +#[doc = "Interrupt Processor Target 12 - 15"] +pub mod gicd_itargetsr3; +#[doc = "GICD_ITARGETSR4 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR4 = crate::Reg; +#[doc = "Interrupt Processor Target 16 - 19"] +pub mod gicd_itargetsr4; +#[doc = "GICD_ITARGETSR5 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR5 = crate::Reg; +#[doc = "Interrupt Processor Target 20 - 23"] +pub mod gicd_itargetsr5; +#[doc = "GICD_ITARGETSR6 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR6 = crate::Reg; +#[doc = "Interrupt Processor Target 24 - 27"] +pub mod gicd_itargetsr6; +#[doc = "GICD_ITARGETSR7 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR7 = crate::Reg; +#[doc = "Interrupt Processor Target 28 - 31"] +pub mod gicd_itargetsr7; +#[doc = "GICD_ITARGETSR8 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR8 = crate::Reg; +#[doc = "Interrupt Processor Target 32 - 35"] +pub mod gicd_itargetsr8; +#[doc = "GICD_ITARGETSR9 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR9 = crate::Reg; +#[doc = "Interrupt Processor Target 36 - 39"] +pub mod gicd_itargetsr9; +#[doc = "GICD_ITARGETSR10 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR10 = crate::Reg; +#[doc = "Interrupt Processor Target 40 - 43"] +pub mod gicd_itargetsr10; +#[doc = "GICD_ITARGETSR11 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR11 = crate::Reg; +#[doc = "Interrupt Processor Target 44 - 47"] +pub mod gicd_itargetsr11; +#[doc = "GICD_ITARGETSR12 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR12 = crate::Reg; +#[doc = "Interrupt Processor Target 48 - 51"] +pub mod gicd_itargetsr12; +#[doc = "GICD_ITARGETSR13 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR13 = crate::Reg; +#[doc = "Interrupt Processor Target 52 - 55"] +pub mod gicd_itargetsr13; +#[doc = "GICD_ITARGETSR14 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR14 = crate::Reg; +#[doc = "Interrupt Processor Target 56 - 59"] +pub mod gicd_itargetsr14; +#[doc = "GICD_ITARGETSR15 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR15 = crate::Reg; +#[doc = "Interrupt Processor Target 60 - 63"] +pub mod gicd_itargetsr15; +#[doc = "GICD_ITARGETSR16 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR16 = crate::Reg; +#[doc = "Interrupt Processor Target 64 - 67"] +pub mod gicd_itargetsr16; +#[doc = "GICD_ITARGETSR17 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR17 = crate::Reg; +#[doc = "Interrupt Processor Target 68 - 71"] +pub mod gicd_itargetsr17; +#[doc = "GICD_ITARGETSR18 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR18 = crate::Reg; +#[doc = "Interrupt Processor Target 72 - 75"] +pub mod gicd_itargetsr18; +#[doc = "GICD_ITARGETSR19 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR19 = crate::Reg; +#[doc = "Interrupt Processor Target 76 - 79"] +pub mod gicd_itargetsr19; +#[doc = "GICD_ITARGETSR20 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR20 = crate::Reg; +#[doc = "Interrupt Processor Target 80 - 83"] +pub mod gicd_itargetsr20; +#[doc = "GICD_ITARGETSR21 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR21 = crate::Reg; +#[doc = "Interrupt Processor Target 84 - 87"] +pub mod gicd_itargetsr21; +#[doc = "GICD_ITARGETSR22 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR22 = crate::Reg; +#[doc = "Interrupt Processor Target 88 - 91"] +pub mod gicd_itargetsr22; +#[doc = "GICD_ITARGETSR23 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR23 = crate::Reg; +#[doc = "Interrupt Processor Target 92 - 95"] +pub mod gicd_itargetsr23; +#[doc = "GICD_ITARGETSR24 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR24 = crate::Reg; +#[doc = "Interrupt Processor Target 96 - 99"] +pub mod gicd_itargetsr24; +#[doc = "GICD_ITARGETSR25 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR25 = crate::Reg; +#[doc = "Interrupt Processor Target 100 - 103"] +pub mod gicd_itargetsr25; +#[doc = "GICD_ITARGETSR26 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR26 = crate::Reg; +#[doc = "Interrupt Processor Target 104 - 107"] +pub mod gicd_itargetsr26; +#[doc = "GICD_ITARGETSR27 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR27 = crate::Reg; +#[doc = "Interrupt Processor Target 108 - 111"] +pub mod gicd_itargetsr27; +#[doc = "GICD_ITARGETSR28 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR28 = crate::Reg; +#[doc = "Interrupt Processor Target 112 - 115"] +pub mod gicd_itargetsr28; +#[doc = "GICD_ITARGETSR29 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR29 = crate::Reg; +#[doc = "Interrupt Processor Target 116 - 119"] +pub mod gicd_itargetsr29; +#[doc = "GICD_ITARGETSR30 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR30 = crate::Reg; +#[doc = "Interrupt Processor Target 120 - 123"] +pub mod gicd_itargetsr30; +#[doc = "GICD_ITARGETSR31 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR31 = crate::Reg; +#[doc = "Interrupt Processor Target 124 - 127"] +pub mod gicd_itargetsr31; +#[doc = "GICD_ITARGETSR32 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR32 = crate::Reg; +#[doc = "Interrupt Processor Target 128 - 131"] +pub mod gicd_itargetsr32; +#[doc = "GICD_ITARGETSR33 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR33 = crate::Reg; +#[doc = "Interrupt Processor Target 132 - 135"] +pub mod gicd_itargetsr33; +#[doc = "GICD_ITARGETSR34 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR34 = crate::Reg; +#[doc = "Interrupt Processor Target 136 - 139"] +pub mod gicd_itargetsr34; +#[doc = "GICD_ITARGETSR35 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR35 = crate::Reg; +#[doc = "Interrupt Processor Target 140 - 143"] +pub mod gicd_itargetsr35; +#[doc = "GICD_ITARGETSR36 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR36 = crate::Reg; +#[doc = "Interrupt Processor Target 144 - 147"] +pub mod gicd_itargetsr36; +#[doc = "GICD_ITARGETSR37 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR37 = crate::Reg; +#[doc = "Interrupt Processor Target 148 - 151"] +pub mod gicd_itargetsr37; +#[doc = "GICD_ITARGETSR38 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR38 = crate::Reg; +#[doc = "Interrupt Processor Target 152 - 155"] +pub mod gicd_itargetsr38; +#[doc = "GICD_ITARGETSR39 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR39 = crate::Reg; +#[doc = "Interrupt Processor Target 156 - 159"] +pub mod gicd_itargetsr39; +#[doc = "GICD_ITARGETSR40 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR40 = crate::Reg; +#[doc = "Interrupt Processor Target 160 - 163"] +pub mod gicd_itargetsr40; +#[doc = "GICD_ITARGETSR41 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR41 = crate::Reg; +#[doc = "Interrupt Processor Target 164 - 167"] +pub mod gicd_itargetsr41; +#[doc = "GICD_ITARGETSR42 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR42 = crate::Reg; +#[doc = "Interrupt Processor Target 168 - 171"] +pub mod gicd_itargetsr42; +#[doc = "GICD_ITARGETSR43 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR43 = crate::Reg; +#[doc = "Interrupt Processor Target 172 - 175"] +pub mod gicd_itargetsr43; +#[doc = "GICD_ITARGETSR44 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR44 = crate::Reg; +#[doc = "Interrupt Processor Target 176 - 179"] +pub mod gicd_itargetsr44; +#[doc = "GICD_ITARGETSR45 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR45 = crate::Reg; +#[doc = "Interrupt Processor Target 180 - 183"] +pub mod gicd_itargetsr45; +#[doc = "GICD_ITARGETSR46 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR46 = crate::Reg; +#[doc = "Interrupt Processor Target 184 - 187"] +pub mod gicd_itargetsr46; +#[doc = "GICD_ITARGETSR47 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR47 = crate::Reg; +#[doc = "Interrupt Processor Target 188 - 191"] +pub mod gicd_itargetsr47; +#[doc = "GICD_ITARGETSR48 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR48 = crate::Reg; +#[doc = "Interrupt Processor Target 192 - 195"] +pub mod gicd_itargetsr48; +#[doc = "GICD_ITARGETSR49 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR49 = crate::Reg; +#[doc = "Interrupt Processor Target 196 - 199"] +pub mod gicd_itargetsr49; +#[doc = "GICD_ITARGETSR50 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR50 = crate::Reg; +#[doc = "Interrupt Processor Target 200 - 203"] +pub mod gicd_itargetsr50; +#[doc = "GICD_ITARGETSR51 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR51 = crate::Reg; +#[doc = "Interrupt Processor Target 204 - 207"] +pub mod gicd_itargetsr51; +#[doc = "GICD_ITARGETSR52 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR52 = crate::Reg; +#[doc = "Interrupt Processor Target 208 - 211"] +pub mod gicd_itargetsr52; +#[doc = "GICD_ITARGETSR53 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR53 = crate::Reg; +#[doc = "Interrupt Processor Target 212 - 215"] +pub mod gicd_itargetsr53; +#[doc = "GICD_ITARGETSR54 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR54 = crate::Reg; +#[doc = "Interrupt Processor Target 216 - 219"] +pub mod gicd_itargetsr54; +#[doc = "GICD_ITARGETSR55 (rw) register accessor: an alias for `Reg`"] +pub type GICD_ITARGETSR55 = crate::Reg; +#[doc = "Interrupt Processor Target 220 - 223"] +pub mod gicd_itargetsr55; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs new file mode 100644 index 0000000..5ff6216 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::FieldReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::FieldReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::FieldReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::FieldReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<8> { + INT1_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<16> { + INT2_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<24> { + INT3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 0 - 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr0](index.html) module"] +pub struct GICD_ITARGETSR0_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr0::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr0::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR0 to value 0"] +impl crate::Resettable for GICD_ITARGETSR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs new file mode 100644 index 0000000..b2e62dd --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::FieldReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::FieldReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::FieldReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::FieldReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<0> { + INT4_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<8> { + INT5_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<16> { + INT6_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<24> { + INT7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 4 - 7\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr1](index.html) module"] +pub struct GICD_ITARGETSR1_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr1::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr1::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR1 to value 0"] +impl crate::Resettable for GICD_ITARGETSR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs new file mode 100644 index 0000000..c1a701c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::FieldReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::FieldReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::FieldReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::FieldReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<0> { + INT40_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<8> { + INT41_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<16> { + INT42_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<24> { + INT43_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 40 - 43\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr10](index.html) module"] +pub struct GICD_ITARGETSR10_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr10::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr10::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR10_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR10 to value 0"] +impl crate::Resettable for GICD_ITARGETSR10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs new file mode 100644 index 0000000..a5378bb --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::FieldReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::FieldReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::FieldReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::FieldReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<0> { + INT44_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<8> { + INT45_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<16> { + INT46_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<24> { + INT47_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 44 - 47\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr11](index.html) module"] +pub struct GICD_ITARGETSR11_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr11::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr11::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR11_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR11 to value 0"] +impl crate::Resettable for GICD_ITARGETSR11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs new file mode 100644 index 0000000..d479178 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::FieldReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::FieldReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::FieldReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::FieldReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<0> { + INT48_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<8> { + INT49_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<16> { + INT50_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<24> { + INT51_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 48 - 51\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr12](index.html) module"] +pub struct GICD_ITARGETSR12_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr12::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr12::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR12_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR12 to value 0"] +impl crate::Resettable for GICD_ITARGETSR12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs new file mode 100644 index 0000000..0917102 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::FieldReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::FieldReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::FieldReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::FieldReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<0> { + INT52_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<8> { + INT53_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<16> { + INT54_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<24> { + INT55_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 52 - 55\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr13](index.html) module"] +pub struct GICD_ITARGETSR13_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr13::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr13::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR13_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR13 to value 0"] +impl crate::Resettable for GICD_ITARGETSR13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs new file mode 100644 index 0000000..a8677c1 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::FieldReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::FieldReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::FieldReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::FieldReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<0> { + INT56_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<8> { + INT57_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<16> { + INT58_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<24> { + INT59_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 56 - 59\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr14](index.html) module"] +pub struct GICD_ITARGETSR14_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr14::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr14::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR14_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR14 to value 0"] +impl crate::Resettable for GICD_ITARGETSR14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs new file mode 100644 index 0000000..9733ca2 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR15` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR15` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::FieldReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::FieldReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::FieldReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::FieldReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<0> { + INT60_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<8> { + INT61_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<16> { + INT62_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<24> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 60 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr15](index.html) module"] +pub struct GICD_ITARGETSR15_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr15::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR15_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr15::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR15_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR15 to value 0"] +impl crate::Resettable for GICD_ITARGETSR15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs new file mode 100644 index 0000000..3382e16 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR16` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR16` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::FieldReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::FieldReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::FieldReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::FieldReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bits 8:15 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<8> { + MAILBOX_W::new(self) + } + #[doc = "Bits 16:23 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<16> { + DOORBELL0_W::new(self) + } + #[doc = "Bits 24:31 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<24> { + DOORBELL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 64 - 67\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr16](index.html) module"] +pub struct GICD_ITARGETSR16_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr16::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR16_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr16::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR16_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR16 to value 0"] +impl crate::Resettable for GICD_ITARGETSR16_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs new file mode 100644 index 0000000..b077d1f --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR17` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR17` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::FieldReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::FieldReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::FieldReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::FieldReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<0> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bits 8:15 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<8> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bits 16:23 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<16> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bits 24:31 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<24> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 68 - 71\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr17](index.html) module"] +pub struct GICD_ITARGETSR17_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr17::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR17_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr17::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR17_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR17 to value 0"] +impl crate::Resettable for GICD_ITARGETSR17_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs new file mode 100644 index 0000000..50ca471 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR18` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR18` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::FieldReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::FieldReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::FieldReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::FieldReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<0> { + SWI0_W::new(self) + } + #[doc = "Bits 8:15 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<8> { + SWI1_W::new(self) + } + #[doc = "Bits 16:23 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<16> { + SWI2_W::new(self) + } + #[doc = "Bits 24:31 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<24> { + SWI3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 72 - 75\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr18](index.html) module"] +pub struct GICD_ITARGETSR18_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR18_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr18::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR18_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr18::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR18_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR18 to value 0"] +impl crate::Resettable for GICD_ITARGETSR18_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs new file mode 100644 index 0000000..5616822 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR19` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR19` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::FieldReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::FieldReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::FieldReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::FieldReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<0> { + SWI4_W::new(self) + } + #[doc = "Bits 8:15 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<8> { + SWI5_W::new(self) + } + #[doc = "Bits 16:23 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<16> { + SWI6_W::new(self) + } + #[doc = "Bits 24:31 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<24> { + SWI7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 76 - 79\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr19](index.html) module"] +pub struct GICD_ITARGETSR19_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR19_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr19::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR19_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr19::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR19_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR19 to value 0"] +impl crate::Resettable for GICD_ITARGETSR19_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs new file mode 100644 index 0000000..a651c0b --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::FieldReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::FieldReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::FieldReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::FieldReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<0> { + INT8_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<8> { + INT9_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<16> { + INT10_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<24> { + INT11_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 8 - 11\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr2](index.html) module"] +pub struct GICD_ITARGETSR2_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr2::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr2::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR2 to value 0"] +impl crate::Resettable for GICD_ITARGETSR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs new file mode 100644 index 0000000..ad5ec09 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR20` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR20` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT80` reader - Interrupt 80"] +pub type INT80_R = crate::FieldReader; +#[doc = "Field `INT80` writer - Interrupt 80"] +pub type INT80_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT81` reader - Interrupt 81"] +pub type INT81_R = crate::FieldReader; +#[doc = "Field `INT81` writer - Interrupt 81"] +pub type INT81_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT82` reader - Interrupt 82"] +pub type INT82_R = crate::FieldReader; +#[doc = "Field `INT82` writer - Interrupt 82"] +pub type INT82_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT83` reader - Interrupt 83"] +pub type INT83_R = crate::FieldReader; +#[doc = "Field `INT83` writer - Interrupt 83"] +pub type INT83_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 80"] + #[inline(always)] + pub fn int80(&self) -> INT80_R { + INT80_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 81"] + #[inline(always)] + pub fn int81(&self) -> INT81_R { + INT81_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 82"] + #[inline(always)] + pub fn int82(&self) -> INT82_R { + INT82_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 83"] + #[inline(always)] + pub fn int83(&self) -> INT83_R { + INT83_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 80"] + #[inline(always)] + #[must_use] + pub fn int80(&mut self) -> INT80_W<0> { + INT80_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 81"] + #[inline(always)] + #[must_use] + pub fn int81(&mut self) -> INT81_W<8> { + INT81_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 82"] + #[inline(always)] + #[must_use] + pub fn int82(&mut self) -> INT82_W<16> { + INT82_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 83"] + #[inline(always)] + #[must_use] + pub fn int83(&mut self) -> INT83_W<24> { + INT83_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 80 - 83\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr20](index.html) module"] +pub struct GICD_ITARGETSR20_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr20::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR20_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr20::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR20_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR20 to value 0"] +impl crate::Resettable for GICD_ITARGETSR20_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs new file mode 100644 index 0000000..2e201ff --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR21` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR21` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT84` reader - Interrupt 84"] +pub type INT84_R = crate::FieldReader; +#[doc = "Field `INT84` writer - Interrupt 84"] +pub type INT84_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT85` reader - Interrupt 85"] +pub type INT85_R = crate::FieldReader; +#[doc = "Field `INT85` writer - Interrupt 85"] +pub type INT85_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT86` reader - Interrupt 86"] +pub type INT86_R = crate::FieldReader; +#[doc = "Field `INT86` writer - Interrupt 86"] +pub type INT86_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT87` reader - Interrupt 87"] +pub type INT87_R = crate::FieldReader; +#[doc = "Field `INT87` writer - Interrupt 87"] +pub type INT87_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 84"] + #[inline(always)] + pub fn int84(&self) -> INT84_R { + INT84_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 85"] + #[inline(always)] + pub fn int85(&self) -> INT85_R { + INT85_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 86"] + #[inline(always)] + pub fn int86(&self) -> INT86_R { + INT86_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 87"] + #[inline(always)] + pub fn int87(&self) -> INT87_R { + INT87_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 84"] + #[inline(always)] + #[must_use] + pub fn int84(&mut self) -> INT84_W<0> { + INT84_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 85"] + #[inline(always)] + #[must_use] + pub fn int85(&mut self) -> INT85_W<8> { + INT85_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 86"] + #[inline(always)] + #[must_use] + pub fn int86(&mut self) -> INT86_W<16> { + INT86_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 87"] + #[inline(always)] + #[must_use] + pub fn int87(&mut self) -> INT87_W<24> { + INT87_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 84 - 87\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr21](index.html) module"] +pub struct GICD_ITARGETSR21_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR21_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr21::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR21_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr21::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR21_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR21 to value 0"] +impl crate::Resettable for GICD_ITARGETSR21_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs new file mode 100644 index 0000000..1169a9c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR22` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR22` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT88` reader - Interrupt 88"] +pub type INT88_R = crate::FieldReader; +#[doc = "Field `INT88` writer - Interrupt 88"] +pub type INT88_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT89` reader - Interrupt 89"] +pub type INT89_R = crate::FieldReader; +#[doc = "Field `INT89` writer - Interrupt 89"] +pub type INT89_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT90` reader - Interrupt 90"] +pub type INT90_R = crate::FieldReader; +#[doc = "Field `INT90` writer - Interrupt 90"] +pub type INT90_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT91` reader - Interrupt 91"] +pub type INT91_R = crate::FieldReader; +#[doc = "Field `INT91` writer - Interrupt 91"] +pub type INT91_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 88"] + #[inline(always)] + pub fn int88(&self) -> INT88_R { + INT88_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 89"] + #[inline(always)] + pub fn int89(&self) -> INT89_R { + INT89_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 90"] + #[inline(always)] + pub fn int90(&self) -> INT90_R { + INT90_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 91"] + #[inline(always)] + pub fn int91(&self) -> INT91_R { + INT91_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 88"] + #[inline(always)] + #[must_use] + pub fn int88(&mut self) -> INT88_W<0> { + INT88_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 89"] + #[inline(always)] + #[must_use] + pub fn int89(&mut self) -> INT89_W<8> { + INT89_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 90"] + #[inline(always)] + #[must_use] + pub fn int90(&mut self) -> INT90_W<16> { + INT90_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 91"] + #[inline(always)] + #[must_use] + pub fn int91(&mut self) -> INT91_W<24> { + INT91_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 88 - 91\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr22](index.html) module"] +pub struct GICD_ITARGETSR22_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR22_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr22::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR22_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr22::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR22_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR22 to value 0"] +impl crate::Resettable for GICD_ITARGETSR22_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs new file mode 100644 index 0000000..4035137 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR23` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR23` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT92` reader - Interrupt 92"] +pub type INT92_R = crate::FieldReader; +#[doc = "Field `INT92` writer - Interrupt 92"] +pub type INT92_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT93` reader - Interrupt 93"] +pub type INT93_R = crate::FieldReader; +#[doc = "Field `INT93` writer - Interrupt 93"] +pub type INT93_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT94` reader - Interrupt 94"] +pub type INT94_R = crate::FieldReader; +#[doc = "Field `INT94` writer - Interrupt 94"] +pub type INT94_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT95` reader - Interrupt 95"] +pub type INT95_R = crate::FieldReader; +#[doc = "Field `INT95` writer - Interrupt 95"] +pub type INT95_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 92"] + #[inline(always)] + pub fn int92(&self) -> INT92_R { + INT92_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 93"] + #[inline(always)] + pub fn int93(&self) -> INT93_R { + INT93_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 94"] + #[inline(always)] + pub fn int94(&self) -> INT94_R { + INT94_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 95"] + #[inline(always)] + pub fn int95(&self) -> INT95_R { + INT95_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 92"] + #[inline(always)] + #[must_use] + pub fn int92(&mut self) -> INT92_W<0> { + INT92_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 93"] + #[inline(always)] + #[must_use] + pub fn int93(&mut self) -> INT93_W<8> { + INT93_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 94"] + #[inline(always)] + #[must_use] + pub fn int94(&mut self) -> INT94_W<16> { + INT94_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 95"] + #[inline(always)] + #[must_use] + pub fn int95(&mut self) -> INT95_W<24> { + INT95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 92 - 95\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr23](index.html) module"] +pub struct GICD_ITARGETSR23_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR23_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr23::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR23_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr23::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR23_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR23 to value 0"] +impl crate::Resettable for GICD_ITARGETSR23_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs new file mode 100644 index 0000000..e177a8f --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR24` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR24` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::FieldReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::FieldReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::FieldReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::FieldReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bits 8:15 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<8> { + TIMER_1_W::new(self) + } + #[doc = "Bits 16:23 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<16> { + TIMER_2_W::new(self) + } + #[doc = "Bits 24:31 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<24> { + TIMER_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 96 - 99\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr24](index.html) module"] +pub struct GICD_ITARGETSR24_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr24::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR24_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr24::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR24_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR24 to value 0"] +impl crate::Resettable for GICD_ITARGETSR24_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs new file mode 100644 index 0000000..7d792a5 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs @@ -0,0 +1,128 @@ +#[doc = "Register `GICD_ITARGETSR25` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR25` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::FieldReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::FieldReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::FieldReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::FieldReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<0> { + H264_0_W::new(self) + } + #[doc = "Bits 8:15 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<8> { + H264_1_W::new(self) + } + #[doc = "Bits 16:23 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<16> { + H264_2_W::new(self) + } + #[doc = "Bits 24:31 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<24> { + JPEG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 100 - 103\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr25](index.html) module"] +pub struct GICD_ITARGETSR25_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR25_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr25::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR25_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr25::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR25_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR25 to value 0"] +impl crate::Resettable for GICD_ITARGETSR25_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs new file mode 100644 index 0000000..3b5ee68 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs @@ -0,0 +1,126 @@ +#[doc = "Register `GICD_ITARGETSR26` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR26` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::FieldReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::FieldReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::FieldReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::FieldReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<0> { + ISP_W::new(self) + } + #[doc = "Bits 8:15 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<8> { + USB_W::new(self) + } + #[doc = "Bits 16:23 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<16> { + V3D_W::new(self) + } + #[doc = "Bits 24:31 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<24> { + TRANSPOSER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 104 - 107\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr26](index.html) module"] +pub struct GICD_ITARGETSR26_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR26_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr26::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR26_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr26::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR26_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR26 to value 0"] +impl crate::Resettable for GICD_ITARGETSR26_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs new file mode 100644 index 0000000..6b66f35 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR27` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR27` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::FieldReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<0> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bits 8:15 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<8> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bits 16:23 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<16> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bits 24:31 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<24> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 108 - 111\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr27](index.html) module"] +pub struct GICD_ITARGETSR27_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR27_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr27::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR27_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr27::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR27_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR27 to value 0"] +impl crate::Resettable for GICD_ITARGETSR27_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs new file mode 100644 index 0000000..929f551 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR28` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR28` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::FieldReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::FieldReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::FieldReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::FieldReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<0> { + DMA_0_W::new(self) + } + #[doc = "Bits 8:15 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<8> { + DMA_1_W::new(self) + } + #[doc = "Bits 16:23 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<16> { + DMA_2_W::new(self) + } + #[doc = "Bits 24:31 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<24> { + DMA_3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 112 - 115\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr28](index.html) module"] +pub struct GICD_ITARGETSR28_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR28_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr28::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR28_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr28::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR28_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR28 to value 0"] +impl crate::Resettable for GICD_ITARGETSR28_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs new file mode 100644 index 0000000..a7e7047 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR29` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR29` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::FieldReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::FieldReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::FieldReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::FieldReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<0> { + DMA_4_W::new(self) + } + #[doc = "Bits 8:15 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<8> { + DMA_5_W::new(self) + } + #[doc = "Bits 16:23 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<16> { + DMA_6_W::new(self) + } + #[doc = "Bits 24:31 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<24> { + DMA_7_8_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 116 - 119\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr29](index.html) module"] +pub struct GICD_ITARGETSR29_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR29_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr29::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR29_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr29::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR29_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR29 to value 0"] +impl crate::Resettable for GICD_ITARGETSR29_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs new file mode 100644 index 0000000..2836e5c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::FieldReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::FieldReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::FieldReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::FieldReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<0> { + INT12_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<8> { + INT13_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<16> { + INT14_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<24> { + INT15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 12 - 15\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr3](index.html) module"] +pub struct GICD_ITARGETSR3_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr3::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr3::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR3 to value 0"] +impl crate::Resettable for GICD_ITARGETSR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs new file mode 100644 index 0000000..1a9adc4 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR30` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR30` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::FieldReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::FieldReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::FieldReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::FieldReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<0> { + DMA_9_10_W::new(self) + } + #[doc = "Bits 8:15 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<8> { + DMA_11_W::new(self) + } + #[doc = "Bits 16:23 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<16> { + DMA_12_W::new(self) + } + #[doc = "Bits 24:31 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<24> { + DMA_13_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 120 - 123\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr30](index.html) module"] +pub struct GICD_ITARGETSR30_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR30_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr30::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR30_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr30::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR30_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR30 to value 0"] +impl crate::Resettable for GICD_ITARGETSR30_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs new file mode 100644 index 0000000..7fec65c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_ITARGETSR31` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR31` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::FieldReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::FieldReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::FieldReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::FieldReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<0> { + DMA_14_W::new(self) + } + #[doc = "Bits 8:15 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<8> { + AUX_W::new(self) + } + #[doc = "Bits 16:23 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<16> { + ARM_W::new(self) + } + #[doc = "Bits 24:31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<24> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 124 - 127\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr31](index.html) module"] +pub struct GICD_ITARGETSR31_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR31_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr31::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR31_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr31::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR31_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR31 to value 0"] +impl crate::Resettable for GICD_ITARGETSR31_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs new file mode 100644 index 0000000..6f07c87 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_ITARGETSR32` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR32` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::FieldReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::FieldReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::FieldReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::FieldReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bits 8:15 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<8> { + HVS_W::new(self) + } + #[doc = "Bits 16:23 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<16> { + RPIVID_W::new(self) + } + #[doc = "Bits 24:31 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<24> { + SDC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 128 - 131\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr32](index.html) module"] +pub struct GICD_ITARGETSR32_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr32::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR32_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr32::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR32_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR32 to value 0"] +impl crate::Resettable for GICD_ITARGETSR32_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs new file mode 100644 index 0000000..cc64645 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::FieldReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::FieldReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::FieldReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<0> { + DSI_0_W::new(self) + } + #[doc = "Bits 8:15 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<8> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bits 16:23 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<16> { + CAMERA_0_W::new(self) + } + #[doc = "Bits 24:31 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<24> { + CAMERA_1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 132 - 135\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr33](index.html) module"] +pub struct GICD_ITARGETSR33_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr33::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr33::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR33_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR33 to value 0"] +impl crate::Resettable for GICD_ITARGETSR33_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs new file mode 100644 index 0000000..36c544c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR34` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR34` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::FieldReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::FieldReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::FieldReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<0> { + HDMI_0_W::new(self) + } + #[doc = "Bits 8:15 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<8> { + HDMI_1_W::new(self) + } + #[doc = "Bits 16:23 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<16> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bits 24:31 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<24> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 136 - 139\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr34](index.html) module"] +pub struct GICD_ITARGETSR34_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR34_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr34::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR34_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr34::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR34_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR34 to value 0"] +impl crate::Resettable for GICD_ITARGETSR34_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs new file mode 100644 index 0000000..c97c808 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs @@ -0,0 +1,128 @@ +#[doc = "Register `GICD_ITARGETSR35` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR35` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::FieldReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::FieldReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::FieldReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<0> { + DSI_1_W::new(self) + } + #[doc = "Bits 8:15 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<8> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bits 16:23 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<16> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bits 24:31 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<24> { + CPR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 140 - 143\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr35](index.html) module"] +pub struct GICD_ITARGETSR35_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR35_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr35::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR35_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr35::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR35_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR35 to value 0"] +impl crate::Resettable for GICD_ITARGETSR35_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs new file mode 100644 index 0000000..bab42ff --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs @@ -0,0 +1,128 @@ +#[doc = "Register `GICD_ITARGETSR36` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR36` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::FieldReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::FieldReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::FieldReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::FieldReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<0> { + SMI_W::new(self) + } + #[doc = "Bits 8:15 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<8> { + GPIO_0_W::new(self) + } + #[doc = "Bits 16:23 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<16> { + GPIO_1_W::new(self) + } + #[doc = "Bits 24:31 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<24> { + GPIO_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 144 - 147\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr36](index.html) module"] +pub struct GICD_ITARGETSR36_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR36_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr36::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR36_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr36::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR36_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR36 to value 0"] +impl crate::Resettable for GICD_ITARGETSR36_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs new file mode 100644 index 0000000..0142d8e --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_ITARGETSR37` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR37` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::FieldReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::FieldReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::FieldReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::FieldReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<0> { + GPIO_3_W::new(self) + } + #[doc = "Bits 8:15 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<8> { + I2C_W::new(self) + } + #[doc = "Bits 16:23 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<16> { + SPI_W::new(self) + } + #[doc = "Bits 24:31 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<24> { + PCM_I2S_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 148 - 151\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr37](index.html) module"] +pub struct GICD_ITARGETSR37_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR37_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr37::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR37_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr37::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR37_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR37 to value 0"] +impl crate::Resettable for GICD_ITARGETSR37_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs new file mode 100644 index 0000000..9cb7a0d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs @@ -0,0 +1,127 @@ +#[doc = "Register `GICD_ITARGETSR38` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR38` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::FieldReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::FieldReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::FieldReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::FieldReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<0> { + SDHOST_W::new(self) + } + #[doc = "Bits 8:15 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<8> { + UART_W::new(self) + } + #[doc = "Bits 16:23 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<16> { + ETH_PCIE_W::new(self) + } + #[doc = "Bits 24:31 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<24> { + VEC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 152 - 155\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr38](index.html) module"] +pub struct GICD_ITARGETSR38_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR38_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr38::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR38_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr38::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR38_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR38 to value 0"] +impl crate::Resettable for GICD_ITARGETSR38_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs new file mode 100644 index 0000000..a63e3b8 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs @@ -0,0 +1,126 @@ +#[doc = "Register `GICD_ITARGETSR39` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR39` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::FieldReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::FieldReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::FieldReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::FieldReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<0> { + CPG_W::new(self) + } + #[doc = "Bits 8:15 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<8> { + RNG_W::new(self) + } + #[doc = "Bits 16:23 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<16> { + EMMC_W::new(self) + } + #[doc = "Bits 24:31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<24> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 156 - 159\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr39](index.html) module"] +pub struct GICD_ITARGETSR39_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR39_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr39::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR39_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr39::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR39_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR39 to value 0"] +impl crate::Resettable for GICD_ITARGETSR39_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs new file mode 100644 index 0000000..1c16cfd --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::FieldReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::FieldReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::FieldReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::FieldReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<0> { + INT16_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<8> { + INT17_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<16> { + INT18_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<24> { + INT19_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 16 - 19\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr4](index.html) module"] +pub struct GICD_ITARGETSR4_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr4::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr4::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR4 to value 0"] +impl crate::Resettable for GICD_ITARGETSR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs new file mode 100644 index 0000000..405eeb4 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR40` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR40` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT160` reader - Interrupt 160"] +pub type INT160_R = crate::FieldReader; +#[doc = "Field `INT160` writer - Interrupt 160"] +pub type INT160_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT161` reader - Interrupt 161"] +pub type INT161_R = crate::FieldReader; +#[doc = "Field `INT161` writer - Interrupt 161"] +pub type INT161_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT162` reader - Interrupt 162"] +pub type INT162_R = crate::FieldReader; +#[doc = "Field `INT162` writer - Interrupt 162"] +pub type INT162_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT163` reader - Interrupt 163"] +pub type INT163_R = crate::FieldReader; +#[doc = "Field `INT163` writer - Interrupt 163"] +pub type INT163_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 160"] + #[inline(always)] + pub fn int160(&self) -> INT160_R { + INT160_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 161"] + #[inline(always)] + pub fn int161(&self) -> INT161_R { + INT161_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 162"] + #[inline(always)] + pub fn int162(&self) -> INT162_R { + INT162_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 163"] + #[inline(always)] + pub fn int163(&self) -> INT163_R { + INT163_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 160"] + #[inline(always)] + #[must_use] + pub fn int160(&mut self) -> INT160_W<0> { + INT160_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 161"] + #[inline(always)] + #[must_use] + pub fn int161(&mut self) -> INT161_W<8> { + INT161_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 162"] + #[inline(always)] + #[must_use] + pub fn int162(&mut self) -> INT162_W<16> { + INT162_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 163"] + #[inline(always)] + #[must_use] + pub fn int163(&mut self) -> INT163_W<24> { + INT163_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 160 - 163\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr40](index.html) module"] +pub struct GICD_ITARGETSR40_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR40_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr40::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR40_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr40::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR40_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR40 to value 0"] +impl crate::Resettable for GICD_ITARGETSR40_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs new file mode 100644 index 0000000..4cf2746 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR41` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR41` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT164` reader - Interrupt 164"] +pub type INT164_R = crate::FieldReader; +#[doc = "Field `INT164` writer - Interrupt 164"] +pub type INT164_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT165` reader - Interrupt 165"] +pub type INT165_R = crate::FieldReader; +#[doc = "Field `INT165` writer - Interrupt 165"] +pub type INT165_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT166` reader - Interrupt 166"] +pub type INT166_R = crate::FieldReader; +#[doc = "Field `INT166` writer - Interrupt 166"] +pub type INT166_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT167` reader - Interrupt 167"] +pub type INT167_R = crate::FieldReader; +#[doc = "Field `INT167` writer - Interrupt 167"] +pub type INT167_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 164"] + #[inline(always)] + pub fn int164(&self) -> INT164_R { + INT164_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 165"] + #[inline(always)] + pub fn int165(&self) -> INT165_R { + INT165_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 166"] + #[inline(always)] + pub fn int166(&self) -> INT166_R { + INT166_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 167"] + #[inline(always)] + pub fn int167(&self) -> INT167_R { + INT167_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 164"] + #[inline(always)] + #[must_use] + pub fn int164(&mut self) -> INT164_W<0> { + INT164_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 165"] + #[inline(always)] + #[must_use] + pub fn int165(&mut self) -> INT165_W<8> { + INT165_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 166"] + #[inline(always)] + #[must_use] + pub fn int166(&mut self) -> INT166_W<16> { + INT166_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 167"] + #[inline(always)] + #[must_use] + pub fn int167(&mut self) -> INT167_W<24> { + INT167_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 164 - 167\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr41](index.html) module"] +pub struct GICD_ITARGETSR41_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR41_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr41::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR41_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr41::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR41_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR41 to value 0"] +impl crate::Resettable for GICD_ITARGETSR41_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs new file mode 100644 index 0000000..7aafb04 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR42` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR42` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT168` reader - Interrupt 168"] +pub type INT168_R = crate::FieldReader; +#[doc = "Field `INT168` writer - Interrupt 168"] +pub type INT168_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT169` reader - Interrupt 169"] +pub type INT169_R = crate::FieldReader; +#[doc = "Field `INT169` writer - Interrupt 169"] +pub type INT169_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT170` reader - Interrupt 170"] +pub type INT170_R = crate::FieldReader; +#[doc = "Field `INT170` writer - Interrupt 170"] +pub type INT170_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT171` reader - Interrupt 171"] +pub type INT171_R = crate::FieldReader; +#[doc = "Field `INT171` writer - Interrupt 171"] +pub type INT171_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 168"] + #[inline(always)] + pub fn int168(&self) -> INT168_R { + INT168_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 169"] + #[inline(always)] + pub fn int169(&self) -> INT169_R { + INT169_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 170"] + #[inline(always)] + pub fn int170(&self) -> INT170_R { + INT170_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 171"] + #[inline(always)] + pub fn int171(&self) -> INT171_R { + INT171_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 168"] + #[inline(always)] + #[must_use] + pub fn int168(&mut self) -> INT168_W<0> { + INT168_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 169"] + #[inline(always)] + #[must_use] + pub fn int169(&mut self) -> INT169_W<8> { + INT169_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 170"] + #[inline(always)] + #[must_use] + pub fn int170(&mut self) -> INT170_W<16> { + INT170_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 171"] + #[inline(always)] + #[must_use] + pub fn int171(&mut self) -> INT171_W<24> { + INT171_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 168 - 171\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr42](index.html) module"] +pub struct GICD_ITARGETSR42_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR42_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr42::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR42_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr42::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR42_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR42 to value 0"] +impl crate::Resettable for GICD_ITARGETSR42_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs new file mode 100644 index 0000000..9544198 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR43` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR43` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT172` reader - Interrupt 172"] +pub type INT172_R = crate::FieldReader; +#[doc = "Field `INT172` writer - Interrupt 172"] +pub type INT172_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT173` reader - Interrupt 173"] +pub type INT173_R = crate::FieldReader; +#[doc = "Field `INT173` writer - Interrupt 173"] +pub type INT173_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT174` reader - Interrupt 174"] +pub type INT174_R = crate::FieldReader; +#[doc = "Field `INT174` writer - Interrupt 174"] +pub type INT174_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT175` reader - Interrupt 175"] +pub type INT175_R = crate::FieldReader; +#[doc = "Field `INT175` writer - Interrupt 175"] +pub type INT175_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 172"] + #[inline(always)] + pub fn int172(&self) -> INT172_R { + INT172_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 173"] + #[inline(always)] + pub fn int173(&self) -> INT173_R { + INT173_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 174"] + #[inline(always)] + pub fn int174(&self) -> INT174_R { + INT174_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 175"] + #[inline(always)] + pub fn int175(&self) -> INT175_R { + INT175_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 172"] + #[inline(always)] + #[must_use] + pub fn int172(&mut self) -> INT172_W<0> { + INT172_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 173"] + #[inline(always)] + #[must_use] + pub fn int173(&mut self) -> INT173_W<8> { + INT173_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 174"] + #[inline(always)] + #[must_use] + pub fn int174(&mut self) -> INT174_W<16> { + INT174_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 175"] + #[inline(always)] + #[must_use] + pub fn int175(&mut self) -> INT175_W<24> { + INT175_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 172 - 175\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr43](index.html) module"] +pub struct GICD_ITARGETSR43_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR43_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr43::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR43_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr43::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR43_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR43 to value 0"] +impl crate::Resettable for GICD_ITARGETSR43_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs new file mode 100644 index 0000000..fb06269 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR44` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR44` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT176` reader - Interrupt 176"] +pub type INT176_R = crate::FieldReader; +#[doc = "Field `INT176` writer - Interrupt 176"] +pub type INT176_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT177` reader - Interrupt 177"] +pub type INT177_R = crate::FieldReader; +#[doc = "Field `INT177` writer - Interrupt 177"] +pub type INT177_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT178` reader - Interrupt 178"] +pub type INT178_R = crate::FieldReader; +#[doc = "Field `INT178` writer - Interrupt 178"] +pub type INT178_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT179` reader - Interrupt 179"] +pub type INT179_R = crate::FieldReader; +#[doc = "Field `INT179` writer - Interrupt 179"] +pub type INT179_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 176"] + #[inline(always)] + pub fn int176(&self) -> INT176_R { + INT176_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 177"] + #[inline(always)] + pub fn int177(&self) -> INT177_R { + INT177_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 178"] + #[inline(always)] + pub fn int178(&self) -> INT178_R { + INT178_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 179"] + #[inline(always)] + pub fn int179(&self) -> INT179_R { + INT179_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 176"] + #[inline(always)] + #[must_use] + pub fn int176(&mut self) -> INT176_W<0> { + INT176_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 177"] + #[inline(always)] + #[must_use] + pub fn int177(&mut self) -> INT177_W<8> { + INT177_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 178"] + #[inline(always)] + #[must_use] + pub fn int178(&mut self) -> INT178_W<16> { + INT178_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 179"] + #[inline(always)] + #[must_use] + pub fn int179(&mut self) -> INT179_W<24> { + INT179_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 176 - 179\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr44](index.html) module"] +pub struct GICD_ITARGETSR44_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR44_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr44::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR44_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr44::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR44_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR44 to value 0"] +impl crate::Resettable for GICD_ITARGETSR44_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs new file mode 100644 index 0000000..38d0d32 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR45` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR45` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT180` reader - Interrupt 180"] +pub type INT180_R = crate::FieldReader; +#[doc = "Field `INT180` writer - Interrupt 180"] +pub type INT180_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT181` reader - Interrupt 181"] +pub type INT181_R = crate::FieldReader; +#[doc = "Field `INT181` writer - Interrupt 181"] +pub type INT181_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT182` reader - Interrupt 182"] +pub type INT182_R = crate::FieldReader; +#[doc = "Field `INT182` writer - Interrupt 182"] +pub type INT182_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT183` reader - Interrupt 183"] +pub type INT183_R = crate::FieldReader; +#[doc = "Field `INT183` writer - Interrupt 183"] +pub type INT183_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 180"] + #[inline(always)] + pub fn int180(&self) -> INT180_R { + INT180_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 181"] + #[inline(always)] + pub fn int181(&self) -> INT181_R { + INT181_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 182"] + #[inline(always)] + pub fn int182(&self) -> INT182_R { + INT182_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 183"] + #[inline(always)] + pub fn int183(&self) -> INT183_R { + INT183_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 180"] + #[inline(always)] + #[must_use] + pub fn int180(&mut self) -> INT180_W<0> { + INT180_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 181"] + #[inline(always)] + #[must_use] + pub fn int181(&mut self) -> INT181_W<8> { + INT181_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 182"] + #[inline(always)] + #[must_use] + pub fn int182(&mut self) -> INT182_W<16> { + INT182_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 183"] + #[inline(always)] + #[must_use] + pub fn int183(&mut self) -> INT183_W<24> { + INT183_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 180 - 183\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr45](index.html) module"] +pub struct GICD_ITARGETSR45_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR45_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr45::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR45_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr45::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR45_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR45 to value 0"] +impl crate::Resettable for GICD_ITARGETSR45_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs new file mode 100644 index 0000000..2bbf68c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR46` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR46` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT184` reader - Interrupt 184"] +pub type INT184_R = crate::FieldReader; +#[doc = "Field `INT184` writer - Interrupt 184"] +pub type INT184_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT185` reader - Interrupt 185"] +pub type INT185_R = crate::FieldReader; +#[doc = "Field `INT185` writer - Interrupt 185"] +pub type INT185_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT186` reader - Interrupt 186"] +pub type INT186_R = crate::FieldReader; +#[doc = "Field `INT186` writer - Interrupt 186"] +pub type INT186_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT187` reader - Interrupt 187"] +pub type INT187_R = crate::FieldReader; +#[doc = "Field `INT187` writer - Interrupt 187"] +pub type INT187_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 184"] + #[inline(always)] + pub fn int184(&self) -> INT184_R { + INT184_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 185"] + #[inline(always)] + pub fn int185(&self) -> INT185_R { + INT185_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 186"] + #[inline(always)] + pub fn int186(&self) -> INT186_R { + INT186_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 187"] + #[inline(always)] + pub fn int187(&self) -> INT187_R { + INT187_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 184"] + #[inline(always)] + #[must_use] + pub fn int184(&mut self) -> INT184_W<0> { + INT184_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 185"] + #[inline(always)] + #[must_use] + pub fn int185(&mut self) -> INT185_W<8> { + INT185_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 186"] + #[inline(always)] + #[must_use] + pub fn int186(&mut self) -> INT186_W<16> { + INT186_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 187"] + #[inline(always)] + #[must_use] + pub fn int187(&mut self) -> INT187_W<24> { + INT187_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 184 - 187\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr46](index.html) module"] +pub struct GICD_ITARGETSR46_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR46_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr46::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR46_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr46::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR46_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR46 to value 0"] +impl crate::Resettable for GICD_ITARGETSR46_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs new file mode 100644 index 0000000..ae06a37 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR47` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR47` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT188` reader - Interrupt 188"] +pub type INT188_R = crate::FieldReader; +#[doc = "Field `INT188` writer - Interrupt 188"] +pub type INT188_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT189` reader - Interrupt 189"] +pub type INT189_R = crate::FieldReader; +#[doc = "Field `INT189` writer - Interrupt 189"] +pub type INT189_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT190` reader - Interrupt 190"] +pub type INT190_R = crate::FieldReader; +#[doc = "Field `INT190` writer - Interrupt 190"] +pub type INT190_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT191` reader - Interrupt 191"] +pub type INT191_R = crate::FieldReader; +#[doc = "Field `INT191` writer - Interrupt 191"] +pub type INT191_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 188"] + #[inline(always)] + pub fn int188(&self) -> INT188_R { + INT188_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 189"] + #[inline(always)] + pub fn int189(&self) -> INT189_R { + INT189_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 190"] + #[inline(always)] + pub fn int190(&self) -> INT190_R { + INT190_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 191"] + #[inline(always)] + pub fn int191(&self) -> INT191_R { + INT191_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 188"] + #[inline(always)] + #[must_use] + pub fn int188(&mut self) -> INT188_W<0> { + INT188_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 189"] + #[inline(always)] + #[must_use] + pub fn int189(&mut self) -> INT189_W<8> { + INT189_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 190"] + #[inline(always)] + #[must_use] + pub fn int190(&mut self) -> INT190_W<16> { + INT190_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 191"] + #[inline(always)] + #[must_use] + pub fn int191(&mut self) -> INT191_W<24> { + INT191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 188 - 191\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr47](index.html) module"] +pub struct GICD_ITARGETSR47_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR47_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr47::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR47_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr47::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR47_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR47 to value 0"] +impl crate::Resettable for GICD_ITARGETSR47_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs new file mode 100644 index 0000000..aa5a789 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR48` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR48` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT192` reader - Interrupt 192"] +pub type INT192_R = crate::FieldReader; +#[doc = "Field `INT192` writer - Interrupt 192"] +pub type INT192_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT193` reader - Interrupt 193"] +pub type INT193_R = crate::FieldReader; +#[doc = "Field `INT193` writer - Interrupt 193"] +pub type INT193_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT194` reader - Interrupt 194"] +pub type INT194_R = crate::FieldReader; +#[doc = "Field `INT194` writer - Interrupt 194"] +pub type INT194_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT195` reader - Interrupt 195"] +pub type INT195_R = crate::FieldReader; +#[doc = "Field `INT195` writer - Interrupt 195"] +pub type INT195_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 192"] + #[inline(always)] + pub fn int192(&self) -> INT192_R { + INT192_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 193"] + #[inline(always)] + pub fn int193(&self) -> INT193_R { + INT193_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 194"] + #[inline(always)] + pub fn int194(&self) -> INT194_R { + INT194_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 195"] + #[inline(always)] + pub fn int195(&self) -> INT195_R { + INT195_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 192"] + #[inline(always)] + #[must_use] + pub fn int192(&mut self) -> INT192_W<0> { + INT192_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 193"] + #[inline(always)] + #[must_use] + pub fn int193(&mut self) -> INT193_W<8> { + INT193_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 194"] + #[inline(always)] + #[must_use] + pub fn int194(&mut self) -> INT194_W<16> { + INT194_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 195"] + #[inline(always)] + #[must_use] + pub fn int195(&mut self) -> INT195_W<24> { + INT195_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 192 - 195\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr48](index.html) module"] +pub struct GICD_ITARGETSR48_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr48::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR48_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr48::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR48_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR48 to value 0"] +impl crate::Resettable for GICD_ITARGETSR48_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs new file mode 100644 index 0000000..521fdd6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR49` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR49` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT196` reader - Interrupt 196"] +pub type INT196_R = crate::FieldReader; +#[doc = "Field `INT196` writer - Interrupt 196"] +pub type INT196_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT197` reader - Interrupt 197"] +pub type INT197_R = crate::FieldReader; +#[doc = "Field `INT197` writer - Interrupt 197"] +pub type INT197_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT198` reader - Interrupt 198"] +pub type INT198_R = crate::FieldReader; +#[doc = "Field `INT198` writer - Interrupt 198"] +pub type INT198_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT199` reader - Interrupt 199"] +pub type INT199_R = crate::FieldReader; +#[doc = "Field `INT199` writer - Interrupt 199"] +pub type INT199_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 196"] + #[inline(always)] + pub fn int196(&self) -> INT196_R { + INT196_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 197"] + #[inline(always)] + pub fn int197(&self) -> INT197_R { + INT197_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 198"] + #[inline(always)] + pub fn int198(&self) -> INT198_R { + INT198_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 199"] + #[inline(always)] + pub fn int199(&self) -> INT199_R { + INT199_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 196"] + #[inline(always)] + #[must_use] + pub fn int196(&mut self) -> INT196_W<0> { + INT196_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 197"] + #[inline(always)] + #[must_use] + pub fn int197(&mut self) -> INT197_W<8> { + INT197_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 198"] + #[inline(always)] + #[must_use] + pub fn int198(&mut self) -> INT198_W<16> { + INT198_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 199"] + #[inline(always)] + #[must_use] + pub fn int199(&mut self) -> INT199_W<24> { + INT199_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 196 - 199\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr49](index.html) module"] +pub struct GICD_ITARGETSR49_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR49_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr49::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR49_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr49::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR49_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR49 to value 0"] +impl crate::Resettable for GICD_ITARGETSR49_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs new file mode 100644 index 0000000..4392dd7 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::FieldReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::FieldReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::FieldReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::FieldReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<0> { + INT20_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<8> { + INT21_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<16> { + INT22_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<24> { + INT23_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 20 - 23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr5](index.html) module"] +pub struct GICD_ITARGETSR5_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr5::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr5::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR5 to value 0"] +impl crate::Resettable for GICD_ITARGETSR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs new file mode 100644 index 0000000..50c0b1c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR50` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR50` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT200` reader - Interrupt 200"] +pub type INT200_R = crate::FieldReader; +#[doc = "Field `INT200` writer - Interrupt 200"] +pub type INT200_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT201` reader - Interrupt 201"] +pub type INT201_R = crate::FieldReader; +#[doc = "Field `INT201` writer - Interrupt 201"] +pub type INT201_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT202` reader - Interrupt 202"] +pub type INT202_R = crate::FieldReader; +#[doc = "Field `INT202` writer - Interrupt 202"] +pub type INT202_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT203` reader - Interrupt 203"] +pub type INT203_R = crate::FieldReader; +#[doc = "Field `INT203` writer - Interrupt 203"] +pub type INT203_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 200"] + #[inline(always)] + pub fn int200(&self) -> INT200_R { + INT200_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 201"] + #[inline(always)] + pub fn int201(&self) -> INT201_R { + INT201_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 202"] + #[inline(always)] + pub fn int202(&self) -> INT202_R { + INT202_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 203"] + #[inline(always)] + pub fn int203(&self) -> INT203_R { + INT203_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 200"] + #[inline(always)] + #[must_use] + pub fn int200(&mut self) -> INT200_W<0> { + INT200_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 201"] + #[inline(always)] + #[must_use] + pub fn int201(&mut self) -> INT201_W<8> { + INT201_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 202"] + #[inline(always)] + #[must_use] + pub fn int202(&mut self) -> INT202_W<16> { + INT202_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 203"] + #[inline(always)] + #[must_use] + pub fn int203(&mut self) -> INT203_W<24> { + INT203_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 200 - 203\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr50](index.html) module"] +pub struct GICD_ITARGETSR50_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR50_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr50::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR50_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr50::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR50_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR50 to value 0"] +impl crate::Resettable for GICD_ITARGETSR50_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs new file mode 100644 index 0000000..4fc2ee2 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR51` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR51` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT204` reader - Interrupt 204"] +pub type INT204_R = crate::FieldReader; +#[doc = "Field `INT204` writer - Interrupt 204"] +pub type INT204_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT205` reader - Interrupt 205"] +pub type INT205_R = crate::FieldReader; +#[doc = "Field `INT205` writer - Interrupt 205"] +pub type INT205_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT206` reader - Interrupt 206"] +pub type INT206_R = crate::FieldReader; +#[doc = "Field `INT206` writer - Interrupt 206"] +pub type INT206_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT207` reader - Interrupt 207"] +pub type INT207_R = crate::FieldReader; +#[doc = "Field `INT207` writer - Interrupt 207"] +pub type INT207_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 204"] + #[inline(always)] + pub fn int204(&self) -> INT204_R { + INT204_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 205"] + #[inline(always)] + pub fn int205(&self) -> INT205_R { + INT205_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 206"] + #[inline(always)] + pub fn int206(&self) -> INT206_R { + INT206_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 207"] + #[inline(always)] + pub fn int207(&self) -> INT207_R { + INT207_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 204"] + #[inline(always)] + #[must_use] + pub fn int204(&mut self) -> INT204_W<0> { + INT204_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 205"] + #[inline(always)] + #[must_use] + pub fn int205(&mut self) -> INT205_W<8> { + INT205_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 206"] + #[inline(always)] + #[must_use] + pub fn int206(&mut self) -> INT206_W<16> { + INT206_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 207"] + #[inline(always)] + #[must_use] + pub fn int207(&mut self) -> INT207_W<24> { + INT207_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 204 - 207\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr51](index.html) module"] +pub struct GICD_ITARGETSR51_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR51_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr51::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR51_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr51::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR51_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR51 to value 0"] +impl crate::Resettable for GICD_ITARGETSR51_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs new file mode 100644 index 0000000..aee42d1 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR52` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR52` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT208` reader - Interrupt 208"] +pub type INT208_R = crate::FieldReader; +#[doc = "Field `INT208` writer - Interrupt 208"] +pub type INT208_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT209` reader - Interrupt 209"] +pub type INT209_R = crate::FieldReader; +#[doc = "Field `INT209` writer - Interrupt 209"] +pub type INT209_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT210` reader - Interrupt 210"] +pub type INT210_R = crate::FieldReader; +#[doc = "Field `INT210` writer - Interrupt 210"] +pub type INT210_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT211` reader - Interrupt 211"] +pub type INT211_R = crate::FieldReader; +#[doc = "Field `INT211` writer - Interrupt 211"] +pub type INT211_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 208"] + #[inline(always)] + pub fn int208(&self) -> INT208_R { + INT208_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 209"] + #[inline(always)] + pub fn int209(&self) -> INT209_R { + INT209_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 210"] + #[inline(always)] + pub fn int210(&self) -> INT210_R { + INT210_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 211"] + #[inline(always)] + pub fn int211(&self) -> INT211_R { + INT211_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 208"] + #[inline(always)] + #[must_use] + pub fn int208(&mut self) -> INT208_W<0> { + INT208_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 209"] + #[inline(always)] + #[must_use] + pub fn int209(&mut self) -> INT209_W<8> { + INT209_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 210"] + #[inline(always)] + #[must_use] + pub fn int210(&mut self) -> INT210_W<16> { + INT210_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 211"] + #[inline(always)] + #[must_use] + pub fn int211(&mut self) -> INT211_W<24> { + INT211_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 208 - 211\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr52](index.html) module"] +pub struct GICD_ITARGETSR52_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR52_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr52::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR52_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr52::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR52_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR52 to value 0"] +impl crate::Resettable for GICD_ITARGETSR52_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs new file mode 100644 index 0000000..5923b06 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR53` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR53` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT212` reader - Interrupt 212"] +pub type INT212_R = crate::FieldReader; +#[doc = "Field `INT212` writer - Interrupt 212"] +pub type INT212_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT213` reader - Interrupt 213"] +pub type INT213_R = crate::FieldReader; +#[doc = "Field `INT213` writer - Interrupt 213"] +pub type INT213_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT214` reader - Interrupt 214"] +pub type INT214_R = crate::FieldReader; +#[doc = "Field `INT214` writer - Interrupt 214"] +pub type INT214_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT215` reader - Interrupt 215"] +pub type INT215_R = crate::FieldReader; +#[doc = "Field `INT215` writer - Interrupt 215"] +pub type INT215_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 212"] + #[inline(always)] + pub fn int212(&self) -> INT212_R { + INT212_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 213"] + #[inline(always)] + pub fn int213(&self) -> INT213_R { + INT213_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 214"] + #[inline(always)] + pub fn int214(&self) -> INT214_R { + INT214_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 215"] + #[inline(always)] + pub fn int215(&self) -> INT215_R { + INT215_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 212"] + #[inline(always)] + #[must_use] + pub fn int212(&mut self) -> INT212_W<0> { + INT212_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 213"] + #[inline(always)] + #[must_use] + pub fn int213(&mut self) -> INT213_W<8> { + INT213_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 214"] + #[inline(always)] + #[must_use] + pub fn int214(&mut self) -> INT214_W<16> { + INT214_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 215"] + #[inline(always)] + #[must_use] + pub fn int215(&mut self) -> INT215_W<24> { + INT215_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 212 - 215\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr53](index.html) module"] +pub struct GICD_ITARGETSR53_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR53_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr53::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR53_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr53::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR53_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR53 to value 0"] +impl crate::Resettable for GICD_ITARGETSR53_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs new file mode 100644 index 0000000..c0a5719 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR54` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR54` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT216` reader - Interrupt 216"] +pub type INT216_R = crate::FieldReader; +#[doc = "Field `INT216` writer - Interrupt 216"] +pub type INT216_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT217` reader - Interrupt 217"] +pub type INT217_R = crate::FieldReader; +#[doc = "Field `INT217` writer - Interrupt 217"] +pub type INT217_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT218` reader - Interrupt 218"] +pub type INT218_R = crate::FieldReader; +#[doc = "Field `INT218` writer - Interrupt 218"] +pub type INT218_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT219` reader - Interrupt 219"] +pub type INT219_R = crate::FieldReader; +#[doc = "Field `INT219` writer - Interrupt 219"] +pub type INT219_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 216"] + #[inline(always)] + pub fn int216(&self) -> INT216_R { + INT216_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 217"] + #[inline(always)] + pub fn int217(&self) -> INT217_R { + INT217_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 218"] + #[inline(always)] + pub fn int218(&self) -> INT218_R { + INT218_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 219"] + #[inline(always)] + pub fn int219(&self) -> INT219_R { + INT219_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 216"] + #[inline(always)] + #[must_use] + pub fn int216(&mut self) -> INT216_W<0> { + INT216_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 217"] + #[inline(always)] + #[must_use] + pub fn int217(&mut self) -> INT217_W<8> { + INT217_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 218"] + #[inline(always)] + #[must_use] + pub fn int218(&mut self) -> INT218_W<16> { + INT218_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 219"] + #[inline(always)] + #[must_use] + pub fn int219(&mut self) -> INT219_W<24> { + INT219_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 216 - 219\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr54](index.html) module"] +pub struct GICD_ITARGETSR54_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR54_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr54::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR54_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr54::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR54_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR54 to value 0"] +impl crate::Resettable for GICD_ITARGETSR54_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs new file mode 100644 index 0000000..ea2e0a5 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs @@ -0,0 +1,129 @@ +#[doc = "Register `GICD_ITARGETSR55` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR55` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT220` reader - Interrupt 220"] +pub type INT220_R = crate::FieldReader; +#[doc = "Field `INT220` writer - Interrupt 220"] +pub type INT220_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT221` reader - Interrupt 221"] +pub type INT221_R = crate::FieldReader; +#[doc = "Field `INT221` writer - Interrupt 221"] +pub type INT221_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT222` reader - Interrupt 222"] +pub type INT222_R = crate::FieldReader; +#[doc = "Field `INT222` writer - Interrupt 222"] +pub type INT222_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT223` reader - Interrupt 223"] +pub type INT223_R = crate::FieldReader; +#[doc = "Field `INT223` writer - Interrupt 223"] +pub type INT223_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 220"] + #[inline(always)] + pub fn int220(&self) -> INT220_R { + INT220_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 221"] + #[inline(always)] + pub fn int221(&self) -> INT221_R { + INT221_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 222"] + #[inline(always)] + pub fn int222(&self) -> INT222_R { + INT222_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 223"] + #[inline(always)] + pub fn int223(&self) -> INT223_R { + INT223_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 220"] + #[inline(always)] + #[must_use] + pub fn int220(&mut self) -> INT220_W<0> { + INT220_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 221"] + #[inline(always)] + #[must_use] + pub fn int221(&mut self) -> INT221_W<8> { + INT221_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 222"] + #[inline(always)] + #[must_use] + pub fn int222(&mut self) -> INT222_W<16> { + INT222_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 223"] + #[inline(always)] + #[must_use] + pub fn int223(&mut self) -> INT223_W<24> { + INT223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 220 - 223\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr55](index.html) module"] +pub struct GICD_ITARGETSR55_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR55_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr55::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR55_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr55::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR55_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR55 to value 0"] +impl crate::Resettable for GICD_ITARGETSR55_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs new file mode 100644 index 0000000..b0feb60 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::FieldReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::FieldReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::FieldReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::FieldReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<0> { + INT24_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<8> { + INT25_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<16> { + INT26_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<24> { + INT27_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 24 - 27\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr6](index.html) module"] +pub struct GICD_ITARGETSR6_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr6::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr6::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR6 to value 0"] +impl crate::Resettable for GICD_ITARGETSR6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs new file mode 100644 index 0000000..e53083c --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::FieldReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::FieldReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::FieldReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::FieldReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<0> { + INT28_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<8> { + INT29_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<16> { + INT30_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<24> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 28 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr7](index.html) module"] +pub struct GICD_ITARGETSR7_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr7::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr7::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR7 to value 0"] +impl crate::Resettable for GICD_ITARGETSR7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs new file mode 100644 index 0000000..80c1bed --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::FieldReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::FieldReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::FieldReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::FieldReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<8> { + INT33_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<16> { + INT34_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<24> { + INT35_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 32 - 35\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr8](index.html) module"] +pub struct GICD_ITARGETSR8_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr8::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr8::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR8_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR8 to value 0"] +impl crate::Resettable for GICD_ITARGETSR8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs new file mode 100644 index 0000000..07224dd --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs @@ -0,0 +1,125 @@ +#[doc = "Register `GICD_ITARGETSR9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_ITARGETSR9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::FieldReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::FieldReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::FieldReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::FieldReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<0> { + INT36_W::new(self) + } + #[doc = "Bits 8:15 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<8> { + INT37_W::new(self) + } + #[doc = "Bits 16:23 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<16> { + INT38_W::new(self) + } + #[doc = "Bits 24:31 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<24> { + INT39_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Processor Target 36 - 39\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr9](index.html) module"] +pub struct GICD_ITARGETSR9_SPEC; +impl crate::RegisterSpec for GICD_ITARGETSR9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_itargetsr9::R](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_itargetsr9::W](W) writer structure"] +impl crate::Writable for GICD_ITARGETSR9_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_ITARGETSR9 to value 0"] +impl crate::Resettable for GICD_ITARGETSR9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs new file mode 100644 index 0000000..475a66f --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR0` reader - Peripheral ID 0"] +pub type GICD_PIDR0_R = crate::FieldReader; +#[doc = "Peripheral ID 0\n\nValue on reset: 144"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR0_A { + #[doc = "144: Valid"] + VALID = 144, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR0_A) -> Self { + variant as _ + } +} +impl GICD_PIDR0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 144 => Some(GICD_PIDR0_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR0_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 0"] + #[inline(always)] + pub fn gicd_pidr0(&self) -> GICD_PIDR0_R { + GICD_PIDR0_R::new(self.bits) + } +} +#[doc = "Peripheral ID 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr0](index.html) module"] +pub struct GICD_PIDR0_SPEC; +impl crate::RegisterSpec for GICD_PIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr0::R](R) reader structure"] +impl crate::Readable for GICD_PIDR0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR0 to value 0x90"] +impl crate::Resettable for GICD_PIDR0_SPEC { + const RESET_VALUE: Self::Ux = 0x90; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs new file mode 100644 index 0000000..5bab832 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR1` reader - Peripheral ID 1"] +pub type GICD_PIDR1_R = crate::FieldReader; +#[doc = "Peripheral ID 1\n\nValue on reset: 180"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR1_A { + #[doc = "180: Valid"] + VALID = 180, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR1_A) -> Self { + variant as _ + } +} +impl GICD_PIDR1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 180 => Some(GICD_PIDR1_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR1_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 1"] + #[inline(always)] + pub fn gicd_pidr1(&self) -> GICD_PIDR1_R { + GICD_PIDR1_R::new(self.bits) + } +} +#[doc = "Peripheral ID 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr1](index.html) module"] +pub struct GICD_PIDR1_SPEC; +impl crate::RegisterSpec for GICD_PIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr1::R](R) reader structure"] +impl crate::Readable for GICD_PIDR1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR1 to value 0xb4"] +impl crate::Resettable for GICD_PIDR1_SPEC { + const RESET_VALUE: Self::Ux = 0xb4; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs new file mode 100644 index 0000000..9dd9594 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR2` reader - Peripheral ID 2"] +pub type GICD_PIDR2_R = crate::FieldReader; +#[doc = "Peripheral ID 2\n\nValue on reset: 43"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR2_A { + #[doc = "43: Valid"] + VALID = 43, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR2_A) -> Self { + variant as _ + } +} +impl GICD_PIDR2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 43 => Some(GICD_PIDR2_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR2_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 2"] + #[inline(always)] + pub fn gicd_pidr2(&self) -> GICD_PIDR2_R { + GICD_PIDR2_R::new(self.bits) + } +} +#[doc = "Peripheral ID 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr2](index.html) module"] +pub struct GICD_PIDR2_SPEC; +impl crate::RegisterSpec for GICD_PIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr2::R](R) reader structure"] +impl crate::Readable for GICD_PIDR2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR2 to value 0x2b"] +impl crate::Resettable for GICD_PIDR2_SPEC { + const RESET_VALUE: Self::Ux = 0x2b; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs new file mode 100644 index 0000000..500d9eb --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR3` reader - Peripheral ID 3"] +pub type GICD_PIDR3_R = crate::FieldReader; +#[doc = "Peripheral ID 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR3_A { + #[doc = "0: Valid"] + VALID = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR3_A) -> Self { + variant as _ + } +} +impl GICD_PIDR3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GICD_PIDR3_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR3_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 3"] + #[inline(always)] + pub fn gicd_pidr3(&self) -> GICD_PIDR3_R { + GICD_PIDR3_R::new(self.bits) + } +} +#[doc = "Peripheral ID 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr3](index.html) module"] +pub struct GICD_PIDR3_SPEC; +impl crate::RegisterSpec for GICD_PIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr3::R](R) reader structure"] +impl crate::Readable for GICD_PIDR3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR3 to value 0"] +impl crate::Resettable for GICD_PIDR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs new file mode 100644 index 0000000..9b4d3a3 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR4` reader - Peripheral ID 4"] +pub type GICD_PIDR4_R = crate::FieldReader; +#[doc = "Peripheral ID 4\n\nValue on reset: 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR4_A { + #[doc = "4: Valid"] + VALID = 4, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR4_A) -> Self { + variant as _ + } +} +impl GICD_PIDR4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 4 => Some(GICD_PIDR4_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR4_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 4"] + #[inline(always)] + pub fn gicd_pidr4(&self) -> GICD_PIDR4_R { + GICD_PIDR4_R::new(self.bits) + } +} +#[doc = "Peripheral ID 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr4](index.html) module"] +pub struct GICD_PIDR4_SPEC; +impl crate::RegisterSpec for GICD_PIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr4::R](R) reader structure"] +impl crate::Readable for GICD_PIDR4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR4 to value 0x04"] +impl crate::Resettable for GICD_PIDR4_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs new file mode 100644 index 0000000..a0c4716 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR5` reader - Peripheral ID 5"] +pub type GICD_PIDR5_R = crate::FieldReader; +#[doc = "Peripheral ID 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR5_A { + #[doc = "0: Valid"] + VALID = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR5_A) -> Self { + variant as _ + } +} +impl GICD_PIDR5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GICD_PIDR5_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR5_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 5"] + #[inline(always)] + pub fn gicd_pidr5(&self) -> GICD_PIDR5_R { + GICD_PIDR5_R::new(self.bits) + } +} +#[doc = "Peripheral ID 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr5](index.html) module"] +pub struct GICD_PIDR5_SPEC; +impl crate::RegisterSpec for GICD_PIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr5::R](R) reader structure"] +impl crate::Readable for GICD_PIDR5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR5 to value 0"] +impl crate::Resettable for GICD_PIDR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs new file mode 100644 index 0000000..6f706f8 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR6` reader - Peripheral ID 6"] +pub type GICD_PIDR6_R = crate::FieldReader; +#[doc = "Peripheral ID 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR6_A { + #[doc = "0: Valid"] + VALID = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR6_A) -> Self { + variant as _ + } +} +impl GICD_PIDR6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GICD_PIDR6_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR6_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 6"] + #[inline(always)] + pub fn gicd_pidr6(&self) -> GICD_PIDR6_R { + GICD_PIDR6_R::new(self.bits) + } +} +#[doc = "Peripheral ID 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr6](index.html) module"] +pub struct GICD_PIDR6_SPEC; +impl crate::RegisterSpec for GICD_PIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr6::R](R) reader structure"] +impl crate::Readable for GICD_PIDR6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR6 to value 0"] +impl crate::Resettable for GICD_PIDR6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs new file mode 100644 index 0000000..6be8720 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GICD_PIDR7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `GICD_PIDR7` reader - Peripheral ID 7"] +pub type GICD_PIDR7_R = crate::FieldReader; +#[doc = "Peripheral ID 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum GICD_PIDR7_A { + #[doc = "0: Valid"] + VALID = 0, +} +impl From for u32 { + #[inline(always)] + fn from(variant: GICD_PIDR7_A) -> Self { + variant as _ + } +} +impl GICD_PIDR7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GICD_PIDR7_A::VALID), + _ => None, + } + } + #[doc = "Checks if the value of the field is `VALID`"] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == GICD_PIDR7_A::VALID + } +} +impl R { + #[doc = "Bits 0:31 - Peripheral ID 7"] + #[inline(always)] + pub fn gicd_pidr7(&self) -> GICD_PIDR7_R { + GICD_PIDR7_R::new(self.bits) + } +} +#[doc = "Peripheral ID 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr7](index.html) module"] +pub struct GICD_PIDR7_SPEC; +impl crate::RegisterSpec for GICD_PIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_pidr7::R](R) reader structure"] +impl crate::Readable for GICD_PIDR7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_PIDR7 to value 0"] +impl crate::Resettable for GICD_PIDR7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs new file mode 100644 index 0000000..1c98035 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs @@ -0,0 +1,170 @@ +#[doc = "Register `GICD_PPISR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_PPISR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID25` reader - Virtual maintenance interrupt"] +pub type ID25_R = crate::BitReader; +#[doc = "Field `ID25` writer - Virtual maintenance interrupt"] +pub type ID25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +#[doc = "Field `ID26` reader - Hypervisor timer event"] +pub type ID26_R = crate::BitReader; +#[doc = "Field `ID26` writer - Hypervisor timer event"] +pub type ID26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +#[doc = "Field `ID27` reader - Virtual timer event"] +pub type ID27_R = crate::BitReader; +#[doc = "Field `ID27` writer - Virtual timer event"] +pub type ID27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +#[doc = "Field `ID28` reader - nLEGACYFIQ signal"] +pub type ID28_R = crate::BitReader; +#[doc = "Field `ID28` writer - nLEGACYFIQ signal"] +pub type ID28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +#[doc = "Field `ID29` reader - Secure physical timer event"] +pub type ID29_R = crate::BitReader; +#[doc = "Field `ID29` writer - Secure physical timer event"] +pub type ID29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +#[doc = "Field `ID30` reader - Non-secure physical timer event"] +pub type ID30_R = crate::BitReader; +#[doc = "Field `ID30` writer - Non-secure physical timer event"] +pub type ID30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +#[doc = "Field `ID31` reader - nLEGACYIRQ signal"] +pub type ID31_R = crate::BitReader; +#[doc = "Field `ID31` writer - nLEGACYIRQ signal"] +pub type ID31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +impl R { + #[doc = "Bit 9 - Virtual maintenance interrupt"] + #[inline(always)] + pub fn id25(&self) -> ID25_R { + ID25_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Hypervisor timer event"] + #[inline(always)] + pub fn id26(&self) -> ID26_R { + ID26_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Virtual timer event"] + #[inline(always)] + pub fn id27(&self) -> ID27_R { + ID27_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - nLEGACYFIQ signal"] + #[inline(always)] + pub fn id28(&self) -> ID28_R { + ID28_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Secure physical timer event"] + #[inline(always)] + pub fn id29(&self) -> ID29_R { + ID29_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Non-secure physical timer event"] + #[inline(always)] + pub fn id30(&self) -> ID30_R { + ID30_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - nLEGACYIRQ signal"] + #[inline(always)] + pub fn id31(&self) -> ID31_R { + ID31_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 9 - Virtual maintenance interrupt"] + #[inline(always)] + #[must_use] + pub fn id25(&mut self) -> ID25_W<9> { + ID25_W::new(self) + } + #[doc = "Bit 10 - Hypervisor timer event"] + #[inline(always)] + #[must_use] + pub fn id26(&mut self) -> ID26_W<10> { + ID26_W::new(self) + } + #[doc = "Bit 11 - Virtual timer event"] + #[inline(always)] + #[must_use] + pub fn id27(&mut self) -> ID27_W<11> { + ID27_W::new(self) + } + #[doc = "Bit 12 - nLEGACYFIQ signal"] + #[inline(always)] + #[must_use] + pub fn id28(&mut self) -> ID28_W<12> { + ID28_W::new(self) + } + #[doc = "Bit 13 - Secure physical timer event"] + #[inline(always)] + #[must_use] + pub fn id29(&mut self) -> ID29_W<13> { + ID29_W::new(self) + } + #[doc = "Bit 14 - Non-secure physical timer event"] + #[inline(always)] + #[must_use] + pub fn id30(&mut self) -> ID30_W<14> { + ID30_W::new(self) + } + #[doc = "Bit 15 - nLEGACYIRQ signal"] + #[inline(always)] + #[must_use] + pub fn id31(&mut self) -> ID31_W<15> { + ID31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Private Peripheral Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ppisr](index.html) module"] +pub struct GICD_PPISR_SPEC; +impl crate::RegisterSpec for GICD_PPISR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_ppisr::R](R) reader structure"] +impl crate::Readable for GICD_PPISR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_ppisr::W](W) writer structure"] +impl crate::Writable for GICD_PPISR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_PPISR to value 0"] +impl crate::Resettable for GICD_PPISR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs new file mode 100644 index 0000000..fc59dc1 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs @@ -0,0 +1,40 @@ +#[doc = "Register `GICD_SGIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Generated Interrupt Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_sgir](index.html) module"] +pub struct GICD_SGIR_SPEC; +impl crate::RegisterSpec for GICD_SGIR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gicd_sgir::W](W) writer structure"] +impl crate::Writable for GICD_SGIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs new file mode 100644 index 0000000..25310c6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GICD_SPENDSGIRn` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPENDSGIRn` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SGI Set-Pending Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spendsgirn](index.html) module"] +pub struct GICD_SPENDSGIRN_SPEC; +impl crate::RegisterSpec for GICD_SPENDSGIRN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spendsgirn::R](R) reader structure"] +impl crate::Readable for GICD_SPENDSGIRN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spendsgirn::W](W) writer structure"] +impl crate::Writable for GICD_SPENDSGIRN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPENDSGIRn to value 0"] +impl crate::Resettable for GICD_SPENDSGIRN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs new file mode 100644 index 0000000..24de248 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_SPISR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPISR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPI32` reader - Shared interrupt 32"] +pub type SPI32_R = crate::BitReader; +#[doc = "Field `SPI32` writer - Shared interrupt 32"] +pub type SPI32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI33` reader - Shared interrupt 33"] +pub type SPI33_R = crate::BitReader; +#[doc = "Field `SPI33` writer - Shared interrupt 33"] +pub type SPI33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI34` reader - Shared interrupt 34"] +pub type SPI34_R = crate::BitReader; +#[doc = "Field `SPI34` writer - Shared interrupt 34"] +pub type SPI34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI35` reader - Shared interrupt 35"] +pub type SPI35_R = crate::BitReader; +#[doc = "Field `SPI35` writer - Shared interrupt 35"] +pub type SPI35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI36` reader - Shared interrupt 36"] +pub type SPI36_R = crate::BitReader; +#[doc = "Field `SPI36` writer - Shared interrupt 36"] +pub type SPI36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI37` reader - Shared interrupt 37"] +pub type SPI37_R = crate::BitReader; +#[doc = "Field `SPI37` writer - Shared interrupt 37"] +pub type SPI37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI38` reader - Shared interrupt 38"] +pub type SPI38_R = crate::BitReader; +#[doc = "Field `SPI38` writer - Shared interrupt 38"] +pub type SPI38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI39` reader - Shared interrupt 39"] +pub type SPI39_R = crate::BitReader; +#[doc = "Field `SPI39` writer - Shared interrupt 39"] +pub type SPI39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI40` reader - Shared interrupt 40"] +pub type SPI40_R = crate::BitReader; +#[doc = "Field `SPI40` writer - Shared interrupt 40"] +pub type SPI40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI41` reader - Shared interrupt 41"] +pub type SPI41_R = crate::BitReader; +#[doc = "Field `SPI41` writer - Shared interrupt 41"] +pub type SPI41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI42` reader - Shared interrupt 42"] +pub type SPI42_R = crate::BitReader; +#[doc = "Field `SPI42` writer - Shared interrupt 42"] +pub type SPI42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI43` reader - Shared interrupt 43"] +pub type SPI43_R = crate::BitReader; +#[doc = "Field `SPI43` writer - Shared interrupt 43"] +pub type SPI43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI44` reader - Shared interrupt 44"] +pub type SPI44_R = crate::BitReader; +#[doc = "Field `SPI44` writer - Shared interrupt 44"] +pub type SPI44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI45` reader - Shared interrupt 45"] +pub type SPI45_R = crate::BitReader; +#[doc = "Field `SPI45` writer - Shared interrupt 45"] +pub type SPI45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI46` reader - Shared interrupt 46"] +pub type SPI46_R = crate::BitReader; +#[doc = "Field `SPI46` writer - Shared interrupt 46"] +pub type SPI46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI47` reader - Shared interrupt 47"] +pub type SPI47_R = crate::BitReader; +#[doc = "Field `SPI47` writer - Shared interrupt 47"] +pub type SPI47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI48` reader - Shared interrupt 48"] +pub type SPI48_R = crate::BitReader; +#[doc = "Field `SPI48` writer - Shared interrupt 48"] +pub type SPI48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI49` reader - Shared interrupt 49"] +pub type SPI49_R = crate::BitReader; +#[doc = "Field `SPI49` writer - Shared interrupt 49"] +pub type SPI49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI50` reader - Shared interrupt 50"] +pub type SPI50_R = crate::BitReader; +#[doc = "Field `SPI50` writer - Shared interrupt 50"] +pub type SPI50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI51` reader - Shared interrupt 51"] +pub type SPI51_R = crate::BitReader; +#[doc = "Field `SPI51` writer - Shared interrupt 51"] +pub type SPI51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI52` reader - Shared interrupt 52"] +pub type SPI52_R = crate::BitReader; +#[doc = "Field `SPI52` writer - Shared interrupt 52"] +pub type SPI52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI53` reader - Shared interrupt 53"] +pub type SPI53_R = crate::BitReader; +#[doc = "Field `SPI53` writer - Shared interrupt 53"] +pub type SPI53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI54` reader - Shared interrupt 54"] +pub type SPI54_R = crate::BitReader; +#[doc = "Field `SPI54` writer - Shared interrupt 54"] +pub type SPI54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI55` reader - Shared interrupt 55"] +pub type SPI55_R = crate::BitReader; +#[doc = "Field `SPI55` writer - Shared interrupt 55"] +pub type SPI55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI56` reader - Shared interrupt 56"] +pub type SPI56_R = crate::BitReader; +#[doc = "Field `SPI56` writer - Shared interrupt 56"] +pub type SPI56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI57` reader - Shared interrupt 57"] +pub type SPI57_R = crate::BitReader; +#[doc = "Field `SPI57` writer - Shared interrupt 57"] +pub type SPI57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI58` reader - Shared interrupt 58"] +pub type SPI58_R = crate::BitReader; +#[doc = "Field `SPI58` writer - Shared interrupt 58"] +pub type SPI58_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI59` reader - Shared interrupt 59"] +pub type SPI59_R = crate::BitReader; +#[doc = "Field `SPI59` writer - Shared interrupt 59"] +pub type SPI59_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI60` reader - Shared interrupt 60"] +pub type SPI60_R = crate::BitReader; +#[doc = "Field `SPI60` writer - Shared interrupt 60"] +pub type SPI60_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI61` reader - Shared interrupt 61"] +pub type SPI61_R = crate::BitReader; +#[doc = "Field `SPI61` writer - Shared interrupt 61"] +pub type SPI61_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI62` reader - Shared interrupt 62"] +pub type SPI62_R = crate::BitReader; +#[doc = "Field `SPI62` writer - Shared interrupt 62"] +pub type SPI62_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +#[doc = "Field `SPI63` reader - Shared interrupt 63"] +pub type SPI63_R = crate::BitReader; +#[doc = "Field `SPI63` writer - Shared interrupt 63"] +pub type SPI63_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Shared interrupt 32"] + #[inline(always)] + pub fn spi32(&self) -> SPI32_R { + SPI32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shared interrupt 33"] + #[inline(always)] + pub fn spi33(&self) -> SPI33_R { + SPI33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Shared interrupt 34"] + #[inline(always)] + pub fn spi34(&self) -> SPI34_R { + SPI34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Shared interrupt 35"] + #[inline(always)] + pub fn spi35(&self) -> SPI35_R { + SPI35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Shared interrupt 36"] + #[inline(always)] + pub fn spi36(&self) -> SPI36_R { + SPI36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Shared interrupt 37"] + #[inline(always)] + pub fn spi37(&self) -> SPI37_R { + SPI37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Shared interrupt 38"] + #[inline(always)] + pub fn spi38(&self) -> SPI38_R { + SPI38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Shared interrupt 39"] + #[inline(always)] + pub fn spi39(&self) -> SPI39_R { + SPI39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Shared interrupt 40"] + #[inline(always)] + pub fn spi40(&self) -> SPI40_R { + SPI40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Shared interrupt 41"] + #[inline(always)] + pub fn spi41(&self) -> SPI41_R { + SPI41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Shared interrupt 42"] + #[inline(always)] + pub fn spi42(&self) -> SPI42_R { + SPI42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Shared interrupt 43"] + #[inline(always)] + pub fn spi43(&self) -> SPI43_R { + SPI43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Shared interrupt 44"] + #[inline(always)] + pub fn spi44(&self) -> SPI44_R { + SPI44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Shared interrupt 45"] + #[inline(always)] + pub fn spi45(&self) -> SPI45_R { + SPI45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Shared interrupt 46"] + #[inline(always)] + pub fn spi46(&self) -> SPI46_R { + SPI46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Shared interrupt 47"] + #[inline(always)] + pub fn spi47(&self) -> SPI47_R { + SPI47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Shared interrupt 48"] + #[inline(always)] + pub fn spi48(&self) -> SPI48_R { + SPI48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Shared interrupt 49"] + #[inline(always)] + pub fn spi49(&self) -> SPI49_R { + SPI49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Shared interrupt 50"] + #[inline(always)] + pub fn spi50(&self) -> SPI50_R { + SPI50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Shared interrupt 51"] + #[inline(always)] + pub fn spi51(&self) -> SPI51_R { + SPI51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Shared interrupt 52"] + #[inline(always)] + pub fn spi52(&self) -> SPI52_R { + SPI52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Shared interrupt 53"] + #[inline(always)] + pub fn spi53(&self) -> SPI53_R { + SPI53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Shared interrupt 54"] + #[inline(always)] + pub fn spi54(&self) -> SPI54_R { + SPI54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Shared interrupt 55"] + #[inline(always)] + pub fn spi55(&self) -> SPI55_R { + SPI55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Shared interrupt 56"] + #[inline(always)] + pub fn spi56(&self) -> SPI56_R { + SPI56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Shared interrupt 57"] + #[inline(always)] + pub fn spi57(&self) -> SPI57_R { + SPI57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Shared interrupt 58"] + #[inline(always)] + pub fn spi58(&self) -> SPI58_R { + SPI58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Shared interrupt 59"] + #[inline(always)] + pub fn spi59(&self) -> SPI59_R { + SPI59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Shared interrupt 60"] + #[inline(always)] + pub fn spi60(&self) -> SPI60_R { + SPI60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Shared interrupt 61"] + #[inline(always)] + pub fn spi61(&self) -> SPI61_R { + SPI61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Shared interrupt 62"] + #[inline(always)] + pub fn spi62(&self) -> SPI62_R { + SPI62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Shared interrupt 63"] + #[inline(always)] + pub fn spi63(&self) -> SPI63_R { + SPI63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Shared interrupt 32"] + #[inline(always)] + #[must_use] + pub fn spi32(&mut self) -> SPI32_W<0> { + SPI32_W::new(self) + } + #[doc = "Bit 1 - Shared interrupt 33"] + #[inline(always)] + #[must_use] + pub fn spi33(&mut self) -> SPI33_W<1> { + SPI33_W::new(self) + } + #[doc = "Bit 2 - Shared interrupt 34"] + #[inline(always)] + #[must_use] + pub fn spi34(&mut self) -> SPI34_W<2> { + SPI34_W::new(self) + } + #[doc = "Bit 3 - Shared interrupt 35"] + #[inline(always)] + #[must_use] + pub fn spi35(&mut self) -> SPI35_W<3> { + SPI35_W::new(self) + } + #[doc = "Bit 4 - Shared interrupt 36"] + #[inline(always)] + #[must_use] + pub fn spi36(&mut self) -> SPI36_W<4> { + SPI36_W::new(self) + } + #[doc = "Bit 5 - Shared interrupt 37"] + #[inline(always)] + #[must_use] + pub fn spi37(&mut self) -> SPI37_W<5> { + SPI37_W::new(self) + } + #[doc = "Bit 6 - Shared interrupt 38"] + #[inline(always)] + #[must_use] + pub fn spi38(&mut self) -> SPI38_W<6> { + SPI38_W::new(self) + } + #[doc = "Bit 7 - Shared interrupt 39"] + #[inline(always)] + #[must_use] + pub fn spi39(&mut self) -> SPI39_W<7> { + SPI39_W::new(self) + } + #[doc = "Bit 8 - Shared interrupt 40"] + #[inline(always)] + #[must_use] + pub fn spi40(&mut self) -> SPI40_W<8> { + SPI40_W::new(self) + } + #[doc = "Bit 9 - Shared interrupt 41"] + #[inline(always)] + #[must_use] + pub fn spi41(&mut self) -> SPI41_W<9> { + SPI41_W::new(self) + } + #[doc = "Bit 10 - Shared interrupt 42"] + #[inline(always)] + #[must_use] + pub fn spi42(&mut self) -> SPI42_W<10> { + SPI42_W::new(self) + } + #[doc = "Bit 11 - Shared interrupt 43"] + #[inline(always)] + #[must_use] + pub fn spi43(&mut self) -> SPI43_W<11> { + SPI43_W::new(self) + } + #[doc = "Bit 12 - Shared interrupt 44"] + #[inline(always)] + #[must_use] + pub fn spi44(&mut self) -> SPI44_W<12> { + SPI44_W::new(self) + } + #[doc = "Bit 13 - Shared interrupt 45"] + #[inline(always)] + #[must_use] + pub fn spi45(&mut self) -> SPI45_W<13> { + SPI45_W::new(self) + } + #[doc = "Bit 14 - Shared interrupt 46"] + #[inline(always)] + #[must_use] + pub fn spi46(&mut self) -> SPI46_W<14> { + SPI46_W::new(self) + } + #[doc = "Bit 15 - Shared interrupt 47"] + #[inline(always)] + #[must_use] + pub fn spi47(&mut self) -> SPI47_W<15> { + SPI47_W::new(self) + } + #[doc = "Bit 16 - Shared interrupt 48"] + #[inline(always)] + #[must_use] + pub fn spi48(&mut self) -> SPI48_W<16> { + SPI48_W::new(self) + } + #[doc = "Bit 17 - Shared interrupt 49"] + #[inline(always)] + #[must_use] + pub fn spi49(&mut self) -> SPI49_W<17> { + SPI49_W::new(self) + } + #[doc = "Bit 18 - Shared interrupt 50"] + #[inline(always)] + #[must_use] + pub fn spi50(&mut self) -> SPI50_W<18> { + SPI50_W::new(self) + } + #[doc = "Bit 19 - Shared interrupt 51"] + #[inline(always)] + #[must_use] + pub fn spi51(&mut self) -> SPI51_W<19> { + SPI51_W::new(self) + } + #[doc = "Bit 20 - Shared interrupt 52"] + #[inline(always)] + #[must_use] + pub fn spi52(&mut self) -> SPI52_W<20> { + SPI52_W::new(self) + } + #[doc = "Bit 21 - Shared interrupt 53"] + #[inline(always)] + #[must_use] + pub fn spi53(&mut self) -> SPI53_W<21> { + SPI53_W::new(self) + } + #[doc = "Bit 22 - Shared interrupt 54"] + #[inline(always)] + #[must_use] + pub fn spi54(&mut self) -> SPI54_W<22> { + SPI54_W::new(self) + } + #[doc = "Bit 23 - Shared interrupt 55"] + #[inline(always)] + #[must_use] + pub fn spi55(&mut self) -> SPI55_W<23> { + SPI55_W::new(self) + } + #[doc = "Bit 24 - Shared interrupt 56"] + #[inline(always)] + #[must_use] + pub fn spi56(&mut self) -> SPI56_W<24> { + SPI56_W::new(self) + } + #[doc = "Bit 25 - Shared interrupt 57"] + #[inline(always)] + #[must_use] + pub fn spi57(&mut self) -> SPI57_W<25> { + SPI57_W::new(self) + } + #[doc = "Bit 26 - Shared interrupt 58"] + #[inline(always)] + #[must_use] + pub fn spi58(&mut self) -> SPI58_W<26> { + SPI58_W::new(self) + } + #[doc = "Bit 27 - Shared interrupt 59"] + #[inline(always)] + #[must_use] + pub fn spi59(&mut self) -> SPI59_W<27> { + SPI59_W::new(self) + } + #[doc = "Bit 28 - Shared interrupt 60"] + #[inline(always)] + #[must_use] + pub fn spi60(&mut self) -> SPI60_W<28> { + SPI60_W::new(self) + } + #[doc = "Bit 29 - Shared interrupt 61"] + #[inline(always)] + #[must_use] + pub fn spi61(&mut self) -> SPI61_W<29> { + SPI61_W::new(self) + } + #[doc = "Bit 30 - Shared interrupt 62"] + #[inline(always)] + #[must_use] + pub fn spi62(&mut self) -> SPI62_W<30> { + SPI62_W::new(self) + } + #[doc = "Bit 31 - Shared interrupt 63"] + #[inline(always)] + #[must_use] + pub fn spi63(&mut self) -> SPI63_W<31> { + SPI63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr0](index.html) module"] +pub struct GICD_SPISR0_SPEC; +impl crate::RegisterSpec for GICD_SPISR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spisr0::R](R) reader structure"] +impl crate::Readable for GICD_SPISR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spisr0::W](W) writer structure"] +impl crate::Writable for GICD_SPISR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPISR0 to value 0"] +impl crate::Resettable for GICD_SPISR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs new file mode 100644 index 0000000..5a14b66 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs @@ -0,0 +1,546 @@ +#[doc = "Register `GICD_SPISR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPISR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI0` reader - Software interrupt 0"] +pub type SWI0_R = crate::BitReader; +#[doc = "Field `SWI0` writer - Software interrupt 0"] +pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI1` reader - Software interrupt 1"] +pub type SWI1_R = crate::BitReader; +#[doc = "Field `SWI1` writer - Software interrupt 1"] +pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI2` reader - Software interrupt 2"] +pub type SWI2_R = crate::BitReader; +#[doc = "Field `SWI2` writer - Software interrupt 2"] +pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI3` reader - Software interrupt 3"] +pub type SWI3_R = crate::BitReader; +#[doc = "Field `SWI3` writer - Software interrupt 3"] +pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI4` reader - Software interrupt 4"] +pub type SWI4_R = crate::BitReader; +#[doc = "Field `SWI4` writer - Software interrupt 4"] +pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI5` reader - Software interrupt 5"] +pub type SWI5_R = crate::BitReader; +#[doc = "Field `SWI5` writer - Software interrupt 5"] +pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI6` reader - Software interrupt 6"] +pub type SWI6_R = crate::BitReader; +#[doc = "Field `SWI6` writer - Software interrupt 6"] +pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SWI7` reader - Software interrupt 7"] +pub type SWI7_R = crate::BitReader; +#[doc = "Field `SWI7` writer - Software interrupt 7"] +pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI80` reader - Shared interrupt 80"] +pub type SPI80_R = crate::BitReader; +#[doc = "Field `SPI80` writer - Shared interrupt 80"] +pub type SPI80_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI81` reader - Shared interrupt 81"] +pub type SPI81_R = crate::BitReader; +#[doc = "Field `SPI81` writer - Shared interrupt 81"] +pub type SPI81_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI82` reader - Shared interrupt 82"] +pub type SPI82_R = crate::BitReader; +#[doc = "Field `SPI82` writer - Shared interrupt 82"] +pub type SPI82_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI83` reader - Shared interrupt 83"] +pub type SPI83_R = crate::BitReader; +#[doc = "Field `SPI83` writer - Shared interrupt 83"] +pub type SPI83_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI84` reader - Shared interrupt 84"] +pub type SPI84_R = crate::BitReader; +#[doc = "Field `SPI84` writer - Shared interrupt 84"] +pub type SPI84_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI85` reader - Shared interrupt 85"] +pub type SPI85_R = crate::BitReader; +#[doc = "Field `SPI85` writer - Shared interrupt 85"] +pub type SPI85_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI86` reader - Shared interrupt 86"] +pub type SPI86_R = crate::BitReader; +#[doc = "Field `SPI86` writer - Shared interrupt 86"] +pub type SPI86_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI87` reader - Shared interrupt 87"] +pub type SPI87_R = crate::BitReader; +#[doc = "Field `SPI87` writer - Shared interrupt 87"] +pub type SPI87_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI88` reader - Shared interrupt 88"] +pub type SPI88_R = crate::BitReader; +#[doc = "Field `SPI88` writer - Shared interrupt 88"] +pub type SPI88_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI89` reader - Shared interrupt 89"] +pub type SPI89_R = crate::BitReader; +#[doc = "Field `SPI89` writer - Shared interrupt 89"] +pub type SPI89_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI90` reader - Shared interrupt 90"] +pub type SPI90_R = crate::BitReader; +#[doc = "Field `SPI90` writer - Shared interrupt 90"] +pub type SPI90_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI91` reader - Shared interrupt 91"] +pub type SPI91_R = crate::BitReader; +#[doc = "Field `SPI91` writer - Shared interrupt 91"] +pub type SPI91_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI92` reader - Shared interrupt 92"] +pub type SPI92_R = crate::BitReader; +#[doc = "Field `SPI92` writer - Shared interrupt 92"] +pub type SPI92_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI93` reader - Shared interrupt 93"] +pub type SPI93_R = crate::BitReader; +#[doc = "Field `SPI93` writer - Shared interrupt 93"] +pub type SPI93_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI94` reader - Shared interrupt 94"] +pub type SPI94_R = crate::BitReader; +#[doc = "Field `SPI94` writer - Shared interrupt 94"] +pub type SPI94_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +#[doc = "Field `SPI95` reader - Shared interrupt 95"] +pub type SPI95_R = crate::BitReader; +#[doc = "Field `SPI95` writer - Shared interrupt 95"] +pub type SPI95_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + pub fn swi0(&self) -> SWI0_R { + SWI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + pub fn swi1(&self) -> SWI1_R { + SWI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + pub fn swi2(&self) -> SWI2_R { + SWI2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + pub fn swi3(&self) -> SWI3_R { + SWI3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + pub fn swi4(&self) -> SWI4_R { + SWI4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + pub fn swi5(&self) -> SWI5_R { + SWI5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + pub fn swi6(&self) -> SWI6_R { + SWI6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + pub fn swi7(&self) -> SWI7_R { + SWI7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Shared interrupt 80"] + #[inline(always)] + pub fn spi80(&self) -> SPI80_R { + SPI80_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Shared interrupt 81"] + #[inline(always)] + pub fn spi81(&self) -> SPI81_R { + SPI81_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Shared interrupt 82"] + #[inline(always)] + pub fn spi82(&self) -> SPI82_R { + SPI82_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Shared interrupt 83"] + #[inline(always)] + pub fn spi83(&self) -> SPI83_R { + SPI83_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Shared interrupt 84"] + #[inline(always)] + pub fn spi84(&self) -> SPI84_R { + SPI84_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Shared interrupt 85"] + #[inline(always)] + pub fn spi85(&self) -> SPI85_R { + SPI85_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Shared interrupt 86"] + #[inline(always)] + pub fn spi86(&self) -> SPI86_R { + SPI86_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Shared interrupt 87"] + #[inline(always)] + pub fn spi87(&self) -> SPI87_R { + SPI87_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Shared interrupt 88"] + #[inline(always)] + pub fn spi88(&self) -> SPI88_R { + SPI88_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Shared interrupt 89"] + #[inline(always)] + pub fn spi89(&self) -> SPI89_R { + SPI89_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Shared interrupt 90"] + #[inline(always)] + pub fn spi90(&self) -> SPI90_R { + SPI90_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Shared interrupt 91"] + #[inline(always)] + pub fn spi91(&self) -> SPI91_R { + SPI91_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Shared interrupt 92"] + #[inline(always)] + pub fn spi92(&self) -> SPI92_R { + SPI92_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Shared interrupt 93"] + #[inline(always)] + pub fn spi93(&self) -> SPI93_R { + SPI93_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Shared interrupt 94"] + #[inline(always)] + pub fn spi94(&self) -> SPI94_R { + SPI94_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Shared interrupt 95"] + #[inline(always)] + pub fn spi95(&self) -> SPI95_R { + SPI95_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Bit 8 - Software interrupt 0"] + #[inline(always)] + #[must_use] + pub fn swi0(&mut self) -> SWI0_W<8> { + SWI0_W::new(self) + } + #[doc = "Bit 9 - Software interrupt 1"] + #[inline(always)] + #[must_use] + pub fn swi1(&mut self) -> SWI1_W<9> { + SWI1_W::new(self) + } + #[doc = "Bit 10 - Software interrupt 2"] + #[inline(always)] + #[must_use] + pub fn swi2(&mut self) -> SWI2_W<10> { + SWI2_W::new(self) + } + #[doc = "Bit 11 - Software interrupt 3"] + #[inline(always)] + #[must_use] + pub fn swi3(&mut self) -> SWI3_W<11> { + SWI3_W::new(self) + } + #[doc = "Bit 12 - Software interrupt 4"] + #[inline(always)] + #[must_use] + pub fn swi4(&mut self) -> SWI4_W<12> { + SWI4_W::new(self) + } + #[doc = "Bit 13 - Software interrupt 5"] + #[inline(always)] + #[must_use] + pub fn swi5(&mut self) -> SWI5_W<13> { + SWI5_W::new(self) + } + #[doc = "Bit 14 - Software interrupt 6"] + #[inline(always)] + #[must_use] + pub fn swi6(&mut self) -> SWI6_W<14> { + SWI6_W::new(self) + } + #[doc = "Bit 15 - Software interrupt 7"] + #[inline(always)] + #[must_use] + pub fn swi7(&mut self) -> SWI7_W<15> { + SWI7_W::new(self) + } + #[doc = "Bit 16 - Shared interrupt 80"] + #[inline(always)] + #[must_use] + pub fn spi80(&mut self) -> SPI80_W<16> { + SPI80_W::new(self) + } + #[doc = "Bit 17 - Shared interrupt 81"] + #[inline(always)] + #[must_use] + pub fn spi81(&mut self) -> SPI81_W<17> { + SPI81_W::new(self) + } + #[doc = "Bit 18 - Shared interrupt 82"] + #[inline(always)] + #[must_use] + pub fn spi82(&mut self) -> SPI82_W<18> { + SPI82_W::new(self) + } + #[doc = "Bit 19 - Shared interrupt 83"] + #[inline(always)] + #[must_use] + pub fn spi83(&mut self) -> SPI83_W<19> { + SPI83_W::new(self) + } + #[doc = "Bit 20 - Shared interrupt 84"] + #[inline(always)] + #[must_use] + pub fn spi84(&mut self) -> SPI84_W<20> { + SPI84_W::new(self) + } + #[doc = "Bit 21 - Shared interrupt 85"] + #[inline(always)] + #[must_use] + pub fn spi85(&mut self) -> SPI85_W<21> { + SPI85_W::new(self) + } + #[doc = "Bit 22 - Shared interrupt 86"] + #[inline(always)] + #[must_use] + pub fn spi86(&mut self) -> SPI86_W<22> { + SPI86_W::new(self) + } + #[doc = "Bit 23 - Shared interrupt 87"] + #[inline(always)] + #[must_use] + pub fn spi87(&mut self) -> SPI87_W<23> { + SPI87_W::new(self) + } + #[doc = "Bit 24 - Shared interrupt 88"] + #[inline(always)] + #[must_use] + pub fn spi88(&mut self) -> SPI88_W<24> { + SPI88_W::new(self) + } + #[doc = "Bit 25 - Shared interrupt 89"] + #[inline(always)] + #[must_use] + pub fn spi89(&mut self) -> SPI89_W<25> { + SPI89_W::new(self) + } + #[doc = "Bit 26 - Shared interrupt 90"] + #[inline(always)] + #[must_use] + pub fn spi90(&mut self) -> SPI90_W<26> { + SPI90_W::new(self) + } + #[doc = "Bit 27 - Shared interrupt 91"] + #[inline(always)] + #[must_use] + pub fn spi91(&mut self) -> SPI91_W<27> { + SPI91_W::new(self) + } + #[doc = "Bit 28 - Shared interrupt 92"] + #[inline(always)] + #[must_use] + pub fn spi92(&mut self) -> SPI92_W<28> { + SPI92_W::new(self) + } + #[doc = "Bit 29 - Shared interrupt 93"] + #[inline(always)] + #[must_use] + pub fn spi93(&mut self) -> SPI93_W<29> { + SPI93_W::new(self) + } + #[doc = "Bit 30 - Shared interrupt 94"] + #[inline(always)] + #[must_use] + pub fn spi94(&mut self) -> SPI94_W<30> { + SPI94_W::new(self) + } + #[doc = "Bit 31 - Shared interrupt 95"] + #[inline(always)] + #[must_use] + pub fn spi95(&mut self) -> SPI95_W<31> { + SPI95_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr1](index.html) module"] +pub struct GICD_SPISR1_SPEC; +impl crate::RegisterSpec for GICD_SPISR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spisr1::R](R) reader structure"] +impl crate::Readable for GICD_SPISR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spisr1::W](W) writer structure"] +impl crate::Writable for GICD_SPISR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPISR1 to value 0"] +impl crate::Resettable for GICD_SPISR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs new file mode 100644 index 0000000..ba4b79d --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_SPISR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPISR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr2](index.html) module"] +pub struct GICD_SPISR2_SPEC; +impl crate::RegisterSpec for GICD_SPISR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spisr2::R](R) reader structure"] +impl crate::Readable for GICD_SPISR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spisr2::W](W) writer structure"] +impl crate::Writable for GICD_SPISR2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPISR2 to value 0"] +impl crate::Resettable for GICD_SPISR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs new file mode 100644 index 0000000..18ccfd0 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_SPISR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPISR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr3](index.html) module"] +pub struct GICD_SPISR3_SPEC; +impl crate::RegisterSpec for GICD_SPISR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spisr3::R](R) reader structure"] +impl crate::Readable for GICD_SPISR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spisr3::W](W) writer structure"] +impl crate::Writable for GICD_SPISR3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPISR3 to value 0"] +impl crate::Resettable for GICD_SPISR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs new file mode 100644 index 0000000..5ffc919 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_SPISR4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPISR4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPI160` reader - Shared interrupt 160"] +pub type SPI160_R = crate::BitReader; +#[doc = "Field `SPI160` writer - Shared interrupt 160"] +pub type SPI160_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI161` reader - Shared interrupt 161"] +pub type SPI161_R = crate::BitReader; +#[doc = "Field `SPI161` writer - Shared interrupt 161"] +pub type SPI161_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI162` reader - Shared interrupt 162"] +pub type SPI162_R = crate::BitReader; +#[doc = "Field `SPI162` writer - Shared interrupt 162"] +pub type SPI162_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI163` reader - Shared interrupt 163"] +pub type SPI163_R = crate::BitReader; +#[doc = "Field `SPI163` writer - Shared interrupt 163"] +pub type SPI163_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI164` reader - Shared interrupt 164"] +pub type SPI164_R = crate::BitReader; +#[doc = "Field `SPI164` writer - Shared interrupt 164"] +pub type SPI164_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI165` reader - Shared interrupt 165"] +pub type SPI165_R = crate::BitReader; +#[doc = "Field `SPI165` writer - Shared interrupt 165"] +pub type SPI165_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI166` reader - Shared interrupt 166"] +pub type SPI166_R = crate::BitReader; +#[doc = "Field `SPI166` writer - Shared interrupt 166"] +pub type SPI166_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI167` reader - Shared interrupt 167"] +pub type SPI167_R = crate::BitReader; +#[doc = "Field `SPI167` writer - Shared interrupt 167"] +pub type SPI167_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI168` reader - Shared interrupt 168"] +pub type SPI168_R = crate::BitReader; +#[doc = "Field `SPI168` writer - Shared interrupt 168"] +pub type SPI168_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI169` reader - Shared interrupt 169"] +pub type SPI169_R = crate::BitReader; +#[doc = "Field `SPI169` writer - Shared interrupt 169"] +pub type SPI169_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI170` reader - Shared interrupt 170"] +pub type SPI170_R = crate::BitReader; +#[doc = "Field `SPI170` writer - Shared interrupt 170"] +pub type SPI170_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI171` reader - Shared interrupt 171"] +pub type SPI171_R = crate::BitReader; +#[doc = "Field `SPI171` writer - Shared interrupt 171"] +pub type SPI171_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI172` reader - Shared interrupt 172"] +pub type SPI172_R = crate::BitReader; +#[doc = "Field `SPI172` writer - Shared interrupt 172"] +pub type SPI172_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI173` reader - Shared interrupt 173"] +pub type SPI173_R = crate::BitReader; +#[doc = "Field `SPI173` writer - Shared interrupt 173"] +pub type SPI173_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI174` reader - Shared interrupt 174"] +pub type SPI174_R = crate::BitReader; +#[doc = "Field `SPI174` writer - Shared interrupt 174"] +pub type SPI174_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI175` reader - Shared interrupt 175"] +pub type SPI175_R = crate::BitReader; +#[doc = "Field `SPI175` writer - Shared interrupt 175"] +pub type SPI175_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI176` reader - Shared interrupt 176"] +pub type SPI176_R = crate::BitReader; +#[doc = "Field `SPI176` writer - Shared interrupt 176"] +pub type SPI176_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI177` reader - Shared interrupt 177"] +pub type SPI177_R = crate::BitReader; +#[doc = "Field `SPI177` writer - Shared interrupt 177"] +pub type SPI177_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI178` reader - Shared interrupt 178"] +pub type SPI178_R = crate::BitReader; +#[doc = "Field `SPI178` writer - Shared interrupt 178"] +pub type SPI178_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI179` reader - Shared interrupt 179"] +pub type SPI179_R = crate::BitReader; +#[doc = "Field `SPI179` writer - Shared interrupt 179"] +pub type SPI179_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI180` reader - Shared interrupt 180"] +pub type SPI180_R = crate::BitReader; +#[doc = "Field `SPI180` writer - Shared interrupt 180"] +pub type SPI180_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI181` reader - Shared interrupt 181"] +pub type SPI181_R = crate::BitReader; +#[doc = "Field `SPI181` writer - Shared interrupt 181"] +pub type SPI181_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI182` reader - Shared interrupt 182"] +pub type SPI182_R = crate::BitReader; +#[doc = "Field `SPI182` writer - Shared interrupt 182"] +pub type SPI182_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI183` reader - Shared interrupt 183"] +pub type SPI183_R = crate::BitReader; +#[doc = "Field `SPI183` writer - Shared interrupt 183"] +pub type SPI183_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI184` reader - Shared interrupt 184"] +pub type SPI184_R = crate::BitReader; +#[doc = "Field `SPI184` writer - Shared interrupt 184"] +pub type SPI184_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI185` reader - Shared interrupt 185"] +pub type SPI185_R = crate::BitReader; +#[doc = "Field `SPI185` writer - Shared interrupt 185"] +pub type SPI185_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI186` reader - Shared interrupt 186"] +pub type SPI186_R = crate::BitReader; +#[doc = "Field `SPI186` writer - Shared interrupt 186"] +pub type SPI186_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI187` reader - Shared interrupt 187"] +pub type SPI187_R = crate::BitReader; +#[doc = "Field `SPI187` writer - Shared interrupt 187"] +pub type SPI187_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI188` reader - Shared interrupt 188"] +pub type SPI188_R = crate::BitReader; +#[doc = "Field `SPI188` writer - Shared interrupt 188"] +pub type SPI188_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI189` reader - Shared interrupt 189"] +pub type SPI189_R = crate::BitReader; +#[doc = "Field `SPI189` writer - Shared interrupt 189"] +pub type SPI189_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI190` reader - Shared interrupt 190"] +pub type SPI190_R = crate::BitReader; +#[doc = "Field `SPI190` writer - Shared interrupt 190"] +pub type SPI190_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +#[doc = "Field `SPI191` reader - Shared interrupt 191"] +pub type SPI191_R = crate::BitReader; +#[doc = "Field `SPI191` writer - Shared interrupt 191"] +pub type SPI191_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Shared interrupt 160"] + #[inline(always)] + pub fn spi160(&self) -> SPI160_R { + SPI160_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shared interrupt 161"] + #[inline(always)] + pub fn spi161(&self) -> SPI161_R { + SPI161_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Shared interrupt 162"] + #[inline(always)] + pub fn spi162(&self) -> SPI162_R { + SPI162_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Shared interrupt 163"] + #[inline(always)] + pub fn spi163(&self) -> SPI163_R { + SPI163_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Shared interrupt 164"] + #[inline(always)] + pub fn spi164(&self) -> SPI164_R { + SPI164_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Shared interrupt 165"] + #[inline(always)] + pub fn spi165(&self) -> SPI165_R { + SPI165_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Shared interrupt 166"] + #[inline(always)] + pub fn spi166(&self) -> SPI166_R { + SPI166_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Shared interrupt 167"] + #[inline(always)] + pub fn spi167(&self) -> SPI167_R { + SPI167_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Shared interrupt 168"] + #[inline(always)] + pub fn spi168(&self) -> SPI168_R { + SPI168_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Shared interrupt 169"] + #[inline(always)] + pub fn spi169(&self) -> SPI169_R { + SPI169_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Shared interrupt 170"] + #[inline(always)] + pub fn spi170(&self) -> SPI170_R { + SPI170_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Shared interrupt 171"] + #[inline(always)] + pub fn spi171(&self) -> SPI171_R { + SPI171_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Shared interrupt 172"] + #[inline(always)] + pub fn spi172(&self) -> SPI172_R { + SPI172_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Shared interrupt 173"] + #[inline(always)] + pub fn spi173(&self) -> SPI173_R { + SPI173_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Shared interrupt 174"] + #[inline(always)] + pub fn spi174(&self) -> SPI174_R { + SPI174_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Shared interrupt 175"] + #[inline(always)] + pub fn spi175(&self) -> SPI175_R { + SPI175_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Shared interrupt 176"] + #[inline(always)] + pub fn spi176(&self) -> SPI176_R { + SPI176_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Shared interrupt 177"] + #[inline(always)] + pub fn spi177(&self) -> SPI177_R { + SPI177_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Shared interrupt 178"] + #[inline(always)] + pub fn spi178(&self) -> SPI178_R { + SPI178_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Shared interrupt 179"] + #[inline(always)] + pub fn spi179(&self) -> SPI179_R { + SPI179_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Shared interrupt 180"] + #[inline(always)] + pub fn spi180(&self) -> SPI180_R { + SPI180_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Shared interrupt 181"] + #[inline(always)] + pub fn spi181(&self) -> SPI181_R { + SPI181_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Shared interrupt 182"] + #[inline(always)] + pub fn spi182(&self) -> SPI182_R { + SPI182_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Shared interrupt 183"] + #[inline(always)] + pub fn spi183(&self) -> SPI183_R { + SPI183_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Shared interrupt 184"] + #[inline(always)] + pub fn spi184(&self) -> SPI184_R { + SPI184_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Shared interrupt 185"] + #[inline(always)] + pub fn spi185(&self) -> SPI185_R { + SPI185_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Shared interrupt 186"] + #[inline(always)] + pub fn spi186(&self) -> SPI186_R { + SPI186_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Shared interrupt 187"] + #[inline(always)] + pub fn spi187(&self) -> SPI187_R { + SPI187_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Shared interrupt 188"] + #[inline(always)] + pub fn spi188(&self) -> SPI188_R { + SPI188_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Shared interrupt 189"] + #[inline(always)] + pub fn spi189(&self) -> SPI189_R { + SPI189_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Shared interrupt 190"] + #[inline(always)] + pub fn spi190(&self) -> SPI190_R { + SPI190_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Shared interrupt 191"] + #[inline(always)] + pub fn spi191(&self) -> SPI191_R { + SPI191_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Shared interrupt 160"] + #[inline(always)] + #[must_use] + pub fn spi160(&mut self) -> SPI160_W<0> { + SPI160_W::new(self) + } + #[doc = "Bit 1 - Shared interrupt 161"] + #[inline(always)] + #[must_use] + pub fn spi161(&mut self) -> SPI161_W<1> { + SPI161_W::new(self) + } + #[doc = "Bit 2 - Shared interrupt 162"] + #[inline(always)] + #[must_use] + pub fn spi162(&mut self) -> SPI162_W<2> { + SPI162_W::new(self) + } + #[doc = "Bit 3 - Shared interrupt 163"] + #[inline(always)] + #[must_use] + pub fn spi163(&mut self) -> SPI163_W<3> { + SPI163_W::new(self) + } + #[doc = "Bit 4 - Shared interrupt 164"] + #[inline(always)] + #[must_use] + pub fn spi164(&mut self) -> SPI164_W<4> { + SPI164_W::new(self) + } + #[doc = "Bit 5 - Shared interrupt 165"] + #[inline(always)] + #[must_use] + pub fn spi165(&mut self) -> SPI165_W<5> { + SPI165_W::new(self) + } + #[doc = "Bit 6 - Shared interrupt 166"] + #[inline(always)] + #[must_use] + pub fn spi166(&mut self) -> SPI166_W<6> { + SPI166_W::new(self) + } + #[doc = "Bit 7 - Shared interrupt 167"] + #[inline(always)] + #[must_use] + pub fn spi167(&mut self) -> SPI167_W<7> { + SPI167_W::new(self) + } + #[doc = "Bit 8 - Shared interrupt 168"] + #[inline(always)] + #[must_use] + pub fn spi168(&mut self) -> SPI168_W<8> { + SPI168_W::new(self) + } + #[doc = "Bit 9 - Shared interrupt 169"] + #[inline(always)] + #[must_use] + pub fn spi169(&mut self) -> SPI169_W<9> { + SPI169_W::new(self) + } + #[doc = "Bit 10 - Shared interrupt 170"] + #[inline(always)] + #[must_use] + pub fn spi170(&mut self) -> SPI170_W<10> { + SPI170_W::new(self) + } + #[doc = "Bit 11 - Shared interrupt 171"] + #[inline(always)] + #[must_use] + pub fn spi171(&mut self) -> SPI171_W<11> { + SPI171_W::new(self) + } + #[doc = "Bit 12 - Shared interrupt 172"] + #[inline(always)] + #[must_use] + pub fn spi172(&mut self) -> SPI172_W<12> { + SPI172_W::new(self) + } + #[doc = "Bit 13 - Shared interrupt 173"] + #[inline(always)] + #[must_use] + pub fn spi173(&mut self) -> SPI173_W<13> { + SPI173_W::new(self) + } + #[doc = "Bit 14 - Shared interrupt 174"] + #[inline(always)] + #[must_use] + pub fn spi174(&mut self) -> SPI174_W<14> { + SPI174_W::new(self) + } + #[doc = "Bit 15 - Shared interrupt 175"] + #[inline(always)] + #[must_use] + pub fn spi175(&mut self) -> SPI175_W<15> { + SPI175_W::new(self) + } + #[doc = "Bit 16 - Shared interrupt 176"] + #[inline(always)] + #[must_use] + pub fn spi176(&mut self) -> SPI176_W<16> { + SPI176_W::new(self) + } + #[doc = "Bit 17 - Shared interrupt 177"] + #[inline(always)] + #[must_use] + pub fn spi177(&mut self) -> SPI177_W<17> { + SPI177_W::new(self) + } + #[doc = "Bit 18 - Shared interrupt 178"] + #[inline(always)] + #[must_use] + pub fn spi178(&mut self) -> SPI178_W<18> { + SPI178_W::new(self) + } + #[doc = "Bit 19 - Shared interrupt 179"] + #[inline(always)] + #[must_use] + pub fn spi179(&mut self) -> SPI179_W<19> { + SPI179_W::new(self) + } + #[doc = "Bit 20 - Shared interrupt 180"] + #[inline(always)] + #[must_use] + pub fn spi180(&mut self) -> SPI180_W<20> { + SPI180_W::new(self) + } + #[doc = "Bit 21 - Shared interrupt 181"] + #[inline(always)] + #[must_use] + pub fn spi181(&mut self) -> SPI181_W<21> { + SPI181_W::new(self) + } + #[doc = "Bit 22 - Shared interrupt 182"] + #[inline(always)] + #[must_use] + pub fn spi182(&mut self) -> SPI182_W<22> { + SPI182_W::new(self) + } + #[doc = "Bit 23 - Shared interrupt 183"] + #[inline(always)] + #[must_use] + pub fn spi183(&mut self) -> SPI183_W<23> { + SPI183_W::new(self) + } + #[doc = "Bit 24 - Shared interrupt 184"] + #[inline(always)] + #[must_use] + pub fn spi184(&mut self) -> SPI184_W<24> { + SPI184_W::new(self) + } + #[doc = "Bit 25 - Shared interrupt 185"] + #[inline(always)] + #[must_use] + pub fn spi185(&mut self) -> SPI185_W<25> { + SPI185_W::new(self) + } + #[doc = "Bit 26 - Shared interrupt 186"] + #[inline(always)] + #[must_use] + pub fn spi186(&mut self) -> SPI186_W<26> { + SPI186_W::new(self) + } + #[doc = "Bit 27 - Shared interrupt 187"] + #[inline(always)] + #[must_use] + pub fn spi187(&mut self) -> SPI187_W<27> { + SPI187_W::new(self) + } + #[doc = "Bit 28 - Shared interrupt 188"] + #[inline(always)] + #[must_use] + pub fn spi188(&mut self) -> SPI188_W<28> { + SPI188_W::new(self) + } + #[doc = "Bit 29 - Shared interrupt 189"] + #[inline(always)] + #[must_use] + pub fn spi189(&mut self) -> SPI189_W<29> { + SPI189_W::new(self) + } + #[doc = "Bit 30 - Shared interrupt 190"] + #[inline(always)] + #[must_use] + pub fn spi190(&mut self) -> SPI190_W<30> { + SPI190_W::new(self) + } + #[doc = "Bit 31 - Shared interrupt 191"] + #[inline(always)] + #[must_use] + pub fn spi191(&mut self) -> SPI191_W<31> { + SPI191_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr4](index.html) module"] +pub struct GICD_SPISR4_SPEC; +impl crate::RegisterSpec for GICD_SPISR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spisr4::R](R) reader structure"] +impl crate::Readable for GICD_SPISR4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spisr4::W](W) writer structure"] +impl crate::Writable for GICD_SPISR4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPISR4 to value 0"] +impl crate::Resettable for GICD_SPISR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs new file mode 100644 index 0000000..efb5a72 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs @@ -0,0 +1,545 @@ +#[doc = "Register `GICD_SPISR5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GICD_SPISR5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPI192` reader - Shared interrupt 192"] +pub type SPI192_R = crate::BitReader; +#[doc = "Field `SPI192` writer - Shared interrupt 192"] +pub type SPI192_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI193` reader - Shared interrupt 193"] +pub type SPI193_R = crate::BitReader; +#[doc = "Field `SPI193` writer - Shared interrupt 193"] +pub type SPI193_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI194` reader - Shared interrupt 194"] +pub type SPI194_R = crate::BitReader; +#[doc = "Field `SPI194` writer - Shared interrupt 194"] +pub type SPI194_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI195` reader - Shared interrupt 195"] +pub type SPI195_R = crate::BitReader; +#[doc = "Field `SPI195` writer - Shared interrupt 195"] +pub type SPI195_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI196` reader - Shared interrupt 196"] +pub type SPI196_R = crate::BitReader; +#[doc = "Field `SPI196` writer - Shared interrupt 196"] +pub type SPI196_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI197` reader - Shared interrupt 197"] +pub type SPI197_R = crate::BitReader; +#[doc = "Field `SPI197` writer - Shared interrupt 197"] +pub type SPI197_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI198` reader - Shared interrupt 198"] +pub type SPI198_R = crate::BitReader; +#[doc = "Field `SPI198` writer - Shared interrupt 198"] +pub type SPI198_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI199` reader - Shared interrupt 199"] +pub type SPI199_R = crate::BitReader; +#[doc = "Field `SPI199` writer - Shared interrupt 199"] +pub type SPI199_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI200` reader - Shared interrupt 200"] +pub type SPI200_R = crate::BitReader; +#[doc = "Field `SPI200` writer - Shared interrupt 200"] +pub type SPI200_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI201` reader - Shared interrupt 201"] +pub type SPI201_R = crate::BitReader; +#[doc = "Field `SPI201` writer - Shared interrupt 201"] +pub type SPI201_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI202` reader - Shared interrupt 202"] +pub type SPI202_R = crate::BitReader; +#[doc = "Field `SPI202` writer - Shared interrupt 202"] +pub type SPI202_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI203` reader - Shared interrupt 203"] +pub type SPI203_R = crate::BitReader; +#[doc = "Field `SPI203` writer - Shared interrupt 203"] +pub type SPI203_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI204` reader - Shared interrupt 204"] +pub type SPI204_R = crate::BitReader; +#[doc = "Field `SPI204` writer - Shared interrupt 204"] +pub type SPI204_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI205` reader - Shared interrupt 205"] +pub type SPI205_R = crate::BitReader; +#[doc = "Field `SPI205` writer - Shared interrupt 205"] +pub type SPI205_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI206` reader - Shared interrupt 206"] +pub type SPI206_R = crate::BitReader; +#[doc = "Field `SPI206` writer - Shared interrupt 206"] +pub type SPI206_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI207` reader - Shared interrupt 207"] +pub type SPI207_R = crate::BitReader; +#[doc = "Field `SPI207` writer - Shared interrupt 207"] +pub type SPI207_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI208` reader - Shared interrupt 208"] +pub type SPI208_R = crate::BitReader; +#[doc = "Field `SPI208` writer - Shared interrupt 208"] +pub type SPI208_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI209` reader - Shared interrupt 209"] +pub type SPI209_R = crate::BitReader; +#[doc = "Field `SPI209` writer - Shared interrupt 209"] +pub type SPI209_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI210` reader - Shared interrupt 210"] +pub type SPI210_R = crate::BitReader; +#[doc = "Field `SPI210` writer - Shared interrupt 210"] +pub type SPI210_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI211` reader - Shared interrupt 211"] +pub type SPI211_R = crate::BitReader; +#[doc = "Field `SPI211` writer - Shared interrupt 211"] +pub type SPI211_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI212` reader - Shared interrupt 212"] +pub type SPI212_R = crate::BitReader; +#[doc = "Field `SPI212` writer - Shared interrupt 212"] +pub type SPI212_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI213` reader - Shared interrupt 213"] +pub type SPI213_R = crate::BitReader; +#[doc = "Field `SPI213` writer - Shared interrupt 213"] +pub type SPI213_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI214` reader - Shared interrupt 214"] +pub type SPI214_R = crate::BitReader; +#[doc = "Field `SPI214` writer - Shared interrupt 214"] +pub type SPI214_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI215` reader - Shared interrupt 215"] +pub type SPI215_R = crate::BitReader; +#[doc = "Field `SPI215` writer - Shared interrupt 215"] +pub type SPI215_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI216` reader - Shared interrupt 216"] +pub type SPI216_R = crate::BitReader; +#[doc = "Field `SPI216` writer - Shared interrupt 216"] +pub type SPI216_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI217` reader - Shared interrupt 217"] +pub type SPI217_R = crate::BitReader; +#[doc = "Field `SPI217` writer - Shared interrupt 217"] +pub type SPI217_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI218` reader - Shared interrupt 218"] +pub type SPI218_R = crate::BitReader; +#[doc = "Field `SPI218` writer - Shared interrupt 218"] +pub type SPI218_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI219` reader - Shared interrupt 219"] +pub type SPI219_R = crate::BitReader; +#[doc = "Field `SPI219` writer - Shared interrupt 219"] +pub type SPI219_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI220` reader - Shared interrupt 220"] +pub type SPI220_R = crate::BitReader; +#[doc = "Field `SPI220` writer - Shared interrupt 220"] +pub type SPI220_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI221` reader - Shared interrupt 221"] +pub type SPI221_R = crate::BitReader; +#[doc = "Field `SPI221` writer - Shared interrupt 221"] +pub type SPI221_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI222` reader - Shared interrupt 222"] +pub type SPI222_R = crate::BitReader; +#[doc = "Field `SPI222` writer - Shared interrupt 222"] +pub type SPI222_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +#[doc = "Field `SPI223` reader - Shared interrupt 223"] +pub type SPI223_R = crate::BitReader; +#[doc = "Field `SPI223` writer - Shared interrupt 223"] +pub type SPI223_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Shared interrupt 192"] + #[inline(always)] + pub fn spi192(&self) -> SPI192_R { + SPI192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shared interrupt 193"] + #[inline(always)] + pub fn spi193(&self) -> SPI193_R { + SPI193_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Shared interrupt 194"] + #[inline(always)] + pub fn spi194(&self) -> SPI194_R { + SPI194_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Shared interrupt 195"] + #[inline(always)] + pub fn spi195(&self) -> SPI195_R { + SPI195_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Shared interrupt 196"] + #[inline(always)] + pub fn spi196(&self) -> SPI196_R { + SPI196_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Shared interrupt 197"] + #[inline(always)] + pub fn spi197(&self) -> SPI197_R { + SPI197_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Shared interrupt 198"] + #[inline(always)] + pub fn spi198(&self) -> SPI198_R { + SPI198_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Shared interrupt 199"] + #[inline(always)] + pub fn spi199(&self) -> SPI199_R { + SPI199_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Shared interrupt 200"] + #[inline(always)] + pub fn spi200(&self) -> SPI200_R { + SPI200_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Shared interrupt 201"] + #[inline(always)] + pub fn spi201(&self) -> SPI201_R { + SPI201_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Shared interrupt 202"] + #[inline(always)] + pub fn spi202(&self) -> SPI202_R { + SPI202_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Shared interrupt 203"] + #[inline(always)] + pub fn spi203(&self) -> SPI203_R { + SPI203_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Shared interrupt 204"] + #[inline(always)] + pub fn spi204(&self) -> SPI204_R { + SPI204_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Shared interrupt 205"] + #[inline(always)] + pub fn spi205(&self) -> SPI205_R { + SPI205_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Shared interrupt 206"] + #[inline(always)] + pub fn spi206(&self) -> SPI206_R { + SPI206_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Shared interrupt 207"] + #[inline(always)] + pub fn spi207(&self) -> SPI207_R { + SPI207_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Shared interrupt 208"] + #[inline(always)] + pub fn spi208(&self) -> SPI208_R { + SPI208_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Shared interrupt 209"] + #[inline(always)] + pub fn spi209(&self) -> SPI209_R { + SPI209_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Shared interrupt 210"] + #[inline(always)] + pub fn spi210(&self) -> SPI210_R { + SPI210_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Shared interrupt 211"] + #[inline(always)] + pub fn spi211(&self) -> SPI211_R { + SPI211_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Shared interrupt 212"] + #[inline(always)] + pub fn spi212(&self) -> SPI212_R { + SPI212_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Shared interrupt 213"] + #[inline(always)] + pub fn spi213(&self) -> SPI213_R { + SPI213_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Shared interrupt 214"] + #[inline(always)] + pub fn spi214(&self) -> SPI214_R { + SPI214_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Shared interrupt 215"] + #[inline(always)] + pub fn spi215(&self) -> SPI215_R { + SPI215_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Shared interrupt 216"] + #[inline(always)] + pub fn spi216(&self) -> SPI216_R { + SPI216_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Shared interrupt 217"] + #[inline(always)] + pub fn spi217(&self) -> SPI217_R { + SPI217_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Shared interrupt 218"] + #[inline(always)] + pub fn spi218(&self) -> SPI218_R { + SPI218_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Shared interrupt 219"] + #[inline(always)] + pub fn spi219(&self) -> SPI219_R { + SPI219_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Shared interrupt 220"] + #[inline(always)] + pub fn spi220(&self) -> SPI220_R { + SPI220_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Shared interrupt 221"] + #[inline(always)] + pub fn spi221(&self) -> SPI221_R { + SPI221_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Shared interrupt 222"] + #[inline(always)] + pub fn spi222(&self) -> SPI222_R { + SPI222_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Shared interrupt 223"] + #[inline(always)] + pub fn spi223(&self) -> SPI223_R { + SPI223_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Shared interrupt 192"] + #[inline(always)] + #[must_use] + pub fn spi192(&mut self) -> SPI192_W<0> { + SPI192_W::new(self) + } + #[doc = "Bit 1 - Shared interrupt 193"] + #[inline(always)] + #[must_use] + pub fn spi193(&mut self) -> SPI193_W<1> { + SPI193_W::new(self) + } + #[doc = "Bit 2 - Shared interrupt 194"] + #[inline(always)] + #[must_use] + pub fn spi194(&mut self) -> SPI194_W<2> { + SPI194_W::new(self) + } + #[doc = "Bit 3 - Shared interrupt 195"] + #[inline(always)] + #[must_use] + pub fn spi195(&mut self) -> SPI195_W<3> { + SPI195_W::new(self) + } + #[doc = "Bit 4 - Shared interrupt 196"] + #[inline(always)] + #[must_use] + pub fn spi196(&mut self) -> SPI196_W<4> { + SPI196_W::new(self) + } + #[doc = "Bit 5 - Shared interrupt 197"] + #[inline(always)] + #[must_use] + pub fn spi197(&mut self) -> SPI197_W<5> { + SPI197_W::new(self) + } + #[doc = "Bit 6 - Shared interrupt 198"] + #[inline(always)] + #[must_use] + pub fn spi198(&mut self) -> SPI198_W<6> { + SPI198_W::new(self) + } + #[doc = "Bit 7 - Shared interrupt 199"] + #[inline(always)] + #[must_use] + pub fn spi199(&mut self) -> SPI199_W<7> { + SPI199_W::new(self) + } + #[doc = "Bit 8 - Shared interrupt 200"] + #[inline(always)] + #[must_use] + pub fn spi200(&mut self) -> SPI200_W<8> { + SPI200_W::new(self) + } + #[doc = "Bit 9 - Shared interrupt 201"] + #[inline(always)] + #[must_use] + pub fn spi201(&mut self) -> SPI201_W<9> { + SPI201_W::new(self) + } + #[doc = "Bit 10 - Shared interrupt 202"] + #[inline(always)] + #[must_use] + pub fn spi202(&mut self) -> SPI202_W<10> { + SPI202_W::new(self) + } + #[doc = "Bit 11 - Shared interrupt 203"] + #[inline(always)] + #[must_use] + pub fn spi203(&mut self) -> SPI203_W<11> { + SPI203_W::new(self) + } + #[doc = "Bit 12 - Shared interrupt 204"] + #[inline(always)] + #[must_use] + pub fn spi204(&mut self) -> SPI204_W<12> { + SPI204_W::new(self) + } + #[doc = "Bit 13 - Shared interrupt 205"] + #[inline(always)] + #[must_use] + pub fn spi205(&mut self) -> SPI205_W<13> { + SPI205_W::new(self) + } + #[doc = "Bit 14 - Shared interrupt 206"] + #[inline(always)] + #[must_use] + pub fn spi206(&mut self) -> SPI206_W<14> { + SPI206_W::new(self) + } + #[doc = "Bit 15 - Shared interrupt 207"] + #[inline(always)] + #[must_use] + pub fn spi207(&mut self) -> SPI207_W<15> { + SPI207_W::new(self) + } + #[doc = "Bit 16 - Shared interrupt 208"] + #[inline(always)] + #[must_use] + pub fn spi208(&mut self) -> SPI208_W<16> { + SPI208_W::new(self) + } + #[doc = "Bit 17 - Shared interrupt 209"] + #[inline(always)] + #[must_use] + pub fn spi209(&mut self) -> SPI209_W<17> { + SPI209_W::new(self) + } + #[doc = "Bit 18 - Shared interrupt 210"] + #[inline(always)] + #[must_use] + pub fn spi210(&mut self) -> SPI210_W<18> { + SPI210_W::new(self) + } + #[doc = "Bit 19 - Shared interrupt 211"] + #[inline(always)] + #[must_use] + pub fn spi211(&mut self) -> SPI211_W<19> { + SPI211_W::new(self) + } + #[doc = "Bit 20 - Shared interrupt 212"] + #[inline(always)] + #[must_use] + pub fn spi212(&mut self) -> SPI212_W<20> { + SPI212_W::new(self) + } + #[doc = "Bit 21 - Shared interrupt 213"] + #[inline(always)] + #[must_use] + pub fn spi213(&mut self) -> SPI213_W<21> { + SPI213_W::new(self) + } + #[doc = "Bit 22 - Shared interrupt 214"] + #[inline(always)] + #[must_use] + pub fn spi214(&mut self) -> SPI214_W<22> { + SPI214_W::new(self) + } + #[doc = "Bit 23 - Shared interrupt 215"] + #[inline(always)] + #[must_use] + pub fn spi215(&mut self) -> SPI215_W<23> { + SPI215_W::new(self) + } + #[doc = "Bit 24 - Shared interrupt 216"] + #[inline(always)] + #[must_use] + pub fn spi216(&mut self) -> SPI216_W<24> { + SPI216_W::new(self) + } + #[doc = "Bit 25 - Shared interrupt 217"] + #[inline(always)] + #[must_use] + pub fn spi217(&mut self) -> SPI217_W<25> { + SPI217_W::new(self) + } + #[doc = "Bit 26 - Shared interrupt 218"] + #[inline(always)] + #[must_use] + pub fn spi218(&mut self) -> SPI218_W<26> { + SPI218_W::new(self) + } + #[doc = "Bit 27 - Shared interrupt 219"] + #[inline(always)] + #[must_use] + pub fn spi219(&mut self) -> SPI219_W<27> { + SPI219_W::new(self) + } + #[doc = "Bit 28 - Shared interrupt 220"] + #[inline(always)] + #[must_use] + pub fn spi220(&mut self) -> SPI220_W<28> { + SPI220_W::new(self) + } + #[doc = "Bit 29 - Shared interrupt 221"] + #[inline(always)] + #[must_use] + pub fn spi221(&mut self) -> SPI221_W<29> { + SPI221_W::new(self) + } + #[doc = "Bit 30 - Shared interrupt 222"] + #[inline(always)] + #[must_use] + pub fn spi222(&mut self) -> SPI222_W<30> { + SPI222_W::new(self) + } + #[doc = "Bit 31 - Shared interrupt 223"] + #[inline(always)] + #[must_use] + pub fn spi223(&mut self) -> SPI223_W<31> { + SPI223_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr5](index.html) module"] +pub struct GICD_SPISR5_SPEC; +impl crate::RegisterSpec for GICD_SPISR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_spisr5::R](R) reader structure"] +impl crate::Readable for GICD_SPISR5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gicd_spisr5::W](W) writer structure"] +impl crate::Writable for GICD_SPISR5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GICD_SPISR5 to value 0"] +impl crate::Resettable for GICD_SPISR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs new file mode 100644 index 0000000..6e6c6c3 --- /dev/null +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GICD_TYPER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IT_LINES_NUMBER` reader - Interrupt line number"] +pub type IT_LINES_NUMBER_R = crate::FieldReader; +#[doc = "Field `CPU_NUMBER` reader - CPU number"] +pub type CPU_NUMBER_R = crate::FieldReader; +#[doc = "Field `SECURITY_EXTENSION` reader - Security extension implemented"] +pub type SECURITY_EXTENSION_R = crate::BitReader; +#[doc = "Field `LSPI` reader - Lockable SPI count"] +pub type LSPI_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Interrupt line number"] + #[inline(always)] + pub fn it_lines_number(&self) -> IT_LINES_NUMBER_R { + IT_LINES_NUMBER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:7 - CPU number"] + #[inline(always)] + pub fn cpu_number(&self) -> CPU_NUMBER_R { + CPU_NUMBER_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 10 - Security extension implemented"] + #[inline(always)] + pub fn security_extension(&self) -> SECURITY_EXTENSION_R { + SECURITY_EXTENSION_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:14 - Lockable SPI count"] + #[inline(always)] + pub fn lspi(&self) -> LSPI_R { + LSPI_R::new(((self.bits >> 11) & 0x0f) as u8) + } +} +#[doc = "Interrupt Controller Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_typer](index.html) module"] +pub struct GICD_TYPER_SPEC; +impl crate::RegisterSpec for GICD_TYPER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gicd_typer::R](R) reader structure"] +impl crate::Readable for GICD_TYPER_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GICD_TYPER to value 0"] +impl crate::Resettable for GICD_TYPER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio.rs b/crates/bcm2711-lpa/src/gpio.rs new file mode 100644 index 0000000..e643036 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio.rs @@ -0,0 +1,206 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - GPIO Function Select 0"] + pub gpfsel0: GPFSEL0, + #[doc = "0x04 - GPIO Function Select 1"] + pub gpfsel1: GPFSEL1, + #[doc = "0x08 - GPIO Function Select 2"] + pub gpfsel2: GPFSEL2, + #[doc = "0x0c - GPIO Function Select 3"] + pub gpfsel3: GPFSEL3, + #[doc = "0x10 - GPIO Function Select 4"] + pub gpfsel4: GPFSEL4, + #[doc = "0x14 - GPIO Function Select 5"] + pub gpfsel5: GPFSEL5, + _reserved6: [u8; 0x04], + #[doc = "0x1c - GPIO Pin Output Set 0"] + pub gpset0: GPSET0, + #[doc = "0x20 - GPIO Pin Output Set 1"] + pub gpset1: GPSET1, + _reserved8: [u8; 0x04], + #[doc = "0x28 - GPIO Pin Output Clear 0"] + pub gpclr0: GPCLR0, + #[doc = "0x2c - GPIO Pin Output Clear 1"] + pub gpclr1: GPCLR1, + _reserved10: [u8; 0x04], + #[doc = "0x34 - GPIO Pin Level 0"] + pub gplev0: GPLEV0, + #[doc = "0x38 - GPIO Pin Level 1"] + pub gplev1: GPLEV1, + _reserved12: [u8; 0x04], + #[doc = "0x40 - GPIO Pin Event Detect Status 0"] + pub gpeds0: GPEDS0, + #[doc = "0x44 - GPIO Pin Event Detect Status 1"] + pub gpeds1: GPEDS1, + _reserved14: [u8; 0x04], + #[doc = "0x4c - GPIO Pin Rising Edge Detect Enable 0"] + pub gpren0: GPREN0, + #[doc = "0x50 - GPIO Pin Rising Edge Detect Enable 1"] + pub gpren1: GPREN1, + _reserved16: [u8; 0x04], + #[doc = "0x58 - GPIO Pin Falling Edge Detect Enable 0"] + pub gpfen0: GPFEN0, + #[doc = "0x5c - GPIO Pin Falling Edge Detect Enable 1"] + pub gpfen1: GPFEN1, + _reserved18: [u8; 0x04], + #[doc = "0x64 - GPIO Pin High Detect Enable 0"] + pub gphen0: GPHEN0, + #[doc = "0x68 - GPIO Pin High Detect Enable 1"] + pub gphen1: GPHEN1, + _reserved20: [u8; 0x04], + #[doc = "0x70 - GPIO Pin Low Detect Enable 0"] + pub gplen0: GPLEN0, + #[doc = "0x74 - GPIO Pin Low Detect Enable 1"] + pub gplen1: GPLEN1, + _reserved22: [u8; 0x04], + #[doc = "0x7c - GPIO Pin Async. Rising Edge Detect 0"] + pub gparen0: GPAREN0, + #[doc = "0x80 - GPIO Pin Async. Rising Edge Detect 1"] + pub gparen1: GPAREN1, + _reserved24: [u8; 0x04], + #[doc = "0x88 - GPIO Pin Async. Falling Edge Detect 0"] + pub gpafen0: GPAFEN0, + #[doc = "0x8c - GPIO Pin Async. Falling Edge Detect 1"] + pub gpafen1: GPAFEN1, + _reserved26: [u8; 0x40], + #[doc = "0xd0 - Undocumented multiplexing bits"] + pub extra_mux: EXTRA_MUX, + _reserved27: [u8; 0x10], + #[doc = "0xe4 - GPIO Pull-up / Pull-down Register 0"] + pub gpio_pup_pdn_cntrl_reg0: GPIO_PUP_PDN_CNTRL_REG0, + #[doc = "0xe8 - GPIO Pull-up / Pull-down Register 1"] + pub gpio_pup_pdn_cntrl_reg1: GPIO_PUP_PDN_CNTRL_REG1, + #[doc = "0xec - GPIO Pull-up / Pull-down Register 2"] + pub gpio_pup_pdn_cntrl_reg2: GPIO_PUP_PDN_CNTRL_REG2, + #[doc = "0xf0 - GPIO Pull-up / Pull-down Register 3"] + pub gpio_pup_pdn_cntrl_reg3: GPIO_PUP_PDN_CNTRL_REG3, +} +#[doc = "GPFSEL0 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL0 = crate::Reg; +#[doc = "GPIO Function Select 0"] +pub mod gpfsel0; +#[doc = "GPFSEL1 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL1 = crate::Reg; +#[doc = "GPIO Function Select 1"] +pub mod gpfsel1; +#[doc = "GPFSEL2 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL2 = crate::Reg; +#[doc = "GPIO Function Select 2"] +pub mod gpfsel2; +#[doc = "GPFSEL3 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL3 = crate::Reg; +#[doc = "GPIO Function Select 3"] +pub mod gpfsel3; +#[doc = "GPFSEL4 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL4 = crate::Reg; +#[doc = "GPIO Function Select 4"] +pub mod gpfsel4; +#[doc = "GPFSEL5 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL5 = crate::Reg; +#[doc = "GPIO Function Select 5"] +pub mod gpfsel5; +#[doc = "GPSET0 (w) register accessor: an alias for `Reg`"] +pub type GPSET0 = crate::Reg; +#[doc = "GPIO Pin Output Set 0"] +pub mod gpset0; +#[doc = "GPSET1 (w) register accessor: an alias for `Reg`"] +pub type GPSET1 = crate::Reg; +#[doc = "GPIO Pin Output Set 1"] +pub mod gpset1; +#[doc = "GPCLR0 (w) register accessor: an alias for `Reg`"] +pub type GPCLR0 = crate::Reg; +#[doc = "GPIO Pin Output Clear 0"] +pub mod gpclr0; +#[doc = "GPCLR1 (w) register accessor: an alias for `Reg`"] +pub type GPCLR1 = crate::Reg; +#[doc = "GPIO Pin Output Clear 1"] +pub mod gpclr1; +#[doc = "GPLEV0 (r) register accessor: an alias for `Reg`"] +pub type GPLEV0 = crate::Reg; +#[doc = "GPIO Pin Level 0"] +pub mod gplev0; +#[doc = "GPLEV1 (r) register accessor: an alias for `Reg`"] +pub type GPLEV1 = crate::Reg; +#[doc = "GPIO Pin Level 1"] +pub mod gplev1; +#[doc = "GPEDS0 (rw) register accessor: an alias for `Reg`"] +pub type GPEDS0 = crate::Reg; +#[doc = "GPIO Pin Event Detect Status 0"] +pub mod gpeds0; +#[doc = "GPEDS1 (rw) register accessor: an alias for `Reg`"] +pub type GPEDS1 = crate::Reg; +#[doc = "GPIO Pin Event Detect Status 1"] +pub mod gpeds1; +#[doc = "GPREN0 (rw) register accessor: an alias for `Reg`"] +pub type GPREN0 = crate::Reg; +#[doc = "GPIO Pin Rising Edge Detect Enable 0"] +pub mod gpren0; +#[doc = "GPREN1 (rw) register accessor: an alias for `Reg`"] +pub type GPREN1 = crate::Reg; +#[doc = "GPIO Pin Rising Edge Detect Enable 1"] +pub mod gpren1; +#[doc = "GPFEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPFEN0 = crate::Reg; +#[doc = "GPIO Pin Falling Edge Detect Enable 0"] +pub mod gpfen0; +#[doc = "GPFEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPFEN1 = crate::Reg; +#[doc = "GPIO Pin Falling Edge Detect Enable 1"] +pub mod gpfen1; +#[doc = "GPHEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPHEN0 = crate::Reg; +#[doc = "GPIO Pin High Detect Enable 0"] +pub mod gphen0; +#[doc = "GPHEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPHEN1 = crate::Reg; +#[doc = "GPIO Pin High Detect Enable 1"] +pub mod gphen1; +#[doc = "GPLEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPLEN0 = crate::Reg; +#[doc = "GPIO Pin Low Detect Enable 0"] +pub mod gplen0; +#[doc = "GPLEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPLEN1 = crate::Reg; +#[doc = "GPIO Pin Low Detect Enable 1"] +pub mod gplen1; +#[doc = "GPAREN0 (rw) register accessor: an alias for `Reg`"] +pub type GPAREN0 = crate::Reg; +#[doc = "GPIO Pin Async. Rising Edge Detect 0"] +pub mod gparen0; +#[doc = "GPAREN1 (rw) register accessor: an alias for `Reg`"] +pub type GPAREN1 = crate::Reg; +#[doc = "GPIO Pin Async. Rising Edge Detect 1"] +pub mod gparen1; +#[doc = "GPAFEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPAFEN0 = crate::Reg; +#[doc = "GPIO Pin Async. Falling Edge Detect 0"] +pub mod gpafen0; +#[doc = "GPAFEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPAFEN1 = crate::Reg; +#[doc = "GPIO Pin Async. Falling Edge Detect 1"] +pub mod gpafen1; +#[doc = "EXTRA_MUX (rw) register accessor: an alias for `Reg`"] +pub type EXTRA_MUX = crate::Reg; +#[doc = "Undocumented multiplexing bits"] +pub mod extra_mux; +#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG0 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 0"] +pub mod gpio_pup_pdn_cntrl_reg0; +#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG1 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 1"] +pub mod gpio_pup_pdn_cntrl_reg1; +#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG2 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 2"] +pub mod gpio_pup_pdn_cntrl_reg2; +#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG3 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 3"] +pub mod gpio_pup_pdn_cntrl_reg3; diff --git a/crates/bcm2711-lpa/src/gpio/extra_mux.rs b/crates/bcm2711-lpa/src/gpio/extra_mux.rs new file mode 100644 index 0000000..a35ba4f --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/extra_mux.rs @@ -0,0 +1,122 @@ +#[doc = "Register `EXTRA_MUX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTRA_MUX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDIO` reader - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +pub type SDIO_R = crate::BitReader; +#[doc = "Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SDIO_A { + #[doc = "0: Connect the newer SD host"] + SDHOST = 0, + #[doc = "1: Connect Arasan SD/EMMC host"] + ARASAN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SDIO_A) -> Self { + variant as u8 != 0 + } +} +impl SDIO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDIO_A { + match self.bits { + false => SDIO_A::SDHOST, + true => SDIO_A::ARASAN, + } + } + #[doc = "Checks if the value of the field is `SDHOST`"] + #[inline(always)] + pub fn is_sdhost(&self) -> bool { + *self == SDIO_A::SDHOST + } + #[doc = "Checks if the value of the field is `ARASAN`"] + #[inline(always)] + pub fn is_arasan(&self) -> bool { + *self == SDIO_A::ARASAN + } +} +#[doc = "Field `SDIO` writer - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +pub type SDIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTRA_MUX_SPEC, SDIO_A, O>; +impl<'a, const O: u8> SDIO_W<'a, O> { + #[doc = "Connect the newer SD host"] + #[inline(always)] + pub fn sdhost(self) -> &'a mut W { + self.variant(SDIO_A::SDHOST) + } + #[doc = "Connect Arasan SD/EMMC host"] + #[inline(always)] + pub fn arasan(self) -> &'a mut W { + self.variant(SDIO_A::ARASAN) + } +} +impl R { + #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] + #[inline(always)] + pub fn sdio(&self) -> SDIO_R { + SDIO_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] + #[inline(always)] + #[must_use] + pub fn sdio(&mut self) -> SDIO_W<1> { + SDIO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Undocumented multiplexing bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extra_mux](index.html) module"] +pub struct EXTRA_MUX_SPEC; +impl crate::RegisterSpec for EXTRA_MUX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [extra_mux::R](R) reader structure"] +impl crate::Readable for EXTRA_MUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extra_mux::W](W) writer structure"] +impl crate::Writable for EXTRA_MUX_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpafen0.rs b/crates/bcm2711-lpa/src/gpio/gpafen0.rs new file mode 100644 index 0000000..5c84fd8 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpafen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPAFEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAFEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AFEN0` reader - Async falling enabled 0"] +pub type AFEN0_R = crate::BitReader; +#[doc = "Field `AFEN0` writer - Async falling enabled 0"] +pub type AFEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN1` reader - Async falling enabled 1"] +pub type AFEN1_R = crate::BitReader; +#[doc = "Field `AFEN1` writer - Async falling enabled 1"] +pub type AFEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN2` reader - Async falling enabled 2"] +pub type AFEN2_R = crate::BitReader; +#[doc = "Field `AFEN2` writer - Async falling enabled 2"] +pub type AFEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN3` reader - Async falling enabled 3"] +pub type AFEN3_R = crate::BitReader; +#[doc = "Field `AFEN3` writer - Async falling enabled 3"] +pub type AFEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN4` reader - Async falling enabled 4"] +pub type AFEN4_R = crate::BitReader; +#[doc = "Field `AFEN4` writer - Async falling enabled 4"] +pub type AFEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN5` reader - Async falling enabled 5"] +pub type AFEN5_R = crate::BitReader; +#[doc = "Field `AFEN5` writer - Async falling enabled 5"] +pub type AFEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN6` reader - Async falling enabled 6"] +pub type AFEN6_R = crate::BitReader; +#[doc = "Field `AFEN6` writer - Async falling enabled 6"] +pub type AFEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN7` reader - Async falling enabled 7"] +pub type AFEN7_R = crate::BitReader; +#[doc = "Field `AFEN7` writer - Async falling enabled 7"] +pub type AFEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN8` reader - Async falling enabled 8"] +pub type AFEN8_R = crate::BitReader; +#[doc = "Field `AFEN8` writer - Async falling enabled 8"] +pub type AFEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN9` reader - Async falling enabled 9"] +pub type AFEN9_R = crate::BitReader; +#[doc = "Field `AFEN9` writer - Async falling enabled 9"] +pub type AFEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN10` reader - Async falling enabled 10"] +pub type AFEN10_R = crate::BitReader; +#[doc = "Field `AFEN10` writer - Async falling enabled 10"] +pub type AFEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN11` reader - Async falling enabled 11"] +pub type AFEN11_R = crate::BitReader; +#[doc = "Field `AFEN11` writer - Async falling enabled 11"] +pub type AFEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN12` reader - Async falling enabled 12"] +pub type AFEN12_R = crate::BitReader; +#[doc = "Field `AFEN12` writer - Async falling enabled 12"] +pub type AFEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN13` reader - Async falling enabled 13"] +pub type AFEN13_R = crate::BitReader; +#[doc = "Field `AFEN13` writer - Async falling enabled 13"] +pub type AFEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN14` reader - Async falling enabled 14"] +pub type AFEN14_R = crate::BitReader; +#[doc = "Field `AFEN14` writer - Async falling enabled 14"] +pub type AFEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN15` reader - Async falling enabled 15"] +pub type AFEN15_R = crate::BitReader; +#[doc = "Field `AFEN15` writer - Async falling enabled 15"] +pub type AFEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN16` reader - Async falling enabled 16"] +pub type AFEN16_R = crate::BitReader; +#[doc = "Field `AFEN16` writer - Async falling enabled 16"] +pub type AFEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN17` reader - Async falling enabled 17"] +pub type AFEN17_R = crate::BitReader; +#[doc = "Field `AFEN17` writer - Async falling enabled 17"] +pub type AFEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN18` reader - Async falling enabled 18"] +pub type AFEN18_R = crate::BitReader; +#[doc = "Field `AFEN18` writer - Async falling enabled 18"] +pub type AFEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN19` reader - Async falling enabled 19"] +pub type AFEN19_R = crate::BitReader; +#[doc = "Field `AFEN19` writer - Async falling enabled 19"] +pub type AFEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN20` reader - Async falling enabled 20"] +pub type AFEN20_R = crate::BitReader; +#[doc = "Field `AFEN20` writer - Async falling enabled 20"] +pub type AFEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN21` reader - Async falling enabled 21"] +pub type AFEN21_R = crate::BitReader; +#[doc = "Field `AFEN21` writer - Async falling enabled 21"] +pub type AFEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN22` reader - Async falling enabled 22"] +pub type AFEN22_R = crate::BitReader; +#[doc = "Field `AFEN22` writer - Async falling enabled 22"] +pub type AFEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN23` reader - Async falling enabled 23"] +pub type AFEN23_R = crate::BitReader; +#[doc = "Field `AFEN23` writer - Async falling enabled 23"] +pub type AFEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN24` reader - Async falling enabled 24"] +pub type AFEN24_R = crate::BitReader; +#[doc = "Field `AFEN24` writer - Async falling enabled 24"] +pub type AFEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN25` reader - Async falling enabled 25"] +pub type AFEN25_R = crate::BitReader; +#[doc = "Field `AFEN25` writer - Async falling enabled 25"] +pub type AFEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN26` reader - Async falling enabled 26"] +pub type AFEN26_R = crate::BitReader; +#[doc = "Field `AFEN26` writer - Async falling enabled 26"] +pub type AFEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN27` reader - Async falling enabled 27"] +pub type AFEN27_R = crate::BitReader; +#[doc = "Field `AFEN27` writer - Async falling enabled 27"] +pub type AFEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN28` reader - Async falling enabled 28"] +pub type AFEN28_R = crate::BitReader; +#[doc = "Field `AFEN28` writer - Async falling enabled 28"] +pub type AFEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN29` reader - Async falling enabled 29"] +pub type AFEN29_R = crate::BitReader; +#[doc = "Field `AFEN29` writer - Async falling enabled 29"] +pub type AFEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN30` reader - Async falling enabled 30"] +pub type AFEN30_R = crate::BitReader; +#[doc = "Field `AFEN30` writer - Async falling enabled 30"] +pub type AFEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN31` reader - Async falling enabled 31"] +pub type AFEN31_R = crate::BitReader; +#[doc = "Field `AFEN31` writer - Async falling enabled 31"] +pub type AFEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async falling enabled 0"] + #[inline(always)] + pub fn afen0(&self) -> AFEN0_R { + AFEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async falling enabled 1"] + #[inline(always)] + pub fn afen1(&self) -> AFEN1_R { + AFEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async falling enabled 2"] + #[inline(always)] + pub fn afen2(&self) -> AFEN2_R { + AFEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async falling enabled 3"] + #[inline(always)] + pub fn afen3(&self) -> AFEN3_R { + AFEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async falling enabled 4"] + #[inline(always)] + pub fn afen4(&self) -> AFEN4_R { + AFEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async falling enabled 5"] + #[inline(always)] + pub fn afen5(&self) -> AFEN5_R { + AFEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async falling enabled 6"] + #[inline(always)] + pub fn afen6(&self) -> AFEN6_R { + AFEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async falling enabled 7"] + #[inline(always)] + pub fn afen7(&self) -> AFEN7_R { + AFEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async falling enabled 8"] + #[inline(always)] + pub fn afen8(&self) -> AFEN8_R { + AFEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async falling enabled 9"] + #[inline(always)] + pub fn afen9(&self) -> AFEN9_R { + AFEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async falling enabled 10"] + #[inline(always)] + pub fn afen10(&self) -> AFEN10_R { + AFEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async falling enabled 11"] + #[inline(always)] + pub fn afen11(&self) -> AFEN11_R { + AFEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async falling enabled 12"] + #[inline(always)] + pub fn afen12(&self) -> AFEN12_R { + AFEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async falling enabled 13"] + #[inline(always)] + pub fn afen13(&self) -> AFEN13_R { + AFEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async falling enabled 14"] + #[inline(always)] + pub fn afen14(&self) -> AFEN14_R { + AFEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async falling enabled 15"] + #[inline(always)] + pub fn afen15(&self) -> AFEN15_R { + AFEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async falling enabled 16"] + #[inline(always)] + pub fn afen16(&self) -> AFEN16_R { + AFEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async falling enabled 17"] + #[inline(always)] + pub fn afen17(&self) -> AFEN17_R { + AFEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async falling enabled 18"] + #[inline(always)] + pub fn afen18(&self) -> AFEN18_R { + AFEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async falling enabled 19"] + #[inline(always)] + pub fn afen19(&self) -> AFEN19_R { + AFEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async falling enabled 20"] + #[inline(always)] + pub fn afen20(&self) -> AFEN20_R { + AFEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async falling enabled 21"] + #[inline(always)] + pub fn afen21(&self) -> AFEN21_R { + AFEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async falling enabled 22"] + #[inline(always)] + pub fn afen22(&self) -> AFEN22_R { + AFEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async falling enabled 23"] + #[inline(always)] + pub fn afen23(&self) -> AFEN23_R { + AFEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async falling enabled 24"] + #[inline(always)] + pub fn afen24(&self) -> AFEN24_R { + AFEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async falling enabled 25"] + #[inline(always)] + pub fn afen25(&self) -> AFEN25_R { + AFEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Async falling enabled 26"] + #[inline(always)] + pub fn afen26(&self) -> AFEN26_R { + AFEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Async falling enabled 27"] + #[inline(always)] + pub fn afen27(&self) -> AFEN27_R { + AFEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Async falling enabled 28"] + #[inline(always)] + pub fn afen28(&self) -> AFEN28_R { + AFEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Async falling enabled 29"] + #[inline(always)] + pub fn afen29(&self) -> AFEN29_R { + AFEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Async falling enabled 30"] + #[inline(always)] + pub fn afen30(&self) -> AFEN30_R { + AFEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Async falling enabled 31"] + #[inline(always)] + pub fn afen31(&self) -> AFEN31_R { + AFEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async falling enabled 0"] + #[inline(always)] + #[must_use] + pub fn afen0(&mut self) -> AFEN0_W<0> { + AFEN0_W::new(self) + } + #[doc = "Bit 1 - Async falling enabled 1"] + #[inline(always)] + #[must_use] + pub fn afen1(&mut self) -> AFEN1_W<1> { + AFEN1_W::new(self) + } + #[doc = "Bit 2 - Async falling enabled 2"] + #[inline(always)] + #[must_use] + pub fn afen2(&mut self) -> AFEN2_W<2> { + AFEN2_W::new(self) + } + #[doc = "Bit 3 - Async falling enabled 3"] + #[inline(always)] + #[must_use] + pub fn afen3(&mut self) -> AFEN3_W<3> { + AFEN3_W::new(self) + } + #[doc = "Bit 4 - Async falling enabled 4"] + #[inline(always)] + #[must_use] + pub fn afen4(&mut self) -> AFEN4_W<4> { + AFEN4_W::new(self) + } + #[doc = "Bit 5 - Async falling enabled 5"] + #[inline(always)] + #[must_use] + pub fn afen5(&mut self) -> AFEN5_W<5> { + AFEN5_W::new(self) + } + #[doc = "Bit 6 - Async falling enabled 6"] + #[inline(always)] + #[must_use] + pub fn afen6(&mut self) -> AFEN6_W<6> { + AFEN6_W::new(self) + } + #[doc = "Bit 7 - Async falling enabled 7"] + #[inline(always)] + #[must_use] + pub fn afen7(&mut self) -> AFEN7_W<7> { + AFEN7_W::new(self) + } + #[doc = "Bit 8 - Async falling enabled 8"] + #[inline(always)] + #[must_use] + pub fn afen8(&mut self) -> AFEN8_W<8> { + AFEN8_W::new(self) + } + #[doc = "Bit 9 - Async falling enabled 9"] + #[inline(always)] + #[must_use] + pub fn afen9(&mut self) -> AFEN9_W<9> { + AFEN9_W::new(self) + } + #[doc = "Bit 10 - Async falling enabled 10"] + #[inline(always)] + #[must_use] + pub fn afen10(&mut self) -> AFEN10_W<10> { + AFEN10_W::new(self) + } + #[doc = "Bit 11 - Async falling enabled 11"] + #[inline(always)] + #[must_use] + pub fn afen11(&mut self) -> AFEN11_W<11> { + AFEN11_W::new(self) + } + #[doc = "Bit 12 - Async falling enabled 12"] + #[inline(always)] + #[must_use] + pub fn afen12(&mut self) -> AFEN12_W<12> { + AFEN12_W::new(self) + } + #[doc = "Bit 13 - Async falling enabled 13"] + #[inline(always)] + #[must_use] + pub fn afen13(&mut self) -> AFEN13_W<13> { + AFEN13_W::new(self) + } + #[doc = "Bit 14 - Async falling enabled 14"] + #[inline(always)] + #[must_use] + pub fn afen14(&mut self) -> AFEN14_W<14> { + AFEN14_W::new(self) + } + #[doc = "Bit 15 - Async falling enabled 15"] + #[inline(always)] + #[must_use] + pub fn afen15(&mut self) -> AFEN15_W<15> { + AFEN15_W::new(self) + } + #[doc = "Bit 16 - Async falling enabled 16"] + #[inline(always)] + #[must_use] + pub fn afen16(&mut self) -> AFEN16_W<16> { + AFEN16_W::new(self) + } + #[doc = "Bit 17 - Async falling enabled 17"] + #[inline(always)] + #[must_use] + pub fn afen17(&mut self) -> AFEN17_W<17> { + AFEN17_W::new(self) + } + #[doc = "Bit 18 - Async falling enabled 18"] + #[inline(always)] + #[must_use] + pub fn afen18(&mut self) -> AFEN18_W<18> { + AFEN18_W::new(self) + } + #[doc = "Bit 19 - Async falling enabled 19"] + #[inline(always)] + #[must_use] + pub fn afen19(&mut self) -> AFEN19_W<19> { + AFEN19_W::new(self) + } + #[doc = "Bit 20 - Async falling enabled 20"] + #[inline(always)] + #[must_use] + pub fn afen20(&mut self) -> AFEN20_W<20> { + AFEN20_W::new(self) + } + #[doc = "Bit 21 - Async falling enabled 21"] + #[inline(always)] + #[must_use] + pub fn afen21(&mut self) -> AFEN21_W<21> { + AFEN21_W::new(self) + } + #[doc = "Bit 22 - Async falling enabled 22"] + #[inline(always)] + #[must_use] + pub fn afen22(&mut self) -> AFEN22_W<22> { + AFEN22_W::new(self) + } + #[doc = "Bit 23 - Async falling enabled 23"] + #[inline(always)] + #[must_use] + pub fn afen23(&mut self) -> AFEN23_W<23> { + AFEN23_W::new(self) + } + #[doc = "Bit 24 - Async falling enabled 24"] + #[inline(always)] + #[must_use] + pub fn afen24(&mut self) -> AFEN24_W<24> { + AFEN24_W::new(self) + } + #[doc = "Bit 25 - Async falling enabled 25"] + #[inline(always)] + #[must_use] + pub fn afen25(&mut self) -> AFEN25_W<25> { + AFEN25_W::new(self) + } + #[doc = "Bit 26 - Async falling enabled 26"] + #[inline(always)] + #[must_use] + pub fn afen26(&mut self) -> AFEN26_W<26> { + AFEN26_W::new(self) + } + #[doc = "Bit 27 - Async falling enabled 27"] + #[inline(always)] + #[must_use] + pub fn afen27(&mut self) -> AFEN27_W<27> { + AFEN27_W::new(self) + } + #[doc = "Bit 28 - Async falling enabled 28"] + #[inline(always)] + #[must_use] + pub fn afen28(&mut self) -> AFEN28_W<28> { + AFEN28_W::new(self) + } + #[doc = "Bit 29 - Async falling enabled 29"] + #[inline(always)] + #[must_use] + pub fn afen29(&mut self) -> AFEN29_W<29> { + AFEN29_W::new(self) + } + #[doc = "Bit 30 - Async falling enabled 30"] + #[inline(always)] + #[must_use] + pub fn afen30(&mut self) -> AFEN30_W<30> { + AFEN30_W::new(self) + } + #[doc = "Bit 31 - Async falling enabled 31"] + #[inline(always)] + #[must_use] + pub fn afen31(&mut self) -> AFEN31_W<31> { + AFEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen0](index.html) module"] +pub struct GPAFEN0_SPEC; +impl crate::RegisterSpec for GPAFEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpafen0::R](R) reader structure"] +impl crate::Readable for GPAFEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpafen0::W](W) writer structure"] +impl crate::Writable for GPAFEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpafen1.rs b/crates/bcm2711-lpa/src/gpio/gpafen1.rs new file mode 100644 index 0000000..68f50fe --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpafen1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPAFEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAFEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AFEN32` reader - Async falling enabled 32"] +pub type AFEN32_R = crate::BitReader; +#[doc = "Field `AFEN32` writer - Async falling enabled 32"] +pub type AFEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN33` reader - Async falling enabled 33"] +pub type AFEN33_R = crate::BitReader; +#[doc = "Field `AFEN33` writer - Async falling enabled 33"] +pub type AFEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN34` reader - Async falling enabled 34"] +pub type AFEN34_R = crate::BitReader; +#[doc = "Field `AFEN34` writer - Async falling enabled 34"] +pub type AFEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN35` reader - Async falling enabled 35"] +pub type AFEN35_R = crate::BitReader; +#[doc = "Field `AFEN35` writer - Async falling enabled 35"] +pub type AFEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN36` reader - Async falling enabled 36"] +pub type AFEN36_R = crate::BitReader; +#[doc = "Field `AFEN36` writer - Async falling enabled 36"] +pub type AFEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN37` reader - Async falling enabled 37"] +pub type AFEN37_R = crate::BitReader; +#[doc = "Field `AFEN37` writer - Async falling enabled 37"] +pub type AFEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN38` reader - Async falling enabled 38"] +pub type AFEN38_R = crate::BitReader; +#[doc = "Field `AFEN38` writer - Async falling enabled 38"] +pub type AFEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN39` reader - Async falling enabled 39"] +pub type AFEN39_R = crate::BitReader; +#[doc = "Field `AFEN39` writer - Async falling enabled 39"] +pub type AFEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN40` reader - Async falling enabled 40"] +pub type AFEN40_R = crate::BitReader; +#[doc = "Field `AFEN40` writer - Async falling enabled 40"] +pub type AFEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN41` reader - Async falling enabled 41"] +pub type AFEN41_R = crate::BitReader; +#[doc = "Field `AFEN41` writer - Async falling enabled 41"] +pub type AFEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN42` reader - Async falling enabled 42"] +pub type AFEN42_R = crate::BitReader; +#[doc = "Field `AFEN42` writer - Async falling enabled 42"] +pub type AFEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN43` reader - Async falling enabled 43"] +pub type AFEN43_R = crate::BitReader; +#[doc = "Field `AFEN43` writer - Async falling enabled 43"] +pub type AFEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN44` reader - Async falling enabled 44"] +pub type AFEN44_R = crate::BitReader; +#[doc = "Field `AFEN44` writer - Async falling enabled 44"] +pub type AFEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN45` reader - Async falling enabled 45"] +pub type AFEN45_R = crate::BitReader; +#[doc = "Field `AFEN45` writer - Async falling enabled 45"] +pub type AFEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN46` reader - Async falling enabled 46"] +pub type AFEN46_R = crate::BitReader; +#[doc = "Field `AFEN46` writer - Async falling enabled 46"] +pub type AFEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN47` reader - Async falling enabled 47"] +pub type AFEN47_R = crate::BitReader; +#[doc = "Field `AFEN47` writer - Async falling enabled 47"] +pub type AFEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN48` reader - Async falling enabled 48"] +pub type AFEN48_R = crate::BitReader; +#[doc = "Field `AFEN48` writer - Async falling enabled 48"] +pub type AFEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN49` reader - Async falling enabled 49"] +pub type AFEN49_R = crate::BitReader; +#[doc = "Field `AFEN49` writer - Async falling enabled 49"] +pub type AFEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN50` reader - Async falling enabled 50"] +pub type AFEN50_R = crate::BitReader; +#[doc = "Field `AFEN50` writer - Async falling enabled 50"] +pub type AFEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN51` reader - Async falling enabled 51"] +pub type AFEN51_R = crate::BitReader; +#[doc = "Field `AFEN51` writer - Async falling enabled 51"] +pub type AFEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN52` reader - Async falling enabled 52"] +pub type AFEN52_R = crate::BitReader; +#[doc = "Field `AFEN52` writer - Async falling enabled 52"] +pub type AFEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN53` reader - Async falling enabled 53"] +pub type AFEN53_R = crate::BitReader; +#[doc = "Field `AFEN53` writer - Async falling enabled 53"] +pub type AFEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN54` reader - Async falling enabled 54"] +pub type AFEN54_R = crate::BitReader; +#[doc = "Field `AFEN54` writer - Async falling enabled 54"] +pub type AFEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN55` reader - Async falling enabled 55"] +pub type AFEN55_R = crate::BitReader; +#[doc = "Field `AFEN55` writer - Async falling enabled 55"] +pub type AFEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN56` reader - Async falling enabled 56"] +pub type AFEN56_R = crate::BitReader; +#[doc = "Field `AFEN56` writer - Async falling enabled 56"] +pub type AFEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN57` reader - Async falling enabled 57"] +pub type AFEN57_R = crate::BitReader; +#[doc = "Field `AFEN57` writer - Async falling enabled 57"] +pub type AFEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async falling enabled 32"] + #[inline(always)] + pub fn afen32(&self) -> AFEN32_R { + AFEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async falling enabled 33"] + #[inline(always)] + pub fn afen33(&self) -> AFEN33_R { + AFEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async falling enabled 34"] + #[inline(always)] + pub fn afen34(&self) -> AFEN34_R { + AFEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async falling enabled 35"] + #[inline(always)] + pub fn afen35(&self) -> AFEN35_R { + AFEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async falling enabled 36"] + #[inline(always)] + pub fn afen36(&self) -> AFEN36_R { + AFEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async falling enabled 37"] + #[inline(always)] + pub fn afen37(&self) -> AFEN37_R { + AFEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async falling enabled 38"] + #[inline(always)] + pub fn afen38(&self) -> AFEN38_R { + AFEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async falling enabled 39"] + #[inline(always)] + pub fn afen39(&self) -> AFEN39_R { + AFEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async falling enabled 40"] + #[inline(always)] + pub fn afen40(&self) -> AFEN40_R { + AFEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async falling enabled 41"] + #[inline(always)] + pub fn afen41(&self) -> AFEN41_R { + AFEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async falling enabled 42"] + #[inline(always)] + pub fn afen42(&self) -> AFEN42_R { + AFEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async falling enabled 43"] + #[inline(always)] + pub fn afen43(&self) -> AFEN43_R { + AFEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async falling enabled 44"] + #[inline(always)] + pub fn afen44(&self) -> AFEN44_R { + AFEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async falling enabled 45"] + #[inline(always)] + pub fn afen45(&self) -> AFEN45_R { + AFEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async falling enabled 46"] + #[inline(always)] + pub fn afen46(&self) -> AFEN46_R { + AFEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async falling enabled 47"] + #[inline(always)] + pub fn afen47(&self) -> AFEN47_R { + AFEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async falling enabled 48"] + #[inline(always)] + pub fn afen48(&self) -> AFEN48_R { + AFEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async falling enabled 49"] + #[inline(always)] + pub fn afen49(&self) -> AFEN49_R { + AFEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async falling enabled 50"] + #[inline(always)] + pub fn afen50(&self) -> AFEN50_R { + AFEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async falling enabled 51"] + #[inline(always)] + pub fn afen51(&self) -> AFEN51_R { + AFEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async falling enabled 52"] + #[inline(always)] + pub fn afen52(&self) -> AFEN52_R { + AFEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async falling enabled 53"] + #[inline(always)] + pub fn afen53(&self) -> AFEN53_R { + AFEN53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async falling enabled 54"] + #[inline(always)] + pub fn afen54(&self) -> AFEN54_R { + AFEN54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async falling enabled 55"] + #[inline(always)] + pub fn afen55(&self) -> AFEN55_R { + AFEN55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async falling enabled 56"] + #[inline(always)] + pub fn afen56(&self) -> AFEN56_R { + AFEN56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async falling enabled 57"] + #[inline(always)] + pub fn afen57(&self) -> AFEN57_R { + AFEN57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async falling enabled 32"] + #[inline(always)] + #[must_use] + pub fn afen32(&mut self) -> AFEN32_W<0> { + AFEN32_W::new(self) + } + #[doc = "Bit 1 - Async falling enabled 33"] + #[inline(always)] + #[must_use] + pub fn afen33(&mut self) -> AFEN33_W<1> { + AFEN33_W::new(self) + } + #[doc = "Bit 2 - Async falling enabled 34"] + #[inline(always)] + #[must_use] + pub fn afen34(&mut self) -> AFEN34_W<2> { + AFEN34_W::new(self) + } + #[doc = "Bit 3 - Async falling enabled 35"] + #[inline(always)] + #[must_use] + pub fn afen35(&mut self) -> AFEN35_W<3> { + AFEN35_W::new(self) + } + #[doc = "Bit 4 - Async falling enabled 36"] + #[inline(always)] + #[must_use] + pub fn afen36(&mut self) -> AFEN36_W<4> { + AFEN36_W::new(self) + } + #[doc = "Bit 5 - Async falling enabled 37"] + #[inline(always)] + #[must_use] + pub fn afen37(&mut self) -> AFEN37_W<5> { + AFEN37_W::new(self) + } + #[doc = "Bit 6 - Async falling enabled 38"] + #[inline(always)] + #[must_use] + pub fn afen38(&mut self) -> AFEN38_W<6> { + AFEN38_W::new(self) + } + #[doc = "Bit 7 - Async falling enabled 39"] + #[inline(always)] + #[must_use] + pub fn afen39(&mut self) -> AFEN39_W<7> { + AFEN39_W::new(self) + } + #[doc = "Bit 8 - Async falling enabled 40"] + #[inline(always)] + #[must_use] + pub fn afen40(&mut self) -> AFEN40_W<8> { + AFEN40_W::new(self) + } + #[doc = "Bit 9 - Async falling enabled 41"] + #[inline(always)] + #[must_use] + pub fn afen41(&mut self) -> AFEN41_W<9> { + AFEN41_W::new(self) + } + #[doc = "Bit 10 - Async falling enabled 42"] + #[inline(always)] + #[must_use] + pub fn afen42(&mut self) -> AFEN42_W<10> { + AFEN42_W::new(self) + } + #[doc = "Bit 11 - Async falling enabled 43"] + #[inline(always)] + #[must_use] + pub fn afen43(&mut self) -> AFEN43_W<11> { + AFEN43_W::new(self) + } + #[doc = "Bit 12 - Async falling enabled 44"] + #[inline(always)] + #[must_use] + pub fn afen44(&mut self) -> AFEN44_W<12> { + AFEN44_W::new(self) + } + #[doc = "Bit 13 - Async falling enabled 45"] + #[inline(always)] + #[must_use] + pub fn afen45(&mut self) -> AFEN45_W<13> { + AFEN45_W::new(self) + } + #[doc = "Bit 14 - Async falling enabled 46"] + #[inline(always)] + #[must_use] + pub fn afen46(&mut self) -> AFEN46_W<14> { + AFEN46_W::new(self) + } + #[doc = "Bit 15 - Async falling enabled 47"] + #[inline(always)] + #[must_use] + pub fn afen47(&mut self) -> AFEN47_W<15> { + AFEN47_W::new(self) + } + #[doc = "Bit 16 - Async falling enabled 48"] + #[inline(always)] + #[must_use] + pub fn afen48(&mut self) -> AFEN48_W<16> { + AFEN48_W::new(self) + } + #[doc = "Bit 17 - Async falling enabled 49"] + #[inline(always)] + #[must_use] + pub fn afen49(&mut self) -> AFEN49_W<17> { + AFEN49_W::new(self) + } + #[doc = "Bit 18 - Async falling enabled 50"] + #[inline(always)] + #[must_use] + pub fn afen50(&mut self) -> AFEN50_W<18> { + AFEN50_W::new(self) + } + #[doc = "Bit 19 - Async falling enabled 51"] + #[inline(always)] + #[must_use] + pub fn afen51(&mut self) -> AFEN51_W<19> { + AFEN51_W::new(self) + } + #[doc = "Bit 20 - Async falling enabled 52"] + #[inline(always)] + #[must_use] + pub fn afen52(&mut self) -> AFEN52_W<20> { + AFEN52_W::new(self) + } + #[doc = "Bit 21 - Async falling enabled 53"] + #[inline(always)] + #[must_use] + pub fn afen53(&mut self) -> AFEN53_W<21> { + AFEN53_W::new(self) + } + #[doc = "Bit 22 - Async falling enabled 54"] + #[inline(always)] + #[must_use] + pub fn afen54(&mut self) -> AFEN54_W<22> { + AFEN54_W::new(self) + } + #[doc = "Bit 23 - Async falling enabled 55"] + #[inline(always)] + #[must_use] + pub fn afen55(&mut self) -> AFEN55_W<23> { + AFEN55_W::new(self) + } + #[doc = "Bit 24 - Async falling enabled 56"] + #[inline(always)] + #[must_use] + pub fn afen56(&mut self) -> AFEN56_W<24> { + AFEN56_W::new(self) + } + #[doc = "Bit 25 - Async falling enabled 57"] + #[inline(always)] + #[must_use] + pub fn afen57(&mut self) -> AFEN57_W<25> { + AFEN57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen1](index.html) module"] +pub struct GPAFEN1_SPEC; +impl crate::RegisterSpec for GPAFEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpafen1::R](R) reader structure"] +impl crate::Readable for GPAFEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpafen1::W](W) writer structure"] +impl crate::Writable for GPAFEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gparen0.rs b/crates/bcm2711-lpa/src/gpio/gparen0.rs new file mode 100644 index 0000000..f4ef746 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gparen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPAREN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAREN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AREN0` reader - Async rising enabled 0"] +pub type AREN0_R = crate::BitReader; +#[doc = "Field `AREN0` writer - Async rising enabled 0"] +pub type AREN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN1` reader - Async rising enabled 1"] +pub type AREN1_R = crate::BitReader; +#[doc = "Field `AREN1` writer - Async rising enabled 1"] +pub type AREN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN2` reader - Async rising enabled 2"] +pub type AREN2_R = crate::BitReader; +#[doc = "Field `AREN2` writer - Async rising enabled 2"] +pub type AREN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN3` reader - Async rising enabled 3"] +pub type AREN3_R = crate::BitReader; +#[doc = "Field `AREN3` writer - Async rising enabled 3"] +pub type AREN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN4` reader - Async rising enabled 4"] +pub type AREN4_R = crate::BitReader; +#[doc = "Field `AREN4` writer - Async rising enabled 4"] +pub type AREN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN5` reader - Async rising enabled 5"] +pub type AREN5_R = crate::BitReader; +#[doc = "Field `AREN5` writer - Async rising enabled 5"] +pub type AREN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN6` reader - Async rising enabled 6"] +pub type AREN6_R = crate::BitReader; +#[doc = "Field `AREN6` writer - Async rising enabled 6"] +pub type AREN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN7` reader - Async rising enabled 7"] +pub type AREN7_R = crate::BitReader; +#[doc = "Field `AREN7` writer - Async rising enabled 7"] +pub type AREN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN8` reader - Async rising enabled 8"] +pub type AREN8_R = crate::BitReader; +#[doc = "Field `AREN8` writer - Async rising enabled 8"] +pub type AREN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN9` reader - Async rising enabled 9"] +pub type AREN9_R = crate::BitReader; +#[doc = "Field `AREN9` writer - Async rising enabled 9"] +pub type AREN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN10` reader - Async rising enabled 10"] +pub type AREN10_R = crate::BitReader; +#[doc = "Field `AREN10` writer - Async rising enabled 10"] +pub type AREN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN11` reader - Async rising enabled 11"] +pub type AREN11_R = crate::BitReader; +#[doc = "Field `AREN11` writer - Async rising enabled 11"] +pub type AREN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN12` reader - Async rising enabled 12"] +pub type AREN12_R = crate::BitReader; +#[doc = "Field `AREN12` writer - Async rising enabled 12"] +pub type AREN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN13` reader - Async rising enabled 13"] +pub type AREN13_R = crate::BitReader; +#[doc = "Field `AREN13` writer - Async rising enabled 13"] +pub type AREN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN14` reader - Async rising enabled 14"] +pub type AREN14_R = crate::BitReader; +#[doc = "Field `AREN14` writer - Async rising enabled 14"] +pub type AREN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN15` reader - Async rising enabled 15"] +pub type AREN15_R = crate::BitReader; +#[doc = "Field `AREN15` writer - Async rising enabled 15"] +pub type AREN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN16` reader - Async rising enabled 16"] +pub type AREN16_R = crate::BitReader; +#[doc = "Field `AREN16` writer - Async rising enabled 16"] +pub type AREN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN17` reader - Async rising enabled 17"] +pub type AREN17_R = crate::BitReader; +#[doc = "Field `AREN17` writer - Async rising enabled 17"] +pub type AREN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN18` reader - Async rising enabled 18"] +pub type AREN18_R = crate::BitReader; +#[doc = "Field `AREN18` writer - Async rising enabled 18"] +pub type AREN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN19` reader - Async rising enabled 19"] +pub type AREN19_R = crate::BitReader; +#[doc = "Field `AREN19` writer - Async rising enabled 19"] +pub type AREN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN20` reader - Async rising enabled 20"] +pub type AREN20_R = crate::BitReader; +#[doc = "Field `AREN20` writer - Async rising enabled 20"] +pub type AREN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN21` reader - Async rising enabled 21"] +pub type AREN21_R = crate::BitReader; +#[doc = "Field `AREN21` writer - Async rising enabled 21"] +pub type AREN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN22` reader - Async rising enabled 22"] +pub type AREN22_R = crate::BitReader; +#[doc = "Field `AREN22` writer - Async rising enabled 22"] +pub type AREN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN23` reader - Async rising enabled 23"] +pub type AREN23_R = crate::BitReader; +#[doc = "Field `AREN23` writer - Async rising enabled 23"] +pub type AREN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN24` reader - Async rising enabled 24"] +pub type AREN24_R = crate::BitReader; +#[doc = "Field `AREN24` writer - Async rising enabled 24"] +pub type AREN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN25` reader - Async rising enabled 25"] +pub type AREN25_R = crate::BitReader; +#[doc = "Field `AREN25` writer - Async rising enabled 25"] +pub type AREN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN26` reader - Async rising enabled 26"] +pub type AREN26_R = crate::BitReader; +#[doc = "Field `AREN26` writer - Async rising enabled 26"] +pub type AREN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN27` reader - Async rising enabled 27"] +pub type AREN27_R = crate::BitReader; +#[doc = "Field `AREN27` writer - Async rising enabled 27"] +pub type AREN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN28` reader - Async rising enabled 28"] +pub type AREN28_R = crate::BitReader; +#[doc = "Field `AREN28` writer - Async rising enabled 28"] +pub type AREN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN29` reader - Async rising enabled 29"] +pub type AREN29_R = crate::BitReader; +#[doc = "Field `AREN29` writer - Async rising enabled 29"] +pub type AREN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN30` reader - Async rising enabled 30"] +pub type AREN30_R = crate::BitReader; +#[doc = "Field `AREN30` writer - Async rising enabled 30"] +pub type AREN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN31` reader - Async rising enabled 31"] +pub type AREN31_R = crate::BitReader; +#[doc = "Field `AREN31` writer - Async rising enabled 31"] +pub type AREN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async rising enabled 0"] + #[inline(always)] + pub fn aren0(&self) -> AREN0_R { + AREN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async rising enabled 1"] + #[inline(always)] + pub fn aren1(&self) -> AREN1_R { + AREN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async rising enabled 2"] + #[inline(always)] + pub fn aren2(&self) -> AREN2_R { + AREN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async rising enabled 3"] + #[inline(always)] + pub fn aren3(&self) -> AREN3_R { + AREN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async rising enabled 4"] + #[inline(always)] + pub fn aren4(&self) -> AREN4_R { + AREN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async rising enabled 5"] + #[inline(always)] + pub fn aren5(&self) -> AREN5_R { + AREN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async rising enabled 6"] + #[inline(always)] + pub fn aren6(&self) -> AREN6_R { + AREN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async rising enabled 7"] + #[inline(always)] + pub fn aren7(&self) -> AREN7_R { + AREN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async rising enabled 8"] + #[inline(always)] + pub fn aren8(&self) -> AREN8_R { + AREN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async rising enabled 9"] + #[inline(always)] + pub fn aren9(&self) -> AREN9_R { + AREN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async rising enabled 10"] + #[inline(always)] + pub fn aren10(&self) -> AREN10_R { + AREN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async rising enabled 11"] + #[inline(always)] + pub fn aren11(&self) -> AREN11_R { + AREN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async rising enabled 12"] + #[inline(always)] + pub fn aren12(&self) -> AREN12_R { + AREN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async rising enabled 13"] + #[inline(always)] + pub fn aren13(&self) -> AREN13_R { + AREN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async rising enabled 14"] + #[inline(always)] + pub fn aren14(&self) -> AREN14_R { + AREN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async rising enabled 15"] + #[inline(always)] + pub fn aren15(&self) -> AREN15_R { + AREN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async rising enabled 16"] + #[inline(always)] + pub fn aren16(&self) -> AREN16_R { + AREN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async rising enabled 17"] + #[inline(always)] + pub fn aren17(&self) -> AREN17_R { + AREN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async rising enabled 18"] + #[inline(always)] + pub fn aren18(&self) -> AREN18_R { + AREN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async rising enabled 19"] + #[inline(always)] + pub fn aren19(&self) -> AREN19_R { + AREN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async rising enabled 20"] + #[inline(always)] + pub fn aren20(&self) -> AREN20_R { + AREN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async rising enabled 21"] + #[inline(always)] + pub fn aren21(&self) -> AREN21_R { + AREN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async rising enabled 22"] + #[inline(always)] + pub fn aren22(&self) -> AREN22_R { + AREN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async rising enabled 23"] + #[inline(always)] + pub fn aren23(&self) -> AREN23_R { + AREN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async rising enabled 24"] + #[inline(always)] + pub fn aren24(&self) -> AREN24_R { + AREN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async rising enabled 25"] + #[inline(always)] + pub fn aren25(&self) -> AREN25_R { + AREN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Async rising enabled 26"] + #[inline(always)] + pub fn aren26(&self) -> AREN26_R { + AREN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Async rising enabled 27"] + #[inline(always)] + pub fn aren27(&self) -> AREN27_R { + AREN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Async rising enabled 28"] + #[inline(always)] + pub fn aren28(&self) -> AREN28_R { + AREN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Async rising enabled 29"] + #[inline(always)] + pub fn aren29(&self) -> AREN29_R { + AREN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Async rising enabled 30"] + #[inline(always)] + pub fn aren30(&self) -> AREN30_R { + AREN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Async rising enabled 31"] + #[inline(always)] + pub fn aren31(&self) -> AREN31_R { + AREN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async rising enabled 0"] + #[inline(always)] + #[must_use] + pub fn aren0(&mut self) -> AREN0_W<0> { + AREN0_W::new(self) + } + #[doc = "Bit 1 - Async rising enabled 1"] + #[inline(always)] + #[must_use] + pub fn aren1(&mut self) -> AREN1_W<1> { + AREN1_W::new(self) + } + #[doc = "Bit 2 - Async rising enabled 2"] + #[inline(always)] + #[must_use] + pub fn aren2(&mut self) -> AREN2_W<2> { + AREN2_W::new(self) + } + #[doc = "Bit 3 - Async rising enabled 3"] + #[inline(always)] + #[must_use] + pub fn aren3(&mut self) -> AREN3_W<3> { + AREN3_W::new(self) + } + #[doc = "Bit 4 - Async rising enabled 4"] + #[inline(always)] + #[must_use] + pub fn aren4(&mut self) -> AREN4_W<4> { + AREN4_W::new(self) + } + #[doc = "Bit 5 - Async rising enabled 5"] + #[inline(always)] + #[must_use] + pub fn aren5(&mut self) -> AREN5_W<5> { + AREN5_W::new(self) + } + #[doc = "Bit 6 - Async rising enabled 6"] + #[inline(always)] + #[must_use] + pub fn aren6(&mut self) -> AREN6_W<6> { + AREN6_W::new(self) + } + #[doc = "Bit 7 - Async rising enabled 7"] + #[inline(always)] + #[must_use] + pub fn aren7(&mut self) -> AREN7_W<7> { + AREN7_W::new(self) + } + #[doc = "Bit 8 - Async rising enabled 8"] + #[inline(always)] + #[must_use] + pub fn aren8(&mut self) -> AREN8_W<8> { + AREN8_W::new(self) + } + #[doc = "Bit 9 - Async rising enabled 9"] + #[inline(always)] + #[must_use] + pub fn aren9(&mut self) -> AREN9_W<9> { + AREN9_W::new(self) + } + #[doc = "Bit 10 - Async rising enabled 10"] + #[inline(always)] + #[must_use] + pub fn aren10(&mut self) -> AREN10_W<10> { + AREN10_W::new(self) + } + #[doc = "Bit 11 - Async rising enabled 11"] + #[inline(always)] + #[must_use] + pub fn aren11(&mut self) -> AREN11_W<11> { + AREN11_W::new(self) + } + #[doc = "Bit 12 - Async rising enabled 12"] + #[inline(always)] + #[must_use] + pub fn aren12(&mut self) -> AREN12_W<12> { + AREN12_W::new(self) + } + #[doc = "Bit 13 - Async rising enabled 13"] + #[inline(always)] + #[must_use] + pub fn aren13(&mut self) -> AREN13_W<13> { + AREN13_W::new(self) + } + #[doc = "Bit 14 - Async rising enabled 14"] + #[inline(always)] + #[must_use] + pub fn aren14(&mut self) -> AREN14_W<14> { + AREN14_W::new(self) + } + #[doc = "Bit 15 - Async rising enabled 15"] + #[inline(always)] + #[must_use] + pub fn aren15(&mut self) -> AREN15_W<15> { + AREN15_W::new(self) + } + #[doc = "Bit 16 - Async rising enabled 16"] + #[inline(always)] + #[must_use] + pub fn aren16(&mut self) -> AREN16_W<16> { + AREN16_W::new(self) + } + #[doc = "Bit 17 - Async rising enabled 17"] + #[inline(always)] + #[must_use] + pub fn aren17(&mut self) -> AREN17_W<17> { + AREN17_W::new(self) + } + #[doc = "Bit 18 - Async rising enabled 18"] + #[inline(always)] + #[must_use] + pub fn aren18(&mut self) -> AREN18_W<18> { + AREN18_W::new(self) + } + #[doc = "Bit 19 - Async rising enabled 19"] + #[inline(always)] + #[must_use] + pub fn aren19(&mut self) -> AREN19_W<19> { + AREN19_W::new(self) + } + #[doc = "Bit 20 - Async rising enabled 20"] + #[inline(always)] + #[must_use] + pub fn aren20(&mut self) -> AREN20_W<20> { + AREN20_W::new(self) + } + #[doc = "Bit 21 - Async rising enabled 21"] + #[inline(always)] + #[must_use] + pub fn aren21(&mut self) -> AREN21_W<21> { + AREN21_W::new(self) + } + #[doc = "Bit 22 - Async rising enabled 22"] + #[inline(always)] + #[must_use] + pub fn aren22(&mut self) -> AREN22_W<22> { + AREN22_W::new(self) + } + #[doc = "Bit 23 - Async rising enabled 23"] + #[inline(always)] + #[must_use] + pub fn aren23(&mut self) -> AREN23_W<23> { + AREN23_W::new(self) + } + #[doc = "Bit 24 - Async rising enabled 24"] + #[inline(always)] + #[must_use] + pub fn aren24(&mut self) -> AREN24_W<24> { + AREN24_W::new(self) + } + #[doc = "Bit 25 - Async rising enabled 25"] + #[inline(always)] + #[must_use] + pub fn aren25(&mut self) -> AREN25_W<25> { + AREN25_W::new(self) + } + #[doc = "Bit 26 - Async rising enabled 26"] + #[inline(always)] + #[must_use] + pub fn aren26(&mut self) -> AREN26_W<26> { + AREN26_W::new(self) + } + #[doc = "Bit 27 - Async rising enabled 27"] + #[inline(always)] + #[must_use] + pub fn aren27(&mut self) -> AREN27_W<27> { + AREN27_W::new(self) + } + #[doc = "Bit 28 - Async rising enabled 28"] + #[inline(always)] + #[must_use] + pub fn aren28(&mut self) -> AREN28_W<28> { + AREN28_W::new(self) + } + #[doc = "Bit 29 - Async rising enabled 29"] + #[inline(always)] + #[must_use] + pub fn aren29(&mut self) -> AREN29_W<29> { + AREN29_W::new(self) + } + #[doc = "Bit 30 - Async rising enabled 30"] + #[inline(always)] + #[must_use] + pub fn aren30(&mut self) -> AREN30_W<30> { + AREN30_W::new(self) + } + #[doc = "Bit 31 - Async rising enabled 31"] + #[inline(always)] + #[must_use] + pub fn aren31(&mut self) -> AREN31_W<31> { + AREN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen0](index.html) module"] +pub struct GPAREN0_SPEC; +impl crate::RegisterSpec for GPAREN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gparen0::R](R) reader structure"] +impl crate::Readable for GPAREN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gparen0::W](W) writer structure"] +impl crate::Writable for GPAREN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gparen1.rs b/crates/bcm2711-lpa/src/gpio/gparen1.rs new file mode 100644 index 0000000..28863a6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gparen1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPAREN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAREN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AREN32` reader - Async rising enabled 32"] +pub type AREN32_R = crate::BitReader; +#[doc = "Field `AREN32` writer - Async rising enabled 32"] +pub type AREN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN33` reader - Async rising enabled 33"] +pub type AREN33_R = crate::BitReader; +#[doc = "Field `AREN33` writer - Async rising enabled 33"] +pub type AREN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN34` reader - Async rising enabled 34"] +pub type AREN34_R = crate::BitReader; +#[doc = "Field `AREN34` writer - Async rising enabled 34"] +pub type AREN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN35` reader - Async rising enabled 35"] +pub type AREN35_R = crate::BitReader; +#[doc = "Field `AREN35` writer - Async rising enabled 35"] +pub type AREN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN36` reader - Async rising enabled 36"] +pub type AREN36_R = crate::BitReader; +#[doc = "Field `AREN36` writer - Async rising enabled 36"] +pub type AREN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN37` reader - Async rising enabled 37"] +pub type AREN37_R = crate::BitReader; +#[doc = "Field `AREN37` writer - Async rising enabled 37"] +pub type AREN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN38` reader - Async rising enabled 38"] +pub type AREN38_R = crate::BitReader; +#[doc = "Field `AREN38` writer - Async rising enabled 38"] +pub type AREN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN39` reader - Async rising enabled 39"] +pub type AREN39_R = crate::BitReader; +#[doc = "Field `AREN39` writer - Async rising enabled 39"] +pub type AREN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN40` reader - Async rising enabled 40"] +pub type AREN40_R = crate::BitReader; +#[doc = "Field `AREN40` writer - Async rising enabled 40"] +pub type AREN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN41` reader - Async rising enabled 41"] +pub type AREN41_R = crate::BitReader; +#[doc = "Field `AREN41` writer - Async rising enabled 41"] +pub type AREN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN42` reader - Async rising enabled 42"] +pub type AREN42_R = crate::BitReader; +#[doc = "Field `AREN42` writer - Async rising enabled 42"] +pub type AREN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN43` reader - Async rising enabled 43"] +pub type AREN43_R = crate::BitReader; +#[doc = "Field `AREN43` writer - Async rising enabled 43"] +pub type AREN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN44` reader - Async rising enabled 44"] +pub type AREN44_R = crate::BitReader; +#[doc = "Field `AREN44` writer - Async rising enabled 44"] +pub type AREN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN45` reader - Async rising enabled 45"] +pub type AREN45_R = crate::BitReader; +#[doc = "Field `AREN45` writer - Async rising enabled 45"] +pub type AREN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN46` reader - Async rising enabled 46"] +pub type AREN46_R = crate::BitReader; +#[doc = "Field `AREN46` writer - Async rising enabled 46"] +pub type AREN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN47` reader - Async rising enabled 47"] +pub type AREN47_R = crate::BitReader; +#[doc = "Field `AREN47` writer - Async rising enabled 47"] +pub type AREN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN48` reader - Async rising enabled 48"] +pub type AREN48_R = crate::BitReader; +#[doc = "Field `AREN48` writer - Async rising enabled 48"] +pub type AREN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN49` reader - Async rising enabled 49"] +pub type AREN49_R = crate::BitReader; +#[doc = "Field `AREN49` writer - Async rising enabled 49"] +pub type AREN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN50` reader - Async rising enabled 50"] +pub type AREN50_R = crate::BitReader; +#[doc = "Field `AREN50` writer - Async rising enabled 50"] +pub type AREN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN51` reader - Async rising enabled 51"] +pub type AREN51_R = crate::BitReader; +#[doc = "Field `AREN51` writer - Async rising enabled 51"] +pub type AREN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN52` reader - Async rising enabled 52"] +pub type AREN52_R = crate::BitReader; +#[doc = "Field `AREN52` writer - Async rising enabled 52"] +pub type AREN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN53` reader - Async rising enabled 53"] +pub type AREN53_R = crate::BitReader; +#[doc = "Field `AREN53` writer - Async rising enabled 53"] +pub type AREN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN54` reader - Async rising enabled 54"] +pub type AREN54_R = crate::BitReader; +#[doc = "Field `AREN54` writer - Async rising enabled 54"] +pub type AREN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN55` reader - Async rising enabled 55"] +pub type AREN55_R = crate::BitReader; +#[doc = "Field `AREN55` writer - Async rising enabled 55"] +pub type AREN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN56` reader - Async rising enabled 56"] +pub type AREN56_R = crate::BitReader; +#[doc = "Field `AREN56` writer - Async rising enabled 56"] +pub type AREN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN57` reader - Async rising enabled 57"] +pub type AREN57_R = crate::BitReader; +#[doc = "Field `AREN57` writer - Async rising enabled 57"] +pub type AREN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async rising enabled 32"] + #[inline(always)] + pub fn aren32(&self) -> AREN32_R { + AREN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async rising enabled 33"] + #[inline(always)] + pub fn aren33(&self) -> AREN33_R { + AREN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async rising enabled 34"] + #[inline(always)] + pub fn aren34(&self) -> AREN34_R { + AREN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async rising enabled 35"] + #[inline(always)] + pub fn aren35(&self) -> AREN35_R { + AREN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async rising enabled 36"] + #[inline(always)] + pub fn aren36(&self) -> AREN36_R { + AREN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async rising enabled 37"] + #[inline(always)] + pub fn aren37(&self) -> AREN37_R { + AREN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async rising enabled 38"] + #[inline(always)] + pub fn aren38(&self) -> AREN38_R { + AREN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async rising enabled 39"] + #[inline(always)] + pub fn aren39(&self) -> AREN39_R { + AREN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async rising enabled 40"] + #[inline(always)] + pub fn aren40(&self) -> AREN40_R { + AREN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async rising enabled 41"] + #[inline(always)] + pub fn aren41(&self) -> AREN41_R { + AREN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async rising enabled 42"] + #[inline(always)] + pub fn aren42(&self) -> AREN42_R { + AREN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async rising enabled 43"] + #[inline(always)] + pub fn aren43(&self) -> AREN43_R { + AREN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async rising enabled 44"] + #[inline(always)] + pub fn aren44(&self) -> AREN44_R { + AREN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async rising enabled 45"] + #[inline(always)] + pub fn aren45(&self) -> AREN45_R { + AREN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async rising enabled 46"] + #[inline(always)] + pub fn aren46(&self) -> AREN46_R { + AREN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async rising enabled 47"] + #[inline(always)] + pub fn aren47(&self) -> AREN47_R { + AREN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async rising enabled 48"] + #[inline(always)] + pub fn aren48(&self) -> AREN48_R { + AREN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async rising enabled 49"] + #[inline(always)] + pub fn aren49(&self) -> AREN49_R { + AREN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async rising enabled 50"] + #[inline(always)] + pub fn aren50(&self) -> AREN50_R { + AREN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async rising enabled 51"] + #[inline(always)] + pub fn aren51(&self) -> AREN51_R { + AREN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async rising enabled 52"] + #[inline(always)] + pub fn aren52(&self) -> AREN52_R { + AREN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async rising enabled 53"] + #[inline(always)] + pub fn aren53(&self) -> AREN53_R { + AREN53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async rising enabled 54"] + #[inline(always)] + pub fn aren54(&self) -> AREN54_R { + AREN54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async rising enabled 55"] + #[inline(always)] + pub fn aren55(&self) -> AREN55_R { + AREN55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async rising enabled 56"] + #[inline(always)] + pub fn aren56(&self) -> AREN56_R { + AREN56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async rising enabled 57"] + #[inline(always)] + pub fn aren57(&self) -> AREN57_R { + AREN57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async rising enabled 32"] + #[inline(always)] + #[must_use] + pub fn aren32(&mut self) -> AREN32_W<0> { + AREN32_W::new(self) + } + #[doc = "Bit 1 - Async rising enabled 33"] + #[inline(always)] + #[must_use] + pub fn aren33(&mut self) -> AREN33_W<1> { + AREN33_W::new(self) + } + #[doc = "Bit 2 - Async rising enabled 34"] + #[inline(always)] + #[must_use] + pub fn aren34(&mut self) -> AREN34_W<2> { + AREN34_W::new(self) + } + #[doc = "Bit 3 - Async rising enabled 35"] + #[inline(always)] + #[must_use] + pub fn aren35(&mut self) -> AREN35_W<3> { + AREN35_W::new(self) + } + #[doc = "Bit 4 - Async rising enabled 36"] + #[inline(always)] + #[must_use] + pub fn aren36(&mut self) -> AREN36_W<4> { + AREN36_W::new(self) + } + #[doc = "Bit 5 - Async rising enabled 37"] + #[inline(always)] + #[must_use] + pub fn aren37(&mut self) -> AREN37_W<5> { + AREN37_W::new(self) + } + #[doc = "Bit 6 - Async rising enabled 38"] + #[inline(always)] + #[must_use] + pub fn aren38(&mut self) -> AREN38_W<6> { + AREN38_W::new(self) + } + #[doc = "Bit 7 - Async rising enabled 39"] + #[inline(always)] + #[must_use] + pub fn aren39(&mut self) -> AREN39_W<7> { + AREN39_W::new(self) + } + #[doc = "Bit 8 - Async rising enabled 40"] + #[inline(always)] + #[must_use] + pub fn aren40(&mut self) -> AREN40_W<8> { + AREN40_W::new(self) + } + #[doc = "Bit 9 - Async rising enabled 41"] + #[inline(always)] + #[must_use] + pub fn aren41(&mut self) -> AREN41_W<9> { + AREN41_W::new(self) + } + #[doc = "Bit 10 - Async rising enabled 42"] + #[inline(always)] + #[must_use] + pub fn aren42(&mut self) -> AREN42_W<10> { + AREN42_W::new(self) + } + #[doc = "Bit 11 - Async rising enabled 43"] + #[inline(always)] + #[must_use] + pub fn aren43(&mut self) -> AREN43_W<11> { + AREN43_W::new(self) + } + #[doc = "Bit 12 - Async rising enabled 44"] + #[inline(always)] + #[must_use] + pub fn aren44(&mut self) -> AREN44_W<12> { + AREN44_W::new(self) + } + #[doc = "Bit 13 - Async rising enabled 45"] + #[inline(always)] + #[must_use] + pub fn aren45(&mut self) -> AREN45_W<13> { + AREN45_W::new(self) + } + #[doc = "Bit 14 - Async rising enabled 46"] + #[inline(always)] + #[must_use] + pub fn aren46(&mut self) -> AREN46_W<14> { + AREN46_W::new(self) + } + #[doc = "Bit 15 - Async rising enabled 47"] + #[inline(always)] + #[must_use] + pub fn aren47(&mut self) -> AREN47_W<15> { + AREN47_W::new(self) + } + #[doc = "Bit 16 - Async rising enabled 48"] + #[inline(always)] + #[must_use] + pub fn aren48(&mut self) -> AREN48_W<16> { + AREN48_W::new(self) + } + #[doc = "Bit 17 - Async rising enabled 49"] + #[inline(always)] + #[must_use] + pub fn aren49(&mut self) -> AREN49_W<17> { + AREN49_W::new(self) + } + #[doc = "Bit 18 - Async rising enabled 50"] + #[inline(always)] + #[must_use] + pub fn aren50(&mut self) -> AREN50_W<18> { + AREN50_W::new(self) + } + #[doc = "Bit 19 - Async rising enabled 51"] + #[inline(always)] + #[must_use] + pub fn aren51(&mut self) -> AREN51_W<19> { + AREN51_W::new(self) + } + #[doc = "Bit 20 - Async rising enabled 52"] + #[inline(always)] + #[must_use] + pub fn aren52(&mut self) -> AREN52_W<20> { + AREN52_W::new(self) + } + #[doc = "Bit 21 - Async rising enabled 53"] + #[inline(always)] + #[must_use] + pub fn aren53(&mut self) -> AREN53_W<21> { + AREN53_W::new(self) + } + #[doc = "Bit 22 - Async rising enabled 54"] + #[inline(always)] + #[must_use] + pub fn aren54(&mut self) -> AREN54_W<22> { + AREN54_W::new(self) + } + #[doc = "Bit 23 - Async rising enabled 55"] + #[inline(always)] + #[must_use] + pub fn aren55(&mut self) -> AREN55_W<23> { + AREN55_W::new(self) + } + #[doc = "Bit 24 - Async rising enabled 56"] + #[inline(always)] + #[must_use] + pub fn aren56(&mut self) -> AREN56_W<24> { + AREN56_W::new(self) + } + #[doc = "Bit 25 - Async rising enabled 57"] + #[inline(always)] + #[must_use] + pub fn aren57(&mut self) -> AREN57_W<25> { + AREN57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen1](index.html) module"] +pub struct GPAREN1_SPEC; +impl crate::RegisterSpec for GPAREN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gparen1::R](R) reader structure"] +impl crate::Readable for GPAREN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gparen1::W](W) writer structure"] +impl crate::Writable for GPAREN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpclr0.rs b/crates/bcm2711-lpa/src/gpio/gpclr0.rs new file mode 100644 index 0000000..1a6b2cd --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpclr0.rs @@ -0,0 +1,296 @@ +#[doc = "Register `GPCLR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLR0` writer - Clear 0"] +pub type CLR0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR1` writer - Clear 1"] +pub type CLR1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR2` writer - Clear 2"] +pub type CLR2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR3` writer - Clear 3"] +pub type CLR3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR4` writer - Clear 4"] +pub type CLR4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR5` writer - Clear 5"] +pub type CLR5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR6` writer - Clear 6"] +pub type CLR6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR7` writer - Clear 7"] +pub type CLR7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR8` writer - Clear 8"] +pub type CLR8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR9` writer - Clear 9"] +pub type CLR9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR10` writer - Clear 10"] +pub type CLR10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR11` writer - Clear 11"] +pub type CLR11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR12` writer - Clear 12"] +pub type CLR12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR13` writer - Clear 13"] +pub type CLR13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR14` writer - Clear 14"] +pub type CLR14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR15` writer - Clear 15"] +pub type CLR15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR16` writer - Clear 16"] +pub type CLR16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR17` writer - Clear 17"] +pub type CLR17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR18` writer - Clear 18"] +pub type CLR18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR19` writer - Clear 19"] +pub type CLR19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR20` writer - Clear 20"] +pub type CLR20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR21` writer - Clear 21"] +pub type CLR21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR22` writer - Clear 22"] +pub type CLR22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR23` writer - Clear 23"] +pub type CLR23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR24` writer - Clear 24"] +pub type CLR24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR25` writer - Clear 25"] +pub type CLR25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR26` writer - Clear 26"] +pub type CLR26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR27` writer - Clear 27"] +pub type CLR27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR28` writer - Clear 28"] +pub type CLR28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR29` writer - Clear 29"] +pub type CLR29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR30` writer - Clear 30"] +pub type CLR30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR31` writer - Clear 31"] +pub type CLR31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Clear 0"] + #[inline(always)] + #[must_use] + pub fn clr0(&mut self) -> CLR0_W<0> { + CLR0_W::new(self) + } + #[doc = "Bit 1 - Clear 1"] + #[inline(always)] + #[must_use] + pub fn clr1(&mut self) -> CLR1_W<1> { + CLR1_W::new(self) + } + #[doc = "Bit 2 - Clear 2"] + #[inline(always)] + #[must_use] + pub fn clr2(&mut self) -> CLR2_W<2> { + CLR2_W::new(self) + } + #[doc = "Bit 3 - Clear 3"] + #[inline(always)] + #[must_use] + pub fn clr3(&mut self) -> CLR3_W<3> { + CLR3_W::new(self) + } + #[doc = "Bit 4 - Clear 4"] + #[inline(always)] + #[must_use] + pub fn clr4(&mut self) -> CLR4_W<4> { + CLR4_W::new(self) + } + #[doc = "Bit 5 - Clear 5"] + #[inline(always)] + #[must_use] + pub fn clr5(&mut self) -> CLR5_W<5> { + CLR5_W::new(self) + } + #[doc = "Bit 6 - Clear 6"] + #[inline(always)] + #[must_use] + pub fn clr6(&mut self) -> CLR6_W<6> { + CLR6_W::new(self) + } + #[doc = "Bit 7 - Clear 7"] + #[inline(always)] + #[must_use] + pub fn clr7(&mut self) -> CLR7_W<7> { + CLR7_W::new(self) + } + #[doc = "Bit 8 - Clear 8"] + #[inline(always)] + #[must_use] + pub fn clr8(&mut self) -> CLR8_W<8> { + CLR8_W::new(self) + } + #[doc = "Bit 9 - Clear 9"] + #[inline(always)] + #[must_use] + pub fn clr9(&mut self) -> CLR9_W<9> { + CLR9_W::new(self) + } + #[doc = "Bit 10 - Clear 10"] + #[inline(always)] + #[must_use] + pub fn clr10(&mut self) -> CLR10_W<10> { + CLR10_W::new(self) + } + #[doc = "Bit 11 - Clear 11"] + #[inline(always)] + #[must_use] + pub fn clr11(&mut self) -> CLR11_W<11> { + CLR11_W::new(self) + } + #[doc = "Bit 12 - Clear 12"] + #[inline(always)] + #[must_use] + pub fn clr12(&mut self) -> CLR12_W<12> { + CLR12_W::new(self) + } + #[doc = "Bit 13 - Clear 13"] + #[inline(always)] + #[must_use] + pub fn clr13(&mut self) -> CLR13_W<13> { + CLR13_W::new(self) + } + #[doc = "Bit 14 - Clear 14"] + #[inline(always)] + #[must_use] + pub fn clr14(&mut self) -> CLR14_W<14> { + CLR14_W::new(self) + } + #[doc = "Bit 15 - Clear 15"] + #[inline(always)] + #[must_use] + pub fn clr15(&mut self) -> CLR15_W<15> { + CLR15_W::new(self) + } + #[doc = "Bit 16 - Clear 16"] + #[inline(always)] + #[must_use] + pub fn clr16(&mut self) -> CLR16_W<16> { + CLR16_W::new(self) + } + #[doc = "Bit 17 - Clear 17"] + #[inline(always)] + #[must_use] + pub fn clr17(&mut self) -> CLR17_W<17> { + CLR17_W::new(self) + } + #[doc = "Bit 18 - Clear 18"] + #[inline(always)] + #[must_use] + pub fn clr18(&mut self) -> CLR18_W<18> { + CLR18_W::new(self) + } + #[doc = "Bit 19 - Clear 19"] + #[inline(always)] + #[must_use] + pub fn clr19(&mut self) -> CLR19_W<19> { + CLR19_W::new(self) + } + #[doc = "Bit 20 - Clear 20"] + #[inline(always)] + #[must_use] + pub fn clr20(&mut self) -> CLR20_W<20> { + CLR20_W::new(self) + } + #[doc = "Bit 21 - Clear 21"] + #[inline(always)] + #[must_use] + pub fn clr21(&mut self) -> CLR21_W<21> { + CLR21_W::new(self) + } + #[doc = "Bit 22 - Clear 22"] + #[inline(always)] + #[must_use] + pub fn clr22(&mut self) -> CLR22_W<22> { + CLR22_W::new(self) + } + #[doc = "Bit 23 - Clear 23"] + #[inline(always)] + #[must_use] + pub fn clr23(&mut self) -> CLR23_W<23> { + CLR23_W::new(self) + } + #[doc = "Bit 24 - Clear 24"] + #[inline(always)] + #[must_use] + pub fn clr24(&mut self) -> CLR24_W<24> { + CLR24_W::new(self) + } + #[doc = "Bit 25 - Clear 25"] + #[inline(always)] + #[must_use] + pub fn clr25(&mut self) -> CLR25_W<25> { + CLR25_W::new(self) + } + #[doc = "Bit 26 - Clear 26"] + #[inline(always)] + #[must_use] + pub fn clr26(&mut self) -> CLR26_W<26> { + CLR26_W::new(self) + } + #[doc = "Bit 27 - Clear 27"] + #[inline(always)] + #[must_use] + pub fn clr27(&mut self) -> CLR27_W<27> { + CLR27_W::new(self) + } + #[doc = "Bit 28 - Clear 28"] + #[inline(always)] + #[must_use] + pub fn clr28(&mut self) -> CLR28_W<28> { + CLR28_W::new(self) + } + #[doc = "Bit 29 - Clear 29"] + #[inline(always)] + #[must_use] + pub fn clr29(&mut self) -> CLR29_W<29> { + CLR29_W::new(self) + } + #[doc = "Bit 30 - Clear 30"] + #[inline(always)] + #[must_use] + pub fn clr30(&mut self) -> CLR30_W<30> { + CLR30_W::new(self) + } + #[doc = "Bit 31 - Clear 31"] + #[inline(always)] + #[must_use] + pub fn clr31(&mut self) -> CLR31_W<31> { + CLR31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Clear 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr0](index.html) module"] +pub struct GPCLR0_SPEC; +impl crate::RegisterSpec for GPCLR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpclr0::W](W) writer structure"] +impl crate::Writable for GPCLR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpclr1.rs b/crates/bcm2711-lpa/src/gpio/gpclr1.rs new file mode 100644 index 0000000..60a0085 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpclr1.rs @@ -0,0 +1,248 @@ +#[doc = "Register `GPCLR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLR32` writer - Clear 32"] +pub type CLR32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR33` writer - Clear 33"] +pub type CLR33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR34` writer - Clear 34"] +pub type CLR34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR35` writer - Clear 35"] +pub type CLR35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR36` writer - Clear 36"] +pub type CLR36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR37` writer - Clear 37"] +pub type CLR37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR38` writer - Clear 38"] +pub type CLR38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR39` writer - Clear 39"] +pub type CLR39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR40` writer - Clear 40"] +pub type CLR40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR41` writer - Clear 41"] +pub type CLR41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR42` writer - Clear 42"] +pub type CLR42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR43` writer - Clear 43"] +pub type CLR43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR44` writer - Clear 44"] +pub type CLR44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR45` writer - Clear 45"] +pub type CLR45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR46` writer - Clear 46"] +pub type CLR46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR47` writer - Clear 47"] +pub type CLR47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR48` writer - Clear 48"] +pub type CLR48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR49` writer - Clear 49"] +pub type CLR49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR50` writer - Clear 50"] +pub type CLR50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR51` writer - Clear 51"] +pub type CLR51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR52` writer - Clear 52"] +pub type CLR52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR53` writer - Clear 53"] +pub type CLR53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR54` writer - Clear 54"] +pub type CLR54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR55` writer - Clear 55"] +pub type CLR55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR56` writer - Clear 56"] +pub type CLR56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR57` writer - Clear 57"] +pub type CLR57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Clear 32"] + #[inline(always)] + #[must_use] + pub fn clr32(&mut self) -> CLR32_W<0> { + CLR32_W::new(self) + } + #[doc = "Bit 1 - Clear 33"] + #[inline(always)] + #[must_use] + pub fn clr33(&mut self) -> CLR33_W<1> { + CLR33_W::new(self) + } + #[doc = "Bit 2 - Clear 34"] + #[inline(always)] + #[must_use] + pub fn clr34(&mut self) -> CLR34_W<2> { + CLR34_W::new(self) + } + #[doc = "Bit 3 - Clear 35"] + #[inline(always)] + #[must_use] + pub fn clr35(&mut self) -> CLR35_W<3> { + CLR35_W::new(self) + } + #[doc = "Bit 4 - Clear 36"] + #[inline(always)] + #[must_use] + pub fn clr36(&mut self) -> CLR36_W<4> { + CLR36_W::new(self) + } + #[doc = "Bit 5 - Clear 37"] + #[inline(always)] + #[must_use] + pub fn clr37(&mut self) -> CLR37_W<5> { + CLR37_W::new(self) + } + #[doc = "Bit 6 - Clear 38"] + #[inline(always)] + #[must_use] + pub fn clr38(&mut self) -> CLR38_W<6> { + CLR38_W::new(self) + } + #[doc = "Bit 7 - Clear 39"] + #[inline(always)] + #[must_use] + pub fn clr39(&mut self) -> CLR39_W<7> { + CLR39_W::new(self) + } + #[doc = "Bit 8 - Clear 40"] + #[inline(always)] + #[must_use] + pub fn clr40(&mut self) -> CLR40_W<8> { + CLR40_W::new(self) + } + #[doc = "Bit 9 - Clear 41"] + #[inline(always)] + #[must_use] + pub fn clr41(&mut self) -> CLR41_W<9> { + CLR41_W::new(self) + } + #[doc = "Bit 10 - Clear 42"] + #[inline(always)] + #[must_use] + pub fn clr42(&mut self) -> CLR42_W<10> { + CLR42_W::new(self) + } + #[doc = "Bit 11 - Clear 43"] + #[inline(always)] + #[must_use] + pub fn clr43(&mut self) -> CLR43_W<11> { + CLR43_W::new(self) + } + #[doc = "Bit 12 - Clear 44"] + #[inline(always)] + #[must_use] + pub fn clr44(&mut self) -> CLR44_W<12> { + CLR44_W::new(self) + } + #[doc = "Bit 13 - Clear 45"] + #[inline(always)] + #[must_use] + pub fn clr45(&mut self) -> CLR45_W<13> { + CLR45_W::new(self) + } + #[doc = "Bit 14 - Clear 46"] + #[inline(always)] + #[must_use] + pub fn clr46(&mut self) -> CLR46_W<14> { + CLR46_W::new(self) + } + #[doc = "Bit 15 - Clear 47"] + #[inline(always)] + #[must_use] + pub fn clr47(&mut self) -> CLR47_W<15> { + CLR47_W::new(self) + } + #[doc = "Bit 16 - Clear 48"] + #[inline(always)] + #[must_use] + pub fn clr48(&mut self) -> CLR48_W<16> { + CLR48_W::new(self) + } + #[doc = "Bit 17 - Clear 49"] + #[inline(always)] + #[must_use] + pub fn clr49(&mut self) -> CLR49_W<17> { + CLR49_W::new(self) + } + #[doc = "Bit 18 - Clear 50"] + #[inline(always)] + #[must_use] + pub fn clr50(&mut self) -> CLR50_W<18> { + CLR50_W::new(self) + } + #[doc = "Bit 19 - Clear 51"] + #[inline(always)] + #[must_use] + pub fn clr51(&mut self) -> CLR51_W<19> { + CLR51_W::new(self) + } + #[doc = "Bit 20 - Clear 52"] + #[inline(always)] + #[must_use] + pub fn clr52(&mut self) -> CLR52_W<20> { + CLR52_W::new(self) + } + #[doc = "Bit 21 - Clear 53"] + #[inline(always)] + #[must_use] + pub fn clr53(&mut self) -> CLR53_W<21> { + CLR53_W::new(self) + } + #[doc = "Bit 22 - Clear 54"] + #[inline(always)] + #[must_use] + pub fn clr54(&mut self) -> CLR54_W<22> { + CLR54_W::new(self) + } + #[doc = "Bit 23 - Clear 55"] + #[inline(always)] + #[must_use] + pub fn clr55(&mut self) -> CLR55_W<23> { + CLR55_W::new(self) + } + #[doc = "Bit 24 - Clear 56"] + #[inline(always)] + #[must_use] + pub fn clr56(&mut self) -> CLR56_W<24> { + CLR56_W::new(self) + } + #[doc = "Bit 25 - Clear 57"] + #[inline(always)] + #[must_use] + pub fn clr57(&mut self) -> CLR57_W<25> { + CLR57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Clear 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr1](index.html) module"] +pub struct GPCLR1_SPEC; +impl crate::RegisterSpec for GPCLR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpclr1::W](W) writer structure"] +impl crate::Writable for GPCLR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03ff_ffff; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpeds0.rs b/crates/bcm2711-lpa/src/gpio/gpeds0.rs new file mode 100644 index 0000000..7aadf5b --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpeds0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPEDS0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPEDS0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EDS0` reader - Event detected 0"] +pub type EDS0_R = crate::BitReader; +#[doc = "Field `EDS0` writer - Event detected 0"] +pub type EDS0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS1` reader - Event detected 1"] +pub type EDS1_R = crate::BitReader; +#[doc = "Field `EDS1` writer - Event detected 1"] +pub type EDS1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS2` reader - Event detected 2"] +pub type EDS2_R = crate::BitReader; +#[doc = "Field `EDS2` writer - Event detected 2"] +pub type EDS2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS3` reader - Event detected 3"] +pub type EDS3_R = crate::BitReader; +#[doc = "Field `EDS3` writer - Event detected 3"] +pub type EDS3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS4` reader - Event detected 4"] +pub type EDS4_R = crate::BitReader; +#[doc = "Field `EDS4` writer - Event detected 4"] +pub type EDS4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS5` reader - Event detected 5"] +pub type EDS5_R = crate::BitReader; +#[doc = "Field `EDS5` writer - Event detected 5"] +pub type EDS5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS6` reader - Event detected 6"] +pub type EDS6_R = crate::BitReader; +#[doc = "Field `EDS6` writer - Event detected 6"] +pub type EDS6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS7` reader - Event detected 7"] +pub type EDS7_R = crate::BitReader; +#[doc = "Field `EDS7` writer - Event detected 7"] +pub type EDS7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS8` reader - Event detected 8"] +pub type EDS8_R = crate::BitReader; +#[doc = "Field `EDS8` writer - Event detected 8"] +pub type EDS8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS9` reader - Event detected 9"] +pub type EDS9_R = crate::BitReader; +#[doc = "Field `EDS9` writer - Event detected 9"] +pub type EDS9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS10` reader - Event detected 10"] +pub type EDS10_R = crate::BitReader; +#[doc = "Field `EDS10` writer - Event detected 10"] +pub type EDS10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS11` reader - Event detected 11"] +pub type EDS11_R = crate::BitReader; +#[doc = "Field `EDS11` writer - Event detected 11"] +pub type EDS11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS12` reader - Event detected 12"] +pub type EDS12_R = crate::BitReader; +#[doc = "Field `EDS12` writer - Event detected 12"] +pub type EDS12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS13` reader - Event detected 13"] +pub type EDS13_R = crate::BitReader; +#[doc = "Field `EDS13` writer - Event detected 13"] +pub type EDS13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS14` reader - Event detected 14"] +pub type EDS14_R = crate::BitReader; +#[doc = "Field `EDS14` writer - Event detected 14"] +pub type EDS14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS15` reader - Event detected 15"] +pub type EDS15_R = crate::BitReader; +#[doc = "Field `EDS15` writer - Event detected 15"] +pub type EDS15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS16` reader - Event detected 16"] +pub type EDS16_R = crate::BitReader; +#[doc = "Field `EDS16` writer - Event detected 16"] +pub type EDS16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS17` reader - Event detected 17"] +pub type EDS17_R = crate::BitReader; +#[doc = "Field `EDS17` writer - Event detected 17"] +pub type EDS17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS18` reader - Event detected 18"] +pub type EDS18_R = crate::BitReader; +#[doc = "Field `EDS18` writer - Event detected 18"] +pub type EDS18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS19` reader - Event detected 19"] +pub type EDS19_R = crate::BitReader; +#[doc = "Field `EDS19` writer - Event detected 19"] +pub type EDS19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS20` reader - Event detected 20"] +pub type EDS20_R = crate::BitReader; +#[doc = "Field `EDS20` writer - Event detected 20"] +pub type EDS20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS21` reader - Event detected 21"] +pub type EDS21_R = crate::BitReader; +#[doc = "Field `EDS21` writer - Event detected 21"] +pub type EDS21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS22` reader - Event detected 22"] +pub type EDS22_R = crate::BitReader; +#[doc = "Field `EDS22` writer - Event detected 22"] +pub type EDS22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS23` reader - Event detected 23"] +pub type EDS23_R = crate::BitReader; +#[doc = "Field `EDS23` writer - Event detected 23"] +pub type EDS23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS24` reader - Event detected 24"] +pub type EDS24_R = crate::BitReader; +#[doc = "Field `EDS24` writer - Event detected 24"] +pub type EDS24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS25` reader - Event detected 25"] +pub type EDS25_R = crate::BitReader; +#[doc = "Field `EDS25` writer - Event detected 25"] +pub type EDS25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS26` reader - Event detected 26"] +pub type EDS26_R = crate::BitReader; +#[doc = "Field `EDS26` writer - Event detected 26"] +pub type EDS26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS27` reader - Event detected 27"] +pub type EDS27_R = crate::BitReader; +#[doc = "Field `EDS27` writer - Event detected 27"] +pub type EDS27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS28` reader - Event detected 28"] +pub type EDS28_R = crate::BitReader; +#[doc = "Field `EDS28` writer - Event detected 28"] +pub type EDS28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS29` reader - Event detected 29"] +pub type EDS29_R = crate::BitReader; +#[doc = "Field `EDS29` writer - Event detected 29"] +pub type EDS29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS30` reader - Event detected 30"] +pub type EDS30_R = crate::BitReader; +#[doc = "Field `EDS30` writer - Event detected 30"] +pub type EDS30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS31` reader - Event detected 31"] +pub type EDS31_R = crate::BitReader; +#[doc = "Field `EDS31` writer - Event detected 31"] +pub type EDS31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Event detected 0"] + #[inline(always)] + pub fn eds0(&self) -> EDS0_R { + EDS0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Event detected 1"] + #[inline(always)] + pub fn eds1(&self) -> EDS1_R { + EDS1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Event detected 2"] + #[inline(always)] + pub fn eds2(&self) -> EDS2_R { + EDS2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Event detected 3"] + #[inline(always)] + pub fn eds3(&self) -> EDS3_R { + EDS3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Event detected 4"] + #[inline(always)] + pub fn eds4(&self) -> EDS4_R { + EDS4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Event detected 5"] + #[inline(always)] + pub fn eds5(&self) -> EDS5_R { + EDS5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Event detected 6"] + #[inline(always)] + pub fn eds6(&self) -> EDS6_R { + EDS6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Event detected 7"] + #[inline(always)] + pub fn eds7(&self) -> EDS7_R { + EDS7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Event detected 8"] + #[inline(always)] + pub fn eds8(&self) -> EDS8_R { + EDS8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Event detected 9"] + #[inline(always)] + pub fn eds9(&self) -> EDS9_R { + EDS9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Event detected 10"] + #[inline(always)] + pub fn eds10(&self) -> EDS10_R { + EDS10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Event detected 11"] + #[inline(always)] + pub fn eds11(&self) -> EDS11_R { + EDS11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Event detected 12"] + #[inline(always)] + pub fn eds12(&self) -> EDS12_R { + EDS12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Event detected 13"] + #[inline(always)] + pub fn eds13(&self) -> EDS13_R { + EDS13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Event detected 14"] + #[inline(always)] + pub fn eds14(&self) -> EDS14_R { + EDS14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Event detected 15"] + #[inline(always)] + pub fn eds15(&self) -> EDS15_R { + EDS15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Event detected 16"] + #[inline(always)] + pub fn eds16(&self) -> EDS16_R { + EDS16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Event detected 17"] + #[inline(always)] + pub fn eds17(&self) -> EDS17_R { + EDS17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event detected 18"] + #[inline(always)] + pub fn eds18(&self) -> EDS18_R { + EDS18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Event detected 19"] + #[inline(always)] + pub fn eds19(&self) -> EDS19_R { + EDS19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Event detected 20"] + #[inline(always)] + pub fn eds20(&self) -> EDS20_R { + EDS20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event detected 21"] + #[inline(always)] + pub fn eds21(&self) -> EDS21_R { + EDS21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Event detected 22"] + #[inline(always)] + pub fn eds22(&self) -> EDS22_R { + EDS22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Event detected 23"] + #[inline(always)] + pub fn eds23(&self) -> EDS23_R { + EDS23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Event detected 24"] + #[inline(always)] + pub fn eds24(&self) -> EDS24_R { + EDS24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Event detected 25"] + #[inline(always)] + pub fn eds25(&self) -> EDS25_R { + EDS25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Event detected 26"] + #[inline(always)] + pub fn eds26(&self) -> EDS26_R { + EDS26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Event detected 27"] + #[inline(always)] + pub fn eds27(&self) -> EDS27_R { + EDS27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Event detected 28"] + #[inline(always)] + pub fn eds28(&self) -> EDS28_R { + EDS28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Event detected 29"] + #[inline(always)] + pub fn eds29(&self) -> EDS29_R { + EDS29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Event detected 30"] + #[inline(always)] + pub fn eds30(&self) -> EDS30_R { + EDS30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Event detected 31"] + #[inline(always)] + pub fn eds31(&self) -> EDS31_R { + EDS31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event detected 0"] + #[inline(always)] + #[must_use] + pub fn eds0(&mut self) -> EDS0_W<0> { + EDS0_W::new(self) + } + #[doc = "Bit 1 - Event detected 1"] + #[inline(always)] + #[must_use] + pub fn eds1(&mut self) -> EDS1_W<1> { + EDS1_W::new(self) + } + #[doc = "Bit 2 - Event detected 2"] + #[inline(always)] + #[must_use] + pub fn eds2(&mut self) -> EDS2_W<2> { + EDS2_W::new(self) + } + #[doc = "Bit 3 - Event detected 3"] + #[inline(always)] + #[must_use] + pub fn eds3(&mut self) -> EDS3_W<3> { + EDS3_W::new(self) + } + #[doc = "Bit 4 - Event detected 4"] + #[inline(always)] + #[must_use] + pub fn eds4(&mut self) -> EDS4_W<4> { + EDS4_W::new(self) + } + #[doc = "Bit 5 - Event detected 5"] + #[inline(always)] + #[must_use] + pub fn eds5(&mut self) -> EDS5_W<5> { + EDS5_W::new(self) + } + #[doc = "Bit 6 - Event detected 6"] + #[inline(always)] + #[must_use] + pub fn eds6(&mut self) -> EDS6_W<6> { + EDS6_W::new(self) + } + #[doc = "Bit 7 - Event detected 7"] + #[inline(always)] + #[must_use] + pub fn eds7(&mut self) -> EDS7_W<7> { + EDS7_W::new(self) + } + #[doc = "Bit 8 - Event detected 8"] + #[inline(always)] + #[must_use] + pub fn eds8(&mut self) -> EDS8_W<8> { + EDS8_W::new(self) + } + #[doc = "Bit 9 - Event detected 9"] + #[inline(always)] + #[must_use] + pub fn eds9(&mut self) -> EDS9_W<9> { + EDS9_W::new(self) + } + #[doc = "Bit 10 - Event detected 10"] + #[inline(always)] + #[must_use] + pub fn eds10(&mut self) -> EDS10_W<10> { + EDS10_W::new(self) + } + #[doc = "Bit 11 - Event detected 11"] + #[inline(always)] + #[must_use] + pub fn eds11(&mut self) -> EDS11_W<11> { + EDS11_W::new(self) + } + #[doc = "Bit 12 - Event detected 12"] + #[inline(always)] + #[must_use] + pub fn eds12(&mut self) -> EDS12_W<12> { + EDS12_W::new(self) + } + #[doc = "Bit 13 - Event detected 13"] + #[inline(always)] + #[must_use] + pub fn eds13(&mut self) -> EDS13_W<13> { + EDS13_W::new(self) + } + #[doc = "Bit 14 - Event detected 14"] + #[inline(always)] + #[must_use] + pub fn eds14(&mut self) -> EDS14_W<14> { + EDS14_W::new(self) + } + #[doc = "Bit 15 - Event detected 15"] + #[inline(always)] + #[must_use] + pub fn eds15(&mut self) -> EDS15_W<15> { + EDS15_W::new(self) + } + #[doc = "Bit 16 - Event detected 16"] + #[inline(always)] + #[must_use] + pub fn eds16(&mut self) -> EDS16_W<16> { + EDS16_W::new(self) + } + #[doc = "Bit 17 - Event detected 17"] + #[inline(always)] + #[must_use] + pub fn eds17(&mut self) -> EDS17_W<17> { + EDS17_W::new(self) + } + #[doc = "Bit 18 - Event detected 18"] + #[inline(always)] + #[must_use] + pub fn eds18(&mut self) -> EDS18_W<18> { + EDS18_W::new(self) + } + #[doc = "Bit 19 - Event detected 19"] + #[inline(always)] + #[must_use] + pub fn eds19(&mut self) -> EDS19_W<19> { + EDS19_W::new(self) + } + #[doc = "Bit 20 - Event detected 20"] + #[inline(always)] + #[must_use] + pub fn eds20(&mut self) -> EDS20_W<20> { + EDS20_W::new(self) + } + #[doc = "Bit 21 - Event detected 21"] + #[inline(always)] + #[must_use] + pub fn eds21(&mut self) -> EDS21_W<21> { + EDS21_W::new(self) + } + #[doc = "Bit 22 - Event detected 22"] + #[inline(always)] + #[must_use] + pub fn eds22(&mut self) -> EDS22_W<22> { + EDS22_W::new(self) + } + #[doc = "Bit 23 - Event detected 23"] + #[inline(always)] + #[must_use] + pub fn eds23(&mut self) -> EDS23_W<23> { + EDS23_W::new(self) + } + #[doc = "Bit 24 - Event detected 24"] + #[inline(always)] + #[must_use] + pub fn eds24(&mut self) -> EDS24_W<24> { + EDS24_W::new(self) + } + #[doc = "Bit 25 - Event detected 25"] + #[inline(always)] + #[must_use] + pub fn eds25(&mut self) -> EDS25_W<25> { + EDS25_W::new(self) + } + #[doc = "Bit 26 - Event detected 26"] + #[inline(always)] + #[must_use] + pub fn eds26(&mut self) -> EDS26_W<26> { + EDS26_W::new(self) + } + #[doc = "Bit 27 - Event detected 27"] + #[inline(always)] + #[must_use] + pub fn eds27(&mut self) -> EDS27_W<27> { + EDS27_W::new(self) + } + #[doc = "Bit 28 - Event detected 28"] + #[inline(always)] + #[must_use] + pub fn eds28(&mut self) -> EDS28_W<28> { + EDS28_W::new(self) + } + #[doc = "Bit 29 - Event detected 29"] + #[inline(always)] + #[must_use] + pub fn eds29(&mut self) -> EDS29_W<29> { + EDS29_W::new(self) + } + #[doc = "Bit 30 - Event detected 30"] + #[inline(always)] + #[must_use] + pub fn eds30(&mut self) -> EDS30_W<30> { + EDS30_W::new(self) + } + #[doc = "Bit 31 - Event detected 31"] + #[inline(always)] + #[must_use] + pub fn eds31(&mut self) -> EDS31_W<31> { + EDS31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Event Detect Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds0](index.html) module"] +pub struct GPEDS0_SPEC; +impl crate::RegisterSpec for GPEDS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpeds0::R](R) reader structure"] +impl crate::Readable for GPEDS0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpeds0::W](W) writer structure"] +impl crate::Writable for GPEDS0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpeds1.rs b/crates/bcm2711-lpa/src/gpio/gpeds1.rs new file mode 100644 index 0000000..d233308 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpeds1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPEDS1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPEDS1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EDS32` reader - Event detected 32"] +pub type EDS32_R = crate::BitReader; +#[doc = "Field `EDS32` writer - Event detected 32"] +pub type EDS32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS33` reader - Event detected 33"] +pub type EDS33_R = crate::BitReader; +#[doc = "Field `EDS33` writer - Event detected 33"] +pub type EDS33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS34` reader - Event detected 34"] +pub type EDS34_R = crate::BitReader; +#[doc = "Field `EDS34` writer - Event detected 34"] +pub type EDS34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS35` reader - Event detected 35"] +pub type EDS35_R = crate::BitReader; +#[doc = "Field `EDS35` writer - Event detected 35"] +pub type EDS35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS36` reader - Event detected 36"] +pub type EDS36_R = crate::BitReader; +#[doc = "Field `EDS36` writer - Event detected 36"] +pub type EDS36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS37` reader - Event detected 37"] +pub type EDS37_R = crate::BitReader; +#[doc = "Field `EDS37` writer - Event detected 37"] +pub type EDS37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS38` reader - Event detected 38"] +pub type EDS38_R = crate::BitReader; +#[doc = "Field `EDS38` writer - Event detected 38"] +pub type EDS38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS39` reader - Event detected 39"] +pub type EDS39_R = crate::BitReader; +#[doc = "Field `EDS39` writer - Event detected 39"] +pub type EDS39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS40` reader - Event detected 40"] +pub type EDS40_R = crate::BitReader; +#[doc = "Field `EDS40` writer - Event detected 40"] +pub type EDS40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS41` reader - Event detected 41"] +pub type EDS41_R = crate::BitReader; +#[doc = "Field `EDS41` writer - Event detected 41"] +pub type EDS41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS42` reader - Event detected 42"] +pub type EDS42_R = crate::BitReader; +#[doc = "Field `EDS42` writer - Event detected 42"] +pub type EDS42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS43` reader - Event detected 43"] +pub type EDS43_R = crate::BitReader; +#[doc = "Field `EDS43` writer - Event detected 43"] +pub type EDS43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS44` reader - Event detected 44"] +pub type EDS44_R = crate::BitReader; +#[doc = "Field `EDS44` writer - Event detected 44"] +pub type EDS44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS45` reader - Event detected 45"] +pub type EDS45_R = crate::BitReader; +#[doc = "Field `EDS45` writer - Event detected 45"] +pub type EDS45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS46` reader - Event detected 46"] +pub type EDS46_R = crate::BitReader; +#[doc = "Field `EDS46` writer - Event detected 46"] +pub type EDS46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS47` reader - Event detected 47"] +pub type EDS47_R = crate::BitReader; +#[doc = "Field `EDS47` writer - Event detected 47"] +pub type EDS47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS48` reader - Event detected 48"] +pub type EDS48_R = crate::BitReader; +#[doc = "Field `EDS48` writer - Event detected 48"] +pub type EDS48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS49` reader - Event detected 49"] +pub type EDS49_R = crate::BitReader; +#[doc = "Field `EDS49` writer - Event detected 49"] +pub type EDS49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS50` reader - Event detected 50"] +pub type EDS50_R = crate::BitReader; +#[doc = "Field `EDS50` writer - Event detected 50"] +pub type EDS50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS51` reader - Event detected 51"] +pub type EDS51_R = crate::BitReader; +#[doc = "Field `EDS51` writer - Event detected 51"] +pub type EDS51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS52` reader - Event detected 52"] +pub type EDS52_R = crate::BitReader; +#[doc = "Field `EDS52` writer - Event detected 52"] +pub type EDS52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS53` reader - Event detected 53"] +pub type EDS53_R = crate::BitReader; +#[doc = "Field `EDS53` writer - Event detected 53"] +pub type EDS53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS54` reader - Event detected 54"] +pub type EDS54_R = crate::BitReader; +#[doc = "Field `EDS54` writer - Event detected 54"] +pub type EDS54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS55` reader - Event detected 55"] +pub type EDS55_R = crate::BitReader; +#[doc = "Field `EDS55` writer - Event detected 55"] +pub type EDS55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS56` reader - Event detected 56"] +pub type EDS56_R = crate::BitReader; +#[doc = "Field `EDS56` writer - Event detected 56"] +pub type EDS56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS57` reader - Event detected 57"] +pub type EDS57_R = crate::BitReader; +#[doc = "Field `EDS57` writer - Event detected 57"] +pub type EDS57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Event detected 32"] + #[inline(always)] + pub fn eds32(&self) -> EDS32_R { + EDS32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Event detected 33"] + #[inline(always)] + pub fn eds33(&self) -> EDS33_R { + EDS33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Event detected 34"] + #[inline(always)] + pub fn eds34(&self) -> EDS34_R { + EDS34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Event detected 35"] + #[inline(always)] + pub fn eds35(&self) -> EDS35_R { + EDS35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Event detected 36"] + #[inline(always)] + pub fn eds36(&self) -> EDS36_R { + EDS36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Event detected 37"] + #[inline(always)] + pub fn eds37(&self) -> EDS37_R { + EDS37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Event detected 38"] + #[inline(always)] + pub fn eds38(&self) -> EDS38_R { + EDS38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Event detected 39"] + #[inline(always)] + pub fn eds39(&self) -> EDS39_R { + EDS39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Event detected 40"] + #[inline(always)] + pub fn eds40(&self) -> EDS40_R { + EDS40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Event detected 41"] + #[inline(always)] + pub fn eds41(&self) -> EDS41_R { + EDS41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Event detected 42"] + #[inline(always)] + pub fn eds42(&self) -> EDS42_R { + EDS42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Event detected 43"] + #[inline(always)] + pub fn eds43(&self) -> EDS43_R { + EDS43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Event detected 44"] + #[inline(always)] + pub fn eds44(&self) -> EDS44_R { + EDS44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Event detected 45"] + #[inline(always)] + pub fn eds45(&self) -> EDS45_R { + EDS45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Event detected 46"] + #[inline(always)] + pub fn eds46(&self) -> EDS46_R { + EDS46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Event detected 47"] + #[inline(always)] + pub fn eds47(&self) -> EDS47_R { + EDS47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Event detected 48"] + #[inline(always)] + pub fn eds48(&self) -> EDS48_R { + EDS48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Event detected 49"] + #[inline(always)] + pub fn eds49(&self) -> EDS49_R { + EDS49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event detected 50"] + #[inline(always)] + pub fn eds50(&self) -> EDS50_R { + EDS50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Event detected 51"] + #[inline(always)] + pub fn eds51(&self) -> EDS51_R { + EDS51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Event detected 52"] + #[inline(always)] + pub fn eds52(&self) -> EDS52_R { + EDS52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event detected 53"] + #[inline(always)] + pub fn eds53(&self) -> EDS53_R { + EDS53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Event detected 54"] + #[inline(always)] + pub fn eds54(&self) -> EDS54_R { + EDS54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Event detected 55"] + #[inline(always)] + pub fn eds55(&self) -> EDS55_R { + EDS55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Event detected 56"] + #[inline(always)] + pub fn eds56(&self) -> EDS56_R { + EDS56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Event detected 57"] + #[inline(always)] + pub fn eds57(&self) -> EDS57_R { + EDS57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event detected 32"] + #[inline(always)] + #[must_use] + pub fn eds32(&mut self) -> EDS32_W<0> { + EDS32_W::new(self) + } + #[doc = "Bit 1 - Event detected 33"] + #[inline(always)] + #[must_use] + pub fn eds33(&mut self) -> EDS33_W<1> { + EDS33_W::new(self) + } + #[doc = "Bit 2 - Event detected 34"] + #[inline(always)] + #[must_use] + pub fn eds34(&mut self) -> EDS34_W<2> { + EDS34_W::new(self) + } + #[doc = "Bit 3 - Event detected 35"] + #[inline(always)] + #[must_use] + pub fn eds35(&mut self) -> EDS35_W<3> { + EDS35_W::new(self) + } + #[doc = "Bit 4 - Event detected 36"] + #[inline(always)] + #[must_use] + pub fn eds36(&mut self) -> EDS36_W<4> { + EDS36_W::new(self) + } + #[doc = "Bit 5 - Event detected 37"] + #[inline(always)] + #[must_use] + pub fn eds37(&mut self) -> EDS37_W<5> { + EDS37_W::new(self) + } + #[doc = "Bit 6 - Event detected 38"] + #[inline(always)] + #[must_use] + pub fn eds38(&mut self) -> EDS38_W<6> { + EDS38_W::new(self) + } + #[doc = "Bit 7 - Event detected 39"] + #[inline(always)] + #[must_use] + pub fn eds39(&mut self) -> EDS39_W<7> { + EDS39_W::new(self) + } + #[doc = "Bit 8 - Event detected 40"] + #[inline(always)] + #[must_use] + pub fn eds40(&mut self) -> EDS40_W<8> { + EDS40_W::new(self) + } + #[doc = "Bit 9 - Event detected 41"] + #[inline(always)] + #[must_use] + pub fn eds41(&mut self) -> EDS41_W<9> { + EDS41_W::new(self) + } + #[doc = "Bit 10 - Event detected 42"] + #[inline(always)] + #[must_use] + pub fn eds42(&mut self) -> EDS42_W<10> { + EDS42_W::new(self) + } + #[doc = "Bit 11 - Event detected 43"] + #[inline(always)] + #[must_use] + pub fn eds43(&mut self) -> EDS43_W<11> { + EDS43_W::new(self) + } + #[doc = "Bit 12 - Event detected 44"] + #[inline(always)] + #[must_use] + pub fn eds44(&mut self) -> EDS44_W<12> { + EDS44_W::new(self) + } + #[doc = "Bit 13 - Event detected 45"] + #[inline(always)] + #[must_use] + pub fn eds45(&mut self) -> EDS45_W<13> { + EDS45_W::new(self) + } + #[doc = "Bit 14 - Event detected 46"] + #[inline(always)] + #[must_use] + pub fn eds46(&mut self) -> EDS46_W<14> { + EDS46_W::new(self) + } + #[doc = "Bit 15 - Event detected 47"] + #[inline(always)] + #[must_use] + pub fn eds47(&mut self) -> EDS47_W<15> { + EDS47_W::new(self) + } + #[doc = "Bit 16 - Event detected 48"] + #[inline(always)] + #[must_use] + pub fn eds48(&mut self) -> EDS48_W<16> { + EDS48_W::new(self) + } + #[doc = "Bit 17 - Event detected 49"] + #[inline(always)] + #[must_use] + pub fn eds49(&mut self) -> EDS49_W<17> { + EDS49_W::new(self) + } + #[doc = "Bit 18 - Event detected 50"] + #[inline(always)] + #[must_use] + pub fn eds50(&mut self) -> EDS50_W<18> { + EDS50_W::new(self) + } + #[doc = "Bit 19 - Event detected 51"] + #[inline(always)] + #[must_use] + pub fn eds51(&mut self) -> EDS51_W<19> { + EDS51_W::new(self) + } + #[doc = "Bit 20 - Event detected 52"] + #[inline(always)] + #[must_use] + pub fn eds52(&mut self) -> EDS52_W<20> { + EDS52_W::new(self) + } + #[doc = "Bit 21 - Event detected 53"] + #[inline(always)] + #[must_use] + pub fn eds53(&mut self) -> EDS53_W<21> { + EDS53_W::new(self) + } + #[doc = "Bit 22 - Event detected 54"] + #[inline(always)] + #[must_use] + pub fn eds54(&mut self) -> EDS54_W<22> { + EDS54_W::new(self) + } + #[doc = "Bit 23 - Event detected 55"] + #[inline(always)] + #[must_use] + pub fn eds55(&mut self) -> EDS55_W<23> { + EDS55_W::new(self) + } + #[doc = "Bit 24 - Event detected 56"] + #[inline(always)] + #[must_use] + pub fn eds56(&mut self) -> EDS56_W<24> { + EDS56_W::new(self) + } + #[doc = "Bit 25 - Event detected 57"] + #[inline(always)] + #[must_use] + pub fn eds57(&mut self) -> EDS57_W<25> { + EDS57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Event Detect Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds1](index.html) module"] +pub struct GPEDS1_SPEC; +impl crate::RegisterSpec for GPEDS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpeds1::R](R) reader structure"] +impl crate::Readable for GPEDS1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpeds1::W](W) writer structure"] +impl crate::Writable for GPEDS1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03ff_ffff; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfen0.rs b/crates/bcm2711-lpa/src/gpio/gpfen0.rs new file mode 100644 index 0000000..58ded22 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPFEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FEN0` reader - Falling edge enabled 0"] +pub type FEN0_R = crate::BitReader; +#[doc = "Field `FEN0` writer - Falling edge enabled 0"] +pub type FEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN1` reader - Falling edge enabled 1"] +pub type FEN1_R = crate::BitReader; +#[doc = "Field `FEN1` writer - Falling edge enabled 1"] +pub type FEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN2` reader - Falling edge enabled 2"] +pub type FEN2_R = crate::BitReader; +#[doc = "Field `FEN2` writer - Falling edge enabled 2"] +pub type FEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN3` reader - Falling edge enabled 3"] +pub type FEN3_R = crate::BitReader; +#[doc = "Field `FEN3` writer - Falling edge enabled 3"] +pub type FEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN4` reader - Falling edge enabled 4"] +pub type FEN4_R = crate::BitReader; +#[doc = "Field `FEN4` writer - Falling edge enabled 4"] +pub type FEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN5` reader - Falling edge enabled 5"] +pub type FEN5_R = crate::BitReader; +#[doc = "Field `FEN5` writer - Falling edge enabled 5"] +pub type FEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN6` reader - Falling edge enabled 6"] +pub type FEN6_R = crate::BitReader; +#[doc = "Field `FEN6` writer - Falling edge enabled 6"] +pub type FEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN7` reader - Falling edge enabled 7"] +pub type FEN7_R = crate::BitReader; +#[doc = "Field `FEN7` writer - Falling edge enabled 7"] +pub type FEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN8` reader - Falling edge enabled 8"] +pub type FEN8_R = crate::BitReader; +#[doc = "Field `FEN8` writer - Falling edge enabled 8"] +pub type FEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN9` reader - Falling edge enabled 9"] +pub type FEN9_R = crate::BitReader; +#[doc = "Field `FEN9` writer - Falling edge enabled 9"] +pub type FEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN10` reader - Falling edge enabled 10"] +pub type FEN10_R = crate::BitReader; +#[doc = "Field `FEN10` writer - Falling edge enabled 10"] +pub type FEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN11` reader - Falling edge enabled 11"] +pub type FEN11_R = crate::BitReader; +#[doc = "Field `FEN11` writer - Falling edge enabled 11"] +pub type FEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN12` reader - Falling edge enabled 12"] +pub type FEN12_R = crate::BitReader; +#[doc = "Field `FEN12` writer - Falling edge enabled 12"] +pub type FEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN13` reader - Falling edge enabled 13"] +pub type FEN13_R = crate::BitReader; +#[doc = "Field `FEN13` writer - Falling edge enabled 13"] +pub type FEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN14` reader - Falling edge enabled 14"] +pub type FEN14_R = crate::BitReader; +#[doc = "Field `FEN14` writer - Falling edge enabled 14"] +pub type FEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN15` reader - Falling edge enabled 15"] +pub type FEN15_R = crate::BitReader; +#[doc = "Field `FEN15` writer - Falling edge enabled 15"] +pub type FEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN16` reader - Falling edge enabled 16"] +pub type FEN16_R = crate::BitReader; +#[doc = "Field `FEN16` writer - Falling edge enabled 16"] +pub type FEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN17` reader - Falling edge enabled 17"] +pub type FEN17_R = crate::BitReader; +#[doc = "Field `FEN17` writer - Falling edge enabled 17"] +pub type FEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN18` reader - Falling edge enabled 18"] +pub type FEN18_R = crate::BitReader; +#[doc = "Field `FEN18` writer - Falling edge enabled 18"] +pub type FEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN19` reader - Falling edge enabled 19"] +pub type FEN19_R = crate::BitReader; +#[doc = "Field `FEN19` writer - Falling edge enabled 19"] +pub type FEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN20` reader - Falling edge enabled 20"] +pub type FEN20_R = crate::BitReader; +#[doc = "Field `FEN20` writer - Falling edge enabled 20"] +pub type FEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN21` reader - Falling edge enabled 21"] +pub type FEN21_R = crate::BitReader; +#[doc = "Field `FEN21` writer - Falling edge enabled 21"] +pub type FEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN22` reader - Falling edge enabled 22"] +pub type FEN22_R = crate::BitReader; +#[doc = "Field `FEN22` writer - Falling edge enabled 22"] +pub type FEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN23` reader - Falling edge enabled 23"] +pub type FEN23_R = crate::BitReader; +#[doc = "Field `FEN23` writer - Falling edge enabled 23"] +pub type FEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN24` reader - Falling edge enabled 24"] +pub type FEN24_R = crate::BitReader; +#[doc = "Field `FEN24` writer - Falling edge enabled 24"] +pub type FEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN25` reader - Falling edge enabled 25"] +pub type FEN25_R = crate::BitReader; +#[doc = "Field `FEN25` writer - Falling edge enabled 25"] +pub type FEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN26` reader - Falling edge enabled 26"] +pub type FEN26_R = crate::BitReader; +#[doc = "Field `FEN26` writer - Falling edge enabled 26"] +pub type FEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN27` reader - Falling edge enabled 27"] +pub type FEN27_R = crate::BitReader; +#[doc = "Field `FEN27` writer - Falling edge enabled 27"] +pub type FEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN28` reader - Falling edge enabled 28"] +pub type FEN28_R = crate::BitReader; +#[doc = "Field `FEN28` writer - Falling edge enabled 28"] +pub type FEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN29` reader - Falling edge enabled 29"] +pub type FEN29_R = crate::BitReader; +#[doc = "Field `FEN29` writer - Falling edge enabled 29"] +pub type FEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN30` reader - Falling edge enabled 30"] +pub type FEN30_R = crate::BitReader; +#[doc = "Field `FEN30` writer - Falling edge enabled 30"] +pub type FEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN31` reader - Falling edge enabled 31"] +pub type FEN31_R = crate::BitReader; +#[doc = "Field `FEN31` writer - Falling edge enabled 31"] +pub type FEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Falling edge enabled 0"] + #[inline(always)] + pub fn fen0(&self) -> FEN0_R { + FEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling edge enabled 1"] + #[inline(always)] + pub fn fen1(&self) -> FEN1_R { + FEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Falling edge enabled 2"] + #[inline(always)] + pub fn fen2(&self) -> FEN2_R { + FEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Falling edge enabled 3"] + #[inline(always)] + pub fn fen3(&self) -> FEN3_R { + FEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling edge enabled 4"] + #[inline(always)] + pub fn fen4(&self) -> FEN4_R { + FEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Falling edge enabled 5"] + #[inline(always)] + pub fn fen5(&self) -> FEN5_R { + FEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Falling edge enabled 6"] + #[inline(always)] + pub fn fen6(&self) -> FEN6_R { + FEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling edge enabled 7"] + #[inline(always)] + pub fn fen7(&self) -> FEN7_R { + FEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Falling edge enabled 8"] + #[inline(always)] + pub fn fen8(&self) -> FEN8_R { + FEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Falling edge enabled 9"] + #[inline(always)] + pub fn fen9(&self) -> FEN9_R { + FEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling edge enabled 10"] + #[inline(always)] + pub fn fen10(&self) -> FEN10_R { + FEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Falling edge enabled 11"] + #[inline(always)] + pub fn fen11(&self) -> FEN11_R { + FEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Falling edge enabled 12"] + #[inline(always)] + pub fn fen12(&self) -> FEN12_R { + FEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Falling edge enabled 13"] + #[inline(always)] + pub fn fen13(&self) -> FEN13_R { + FEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Falling edge enabled 14"] + #[inline(always)] + pub fn fen14(&self) -> FEN14_R { + FEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Falling edge enabled 15"] + #[inline(always)] + pub fn fen15(&self) -> FEN15_R { + FEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Falling edge enabled 16"] + #[inline(always)] + pub fn fen16(&self) -> FEN16_R { + FEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Falling edge enabled 17"] + #[inline(always)] + pub fn fen17(&self) -> FEN17_R { + FEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Falling edge enabled 18"] + #[inline(always)] + pub fn fen18(&self) -> FEN18_R { + FEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Falling edge enabled 19"] + #[inline(always)] + pub fn fen19(&self) -> FEN19_R { + FEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Falling edge enabled 20"] + #[inline(always)] + pub fn fen20(&self) -> FEN20_R { + FEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Falling edge enabled 21"] + #[inline(always)] + pub fn fen21(&self) -> FEN21_R { + FEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Falling edge enabled 22"] + #[inline(always)] + pub fn fen22(&self) -> FEN22_R { + FEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Falling edge enabled 23"] + #[inline(always)] + pub fn fen23(&self) -> FEN23_R { + FEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Falling edge enabled 24"] + #[inline(always)] + pub fn fen24(&self) -> FEN24_R { + FEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Falling edge enabled 25"] + #[inline(always)] + pub fn fen25(&self) -> FEN25_R { + FEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Falling edge enabled 26"] + #[inline(always)] + pub fn fen26(&self) -> FEN26_R { + FEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Falling edge enabled 27"] + #[inline(always)] + pub fn fen27(&self) -> FEN27_R { + FEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Falling edge enabled 28"] + #[inline(always)] + pub fn fen28(&self) -> FEN28_R { + FEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Falling edge enabled 29"] + #[inline(always)] + pub fn fen29(&self) -> FEN29_R { + FEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Falling edge enabled 30"] + #[inline(always)] + pub fn fen30(&self) -> FEN30_R { + FEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Falling edge enabled 31"] + #[inline(always)] + pub fn fen31(&self) -> FEN31_R { + FEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Falling edge enabled 0"] + #[inline(always)] + #[must_use] + pub fn fen0(&mut self) -> FEN0_W<0> { + FEN0_W::new(self) + } + #[doc = "Bit 1 - Falling edge enabled 1"] + #[inline(always)] + #[must_use] + pub fn fen1(&mut self) -> FEN1_W<1> { + FEN1_W::new(self) + } + #[doc = "Bit 2 - Falling edge enabled 2"] + #[inline(always)] + #[must_use] + pub fn fen2(&mut self) -> FEN2_W<2> { + FEN2_W::new(self) + } + #[doc = "Bit 3 - Falling edge enabled 3"] + #[inline(always)] + #[must_use] + pub fn fen3(&mut self) -> FEN3_W<3> { + FEN3_W::new(self) + } + #[doc = "Bit 4 - Falling edge enabled 4"] + #[inline(always)] + #[must_use] + pub fn fen4(&mut self) -> FEN4_W<4> { + FEN4_W::new(self) + } + #[doc = "Bit 5 - Falling edge enabled 5"] + #[inline(always)] + #[must_use] + pub fn fen5(&mut self) -> FEN5_W<5> { + FEN5_W::new(self) + } + #[doc = "Bit 6 - Falling edge enabled 6"] + #[inline(always)] + #[must_use] + pub fn fen6(&mut self) -> FEN6_W<6> { + FEN6_W::new(self) + } + #[doc = "Bit 7 - Falling edge enabled 7"] + #[inline(always)] + #[must_use] + pub fn fen7(&mut self) -> FEN7_W<7> { + FEN7_W::new(self) + } + #[doc = "Bit 8 - Falling edge enabled 8"] + #[inline(always)] + #[must_use] + pub fn fen8(&mut self) -> FEN8_W<8> { + FEN8_W::new(self) + } + #[doc = "Bit 9 - Falling edge enabled 9"] + #[inline(always)] + #[must_use] + pub fn fen9(&mut self) -> FEN9_W<9> { + FEN9_W::new(self) + } + #[doc = "Bit 10 - Falling edge enabled 10"] + #[inline(always)] + #[must_use] + pub fn fen10(&mut self) -> FEN10_W<10> { + FEN10_W::new(self) + } + #[doc = "Bit 11 - Falling edge enabled 11"] + #[inline(always)] + #[must_use] + pub fn fen11(&mut self) -> FEN11_W<11> { + FEN11_W::new(self) + } + #[doc = "Bit 12 - Falling edge enabled 12"] + #[inline(always)] + #[must_use] + pub fn fen12(&mut self) -> FEN12_W<12> { + FEN12_W::new(self) + } + #[doc = "Bit 13 - Falling edge enabled 13"] + #[inline(always)] + #[must_use] + pub fn fen13(&mut self) -> FEN13_W<13> { + FEN13_W::new(self) + } + #[doc = "Bit 14 - Falling edge enabled 14"] + #[inline(always)] + #[must_use] + pub fn fen14(&mut self) -> FEN14_W<14> { + FEN14_W::new(self) + } + #[doc = "Bit 15 - Falling edge enabled 15"] + #[inline(always)] + #[must_use] + pub fn fen15(&mut self) -> FEN15_W<15> { + FEN15_W::new(self) + } + #[doc = "Bit 16 - Falling edge enabled 16"] + #[inline(always)] + #[must_use] + pub fn fen16(&mut self) -> FEN16_W<16> { + FEN16_W::new(self) + } + #[doc = "Bit 17 - Falling edge enabled 17"] + #[inline(always)] + #[must_use] + pub fn fen17(&mut self) -> FEN17_W<17> { + FEN17_W::new(self) + } + #[doc = "Bit 18 - Falling edge enabled 18"] + #[inline(always)] + #[must_use] + pub fn fen18(&mut self) -> FEN18_W<18> { + FEN18_W::new(self) + } + #[doc = "Bit 19 - Falling edge enabled 19"] + #[inline(always)] + #[must_use] + pub fn fen19(&mut self) -> FEN19_W<19> { + FEN19_W::new(self) + } + #[doc = "Bit 20 - Falling edge enabled 20"] + #[inline(always)] + #[must_use] + pub fn fen20(&mut self) -> FEN20_W<20> { + FEN20_W::new(self) + } + #[doc = "Bit 21 - Falling edge enabled 21"] + #[inline(always)] + #[must_use] + pub fn fen21(&mut self) -> FEN21_W<21> { + FEN21_W::new(self) + } + #[doc = "Bit 22 - Falling edge enabled 22"] + #[inline(always)] + #[must_use] + pub fn fen22(&mut self) -> FEN22_W<22> { + FEN22_W::new(self) + } + #[doc = "Bit 23 - Falling edge enabled 23"] + #[inline(always)] + #[must_use] + pub fn fen23(&mut self) -> FEN23_W<23> { + FEN23_W::new(self) + } + #[doc = "Bit 24 - Falling edge enabled 24"] + #[inline(always)] + #[must_use] + pub fn fen24(&mut self) -> FEN24_W<24> { + FEN24_W::new(self) + } + #[doc = "Bit 25 - Falling edge enabled 25"] + #[inline(always)] + #[must_use] + pub fn fen25(&mut self) -> FEN25_W<25> { + FEN25_W::new(self) + } + #[doc = "Bit 26 - Falling edge enabled 26"] + #[inline(always)] + #[must_use] + pub fn fen26(&mut self) -> FEN26_W<26> { + FEN26_W::new(self) + } + #[doc = "Bit 27 - Falling edge enabled 27"] + #[inline(always)] + #[must_use] + pub fn fen27(&mut self) -> FEN27_W<27> { + FEN27_W::new(self) + } + #[doc = "Bit 28 - Falling edge enabled 28"] + #[inline(always)] + #[must_use] + pub fn fen28(&mut self) -> FEN28_W<28> { + FEN28_W::new(self) + } + #[doc = "Bit 29 - Falling edge enabled 29"] + #[inline(always)] + #[must_use] + pub fn fen29(&mut self) -> FEN29_W<29> { + FEN29_W::new(self) + } + #[doc = "Bit 30 - Falling edge enabled 30"] + #[inline(always)] + #[must_use] + pub fn fen30(&mut self) -> FEN30_W<30> { + FEN30_W::new(self) + } + #[doc = "Bit 31 - Falling edge enabled 31"] + #[inline(always)] + #[must_use] + pub fn fen31(&mut self) -> FEN31_W<31> { + FEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen0](index.html) module"] +pub struct GPFEN0_SPEC; +impl crate::RegisterSpec for GPFEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfen0::R](R) reader structure"] +impl crate::Readable for GPFEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfen0::W](W) writer structure"] +impl crate::Writable for GPFEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfen1.rs b/crates/bcm2711-lpa/src/gpio/gpfen1.rs new file mode 100644 index 0000000..9d3519c --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfen1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPFEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FEN32` reader - Falling edge enabled 32"] +pub type FEN32_R = crate::BitReader; +#[doc = "Field `FEN32` writer - Falling edge enabled 32"] +pub type FEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN33` reader - Falling edge enabled 33"] +pub type FEN33_R = crate::BitReader; +#[doc = "Field `FEN33` writer - Falling edge enabled 33"] +pub type FEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN34` reader - Falling edge enabled 34"] +pub type FEN34_R = crate::BitReader; +#[doc = "Field `FEN34` writer - Falling edge enabled 34"] +pub type FEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN35` reader - Falling edge enabled 35"] +pub type FEN35_R = crate::BitReader; +#[doc = "Field `FEN35` writer - Falling edge enabled 35"] +pub type FEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN36` reader - Falling edge enabled 36"] +pub type FEN36_R = crate::BitReader; +#[doc = "Field `FEN36` writer - Falling edge enabled 36"] +pub type FEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN37` reader - Falling edge enabled 37"] +pub type FEN37_R = crate::BitReader; +#[doc = "Field `FEN37` writer - Falling edge enabled 37"] +pub type FEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN38` reader - Falling edge enabled 38"] +pub type FEN38_R = crate::BitReader; +#[doc = "Field `FEN38` writer - Falling edge enabled 38"] +pub type FEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN39` reader - Falling edge enabled 39"] +pub type FEN39_R = crate::BitReader; +#[doc = "Field `FEN39` writer - Falling edge enabled 39"] +pub type FEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN40` reader - Falling edge enabled 40"] +pub type FEN40_R = crate::BitReader; +#[doc = "Field `FEN40` writer - Falling edge enabled 40"] +pub type FEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN41` reader - Falling edge enabled 41"] +pub type FEN41_R = crate::BitReader; +#[doc = "Field `FEN41` writer - Falling edge enabled 41"] +pub type FEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN42` reader - Falling edge enabled 42"] +pub type FEN42_R = crate::BitReader; +#[doc = "Field `FEN42` writer - Falling edge enabled 42"] +pub type FEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN43` reader - Falling edge enabled 43"] +pub type FEN43_R = crate::BitReader; +#[doc = "Field `FEN43` writer - Falling edge enabled 43"] +pub type FEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN44` reader - Falling edge enabled 44"] +pub type FEN44_R = crate::BitReader; +#[doc = "Field `FEN44` writer - Falling edge enabled 44"] +pub type FEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN45` reader - Falling edge enabled 45"] +pub type FEN45_R = crate::BitReader; +#[doc = "Field `FEN45` writer - Falling edge enabled 45"] +pub type FEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN46` reader - Falling edge enabled 46"] +pub type FEN46_R = crate::BitReader; +#[doc = "Field `FEN46` writer - Falling edge enabled 46"] +pub type FEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN47` reader - Falling edge enabled 47"] +pub type FEN47_R = crate::BitReader; +#[doc = "Field `FEN47` writer - Falling edge enabled 47"] +pub type FEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN48` reader - Falling edge enabled 48"] +pub type FEN48_R = crate::BitReader; +#[doc = "Field `FEN48` writer - Falling edge enabled 48"] +pub type FEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN49` reader - Falling edge enabled 49"] +pub type FEN49_R = crate::BitReader; +#[doc = "Field `FEN49` writer - Falling edge enabled 49"] +pub type FEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN50` reader - Falling edge enabled 50"] +pub type FEN50_R = crate::BitReader; +#[doc = "Field `FEN50` writer - Falling edge enabled 50"] +pub type FEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN51` reader - Falling edge enabled 51"] +pub type FEN51_R = crate::BitReader; +#[doc = "Field `FEN51` writer - Falling edge enabled 51"] +pub type FEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN52` reader - Falling edge enabled 52"] +pub type FEN52_R = crate::BitReader; +#[doc = "Field `FEN52` writer - Falling edge enabled 52"] +pub type FEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN53` reader - Falling edge enabled 53"] +pub type FEN53_R = crate::BitReader; +#[doc = "Field `FEN53` writer - Falling edge enabled 53"] +pub type FEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN54` reader - Falling edge enabled 54"] +pub type FEN54_R = crate::BitReader; +#[doc = "Field `FEN54` writer - Falling edge enabled 54"] +pub type FEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN55` reader - Falling edge enabled 55"] +pub type FEN55_R = crate::BitReader; +#[doc = "Field `FEN55` writer - Falling edge enabled 55"] +pub type FEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN56` reader - Falling edge enabled 56"] +pub type FEN56_R = crate::BitReader; +#[doc = "Field `FEN56` writer - Falling edge enabled 56"] +pub type FEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN57` reader - Falling edge enabled 57"] +pub type FEN57_R = crate::BitReader; +#[doc = "Field `FEN57` writer - Falling edge enabled 57"] +pub type FEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Falling edge enabled 32"] + #[inline(always)] + pub fn fen32(&self) -> FEN32_R { + FEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling edge enabled 33"] + #[inline(always)] + pub fn fen33(&self) -> FEN33_R { + FEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Falling edge enabled 34"] + #[inline(always)] + pub fn fen34(&self) -> FEN34_R { + FEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Falling edge enabled 35"] + #[inline(always)] + pub fn fen35(&self) -> FEN35_R { + FEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling edge enabled 36"] + #[inline(always)] + pub fn fen36(&self) -> FEN36_R { + FEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Falling edge enabled 37"] + #[inline(always)] + pub fn fen37(&self) -> FEN37_R { + FEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Falling edge enabled 38"] + #[inline(always)] + pub fn fen38(&self) -> FEN38_R { + FEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling edge enabled 39"] + #[inline(always)] + pub fn fen39(&self) -> FEN39_R { + FEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Falling edge enabled 40"] + #[inline(always)] + pub fn fen40(&self) -> FEN40_R { + FEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Falling edge enabled 41"] + #[inline(always)] + pub fn fen41(&self) -> FEN41_R { + FEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling edge enabled 42"] + #[inline(always)] + pub fn fen42(&self) -> FEN42_R { + FEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Falling edge enabled 43"] + #[inline(always)] + pub fn fen43(&self) -> FEN43_R { + FEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Falling edge enabled 44"] + #[inline(always)] + pub fn fen44(&self) -> FEN44_R { + FEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Falling edge enabled 45"] + #[inline(always)] + pub fn fen45(&self) -> FEN45_R { + FEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Falling edge enabled 46"] + #[inline(always)] + pub fn fen46(&self) -> FEN46_R { + FEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Falling edge enabled 47"] + #[inline(always)] + pub fn fen47(&self) -> FEN47_R { + FEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Falling edge enabled 48"] + #[inline(always)] + pub fn fen48(&self) -> FEN48_R { + FEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Falling edge enabled 49"] + #[inline(always)] + pub fn fen49(&self) -> FEN49_R { + FEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Falling edge enabled 50"] + #[inline(always)] + pub fn fen50(&self) -> FEN50_R { + FEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Falling edge enabled 51"] + #[inline(always)] + pub fn fen51(&self) -> FEN51_R { + FEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Falling edge enabled 52"] + #[inline(always)] + pub fn fen52(&self) -> FEN52_R { + FEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Falling edge enabled 53"] + #[inline(always)] + pub fn fen53(&self) -> FEN53_R { + FEN53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Falling edge enabled 54"] + #[inline(always)] + pub fn fen54(&self) -> FEN54_R { + FEN54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Falling edge enabled 55"] + #[inline(always)] + pub fn fen55(&self) -> FEN55_R { + FEN55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Falling edge enabled 56"] + #[inline(always)] + pub fn fen56(&self) -> FEN56_R { + FEN56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Falling edge enabled 57"] + #[inline(always)] + pub fn fen57(&self) -> FEN57_R { + FEN57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Falling edge enabled 32"] + #[inline(always)] + #[must_use] + pub fn fen32(&mut self) -> FEN32_W<0> { + FEN32_W::new(self) + } + #[doc = "Bit 1 - Falling edge enabled 33"] + #[inline(always)] + #[must_use] + pub fn fen33(&mut self) -> FEN33_W<1> { + FEN33_W::new(self) + } + #[doc = "Bit 2 - Falling edge enabled 34"] + #[inline(always)] + #[must_use] + pub fn fen34(&mut self) -> FEN34_W<2> { + FEN34_W::new(self) + } + #[doc = "Bit 3 - Falling edge enabled 35"] + #[inline(always)] + #[must_use] + pub fn fen35(&mut self) -> FEN35_W<3> { + FEN35_W::new(self) + } + #[doc = "Bit 4 - Falling edge enabled 36"] + #[inline(always)] + #[must_use] + pub fn fen36(&mut self) -> FEN36_W<4> { + FEN36_W::new(self) + } + #[doc = "Bit 5 - Falling edge enabled 37"] + #[inline(always)] + #[must_use] + pub fn fen37(&mut self) -> FEN37_W<5> { + FEN37_W::new(self) + } + #[doc = "Bit 6 - Falling edge enabled 38"] + #[inline(always)] + #[must_use] + pub fn fen38(&mut self) -> FEN38_W<6> { + FEN38_W::new(self) + } + #[doc = "Bit 7 - Falling edge enabled 39"] + #[inline(always)] + #[must_use] + pub fn fen39(&mut self) -> FEN39_W<7> { + FEN39_W::new(self) + } + #[doc = "Bit 8 - Falling edge enabled 40"] + #[inline(always)] + #[must_use] + pub fn fen40(&mut self) -> FEN40_W<8> { + FEN40_W::new(self) + } + #[doc = "Bit 9 - Falling edge enabled 41"] + #[inline(always)] + #[must_use] + pub fn fen41(&mut self) -> FEN41_W<9> { + FEN41_W::new(self) + } + #[doc = "Bit 10 - Falling edge enabled 42"] + #[inline(always)] + #[must_use] + pub fn fen42(&mut self) -> FEN42_W<10> { + FEN42_W::new(self) + } + #[doc = "Bit 11 - Falling edge enabled 43"] + #[inline(always)] + #[must_use] + pub fn fen43(&mut self) -> FEN43_W<11> { + FEN43_W::new(self) + } + #[doc = "Bit 12 - Falling edge enabled 44"] + #[inline(always)] + #[must_use] + pub fn fen44(&mut self) -> FEN44_W<12> { + FEN44_W::new(self) + } + #[doc = "Bit 13 - Falling edge enabled 45"] + #[inline(always)] + #[must_use] + pub fn fen45(&mut self) -> FEN45_W<13> { + FEN45_W::new(self) + } + #[doc = "Bit 14 - Falling edge enabled 46"] + #[inline(always)] + #[must_use] + pub fn fen46(&mut self) -> FEN46_W<14> { + FEN46_W::new(self) + } + #[doc = "Bit 15 - Falling edge enabled 47"] + #[inline(always)] + #[must_use] + pub fn fen47(&mut self) -> FEN47_W<15> { + FEN47_W::new(self) + } + #[doc = "Bit 16 - Falling edge enabled 48"] + #[inline(always)] + #[must_use] + pub fn fen48(&mut self) -> FEN48_W<16> { + FEN48_W::new(self) + } + #[doc = "Bit 17 - Falling edge enabled 49"] + #[inline(always)] + #[must_use] + pub fn fen49(&mut self) -> FEN49_W<17> { + FEN49_W::new(self) + } + #[doc = "Bit 18 - Falling edge enabled 50"] + #[inline(always)] + #[must_use] + pub fn fen50(&mut self) -> FEN50_W<18> { + FEN50_W::new(self) + } + #[doc = "Bit 19 - Falling edge enabled 51"] + #[inline(always)] + #[must_use] + pub fn fen51(&mut self) -> FEN51_W<19> { + FEN51_W::new(self) + } + #[doc = "Bit 20 - Falling edge enabled 52"] + #[inline(always)] + #[must_use] + pub fn fen52(&mut self) -> FEN52_W<20> { + FEN52_W::new(self) + } + #[doc = "Bit 21 - Falling edge enabled 53"] + #[inline(always)] + #[must_use] + pub fn fen53(&mut self) -> FEN53_W<21> { + FEN53_W::new(self) + } + #[doc = "Bit 22 - Falling edge enabled 54"] + #[inline(always)] + #[must_use] + pub fn fen54(&mut self) -> FEN54_W<22> { + FEN54_W::new(self) + } + #[doc = "Bit 23 - Falling edge enabled 55"] + #[inline(always)] + #[must_use] + pub fn fen55(&mut self) -> FEN55_W<23> { + FEN55_W::new(self) + } + #[doc = "Bit 24 - Falling edge enabled 56"] + #[inline(always)] + #[must_use] + pub fn fen56(&mut self) -> FEN56_W<24> { + FEN56_W::new(self) + } + #[doc = "Bit 25 - Falling edge enabled 57"] + #[inline(always)] + #[must_use] + pub fn fen57(&mut self) -> FEN57_W<25> { + FEN57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen1](index.html) module"] +pub struct GPFEN1_SPEC; +impl crate::RegisterSpec for GPFEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfen1::R](R) reader structure"] +impl crate::Readable for GPFEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfen1::W](W) writer structure"] +impl crate::Writable for GPFEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel0.rs b/crates/bcm2711-lpa/src/gpio/gpfsel0.rs new file mode 100644 index 0000000..2d16733 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfsel0.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL0` reader - Function Select 0"] +pub type FSEL0_R = crate::FieldReader; +#[doc = "Function Select 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL0_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA0"] + SDA0 = 4, + #[doc = "5: Pin is connected to SA5"] + SA5 = 5, + #[doc = "6: Pin is connected to PCLK"] + PCLK = 6, + #[doc = "7: Pin is connected to SPI3_CE0_N"] + SPI3_CE0_N = 7, + #[doc = "3: Pin is connected to TXD2"] + TXD2 = 3, + #[doc = "2: Pin is connected to SDA6"] + SDA6 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL0_A) -> Self { + variant as _ + } +} +impl FSEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL0_A { + match self.bits { + 0 => FSEL0_A::INPUT, + 1 => FSEL0_A::OUTPUT, + 4 => FSEL0_A::SDA0, + 5 => FSEL0_A::SA5, + 6 => FSEL0_A::PCLK, + 7 => FSEL0_A::SPI3_CE0_N, + 3 => FSEL0_A::TXD2, + 2 => FSEL0_A::SDA6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL0_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL0_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL0_A::SDA0 + } + #[doc = "Checks if the value of the field is `SA5`"] + #[inline(always)] + pub fn is_sa5(&self) -> bool { + *self == FSEL0_A::SA5 + } + #[doc = "Checks if the value of the field is `PCLK`"] + #[inline(always)] + pub fn is_pclk(&self) -> bool { + *self == FSEL0_A::PCLK + } + #[doc = "Checks if the value of the field is `SPI3_CE0_N`"] + #[inline(always)] + pub fn is_spi3_ce0_n(&self) -> bool { + *self == FSEL0_A::SPI3_CE0_N + } + #[doc = "Checks if the value of the field is `TXD2`"] + #[inline(always)] + pub fn is_txd2(&self) -> bool { + *self == FSEL0_A::TXD2 + } + #[doc = "Checks if the value of the field is `SDA6`"] + #[inline(always)] + pub fn is_sda6(&self) -> bool { + *self == FSEL0_A::SDA6 + } +} +#[doc = "Field `FSEL0` writer - Function Select 0"] +pub type FSEL0_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL0_A, 3, O>; +impl<'a, const O: u8> FSEL0_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL0_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL0_A::OUTPUT) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL0_A::SDA0) + } + #[doc = "Pin is connected to SA5"] + #[inline(always)] + pub fn sa5(self) -> &'a mut W { + self.variant(FSEL0_A::SA5) + } + #[doc = "Pin is connected to PCLK"] + #[inline(always)] + pub fn pclk(self) -> &'a mut W { + self.variant(FSEL0_A::PCLK) + } + #[doc = "Pin is connected to SPI3_CE0_N"] + #[inline(always)] + pub fn spi3_ce0_n(self) -> &'a mut W { + self.variant(FSEL0_A::SPI3_CE0_N) + } + #[doc = "Pin is connected to TXD2"] + #[inline(always)] + pub fn txd2(self) -> &'a mut W { + self.variant(FSEL0_A::TXD2) + } + #[doc = "Pin is connected to SDA6"] + #[inline(always)] + pub fn sda6(self) -> &'a mut W { + self.variant(FSEL0_A::SDA6) + } +} +#[doc = "Field `FSEL1` reader - Function Select 1"] +pub type FSEL1_R = crate::FieldReader; +#[doc = "Function Select 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL1_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL0"] + SCL0 = 4, + #[doc = "5: Pin is connected to SA4"] + SA4 = 5, + #[doc = "6: Pin is connected to DE"] + DE = 6, + #[doc = "7: Pin is connected to SPI3_MISO"] + SPI3_MISO = 7, + #[doc = "3: Pin is connected to RXD2"] + RXD2 = 3, + #[doc = "2: Pin is connected to SCL6"] + SCL6 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL1_A) -> Self { + variant as _ + } +} +impl FSEL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL1_A { + match self.bits { + 0 => FSEL1_A::INPUT, + 1 => FSEL1_A::OUTPUT, + 4 => FSEL1_A::SCL0, + 5 => FSEL1_A::SA4, + 6 => FSEL1_A::DE, + 7 => FSEL1_A::SPI3_MISO, + 3 => FSEL1_A::RXD2, + 2 => FSEL1_A::SCL6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL1_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL1_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL1_A::SCL0 + } + #[doc = "Checks if the value of the field is `SA4`"] + #[inline(always)] + pub fn is_sa4(&self) -> bool { + *self == FSEL1_A::SA4 + } + #[doc = "Checks if the value of the field is `DE`"] + #[inline(always)] + pub fn is_de(&self) -> bool { + *self == FSEL1_A::DE + } + #[doc = "Checks if the value of the field is `SPI3_MISO`"] + #[inline(always)] + pub fn is_spi3_miso(&self) -> bool { + *self == FSEL1_A::SPI3_MISO + } + #[doc = "Checks if the value of the field is `RXD2`"] + #[inline(always)] + pub fn is_rxd2(&self) -> bool { + *self == FSEL1_A::RXD2 + } + #[doc = "Checks if the value of the field is `SCL6`"] + #[inline(always)] + pub fn is_scl6(&self) -> bool { + *self == FSEL1_A::SCL6 + } +} +#[doc = "Field `FSEL1` writer - Function Select 1"] +pub type FSEL1_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL1_A, 3, O>; +impl<'a, const O: u8> FSEL1_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL1_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL1_A::OUTPUT) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL1_A::SCL0) + } + #[doc = "Pin is connected to SA4"] + #[inline(always)] + pub fn sa4(self) -> &'a mut W { + self.variant(FSEL1_A::SA4) + } + #[doc = "Pin is connected to DE"] + #[inline(always)] + pub fn de(self) -> &'a mut W { + self.variant(FSEL1_A::DE) + } + #[doc = "Pin is connected to SPI3_MISO"] + #[inline(always)] + pub fn spi3_miso(self) -> &'a mut W { + self.variant(FSEL1_A::SPI3_MISO) + } + #[doc = "Pin is connected to RXD2"] + #[inline(always)] + pub fn rxd2(self) -> &'a mut W { + self.variant(FSEL1_A::RXD2) + } + #[doc = "Pin is connected to SCL6"] + #[inline(always)] + pub fn scl6(self) -> &'a mut W { + self.variant(FSEL1_A::SCL6) + } +} +#[doc = "Field `FSEL2` reader - Function Select 2"] +pub type FSEL2_R = crate::FieldReader; +#[doc = "Function Select 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL2_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA1"] + SDA1 = 4, + #[doc = "5: Pin is connected to SA3"] + SA3 = 5, + #[doc = "6: Pin is connected to LCD_VSYNC"] + LCD_VSYNC = 6, + #[doc = "7: Pin is connected to SPI3_MOSI"] + SPI3_MOSI = 7, + #[doc = "3: Pin is connected to CTS2"] + CTS2 = 3, + #[doc = "2: Pin is connected to SDA3"] + SDA3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL2_A) -> Self { + variant as _ + } +} +impl FSEL2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL2_A { + match self.bits { + 0 => FSEL2_A::INPUT, + 1 => FSEL2_A::OUTPUT, + 4 => FSEL2_A::SDA1, + 5 => FSEL2_A::SA3, + 6 => FSEL2_A::LCD_VSYNC, + 7 => FSEL2_A::SPI3_MOSI, + 3 => FSEL2_A::CTS2, + 2 => FSEL2_A::SDA3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL2_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL2_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA1`"] + #[inline(always)] + pub fn is_sda1(&self) -> bool { + *self == FSEL2_A::SDA1 + } + #[doc = "Checks if the value of the field is `SA3`"] + #[inline(always)] + pub fn is_sa3(&self) -> bool { + *self == FSEL2_A::SA3 + } + #[doc = "Checks if the value of the field is `LCD_VSYNC`"] + #[inline(always)] + pub fn is_lcd_vsync(&self) -> bool { + *self == FSEL2_A::LCD_VSYNC + } + #[doc = "Checks if the value of the field is `SPI3_MOSI`"] + #[inline(always)] + pub fn is_spi3_mosi(&self) -> bool { + *self == FSEL2_A::SPI3_MOSI + } + #[doc = "Checks if the value of the field is `CTS2`"] + #[inline(always)] + pub fn is_cts2(&self) -> bool { + *self == FSEL2_A::CTS2 + } + #[doc = "Checks if the value of the field is `SDA3`"] + #[inline(always)] + pub fn is_sda3(&self) -> bool { + *self == FSEL2_A::SDA3 + } +} +#[doc = "Field `FSEL2` writer - Function Select 2"] +pub type FSEL2_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL2_A, 3, O>; +impl<'a, const O: u8> FSEL2_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL2_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL2_A::OUTPUT) + } + #[doc = "Pin is connected to SDA1"] + #[inline(always)] + pub fn sda1(self) -> &'a mut W { + self.variant(FSEL2_A::SDA1) + } + #[doc = "Pin is connected to SA3"] + #[inline(always)] + pub fn sa3(self) -> &'a mut W { + self.variant(FSEL2_A::SA3) + } + #[doc = "Pin is connected to LCD_VSYNC"] + #[inline(always)] + pub fn lcd_vsync(self) -> &'a mut W { + self.variant(FSEL2_A::LCD_VSYNC) + } + #[doc = "Pin is connected to SPI3_MOSI"] + #[inline(always)] + pub fn spi3_mosi(self) -> &'a mut W { + self.variant(FSEL2_A::SPI3_MOSI) + } + #[doc = "Pin is connected to CTS2"] + #[inline(always)] + pub fn cts2(self) -> &'a mut W { + self.variant(FSEL2_A::CTS2) + } + #[doc = "Pin is connected to SDA3"] + #[inline(always)] + pub fn sda3(self) -> &'a mut W { + self.variant(FSEL2_A::SDA3) + } +} +#[doc = "Field `FSEL3` reader - Function Select 3"] +pub type FSEL3_R = crate::FieldReader; +#[doc = "Function Select 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL3_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL1"] + SCL1 = 4, + #[doc = "5: Pin is connected to SA2"] + SA2 = 5, + #[doc = "6: Pin is connected to LCD_HSYNC"] + LCD_HSYNC = 6, + #[doc = "7: Pin is connected to SPI3_SCLK"] + SPI3_SCLK = 7, + #[doc = "3: Pin is connected to RTS2"] + RTS2 = 3, + #[doc = "2: Pin is connected to SCL3"] + SCL3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL3_A) -> Self { + variant as _ + } +} +impl FSEL3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL3_A { + match self.bits { + 0 => FSEL3_A::INPUT, + 1 => FSEL3_A::OUTPUT, + 4 => FSEL3_A::SCL1, + 5 => FSEL3_A::SA2, + 6 => FSEL3_A::LCD_HSYNC, + 7 => FSEL3_A::SPI3_SCLK, + 3 => FSEL3_A::RTS2, + 2 => FSEL3_A::SCL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL3_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL3_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL1`"] + #[inline(always)] + pub fn is_scl1(&self) -> bool { + *self == FSEL3_A::SCL1 + } + #[doc = "Checks if the value of the field is `SA2`"] + #[inline(always)] + pub fn is_sa2(&self) -> bool { + *self == FSEL3_A::SA2 + } + #[doc = "Checks if the value of the field is `LCD_HSYNC`"] + #[inline(always)] + pub fn is_lcd_hsync(&self) -> bool { + *self == FSEL3_A::LCD_HSYNC + } + #[doc = "Checks if the value of the field is `SPI3_SCLK`"] + #[inline(always)] + pub fn is_spi3_sclk(&self) -> bool { + *self == FSEL3_A::SPI3_SCLK + } + #[doc = "Checks if the value of the field is `RTS2`"] + #[inline(always)] + pub fn is_rts2(&self) -> bool { + *self == FSEL3_A::RTS2 + } + #[doc = "Checks if the value of the field is `SCL3`"] + #[inline(always)] + pub fn is_scl3(&self) -> bool { + *self == FSEL3_A::SCL3 + } +} +#[doc = "Field `FSEL3` writer - Function Select 3"] +pub type FSEL3_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL3_A, 3, O>; +impl<'a, const O: u8> FSEL3_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL3_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL3_A::OUTPUT) + } + #[doc = "Pin is connected to SCL1"] + #[inline(always)] + pub fn scl1(self) -> &'a mut W { + self.variant(FSEL3_A::SCL1) + } + #[doc = "Pin is connected to SA2"] + #[inline(always)] + pub fn sa2(self) -> &'a mut W { + self.variant(FSEL3_A::SA2) + } + #[doc = "Pin is connected to LCD_HSYNC"] + #[inline(always)] + pub fn lcd_hsync(self) -> &'a mut W { + self.variant(FSEL3_A::LCD_HSYNC) + } + #[doc = "Pin is connected to SPI3_SCLK"] + #[inline(always)] + pub fn spi3_sclk(self) -> &'a mut W { + self.variant(FSEL3_A::SPI3_SCLK) + } + #[doc = "Pin is connected to RTS2"] + #[inline(always)] + pub fn rts2(self) -> &'a mut W { + self.variant(FSEL3_A::RTS2) + } + #[doc = "Pin is connected to SCL3"] + #[inline(always)] + pub fn scl3(self) -> &'a mut W { + self.variant(FSEL3_A::SCL3) + } +} +#[doc = "Field `FSEL4` reader - Function Select 4"] +pub type FSEL4_R = crate::FieldReader; +#[doc = "Function Select 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL4_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SA1"] + SA1 = 5, + #[doc = "6: Pin is connected to DPI_D0"] + DPI_D0 = 6, + #[doc = "7: Pin is connected to SPI4_CE0_N"] + SPI4_CE0_N = 7, + #[doc = "3: Pin is connected to TXD3"] + TXD3 = 3, + #[doc = "2: Pin is connected to SDA3"] + SDA3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL4_A) -> Self { + variant as _ + } +} +impl FSEL4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL4_A { + match self.bits { + 0 => FSEL4_A::INPUT, + 1 => FSEL4_A::OUTPUT, + 4 => FSEL4_A::GPCLK0, + 5 => FSEL4_A::SA1, + 6 => FSEL4_A::DPI_D0, + 7 => FSEL4_A::SPI4_CE0_N, + 3 => FSEL4_A::TXD3, + 2 => FSEL4_A::SDA3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL4_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL4_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL4_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SA1`"] + #[inline(always)] + pub fn is_sa1(&self) -> bool { + *self == FSEL4_A::SA1 + } + #[doc = "Checks if the value of the field is `DPI_D0`"] + #[inline(always)] + pub fn is_dpi_d0(&self) -> bool { + *self == FSEL4_A::DPI_D0 + } + #[doc = "Checks if the value of the field is `SPI4_CE0_N`"] + #[inline(always)] + pub fn is_spi4_ce0_n(&self) -> bool { + *self == FSEL4_A::SPI4_CE0_N + } + #[doc = "Checks if the value of the field is `TXD3`"] + #[inline(always)] + pub fn is_txd3(&self) -> bool { + *self == FSEL4_A::TXD3 + } + #[doc = "Checks if the value of the field is `SDA3`"] + #[inline(always)] + pub fn is_sda3(&self) -> bool { + *self == FSEL4_A::SDA3 + } +} +#[doc = "Field `FSEL4` writer - Function Select 4"] +pub type FSEL4_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL4_A, 3, O>; +impl<'a, const O: u8> FSEL4_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL4_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL4_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL4_A::GPCLK0) + } + #[doc = "Pin is connected to SA1"] + #[inline(always)] + pub fn sa1(self) -> &'a mut W { + self.variant(FSEL4_A::SA1) + } + #[doc = "Pin is connected to DPI_D0"] + #[inline(always)] + pub fn dpi_d0(self) -> &'a mut W { + self.variant(FSEL4_A::DPI_D0) + } + #[doc = "Pin is connected to SPI4_CE0_N"] + #[inline(always)] + pub fn spi4_ce0_n(self) -> &'a mut W { + self.variant(FSEL4_A::SPI4_CE0_N) + } + #[doc = "Pin is connected to TXD3"] + #[inline(always)] + pub fn txd3(self) -> &'a mut W { + self.variant(FSEL4_A::TXD3) + } + #[doc = "Pin is connected to SDA3"] + #[inline(always)] + pub fn sda3(self) -> &'a mut W { + self.variant(FSEL4_A::SDA3) + } +} +#[doc = "Field `FSEL5` reader - Function Select 5"] +pub type FSEL5_R = crate::FieldReader; +#[doc = "Function Select 5"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL5_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SA0"] + SA0 = 5, + #[doc = "6: Pin is connected to DPI_D1"] + DPI_D1 = 6, + #[doc = "7: Pin is connected to SPI4_MISO"] + SPI4_MISO = 7, + #[doc = "3: Pin is connected to RXD3"] + RXD3 = 3, + #[doc = "2: Pin is connected to SCL3"] + SCL3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL5_A) -> Self { + variant as _ + } +} +impl FSEL5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL5_A { + match self.bits { + 0 => FSEL5_A::INPUT, + 1 => FSEL5_A::OUTPUT, + 4 => FSEL5_A::GPCLK1, + 5 => FSEL5_A::SA0, + 6 => FSEL5_A::DPI_D1, + 7 => FSEL5_A::SPI4_MISO, + 3 => FSEL5_A::RXD3, + 2 => FSEL5_A::SCL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL5_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL5_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL5_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SA0`"] + #[inline(always)] + pub fn is_sa0(&self) -> bool { + *self == FSEL5_A::SA0 + } + #[doc = "Checks if the value of the field is `DPI_D1`"] + #[inline(always)] + pub fn is_dpi_d1(&self) -> bool { + *self == FSEL5_A::DPI_D1 + } + #[doc = "Checks if the value of the field is `SPI4_MISO`"] + #[inline(always)] + pub fn is_spi4_miso(&self) -> bool { + *self == FSEL5_A::SPI4_MISO + } + #[doc = "Checks if the value of the field is `RXD3`"] + #[inline(always)] + pub fn is_rxd3(&self) -> bool { + *self == FSEL5_A::RXD3 + } + #[doc = "Checks if the value of the field is `SCL3`"] + #[inline(always)] + pub fn is_scl3(&self) -> bool { + *self == FSEL5_A::SCL3 + } +} +#[doc = "Field `FSEL5` writer - Function Select 5"] +pub type FSEL5_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL5_A, 3, O>; +impl<'a, const O: u8> FSEL5_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL5_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL5_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL5_A::GPCLK1) + } + #[doc = "Pin is connected to SA0"] + #[inline(always)] + pub fn sa0(self) -> &'a mut W { + self.variant(FSEL5_A::SA0) + } + #[doc = "Pin is connected to DPI_D1"] + #[inline(always)] + pub fn dpi_d1(self) -> &'a mut W { + self.variant(FSEL5_A::DPI_D1) + } + #[doc = "Pin is connected to SPI4_MISO"] + #[inline(always)] + pub fn spi4_miso(self) -> &'a mut W { + self.variant(FSEL5_A::SPI4_MISO) + } + #[doc = "Pin is connected to RXD3"] + #[inline(always)] + pub fn rxd3(self) -> &'a mut W { + self.variant(FSEL5_A::RXD3) + } + #[doc = "Pin is connected to SCL3"] + #[inline(always)] + pub fn scl3(self) -> &'a mut W { + self.variant(FSEL5_A::SCL3) + } +} +#[doc = "Field `FSEL6` reader - Function Select 6"] +pub type FSEL6_R = crate::FieldReader; +#[doc = "Function Select 6"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL6_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK2"] + GPCLK2 = 4, + #[doc = "5: Pin is connected to SOE_N"] + SOE_N = 5, + #[doc = "6: Pin is connected to DPI_D2"] + DPI_D2 = 6, + #[doc = "7: Pin is connected to SPI4_MOSI"] + SPI4_MOSI = 7, + #[doc = "3: Pin is connected to CTS3"] + CTS3 = 3, + #[doc = "2: Pin is connected to SDA4"] + SDA4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL6_A) -> Self { + variant as _ + } +} +impl FSEL6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL6_A { + match self.bits { + 0 => FSEL6_A::INPUT, + 1 => FSEL6_A::OUTPUT, + 4 => FSEL6_A::GPCLK2, + 5 => FSEL6_A::SOE_N, + 6 => FSEL6_A::DPI_D2, + 7 => FSEL6_A::SPI4_MOSI, + 3 => FSEL6_A::CTS3, + 2 => FSEL6_A::SDA4, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL6_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL6_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK2`"] + #[inline(always)] + pub fn is_gpclk2(&self) -> bool { + *self == FSEL6_A::GPCLK2 + } + #[doc = "Checks if the value of the field is `SOE_N`"] + #[inline(always)] + pub fn is_soe_n(&self) -> bool { + *self == FSEL6_A::SOE_N + } + #[doc = "Checks if the value of the field is `DPI_D2`"] + #[inline(always)] + pub fn is_dpi_d2(&self) -> bool { + *self == FSEL6_A::DPI_D2 + } + #[doc = "Checks if the value of the field is `SPI4_MOSI`"] + #[inline(always)] + pub fn is_spi4_mosi(&self) -> bool { + *self == FSEL6_A::SPI4_MOSI + } + #[doc = "Checks if the value of the field is `CTS3`"] + #[inline(always)] + pub fn is_cts3(&self) -> bool { + *self == FSEL6_A::CTS3 + } + #[doc = "Checks if the value of the field is `SDA4`"] + #[inline(always)] + pub fn is_sda4(&self) -> bool { + *self == FSEL6_A::SDA4 + } +} +#[doc = "Field `FSEL6` writer - Function Select 6"] +pub type FSEL6_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL6_A, 3, O>; +impl<'a, const O: u8> FSEL6_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL6_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL6_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK2"] + #[inline(always)] + pub fn gpclk2(self) -> &'a mut W { + self.variant(FSEL6_A::GPCLK2) + } + #[doc = "Pin is connected to SOE_N"] + #[inline(always)] + pub fn soe_n(self) -> &'a mut W { + self.variant(FSEL6_A::SOE_N) + } + #[doc = "Pin is connected to DPI_D2"] + #[inline(always)] + pub fn dpi_d2(self) -> &'a mut W { + self.variant(FSEL6_A::DPI_D2) + } + #[doc = "Pin is connected to SPI4_MOSI"] + #[inline(always)] + pub fn spi4_mosi(self) -> &'a mut W { + self.variant(FSEL6_A::SPI4_MOSI) + } + #[doc = "Pin is connected to CTS3"] + #[inline(always)] + pub fn cts3(self) -> &'a mut W { + self.variant(FSEL6_A::CTS3) + } + #[doc = "Pin is connected to SDA4"] + #[inline(always)] + pub fn sda4(self) -> &'a mut W { + self.variant(FSEL6_A::SDA4) + } +} +#[doc = "Field `FSEL7` reader - Function Select 7"] +pub type FSEL7_R = crate::FieldReader; +#[doc = "Function Select 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL7_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE1_N"] + SPI0_CE1_N = 4, + #[doc = "5: Pin is connected to SWE_N"] + SWE_N = 5, + #[doc = "6: Pin is connected to DPI_D3"] + DPI_D3 = 6, + #[doc = "7: Pin is connected to SPI4_SCLK"] + SPI4_SCLK = 7, + #[doc = "3: Pin is connected to RTS3"] + RTS3 = 3, + #[doc = "2: Pin is connected to SCL4"] + SCL4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL7_A) -> Self { + variant as _ + } +} +impl FSEL7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL7_A { + match self.bits { + 0 => FSEL7_A::INPUT, + 1 => FSEL7_A::OUTPUT, + 4 => FSEL7_A::SPI0_CE1_N, + 5 => FSEL7_A::SWE_N, + 6 => FSEL7_A::DPI_D3, + 7 => FSEL7_A::SPI4_SCLK, + 3 => FSEL7_A::RTS3, + 2 => FSEL7_A::SCL4, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL7_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL7_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[inline(always)] + pub fn is_spi0_ce1_n(&self) -> bool { + *self == FSEL7_A::SPI0_CE1_N + } + #[doc = "Checks if the value of the field is `SWE_N`"] + #[inline(always)] + pub fn is_swe_n(&self) -> bool { + *self == FSEL7_A::SWE_N + } + #[doc = "Checks if the value of the field is `DPI_D3`"] + #[inline(always)] + pub fn is_dpi_d3(&self) -> bool { + *self == FSEL7_A::DPI_D3 + } + #[doc = "Checks if the value of the field is `SPI4_SCLK`"] + #[inline(always)] + pub fn is_spi4_sclk(&self) -> bool { + *self == FSEL7_A::SPI4_SCLK + } + #[doc = "Checks if the value of the field is `RTS3`"] + #[inline(always)] + pub fn is_rts3(&self) -> bool { + *self == FSEL7_A::RTS3 + } + #[doc = "Checks if the value of the field is `SCL4`"] + #[inline(always)] + pub fn is_scl4(&self) -> bool { + *self == FSEL7_A::SCL4 + } +} +#[doc = "Field `FSEL7` writer - Function Select 7"] +pub type FSEL7_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL7_A, 3, O>; +impl<'a, const O: u8> FSEL7_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL7_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL7_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE1_N"] + #[inline(always)] + pub fn spi0_ce1_n(self) -> &'a mut W { + self.variant(FSEL7_A::SPI0_CE1_N) + } + #[doc = "Pin is connected to SWE_N"] + #[inline(always)] + pub fn swe_n(self) -> &'a mut W { + self.variant(FSEL7_A::SWE_N) + } + #[doc = "Pin is connected to DPI_D3"] + #[inline(always)] + pub fn dpi_d3(self) -> &'a mut W { + self.variant(FSEL7_A::DPI_D3) + } + #[doc = "Pin is connected to SPI4_SCLK"] + #[inline(always)] + pub fn spi4_sclk(self) -> &'a mut W { + self.variant(FSEL7_A::SPI4_SCLK) + } + #[doc = "Pin is connected to RTS3"] + #[inline(always)] + pub fn rts3(self) -> &'a mut W { + self.variant(FSEL7_A::RTS3) + } + #[doc = "Pin is connected to SCL4"] + #[inline(always)] + pub fn scl4(self) -> &'a mut W { + self.variant(FSEL7_A::SCL4) + } +} +#[doc = "Field `FSEL8` reader - Function Select 8"] +pub type FSEL8_R = crate::FieldReader; +#[doc = "Function Select 8"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL8_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE0_N"] + SPI0_CE0_N = 4, + #[doc = "5: Pin is connected to SD0"] + SD0 = 5, + #[doc = "6: Pin is connected to DPI_D4"] + DPI_D4 = 6, + #[doc = "7: Pin is connected to BSCSL_CE_N"] + BSCSL_CE_N = 7, + #[doc = "3: Pin is connected to TXD4"] + TXD4 = 3, + #[doc = "2: Pin is connected to SDA4"] + SDA4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL8_A) -> Self { + variant as _ + } +} +impl FSEL8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL8_A { + match self.bits { + 0 => FSEL8_A::INPUT, + 1 => FSEL8_A::OUTPUT, + 4 => FSEL8_A::SPI0_CE0_N, + 5 => FSEL8_A::SD0, + 6 => FSEL8_A::DPI_D4, + 7 => FSEL8_A::BSCSL_CE_N, + 3 => FSEL8_A::TXD4, + 2 => FSEL8_A::SDA4, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL8_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL8_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[inline(always)] + pub fn is_spi0_ce0_n(&self) -> bool { + *self == FSEL8_A::SPI0_CE0_N + } + #[doc = "Checks if the value of the field is `SD0`"] + #[inline(always)] + pub fn is_sd0(&self) -> bool { + *self == FSEL8_A::SD0 + } + #[doc = "Checks if the value of the field is `DPI_D4`"] + #[inline(always)] + pub fn is_dpi_d4(&self) -> bool { + *self == FSEL8_A::DPI_D4 + } + #[doc = "Checks if the value of the field is `BSCSL_CE_N`"] + #[inline(always)] + pub fn is_bscsl_ce_n(&self) -> bool { + *self == FSEL8_A::BSCSL_CE_N + } + #[doc = "Checks if the value of the field is `TXD4`"] + #[inline(always)] + pub fn is_txd4(&self) -> bool { + *self == FSEL8_A::TXD4 + } + #[doc = "Checks if the value of the field is `SDA4`"] + #[inline(always)] + pub fn is_sda4(&self) -> bool { + *self == FSEL8_A::SDA4 + } +} +#[doc = "Field `FSEL8` writer - Function Select 8"] +pub type FSEL8_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL8_A, 3, O>; +impl<'a, const O: u8> FSEL8_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL8_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL8_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE0_N"] + #[inline(always)] + pub fn spi0_ce0_n(self) -> &'a mut W { + self.variant(FSEL8_A::SPI0_CE0_N) + } + #[doc = "Pin is connected to SD0"] + #[inline(always)] + pub fn sd0(self) -> &'a mut W { + self.variant(FSEL8_A::SD0) + } + #[doc = "Pin is connected to DPI_D4"] + #[inline(always)] + pub fn dpi_d4(self) -> &'a mut W { + self.variant(FSEL8_A::DPI_D4) + } + #[doc = "Pin is connected to BSCSL_CE_N"] + #[inline(always)] + pub fn bscsl_ce_n(self) -> &'a mut W { + self.variant(FSEL8_A::BSCSL_CE_N) + } + #[doc = "Pin is connected to TXD4"] + #[inline(always)] + pub fn txd4(self) -> &'a mut W { + self.variant(FSEL8_A::TXD4) + } + #[doc = "Pin is connected to SDA4"] + #[inline(always)] + pub fn sda4(self) -> &'a mut W { + self.variant(FSEL8_A::SDA4) + } +} +#[doc = "Field `FSEL9` reader - Function Select 9"] +pub type FSEL9_R = crate::FieldReader; +#[doc = "Function Select 9"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL9_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MISO"] + SPI0_MISO = 4, + #[doc = "5: Pin is connected to SD1"] + SD1 = 5, + #[doc = "6: Pin is connected to DPI_D5"] + DPI_D5 = 6, + #[doc = "7: Pin is connected to BSCSL_MISO"] + BSCSL_MISO = 7, + #[doc = "3: Pin is connected to RXD4"] + RXD4 = 3, + #[doc = "2: Pin is connected to SCL4"] + SCL4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL9_A) -> Self { + variant as _ + } +} +impl FSEL9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL9_A { + match self.bits { + 0 => FSEL9_A::INPUT, + 1 => FSEL9_A::OUTPUT, + 4 => FSEL9_A::SPI0_MISO, + 5 => FSEL9_A::SD1, + 6 => FSEL9_A::DPI_D5, + 7 => FSEL9_A::BSCSL_MISO, + 3 => FSEL9_A::RXD4, + 2 => FSEL9_A::SCL4, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL9_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL9_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[inline(always)] + pub fn is_spi0_miso(&self) -> bool { + *self == FSEL9_A::SPI0_MISO + } + #[doc = "Checks if the value of the field is `SD1`"] + #[inline(always)] + pub fn is_sd1(&self) -> bool { + *self == FSEL9_A::SD1 + } + #[doc = "Checks if the value of the field is `DPI_D5`"] + #[inline(always)] + pub fn is_dpi_d5(&self) -> bool { + *self == FSEL9_A::DPI_D5 + } + #[doc = "Checks if the value of the field is `BSCSL_MISO`"] + #[inline(always)] + pub fn is_bscsl_miso(&self) -> bool { + *self == FSEL9_A::BSCSL_MISO + } + #[doc = "Checks if the value of the field is `RXD4`"] + #[inline(always)] + pub fn is_rxd4(&self) -> bool { + *self == FSEL9_A::RXD4 + } + #[doc = "Checks if the value of the field is `SCL4`"] + #[inline(always)] + pub fn is_scl4(&self) -> bool { + *self == FSEL9_A::SCL4 + } +} +#[doc = "Field `FSEL9` writer - Function Select 9"] +pub type FSEL9_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL9_A, 3, O>; +impl<'a, const O: u8> FSEL9_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL9_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL9_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MISO"] + #[inline(always)] + pub fn spi0_miso(self) -> &'a mut W { + self.variant(FSEL9_A::SPI0_MISO) + } + #[doc = "Pin is connected to SD1"] + #[inline(always)] + pub fn sd1(self) -> &'a mut W { + self.variant(FSEL9_A::SD1) + } + #[doc = "Pin is connected to DPI_D5"] + #[inline(always)] + pub fn dpi_d5(self) -> &'a mut W { + self.variant(FSEL9_A::DPI_D5) + } + #[doc = "Pin is connected to BSCSL_MISO"] + #[inline(always)] + pub fn bscsl_miso(self) -> &'a mut W { + self.variant(FSEL9_A::BSCSL_MISO) + } + #[doc = "Pin is connected to RXD4"] + #[inline(always)] + pub fn rxd4(self) -> &'a mut W { + self.variant(FSEL9_A::RXD4) + } + #[doc = "Pin is connected to SCL4"] + #[inline(always)] + pub fn scl4(self) -> &'a mut W { + self.variant(FSEL9_A::SCL4) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 0"] + #[inline(always)] + pub fn fsel0(&self) -> FSEL0_R { + FSEL0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 1"] + #[inline(always)] + pub fn fsel1(&self) -> FSEL1_R { + FSEL1_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 2"] + #[inline(always)] + pub fn fsel2(&self) -> FSEL2_R { + FSEL2_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 3"] + #[inline(always)] + pub fn fsel3(&self) -> FSEL3_R { + FSEL3_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 4"] + #[inline(always)] + pub fn fsel4(&self) -> FSEL4_R { + FSEL4_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 5"] + #[inline(always)] + pub fn fsel5(&self) -> FSEL5_R { + FSEL5_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 6"] + #[inline(always)] + pub fn fsel6(&self) -> FSEL6_R { + FSEL6_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 7"] + #[inline(always)] + pub fn fsel7(&self) -> FSEL7_R { + FSEL7_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 8"] + #[inline(always)] + pub fn fsel8(&self) -> FSEL8_R { + FSEL8_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 9"] + #[inline(always)] + pub fn fsel9(&self) -> FSEL9_R { + FSEL9_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 0"] + #[inline(always)] + #[must_use] + pub fn fsel0(&mut self) -> FSEL0_W<0> { + FSEL0_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 1"] + #[inline(always)] + #[must_use] + pub fn fsel1(&mut self) -> FSEL1_W<3> { + FSEL1_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 2"] + #[inline(always)] + #[must_use] + pub fn fsel2(&mut self) -> FSEL2_W<6> { + FSEL2_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 3"] + #[inline(always)] + #[must_use] + pub fn fsel3(&mut self) -> FSEL3_W<9> { + FSEL3_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 4"] + #[inline(always)] + #[must_use] + pub fn fsel4(&mut self) -> FSEL4_W<12> { + FSEL4_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 5"] + #[inline(always)] + #[must_use] + pub fn fsel5(&mut self) -> FSEL5_W<15> { + FSEL5_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 6"] + #[inline(always)] + #[must_use] + pub fn fsel6(&mut self) -> FSEL6_W<18> { + FSEL6_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 7"] + #[inline(always)] + #[must_use] + pub fn fsel7(&mut self) -> FSEL7_W<21> { + FSEL7_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 8"] + #[inline(always)] + #[must_use] + pub fn fsel8(&mut self) -> FSEL8_W<24> { + FSEL8_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 9"] + #[inline(always)] + #[must_use] + pub fn fsel9(&mut self) -> FSEL9_W<27> { + FSEL9_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel0](index.html) module"] +pub struct GPFSEL0_SPEC; +impl crate::RegisterSpec for GPFSEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel0::R](R) reader structure"] +impl crate::Readable for GPFSEL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel0::W](W) writer structure"] +impl crate::Writable for GPFSEL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel1.rs b/crates/bcm2711-lpa/src/gpio/gpfsel1.rs new file mode 100644 index 0000000..6d8414a --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfsel1.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL10` reader - Function Select 10"] +pub type FSEL10_R = crate::FieldReader; +#[doc = "Function Select 10"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL10_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MOSI"] + SPI0_MOSI = 4, + #[doc = "5: Pin is connected to SD2"] + SD2 = 5, + #[doc = "6: Pin is connected to DPI_D6"] + DPI_D6 = 6, + #[doc = "7: Pin is connected to BSCSL_MOSI"] + BSCSL_MOSI = 7, + #[doc = "3: Pin is connected to CTS4"] + CTS4 = 3, + #[doc = "2: Pin is connected to SDA5"] + SDA5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL10_A) -> Self { + variant as _ + } +} +impl FSEL10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL10_A { + match self.bits { + 0 => FSEL10_A::INPUT, + 1 => FSEL10_A::OUTPUT, + 4 => FSEL10_A::SPI0_MOSI, + 5 => FSEL10_A::SD2, + 6 => FSEL10_A::DPI_D6, + 7 => FSEL10_A::BSCSL_MOSI, + 3 => FSEL10_A::CTS4, + 2 => FSEL10_A::SDA5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL10_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL10_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[inline(always)] + pub fn is_spi0_mosi(&self) -> bool { + *self == FSEL10_A::SPI0_MOSI + } + #[doc = "Checks if the value of the field is `SD2`"] + #[inline(always)] + pub fn is_sd2(&self) -> bool { + *self == FSEL10_A::SD2 + } + #[doc = "Checks if the value of the field is `DPI_D6`"] + #[inline(always)] + pub fn is_dpi_d6(&self) -> bool { + *self == FSEL10_A::DPI_D6 + } + #[doc = "Checks if the value of the field is `BSCSL_MOSI`"] + #[inline(always)] + pub fn is_bscsl_mosi(&self) -> bool { + *self == FSEL10_A::BSCSL_MOSI + } + #[doc = "Checks if the value of the field is `CTS4`"] + #[inline(always)] + pub fn is_cts4(&self) -> bool { + *self == FSEL10_A::CTS4 + } + #[doc = "Checks if the value of the field is `SDA5`"] + #[inline(always)] + pub fn is_sda5(&self) -> bool { + *self == FSEL10_A::SDA5 + } +} +#[doc = "Field `FSEL10` writer - Function Select 10"] +pub type FSEL10_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL10_A, 3, O>; +impl<'a, const O: u8> FSEL10_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL10_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL10_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MOSI"] + #[inline(always)] + pub fn spi0_mosi(self) -> &'a mut W { + self.variant(FSEL10_A::SPI0_MOSI) + } + #[doc = "Pin is connected to SD2"] + #[inline(always)] + pub fn sd2(self) -> &'a mut W { + self.variant(FSEL10_A::SD2) + } + #[doc = "Pin is connected to DPI_D6"] + #[inline(always)] + pub fn dpi_d6(self) -> &'a mut W { + self.variant(FSEL10_A::DPI_D6) + } + #[doc = "Pin is connected to BSCSL_MOSI"] + #[inline(always)] + pub fn bscsl_mosi(self) -> &'a mut W { + self.variant(FSEL10_A::BSCSL_MOSI) + } + #[doc = "Pin is connected to CTS4"] + #[inline(always)] + pub fn cts4(self) -> &'a mut W { + self.variant(FSEL10_A::CTS4) + } + #[doc = "Pin is connected to SDA5"] + #[inline(always)] + pub fn sda5(self) -> &'a mut W { + self.variant(FSEL10_A::SDA5) + } +} +#[doc = "Field `FSEL11` reader - Function Select 11"] +pub type FSEL11_R = crate::FieldReader; +#[doc = "Function Select 11"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL11_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_SCLK"] + SPI0_SCLK = 4, + #[doc = "5: Pin is connected to SD3"] + SD3 = 5, + #[doc = "6: Pin is connected to DPI_D7"] + DPI_D7 = 6, + #[doc = "7: Pin is connected to BSCSL_SCLK"] + BSCSL_SCLK = 7, + #[doc = "3: Pin is connected to RTS4"] + RTS4 = 3, + #[doc = "2: Pin is connected to SCL5"] + SCL5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL11_A) -> Self { + variant as _ + } +} +impl FSEL11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL11_A { + match self.bits { + 0 => FSEL11_A::INPUT, + 1 => FSEL11_A::OUTPUT, + 4 => FSEL11_A::SPI0_SCLK, + 5 => FSEL11_A::SD3, + 6 => FSEL11_A::DPI_D7, + 7 => FSEL11_A::BSCSL_SCLK, + 3 => FSEL11_A::RTS4, + 2 => FSEL11_A::SCL5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL11_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL11_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[inline(always)] + pub fn is_spi0_sclk(&self) -> bool { + *self == FSEL11_A::SPI0_SCLK + } + #[doc = "Checks if the value of the field is `SD3`"] + #[inline(always)] + pub fn is_sd3(&self) -> bool { + *self == FSEL11_A::SD3 + } + #[doc = "Checks if the value of the field is `DPI_D7`"] + #[inline(always)] + pub fn is_dpi_d7(&self) -> bool { + *self == FSEL11_A::DPI_D7 + } + #[doc = "Checks if the value of the field is `BSCSL_SCLK`"] + #[inline(always)] + pub fn is_bscsl_sclk(&self) -> bool { + *self == FSEL11_A::BSCSL_SCLK + } + #[doc = "Checks if the value of the field is `RTS4`"] + #[inline(always)] + pub fn is_rts4(&self) -> bool { + *self == FSEL11_A::RTS4 + } + #[doc = "Checks if the value of the field is `SCL5`"] + #[inline(always)] + pub fn is_scl5(&self) -> bool { + *self == FSEL11_A::SCL5 + } +} +#[doc = "Field `FSEL11` writer - Function Select 11"] +pub type FSEL11_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL11_A, 3, O>; +impl<'a, const O: u8> FSEL11_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL11_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL11_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_SCLK"] + #[inline(always)] + pub fn spi0_sclk(self) -> &'a mut W { + self.variant(FSEL11_A::SPI0_SCLK) + } + #[doc = "Pin is connected to SD3"] + #[inline(always)] + pub fn sd3(self) -> &'a mut W { + self.variant(FSEL11_A::SD3) + } + #[doc = "Pin is connected to DPI_D7"] + #[inline(always)] + pub fn dpi_d7(self) -> &'a mut W { + self.variant(FSEL11_A::DPI_D7) + } + #[doc = "Pin is connected to BSCSL_SCLK"] + #[inline(always)] + pub fn bscsl_sclk(self) -> &'a mut W { + self.variant(FSEL11_A::BSCSL_SCLK) + } + #[doc = "Pin is connected to RTS4"] + #[inline(always)] + pub fn rts4(self) -> &'a mut W { + self.variant(FSEL11_A::RTS4) + } + #[doc = "Pin is connected to SCL5"] + #[inline(always)] + pub fn scl5(self) -> &'a mut W { + self.variant(FSEL11_A::SCL5) + } +} +#[doc = "Field `FSEL12` reader - Function Select 12"] +pub type FSEL12_R = crate::FieldReader; +#[doc = "Function Select 12"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL12_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_0"] + PWM0_0 = 4, + #[doc = "5: Pin is connected to SD4"] + SD4 = 5, + #[doc = "6: Pin is connected to DPI_D8"] + DPI_D8 = 6, + #[doc = "7: Pin is connected to SPI5_CE0_N"] + SPI5_CE0_N = 7, + #[doc = "3: Pin is connected to TXD5"] + TXD5 = 3, + #[doc = "2: Pin is connected to SDA5"] + SDA5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL12_A) -> Self { + variant as _ + } +} +impl FSEL12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL12_A { + match self.bits { + 0 => FSEL12_A::INPUT, + 1 => FSEL12_A::OUTPUT, + 4 => FSEL12_A::PWM0_0, + 5 => FSEL12_A::SD4, + 6 => FSEL12_A::DPI_D8, + 7 => FSEL12_A::SPI5_CE0_N, + 3 => FSEL12_A::TXD5, + 2 => FSEL12_A::SDA5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL12_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL12_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL12_A::PWM0_0 + } + #[doc = "Checks if the value of the field is `SD4`"] + #[inline(always)] + pub fn is_sd4(&self) -> bool { + *self == FSEL12_A::SD4 + } + #[doc = "Checks if the value of the field is `DPI_D8`"] + #[inline(always)] + pub fn is_dpi_d8(&self) -> bool { + *self == FSEL12_A::DPI_D8 + } + #[doc = "Checks if the value of the field is `SPI5_CE0_N`"] + #[inline(always)] + pub fn is_spi5_ce0_n(&self) -> bool { + *self == FSEL12_A::SPI5_CE0_N + } + #[doc = "Checks if the value of the field is `TXD5`"] + #[inline(always)] + pub fn is_txd5(&self) -> bool { + *self == FSEL12_A::TXD5 + } + #[doc = "Checks if the value of the field is `SDA5`"] + #[inline(always)] + pub fn is_sda5(&self) -> bool { + *self == FSEL12_A::SDA5 + } +} +#[doc = "Field `FSEL12` writer - Function Select 12"] +pub type FSEL12_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL12_A, 3, O>; +impl<'a, const O: u8> FSEL12_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL12_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL12_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL12_A::PWM0_0) + } + #[doc = "Pin is connected to SD4"] + #[inline(always)] + pub fn sd4(self) -> &'a mut W { + self.variant(FSEL12_A::SD4) + } + #[doc = "Pin is connected to DPI_D8"] + #[inline(always)] + pub fn dpi_d8(self) -> &'a mut W { + self.variant(FSEL12_A::DPI_D8) + } + #[doc = "Pin is connected to SPI5_CE0_N"] + #[inline(always)] + pub fn spi5_ce0_n(self) -> &'a mut W { + self.variant(FSEL12_A::SPI5_CE0_N) + } + #[doc = "Pin is connected to TXD5"] + #[inline(always)] + pub fn txd5(self) -> &'a mut W { + self.variant(FSEL12_A::TXD5) + } + #[doc = "Pin is connected to SDA5"] + #[inline(always)] + pub fn sda5(self) -> &'a mut W { + self.variant(FSEL12_A::SDA5) + } +} +#[doc = "Field `FSEL13` reader - Function Select 13"] +pub type FSEL13_R = crate::FieldReader; +#[doc = "Function Select 13"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL13_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SD5"] + SD5 = 5, + #[doc = "6: Pin is connected to DPI_D9"] + DPI_D9 = 6, + #[doc = "7: Pin is connected to SPI5_MISO"] + SPI5_MISO = 7, + #[doc = "3: Pin is connected to RXD5"] + RXD5 = 3, + #[doc = "2: Pin is connected to SCL5"] + SCL5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL13_A) -> Self { + variant as _ + } +} +impl FSEL13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL13_A { + match self.bits { + 0 => FSEL13_A::INPUT, + 1 => FSEL13_A::OUTPUT, + 4 => FSEL13_A::PWM0_1, + 5 => FSEL13_A::SD5, + 6 => FSEL13_A::DPI_D9, + 7 => FSEL13_A::SPI5_MISO, + 3 => FSEL13_A::RXD5, + 2 => FSEL13_A::SCL5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL13_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL13_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL13_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SD5`"] + #[inline(always)] + pub fn is_sd5(&self) -> bool { + *self == FSEL13_A::SD5 + } + #[doc = "Checks if the value of the field is `DPI_D9`"] + #[inline(always)] + pub fn is_dpi_d9(&self) -> bool { + *self == FSEL13_A::DPI_D9 + } + #[doc = "Checks if the value of the field is `SPI5_MISO`"] + #[inline(always)] + pub fn is_spi5_miso(&self) -> bool { + *self == FSEL13_A::SPI5_MISO + } + #[doc = "Checks if the value of the field is `RXD5`"] + #[inline(always)] + pub fn is_rxd5(&self) -> bool { + *self == FSEL13_A::RXD5 + } + #[doc = "Checks if the value of the field is `SCL5`"] + #[inline(always)] + pub fn is_scl5(&self) -> bool { + *self == FSEL13_A::SCL5 + } +} +#[doc = "Field `FSEL13` writer - Function Select 13"] +pub type FSEL13_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL13_A, 3, O>; +impl<'a, const O: u8> FSEL13_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL13_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL13_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL13_A::PWM0_1) + } + #[doc = "Pin is connected to SD5"] + #[inline(always)] + pub fn sd5(self) -> &'a mut W { + self.variant(FSEL13_A::SD5) + } + #[doc = "Pin is connected to DPI_D9"] + #[inline(always)] + pub fn dpi_d9(self) -> &'a mut W { + self.variant(FSEL13_A::DPI_D9) + } + #[doc = "Pin is connected to SPI5_MISO"] + #[inline(always)] + pub fn spi5_miso(self) -> &'a mut W { + self.variant(FSEL13_A::SPI5_MISO) + } + #[doc = "Pin is connected to RXD5"] + #[inline(always)] + pub fn rxd5(self) -> &'a mut W { + self.variant(FSEL13_A::RXD5) + } + #[doc = "Pin is connected to SCL5"] + #[inline(always)] + pub fn scl5(self) -> &'a mut W { + self.variant(FSEL13_A::SCL5) + } +} +#[doc = "Field `FSEL14` reader - Function Select 14"] +pub type FSEL14_R = crate::FieldReader; +#[doc = "Function Select 14"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL14_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to TXD0"] + TXD0 = 4, + #[doc = "5: Pin is connected to SD6"] + SD6 = 5, + #[doc = "6: Pin is connected to DPI_D10"] + DPI_D10 = 6, + #[doc = "7: Pin is connected to SPI5_MOSI"] + SPI5_MOSI = 7, + #[doc = "3: Pin is connected to CTS5"] + CTS5 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL14_A) -> Self { + variant as _ + } +} +impl FSEL14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL14_A { + match self.bits { + 0 => FSEL14_A::INPUT, + 1 => FSEL14_A::OUTPUT, + 4 => FSEL14_A::TXD0, + 5 => FSEL14_A::SD6, + 6 => FSEL14_A::DPI_D10, + 7 => FSEL14_A::SPI5_MOSI, + 3 => FSEL14_A::CTS5, + 2 => FSEL14_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL14_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL14_A::OUTPUT + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL14_A::TXD0 + } + #[doc = "Checks if the value of the field is `SD6`"] + #[inline(always)] + pub fn is_sd6(&self) -> bool { + *self == FSEL14_A::SD6 + } + #[doc = "Checks if the value of the field is `DPI_D10`"] + #[inline(always)] + pub fn is_dpi_d10(&self) -> bool { + *self == FSEL14_A::DPI_D10 + } + #[doc = "Checks if the value of the field is `SPI5_MOSI`"] + #[inline(always)] + pub fn is_spi5_mosi(&self) -> bool { + *self == FSEL14_A::SPI5_MOSI + } + #[doc = "Checks if the value of the field is `CTS5`"] + #[inline(always)] + pub fn is_cts5(&self) -> bool { + *self == FSEL14_A::CTS5 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL14_A::TXD1 + } +} +#[doc = "Field `FSEL14` writer - Function Select 14"] +pub type FSEL14_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL14_A, 3, O>; +impl<'a, const O: u8> FSEL14_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL14_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL14_A::OUTPUT) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL14_A::TXD0) + } + #[doc = "Pin is connected to SD6"] + #[inline(always)] + pub fn sd6(self) -> &'a mut W { + self.variant(FSEL14_A::SD6) + } + #[doc = "Pin is connected to DPI_D10"] + #[inline(always)] + pub fn dpi_d10(self) -> &'a mut W { + self.variant(FSEL14_A::DPI_D10) + } + #[doc = "Pin is connected to SPI5_MOSI"] + #[inline(always)] + pub fn spi5_mosi(self) -> &'a mut W { + self.variant(FSEL14_A::SPI5_MOSI) + } + #[doc = "Pin is connected to CTS5"] + #[inline(always)] + pub fn cts5(self) -> &'a mut W { + self.variant(FSEL14_A::CTS5) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL14_A::TXD1) + } +} +#[doc = "Field `FSEL15` reader - Function Select 15"] +pub type FSEL15_R = crate::FieldReader; +#[doc = "Function Select 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL15_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to RXD0"] + RXD0 = 4, + #[doc = "5: Pin is connected to SD7"] + SD7 = 5, + #[doc = "6: Pin is connected to DPI_D11"] + DPI_D11 = 6, + #[doc = "7: Pin is connected to SPI5_SCLK"] + SPI5_SCLK = 7, + #[doc = "3: Pin is connected to RTS5"] + RTS5 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL15_A) -> Self { + variant as _ + } +} +impl FSEL15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL15_A { + match self.bits { + 0 => FSEL15_A::INPUT, + 1 => FSEL15_A::OUTPUT, + 4 => FSEL15_A::RXD0, + 5 => FSEL15_A::SD7, + 6 => FSEL15_A::DPI_D11, + 7 => FSEL15_A::SPI5_SCLK, + 3 => FSEL15_A::RTS5, + 2 => FSEL15_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL15_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL15_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL15_A::RXD0 + } + #[doc = "Checks if the value of the field is `SD7`"] + #[inline(always)] + pub fn is_sd7(&self) -> bool { + *self == FSEL15_A::SD7 + } + #[doc = "Checks if the value of the field is `DPI_D11`"] + #[inline(always)] + pub fn is_dpi_d11(&self) -> bool { + *self == FSEL15_A::DPI_D11 + } + #[doc = "Checks if the value of the field is `SPI5_SCLK`"] + #[inline(always)] + pub fn is_spi5_sclk(&self) -> bool { + *self == FSEL15_A::SPI5_SCLK + } + #[doc = "Checks if the value of the field is `RTS5`"] + #[inline(always)] + pub fn is_rts5(&self) -> bool { + *self == FSEL15_A::RTS5 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL15_A::RXD1 + } +} +#[doc = "Field `FSEL15` writer - Function Select 15"] +pub type FSEL15_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL15_A, 3, O>; +impl<'a, const O: u8> FSEL15_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL15_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL15_A::OUTPUT) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL15_A::RXD0) + } + #[doc = "Pin is connected to SD7"] + #[inline(always)] + pub fn sd7(self) -> &'a mut W { + self.variant(FSEL15_A::SD7) + } + #[doc = "Pin is connected to DPI_D11"] + #[inline(always)] + pub fn dpi_d11(self) -> &'a mut W { + self.variant(FSEL15_A::DPI_D11) + } + #[doc = "Pin is connected to SPI5_SCLK"] + #[inline(always)] + pub fn spi5_sclk(self) -> &'a mut W { + self.variant(FSEL15_A::SPI5_SCLK) + } + #[doc = "Pin is connected to RTS5"] + #[inline(always)] + pub fn rts5(self) -> &'a mut W { + self.variant(FSEL15_A::RTS5) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL15_A::RXD1) + } +} +#[doc = "Field `FSEL16` reader - Function Select 16"] +pub type FSEL16_R = crate::FieldReader; +#[doc = "Function Select 16"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL16_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD8"] + SD8 = 5, + #[doc = "6: Pin is connected to DPI_D12"] + DPI_D12 = 6, + #[doc = "7: Pin is connected to CTS0"] + CTS0 = 7, + #[doc = "3: Pin is connected to SPI1_CE2_N"] + SPI1_CE2_N = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL16_A) -> Self { + variant as _ + } +} +impl FSEL16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL16_A { + match self.bits { + 0 => FSEL16_A::INPUT, + 1 => FSEL16_A::OUTPUT, + 4 => FSEL16_A::RESERVED0, + 5 => FSEL16_A::SD8, + 6 => FSEL16_A::DPI_D12, + 7 => FSEL16_A::CTS0, + 3 => FSEL16_A::SPI1_CE2_N, + 2 => FSEL16_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL16_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL16_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL16_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD8`"] + #[inline(always)] + pub fn is_sd8(&self) -> bool { + *self == FSEL16_A::SD8 + } + #[doc = "Checks if the value of the field is `DPI_D12`"] + #[inline(always)] + pub fn is_dpi_d12(&self) -> bool { + *self == FSEL16_A::DPI_D12 + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL16_A::CTS0 + } + #[doc = "Checks if the value of the field is `SPI1_CE2_N`"] + #[inline(always)] + pub fn is_spi1_ce2_n(&self) -> bool { + *self == FSEL16_A::SPI1_CE2_N + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL16_A::CTS1 + } +} +#[doc = "Field `FSEL16` writer - Function Select 16"] +pub type FSEL16_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL16_A, 3, O>; +impl<'a, const O: u8> FSEL16_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL16_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL16_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL16_A::RESERVED0) + } + #[doc = "Pin is connected to SD8"] + #[inline(always)] + pub fn sd8(self) -> &'a mut W { + self.variant(FSEL16_A::SD8) + } + #[doc = "Pin is connected to DPI_D12"] + #[inline(always)] + pub fn dpi_d12(self) -> &'a mut W { + self.variant(FSEL16_A::DPI_D12) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL16_A::CTS0) + } + #[doc = "Pin is connected to SPI1_CE2_N"] + #[inline(always)] + pub fn spi1_ce2_n(self) -> &'a mut W { + self.variant(FSEL16_A::SPI1_CE2_N) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL16_A::CTS1) + } +} +#[doc = "Field `FSEL17` reader - Function Select 17"] +pub type FSEL17_R = crate::FieldReader; +#[doc = "Function Select 17"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL17_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD9"] + SD9 = 5, + #[doc = "6: Pin is connected to DPI_D13"] + DPI_D13 = 6, + #[doc = "7: Pin is connected to RTS0"] + RTS0 = 7, + #[doc = "3: Pin is connected to SPI1_CE1_N"] + SPI1_CE1_N = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL17_A) -> Self { + variant as _ + } +} +impl FSEL17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL17_A { + match self.bits { + 0 => FSEL17_A::INPUT, + 1 => FSEL17_A::OUTPUT, + 4 => FSEL17_A::RESERVED0, + 5 => FSEL17_A::SD9, + 6 => FSEL17_A::DPI_D13, + 7 => FSEL17_A::RTS0, + 3 => FSEL17_A::SPI1_CE1_N, + 2 => FSEL17_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL17_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL17_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL17_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD9`"] + #[inline(always)] + pub fn is_sd9(&self) -> bool { + *self == FSEL17_A::SD9 + } + #[doc = "Checks if the value of the field is `DPI_D13`"] + #[inline(always)] + pub fn is_dpi_d13(&self) -> bool { + *self == FSEL17_A::DPI_D13 + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL17_A::RTS0 + } + #[doc = "Checks if the value of the field is `SPI1_CE1_N`"] + #[inline(always)] + pub fn is_spi1_ce1_n(&self) -> bool { + *self == FSEL17_A::SPI1_CE1_N + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL17_A::RTS1 + } +} +#[doc = "Field `FSEL17` writer - Function Select 17"] +pub type FSEL17_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL17_A, 3, O>; +impl<'a, const O: u8> FSEL17_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL17_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL17_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL17_A::RESERVED0) + } + #[doc = "Pin is connected to SD9"] + #[inline(always)] + pub fn sd9(self) -> &'a mut W { + self.variant(FSEL17_A::SD9) + } + #[doc = "Pin is connected to DPI_D13"] + #[inline(always)] + pub fn dpi_d13(self) -> &'a mut W { + self.variant(FSEL17_A::DPI_D13) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL17_A::RTS0) + } + #[doc = "Pin is connected to SPI1_CE1_N"] + #[inline(always)] + pub fn spi1_ce1_n(self) -> &'a mut W { + self.variant(FSEL17_A::SPI1_CE1_N) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL17_A::RTS1) + } +} +#[doc = "Field `FSEL18` reader - Function Select 18"] +pub type FSEL18_R = crate::FieldReader; +#[doc = "Function Select 18"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL18_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_CLK"] + PCM_CLK = 4, + #[doc = "5: Pin is connected to SD10"] + SD10 = 5, + #[doc = "6: Pin is connected to DPI_D14"] + DPI_D14 = 6, + #[doc = "7: Pin is connected to SPI6_CE0_N"] + SPI6_CE0_N = 7, + #[doc = "3: Pin is connected to SPI1_CE0_N"] + SPI1_CE0_N = 3, + #[doc = "2: Pin is connected to PWM0_0"] + PWM0_0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL18_A) -> Self { + variant as _ + } +} +impl FSEL18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL18_A { + match self.bits { + 0 => FSEL18_A::INPUT, + 1 => FSEL18_A::OUTPUT, + 4 => FSEL18_A::PCM_CLK, + 5 => FSEL18_A::SD10, + 6 => FSEL18_A::DPI_D14, + 7 => FSEL18_A::SPI6_CE0_N, + 3 => FSEL18_A::SPI1_CE0_N, + 2 => FSEL18_A::PWM0_0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL18_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL18_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[inline(always)] + pub fn is_pcm_clk(&self) -> bool { + *self == FSEL18_A::PCM_CLK + } + #[doc = "Checks if the value of the field is `SD10`"] + #[inline(always)] + pub fn is_sd10(&self) -> bool { + *self == FSEL18_A::SD10 + } + #[doc = "Checks if the value of the field is `DPI_D14`"] + #[inline(always)] + pub fn is_dpi_d14(&self) -> bool { + *self == FSEL18_A::DPI_D14 + } + #[doc = "Checks if the value of the field is `SPI6_CE0_N`"] + #[inline(always)] + pub fn is_spi6_ce0_n(&self) -> bool { + *self == FSEL18_A::SPI6_CE0_N + } + #[doc = "Checks if the value of the field is `SPI1_CE0_N`"] + #[inline(always)] + pub fn is_spi1_ce0_n(&self) -> bool { + *self == FSEL18_A::SPI1_CE0_N + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL18_A::PWM0_0 + } +} +#[doc = "Field `FSEL18` writer - Function Select 18"] +pub type FSEL18_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL18_A, 3, O>; +impl<'a, const O: u8> FSEL18_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL18_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL18_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_CLK"] + #[inline(always)] + pub fn pcm_clk(self) -> &'a mut W { + self.variant(FSEL18_A::PCM_CLK) + } + #[doc = "Pin is connected to SD10"] + #[inline(always)] + pub fn sd10(self) -> &'a mut W { + self.variant(FSEL18_A::SD10) + } + #[doc = "Pin is connected to DPI_D14"] + #[inline(always)] + pub fn dpi_d14(self) -> &'a mut W { + self.variant(FSEL18_A::DPI_D14) + } + #[doc = "Pin is connected to SPI6_CE0_N"] + #[inline(always)] + pub fn spi6_ce0_n(self) -> &'a mut W { + self.variant(FSEL18_A::SPI6_CE0_N) + } + #[doc = "Pin is connected to SPI1_CE0_N"] + #[inline(always)] + pub fn spi1_ce0_n(self) -> &'a mut W { + self.variant(FSEL18_A::SPI1_CE0_N) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL18_A::PWM0_0) + } +} +#[doc = "Field `FSEL19` reader - Function Select 19"] +pub type FSEL19_R = crate::FieldReader; +#[doc = "Function Select 19"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL19_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_FS"] + PCM_FS = 4, + #[doc = "5: Pin is connected to SD11"] + SD11 = 5, + #[doc = "6: Pin is connected to DPI_D15"] + DPI_D15 = 6, + #[doc = "7: Pin is connected to SPI6_MISO"] + SPI6_MISO = 7, + #[doc = "3: Pin is connected to SPI1_MISO"] + SPI1_MISO = 3, + #[doc = "2: Pin is connected to PWM0_1"] + PWM0_1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL19_A) -> Self { + variant as _ + } +} +impl FSEL19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL19_A { + match self.bits { + 0 => FSEL19_A::INPUT, + 1 => FSEL19_A::OUTPUT, + 4 => FSEL19_A::PCM_FS, + 5 => FSEL19_A::SD11, + 6 => FSEL19_A::DPI_D15, + 7 => FSEL19_A::SPI6_MISO, + 3 => FSEL19_A::SPI1_MISO, + 2 => FSEL19_A::PWM0_1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL19_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL19_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_FS`"] + #[inline(always)] + pub fn is_pcm_fs(&self) -> bool { + *self == FSEL19_A::PCM_FS + } + #[doc = "Checks if the value of the field is `SD11`"] + #[inline(always)] + pub fn is_sd11(&self) -> bool { + *self == FSEL19_A::SD11 + } + #[doc = "Checks if the value of the field is `DPI_D15`"] + #[inline(always)] + pub fn is_dpi_d15(&self) -> bool { + *self == FSEL19_A::DPI_D15 + } + #[doc = "Checks if the value of the field is `SPI6_MISO`"] + #[inline(always)] + pub fn is_spi6_miso(&self) -> bool { + *self == FSEL19_A::SPI6_MISO + } + #[doc = "Checks if the value of the field is `SPI1_MISO`"] + #[inline(always)] + pub fn is_spi1_miso(&self) -> bool { + *self == FSEL19_A::SPI1_MISO + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL19_A::PWM0_1 + } +} +#[doc = "Field `FSEL19` writer - Function Select 19"] +pub type FSEL19_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL19_A, 3, O>; +impl<'a, const O: u8> FSEL19_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL19_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL19_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_FS"] + #[inline(always)] + pub fn pcm_fs(self) -> &'a mut W { + self.variant(FSEL19_A::PCM_FS) + } + #[doc = "Pin is connected to SD11"] + #[inline(always)] + pub fn sd11(self) -> &'a mut W { + self.variant(FSEL19_A::SD11) + } + #[doc = "Pin is connected to DPI_D15"] + #[inline(always)] + pub fn dpi_d15(self) -> &'a mut W { + self.variant(FSEL19_A::DPI_D15) + } + #[doc = "Pin is connected to SPI6_MISO"] + #[inline(always)] + pub fn spi6_miso(self) -> &'a mut W { + self.variant(FSEL19_A::SPI6_MISO) + } + #[doc = "Pin is connected to SPI1_MISO"] + #[inline(always)] + pub fn spi1_miso(self) -> &'a mut W { + self.variant(FSEL19_A::SPI1_MISO) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL19_A::PWM0_1) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 10"] + #[inline(always)] + pub fn fsel10(&self) -> FSEL10_R { + FSEL10_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 11"] + #[inline(always)] + pub fn fsel11(&self) -> FSEL11_R { + FSEL11_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 12"] + #[inline(always)] + pub fn fsel12(&self) -> FSEL12_R { + FSEL12_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 13"] + #[inline(always)] + pub fn fsel13(&self) -> FSEL13_R { + FSEL13_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 14"] + #[inline(always)] + pub fn fsel14(&self) -> FSEL14_R { + FSEL14_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 15"] + #[inline(always)] + pub fn fsel15(&self) -> FSEL15_R { + FSEL15_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 16"] + #[inline(always)] + pub fn fsel16(&self) -> FSEL16_R { + FSEL16_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 17"] + #[inline(always)] + pub fn fsel17(&self) -> FSEL17_R { + FSEL17_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 18"] + #[inline(always)] + pub fn fsel18(&self) -> FSEL18_R { + FSEL18_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 19"] + #[inline(always)] + pub fn fsel19(&self) -> FSEL19_R { + FSEL19_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 10"] + #[inline(always)] + #[must_use] + pub fn fsel10(&mut self) -> FSEL10_W<0> { + FSEL10_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 11"] + #[inline(always)] + #[must_use] + pub fn fsel11(&mut self) -> FSEL11_W<3> { + FSEL11_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 12"] + #[inline(always)] + #[must_use] + pub fn fsel12(&mut self) -> FSEL12_W<6> { + FSEL12_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 13"] + #[inline(always)] + #[must_use] + pub fn fsel13(&mut self) -> FSEL13_W<9> { + FSEL13_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 14"] + #[inline(always)] + #[must_use] + pub fn fsel14(&mut self) -> FSEL14_W<12> { + FSEL14_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 15"] + #[inline(always)] + #[must_use] + pub fn fsel15(&mut self) -> FSEL15_W<15> { + FSEL15_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 16"] + #[inline(always)] + #[must_use] + pub fn fsel16(&mut self) -> FSEL16_W<18> { + FSEL16_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 17"] + #[inline(always)] + #[must_use] + pub fn fsel17(&mut self) -> FSEL17_W<21> { + FSEL17_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 18"] + #[inline(always)] + #[must_use] + pub fn fsel18(&mut self) -> FSEL18_W<24> { + FSEL18_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 19"] + #[inline(always)] + #[must_use] + pub fn fsel19(&mut self) -> FSEL19_W<27> { + FSEL19_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel1](index.html) module"] +pub struct GPFSEL1_SPEC; +impl crate::RegisterSpec for GPFSEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel1::R](R) reader structure"] +impl crate::Readable for GPFSEL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel1::W](W) writer structure"] +impl crate::Writable for GPFSEL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel2.rs b/crates/bcm2711-lpa/src/gpio/gpfsel2.rs new file mode 100644 index 0000000..1622933 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfsel2.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL20` reader - Function Select 20"] +pub type FSEL20_R = crate::FieldReader; +#[doc = "Function Select 20"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL20_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_DIN"] + PCM_DIN = 4, + #[doc = "5: Pin is connected to SD12"] + SD12 = 5, + #[doc = "6: Pin is connected to DPI_D16"] + DPI_D16 = 6, + #[doc = "7: Pin is connected to SPI6_MOSI"] + SPI6_MOSI = 7, + #[doc = "3: Pin is connected to SPI1_MOSI"] + SPI1_MOSI = 3, + #[doc = "2: Pin is connected to GPCLK0"] + GPCLK0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL20_A) -> Self { + variant as _ + } +} +impl FSEL20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL20_A { + match self.bits { + 0 => FSEL20_A::INPUT, + 1 => FSEL20_A::OUTPUT, + 4 => FSEL20_A::PCM_DIN, + 5 => FSEL20_A::SD12, + 6 => FSEL20_A::DPI_D16, + 7 => FSEL20_A::SPI6_MOSI, + 3 => FSEL20_A::SPI1_MOSI, + 2 => FSEL20_A::GPCLK0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL20_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL20_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[inline(always)] + pub fn is_pcm_din(&self) -> bool { + *self == FSEL20_A::PCM_DIN + } + #[doc = "Checks if the value of the field is `SD12`"] + #[inline(always)] + pub fn is_sd12(&self) -> bool { + *self == FSEL20_A::SD12 + } + #[doc = "Checks if the value of the field is `DPI_D16`"] + #[inline(always)] + pub fn is_dpi_d16(&self) -> bool { + *self == FSEL20_A::DPI_D16 + } + #[doc = "Checks if the value of the field is `SPI6_MOSI`"] + #[inline(always)] + pub fn is_spi6_mosi(&self) -> bool { + *self == FSEL20_A::SPI6_MOSI + } + #[doc = "Checks if the value of the field is `SPI1_MOSI`"] + #[inline(always)] + pub fn is_spi1_mosi(&self) -> bool { + *self == FSEL20_A::SPI1_MOSI + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL20_A::GPCLK0 + } +} +#[doc = "Field `FSEL20` writer - Function Select 20"] +pub type FSEL20_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL20_A, 3, O>; +impl<'a, const O: u8> FSEL20_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL20_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL20_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_DIN"] + #[inline(always)] + pub fn pcm_din(self) -> &'a mut W { + self.variant(FSEL20_A::PCM_DIN) + } + #[doc = "Pin is connected to SD12"] + #[inline(always)] + pub fn sd12(self) -> &'a mut W { + self.variant(FSEL20_A::SD12) + } + #[doc = "Pin is connected to DPI_D16"] + #[inline(always)] + pub fn dpi_d16(self) -> &'a mut W { + self.variant(FSEL20_A::DPI_D16) + } + #[doc = "Pin is connected to SPI6_MOSI"] + #[inline(always)] + pub fn spi6_mosi(self) -> &'a mut W { + self.variant(FSEL20_A::SPI6_MOSI) + } + #[doc = "Pin is connected to SPI1_MOSI"] + #[inline(always)] + pub fn spi1_mosi(self) -> &'a mut W { + self.variant(FSEL20_A::SPI1_MOSI) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL20_A::GPCLK0) + } +} +#[doc = "Field `FSEL21` reader - Function Select 21"] +pub type FSEL21_R = crate::FieldReader; +#[doc = "Function Select 21"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL21_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_DOUT"] + PCM_DOUT = 4, + #[doc = "5: Pin is connected to SD13"] + SD13 = 5, + #[doc = "6: Pin is connected to DPI_D17"] + DPI_D17 = 6, + #[doc = "7: Pin is connected to SPI6_SCLK"] + SPI6_SCLK = 7, + #[doc = "3: Pin is connected to SPI1_SCLK"] + SPI1_SCLK = 3, + #[doc = "2: Pin is connected to GPCLK1"] + GPCLK1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL21_A) -> Self { + variant as _ + } +} +impl FSEL21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL21_A { + match self.bits { + 0 => FSEL21_A::INPUT, + 1 => FSEL21_A::OUTPUT, + 4 => FSEL21_A::PCM_DOUT, + 5 => FSEL21_A::SD13, + 6 => FSEL21_A::DPI_D17, + 7 => FSEL21_A::SPI6_SCLK, + 3 => FSEL21_A::SPI1_SCLK, + 2 => FSEL21_A::GPCLK1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL21_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL21_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[inline(always)] + pub fn is_pcm_dout(&self) -> bool { + *self == FSEL21_A::PCM_DOUT + } + #[doc = "Checks if the value of the field is `SD13`"] + #[inline(always)] + pub fn is_sd13(&self) -> bool { + *self == FSEL21_A::SD13 + } + #[doc = "Checks if the value of the field is `DPI_D17`"] + #[inline(always)] + pub fn is_dpi_d17(&self) -> bool { + *self == FSEL21_A::DPI_D17 + } + #[doc = "Checks if the value of the field is `SPI6_SCLK`"] + #[inline(always)] + pub fn is_spi6_sclk(&self) -> bool { + *self == FSEL21_A::SPI6_SCLK + } + #[doc = "Checks if the value of the field is `SPI1_SCLK`"] + #[inline(always)] + pub fn is_spi1_sclk(&self) -> bool { + *self == FSEL21_A::SPI1_SCLK + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL21_A::GPCLK1 + } +} +#[doc = "Field `FSEL21` writer - Function Select 21"] +pub type FSEL21_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL21_A, 3, O>; +impl<'a, const O: u8> FSEL21_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL21_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL21_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_DOUT"] + #[inline(always)] + pub fn pcm_dout(self) -> &'a mut W { + self.variant(FSEL21_A::PCM_DOUT) + } + #[doc = "Pin is connected to SD13"] + #[inline(always)] + pub fn sd13(self) -> &'a mut W { + self.variant(FSEL21_A::SD13) + } + #[doc = "Pin is connected to DPI_D17"] + #[inline(always)] + pub fn dpi_d17(self) -> &'a mut W { + self.variant(FSEL21_A::DPI_D17) + } + #[doc = "Pin is connected to SPI6_SCLK"] + #[inline(always)] + pub fn spi6_sclk(self) -> &'a mut W { + self.variant(FSEL21_A::SPI6_SCLK) + } + #[doc = "Pin is connected to SPI1_SCLK"] + #[inline(always)] + pub fn spi1_sclk(self) -> &'a mut W { + self.variant(FSEL21_A::SPI1_SCLK) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL21_A::GPCLK1) + } +} +#[doc = "Field `FSEL22` reader - Function Select 22"] +pub type FSEL22_R = crate::FieldReader; +#[doc = "Function Select 22"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL22_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SD0_CLK"] + SD0_CLK = 4, + #[doc = "5: Pin is connected to SD14"] + SD14 = 5, + #[doc = "6: Pin is connected to DPI_D18"] + DPI_D18 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Pin is connected to ARM_TRST"] + ARM_TRST = 3, + #[doc = "2: Pin is connected to SDA6"] + SDA6 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL22_A) -> Self { + variant as _ + } +} +impl FSEL22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL22_A { + match self.bits { + 0 => FSEL22_A::INPUT, + 1 => FSEL22_A::OUTPUT, + 4 => FSEL22_A::SD0_CLK, + 5 => FSEL22_A::SD14, + 6 => FSEL22_A::DPI_D18, + 7 => FSEL22_A::SD1_CLK, + 3 => FSEL22_A::ARM_TRST, + 2 => FSEL22_A::SDA6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL22_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL22_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SD0_CLK`"] + #[inline(always)] + pub fn is_sd0_clk(&self) -> bool { + *self == FSEL22_A::SD0_CLK + } + #[doc = "Checks if the value of the field is `SD14`"] + #[inline(always)] + pub fn is_sd14(&self) -> bool { + *self == FSEL22_A::SD14 + } + #[doc = "Checks if the value of the field is `DPI_D18`"] + #[inline(always)] + pub fn is_dpi_d18(&self) -> bool { + *self == FSEL22_A::DPI_D18 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL22_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `ARM_TRST`"] + #[inline(always)] + pub fn is_arm_trst(&self) -> bool { + *self == FSEL22_A::ARM_TRST + } + #[doc = "Checks if the value of the field is `SDA6`"] + #[inline(always)] + pub fn is_sda6(&self) -> bool { + *self == FSEL22_A::SDA6 + } +} +#[doc = "Field `FSEL22` writer - Function Select 22"] +pub type FSEL22_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL22_A, 3, O>; +impl<'a, const O: u8> FSEL22_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL22_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL22_A::OUTPUT) + } + #[doc = "Pin is connected to SD0_CLK"] + #[inline(always)] + pub fn sd0_clk(self) -> &'a mut W { + self.variant(FSEL22_A::SD0_CLK) + } + #[doc = "Pin is connected to SD14"] + #[inline(always)] + pub fn sd14(self) -> &'a mut W { + self.variant(FSEL22_A::SD14) + } + #[doc = "Pin is connected to DPI_D18"] + #[inline(always)] + pub fn dpi_d18(self) -> &'a mut W { + self.variant(FSEL22_A::DPI_D18) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL22_A::SD1_CLK) + } + #[doc = "Pin is connected to ARM_TRST"] + #[inline(always)] + pub fn arm_trst(self) -> &'a mut W { + self.variant(FSEL22_A::ARM_TRST) + } + #[doc = "Pin is connected to SDA6"] + #[inline(always)] + pub fn sda6(self) -> &'a mut W { + self.variant(FSEL22_A::SDA6) + } +} +#[doc = "Field `FSEL23` reader - Function Select 23"] +pub type FSEL23_R = crate::FieldReader; +#[doc = "Function Select 23"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL23_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SD0_CMD"] + SD0_CMD = 4, + #[doc = "5: Pin is connected to SD15"] + SD15 = 5, + #[doc = "6: Pin is connected to DPI_D19"] + DPI_D19 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Pin is connected to ARM_RTCK"] + ARM_RTCK = 3, + #[doc = "2: Pin is connected to SCL6"] + SCL6 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL23_A) -> Self { + variant as _ + } +} +impl FSEL23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL23_A { + match self.bits { + 0 => FSEL23_A::INPUT, + 1 => FSEL23_A::OUTPUT, + 4 => FSEL23_A::SD0_CMD, + 5 => FSEL23_A::SD15, + 6 => FSEL23_A::DPI_D19, + 7 => FSEL23_A::SD1_CMD, + 3 => FSEL23_A::ARM_RTCK, + 2 => FSEL23_A::SCL6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL23_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL23_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SD0_CMD`"] + #[inline(always)] + pub fn is_sd0_cmd(&self) -> bool { + *self == FSEL23_A::SD0_CMD + } + #[doc = "Checks if the value of the field is `SD15`"] + #[inline(always)] + pub fn is_sd15(&self) -> bool { + *self == FSEL23_A::SD15 + } + #[doc = "Checks if the value of the field is `DPI_D19`"] + #[inline(always)] + pub fn is_dpi_d19(&self) -> bool { + *self == FSEL23_A::DPI_D19 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL23_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[inline(always)] + pub fn is_arm_rtck(&self) -> bool { + *self == FSEL23_A::ARM_RTCK + } + #[doc = "Checks if the value of the field is `SCL6`"] + #[inline(always)] + pub fn is_scl6(&self) -> bool { + *self == FSEL23_A::SCL6 + } +} +#[doc = "Field `FSEL23` writer - Function Select 23"] +pub type FSEL23_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL23_A, 3, O>; +impl<'a, const O: u8> FSEL23_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL23_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL23_A::OUTPUT) + } + #[doc = "Pin is connected to SD0_CMD"] + #[inline(always)] + pub fn sd0_cmd(self) -> &'a mut W { + self.variant(FSEL23_A::SD0_CMD) + } + #[doc = "Pin is connected to SD15"] + #[inline(always)] + pub fn sd15(self) -> &'a mut W { + self.variant(FSEL23_A::SD15) + } + #[doc = "Pin is connected to DPI_D19"] + #[inline(always)] + pub fn dpi_d19(self) -> &'a mut W { + self.variant(FSEL23_A::DPI_D19) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL23_A::SD1_CMD) + } + #[doc = "Pin is connected to ARM_RTCK"] + #[inline(always)] + pub fn arm_rtck(self) -> &'a mut W { + self.variant(FSEL23_A::ARM_RTCK) + } + #[doc = "Pin is connected to SCL6"] + #[inline(always)] + pub fn scl6(self) -> &'a mut W { + self.variant(FSEL23_A::SCL6) + } +} +#[doc = "Field `FSEL24` reader - Function Select 24"] +pub type FSEL24_R = crate::FieldReader; +#[doc = "Function Select 24"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL24_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SD0_DAT0"] + SD0_DAT0 = 4, + #[doc = "5: Pin is connected to SD16"] + SD16 = 5, + #[doc = "6: Pin is connected to DPI_D20"] + DPI_D20 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Pin is connected to ARM_TDO"] + ARM_TDO = 3, + #[doc = "2: Pin is connected to SPI3_CE1_N"] + SPI3_CE1_N = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL24_A) -> Self { + variant as _ + } +} +impl FSEL24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL24_A { + match self.bits { + 0 => FSEL24_A::INPUT, + 1 => FSEL24_A::OUTPUT, + 4 => FSEL24_A::SD0_DAT0, + 5 => FSEL24_A::SD16, + 6 => FSEL24_A::DPI_D20, + 7 => FSEL24_A::SD1_DAT0, + 3 => FSEL24_A::ARM_TDO, + 2 => FSEL24_A::SPI3_CE1_N, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL24_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL24_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SD0_DAT0`"] + #[inline(always)] + pub fn is_sd0_dat0(&self) -> bool { + *self == FSEL24_A::SD0_DAT0 + } + #[doc = "Checks if the value of the field is `SD16`"] + #[inline(always)] + pub fn is_sd16(&self) -> bool { + *self == FSEL24_A::SD16 + } + #[doc = "Checks if the value of the field is `DPI_D20`"] + #[inline(always)] + pub fn is_dpi_d20(&self) -> bool { + *self == FSEL24_A::DPI_D20 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL24_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[inline(always)] + pub fn is_arm_tdo(&self) -> bool { + *self == FSEL24_A::ARM_TDO + } + #[doc = "Checks if the value of the field is `SPI3_CE1_N`"] + #[inline(always)] + pub fn is_spi3_ce1_n(&self) -> bool { + *self == FSEL24_A::SPI3_CE1_N + } +} +#[doc = "Field `FSEL24` writer - Function Select 24"] +pub type FSEL24_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL24_A, 3, O>; +impl<'a, const O: u8> FSEL24_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL24_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL24_A::OUTPUT) + } + #[doc = "Pin is connected to SD0_DAT0"] + #[inline(always)] + pub fn sd0_dat0(self) -> &'a mut W { + self.variant(FSEL24_A::SD0_DAT0) + } + #[doc = "Pin is connected to SD16"] + #[inline(always)] + pub fn sd16(self) -> &'a mut W { + self.variant(FSEL24_A::SD16) + } + #[doc = "Pin is connected to DPI_D20"] + #[inline(always)] + pub fn dpi_d20(self) -> &'a mut W { + self.variant(FSEL24_A::DPI_D20) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL24_A::SD1_DAT0) + } + #[doc = "Pin is connected to ARM_TDO"] + #[inline(always)] + pub fn arm_tdo(self) -> &'a mut W { + self.variant(FSEL24_A::ARM_TDO) + } + #[doc = "Pin is connected to SPI3_CE1_N"] + #[inline(always)] + pub fn spi3_ce1_n(self) -> &'a mut W { + self.variant(FSEL24_A::SPI3_CE1_N) + } +} +#[doc = "Field `FSEL25` reader - Function Select 25"] +pub type FSEL25_R = crate::FieldReader; +#[doc = "Function Select 25"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL25_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SD0_DAT1"] + SD0_DAT1 = 4, + #[doc = "5: Pin is connected to SD17"] + SD17 = 5, + #[doc = "6: Pin is connected to DPI_D21"] + DPI_D21 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Pin is connected to ARM_TCK"] + ARM_TCK = 3, + #[doc = "2: Pin is connected to SPI4_CE1_N"] + SPI4_CE1_N = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL25_A) -> Self { + variant as _ + } +} +impl FSEL25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL25_A { + match self.bits { + 0 => FSEL25_A::INPUT, + 1 => FSEL25_A::OUTPUT, + 4 => FSEL25_A::SD0_DAT1, + 5 => FSEL25_A::SD17, + 6 => FSEL25_A::DPI_D21, + 7 => FSEL25_A::SD1_DAT1, + 3 => FSEL25_A::ARM_TCK, + 2 => FSEL25_A::SPI4_CE1_N, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL25_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL25_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SD0_DAT1`"] + #[inline(always)] + pub fn is_sd0_dat1(&self) -> bool { + *self == FSEL25_A::SD0_DAT1 + } + #[doc = "Checks if the value of the field is `SD17`"] + #[inline(always)] + pub fn is_sd17(&self) -> bool { + *self == FSEL25_A::SD17 + } + #[doc = "Checks if the value of the field is `DPI_D21`"] + #[inline(always)] + pub fn is_dpi_d21(&self) -> bool { + *self == FSEL25_A::DPI_D21 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL25_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[inline(always)] + pub fn is_arm_tck(&self) -> bool { + *self == FSEL25_A::ARM_TCK + } + #[doc = "Checks if the value of the field is `SPI4_CE1_N`"] + #[inline(always)] + pub fn is_spi4_ce1_n(&self) -> bool { + *self == FSEL25_A::SPI4_CE1_N + } +} +#[doc = "Field `FSEL25` writer - Function Select 25"] +pub type FSEL25_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL25_A, 3, O>; +impl<'a, const O: u8> FSEL25_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL25_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL25_A::OUTPUT) + } + #[doc = "Pin is connected to SD0_DAT1"] + #[inline(always)] + pub fn sd0_dat1(self) -> &'a mut W { + self.variant(FSEL25_A::SD0_DAT1) + } + #[doc = "Pin is connected to SD17"] + #[inline(always)] + pub fn sd17(self) -> &'a mut W { + self.variant(FSEL25_A::SD17) + } + #[doc = "Pin is connected to DPI_D21"] + #[inline(always)] + pub fn dpi_d21(self) -> &'a mut W { + self.variant(FSEL25_A::DPI_D21) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL25_A::SD1_DAT1) + } + #[doc = "Pin is connected to ARM_TCK"] + #[inline(always)] + pub fn arm_tck(self) -> &'a mut W { + self.variant(FSEL25_A::ARM_TCK) + } + #[doc = "Pin is connected to SPI4_CE1_N"] + #[inline(always)] + pub fn spi4_ce1_n(self) -> &'a mut W { + self.variant(FSEL25_A::SPI4_CE1_N) + } +} +#[doc = "Field `FSEL26` reader - Function Select 26"] +pub type FSEL26_R = crate::FieldReader; +#[doc = "Function Select 26"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL26_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SD0_DAT2"] + SD0_DAT2 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Pin is connected to DPI_D22"] + DPI_D22 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Pin is connected to ARM_TDI"] + ARM_TDI = 3, + #[doc = "2: Pin is connected to SPI5_CE1_N"] + SPI5_CE1_N = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL26_A) -> Self { + variant as _ + } +} +impl FSEL26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL26_A { + match self.bits { + 0 => FSEL26_A::INPUT, + 1 => FSEL26_A::OUTPUT, + 4 => FSEL26_A::SD0_DAT2, + 5 => FSEL26_A::RESERVED1, + 6 => FSEL26_A::DPI_D22, + 7 => FSEL26_A::SD1_DAT2, + 3 => FSEL26_A::ARM_TDI, + 2 => FSEL26_A::SPI5_CE1_N, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL26_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL26_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SD0_DAT2`"] + #[inline(always)] + pub fn is_sd0_dat2(&self) -> bool { + *self == FSEL26_A::SD0_DAT2 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL26_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `DPI_D22`"] + #[inline(always)] + pub fn is_dpi_d22(&self) -> bool { + *self == FSEL26_A::DPI_D22 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL26_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[inline(always)] + pub fn is_arm_tdi(&self) -> bool { + *self == FSEL26_A::ARM_TDI + } + #[doc = "Checks if the value of the field is `SPI5_CE1_N`"] + #[inline(always)] + pub fn is_spi5_ce1_n(&self) -> bool { + *self == FSEL26_A::SPI5_CE1_N + } +} +#[doc = "Field `FSEL26` writer - Function Select 26"] +pub type FSEL26_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL26_A, 3, O>; +impl<'a, const O: u8> FSEL26_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL26_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL26_A::OUTPUT) + } + #[doc = "Pin is connected to SD0_DAT2"] + #[inline(always)] + pub fn sd0_dat2(self) -> &'a mut W { + self.variant(FSEL26_A::SD0_DAT2) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED1) + } + #[doc = "Pin is connected to DPI_D22"] + #[inline(always)] + pub fn dpi_d22(self) -> &'a mut W { + self.variant(FSEL26_A::DPI_D22) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL26_A::SD1_DAT2) + } + #[doc = "Pin is connected to ARM_TDI"] + #[inline(always)] + pub fn arm_tdi(self) -> &'a mut W { + self.variant(FSEL26_A::ARM_TDI) + } + #[doc = "Pin is connected to SPI5_CE1_N"] + #[inline(always)] + pub fn spi5_ce1_n(self) -> &'a mut W { + self.variant(FSEL26_A::SPI5_CE1_N) + } +} +#[doc = "Field `FSEL27` reader - Function Select 27"] +pub type FSEL27_R = crate::FieldReader; +#[doc = "Function Select 27"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL27_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SD0_DAT3"] + SD0_DAT3 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Pin is connected to DPI_D23"] + DPI_D23 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Pin is connected to ARM_TMS"] + ARM_TMS = 3, + #[doc = "2: Pin is connected to SPI6_CE1_N"] + SPI6_CE1_N = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL27_A) -> Self { + variant as _ + } +} +impl FSEL27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL27_A { + match self.bits { + 0 => FSEL27_A::INPUT, + 1 => FSEL27_A::OUTPUT, + 4 => FSEL27_A::SD0_DAT3, + 5 => FSEL27_A::RESERVED1, + 6 => FSEL27_A::DPI_D23, + 7 => FSEL27_A::SD1_DAT3, + 3 => FSEL27_A::ARM_TMS, + 2 => FSEL27_A::SPI6_CE1_N, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL27_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL27_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SD0_DAT3`"] + #[inline(always)] + pub fn is_sd0_dat3(&self) -> bool { + *self == FSEL27_A::SD0_DAT3 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL27_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `DPI_D23`"] + #[inline(always)] + pub fn is_dpi_d23(&self) -> bool { + *self == FSEL27_A::DPI_D23 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL27_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[inline(always)] + pub fn is_arm_tms(&self) -> bool { + *self == FSEL27_A::ARM_TMS + } + #[doc = "Checks if the value of the field is `SPI6_CE1_N`"] + #[inline(always)] + pub fn is_spi6_ce1_n(&self) -> bool { + *self == FSEL27_A::SPI6_CE1_N + } +} +#[doc = "Field `FSEL27` writer - Function Select 27"] +pub type FSEL27_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL27_A, 3, O>; +impl<'a, const O: u8> FSEL27_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL27_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL27_A::OUTPUT) + } + #[doc = "Pin is connected to SD0_DAT3"] + #[inline(always)] + pub fn sd0_dat3(self) -> &'a mut W { + self.variant(FSEL27_A::SD0_DAT3) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED1) + } + #[doc = "Pin is connected to DPI_D23"] + #[inline(always)] + pub fn dpi_d23(self) -> &'a mut W { + self.variant(FSEL27_A::DPI_D23) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL27_A::SD1_DAT3) + } + #[doc = "Pin is connected to ARM_TMS"] + #[inline(always)] + pub fn arm_tms(self) -> &'a mut W { + self.variant(FSEL27_A::ARM_TMS) + } + #[doc = "Pin is connected to SPI6_CE1_N"] + #[inline(always)] + pub fn spi6_ce1_n(self) -> &'a mut W { + self.variant(FSEL27_A::SPI6_CE1_N) + } +} +#[doc = "Field `FSEL28` reader - Function Select 28"] +pub type FSEL28_R = crate::FieldReader; +#[doc = "Function Select 28"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL28_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA0"] + SDA0 = 4, + #[doc = "5: Pin is connected to SA5"] + SA5 = 5, + #[doc = "6: Pin is connected to PCM_CLK"] + PCM_CLK = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to MII_A_RX_ERR"] + MII_A_RX_ERR = 3, + #[doc = "2: Pin is connected to RGMII_MDIO"] + RGMII_MDIO = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL28_A) -> Self { + variant as _ + } +} +impl FSEL28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL28_A { + match self.bits { + 0 => FSEL28_A::INPUT, + 1 => FSEL28_A::OUTPUT, + 4 => FSEL28_A::SDA0, + 5 => FSEL28_A::SA5, + 6 => FSEL28_A::PCM_CLK, + 7 => FSEL28_A::RESERVED3, + 3 => FSEL28_A::MII_A_RX_ERR, + 2 => FSEL28_A::RGMII_MDIO, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL28_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL28_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL28_A::SDA0 + } + #[doc = "Checks if the value of the field is `SA5`"] + #[inline(always)] + pub fn is_sa5(&self) -> bool { + *self == FSEL28_A::SA5 + } + #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[inline(always)] + pub fn is_pcm_clk(&self) -> bool { + *self == FSEL28_A::PCM_CLK + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL28_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `MII_A_RX_ERR`"] + #[inline(always)] + pub fn is_mii_a_rx_err(&self) -> bool { + *self == FSEL28_A::MII_A_RX_ERR + } + #[doc = "Checks if the value of the field is `RGMII_MDIO`"] + #[inline(always)] + pub fn is_rgmii_mdio(&self) -> bool { + *self == FSEL28_A::RGMII_MDIO + } +} +#[doc = "Field `FSEL28` writer - Function Select 28"] +pub type FSEL28_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL28_A, 3, O>; +impl<'a, const O: u8> FSEL28_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL28_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL28_A::OUTPUT) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL28_A::SDA0) + } + #[doc = "Pin is connected to SA5"] + #[inline(always)] + pub fn sa5(self) -> &'a mut W { + self.variant(FSEL28_A::SA5) + } + #[doc = "Pin is connected to PCM_CLK"] + #[inline(always)] + pub fn pcm_clk(self) -> &'a mut W { + self.variant(FSEL28_A::PCM_CLK) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED3) + } + #[doc = "Pin is connected to MII_A_RX_ERR"] + #[inline(always)] + pub fn mii_a_rx_err(self) -> &'a mut W { + self.variant(FSEL28_A::MII_A_RX_ERR) + } + #[doc = "Pin is connected to RGMII_MDIO"] + #[inline(always)] + pub fn rgmii_mdio(self) -> &'a mut W { + self.variant(FSEL28_A::RGMII_MDIO) + } +} +#[doc = "Field `FSEL29` reader - Function Select 29"] +pub type FSEL29_R = crate::FieldReader; +#[doc = "Function Select 29"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL29_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL0"] + SCL0 = 4, + #[doc = "5: Pin is connected to SA4"] + SA4 = 5, + #[doc = "6: Pin is connected to PCM_FS"] + PCM_FS = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to MII_A_TX_ERR"] + MII_A_TX_ERR = 3, + #[doc = "2: Pin is connected to RGMII_MDC"] + RGMII_MDC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL29_A) -> Self { + variant as _ + } +} +impl FSEL29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL29_A { + match self.bits { + 0 => FSEL29_A::INPUT, + 1 => FSEL29_A::OUTPUT, + 4 => FSEL29_A::SCL0, + 5 => FSEL29_A::SA4, + 6 => FSEL29_A::PCM_FS, + 7 => FSEL29_A::RESERVED3, + 3 => FSEL29_A::MII_A_TX_ERR, + 2 => FSEL29_A::RGMII_MDC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL29_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL29_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL29_A::SCL0 + } + #[doc = "Checks if the value of the field is `SA4`"] + #[inline(always)] + pub fn is_sa4(&self) -> bool { + *self == FSEL29_A::SA4 + } + #[doc = "Checks if the value of the field is `PCM_FS`"] + #[inline(always)] + pub fn is_pcm_fs(&self) -> bool { + *self == FSEL29_A::PCM_FS + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL29_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `MII_A_TX_ERR`"] + #[inline(always)] + pub fn is_mii_a_tx_err(&self) -> bool { + *self == FSEL29_A::MII_A_TX_ERR + } + #[doc = "Checks if the value of the field is `RGMII_MDC`"] + #[inline(always)] + pub fn is_rgmii_mdc(&self) -> bool { + *self == FSEL29_A::RGMII_MDC + } +} +#[doc = "Field `FSEL29` writer - Function Select 29"] +pub type FSEL29_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL29_A, 3, O>; +impl<'a, const O: u8> FSEL29_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL29_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL29_A::OUTPUT) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL29_A::SCL0) + } + #[doc = "Pin is connected to SA4"] + #[inline(always)] + pub fn sa4(self) -> &'a mut W { + self.variant(FSEL29_A::SA4) + } + #[doc = "Pin is connected to PCM_FS"] + #[inline(always)] + pub fn pcm_fs(self) -> &'a mut W { + self.variant(FSEL29_A::PCM_FS) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED3) + } + #[doc = "Pin is connected to MII_A_TX_ERR"] + #[inline(always)] + pub fn mii_a_tx_err(self) -> &'a mut W { + self.variant(FSEL29_A::MII_A_TX_ERR) + } + #[doc = "Pin is connected to RGMII_MDC"] + #[inline(always)] + pub fn rgmii_mdc(self) -> &'a mut W { + self.variant(FSEL29_A::RGMII_MDC) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 20"] + #[inline(always)] + pub fn fsel20(&self) -> FSEL20_R { + FSEL20_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 21"] + #[inline(always)] + pub fn fsel21(&self) -> FSEL21_R { + FSEL21_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 22"] + #[inline(always)] + pub fn fsel22(&self) -> FSEL22_R { + FSEL22_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 23"] + #[inline(always)] + pub fn fsel23(&self) -> FSEL23_R { + FSEL23_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 24"] + #[inline(always)] + pub fn fsel24(&self) -> FSEL24_R { + FSEL24_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 25"] + #[inline(always)] + pub fn fsel25(&self) -> FSEL25_R { + FSEL25_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 26"] + #[inline(always)] + pub fn fsel26(&self) -> FSEL26_R { + FSEL26_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 27"] + #[inline(always)] + pub fn fsel27(&self) -> FSEL27_R { + FSEL27_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 28"] + #[inline(always)] + pub fn fsel28(&self) -> FSEL28_R { + FSEL28_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 29"] + #[inline(always)] + pub fn fsel29(&self) -> FSEL29_R { + FSEL29_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 20"] + #[inline(always)] + #[must_use] + pub fn fsel20(&mut self) -> FSEL20_W<0> { + FSEL20_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 21"] + #[inline(always)] + #[must_use] + pub fn fsel21(&mut self) -> FSEL21_W<3> { + FSEL21_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 22"] + #[inline(always)] + #[must_use] + pub fn fsel22(&mut self) -> FSEL22_W<6> { + FSEL22_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 23"] + #[inline(always)] + #[must_use] + pub fn fsel23(&mut self) -> FSEL23_W<9> { + FSEL23_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 24"] + #[inline(always)] + #[must_use] + pub fn fsel24(&mut self) -> FSEL24_W<12> { + FSEL24_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 25"] + #[inline(always)] + #[must_use] + pub fn fsel25(&mut self) -> FSEL25_W<15> { + FSEL25_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 26"] + #[inline(always)] + #[must_use] + pub fn fsel26(&mut self) -> FSEL26_W<18> { + FSEL26_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 27"] + #[inline(always)] + #[must_use] + pub fn fsel27(&mut self) -> FSEL27_W<21> { + FSEL27_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 28"] + #[inline(always)] + #[must_use] + pub fn fsel28(&mut self) -> FSEL28_W<24> { + FSEL28_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 29"] + #[inline(always)] + #[must_use] + pub fn fsel29(&mut self) -> FSEL29_W<27> { + FSEL29_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel2](index.html) module"] +pub struct GPFSEL2_SPEC; +impl crate::RegisterSpec for GPFSEL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel2::R](R) reader structure"] +impl crate::Readable for GPFSEL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel2::W](W) writer structure"] +impl crate::Writable for GPFSEL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel3.rs b/crates/bcm2711-lpa/src/gpio/gpfsel3.rs new file mode 100644 index 0000000..892eabb --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfsel3.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL30` reader - Function Select 30"] +pub type FSEL30_R = crate::FieldReader; +#[doc = "Function Select 30"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL30_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA3"] + SA3 = 5, + #[doc = "6: Pin is connected to PCM_DIN"] + PCM_DIN = 6, + #[doc = "7: Pin is connected to CTS0"] + CTS0 = 7, + #[doc = "3: Pin is connected to MII_A_CRS"] + MII_A_CRS = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL30_A) -> Self { + variant as _ + } +} +impl FSEL30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL30_A { + match self.bits { + 0 => FSEL30_A::INPUT, + 1 => FSEL30_A::OUTPUT, + 4 => FSEL30_A::RESERVED0, + 5 => FSEL30_A::SA3, + 6 => FSEL30_A::PCM_DIN, + 7 => FSEL30_A::CTS0, + 3 => FSEL30_A::MII_A_CRS, + 2 => FSEL30_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL30_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL30_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL30_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA3`"] + #[inline(always)] + pub fn is_sa3(&self) -> bool { + *self == FSEL30_A::SA3 + } + #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[inline(always)] + pub fn is_pcm_din(&self) -> bool { + *self == FSEL30_A::PCM_DIN + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL30_A::CTS0 + } + #[doc = "Checks if the value of the field is `MII_A_CRS`"] + #[inline(always)] + pub fn is_mii_a_crs(&self) -> bool { + *self == FSEL30_A::MII_A_CRS + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL30_A::CTS1 + } +} +#[doc = "Field `FSEL30` writer - Function Select 30"] +pub type FSEL30_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL30_A, 3, O>; +impl<'a, const O: u8> FSEL30_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL30_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL30_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL30_A::RESERVED0) + } + #[doc = "Pin is connected to SA3"] + #[inline(always)] + pub fn sa3(self) -> &'a mut W { + self.variant(FSEL30_A::SA3) + } + #[doc = "Pin is connected to PCM_DIN"] + #[inline(always)] + pub fn pcm_din(self) -> &'a mut W { + self.variant(FSEL30_A::PCM_DIN) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL30_A::CTS0) + } + #[doc = "Pin is connected to MII_A_CRS"] + #[inline(always)] + pub fn mii_a_crs(self) -> &'a mut W { + self.variant(FSEL30_A::MII_A_CRS) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL30_A::CTS1) + } +} +#[doc = "Field `FSEL31` reader - Function Select 31"] +pub type FSEL31_R = crate::FieldReader; +#[doc = "Function Select 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL31_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA2"] + SA2 = 5, + #[doc = "6: Pin is connected to PCM_DOUT"] + PCM_DOUT = 6, + #[doc = "7: Pin is connected to RTS0"] + RTS0 = 7, + #[doc = "3: Pin is connected to MII_A_COL"] + MII_A_COL = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL31_A) -> Self { + variant as _ + } +} +impl FSEL31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL31_A { + match self.bits { + 0 => FSEL31_A::INPUT, + 1 => FSEL31_A::OUTPUT, + 4 => FSEL31_A::RESERVED0, + 5 => FSEL31_A::SA2, + 6 => FSEL31_A::PCM_DOUT, + 7 => FSEL31_A::RTS0, + 3 => FSEL31_A::MII_A_COL, + 2 => FSEL31_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL31_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL31_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL31_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA2`"] + #[inline(always)] + pub fn is_sa2(&self) -> bool { + *self == FSEL31_A::SA2 + } + #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[inline(always)] + pub fn is_pcm_dout(&self) -> bool { + *self == FSEL31_A::PCM_DOUT + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL31_A::RTS0 + } + #[doc = "Checks if the value of the field is `MII_A_COL`"] + #[inline(always)] + pub fn is_mii_a_col(&self) -> bool { + *self == FSEL31_A::MII_A_COL + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL31_A::RTS1 + } +} +#[doc = "Field `FSEL31` writer - Function Select 31"] +pub type FSEL31_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL31_A, 3, O>; +impl<'a, const O: u8> FSEL31_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL31_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL31_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL31_A::RESERVED0) + } + #[doc = "Pin is connected to SA2"] + #[inline(always)] + pub fn sa2(self) -> &'a mut W { + self.variant(FSEL31_A::SA2) + } + #[doc = "Pin is connected to PCM_DOUT"] + #[inline(always)] + pub fn pcm_dout(self) -> &'a mut W { + self.variant(FSEL31_A::PCM_DOUT) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL31_A::RTS0) + } + #[doc = "Pin is connected to MII_A_COL"] + #[inline(always)] + pub fn mii_a_col(self) -> &'a mut W { + self.variant(FSEL31_A::MII_A_COL) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL31_A::RTS1) + } +} +#[doc = "Field `FSEL32` reader - Function Select 32"] +pub type FSEL32_R = crate::FieldReader; +#[doc = "Function Select 32"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL32_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SA1"] + SA1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to TXD0"] + TXD0 = 7, + #[doc = "3: Pin is connected to SD_CARD_PRES"] + SD_CARD_PRES = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL32_A) -> Self { + variant as _ + } +} +impl FSEL32_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL32_A { + match self.bits { + 0 => FSEL32_A::INPUT, + 1 => FSEL32_A::OUTPUT, + 4 => FSEL32_A::GPCLK0, + 5 => FSEL32_A::SA1, + 6 => FSEL32_A::RESERVED2, + 7 => FSEL32_A::TXD0, + 3 => FSEL32_A::SD_CARD_PRES, + 2 => FSEL32_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL32_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL32_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL32_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SA1`"] + #[inline(always)] + pub fn is_sa1(&self) -> bool { + *self == FSEL32_A::SA1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL32_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL32_A::TXD0 + } + #[doc = "Checks if the value of the field is `SD_CARD_PRES`"] + #[inline(always)] + pub fn is_sd_card_pres(&self) -> bool { + *self == FSEL32_A::SD_CARD_PRES + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL32_A::TXD1 + } +} +#[doc = "Field `FSEL32` writer - Function Select 32"] +pub type FSEL32_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL32_A, 3, O>; +impl<'a, const O: u8> FSEL32_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL32_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL32_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL32_A::GPCLK0) + } + #[doc = "Pin is connected to SA1"] + #[inline(always)] + pub fn sa1(self) -> &'a mut W { + self.variant(FSEL32_A::SA1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL32_A::RESERVED2) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL32_A::TXD0) + } + #[doc = "Pin is connected to SD_CARD_PRES"] + #[inline(always)] + pub fn sd_card_pres(self) -> &'a mut W { + self.variant(FSEL32_A::SD_CARD_PRES) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL32_A::TXD1) + } +} +#[doc = "Field `FSEL33` reader - Function Select 33"] +pub type FSEL33_R = crate::FieldReader; +#[doc = "Function Select 33"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL33_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA0"] + SA0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to RXD0"] + RXD0 = 7, + #[doc = "3: Pin is connected to SD_CARD_WRPROT"] + SD_CARD_WRPROT = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL33_A) -> Self { + variant as _ + } +} +impl FSEL33_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL33_A { + match self.bits { + 0 => FSEL33_A::INPUT, + 1 => FSEL33_A::OUTPUT, + 4 => FSEL33_A::RESERVED0, + 5 => FSEL33_A::SA0, + 6 => FSEL33_A::RESERVED2, + 7 => FSEL33_A::RXD0, + 3 => FSEL33_A::SD_CARD_WRPROT, + 2 => FSEL33_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL33_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL33_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL33_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA0`"] + #[inline(always)] + pub fn is_sa0(&self) -> bool { + *self == FSEL33_A::SA0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL33_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL33_A::RXD0 + } + #[doc = "Checks if the value of the field is `SD_CARD_WRPROT`"] + #[inline(always)] + pub fn is_sd_card_wrprot(&self) -> bool { + *self == FSEL33_A::SD_CARD_WRPROT + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL33_A::RXD1 + } +} +#[doc = "Field `FSEL33` writer - Function Select 33"] +pub type FSEL33_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL33_A, 3, O>; +impl<'a, const O: u8> FSEL33_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL33_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL33_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED0) + } + #[doc = "Pin is connected to SA0"] + #[inline(always)] + pub fn sa0(self) -> &'a mut W { + self.variant(FSEL33_A::SA0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED2) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL33_A::RXD0) + } + #[doc = "Pin is connected to SD_CARD_WRPROT"] + #[inline(always)] + pub fn sd_card_wrprot(self) -> &'a mut W { + self.variant(FSEL33_A::SD_CARD_WRPROT) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL33_A::RXD1) + } +} +#[doc = "Field `FSEL34` reader - Function Select 34"] +pub type FSEL34_R = crate::FieldReader; +#[doc = "Function Select 34"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL34_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SOE_N"] + SOE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Pin is connected to SD_CARD_LED"] + SD_CARD_LED = 3, + #[doc = "2: Pin is connected to RGMII_IRQ"] + RGMII_IRQ = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL34_A) -> Self { + variant as _ + } +} +impl FSEL34_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL34_A { + match self.bits { + 0 => FSEL34_A::INPUT, + 1 => FSEL34_A::OUTPUT, + 4 => FSEL34_A::GPCLK0, + 5 => FSEL34_A::SOE_N, + 6 => FSEL34_A::RESERVED2, + 7 => FSEL34_A::SD1_CLK, + 3 => FSEL34_A::SD_CARD_LED, + 2 => FSEL34_A::RGMII_IRQ, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL34_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL34_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL34_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SOE_N`"] + #[inline(always)] + pub fn is_soe_n(&self) -> bool { + *self == FSEL34_A::SOE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL34_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL34_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `SD_CARD_LED`"] + #[inline(always)] + pub fn is_sd_card_led(&self) -> bool { + *self == FSEL34_A::SD_CARD_LED + } + #[doc = "Checks if the value of the field is `RGMII_IRQ`"] + #[inline(always)] + pub fn is_rgmii_irq(&self) -> bool { + *self == FSEL34_A::RGMII_IRQ + } +} +#[doc = "Field `FSEL34` writer - Function Select 34"] +pub type FSEL34_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL34_A, 3, O>; +impl<'a, const O: u8> FSEL34_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL34_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL34_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL34_A::GPCLK0) + } + #[doc = "Pin is connected to SOE_N"] + #[inline(always)] + pub fn soe_n(self) -> &'a mut W { + self.variant(FSEL34_A::SOE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL34_A::SD1_CLK) + } + #[doc = "Pin is connected to SD_CARD_LED"] + #[inline(always)] + pub fn sd_card_led(self) -> &'a mut W { + self.variant(FSEL34_A::SD_CARD_LED) + } + #[doc = "Pin is connected to RGMII_IRQ"] + #[inline(always)] + pub fn rgmii_irq(self) -> &'a mut W { + self.variant(FSEL34_A::RGMII_IRQ) + } +} +#[doc = "Field `FSEL35` reader - Function Select 35"] +pub type FSEL35_R = crate::FieldReader; +#[doc = "Function Select 35"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL35_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE1_N"] + SPI0_CE1_N = 4, + #[doc = "5: Pin is connected to SWE_N"] + SWE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Pin is connected to RGMII_START_STOP"] + RGMII_START_STOP = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL35_A) -> Self { + variant as _ + } +} +impl FSEL35_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL35_A { + match self.bits { + 0 => FSEL35_A::INPUT, + 1 => FSEL35_A::OUTPUT, + 4 => FSEL35_A::SPI0_CE1_N, + 5 => FSEL35_A::SWE_N, + 6 => FSEL35_A::RESERVED2, + 7 => FSEL35_A::SD1_CMD, + 3 => FSEL35_A::RGMII_START_STOP, + 2 => FSEL35_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL35_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL35_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[inline(always)] + pub fn is_spi0_ce1_n(&self) -> bool { + *self == FSEL35_A::SPI0_CE1_N + } + #[doc = "Checks if the value of the field is `SWE_N`"] + #[inline(always)] + pub fn is_swe_n(&self) -> bool { + *self == FSEL35_A::SWE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL35_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL35_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `RGMII_START_STOP`"] + #[inline(always)] + pub fn is_rgmii_start_stop(&self) -> bool { + *self == FSEL35_A::RGMII_START_STOP + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL35_A::RESERVED5 + } +} +#[doc = "Field `FSEL35` writer - Function Select 35"] +pub type FSEL35_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL35_A, 3, O>; +impl<'a, const O: u8> FSEL35_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL35_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL35_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE1_N"] + #[inline(always)] + pub fn spi0_ce1_n(self) -> &'a mut W { + self.variant(FSEL35_A::SPI0_CE1_N) + } + #[doc = "Pin is connected to SWE_N"] + #[inline(always)] + pub fn swe_n(self) -> &'a mut W { + self.variant(FSEL35_A::SWE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL35_A::SD1_CMD) + } + #[doc = "Pin is connected to RGMII_START_STOP"] + #[inline(always)] + pub fn rgmii_start_stop(self) -> &'a mut W { + self.variant(FSEL35_A::RGMII_START_STOP) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED5) + } +} +#[doc = "Field `FSEL36` reader - Function Select 36"] +pub type FSEL36_R = crate::FieldReader; +#[doc = "Function Select 36"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL36_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE0_N"] + SPI0_CE0_N = 4, + #[doc = "5: Pin is connected to SD0"] + SD0 = 5, + #[doc = "6: Pin is connected to TXD0"] + TXD0 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Pin is connected to RGMII_RX_OK"] + RGMII_RX_OK = 3, + #[doc = "2: Pin is connected to MII_A_RX_ERR"] + MII_A_RX_ERR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL36_A) -> Self { + variant as _ + } +} +impl FSEL36_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL36_A { + match self.bits { + 0 => FSEL36_A::INPUT, + 1 => FSEL36_A::OUTPUT, + 4 => FSEL36_A::SPI0_CE0_N, + 5 => FSEL36_A::SD0, + 6 => FSEL36_A::TXD0, + 7 => FSEL36_A::SD1_DAT0, + 3 => FSEL36_A::RGMII_RX_OK, + 2 => FSEL36_A::MII_A_RX_ERR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL36_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL36_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[inline(always)] + pub fn is_spi0_ce0_n(&self) -> bool { + *self == FSEL36_A::SPI0_CE0_N + } + #[doc = "Checks if the value of the field is `SD0`"] + #[inline(always)] + pub fn is_sd0(&self) -> bool { + *self == FSEL36_A::SD0 + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL36_A::TXD0 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL36_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `RGMII_RX_OK`"] + #[inline(always)] + pub fn is_rgmii_rx_ok(&self) -> bool { + *self == FSEL36_A::RGMII_RX_OK + } + #[doc = "Checks if the value of the field is `MII_A_RX_ERR`"] + #[inline(always)] + pub fn is_mii_a_rx_err(&self) -> bool { + *self == FSEL36_A::MII_A_RX_ERR + } +} +#[doc = "Field `FSEL36` writer - Function Select 36"] +pub type FSEL36_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL36_A, 3, O>; +impl<'a, const O: u8> FSEL36_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL36_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL36_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE0_N"] + #[inline(always)] + pub fn spi0_ce0_n(self) -> &'a mut W { + self.variant(FSEL36_A::SPI0_CE0_N) + } + #[doc = "Pin is connected to SD0"] + #[inline(always)] + pub fn sd0(self) -> &'a mut W { + self.variant(FSEL36_A::SD0) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL36_A::TXD0) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL36_A::SD1_DAT0) + } + #[doc = "Pin is connected to RGMII_RX_OK"] + #[inline(always)] + pub fn rgmii_rx_ok(self) -> &'a mut W { + self.variant(FSEL36_A::RGMII_RX_OK) + } + #[doc = "Pin is connected to MII_A_RX_ERR"] + #[inline(always)] + pub fn mii_a_rx_err(self) -> &'a mut W { + self.variant(FSEL36_A::MII_A_RX_ERR) + } +} +#[doc = "Field `FSEL37` reader - Function Select 37"] +pub type FSEL37_R = crate::FieldReader; +#[doc = "Function Select 37"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL37_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MISO"] + SPI0_MISO = 4, + #[doc = "5: Pin is connected to SD1"] + SD1 = 5, + #[doc = "6: Pin is connected to RXD0"] + RXD0 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Pin is connected to RGMII_MDIO"] + RGMII_MDIO = 3, + #[doc = "2: Pin is connected to MII_A_TX_ERR"] + MII_A_TX_ERR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL37_A) -> Self { + variant as _ + } +} +impl FSEL37_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL37_A { + match self.bits { + 0 => FSEL37_A::INPUT, + 1 => FSEL37_A::OUTPUT, + 4 => FSEL37_A::SPI0_MISO, + 5 => FSEL37_A::SD1, + 6 => FSEL37_A::RXD0, + 7 => FSEL37_A::SD1_DAT1, + 3 => FSEL37_A::RGMII_MDIO, + 2 => FSEL37_A::MII_A_TX_ERR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL37_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL37_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[inline(always)] + pub fn is_spi0_miso(&self) -> bool { + *self == FSEL37_A::SPI0_MISO + } + #[doc = "Checks if the value of the field is `SD1`"] + #[inline(always)] + pub fn is_sd1(&self) -> bool { + *self == FSEL37_A::SD1 + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL37_A::RXD0 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL37_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `RGMII_MDIO`"] + #[inline(always)] + pub fn is_rgmii_mdio(&self) -> bool { + *self == FSEL37_A::RGMII_MDIO + } + #[doc = "Checks if the value of the field is `MII_A_TX_ERR`"] + #[inline(always)] + pub fn is_mii_a_tx_err(&self) -> bool { + *self == FSEL37_A::MII_A_TX_ERR + } +} +#[doc = "Field `FSEL37` writer - Function Select 37"] +pub type FSEL37_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL37_A, 3, O>; +impl<'a, const O: u8> FSEL37_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL37_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL37_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MISO"] + #[inline(always)] + pub fn spi0_miso(self) -> &'a mut W { + self.variant(FSEL37_A::SPI0_MISO) + } + #[doc = "Pin is connected to SD1"] + #[inline(always)] + pub fn sd1(self) -> &'a mut W { + self.variant(FSEL37_A::SD1) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL37_A::RXD0) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL37_A::SD1_DAT1) + } + #[doc = "Pin is connected to RGMII_MDIO"] + #[inline(always)] + pub fn rgmii_mdio(self) -> &'a mut W { + self.variant(FSEL37_A::RGMII_MDIO) + } + #[doc = "Pin is connected to MII_A_TX_ERR"] + #[inline(always)] + pub fn mii_a_tx_err(self) -> &'a mut W { + self.variant(FSEL37_A::MII_A_TX_ERR) + } +} +#[doc = "Field `FSEL38` reader - Function Select 38"] +pub type FSEL38_R = crate::FieldReader; +#[doc = "Function Select 38"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL38_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MOSI"] + SPI0_MOSI = 4, + #[doc = "5: Pin is connected to SD2"] + SD2 = 5, + #[doc = "6: Pin is connected to CTS0"] + CTS0 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Pin is connected to RGMII_MDC"] + RGMII_MDC = 3, + #[doc = "2: Pin is connected to MII_A_CRS"] + MII_A_CRS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL38_A) -> Self { + variant as _ + } +} +impl FSEL38_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL38_A { + match self.bits { + 0 => FSEL38_A::INPUT, + 1 => FSEL38_A::OUTPUT, + 4 => FSEL38_A::SPI0_MOSI, + 5 => FSEL38_A::SD2, + 6 => FSEL38_A::CTS0, + 7 => FSEL38_A::SD1_DAT2, + 3 => FSEL38_A::RGMII_MDC, + 2 => FSEL38_A::MII_A_CRS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL38_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL38_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[inline(always)] + pub fn is_spi0_mosi(&self) -> bool { + *self == FSEL38_A::SPI0_MOSI + } + #[doc = "Checks if the value of the field is `SD2`"] + #[inline(always)] + pub fn is_sd2(&self) -> bool { + *self == FSEL38_A::SD2 + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL38_A::CTS0 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL38_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `RGMII_MDC`"] + #[inline(always)] + pub fn is_rgmii_mdc(&self) -> bool { + *self == FSEL38_A::RGMII_MDC + } + #[doc = "Checks if the value of the field is `MII_A_CRS`"] + #[inline(always)] + pub fn is_mii_a_crs(&self) -> bool { + *self == FSEL38_A::MII_A_CRS + } +} +#[doc = "Field `FSEL38` writer - Function Select 38"] +pub type FSEL38_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL38_A, 3, O>; +impl<'a, const O: u8> FSEL38_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL38_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL38_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MOSI"] + #[inline(always)] + pub fn spi0_mosi(self) -> &'a mut W { + self.variant(FSEL38_A::SPI0_MOSI) + } + #[doc = "Pin is connected to SD2"] + #[inline(always)] + pub fn sd2(self) -> &'a mut W { + self.variant(FSEL38_A::SD2) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL38_A::CTS0) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL38_A::SD1_DAT2) + } + #[doc = "Pin is connected to RGMII_MDC"] + #[inline(always)] + pub fn rgmii_mdc(self) -> &'a mut W { + self.variant(FSEL38_A::RGMII_MDC) + } + #[doc = "Pin is connected to MII_A_CRS"] + #[inline(always)] + pub fn mii_a_crs(self) -> &'a mut W { + self.variant(FSEL38_A::MII_A_CRS) + } +} +#[doc = "Field `FSEL39` reader - Function Select 39"] +pub type FSEL39_R = crate::FieldReader; +#[doc = "Function Select 39"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL39_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_SCLK"] + SPI0_SCLK = 4, + #[doc = "5: Pin is connected to SD3"] + SD3 = 5, + #[doc = "6: Pin is connected to RTS0"] + RTS0 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Pin is connected to RGMII_IRQ"] + RGMII_IRQ = 3, + #[doc = "2: Pin is connected to MII_A_COL"] + MII_A_COL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL39_A) -> Self { + variant as _ + } +} +impl FSEL39_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL39_A { + match self.bits { + 0 => FSEL39_A::INPUT, + 1 => FSEL39_A::OUTPUT, + 4 => FSEL39_A::SPI0_SCLK, + 5 => FSEL39_A::SD3, + 6 => FSEL39_A::RTS0, + 7 => FSEL39_A::SD1_DAT3, + 3 => FSEL39_A::RGMII_IRQ, + 2 => FSEL39_A::MII_A_COL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL39_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL39_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[inline(always)] + pub fn is_spi0_sclk(&self) -> bool { + *self == FSEL39_A::SPI0_SCLK + } + #[doc = "Checks if the value of the field is `SD3`"] + #[inline(always)] + pub fn is_sd3(&self) -> bool { + *self == FSEL39_A::SD3 + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL39_A::RTS0 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL39_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `RGMII_IRQ`"] + #[inline(always)] + pub fn is_rgmii_irq(&self) -> bool { + *self == FSEL39_A::RGMII_IRQ + } + #[doc = "Checks if the value of the field is `MII_A_COL`"] + #[inline(always)] + pub fn is_mii_a_col(&self) -> bool { + *self == FSEL39_A::MII_A_COL + } +} +#[doc = "Field `FSEL39` writer - Function Select 39"] +pub type FSEL39_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL39_A, 3, O>; +impl<'a, const O: u8> FSEL39_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL39_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL39_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_SCLK"] + #[inline(always)] + pub fn spi0_sclk(self) -> &'a mut W { + self.variant(FSEL39_A::SPI0_SCLK) + } + #[doc = "Pin is connected to SD3"] + #[inline(always)] + pub fn sd3(self) -> &'a mut W { + self.variant(FSEL39_A::SD3) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL39_A::RTS0) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL39_A::SD1_DAT3) + } + #[doc = "Pin is connected to RGMII_IRQ"] + #[inline(always)] + pub fn rgmii_irq(self) -> &'a mut W { + self.variant(FSEL39_A::RGMII_IRQ) + } + #[doc = "Pin is connected to MII_A_COL"] + #[inline(always)] + pub fn mii_a_col(self) -> &'a mut W { + self.variant(FSEL39_A::MII_A_COL) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 30"] + #[inline(always)] + pub fn fsel30(&self) -> FSEL30_R { + FSEL30_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 31"] + #[inline(always)] + pub fn fsel31(&self) -> FSEL31_R { + FSEL31_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 32"] + #[inline(always)] + pub fn fsel32(&self) -> FSEL32_R { + FSEL32_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 33"] + #[inline(always)] + pub fn fsel33(&self) -> FSEL33_R { + FSEL33_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 34"] + #[inline(always)] + pub fn fsel34(&self) -> FSEL34_R { + FSEL34_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 35"] + #[inline(always)] + pub fn fsel35(&self) -> FSEL35_R { + FSEL35_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 36"] + #[inline(always)] + pub fn fsel36(&self) -> FSEL36_R { + FSEL36_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 37"] + #[inline(always)] + pub fn fsel37(&self) -> FSEL37_R { + FSEL37_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 38"] + #[inline(always)] + pub fn fsel38(&self) -> FSEL38_R { + FSEL38_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 39"] + #[inline(always)] + pub fn fsel39(&self) -> FSEL39_R { + FSEL39_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 30"] + #[inline(always)] + #[must_use] + pub fn fsel30(&mut self) -> FSEL30_W<0> { + FSEL30_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 31"] + #[inline(always)] + #[must_use] + pub fn fsel31(&mut self) -> FSEL31_W<3> { + FSEL31_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 32"] + #[inline(always)] + #[must_use] + pub fn fsel32(&mut self) -> FSEL32_W<6> { + FSEL32_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 33"] + #[inline(always)] + #[must_use] + pub fn fsel33(&mut self) -> FSEL33_W<9> { + FSEL33_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 34"] + #[inline(always)] + #[must_use] + pub fn fsel34(&mut self) -> FSEL34_W<12> { + FSEL34_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 35"] + #[inline(always)] + #[must_use] + pub fn fsel35(&mut self) -> FSEL35_W<15> { + FSEL35_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 36"] + #[inline(always)] + #[must_use] + pub fn fsel36(&mut self) -> FSEL36_W<18> { + FSEL36_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 37"] + #[inline(always)] + #[must_use] + pub fn fsel37(&mut self) -> FSEL37_W<21> { + FSEL37_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 38"] + #[inline(always)] + #[must_use] + pub fn fsel38(&mut self) -> FSEL38_W<24> { + FSEL38_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 39"] + #[inline(always)] + #[must_use] + pub fn fsel39(&mut self) -> FSEL39_W<27> { + FSEL39_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel3](index.html) module"] +pub struct GPFSEL3_SPEC; +impl crate::RegisterSpec for GPFSEL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel3::R](R) reader structure"] +impl crate::Readable for GPFSEL3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel3::W](W) writer structure"] +impl crate::Writable for GPFSEL3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel4.rs b/crates/bcm2711-lpa/src/gpio/gpfsel4.rs new file mode 100644 index 0000000..6fc84fe --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfsel4.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL40` reader - Function Select 40"] +pub type FSEL40_R = crate::FieldReader; +#[doc = "Function Select 40"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL40_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM1_0"] + PWM1_0 = 4, + #[doc = "5: Pin is connected to SD4"] + SD4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT4"] + SD1_DAT4 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL40_A) -> Self { + variant as _ + } +} +impl FSEL40_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL40_A { + match self.bits { + 0 => FSEL40_A::INPUT, + 1 => FSEL40_A::OUTPUT, + 4 => FSEL40_A::PWM1_0, + 5 => FSEL40_A::SD4, + 6 => FSEL40_A::RESERVED2, + 7 => FSEL40_A::SD1_DAT4, + 3 => FSEL40_A::RESERVED4, + 2 => FSEL40_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL40_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL40_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM1_0`"] + #[inline(always)] + pub fn is_pwm1_0(&self) -> bool { + *self == FSEL40_A::PWM1_0 + } + #[doc = "Checks if the value of the field is `SD4`"] + #[inline(always)] + pub fn is_sd4(&self) -> bool { + *self == FSEL40_A::SD4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL40_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT4`"] + #[inline(always)] + pub fn is_sd1_dat4(&self) -> bool { + *self == FSEL40_A::SD1_DAT4 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL40_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL40_A::TXD1 + } +} +#[doc = "Field `FSEL40` writer - Function Select 40"] +pub type FSEL40_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL40_A, 3, O>; +impl<'a, const O: u8> FSEL40_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL40_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL40_A::OUTPUT) + } + #[doc = "Pin is connected to PWM1_0"] + #[inline(always)] + pub fn pwm1_0(self) -> &'a mut W { + self.variant(FSEL40_A::PWM1_0) + } + #[doc = "Pin is connected to SD4"] + #[inline(always)] + pub fn sd4(self) -> &'a mut W { + self.variant(FSEL40_A::SD4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT4"] + #[inline(always)] + pub fn sd1_dat4(self) -> &'a mut W { + self.variant(FSEL40_A::SD1_DAT4) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL40_A::TXD1) + } +} +#[doc = "Field `FSEL41` reader - Function Select 41"] +pub type FSEL41_R = crate::FieldReader; +#[doc = "Function Select 41"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL41_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM1_1"] + PWM1_1 = 4, + #[doc = "5: Pin is connected to SD5"] + SD5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT5"] + SD1_DAT5 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL41_A) -> Self { + variant as _ + } +} +impl FSEL41_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL41_A { + match self.bits { + 0 => FSEL41_A::INPUT, + 1 => FSEL41_A::OUTPUT, + 4 => FSEL41_A::PWM1_1, + 5 => FSEL41_A::SD5, + 6 => FSEL41_A::RESERVED2, + 7 => FSEL41_A::SD1_DAT5, + 3 => FSEL41_A::RESERVED4, + 2 => FSEL41_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL41_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL41_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM1_1`"] + #[inline(always)] + pub fn is_pwm1_1(&self) -> bool { + *self == FSEL41_A::PWM1_1 + } + #[doc = "Checks if the value of the field is `SD5`"] + #[inline(always)] + pub fn is_sd5(&self) -> bool { + *self == FSEL41_A::SD5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL41_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT5`"] + #[inline(always)] + pub fn is_sd1_dat5(&self) -> bool { + *self == FSEL41_A::SD1_DAT5 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL41_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL41_A::RXD1 + } +} +#[doc = "Field `FSEL41` writer - Function Select 41"] +pub type FSEL41_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL41_A, 3, O>; +impl<'a, const O: u8> FSEL41_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL41_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL41_A::OUTPUT) + } + #[doc = "Pin is connected to PWM1_1"] + #[inline(always)] + pub fn pwm1_1(self) -> &'a mut W { + self.variant(FSEL41_A::PWM1_1) + } + #[doc = "Pin is connected to SD5"] + #[inline(always)] + pub fn sd5(self) -> &'a mut W { + self.variant(FSEL41_A::SD5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT5"] + #[inline(always)] + pub fn sd1_dat5(self) -> &'a mut W { + self.variant(FSEL41_A::SD1_DAT5) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL41_A::RXD1) + } +} +#[doc = "Field `FSEL42` reader - Function Select 42"] +pub type FSEL42_R = crate::FieldReader; +#[doc = "Function Select 42"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL42_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SD6"] + SD6 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT6"] + SD1_DAT6 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL42_A) -> Self { + variant as _ + } +} +impl FSEL42_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL42_A { + match self.bits { + 0 => FSEL42_A::INPUT, + 1 => FSEL42_A::OUTPUT, + 4 => FSEL42_A::GPCLK1, + 5 => FSEL42_A::SD6, + 6 => FSEL42_A::RESERVED2, + 7 => FSEL42_A::SD1_DAT6, + 3 => FSEL42_A::RESERVED4, + 2 => FSEL42_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL42_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL42_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL42_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SD6`"] + #[inline(always)] + pub fn is_sd6(&self) -> bool { + *self == FSEL42_A::SD6 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL42_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT6`"] + #[inline(always)] + pub fn is_sd1_dat6(&self) -> bool { + *self == FSEL42_A::SD1_DAT6 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL42_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL42_A::CTS1 + } +} +#[doc = "Field `FSEL42` writer - Function Select 42"] +pub type FSEL42_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL42_A, 3, O>; +impl<'a, const O: u8> FSEL42_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL42_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL42_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL42_A::GPCLK1) + } + #[doc = "Pin is connected to SD6"] + #[inline(always)] + pub fn sd6(self) -> &'a mut W { + self.variant(FSEL42_A::SD6) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT6"] + #[inline(always)] + pub fn sd1_dat6(self) -> &'a mut W { + self.variant(FSEL42_A::SD1_DAT6) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED4) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL42_A::CTS1) + } +} +#[doc = "Field `FSEL43` reader - Function Select 43"] +pub type FSEL43_R = crate::FieldReader; +#[doc = "Function Select 43"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL43_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK2"] + GPCLK2 = 4, + #[doc = "5: Pin is connected to SD7"] + SD7 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT7"] + SD1_DAT7 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL43_A) -> Self { + variant as _ + } +} +impl FSEL43_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL43_A { + match self.bits { + 0 => FSEL43_A::INPUT, + 1 => FSEL43_A::OUTPUT, + 4 => FSEL43_A::GPCLK2, + 5 => FSEL43_A::SD7, + 6 => FSEL43_A::RESERVED2, + 7 => FSEL43_A::SD1_DAT7, + 3 => FSEL43_A::RESERVED4, + 2 => FSEL43_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL43_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL43_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK2`"] + #[inline(always)] + pub fn is_gpclk2(&self) -> bool { + *self == FSEL43_A::GPCLK2 + } + #[doc = "Checks if the value of the field is `SD7`"] + #[inline(always)] + pub fn is_sd7(&self) -> bool { + *self == FSEL43_A::SD7 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL43_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT7`"] + #[inline(always)] + pub fn is_sd1_dat7(&self) -> bool { + *self == FSEL43_A::SD1_DAT7 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL43_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL43_A::RTS1 + } +} +#[doc = "Field `FSEL43` writer - Function Select 43"] +pub type FSEL43_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL43_A, 3, O>; +impl<'a, const O: u8> FSEL43_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL43_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL43_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK2"] + #[inline(always)] + pub fn gpclk2(self) -> &'a mut W { + self.variant(FSEL43_A::GPCLK2) + } + #[doc = "Pin is connected to SD7"] + #[inline(always)] + pub fn sd7(self) -> &'a mut W { + self.variant(FSEL43_A::SD7) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT7"] + #[inline(always)] + pub fn sd1_dat7(self) -> &'a mut W { + self.variant(FSEL43_A::SD1_DAT7) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED4) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL43_A::RTS1) + } +} +#[doc = "Field `FSEL44` reader - Function Select 44"] +pub type FSEL44_R = crate::FieldReader; +#[doc = "Function Select 44"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL44_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SDA0"] + SDA0 = 5, + #[doc = "6: Pin is connected to SDA1"] + SDA1 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to SD_CARD_VOLT"] + SD_CARD_VOLT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL44_A) -> Self { + variant as _ + } +} +impl FSEL44_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL44_A { + match self.bits { + 0 => FSEL44_A::INPUT, + 1 => FSEL44_A::OUTPUT, + 4 => FSEL44_A::GPCLK1, + 5 => FSEL44_A::SDA0, + 6 => FSEL44_A::SDA1, + 7 => FSEL44_A::RESERVED3, + 3 => FSEL44_A::RESERVED4, + 2 => FSEL44_A::SD_CARD_VOLT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL44_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL44_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL44_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL44_A::SDA0 + } + #[doc = "Checks if the value of the field is `SDA1`"] + #[inline(always)] + pub fn is_sda1(&self) -> bool { + *self == FSEL44_A::SDA1 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL44_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL44_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `SD_CARD_VOLT`"] + #[inline(always)] + pub fn is_sd_card_volt(&self) -> bool { + *self == FSEL44_A::SD_CARD_VOLT + } +} +#[doc = "Field `FSEL44` writer - Function Select 44"] +pub type FSEL44_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL44_A, 3, O>; +impl<'a, const O: u8> FSEL44_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL44_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL44_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL44_A::GPCLK1) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL44_A::SDA0) + } + #[doc = "Pin is connected to SDA1"] + #[inline(always)] + pub fn sda1(self) -> &'a mut W { + self.variant(FSEL44_A::SDA1) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED4) + } + #[doc = "Pin is connected to SD_CARD_VOLT"] + #[inline(always)] + pub fn sd_card_volt(self) -> &'a mut W { + self.variant(FSEL44_A::SD_CARD_VOLT) + } +} +#[doc = "Field `FSEL45` reader - Function Select 45"] +pub type FSEL45_R = crate::FieldReader; +#[doc = "Function Select 45"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL45_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SCL0"] + SCL0 = 5, + #[doc = "6: Pin is connected to SCL1"] + SCL1 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to SD_CARD_PWR0"] + SD_CARD_PWR0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL45_A) -> Self { + variant as _ + } +} +impl FSEL45_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL45_A { + match self.bits { + 0 => FSEL45_A::INPUT, + 1 => FSEL45_A::OUTPUT, + 4 => FSEL45_A::PWM0_1, + 5 => FSEL45_A::SCL0, + 6 => FSEL45_A::SCL1, + 7 => FSEL45_A::RESERVED3, + 3 => FSEL45_A::RESERVED4, + 2 => FSEL45_A::SD_CARD_PWR0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL45_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL45_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL45_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL45_A::SCL0 + } + #[doc = "Checks if the value of the field is `SCL1`"] + #[inline(always)] + pub fn is_scl1(&self) -> bool { + *self == FSEL45_A::SCL1 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL45_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL45_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `SD_CARD_PWR0`"] + #[inline(always)] + pub fn is_sd_card_pwr0(&self) -> bool { + *self == FSEL45_A::SD_CARD_PWR0 + } +} +#[doc = "Field `FSEL45` writer - Function Select 45"] +pub type FSEL45_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL45_A, 3, O>; +impl<'a, const O: u8> FSEL45_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL45_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL45_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL45_A::PWM0_1) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL45_A::SCL0) + } + #[doc = "Pin is connected to SCL1"] + #[inline(always)] + pub fn scl1(self) -> &'a mut W { + self.variant(FSEL45_A::SCL1) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED4) + } + #[doc = "Pin is connected to SD_CARD_PWR0"] + #[inline(always)] + pub fn sd_card_pwr0(self) -> &'a mut W { + self.variant(FSEL45_A::SD_CARD_PWR0) + } +} +#[doc = "Field `FSEL46` reader - Function Select 46"] +pub type FSEL46_R = crate::FieldReader; +#[doc = "Function Select 46"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL46_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL46_A) -> Self { + variant as _ + } +} +impl FSEL46_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL46_A { + match self.bits { + 0 => FSEL46_A::INPUT, + 1 => FSEL46_A::OUTPUT, + 4 => FSEL46_A::RESERVED0, + 5 => FSEL46_A::RESERVED1, + 6 => FSEL46_A::RESERVED2, + 7 => FSEL46_A::RESERVED3, + 3 => FSEL46_A::RESERVED4, + 2 => FSEL46_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL46_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL46_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL46_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL46_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL46_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL46_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL46_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL46_A::RESERVED5 + } +} +#[doc = "Field `FSEL46` writer - Function Select 46"] +pub type FSEL46_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL46_A, 3, O>; +impl<'a, const O: u8> FSEL46_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL46_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL46_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED5) + } +} +#[doc = "Field `FSEL47` reader - Function Select 47"] +pub type FSEL47_R = crate::FieldReader; +#[doc = "Function Select 47"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL47_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL47_A) -> Self { + variant as _ + } +} +impl FSEL47_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL47_A { + match self.bits { + 0 => FSEL47_A::INPUT, + 1 => FSEL47_A::OUTPUT, + 4 => FSEL47_A::RESERVED0, + 5 => FSEL47_A::RESERVED1, + 6 => FSEL47_A::RESERVED2, + 7 => FSEL47_A::RESERVED3, + 3 => FSEL47_A::RESERVED4, + 2 => FSEL47_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL47_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL47_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL47_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL47_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL47_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL47_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL47_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL47_A::RESERVED5 + } +} +#[doc = "Field `FSEL47` writer - Function Select 47"] +pub type FSEL47_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL47_A, 3, O>; +impl<'a, const O: u8> FSEL47_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL47_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL47_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED5) + } +} +#[doc = "Field `FSEL48` reader - Function Select 48"] +pub type FSEL48_R = crate::FieldReader; +#[doc = "Function Select 48"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL48_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL48_A) -> Self { + variant as _ + } +} +impl FSEL48_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL48_A { + match self.bits { + 0 => FSEL48_A::INPUT, + 1 => FSEL48_A::OUTPUT, + 4 => FSEL48_A::RESERVED0, + 5 => FSEL48_A::RESERVED1, + 6 => FSEL48_A::RESERVED2, + 7 => FSEL48_A::SD1_CLK, + 3 => FSEL48_A::RESERVED4, + 2 => FSEL48_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL48_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL48_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL48_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL48_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL48_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL48_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL48_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL48_A::RESERVED5 + } +} +#[doc = "Field `FSEL48` writer - Function Select 48"] +pub type FSEL48_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL48_A, 3, O>; +impl<'a, const O: u8> FSEL48_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL48_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL48_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL48_A::SD1_CLK) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED5) + } +} +#[doc = "Field `FSEL49` reader - Function Select 49"] +pub type FSEL49_R = crate::FieldReader; +#[doc = "Function Select 49"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL49_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL49_A) -> Self { + variant as _ + } +} +impl FSEL49_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL49_A { + match self.bits { + 0 => FSEL49_A::INPUT, + 1 => FSEL49_A::OUTPUT, + 4 => FSEL49_A::RESERVED0, + 5 => FSEL49_A::RESERVED1, + 6 => FSEL49_A::RESERVED2, + 7 => FSEL49_A::SD1_CMD, + 3 => FSEL49_A::RESERVED4, + 2 => FSEL49_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL49_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL49_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL49_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL49_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL49_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL49_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL49_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL49_A::RESERVED5 + } +} +#[doc = "Field `FSEL49` writer - Function Select 49"] +pub type FSEL49_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL49_A, 3, O>; +impl<'a, const O: u8> FSEL49_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL49_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL49_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL49_A::SD1_CMD) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 40"] + #[inline(always)] + pub fn fsel40(&self) -> FSEL40_R { + FSEL40_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 41"] + #[inline(always)] + pub fn fsel41(&self) -> FSEL41_R { + FSEL41_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 42"] + #[inline(always)] + pub fn fsel42(&self) -> FSEL42_R { + FSEL42_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 43"] + #[inline(always)] + pub fn fsel43(&self) -> FSEL43_R { + FSEL43_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 44"] + #[inline(always)] + pub fn fsel44(&self) -> FSEL44_R { + FSEL44_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 45"] + #[inline(always)] + pub fn fsel45(&self) -> FSEL45_R { + FSEL45_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 46"] + #[inline(always)] + pub fn fsel46(&self) -> FSEL46_R { + FSEL46_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 47"] + #[inline(always)] + pub fn fsel47(&self) -> FSEL47_R { + FSEL47_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 48"] + #[inline(always)] + pub fn fsel48(&self) -> FSEL48_R { + FSEL48_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 49"] + #[inline(always)] + pub fn fsel49(&self) -> FSEL49_R { + FSEL49_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 40"] + #[inline(always)] + #[must_use] + pub fn fsel40(&mut self) -> FSEL40_W<0> { + FSEL40_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 41"] + #[inline(always)] + #[must_use] + pub fn fsel41(&mut self) -> FSEL41_W<3> { + FSEL41_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 42"] + #[inline(always)] + #[must_use] + pub fn fsel42(&mut self) -> FSEL42_W<6> { + FSEL42_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 43"] + #[inline(always)] + #[must_use] + pub fn fsel43(&mut self) -> FSEL43_W<9> { + FSEL43_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 44"] + #[inline(always)] + #[must_use] + pub fn fsel44(&mut self) -> FSEL44_W<12> { + FSEL44_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 45"] + #[inline(always)] + #[must_use] + pub fn fsel45(&mut self) -> FSEL45_W<15> { + FSEL45_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 46"] + #[inline(always)] + #[must_use] + pub fn fsel46(&mut self) -> FSEL46_W<18> { + FSEL46_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 47"] + #[inline(always)] + #[must_use] + pub fn fsel47(&mut self) -> FSEL47_W<21> { + FSEL47_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 48"] + #[inline(always)] + #[must_use] + pub fn fsel48(&mut self) -> FSEL48_W<24> { + FSEL48_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 49"] + #[inline(always)] + #[must_use] + pub fn fsel49(&mut self) -> FSEL49_W<27> { + FSEL49_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel4](index.html) module"] +pub struct GPFSEL4_SPEC; +impl crate::RegisterSpec for GPFSEL4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel4::R](R) reader structure"] +impl crate::Readable for GPFSEL4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel4::W](W) writer structure"] +impl crate::Writable for GPFSEL4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel5.rs b/crates/bcm2711-lpa/src/gpio/gpfsel5.rs new file mode 100644 index 0000000..8bdd3e6 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpfsel5.rs @@ -0,0 +1,1197 @@ +#[doc = "Register `GPFSEL5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL50` reader - Function Select 50"] +pub type FSEL50_R = crate::FieldReader; +#[doc = "Function Select 50"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL50_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL50_A) -> Self { + variant as _ + } +} +impl FSEL50_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL50_A { + match self.bits { + 0 => FSEL50_A::INPUT, + 1 => FSEL50_A::OUTPUT, + 4 => FSEL50_A::RESERVED0, + 5 => FSEL50_A::RESERVED1, + 6 => FSEL50_A::RESERVED2, + 7 => FSEL50_A::SD1_DAT0, + 3 => FSEL50_A::RESERVED4, + 2 => FSEL50_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL50_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL50_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL50_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL50_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL50_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL50_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL50_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL50_A::RESERVED5 + } +} +#[doc = "Field `FSEL50` writer - Function Select 50"] +pub type FSEL50_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL50_A, 3, O>; +impl<'a, const O: u8> FSEL50_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL50_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL50_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL50_A::SD1_DAT0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED5) + } +} +#[doc = "Field `FSEL51` reader - Function Select 51"] +pub type FSEL51_R = crate::FieldReader; +#[doc = "Function Select 51"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL51_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL51_A) -> Self { + variant as _ + } +} +impl FSEL51_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL51_A { + match self.bits { + 0 => FSEL51_A::INPUT, + 1 => FSEL51_A::OUTPUT, + 4 => FSEL51_A::RESERVED0, + 5 => FSEL51_A::RESERVED1, + 6 => FSEL51_A::RESERVED2, + 7 => FSEL51_A::SD1_DAT1, + 3 => FSEL51_A::RESERVED4, + 2 => FSEL51_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL51_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL51_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL51_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL51_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL51_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL51_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL51_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL51_A::RESERVED5 + } +} +#[doc = "Field `FSEL51` writer - Function Select 51"] +pub type FSEL51_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL51_A, 3, O>; +impl<'a, const O: u8> FSEL51_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL51_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL51_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL51_A::SD1_DAT1) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED5) + } +} +#[doc = "Field `FSEL52` reader - Function Select 52"] +pub type FSEL52_R = crate::FieldReader; +#[doc = "Function Select 52"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL52_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL52_A) -> Self { + variant as _ + } +} +impl FSEL52_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL52_A { + match self.bits { + 0 => FSEL52_A::INPUT, + 1 => FSEL52_A::OUTPUT, + 4 => FSEL52_A::RESERVED0, + 5 => FSEL52_A::RESERVED1, + 6 => FSEL52_A::RESERVED2, + 7 => FSEL52_A::SD1_DAT2, + 3 => FSEL52_A::RESERVED4, + 2 => FSEL52_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL52_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL52_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL52_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL52_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL52_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL52_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL52_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL52_A::RESERVED5 + } +} +#[doc = "Field `FSEL52` writer - Function Select 52"] +pub type FSEL52_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL52_A, 3, O>; +impl<'a, const O: u8> FSEL52_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL52_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL52_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL52_A::SD1_DAT2) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED5) + } +} +#[doc = "Field `FSEL53` reader - Function Select 53"] +pub type FSEL53_R = crate::FieldReader; +#[doc = "Function Select 53"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL53_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL53_A) -> Self { + variant as _ + } +} +impl FSEL53_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL53_A { + match self.bits { + 0 => FSEL53_A::INPUT, + 1 => FSEL53_A::OUTPUT, + 4 => FSEL53_A::RESERVED0, + 5 => FSEL53_A::RESERVED1, + 6 => FSEL53_A::RESERVED2, + 7 => FSEL53_A::SD1_DAT3, + 3 => FSEL53_A::RESERVED4, + 2 => FSEL53_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL53_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL53_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL53_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL53_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL53_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL53_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL53_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL53_A::RESERVED5 + } +} +#[doc = "Field `FSEL53` writer - Function Select 53"] +pub type FSEL53_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL53_A, 3, O>; +impl<'a, const O: u8> FSEL53_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL53_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL53_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL53_A::SD1_DAT3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED5) + } +} +#[doc = "Field `FSEL54` reader - Function Select 54"] +pub type FSEL54_R = crate::FieldReader; +#[doc = "Function Select 54"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL54_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL54_A) -> Self { + variant as _ + } +} +impl FSEL54_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL54_A { + match self.bits { + 0 => FSEL54_A::INPUT, + 1 => FSEL54_A::OUTPUT, + 4 => FSEL54_A::RESERVED0, + 5 => FSEL54_A::RESERVED1, + 6 => FSEL54_A::RESERVED2, + 7 => FSEL54_A::RESERVED3, + 3 => FSEL54_A::RESERVED4, + 2 => FSEL54_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL54_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL54_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL54_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL54_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL54_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL54_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL54_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL54_A::RESERVED5 + } +} +#[doc = "Field `FSEL54` writer - Function Select 54"] +pub type FSEL54_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL54_A, 3, O>; +impl<'a, const O: u8> FSEL54_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL54_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL54_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL54_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL54_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL54_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL54_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL54_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL54_A::RESERVED5) + } +} +#[doc = "Field `FSEL55` reader - Function Select 55"] +pub type FSEL55_R = crate::FieldReader; +#[doc = "Function Select 55"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL55_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL55_A) -> Self { + variant as _ + } +} +impl FSEL55_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL55_A { + match self.bits { + 0 => FSEL55_A::INPUT, + 1 => FSEL55_A::OUTPUT, + 4 => FSEL55_A::RESERVED0, + 5 => FSEL55_A::RESERVED1, + 6 => FSEL55_A::RESERVED2, + 7 => FSEL55_A::RESERVED3, + 3 => FSEL55_A::RESERVED4, + 2 => FSEL55_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL55_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL55_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL55_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL55_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL55_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL55_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL55_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL55_A::RESERVED5 + } +} +#[doc = "Field `FSEL55` writer - Function Select 55"] +pub type FSEL55_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL55_A, 3, O>; +impl<'a, const O: u8> FSEL55_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL55_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL55_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL55_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL55_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL55_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL55_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL55_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL55_A::RESERVED5) + } +} +#[doc = "Field `FSEL56` reader - Function Select 56"] +pub type FSEL56_R = crate::FieldReader; +#[doc = "Function Select 56"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL56_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL56_A) -> Self { + variant as _ + } +} +impl FSEL56_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL56_A { + match self.bits { + 0 => FSEL56_A::INPUT, + 1 => FSEL56_A::OUTPUT, + 4 => FSEL56_A::RESERVED0, + 5 => FSEL56_A::RESERVED1, + 6 => FSEL56_A::RESERVED2, + 7 => FSEL56_A::RESERVED3, + 3 => FSEL56_A::RESERVED4, + 2 => FSEL56_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL56_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL56_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL56_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL56_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL56_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL56_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL56_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL56_A::RESERVED5 + } +} +#[doc = "Field `FSEL56` writer - Function Select 56"] +pub type FSEL56_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL56_A, 3, O>; +impl<'a, const O: u8> FSEL56_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL56_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL56_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL56_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL56_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL56_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL56_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL56_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL56_A::RESERVED5) + } +} +#[doc = "Field `FSEL57` reader - Function Select 57"] +pub type FSEL57_R = crate::FieldReader; +#[doc = "Function Select 57"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL57_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL57_A) -> Self { + variant as _ + } +} +impl FSEL57_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL57_A { + match self.bits { + 0 => FSEL57_A::INPUT, + 1 => FSEL57_A::OUTPUT, + 4 => FSEL57_A::RESERVED0, + 5 => FSEL57_A::RESERVED1, + 6 => FSEL57_A::RESERVED2, + 7 => FSEL57_A::RESERVED3, + 3 => FSEL57_A::RESERVED4, + 2 => FSEL57_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL57_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL57_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL57_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL57_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL57_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL57_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL57_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL57_A::RESERVED5 + } +} +#[doc = "Field `FSEL57` writer - Function Select 57"] +pub type FSEL57_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL57_A, 3, O>; +impl<'a, const O: u8> FSEL57_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL57_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL57_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL57_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL57_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL57_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL57_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL57_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL57_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 50"] + #[inline(always)] + pub fn fsel50(&self) -> FSEL50_R { + FSEL50_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 51"] + #[inline(always)] + pub fn fsel51(&self) -> FSEL51_R { + FSEL51_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 52"] + #[inline(always)] + pub fn fsel52(&self) -> FSEL52_R { + FSEL52_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 53"] + #[inline(always)] + pub fn fsel53(&self) -> FSEL53_R { + FSEL53_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 54"] + #[inline(always)] + pub fn fsel54(&self) -> FSEL54_R { + FSEL54_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 55"] + #[inline(always)] + pub fn fsel55(&self) -> FSEL55_R { + FSEL55_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 56"] + #[inline(always)] + pub fn fsel56(&self) -> FSEL56_R { + FSEL56_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 57"] + #[inline(always)] + pub fn fsel57(&self) -> FSEL57_R { + FSEL57_R::new(((self.bits >> 21) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 50"] + #[inline(always)] + #[must_use] + pub fn fsel50(&mut self) -> FSEL50_W<0> { + FSEL50_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 51"] + #[inline(always)] + #[must_use] + pub fn fsel51(&mut self) -> FSEL51_W<3> { + FSEL51_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 52"] + #[inline(always)] + #[must_use] + pub fn fsel52(&mut self) -> FSEL52_W<6> { + FSEL52_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 53"] + #[inline(always)] + #[must_use] + pub fn fsel53(&mut self) -> FSEL53_W<9> { + FSEL53_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 54"] + #[inline(always)] + #[must_use] + pub fn fsel54(&mut self) -> FSEL54_W<12> { + FSEL54_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 55"] + #[inline(always)] + #[must_use] + pub fn fsel55(&mut self) -> FSEL55_W<15> { + FSEL55_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 56"] + #[inline(always)] + #[must_use] + pub fn fsel56(&mut self) -> FSEL56_W<18> { + FSEL56_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 57"] + #[inline(always)] + #[must_use] + pub fn fsel57(&mut self) -> FSEL57_W<21> { + FSEL57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel5](index.html) module"] +pub struct GPFSEL5_SPEC; +impl crate::RegisterSpec for GPFSEL5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel5::R](R) reader structure"] +impl crate::Readable for GPFSEL5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel5::W](W) writer structure"] +impl crate::Writable for GPFSEL5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gphen0.rs b/crates/bcm2711-lpa/src/gpio/gphen0.rs new file mode 100644 index 0000000..b45a414 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gphen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPHEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPHEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HEN0` reader - High detect enabled 0"] +pub type HEN0_R = crate::BitReader; +#[doc = "Field `HEN0` writer - High detect enabled 0"] +pub type HEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN1` reader - High detect enabled 1"] +pub type HEN1_R = crate::BitReader; +#[doc = "Field `HEN1` writer - High detect enabled 1"] +pub type HEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN2` reader - High detect enabled 2"] +pub type HEN2_R = crate::BitReader; +#[doc = "Field `HEN2` writer - High detect enabled 2"] +pub type HEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN3` reader - High detect enabled 3"] +pub type HEN3_R = crate::BitReader; +#[doc = "Field `HEN3` writer - High detect enabled 3"] +pub type HEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN4` reader - High detect enabled 4"] +pub type HEN4_R = crate::BitReader; +#[doc = "Field `HEN4` writer - High detect enabled 4"] +pub type HEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN5` reader - High detect enabled 5"] +pub type HEN5_R = crate::BitReader; +#[doc = "Field `HEN5` writer - High detect enabled 5"] +pub type HEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN6` reader - High detect enabled 6"] +pub type HEN6_R = crate::BitReader; +#[doc = "Field `HEN6` writer - High detect enabled 6"] +pub type HEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN7` reader - High detect enabled 7"] +pub type HEN7_R = crate::BitReader; +#[doc = "Field `HEN7` writer - High detect enabled 7"] +pub type HEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN8` reader - High detect enabled 8"] +pub type HEN8_R = crate::BitReader; +#[doc = "Field `HEN8` writer - High detect enabled 8"] +pub type HEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN9` reader - High detect enabled 9"] +pub type HEN9_R = crate::BitReader; +#[doc = "Field `HEN9` writer - High detect enabled 9"] +pub type HEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN10` reader - High detect enabled 10"] +pub type HEN10_R = crate::BitReader; +#[doc = "Field `HEN10` writer - High detect enabled 10"] +pub type HEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN11` reader - High detect enabled 11"] +pub type HEN11_R = crate::BitReader; +#[doc = "Field `HEN11` writer - High detect enabled 11"] +pub type HEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN12` reader - High detect enabled 12"] +pub type HEN12_R = crate::BitReader; +#[doc = "Field `HEN12` writer - High detect enabled 12"] +pub type HEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN13` reader - High detect enabled 13"] +pub type HEN13_R = crate::BitReader; +#[doc = "Field `HEN13` writer - High detect enabled 13"] +pub type HEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN14` reader - High detect enabled 14"] +pub type HEN14_R = crate::BitReader; +#[doc = "Field `HEN14` writer - High detect enabled 14"] +pub type HEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN15` reader - High detect enabled 15"] +pub type HEN15_R = crate::BitReader; +#[doc = "Field `HEN15` writer - High detect enabled 15"] +pub type HEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN16` reader - High detect enabled 16"] +pub type HEN16_R = crate::BitReader; +#[doc = "Field `HEN16` writer - High detect enabled 16"] +pub type HEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN17` reader - High detect enabled 17"] +pub type HEN17_R = crate::BitReader; +#[doc = "Field `HEN17` writer - High detect enabled 17"] +pub type HEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN18` reader - High detect enabled 18"] +pub type HEN18_R = crate::BitReader; +#[doc = "Field `HEN18` writer - High detect enabled 18"] +pub type HEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN19` reader - High detect enabled 19"] +pub type HEN19_R = crate::BitReader; +#[doc = "Field `HEN19` writer - High detect enabled 19"] +pub type HEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN20` reader - High detect enabled 20"] +pub type HEN20_R = crate::BitReader; +#[doc = "Field `HEN20` writer - High detect enabled 20"] +pub type HEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN21` reader - High detect enabled 21"] +pub type HEN21_R = crate::BitReader; +#[doc = "Field `HEN21` writer - High detect enabled 21"] +pub type HEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN22` reader - High detect enabled 22"] +pub type HEN22_R = crate::BitReader; +#[doc = "Field `HEN22` writer - High detect enabled 22"] +pub type HEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN23` reader - High detect enabled 23"] +pub type HEN23_R = crate::BitReader; +#[doc = "Field `HEN23` writer - High detect enabled 23"] +pub type HEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN24` reader - High detect enabled 24"] +pub type HEN24_R = crate::BitReader; +#[doc = "Field `HEN24` writer - High detect enabled 24"] +pub type HEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN25` reader - High detect enabled 25"] +pub type HEN25_R = crate::BitReader; +#[doc = "Field `HEN25` writer - High detect enabled 25"] +pub type HEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN26` reader - High detect enabled 26"] +pub type HEN26_R = crate::BitReader; +#[doc = "Field `HEN26` writer - High detect enabled 26"] +pub type HEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN27` reader - High detect enabled 27"] +pub type HEN27_R = crate::BitReader; +#[doc = "Field `HEN27` writer - High detect enabled 27"] +pub type HEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN28` reader - High detect enabled 28"] +pub type HEN28_R = crate::BitReader; +#[doc = "Field `HEN28` writer - High detect enabled 28"] +pub type HEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN29` reader - High detect enabled 29"] +pub type HEN29_R = crate::BitReader; +#[doc = "Field `HEN29` writer - High detect enabled 29"] +pub type HEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN30` reader - High detect enabled 30"] +pub type HEN30_R = crate::BitReader; +#[doc = "Field `HEN30` writer - High detect enabled 30"] +pub type HEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN31` reader - High detect enabled 31"] +pub type HEN31_R = crate::BitReader; +#[doc = "Field `HEN31` writer - High detect enabled 31"] +pub type HEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - High detect enabled 0"] + #[inline(always)] + pub fn hen0(&self) -> HEN0_R { + HEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - High detect enabled 1"] + #[inline(always)] + pub fn hen1(&self) -> HEN1_R { + HEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - High detect enabled 2"] + #[inline(always)] + pub fn hen2(&self) -> HEN2_R { + HEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - High detect enabled 3"] + #[inline(always)] + pub fn hen3(&self) -> HEN3_R { + HEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - High detect enabled 4"] + #[inline(always)] + pub fn hen4(&self) -> HEN4_R { + HEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - High detect enabled 5"] + #[inline(always)] + pub fn hen5(&self) -> HEN5_R { + HEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - High detect enabled 6"] + #[inline(always)] + pub fn hen6(&self) -> HEN6_R { + HEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - High detect enabled 7"] + #[inline(always)] + pub fn hen7(&self) -> HEN7_R { + HEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - High detect enabled 8"] + #[inline(always)] + pub fn hen8(&self) -> HEN8_R { + HEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High detect enabled 9"] + #[inline(always)] + pub fn hen9(&self) -> HEN9_R { + HEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High detect enabled 10"] + #[inline(always)] + pub fn hen10(&self) -> HEN10_R { + HEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - High detect enabled 11"] + #[inline(always)] + pub fn hen11(&self) -> HEN11_R { + HEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - High detect enabled 12"] + #[inline(always)] + pub fn hen12(&self) -> HEN12_R { + HEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - High detect enabled 13"] + #[inline(always)] + pub fn hen13(&self) -> HEN13_R { + HEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High detect enabled 14"] + #[inline(always)] + pub fn hen14(&self) -> HEN14_R { + HEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - High detect enabled 15"] + #[inline(always)] + pub fn hen15(&self) -> HEN15_R { + HEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High detect enabled 16"] + #[inline(always)] + pub fn hen16(&self) -> HEN16_R { + HEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - High detect enabled 17"] + #[inline(always)] + pub fn hen17(&self) -> HEN17_R { + HEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - High detect enabled 18"] + #[inline(always)] + pub fn hen18(&self) -> HEN18_R { + HEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - High detect enabled 19"] + #[inline(always)] + pub fn hen19(&self) -> HEN19_R { + HEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - High detect enabled 20"] + #[inline(always)] + pub fn hen20(&self) -> HEN20_R { + HEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - High detect enabled 21"] + #[inline(always)] + pub fn hen21(&self) -> HEN21_R { + HEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - High detect enabled 22"] + #[inline(always)] + pub fn hen22(&self) -> HEN22_R { + HEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - High detect enabled 23"] + #[inline(always)] + pub fn hen23(&self) -> HEN23_R { + HEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - High detect enabled 24"] + #[inline(always)] + pub fn hen24(&self) -> HEN24_R { + HEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - High detect enabled 25"] + #[inline(always)] + pub fn hen25(&self) -> HEN25_R { + HEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - High detect enabled 26"] + #[inline(always)] + pub fn hen26(&self) -> HEN26_R { + HEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - High detect enabled 27"] + #[inline(always)] + pub fn hen27(&self) -> HEN27_R { + HEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - High detect enabled 28"] + #[inline(always)] + pub fn hen28(&self) -> HEN28_R { + HEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - High detect enabled 29"] + #[inline(always)] + pub fn hen29(&self) -> HEN29_R { + HEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - High detect enabled 30"] + #[inline(always)] + pub fn hen30(&self) -> HEN30_R { + HEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - High detect enabled 31"] + #[inline(always)] + pub fn hen31(&self) -> HEN31_R { + HEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - High detect enabled 0"] + #[inline(always)] + #[must_use] + pub fn hen0(&mut self) -> HEN0_W<0> { + HEN0_W::new(self) + } + #[doc = "Bit 1 - High detect enabled 1"] + #[inline(always)] + #[must_use] + pub fn hen1(&mut self) -> HEN1_W<1> { + HEN1_W::new(self) + } + #[doc = "Bit 2 - High detect enabled 2"] + #[inline(always)] + #[must_use] + pub fn hen2(&mut self) -> HEN2_W<2> { + HEN2_W::new(self) + } + #[doc = "Bit 3 - High detect enabled 3"] + #[inline(always)] + #[must_use] + pub fn hen3(&mut self) -> HEN3_W<3> { + HEN3_W::new(self) + } + #[doc = "Bit 4 - High detect enabled 4"] + #[inline(always)] + #[must_use] + pub fn hen4(&mut self) -> HEN4_W<4> { + HEN4_W::new(self) + } + #[doc = "Bit 5 - High detect enabled 5"] + #[inline(always)] + #[must_use] + pub fn hen5(&mut self) -> HEN5_W<5> { + HEN5_W::new(self) + } + #[doc = "Bit 6 - High detect enabled 6"] + #[inline(always)] + #[must_use] + pub fn hen6(&mut self) -> HEN6_W<6> { + HEN6_W::new(self) + } + #[doc = "Bit 7 - High detect enabled 7"] + #[inline(always)] + #[must_use] + pub fn hen7(&mut self) -> HEN7_W<7> { + HEN7_W::new(self) + } + #[doc = "Bit 8 - High detect enabled 8"] + #[inline(always)] + #[must_use] + pub fn hen8(&mut self) -> HEN8_W<8> { + HEN8_W::new(self) + } + #[doc = "Bit 9 - High detect enabled 9"] + #[inline(always)] + #[must_use] + pub fn hen9(&mut self) -> HEN9_W<9> { + HEN9_W::new(self) + } + #[doc = "Bit 10 - High detect enabled 10"] + #[inline(always)] + #[must_use] + pub fn hen10(&mut self) -> HEN10_W<10> { + HEN10_W::new(self) + } + #[doc = "Bit 11 - High detect enabled 11"] + #[inline(always)] + #[must_use] + pub fn hen11(&mut self) -> HEN11_W<11> { + HEN11_W::new(self) + } + #[doc = "Bit 12 - High detect enabled 12"] + #[inline(always)] + #[must_use] + pub fn hen12(&mut self) -> HEN12_W<12> { + HEN12_W::new(self) + } + #[doc = "Bit 13 - High detect enabled 13"] + #[inline(always)] + #[must_use] + pub fn hen13(&mut self) -> HEN13_W<13> { + HEN13_W::new(self) + } + #[doc = "Bit 14 - High detect enabled 14"] + #[inline(always)] + #[must_use] + pub fn hen14(&mut self) -> HEN14_W<14> { + HEN14_W::new(self) + } + #[doc = "Bit 15 - High detect enabled 15"] + #[inline(always)] + #[must_use] + pub fn hen15(&mut self) -> HEN15_W<15> { + HEN15_W::new(self) + } + #[doc = "Bit 16 - High detect enabled 16"] + #[inline(always)] + #[must_use] + pub fn hen16(&mut self) -> HEN16_W<16> { + HEN16_W::new(self) + } + #[doc = "Bit 17 - High detect enabled 17"] + #[inline(always)] + #[must_use] + pub fn hen17(&mut self) -> HEN17_W<17> { + HEN17_W::new(self) + } + #[doc = "Bit 18 - High detect enabled 18"] + #[inline(always)] + #[must_use] + pub fn hen18(&mut self) -> HEN18_W<18> { + HEN18_W::new(self) + } + #[doc = "Bit 19 - High detect enabled 19"] + #[inline(always)] + #[must_use] + pub fn hen19(&mut self) -> HEN19_W<19> { + HEN19_W::new(self) + } + #[doc = "Bit 20 - High detect enabled 20"] + #[inline(always)] + #[must_use] + pub fn hen20(&mut self) -> HEN20_W<20> { + HEN20_W::new(self) + } + #[doc = "Bit 21 - High detect enabled 21"] + #[inline(always)] + #[must_use] + pub fn hen21(&mut self) -> HEN21_W<21> { + HEN21_W::new(self) + } + #[doc = "Bit 22 - High detect enabled 22"] + #[inline(always)] + #[must_use] + pub fn hen22(&mut self) -> HEN22_W<22> { + HEN22_W::new(self) + } + #[doc = "Bit 23 - High detect enabled 23"] + #[inline(always)] + #[must_use] + pub fn hen23(&mut self) -> HEN23_W<23> { + HEN23_W::new(self) + } + #[doc = "Bit 24 - High detect enabled 24"] + #[inline(always)] + #[must_use] + pub fn hen24(&mut self) -> HEN24_W<24> { + HEN24_W::new(self) + } + #[doc = "Bit 25 - High detect enabled 25"] + #[inline(always)] + #[must_use] + pub fn hen25(&mut self) -> HEN25_W<25> { + HEN25_W::new(self) + } + #[doc = "Bit 26 - High detect enabled 26"] + #[inline(always)] + #[must_use] + pub fn hen26(&mut self) -> HEN26_W<26> { + HEN26_W::new(self) + } + #[doc = "Bit 27 - High detect enabled 27"] + #[inline(always)] + #[must_use] + pub fn hen27(&mut self) -> HEN27_W<27> { + HEN27_W::new(self) + } + #[doc = "Bit 28 - High detect enabled 28"] + #[inline(always)] + #[must_use] + pub fn hen28(&mut self) -> HEN28_W<28> { + HEN28_W::new(self) + } + #[doc = "Bit 29 - High detect enabled 29"] + #[inline(always)] + #[must_use] + pub fn hen29(&mut self) -> HEN29_W<29> { + HEN29_W::new(self) + } + #[doc = "Bit 30 - High detect enabled 30"] + #[inline(always)] + #[must_use] + pub fn hen30(&mut self) -> HEN30_W<30> { + HEN30_W::new(self) + } + #[doc = "Bit 31 - High detect enabled 31"] + #[inline(always)] + #[must_use] + pub fn hen31(&mut self) -> HEN31_W<31> { + HEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin High Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen0](index.html) module"] +pub struct GPHEN0_SPEC; +impl crate::RegisterSpec for GPHEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gphen0::R](R) reader structure"] +impl crate::Readable for GPHEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gphen0::W](W) writer structure"] +impl crate::Writable for GPHEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gphen1.rs b/crates/bcm2711-lpa/src/gpio/gphen1.rs new file mode 100644 index 0000000..1c7681b --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gphen1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPHEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPHEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HEN32` reader - High detect enabled 32"] +pub type HEN32_R = crate::BitReader; +#[doc = "Field `HEN32` writer - High detect enabled 32"] +pub type HEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN33` reader - High detect enabled 33"] +pub type HEN33_R = crate::BitReader; +#[doc = "Field `HEN33` writer - High detect enabled 33"] +pub type HEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN34` reader - High detect enabled 34"] +pub type HEN34_R = crate::BitReader; +#[doc = "Field `HEN34` writer - High detect enabled 34"] +pub type HEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN35` reader - High detect enabled 35"] +pub type HEN35_R = crate::BitReader; +#[doc = "Field `HEN35` writer - High detect enabled 35"] +pub type HEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN36` reader - High detect enabled 36"] +pub type HEN36_R = crate::BitReader; +#[doc = "Field `HEN36` writer - High detect enabled 36"] +pub type HEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN37` reader - High detect enabled 37"] +pub type HEN37_R = crate::BitReader; +#[doc = "Field `HEN37` writer - High detect enabled 37"] +pub type HEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN38` reader - High detect enabled 38"] +pub type HEN38_R = crate::BitReader; +#[doc = "Field `HEN38` writer - High detect enabled 38"] +pub type HEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN39` reader - High detect enabled 39"] +pub type HEN39_R = crate::BitReader; +#[doc = "Field `HEN39` writer - High detect enabled 39"] +pub type HEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN40` reader - High detect enabled 40"] +pub type HEN40_R = crate::BitReader; +#[doc = "Field `HEN40` writer - High detect enabled 40"] +pub type HEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN41` reader - High detect enabled 41"] +pub type HEN41_R = crate::BitReader; +#[doc = "Field `HEN41` writer - High detect enabled 41"] +pub type HEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN42` reader - High detect enabled 42"] +pub type HEN42_R = crate::BitReader; +#[doc = "Field `HEN42` writer - High detect enabled 42"] +pub type HEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN43` reader - High detect enabled 43"] +pub type HEN43_R = crate::BitReader; +#[doc = "Field `HEN43` writer - High detect enabled 43"] +pub type HEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN44` reader - High detect enabled 44"] +pub type HEN44_R = crate::BitReader; +#[doc = "Field `HEN44` writer - High detect enabled 44"] +pub type HEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN45` reader - High detect enabled 45"] +pub type HEN45_R = crate::BitReader; +#[doc = "Field `HEN45` writer - High detect enabled 45"] +pub type HEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN46` reader - High detect enabled 46"] +pub type HEN46_R = crate::BitReader; +#[doc = "Field `HEN46` writer - High detect enabled 46"] +pub type HEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN47` reader - High detect enabled 47"] +pub type HEN47_R = crate::BitReader; +#[doc = "Field `HEN47` writer - High detect enabled 47"] +pub type HEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN48` reader - High detect enabled 48"] +pub type HEN48_R = crate::BitReader; +#[doc = "Field `HEN48` writer - High detect enabled 48"] +pub type HEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN49` reader - High detect enabled 49"] +pub type HEN49_R = crate::BitReader; +#[doc = "Field `HEN49` writer - High detect enabled 49"] +pub type HEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN50` reader - High detect enabled 50"] +pub type HEN50_R = crate::BitReader; +#[doc = "Field `HEN50` writer - High detect enabled 50"] +pub type HEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN51` reader - High detect enabled 51"] +pub type HEN51_R = crate::BitReader; +#[doc = "Field `HEN51` writer - High detect enabled 51"] +pub type HEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN52` reader - High detect enabled 52"] +pub type HEN52_R = crate::BitReader; +#[doc = "Field `HEN52` writer - High detect enabled 52"] +pub type HEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN53` reader - High detect enabled 53"] +pub type HEN53_R = crate::BitReader; +#[doc = "Field `HEN53` writer - High detect enabled 53"] +pub type HEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN54` reader - High detect enabled 54"] +pub type HEN54_R = crate::BitReader; +#[doc = "Field `HEN54` writer - High detect enabled 54"] +pub type HEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN55` reader - High detect enabled 55"] +pub type HEN55_R = crate::BitReader; +#[doc = "Field `HEN55` writer - High detect enabled 55"] +pub type HEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN56` reader - High detect enabled 56"] +pub type HEN56_R = crate::BitReader; +#[doc = "Field `HEN56` writer - High detect enabled 56"] +pub type HEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN57` reader - High detect enabled 57"] +pub type HEN57_R = crate::BitReader; +#[doc = "Field `HEN57` writer - High detect enabled 57"] +pub type HEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - High detect enabled 32"] + #[inline(always)] + pub fn hen32(&self) -> HEN32_R { + HEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - High detect enabled 33"] + #[inline(always)] + pub fn hen33(&self) -> HEN33_R { + HEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - High detect enabled 34"] + #[inline(always)] + pub fn hen34(&self) -> HEN34_R { + HEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - High detect enabled 35"] + #[inline(always)] + pub fn hen35(&self) -> HEN35_R { + HEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - High detect enabled 36"] + #[inline(always)] + pub fn hen36(&self) -> HEN36_R { + HEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - High detect enabled 37"] + #[inline(always)] + pub fn hen37(&self) -> HEN37_R { + HEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - High detect enabled 38"] + #[inline(always)] + pub fn hen38(&self) -> HEN38_R { + HEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - High detect enabled 39"] + #[inline(always)] + pub fn hen39(&self) -> HEN39_R { + HEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - High detect enabled 40"] + #[inline(always)] + pub fn hen40(&self) -> HEN40_R { + HEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High detect enabled 41"] + #[inline(always)] + pub fn hen41(&self) -> HEN41_R { + HEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High detect enabled 42"] + #[inline(always)] + pub fn hen42(&self) -> HEN42_R { + HEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - High detect enabled 43"] + #[inline(always)] + pub fn hen43(&self) -> HEN43_R { + HEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - High detect enabled 44"] + #[inline(always)] + pub fn hen44(&self) -> HEN44_R { + HEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - High detect enabled 45"] + #[inline(always)] + pub fn hen45(&self) -> HEN45_R { + HEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High detect enabled 46"] + #[inline(always)] + pub fn hen46(&self) -> HEN46_R { + HEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - High detect enabled 47"] + #[inline(always)] + pub fn hen47(&self) -> HEN47_R { + HEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High detect enabled 48"] + #[inline(always)] + pub fn hen48(&self) -> HEN48_R { + HEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - High detect enabled 49"] + #[inline(always)] + pub fn hen49(&self) -> HEN49_R { + HEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - High detect enabled 50"] + #[inline(always)] + pub fn hen50(&self) -> HEN50_R { + HEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - High detect enabled 51"] + #[inline(always)] + pub fn hen51(&self) -> HEN51_R { + HEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - High detect enabled 52"] + #[inline(always)] + pub fn hen52(&self) -> HEN52_R { + HEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - High detect enabled 53"] + #[inline(always)] + pub fn hen53(&self) -> HEN53_R { + HEN53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - High detect enabled 54"] + #[inline(always)] + pub fn hen54(&self) -> HEN54_R { + HEN54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - High detect enabled 55"] + #[inline(always)] + pub fn hen55(&self) -> HEN55_R { + HEN55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - High detect enabled 56"] + #[inline(always)] + pub fn hen56(&self) -> HEN56_R { + HEN56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - High detect enabled 57"] + #[inline(always)] + pub fn hen57(&self) -> HEN57_R { + HEN57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - High detect enabled 32"] + #[inline(always)] + #[must_use] + pub fn hen32(&mut self) -> HEN32_W<0> { + HEN32_W::new(self) + } + #[doc = "Bit 1 - High detect enabled 33"] + #[inline(always)] + #[must_use] + pub fn hen33(&mut self) -> HEN33_W<1> { + HEN33_W::new(self) + } + #[doc = "Bit 2 - High detect enabled 34"] + #[inline(always)] + #[must_use] + pub fn hen34(&mut self) -> HEN34_W<2> { + HEN34_W::new(self) + } + #[doc = "Bit 3 - High detect enabled 35"] + #[inline(always)] + #[must_use] + pub fn hen35(&mut self) -> HEN35_W<3> { + HEN35_W::new(self) + } + #[doc = "Bit 4 - High detect enabled 36"] + #[inline(always)] + #[must_use] + pub fn hen36(&mut self) -> HEN36_W<4> { + HEN36_W::new(self) + } + #[doc = "Bit 5 - High detect enabled 37"] + #[inline(always)] + #[must_use] + pub fn hen37(&mut self) -> HEN37_W<5> { + HEN37_W::new(self) + } + #[doc = "Bit 6 - High detect enabled 38"] + #[inline(always)] + #[must_use] + pub fn hen38(&mut self) -> HEN38_W<6> { + HEN38_W::new(self) + } + #[doc = "Bit 7 - High detect enabled 39"] + #[inline(always)] + #[must_use] + pub fn hen39(&mut self) -> HEN39_W<7> { + HEN39_W::new(self) + } + #[doc = "Bit 8 - High detect enabled 40"] + #[inline(always)] + #[must_use] + pub fn hen40(&mut self) -> HEN40_W<8> { + HEN40_W::new(self) + } + #[doc = "Bit 9 - High detect enabled 41"] + #[inline(always)] + #[must_use] + pub fn hen41(&mut self) -> HEN41_W<9> { + HEN41_W::new(self) + } + #[doc = "Bit 10 - High detect enabled 42"] + #[inline(always)] + #[must_use] + pub fn hen42(&mut self) -> HEN42_W<10> { + HEN42_W::new(self) + } + #[doc = "Bit 11 - High detect enabled 43"] + #[inline(always)] + #[must_use] + pub fn hen43(&mut self) -> HEN43_W<11> { + HEN43_W::new(self) + } + #[doc = "Bit 12 - High detect enabled 44"] + #[inline(always)] + #[must_use] + pub fn hen44(&mut self) -> HEN44_W<12> { + HEN44_W::new(self) + } + #[doc = "Bit 13 - High detect enabled 45"] + #[inline(always)] + #[must_use] + pub fn hen45(&mut self) -> HEN45_W<13> { + HEN45_W::new(self) + } + #[doc = "Bit 14 - High detect enabled 46"] + #[inline(always)] + #[must_use] + pub fn hen46(&mut self) -> HEN46_W<14> { + HEN46_W::new(self) + } + #[doc = "Bit 15 - High detect enabled 47"] + #[inline(always)] + #[must_use] + pub fn hen47(&mut self) -> HEN47_W<15> { + HEN47_W::new(self) + } + #[doc = "Bit 16 - High detect enabled 48"] + #[inline(always)] + #[must_use] + pub fn hen48(&mut self) -> HEN48_W<16> { + HEN48_W::new(self) + } + #[doc = "Bit 17 - High detect enabled 49"] + #[inline(always)] + #[must_use] + pub fn hen49(&mut self) -> HEN49_W<17> { + HEN49_W::new(self) + } + #[doc = "Bit 18 - High detect enabled 50"] + #[inline(always)] + #[must_use] + pub fn hen50(&mut self) -> HEN50_W<18> { + HEN50_W::new(self) + } + #[doc = "Bit 19 - High detect enabled 51"] + #[inline(always)] + #[must_use] + pub fn hen51(&mut self) -> HEN51_W<19> { + HEN51_W::new(self) + } + #[doc = "Bit 20 - High detect enabled 52"] + #[inline(always)] + #[must_use] + pub fn hen52(&mut self) -> HEN52_W<20> { + HEN52_W::new(self) + } + #[doc = "Bit 21 - High detect enabled 53"] + #[inline(always)] + #[must_use] + pub fn hen53(&mut self) -> HEN53_W<21> { + HEN53_W::new(self) + } + #[doc = "Bit 22 - High detect enabled 54"] + #[inline(always)] + #[must_use] + pub fn hen54(&mut self) -> HEN54_W<22> { + HEN54_W::new(self) + } + #[doc = "Bit 23 - High detect enabled 55"] + #[inline(always)] + #[must_use] + pub fn hen55(&mut self) -> HEN55_W<23> { + HEN55_W::new(self) + } + #[doc = "Bit 24 - High detect enabled 56"] + #[inline(always)] + #[must_use] + pub fn hen56(&mut self) -> HEN56_W<24> { + HEN56_W::new(self) + } + #[doc = "Bit 25 - High detect enabled 57"] + #[inline(always)] + #[must_use] + pub fn hen57(&mut self) -> HEN57_W<25> { + HEN57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin High Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen1](index.html) module"] +pub struct GPHEN1_SPEC; +impl crate::RegisterSpec for GPHEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gphen1::R](R) reader structure"] +impl crate::Readable for GPHEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gphen1::W](W) writer structure"] +impl crate::Writable for GPHEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs new file mode 100644 index 0000000..12b55c2 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs @@ -0,0 +1,363 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL0` reader - Resistor select for 0"] +pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; +#[doc = "Resistor select for 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BP_PULL_A { + #[doc = "0: No pull"] + NONE = 0, + #[doc = "1: Pull up"] + UP = 1, + #[doc = "2: Pull down"] + DOWN = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BP_PULL_A) -> Self { + variant as _ + } +} +impl GPIO_PUP_PDN_CNTRL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(BP_PULL_A::NONE), + 1 => Some(BP_PULL_A::UP), + 2 => Some(BP_PULL_A::DOWN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == BP_PULL_A::NONE + } + #[doc = "Checks if the value of the field is `UP`"] + #[inline(always)] + pub fn is_up(&self) -> bool { + *self == BP_PULL_A::UP + } + #[doc = "Checks if the value of the field is `DOWN`"] + #[inline(always)] + pub fn is_down(&self) -> bool { + *self == BP_PULL_A::DOWN + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL0` writer - Resistor select for 0"] +pub type GPIO_PUP_PDN_CNTRL0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG0_SPEC, u8, BP_PULL_A, 2, O>; +impl<'a, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, O> { + #[doc = "No pull"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BP_PULL_A::NONE) + } + #[doc = "Pull up"] + #[inline(always)] + pub fn up(self) -> &'a mut W { + self.variant(BP_PULL_A::UP) + } + #[doc = "Pull down"] + #[inline(always)] + pub fn down(self) -> &'a mut W { + self.variant(BP_PULL_A::DOWN) + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL1` reader - Resistor select for 1"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL1_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL2` reader - Resistor select for 2"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL2_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL3` reader - Resistor select for 3"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL3_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL4` reader - Resistor select for 4"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL4_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL5` reader - Resistor select for 5"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL5_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL6` reader - Resistor select for 6"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL6_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL7` reader - Resistor select for 7"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL7_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL8` reader - Resistor select for 8"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL8_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL9` reader - Resistor select for 9"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL9_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL10` reader - Resistor select for 10"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL10_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL11` reader - Resistor select for 11"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL11_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL12` reader - Resistor select for 12"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL12_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL13` reader - Resistor select for 13"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL13_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL14` reader - Resistor select for 14"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL14_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL15` reader - Resistor select for 15"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL15_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL1` writer - Resistor select for 1"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL1_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL2` writer - Resistor select for 2"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL2_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL3` writer - Resistor select for 3"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL3_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL4` writer - Resistor select for 4"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL4_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL5` writer - Resistor select for 5"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL5_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL6` writer - Resistor select for 6"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL6_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL7` writer - Resistor select for 7"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL7_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL8` writer - Resistor select for 8"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL8_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL9` writer - Resistor select for 9"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL9_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL10` writer - Resistor select for 10"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL10_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL11` writer - Resistor select for 11"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL11_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL12` writer - Resistor select for 12"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL12_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL13` writer - Resistor select for 13"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL13_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL14` writer - Resistor select for 14"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL14_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL15` writer - Resistor select for 15"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL15_W; +impl R { + #[doc = "Bits 0:1 - Resistor select for 0"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl0(&self) -> GPIO_PUP_PDN_CNTRL0_R { + GPIO_PUP_PDN_CNTRL0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 1"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl1(&self) -> GPIO_PUP_PDN_CNTRL1_R { + GPIO_PUP_PDN_CNTRL1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 2"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl2(&self) -> GPIO_PUP_PDN_CNTRL2_R { + GPIO_PUP_PDN_CNTRL2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 3"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl3(&self) -> GPIO_PUP_PDN_CNTRL3_R { + GPIO_PUP_PDN_CNTRL3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 4"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl4(&self) -> GPIO_PUP_PDN_CNTRL4_R { + GPIO_PUP_PDN_CNTRL4_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 5"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl5(&self) -> GPIO_PUP_PDN_CNTRL5_R { + GPIO_PUP_PDN_CNTRL5_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 6"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl6(&self) -> GPIO_PUP_PDN_CNTRL6_R { + GPIO_PUP_PDN_CNTRL6_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 7"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl7(&self) -> GPIO_PUP_PDN_CNTRL7_R { + GPIO_PUP_PDN_CNTRL7_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 8"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl8(&self) -> GPIO_PUP_PDN_CNTRL8_R { + GPIO_PUP_PDN_CNTRL8_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 9"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl9(&self) -> GPIO_PUP_PDN_CNTRL9_R { + GPIO_PUP_PDN_CNTRL9_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 10"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl10(&self) -> GPIO_PUP_PDN_CNTRL10_R { + GPIO_PUP_PDN_CNTRL10_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 11"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl11(&self) -> GPIO_PUP_PDN_CNTRL11_R { + GPIO_PUP_PDN_CNTRL11_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 12"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl12(&self) -> GPIO_PUP_PDN_CNTRL12_R { + GPIO_PUP_PDN_CNTRL12_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 13"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl13(&self) -> GPIO_PUP_PDN_CNTRL13_R { + GPIO_PUP_PDN_CNTRL13_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 14"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl14(&self) -> GPIO_PUP_PDN_CNTRL14_R { + GPIO_PUP_PDN_CNTRL14_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 15"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl15(&self) -> GPIO_PUP_PDN_CNTRL15_R { + GPIO_PUP_PDN_CNTRL15_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 0"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl0(&mut self) -> GPIO_PUP_PDN_CNTRL0_W<0> { + GPIO_PUP_PDN_CNTRL0_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 1"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl1(&mut self) -> GPIO_PUP_PDN_CNTRL1_W<2> { + GPIO_PUP_PDN_CNTRL1_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 2"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl2(&mut self) -> GPIO_PUP_PDN_CNTRL2_W<4> { + GPIO_PUP_PDN_CNTRL2_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 3"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl3(&mut self) -> GPIO_PUP_PDN_CNTRL3_W<6> { + GPIO_PUP_PDN_CNTRL3_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 4"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl4(&mut self) -> GPIO_PUP_PDN_CNTRL4_W<8> { + GPIO_PUP_PDN_CNTRL4_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 5"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl5(&mut self) -> GPIO_PUP_PDN_CNTRL5_W<10> { + GPIO_PUP_PDN_CNTRL5_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 6"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl6(&mut self) -> GPIO_PUP_PDN_CNTRL6_W<12> { + GPIO_PUP_PDN_CNTRL6_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 7"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl7(&mut self) -> GPIO_PUP_PDN_CNTRL7_W<14> { + GPIO_PUP_PDN_CNTRL7_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 8"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl8(&mut self) -> GPIO_PUP_PDN_CNTRL8_W<16> { + GPIO_PUP_PDN_CNTRL8_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 9"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl9(&mut self) -> GPIO_PUP_PDN_CNTRL9_W<18> { + GPIO_PUP_PDN_CNTRL9_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 10"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl10(&mut self) -> GPIO_PUP_PDN_CNTRL10_W<20> { + GPIO_PUP_PDN_CNTRL10_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 11"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl11(&mut self) -> GPIO_PUP_PDN_CNTRL11_W<22> { + GPIO_PUP_PDN_CNTRL11_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 12"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl12(&mut self) -> GPIO_PUP_PDN_CNTRL12_W<24> { + GPIO_PUP_PDN_CNTRL12_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 13"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl13(&mut self) -> GPIO_PUP_PDN_CNTRL13_W<26> { + GPIO_PUP_PDN_CNTRL13_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 14"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl14(&mut self) -> GPIO_PUP_PDN_CNTRL14_W<28> { + GPIO_PUP_PDN_CNTRL14_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 15"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl15(&mut self) -> GPIO_PUP_PDN_CNTRL15_W<30> { + GPIO_PUP_PDN_CNTRL15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg0](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG0_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg0::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg0::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs new file mode 100644 index 0000000..49faec3 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs @@ -0,0 +1,319 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` reader - Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL16_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] +pub type GPIO_PUP_PDN_CNTRL16_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` reader - Resistor select for 17"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL17_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] +pub type GPIO_PUP_PDN_CNTRL17_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` reader - Resistor select for 18"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL18_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] +pub type GPIO_PUP_PDN_CNTRL18_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` reader - Resistor select for 19"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL19_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] +pub type GPIO_PUP_PDN_CNTRL19_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` reader - Resistor select for 20"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL20_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] +pub type GPIO_PUP_PDN_CNTRL20_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` reader - Resistor select for 21"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL21_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] +pub type GPIO_PUP_PDN_CNTRL21_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` reader - Resistor select for 22"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL22_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] +pub type GPIO_PUP_PDN_CNTRL22_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` reader - Resistor select for 23"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL23_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] +pub type GPIO_PUP_PDN_CNTRL23_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` reader - Resistor select for 24"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL24_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] +pub type GPIO_PUP_PDN_CNTRL24_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` reader - Resistor select for 25"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL25_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] +pub type GPIO_PUP_PDN_CNTRL25_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` reader - Resistor select for 26"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL26_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] +pub type GPIO_PUP_PDN_CNTRL26_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` reader - Resistor select for 27"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL27_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] +pub type GPIO_PUP_PDN_CNTRL27_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` reader - Resistor select for 28"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL28_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] +pub type GPIO_PUP_PDN_CNTRL28_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` reader - Resistor select for 29"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL29_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] +pub type GPIO_PUP_PDN_CNTRL29_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` reader - Resistor select for 30"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL30_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] +pub type GPIO_PUP_PDN_CNTRL30_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL31` reader - Resistor select for 31"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL31_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL31` writer - Resistor select for 31"] +pub type GPIO_PUP_PDN_CNTRL31_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 16"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl16(&self) -> GPIO_PUP_PDN_CNTRL16_R { + GPIO_PUP_PDN_CNTRL16_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 17"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl17(&self) -> GPIO_PUP_PDN_CNTRL17_R { + GPIO_PUP_PDN_CNTRL17_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 18"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl18(&self) -> GPIO_PUP_PDN_CNTRL18_R { + GPIO_PUP_PDN_CNTRL18_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 19"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl19(&self) -> GPIO_PUP_PDN_CNTRL19_R { + GPIO_PUP_PDN_CNTRL19_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 20"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl20(&self) -> GPIO_PUP_PDN_CNTRL20_R { + GPIO_PUP_PDN_CNTRL20_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 21"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl21(&self) -> GPIO_PUP_PDN_CNTRL21_R { + GPIO_PUP_PDN_CNTRL21_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 22"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl22(&self) -> GPIO_PUP_PDN_CNTRL22_R { + GPIO_PUP_PDN_CNTRL22_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 23"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl23(&self) -> GPIO_PUP_PDN_CNTRL23_R { + GPIO_PUP_PDN_CNTRL23_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 24"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl24(&self) -> GPIO_PUP_PDN_CNTRL24_R { + GPIO_PUP_PDN_CNTRL24_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 25"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl25(&self) -> GPIO_PUP_PDN_CNTRL25_R { + GPIO_PUP_PDN_CNTRL25_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 26"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl26(&self) -> GPIO_PUP_PDN_CNTRL26_R { + GPIO_PUP_PDN_CNTRL26_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 27"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl27(&self) -> GPIO_PUP_PDN_CNTRL27_R { + GPIO_PUP_PDN_CNTRL27_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 28"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl28(&self) -> GPIO_PUP_PDN_CNTRL28_R { + GPIO_PUP_PDN_CNTRL28_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 29"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl29(&self) -> GPIO_PUP_PDN_CNTRL29_R { + GPIO_PUP_PDN_CNTRL29_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 30"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl30(&self) -> GPIO_PUP_PDN_CNTRL30_R { + GPIO_PUP_PDN_CNTRL30_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 31"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl31(&self) -> GPIO_PUP_PDN_CNTRL31_R { + GPIO_PUP_PDN_CNTRL31_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 16"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl16(&mut self) -> GPIO_PUP_PDN_CNTRL16_W<0> { + GPIO_PUP_PDN_CNTRL16_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 17"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl17(&mut self) -> GPIO_PUP_PDN_CNTRL17_W<2> { + GPIO_PUP_PDN_CNTRL17_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 18"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl18(&mut self) -> GPIO_PUP_PDN_CNTRL18_W<4> { + GPIO_PUP_PDN_CNTRL18_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 19"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl19(&mut self) -> GPIO_PUP_PDN_CNTRL19_W<6> { + GPIO_PUP_PDN_CNTRL19_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 20"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl20(&mut self) -> GPIO_PUP_PDN_CNTRL20_W<8> { + GPIO_PUP_PDN_CNTRL20_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 21"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl21(&mut self) -> GPIO_PUP_PDN_CNTRL21_W<10> { + GPIO_PUP_PDN_CNTRL21_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 22"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl22(&mut self) -> GPIO_PUP_PDN_CNTRL22_W<12> { + GPIO_PUP_PDN_CNTRL22_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 23"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl23(&mut self) -> GPIO_PUP_PDN_CNTRL23_W<14> { + GPIO_PUP_PDN_CNTRL23_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 24"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl24(&mut self) -> GPIO_PUP_PDN_CNTRL24_W<16> { + GPIO_PUP_PDN_CNTRL24_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 25"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl25(&mut self) -> GPIO_PUP_PDN_CNTRL25_W<18> { + GPIO_PUP_PDN_CNTRL25_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 26"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl26(&mut self) -> GPIO_PUP_PDN_CNTRL26_W<20> { + GPIO_PUP_PDN_CNTRL26_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 27"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl27(&mut self) -> GPIO_PUP_PDN_CNTRL27_W<22> { + GPIO_PUP_PDN_CNTRL27_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 28"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl28(&mut self) -> GPIO_PUP_PDN_CNTRL28_W<24> { + GPIO_PUP_PDN_CNTRL28_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 29"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl29(&mut self) -> GPIO_PUP_PDN_CNTRL29_W<26> { + GPIO_PUP_PDN_CNTRL29_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 30"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl30(&mut self) -> GPIO_PUP_PDN_CNTRL30_W<28> { + GPIO_PUP_PDN_CNTRL30_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 31"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl31(&mut self) -> GPIO_PUP_PDN_CNTRL31_W<30> { + GPIO_PUP_PDN_CNTRL31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg1](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG1_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg1::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg1::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs new file mode 100644 index 0000000..67047c9 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs @@ -0,0 +1,319 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` reader - Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL32_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] +pub type GPIO_PUP_PDN_CNTRL32_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` reader - Resistor select for 33"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL33_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] +pub type GPIO_PUP_PDN_CNTRL33_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` reader - Resistor select for 34"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL34_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] +pub type GPIO_PUP_PDN_CNTRL34_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` reader - Resistor select for 35"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL35_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] +pub type GPIO_PUP_PDN_CNTRL35_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` reader - Resistor select for 36"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL36_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] +pub type GPIO_PUP_PDN_CNTRL36_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` reader - Resistor select for 37"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL37_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] +pub type GPIO_PUP_PDN_CNTRL37_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` reader - Resistor select for 38"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL38_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] +pub type GPIO_PUP_PDN_CNTRL38_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` reader - Resistor select for 39"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL39_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] +pub type GPIO_PUP_PDN_CNTRL39_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` reader - Resistor select for 40"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL40_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] +pub type GPIO_PUP_PDN_CNTRL40_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` reader - Resistor select for 41"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL41_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] +pub type GPIO_PUP_PDN_CNTRL41_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` reader - Resistor select for 42"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL42_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] +pub type GPIO_PUP_PDN_CNTRL42_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` reader - Resistor select for 43"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL43_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] +pub type GPIO_PUP_PDN_CNTRL43_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` reader - Resistor select for 44"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL44_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] +pub type GPIO_PUP_PDN_CNTRL44_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` reader - Resistor select for 45"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL45_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] +pub type GPIO_PUP_PDN_CNTRL45_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` reader - Resistor select for 46"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL46_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] +pub type GPIO_PUP_PDN_CNTRL46_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL47` reader - Resistor select for 47"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL47_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL47` writer - Resistor select for 47"] +pub type GPIO_PUP_PDN_CNTRL47_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 32"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl32(&self) -> GPIO_PUP_PDN_CNTRL32_R { + GPIO_PUP_PDN_CNTRL32_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 33"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl33(&self) -> GPIO_PUP_PDN_CNTRL33_R { + GPIO_PUP_PDN_CNTRL33_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 34"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl34(&self) -> GPIO_PUP_PDN_CNTRL34_R { + GPIO_PUP_PDN_CNTRL34_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 35"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl35(&self) -> GPIO_PUP_PDN_CNTRL35_R { + GPIO_PUP_PDN_CNTRL35_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 36"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl36(&self) -> GPIO_PUP_PDN_CNTRL36_R { + GPIO_PUP_PDN_CNTRL36_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 37"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl37(&self) -> GPIO_PUP_PDN_CNTRL37_R { + GPIO_PUP_PDN_CNTRL37_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 38"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl38(&self) -> GPIO_PUP_PDN_CNTRL38_R { + GPIO_PUP_PDN_CNTRL38_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 39"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl39(&self) -> GPIO_PUP_PDN_CNTRL39_R { + GPIO_PUP_PDN_CNTRL39_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 40"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl40(&self) -> GPIO_PUP_PDN_CNTRL40_R { + GPIO_PUP_PDN_CNTRL40_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 41"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl41(&self) -> GPIO_PUP_PDN_CNTRL41_R { + GPIO_PUP_PDN_CNTRL41_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 42"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl42(&self) -> GPIO_PUP_PDN_CNTRL42_R { + GPIO_PUP_PDN_CNTRL42_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 43"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl43(&self) -> GPIO_PUP_PDN_CNTRL43_R { + GPIO_PUP_PDN_CNTRL43_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 44"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl44(&self) -> GPIO_PUP_PDN_CNTRL44_R { + GPIO_PUP_PDN_CNTRL44_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 45"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl45(&self) -> GPIO_PUP_PDN_CNTRL45_R { + GPIO_PUP_PDN_CNTRL45_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 46"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl46(&self) -> GPIO_PUP_PDN_CNTRL46_R { + GPIO_PUP_PDN_CNTRL46_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 47"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl47(&self) -> GPIO_PUP_PDN_CNTRL47_R { + GPIO_PUP_PDN_CNTRL47_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 32"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl32(&mut self) -> GPIO_PUP_PDN_CNTRL32_W<0> { + GPIO_PUP_PDN_CNTRL32_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 33"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl33(&mut self) -> GPIO_PUP_PDN_CNTRL33_W<2> { + GPIO_PUP_PDN_CNTRL33_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 34"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl34(&mut self) -> GPIO_PUP_PDN_CNTRL34_W<4> { + GPIO_PUP_PDN_CNTRL34_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 35"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl35(&mut self) -> GPIO_PUP_PDN_CNTRL35_W<6> { + GPIO_PUP_PDN_CNTRL35_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 36"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl36(&mut self) -> GPIO_PUP_PDN_CNTRL36_W<8> { + GPIO_PUP_PDN_CNTRL36_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 37"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl37(&mut self) -> GPIO_PUP_PDN_CNTRL37_W<10> { + GPIO_PUP_PDN_CNTRL37_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 38"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl38(&mut self) -> GPIO_PUP_PDN_CNTRL38_W<12> { + GPIO_PUP_PDN_CNTRL38_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 39"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl39(&mut self) -> GPIO_PUP_PDN_CNTRL39_W<14> { + GPIO_PUP_PDN_CNTRL39_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 40"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl40(&mut self) -> GPIO_PUP_PDN_CNTRL40_W<16> { + GPIO_PUP_PDN_CNTRL40_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 41"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl41(&mut self) -> GPIO_PUP_PDN_CNTRL41_W<18> { + GPIO_PUP_PDN_CNTRL41_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 42"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl42(&mut self) -> GPIO_PUP_PDN_CNTRL42_W<20> { + GPIO_PUP_PDN_CNTRL42_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 43"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl43(&mut self) -> GPIO_PUP_PDN_CNTRL43_W<22> { + GPIO_PUP_PDN_CNTRL43_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 44"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl44(&mut self) -> GPIO_PUP_PDN_CNTRL44_W<24> { + GPIO_PUP_PDN_CNTRL44_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 45"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl45(&mut self) -> GPIO_PUP_PDN_CNTRL45_W<26> { + GPIO_PUP_PDN_CNTRL45_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 46"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl46(&mut self) -> GPIO_PUP_PDN_CNTRL46_W<28> { + GPIO_PUP_PDN_CNTRL46_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 47"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl47(&mut self) -> GPIO_PUP_PDN_CNTRL47_W<30> { + GPIO_PUP_PDN_CNTRL47_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg2](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG2_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg2::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg2::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs new file mode 100644 index 0000000..272c950 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs @@ -0,0 +1,223 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` reader - Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL48_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] +pub type GPIO_PUP_PDN_CNTRL48_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` reader - Resistor select for 49"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL49_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] +pub type GPIO_PUP_PDN_CNTRL49_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` reader - Resistor select for 50"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL50_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] +pub type GPIO_PUP_PDN_CNTRL50_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` reader - Resistor select for 51"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL51_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] +pub type GPIO_PUP_PDN_CNTRL51_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` reader - Resistor select for 52"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL52_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] +pub type GPIO_PUP_PDN_CNTRL52_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` reader - Resistor select for 53"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL53_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] +pub type GPIO_PUP_PDN_CNTRL53_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL54` reader - Resistor select for 54"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL54_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL54` writer - Resistor select for 54"] +pub type GPIO_PUP_PDN_CNTRL54_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL55` reader - Resistor select for 55"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL55_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL55` writer - Resistor select for 55"] +pub type GPIO_PUP_PDN_CNTRL55_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL56` reader - Resistor select for 56"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL56_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL56` writer - Resistor select for 56"] +pub type GPIO_PUP_PDN_CNTRL56_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL57` reader - Resistor select for 57"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL57_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL57` writer - Resistor select for 57"] +pub type GPIO_PUP_PDN_CNTRL57_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 48"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl48(&self) -> GPIO_PUP_PDN_CNTRL48_R { + GPIO_PUP_PDN_CNTRL48_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 49"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl49(&self) -> GPIO_PUP_PDN_CNTRL49_R { + GPIO_PUP_PDN_CNTRL49_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 50"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl50(&self) -> GPIO_PUP_PDN_CNTRL50_R { + GPIO_PUP_PDN_CNTRL50_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 51"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl51(&self) -> GPIO_PUP_PDN_CNTRL51_R { + GPIO_PUP_PDN_CNTRL51_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 52"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl52(&self) -> GPIO_PUP_PDN_CNTRL52_R { + GPIO_PUP_PDN_CNTRL52_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 53"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl53(&self) -> GPIO_PUP_PDN_CNTRL53_R { + GPIO_PUP_PDN_CNTRL53_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 54"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl54(&self) -> GPIO_PUP_PDN_CNTRL54_R { + GPIO_PUP_PDN_CNTRL54_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 55"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl55(&self) -> GPIO_PUP_PDN_CNTRL55_R { + GPIO_PUP_PDN_CNTRL55_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 56"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl56(&self) -> GPIO_PUP_PDN_CNTRL56_R { + GPIO_PUP_PDN_CNTRL56_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 57"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl57(&self) -> GPIO_PUP_PDN_CNTRL57_R { + GPIO_PUP_PDN_CNTRL57_R::new(((self.bits >> 18) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 48"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl48(&mut self) -> GPIO_PUP_PDN_CNTRL48_W<0> { + GPIO_PUP_PDN_CNTRL48_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 49"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl49(&mut self) -> GPIO_PUP_PDN_CNTRL49_W<2> { + GPIO_PUP_PDN_CNTRL49_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 50"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl50(&mut self) -> GPIO_PUP_PDN_CNTRL50_W<4> { + GPIO_PUP_PDN_CNTRL50_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 51"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl51(&mut self) -> GPIO_PUP_PDN_CNTRL51_W<6> { + GPIO_PUP_PDN_CNTRL51_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 52"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl52(&mut self) -> GPIO_PUP_PDN_CNTRL52_W<8> { + GPIO_PUP_PDN_CNTRL52_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 53"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl53(&mut self) -> GPIO_PUP_PDN_CNTRL53_W<10> { + GPIO_PUP_PDN_CNTRL53_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 54"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl54(&mut self) -> GPIO_PUP_PDN_CNTRL54_W<12> { + GPIO_PUP_PDN_CNTRL54_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 55"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl55(&mut self) -> GPIO_PUP_PDN_CNTRL55_W<14> { + GPIO_PUP_PDN_CNTRL55_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 56"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl56(&mut self) -> GPIO_PUP_PDN_CNTRL56_W<16> { + GPIO_PUP_PDN_CNTRL56_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 57"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl57(&mut self) -> GPIO_PUP_PDN_CNTRL57_W<18> { + GPIO_PUP_PDN_CNTRL57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg3](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG3_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg3::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg3::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gplen0.rs b/crates/bcm2711-lpa/src/gpio/gplen0.rs new file mode 100644 index 0000000..54f51bd --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gplen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPLEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPLEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEN0` reader - Low detect enabled 0"] +pub type LEN0_R = crate::BitReader; +#[doc = "Field `LEN0` writer - Low detect enabled 0"] +pub type LEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN1` reader - Low detect enabled 1"] +pub type LEN1_R = crate::BitReader; +#[doc = "Field `LEN1` writer - Low detect enabled 1"] +pub type LEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN2` reader - Low detect enabled 2"] +pub type LEN2_R = crate::BitReader; +#[doc = "Field `LEN2` writer - Low detect enabled 2"] +pub type LEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN3` reader - Low detect enabled 3"] +pub type LEN3_R = crate::BitReader; +#[doc = "Field `LEN3` writer - Low detect enabled 3"] +pub type LEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN4` reader - Low detect enabled 4"] +pub type LEN4_R = crate::BitReader; +#[doc = "Field `LEN4` writer - Low detect enabled 4"] +pub type LEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN5` reader - Low detect enabled 5"] +pub type LEN5_R = crate::BitReader; +#[doc = "Field `LEN5` writer - Low detect enabled 5"] +pub type LEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN6` reader - Low detect enabled 6"] +pub type LEN6_R = crate::BitReader; +#[doc = "Field `LEN6` writer - Low detect enabled 6"] +pub type LEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN7` reader - Low detect enabled 7"] +pub type LEN7_R = crate::BitReader; +#[doc = "Field `LEN7` writer - Low detect enabled 7"] +pub type LEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN8` reader - Low detect enabled 8"] +pub type LEN8_R = crate::BitReader; +#[doc = "Field `LEN8` writer - Low detect enabled 8"] +pub type LEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN9` reader - Low detect enabled 9"] +pub type LEN9_R = crate::BitReader; +#[doc = "Field `LEN9` writer - Low detect enabled 9"] +pub type LEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN10` reader - Low detect enabled 10"] +pub type LEN10_R = crate::BitReader; +#[doc = "Field `LEN10` writer - Low detect enabled 10"] +pub type LEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN11` reader - Low detect enabled 11"] +pub type LEN11_R = crate::BitReader; +#[doc = "Field `LEN11` writer - Low detect enabled 11"] +pub type LEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN12` reader - Low detect enabled 12"] +pub type LEN12_R = crate::BitReader; +#[doc = "Field `LEN12` writer - Low detect enabled 12"] +pub type LEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN13` reader - Low detect enabled 13"] +pub type LEN13_R = crate::BitReader; +#[doc = "Field `LEN13` writer - Low detect enabled 13"] +pub type LEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN14` reader - Low detect enabled 14"] +pub type LEN14_R = crate::BitReader; +#[doc = "Field `LEN14` writer - Low detect enabled 14"] +pub type LEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN15` reader - Low detect enabled 15"] +pub type LEN15_R = crate::BitReader; +#[doc = "Field `LEN15` writer - Low detect enabled 15"] +pub type LEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN16` reader - Low detect enabled 16"] +pub type LEN16_R = crate::BitReader; +#[doc = "Field `LEN16` writer - Low detect enabled 16"] +pub type LEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN17` reader - Low detect enabled 17"] +pub type LEN17_R = crate::BitReader; +#[doc = "Field `LEN17` writer - Low detect enabled 17"] +pub type LEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN18` reader - Low detect enabled 18"] +pub type LEN18_R = crate::BitReader; +#[doc = "Field `LEN18` writer - Low detect enabled 18"] +pub type LEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN19` reader - Low detect enabled 19"] +pub type LEN19_R = crate::BitReader; +#[doc = "Field `LEN19` writer - Low detect enabled 19"] +pub type LEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN20` reader - Low detect enabled 20"] +pub type LEN20_R = crate::BitReader; +#[doc = "Field `LEN20` writer - Low detect enabled 20"] +pub type LEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN21` reader - Low detect enabled 21"] +pub type LEN21_R = crate::BitReader; +#[doc = "Field `LEN21` writer - Low detect enabled 21"] +pub type LEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN22` reader - Low detect enabled 22"] +pub type LEN22_R = crate::BitReader; +#[doc = "Field `LEN22` writer - Low detect enabled 22"] +pub type LEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN23` reader - Low detect enabled 23"] +pub type LEN23_R = crate::BitReader; +#[doc = "Field `LEN23` writer - Low detect enabled 23"] +pub type LEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN24` reader - Low detect enabled 24"] +pub type LEN24_R = crate::BitReader; +#[doc = "Field `LEN24` writer - Low detect enabled 24"] +pub type LEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN25` reader - Low detect enabled 25"] +pub type LEN25_R = crate::BitReader; +#[doc = "Field `LEN25` writer - Low detect enabled 25"] +pub type LEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN26` reader - Low detect enabled 26"] +pub type LEN26_R = crate::BitReader; +#[doc = "Field `LEN26` writer - Low detect enabled 26"] +pub type LEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN27` reader - Low detect enabled 27"] +pub type LEN27_R = crate::BitReader; +#[doc = "Field `LEN27` writer - Low detect enabled 27"] +pub type LEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN28` reader - Low detect enabled 28"] +pub type LEN28_R = crate::BitReader; +#[doc = "Field `LEN28` writer - Low detect enabled 28"] +pub type LEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN29` reader - Low detect enabled 29"] +pub type LEN29_R = crate::BitReader; +#[doc = "Field `LEN29` writer - Low detect enabled 29"] +pub type LEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN30` reader - Low detect enabled 30"] +pub type LEN30_R = crate::BitReader; +#[doc = "Field `LEN30` writer - Low detect enabled 30"] +pub type LEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN31` reader - Low detect enabled 31"] +pub type LEN31_R = crate::BitReader; +#[doc = "Field `LEN31` writer - Low detect enabled 31"] +pub type LEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Low detect enabled 0"] + #[inline(always)] + pub fn len0(&self) -> LEN0_R { + LEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low detect enabled 1"] + #[inline(always)] + pub fn len1(&self) -> LEN1_R { + LEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Low detect enabled 2"] + #[inline(always)] + pub fn len2(&self) -> LEN2_R { + LEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Low detect enabled 3"] + #[inline(always)] + pub fn len3(&self) -> LEN3_R { + LEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Low detect enabled 4"] + #[inline(always)] + pub fn len4(&self) -> LEN4_R { + LEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Low detect enabled 5"] + #[inline(always)] + pub fn len5(&self) -> LEN5_R { + LEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Low detect enabled 6"] + #[inline(always)] + pub fn len6(&self) -> LEN6_R { + LEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Low detect enabled 7"] + #[inline(always)] + pub fn len7(&self) -> LEN7_R { + LEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Low detect enabled 8"] + #[inline(always)] + pub fn len8(&self) -> LEN8_R { + LEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low detect enabled 9"] + #[inline(always)] + pub fn len9(&self) -> LEN9_R { + LEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Low detect enabled 10"] + #[inline(always)] + pub fn len10(&self) -> LEN10_R { + LEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low detect enabled 11"] + #[inline(always)] + pub fn len11(&self) -> LEN11_R { + LEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low detect enabled 12"] + #[inline(always)] + pub fn len12(&self) -> LEN12_R { + LEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Low detect enabled 13"] + #[inline(always)] + pub fn len13(&self) -> LEN13_R { + LEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Low detect enabled 14"] + #[inline(always)] + pub fn len14(&self) -> LEN14_R { + LEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Low detect enabled 15"] + #[inline(always)] + pub fn len15(&self) -> LEN15_R { + LEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Low detect enabled 16"] + #[inline(always)] + pub fn len16(&self) -> LEN16_R { + LEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Low detect enabled 17"] + #[inline(always)] + pub fn len17(&self) -> LEN17_R { + LEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Low detect enabled 18"] + #[inline(always)] + pub fn len18(&self) -> LEN18_R { + LEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Low detect enabled 19"] + #[inline(always)] + pub fn len19(&self) -> LEN19_R { + LEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low detect enabled 20"] + #[inline(always)] + pub fn len20(&self) -> LEN20_R { + LEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Low detect enabled 21"] + #[inline(always)] + pub fn len21(&self) -> LEN21_R { + LEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Low detect enabled 22"] + #[inline(always)] + pub fn len22(&self) -> LEN22_R { + LEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Low detect enabled 23"] + #[inline(always)] + pub fn len23(&self) -> LEN23_R { + LEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Low detect enabled 24"] + #[inline(always)] + pub fn len24(&self) -> LEN24_R { + LEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Low detect enabled 25"] + #[inline(always)] + pub fn len25(&self) -> LEN25_R { + LEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Low detect enabled 26"] + #[inline(always)] + pub fn len26(&self) -> LEN26_R { + LEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Low detect enabled 27"] + #[inline(always)] + pub fn len27(&self) -> LEN27_R { + LEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Low detect enabled 28"] + #[inline(always)] + pub fn len28(&self) -> LEN28_R { + LEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Low detect enabled 29"] + #[inline(always)] + pub fn len29(&self) -> LEN29_R { + LEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Low detect enabled 30"] + #[inline(always)] + pub fn len30(&self) -> LEN30_R { + LEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Low detect enabled 31"] + #[inline(always)] + pub fn len31(&self) -> LEN31_R { + LEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Low detect enabled 0"] + #[inline(always)] + #[must_use] + pub fn len0(&mut self) -> LEN0_W<0> { + LEN0_W::new(self) + } + #[doc = "Bit 1 - Low detect enabled 1"] + #[inline(always)] + #[must_use] + pub fn len1(&mut self) -> LEN1_W<1> { + LEN1_W::new(self) + } + #[doc = "Bit 2 - Low detect enabled 2"] + #[inline(always)] + #[must_use] + pub fn len2(&mut self) -> LEN2_W<2> { + LEN2_W::new(self) + } + #[doc = "Bit 3 - Low detect enabled 3"] + #[inline(always)] + #[must_use] + pub fn len3(&mut self) -> LEN3_W<3> { + LEN3_W::new(self) + } + #[doc = "Bit 4 - Low detect enabled 4"] + #[inline(always)] + #[must_use] + pub fn len4(&mut self) -> LEN4_W<4> { + LEN4_W::new(self) + } + #[doc = "Bit 5 - Low detect enabled 5"] + #[inline(always)] + #[must_use] + pub fn len5(&mut self) -> LEN5_W<5> { + LEN5_W::new(self) + } + #[doc = "Bit 6 - Low detect enabled 6"] + #[inline(always)] + #[must_use] + pub fn len6(&mut self) -> LEN6_W<6> { + LEN6_W::new(self) + } + #[doc = "Bit 7 - Low detect enabled 7"] + #[inline(always)] + #[must_use] + pub fn len7(&mut self) -> LEN7_W<7> { + LEN7_W::new(self) + } + #[doc = "Bit 8 - Low detect enabled 8"] + #[inline(always)] + #[must_use] + pub fn len8(&mut self) -> LEN8_W<8> { + LEN8_W::new(self) + } + #[doc = "Bit 9 - Low detect enabled 9"] + #[inline(always)] + #[must_use] + pub fn len9(&mut self) -> LEN9_W<9> { + LEN9_W::new(self) + } + #[doc = "Bit 10 - Low detect enabled 10"] + #[inline(always)] + #[must_use] + pub fn len10(&mut self) -> LEN10_W<10> { + LEN10_W::new(self) + } + #[doc = "Bit 11 - Low detect enabled 11"] + #[inline(always)] + #[must_use] + pub fn len11(&mut self) -> LEN11_W<11> { + LEN11_W::new(self) + } + #[doc = "Bit 12 - Low detect enabled 12"] + #[inline(always)] + #[must_use] + pub fn len12(&mut self) -> LEN12_W<12> { + LEN12_W::new(self) + } + #[doc = "Bit 13 - Low detect enabled 13"] + #[inline(always)] + #[must_use] + pub fn len13(&mut self) -> LEN13_W<13> { + LEN13_W::new(self) + } + #[doc = "Bit 14 - Low detect enabled 14"] + #[inline(always)] + #[must_use] + pub fn len14(&mut self) -> LEN14_W<14> { + LEN14_W::new(self) + } + #[doc = "Bit 15 - Low detect enabled 15"] + #[inline(always)] + #[must_use] + pub fn len15(&mut self) -> LEN15_W<15> { + LEN15_W::new(self) + } + #[doc = "Bit 16 - Low detect enabled 16"] + #[inline(always)] + #[must_use] + pub fn len16(&mut self) -> LEN16_W<16> { + LEN16_W::new(self) + } + #[doc = "Bit 17 - Low detect enabled 17"] + #[inline(always)] + #[must_use] + pub fn len17(&mut self) -> LEN17_W<17> { + LEN17_W::new(self) + } + #[doc = "Bit 18 - Low detect enabled 18"] + #[inline(always)] + #[must_use] + pub fn len18(&mut self) -> LEN18_W<18> { + LEN18_W::new(self) + } + #[doc = "Bit 19 - Low detect enabled 19"] + #[inline(always)] + #[must_use] + pub fn len19(&mut self) -> LEN19_W<19> { + LEN19_W::new(self) + } + #[doc = "Bit 20 - Low detect enabled 20"] + #[inline(always)] + #[must_use] + pub fn len20(&mut self) -> LEN20_W<20> { + LEN20_W::new(self) + } + #[doc = "Bit 21 - Low detect enabled 21"] + #[inline(always)] + #[must_use] + pub fn len21(&mut self) -> LEN21_W<21> { + LEN21_W::new(self) + } + #[doc = "Bit 22 - Low detect enabled 22"] + #[inline(always)] + #[must_use] + pub fn len22(&mut self) -> LEN22_W<22> { + LEN22_W::new(self) + } + #[doc = "Bit 23 - Low detect enabled 23"] + #[inline(always)] + #[must_use] + pub fn len23(&mut self) -> LEN23_W<23> { + LEN23_W::new(self) + } + #[doc = "Bit 24 - Low detect enabled 24"] + #[inline(always)] + #[must_use] + pub fn len24(&mut self) -> LEN24_W<24> { + LEN24_W::new(self) + } + #[doc = "Bit 25 - Low detect enabled 25"] + #[inline(always)] + #[must_use] + pub fn len25(&mut self) -> LEN25_W<25> { + LEN25_W::new(self) + } + #[doc = "Bit 26 - Low detect enabled 26"] + #[inline(always)] + #[must_use] + pub fn len26(&mut self) -> LEN26_W<26> { + LEN26_W::new(self) + } + #[doc = "Bit 27 - Low detect enabled 27"] + #[inline(always)] + #[must_use] + pub fn len27(&mut self) -> LEN27_W<27> { + LEN27_W::new(self) + } + #[doc = "Bit 28 - Low detect enabled 28"] + #[inline(always)] + #[must_use] + pub fn len28(&mut self) -> LEN28_W<28> { + LEN28_W::new(self) + } + #[doc = "Bit 29 - Low detect enabled 29"] + #[inline(always)] + #[must_use] + pub fn len29(&mut self) -> LEN29_W<29> { + LEN29_W::new(self) + } + #[doc = "Bit 30 - Low detect enabled 30"] + #[inline(always)] + #[must_use] + pub fn len30(&mut self) -> LEN30_W<30> { + LEN30_W::new(self) + } + #[doc = "Bit 31 - Low detect enabled 31"] + #[inline(always)] + #[must_use] + pub fn len31(&mut self) -> LEN31_W<31> { + LEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Low Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen0](index.html) module"] +pub struct GPLEN0_SPEC; +impl crate::RegisterSpec for GPLEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplen0::R](R) reader structure"] +impl crate::Readable for GPLEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gplen0::W](W) writer structure"] +impl crate::Writable for GPLEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gplen1.rs b/crates/bcm2711-lpa/src/gpio/gplen1.rs new file mode 100644 index 0000000..76fbc70 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gplen1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPLEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPLEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEN32` reader - Low detect enabled 32"] +pub type LEN32_R = crate::BitReader; +#[doc = "Field `LEN32` writer - Low detect enabled 32"] +pub type LEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN33` reader - Low detect enabled 33"] +pub type LEN33_R = crate::BitReader; +#[doc = "Field `LEN33` writer - Low detect enabled 33"] +pub type LEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN34` reader - Low detect enabled 34"] +pub type LEN34_R = crate::BitReader; +#[doc = "Field `LEN34` writer - Low detect enabled 34"] +pub type LEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN35` reader - Low detect enabled 35"] +pub type LEN35_R = crate::BitReader; +#[doc = "Field `LEN35` writer - Low detect enabled 35"] +pub type LEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN36` reader - Low detect enabled 36"] +pub type LEN36_R = crate::BitReader; +#[doc = "Field `LEN36` writer - Low detect enabled 36"] +pub type LEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN37` reader - Low detect enabled 37"] +pub type LEN37_R = crate::BitReader; +#[doc = "Field `LEN37` writer - Low detect enabled 37"] +pub type LEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN38` reader - Low detect enabled 38"] +pub type LEN38_R = crate::BitReader; +#[doc = "Field `LEN38` writer - Low detect enabled 38"] +pub type LEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN39` reader - Low detect enabled 39"] +pub type LEN39_R = crate::BitReader; +#[doc = "Field `LEN39` writer - Low detect enabled 39"] +pub type LEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN40` reader - Low detect enabled 40"] +pub type LEN40_R = crate::BitReader; +#[doc = "Field `LEN40` writer - Low detect enabled 40"] +pub type LEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN41` reader - Low detect enabled 41"] +pub type LEN41_R = crate::BitReader; +#[doc = "Field `LEN41` writer - Low detect enabled 41"] +pub type LEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN42` reader - Low detect enabled 42"] +pub type LEN42_R = crate::BitReader; +#[doc = "Field `LEN42` writer - Low detect enabled 42"] +pub type LEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN43` reader - Low detect enabled 43"] +pub type LEN43_R = crate::BitReader; +#[doc = "Field `LEN43` writer - Low detect enabled 43"] +pub type LEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN44` reader - Low detect enabled 44"] +pub type LEN44_R = crate::BitReader; +#[doc = "Field `LEN44` writer - Low detect enabled 44"] +pub type LEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN45` reader - Low detect enabled 45"] +pub type LEN45_R = crate::BitReader; +#[doc = "Field `LEN45` writer - Low detect enabled 45"] +pub type LEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN46` reader - Low detect enabled 46"] +pub type LEN46_R = crate::BitReader; +#[doc = "Field `LEN46` writer - Low detect enabled 46"] +pub type LEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN47` reader - Low detect enabled 47"] +pub type LEN47_R = crate::BitReader; +#[doc = "Field `LEN47` writer - Low detect enabled 47"] +pub type LEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN48` reader - Low detect enabled 48"] +pub type LEN48_R = crate::BitReader; +#[doc = "Field `LEN48` writer - Low detect enabled 48"] +pub type LEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN49` reader - Low detect enabled 49"] +pub type LEN49_R = crate::BitReader; +#[doc = "Field `LEN49` writer - Low detect enabled 49"] +pub type LEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN50` reader - Low detect enabled 50"] +pub type LEN50_R = crate::BitReader; +#[doc = "Field `LEN50` writer - Low detect enabled 50"] +pub type LEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN51` reader - Low detect enabled 51"] +pub type LEN51_R = crate::BitReader; +#[doc = "Field `LEN51` writer - Low detect enabled 51"] +pub type LEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN52` reader - Low detect enabled 52"] +pub type LEN52_R = crate::BitReader; +#[doc = "Field `LEN52` writer - Low detect enabled 52"] +pub type LEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN53` reader - Low detect enabled 53"] +pub type LEN53_R = crate::BitReader; +#[doc = "Field `LEN53` writer - Low detect enabled 53"] +pub type LEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN54` reader - Low detect enabled 54"] +pub type LEN54_R = crate::BitReader; +#[doc = "Field `LEN54` writer - Low detect enabled 54"] +pub type LEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN55` reader - Low detect enabled 55"] +pub type LEN55_R = crate::BitReader; +#[doc = "Field `LEN55` writer - Low detect enabled 55"] +pub type LEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN56` reader - Low detect enabled 56"] +pub type LEN56_R = crate::BitReader; +#[doc = "Field `LEN56` writer - Low detect enabled 56"] +pub type LEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN57` reader - Low detect enabled 57"] +pub type LEN57_R = crate::BitReader; +#[doc = "Field `LEN57` writer - Low detect enabled 57"] +pub type LEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Low detect enabled 32"] + #[inline(always)] + pub fn len32(&self) -> LEN32_R { + LEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low detect enabled 33"] + #[inline(always)] + pub fn len33(&self) -> LEN33_R { + LEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Low detect enabled 34"] + #[inline(always)] + pub fn len34(&self) -> LEN34_R { + LEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Low detect enabled 35"] + #[inline(always)] + pub fn len35(&self) -> LEN35_R { + LEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Low detect enabled 36"] + #[inline(always)] + pub fn len36(&self) -> LEN36_R { + LEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Low detect enabled 37"] + #[inline(always)] + pub fn len37(&self) -> LEN37_R { + LEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Low detect enabled 38"] + #[inline(always)] + pub fn len38(&self) -> LEN38_R { + LEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Low detect enabled 39"] + #[inline(always)] + pub fn len39(&self) -> LEN39_R { + LEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Low detect enabled 40"] + #[inline(always)] + pub fn len40(&self) -> LEN40_R { + LEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low detect enabled 41"] + #[inline(always)] + pub fn len41(&self) -> LEN41_R { + LEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Low detect enabled 42"] + #[inline(always)] + pub fn len42(&self) -> LEN42_R { + LEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low detect enabled 43"] + #[inline(always)] + pub fn len43(&self) -> LEN43_R { + LEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low detect enabled 44"] + #[inline(always)] + pub fn len44(&self) -> LEN44_R { + LEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Low detect enabled 45"] + #[inline(always)] + pub fn len45(&self) -> LEN45_R { + LEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Low detect enabled 46"] + #[inline(always)] + pub fn len46(&self) -> LEN46_R { + LEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Low detect enabled 47"] + #[inline(always)] + pub fn len47(&self) -> LEN47_R { + LEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Low detect enabled 48"] + #[inline(always)] + pub fn len48(&self) -> LEN48_R { + LEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Low detect enabled 49"] + #[inline(always)] + pub fn len49(&self) -> LEN49_R { + LEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Low detect enabled 50"] + #[inline(always)] + pub fn len50(&self) -> LEN50_R { + LEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Low detect enabled 51"] + #[inline(always)] + pub fn len51(&self) -> LEN51_R { + LEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low detect enabled 52"] + #[inline(always)] + pub fn len52(&self) -> LEN52_R { + LEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Low detect enabled 53"] + #[inline(always)] + pub fn len53(&self) -> LEN53_R { + LEN53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Low detect enabled 54"] + #[inline(always)] + pub fn len54(&self) -> LEN54_R { + LEN54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Low detect enabled 55"] + #[inline(always)] + pub fn len55(&self) -> LEN55_R { + LEN55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Low detect enabled 56"] + #[inline(always)] + pub fn len56(&self) -> LEN56_R { + LEN56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Low detect enabled 57"] + #[inline(always)] + pub fn len57(&self) -> LEN57_R { + LEN57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Low detect enabled 32"] + #[inline(always)] + #[must_use] + pub fn len32(&mut self) -> LEN32_W<0> { + LEN32_W::new(self) + } + #[doc = "Bit 1 - Low detect enabled 33"] + #[inline(always)] + #[must_use] + pub fn len33(&mut self) -> LEN33_W<1> { + LEN33_W::new(self) + } + #[doc = "Bit 2 - Low detect enabled 34"] + #[inline(always)] + #[must_use] + pub fn len34(&mut self) -> LEN34_W<2> { + LEN34_W::new(self) + } + #[doc = "Bit 3 - Low detect enabled 35"] + #[inline(always)] + #[must_use] + pub fn len35(&mut self) -> LEN35_W<3> { + LEN35_W::new(self) + } + #[doc = "Bit 4 - Low detect enabled 36"] + #[inline(always)] + #[must_use] + pub fn len36(&mut self) -> LEN36_W<4> { + LEN36_W::new(self) + } + #[doc = "Bit 5 - Low detect enabled 37"] + #[inline(always)] + #[must_use] + pub fn len37(&mut self) -> LEN37_W<5> { + LEN37_W::new(self) + } + #[doc = "Bit 6 - Low detect enabled 38"] + #[inline(always)] + #[must_use] + pub fn len38(&mut self) -> LEN38_W<6> { + LEN38_W::new(self) + } + #[doc = "Bit 7 - Low detect enabled 39"] + #[inline(always)] + #[must_use] + pub fn len39(&mut self) -> LEN39_W<7> { + LEN39_W::new(self) + } + #[doc = "Bit 8 - Low detect enabled 40"] + #[inline(always)] + #[must_use] + pub fn len40(&mut self) -> LEN40_W<8> { + LEN40_W::new(self) + } + #[doc = "Bit 9 - Low detect enabled 41"] + #[inline(always)] + #[must_use] + pub fn len41(&mut self) -> LEN41_W<9> { + LEN41_W::new(self) + } + #[doc = "Bit 10 - Low detect enabled 42"] + #[inline(always)] + #[must_use] + pub fn len42(&mut self) -> LEN42_W<10> { + LEN42_W::new(self) + } + #[doc = "Bit 11 - Low detect enabled 43"] + #[inline(always)] + #[must_use] + pub fn len43(&mut self) -> LEN43_W<11> { + LEN43_W::new(self) + } + #[doc = "Bit 12 - Low detect enabled 44"] + #[inline(always)] + #[must_use] + pub fn len44(&mut self) -> LEN44_W<12> { + LEN44_W::new(self) + } + #[doc = "Bit 13 - Low detect enabled 45"] + #[inline(always)] + #[must_use] + pub fn len45(&mut self) -> LEN45_W<13> { + LEN45_W::new(self) + } + #[doc = "Bit 14 - Low detect enabled 46"] + #[inline(always)] + #[must_use] + pub fn len46(&mut self) -> LEN46_W<14> { + LEN46_W::new(self) + } + #[doc = "Bit 15 - Low detect enabled 47"] + #[inline(always)] + #[must_use] + pub fn len47(&mut self) -> LEN47_W<15> { + LEN47_W::new(self) + } + #[doc = "Bit 16 - Low detect enabled 48"] + #[inline(always)] + #[must_use] + pub fn len48(&mut self) -> LEN48_W<16> { + LEN48_W::new(self) + } + #[doc = "Bit 17 - Low detect enabled 49"] + #[inline(always)] + #[must_use] + pub fn len49(&mut self) -> LEN49_W<17> { + LEN49_W::new(self) + } + #[doc = "Bit 18 - Low detect enabled 50"] + #[inline(always)] + #[must_use] + pub fn len50(&mut self) -> LEN50_W<18> { + LEN50_W::new(self) + } + #[doc = "Bit 19 - Low detect enabled 51"] + #[inline(always)] + #[must_use] + pub fn len51(&mut self) -> LEN51_W<19> { + LEN51_W::new(self) + } + #[doc = "Bit 20 - Low detect enabled 52"] + #[inline(always)] + #[must_use] + pub fn len52(&mut self) -> LEN52_W<20> { + LEN52_W::new(self) + } + #[doc = "Bit 21 - Low detect enabled 53"] + #[inline(always)] + #[must_use] + pub fn len53(&mut self) -> LEN53_W<21> { + LEN53_W::new(self) + } + #[doc = "Bit 22 - Low detect enabled 54"] + #[inline(always)] + #[must_use] + pub fn len54(&mut self) -> LEN54_W<22> { + LEN54_W::new(self) + } + #[doc = "Bit 23 - Low detect enabled 55"] + #[inline(always)] + #[must_use] + pub fn len55(&mut self) -> LEN55_W<23> { + LEN55_W::new(self) + } + #[doc = "Bit 24 - Low detect enabled 56"] + #[inline(always)] + #[must_use] + pub fn len56(&mut self) -> LEN56_W<24> { + LEN56_W::new(self) + } + #[doc = "Bit 25 - Low detect enabled 57"] + #[inline(always)] + #[must_use] + pub fn len57(&mut self) -> LEN57_W<25> { + LEN57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Low Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen1](index.html) module"] +pub struct GPLEN1_SPEC; +impl crate::RegisterSpec for GPLEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplen1::R](R) reader structure"] +impl crate::Readable for GPLEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gplen1::W](W) writer structure"] +impl crate::Writable for GPLEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gplev0.rs b/crates/bcm2711-lpa/src/gpio/gplev0.rs new file mode 100644 index 0000000..e6f9b94 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gplev0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `GPLEV0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LEV0` reader - Level 0"] +pub type LEV0_R = crate::BitReader; +#[doc = "Field `LEV1` reader - Level 1"] +pub type LEV1_R = crate::BitReader; +#[doc = "Field `LEV2` reader - Level 2"] +pub type LEV2_R = crate::BitReader; +#[doc = "Field `LEV3` reader - Level 3"] +pub type LEV3_R = crate::BitReader; +#[doc = "Field `LEV4` reader - Level 4"] +pub type LEV4_R = crate::BitReader; +#[doc = "Field `LEV5` reader - Level 5"] +pub type LEV5_R = crate::BitReader; +#[doc = "Field `LEV6` reader - Level 6"] +pub type LEV6_R = crate::BitReader; +#[doc = "Field `LEV7` reader - Level 7"] +pub type LEV7_R = crate::BitReader; +#[doc = "Field `LEV8` reader - Level 8"] +pub type LEV8_R = crate::BitReader; +#[doc = "Field `LEV9` reader - Level 9"] +pub type LEV9_R = crate::BitReader; +#[doc = "Field `LEV10` reader - Level 10"] +pub type LEV10_R = crate::BitReader; +#[doc = "Field `LEV11` reader - Level 11"] +pub type LEV11_R = crate::BitReader; +#[doc = "Field `LEV12` reader - Level 12"] +pub type LEV12_R = crate::BitReader; +#[doc = "Field `LEV13` reader - Level 13"] +pub type LEV13_R = crate::BitReader; +#[doc = "Field `LEV14` reader - Level 14"] +pub type LEV14_R = crate::BitReader; +#[doc = "Field `LEV15` reader - Level 15"] +pub type LEV15_R = crate::BitReader; +#[doc = "Field `LEV16` reader - Level 16"] +pub type LEV16_R = crate::BitReader; +#[doc = "Field `LEV17` reader - Level 17"] +pub type LEV17_R = crate::BitReader; +#[doc = "Field `LEV18` reader - Level 18"] +pub type LEV18_R = crate::BitReader; +#[doc = "Field `LEV19` reader - Level 19"] +pub type LEV19_R = crate::BitReader; +#[doc = "Field `LEV20` reader - Level 20"] +pub type LEV20_R = crate::BitReader; +#[doc = "Field `LEV21` reader - Level 21"] +pub type LEV21_R = crate::BitReader; +#[doc = "Field `LEV22` reader - Level 22"] +pub type LEV22_R = crate::BitReader; +#[doc = "Field `LEV23` reader - Level 23"] +pub type LEV23_R = crate::BitReader; +#[doc = "Field `LEV24` reader - Level 24"] +pub type LEV24_R = crate::BitReader; +#[doc = "Field `LEV25` reader - Level 25"] +pub type LEV25_R = crate::BitReader; +#[doc = "Field `LEV26` reader - Level 26"] +pub type LEV26_R = crate::BitReader; +#[doc = "Field `LEV27` reader - Level 27"] +pub type LEV27_R = crate::BitReader; +#[doc = "Field `LEV28` reader - Level 28"] +pub type LEV28_R = crate::BitReader; +#[doc = "Field `LEV29` reader - Level 29"] +pub type LEV29_R = crate::BitReader; +#[doc = "Field `LEV30` reader - Level 30"] +pub type LEV30_R = crate::BitReader; +#[doc = "Field `LEV31` reader - Level 31"] +pub type LEV31_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Level 0"] + #[inline(always)] + pub fn lev0(&self) -> LEV0_R { + LEV0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 1"] + #[inline(always)] + pub fn lev1(&self) -> LEV1_R { + LEV1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 2"] + #[inline(always)] + pub fn lev2(&self) -> LEV2_R { + LEV2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 3"] + #[inline(always)] + pub fn lev3(&self) -> LEV3_R { + LEV3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Level 4"] + #[inline(always)] + pub fn lev4(&self) -> LEV4_R { + LEV4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Level 5"] + #[inline(always)] + pub fn lev5(&self) -> LEV5_R { + LEV5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Level 6"] + #[inline(always)] + pub fn lev6(&self) -> LEV6_R { + LEV6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Level 7"] + #[inline(always)] + pub fn lev7(&self) -> LEV7_R { + LEV7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Level 8"] + #[inline(always)] + pub fn lev8(&self) -> LEV8_R { + LEV8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Level 9"] + #[inline(always)] + pub fn lev9(&self) -> LEV9_R { + LEV9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Level 10"] + #[inline(always)] + pub fn lev10(&self) -> LEV10_R { + LEV10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Level 11"] + #[inline(always)] + pub fn lev11(&self) -> LEV11_R { + LEV11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Level 12"] + #[inline(always)] + pub fn lev12(&self) -> LEV12_R { + LEV12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Level 13"] + #[inline(always)] + pub fn lev13(&self) -> LEV13_R { + LEV13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Level 14"] + #[inline(always)] + pub fn lev14(&self) -> LEV14_R { + LEV14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Level 15"] + #[inline(always)] + pub fn lev15(&self) -> LEV15_R { + LEV15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Level 16"] + #[inline(always)] + pub fn lev16(&self) -> LEV16_R { + LEV16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Level 17"] + #[inline(always)] + pub fn lev17(&self) -> LEV17_R { + LEV17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Level 18"] + #[inline(always)] + pub fn lev18(&self) -> LEV18_R { + LEV18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Level 19"] + #[inline(always)] + pub fn lev19(&self) -> LEV19_R { + LEV19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Level 20"] + #[inline(always)] + pub fn lev20(&self) -> LEV20_R { + LEV20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Level 21"] + #[inline(always)] + pub fn lev21(&self) -> LEV21_R { + LEV21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Level 22"] + #[inline(always)] + pub fn lev22(&self) -> LEV22_R { + LEV22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Level 23"] + #[inline(always)] + pub fn lev23(&self) -> LEV23_R { + LEV23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Level 24"] + #[inline(always)] + pub fn lev24(&self) -> LEV24_R { + LEV24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Level 25"] + #[inline(always)] + pub fn lev25(&self) -> LEV25_R { + LEV25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Level 26"] + #[inline(always)] + pub fn lev26(&self) -> LEV26_R { + LEV26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Level 27"] + #[inline(always)] + pub fn lev27(&self) -> LEV27_R { + LEV27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Level 28"] + #[inline(always)] + pub fn lev28(&self) -> LEV28_R { + LEV28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Level 29"] + #[inline(always)] + pub fn lev29(&self) -> LEV29_R { + LEV29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Level 30"] + #[inline(always)] + pub fn lev30(&self) -> LEV30_R { + LEV30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Level 31"] + #[inline(always)] + pub fn lev31(&self) -> LEV31_R { + LEV31_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "GPIO Pin Level 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev0](index.html) module"] +pub struct GPLEV0_SPEC; +impl crate::RegisterSpec for GPLEV0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplev0::R](R) reader structure"] +impl crate::Readable for GPLEV0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/gpio/gplev1.rs b/crates/bcm2711-lpa/src/gpio/gplev1.rs new file mode 100644 index 0000000..c351377 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gplev1.rs @@ -0,0 +1,208 @@ +#[doc = "Register `GPLEV1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LEV32` reader - Level 32"] +pub type LEV32_R = crate::BitReader; +#[doc = "Field `LEV33` reader - Level 33"] +pub type LEV33_R = crate::BitReader; +#[doc = "Field `LEV34` reader - Level 34"] +pub type LEV34_R = crate::BitReader; +#[doc = "Field `LEV35` reader - Level 35"] +pub type LEV35_R = crate::BitReader; +#[doc = "Field `LEV36` reader - Level 36"] +pub type LEV36_R = crate::BitReader; +#[doc = "Field `LEV37` reader - Level 37"] +pub type LEV37_R = crate::BitReader; +#[doc = "Field `LEV38` reader - Level 38"] +pub type LEV38_R = crate::BitReader; +#[doc = "Field `LEV39` reader - Level 39"] +pub type LEV39_R = crate::BitReader; +#[doc = "Field `LEV40` reader - Level 40"] +pub type LEV40_R = crate::BitReader; +#[doc = "Field `LEV41` reader - Level 41"] +pub type LEV41_R = crate::BitReader; +#[doc = "Field `LEV42` reader - Level 42"] +pub type LEV42_R = crate::BitReader; +#[doc = "Field `LEV43` reader - Level 43"] +pub type LEV43_R = crate::BitReader; +#[doc = "Field `LEV44` reader - Level 44"] +pub type LEV44_R = crate::BitReader; +#[doc = "Field `LEV45` reader - Level 45"] +pub type LEV45_R = crate::BitReader; +#[doc = "Field `LEV46` reader - Level 46"] +pub type LEV46_R = crate::BitReader; +#[doc = "Field `LEV47` reader - Level 47"] +pub type LEV47_R = crate::BitReader; +#[doc = "Field `LEV48` reader - Level 48"] +pub type LEV48_R = crate::BitReader; +#[doc = "Field `LEV49` reader - Level 49"] +pub type LEV49_R = crate::BitReader; +#[doc = "Field `LEV50` reader - Level 50"] +pub type LEV50_R = crate::BitReader; +#[doc = "Field `LEV51` reader - Level 51"] +pub type LEV51_R = crate::BitReader; +#[doc = "Field `LEV52` reader - Level 52"] +pub type LEV52_R = crate::BitReader; +#[doc = "Field `LEV53` reader - Level 53"] +pub type LEV53_R = crate::BitReader; +#[doc = "Field `LEV54` reader - Level 54"] +pub type LEV54_R = crate::BitReader; +#[doc = "Field `LEV55` reader - Level 55"] +pub type LEV55_R = crate::BitReader; +#[doc = "Field `LEV56` reader - Level 56"] +pub type LEV56_R = crate::BitReader; +#[doc = "Field `LEV57` reader - Level 57"] +pub type LEV57_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Level 32"] + #[inline(always)] + pub fn lev32(&self) -> LEV32_R { + LEV32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 33"] + #[inline(always)] + pub fn lev33(&self) -> LEV33_R { + LEV33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 34"] + #[inline(always)] + pub fn lev34(&self) -> LEV34_R { + LEV34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 35"] + #[inline(always)] + pub fn lev35(&self) -> LEV35_R { + LEV35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Level 36"] + #[inline(always)] + pub fn lev36(&self) -> LEV36_R { + LEV36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Level 37"] + #[inline(always)] + pub fn lev37(&self) -> LEV37_R { + LEV37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Level 38"] + #[inline(always)] + pub fn lev38(&self) -> LEV38_R { + LEV38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Level 39"] + #[inline(always)] + pub fn lev39(&self) -> LEV39_R { + LEV39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Level 40"] + #[inline(always)] + pub fn lev40(&self) -> LEV40_R { + LEV40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Level 41"] + #[inline(always)] + pub fn lev41(&self) -> LEV41_R { + LEV41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Level 42"] + #[inline(always)] + pub fn lev42(&self) -> LEV42_R { + LEV42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Level 43"] + #[inline(always)] + pub fn lev43(&self) -> LEV43_R { + LEV43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Level 44"] + #[inline(always)] + pub fn lev44(&self) -> LEV44_R { + LEV44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Level 45"] + #[inline(always)] + pub fn lev45(&self) -> LEV45_R { + LEV45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Level 46"] + #[inline(always)] + pub fn lev46(&self) -> LEV46_R { + LEV46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Level 47"] + #[inline(always)] + pub fn lev47(&self) -> LEV47_R { + LEV47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Level 48"] + #[inline(always)] + pub fn lev48(&self) -> LEV48_R { + LEV48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Level 49"] + #[inline(always)] + pub fn lev49(&self) -> LEV49_R { + LEV49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Level 50"] + #[inline(always)] + pub fn lev50(&self) -> LEV50_R { + LEV50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Level 51"] + #[inline(always)] + pub fn lev51(&self) -> LEV51_R { + LEV51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Level 52"] + #[inline(always)] + pub fn lev52(&self) -> LEV52_R { + LEV52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Level 53"] + #[inline(always)] + pub fn lev53(&self) -> LEV53_R { + LEV53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Level 54"] + #[inline(always)] + pub fn lev54(&self) -> LEV54_R { + LEV54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Level 55"] + #[inline(always)] + pub fn lev55(&self) -> LEV55_R { + LEV55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Level 56"] + #[inline(always)] + pub fn lev56(&self) -> LEV56_R { + LEV56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Level 57"] + #[inline(always)] + pub fn lev57(&self) -> LEV57_R { + LEV57_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[doc = "GPIO Pin Level 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev1](index.html) module"] +pub struct GPLEV1_SPEC; +impl crate::RegisterSpec for GPLEV1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplev1::R](R) reader structure"] +impl crate::Readable for GPLEV1_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpren0.rs b/crates/bcm2711-lpa/src/gpio/gpren0.rs new file mode 100644 index 0000000..af4f16c --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpren0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPREN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REN0` reader - Rising edge enabled 0"] +pub type REN0_R = crate::BitReader; +#[doc = "Field `REN0` writer - Rising edge enabled 0"] +pub type REN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN1` reader - Rising edge enabled 1"] +pub type REN1_R = crate::BitReader; +#[doc = "Field `REN1` writer - Rising edge enabled 1"] +pub type REN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN2` reader - Rising edge enabled 2"] +pub type REN2_R = crate::BitReader; +#[doc = "Field `REN2` writer - Rising edge enabled 2"] +pub type REN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN3` reader - Rising edge enabled 3"] +pub type REN3_R = crate::BitReader; +#[doc = "Field `REN3` writer - Rising edge enabled 3"] +pub type REN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN4` reader - Rising edge enabled 4"] +pub type REN4_R = crate::BitReader; +#[doc = "Field `REN4` writer - Rising edge enabled 4"] +pub type REN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN5` reader - Rising edge enabled 5"] +pub type REN5_R = crate::BitReader; +#[doc = "Field `REN5` writer - Rising edge enabled 5"] +pub type REN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN6` reader - Rising edge enabled 6"] +pub type REN6_R = crate::BitReader; +#[doc = "Field `REN6` writer - Rising edge enabled 6"] +pub type REN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN7` reader - Rising edge enabled 7"] +pub type REN7_R = crate::BitReader; +#[doc = "Field `REN7` writer - Rising edge enabled 7"] +pub type REN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN8` reader - Rising edge enabled 8"] +pub type REN8_R = crate::BitReader; +#[doc = "Field `REN8` writer - Rising edge enabled 8"] +pub type REN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN9` reader - Rising edge enabled 9"] +pub type REN9_R = crate::BitReader; +#[doc = "Field `REN9` writer - Rising edge enabled 9"] +pub type REN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN10` reader - Rising edge enabled 10"] +pub type REN10_R = crate::BitReader; +#[doc = "Field `REN10` writer - Rising edge enabled 10"] +pub type REN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN11` reader - Rising edge enabled 11"] +pub type REN11_R = crate::BitReader; +#[doc = "Field `REN11` writer - Rising edge enabled 11"] +pub type REN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN12` reader - Rising edge enabled 12"] +pub type REN12_R = crate::BitReader; +#[doc = "Field `REN12` writer - Rising edge enabled 12"] +pub type REN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN13` reader - Rising edge enabled 13"] +pub type REN13_R = crate::BitReader; +#[doc = "Field `REN13` writer - Rising edge enabled 13"] +pub type REN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN14` reader - Rising edge enabled 14"] +pub type REN14_R = crate::BitReader; +#[doc = "Field `REN14` writer - Rising edge enabled 14"] +pub type REN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN15` reader - Rising edge enabled 15"] +pub type REN15_R = crate::BitReader; +#[doc = "Field `REN15` writer - Rising edge enabled 15"] +pub type REN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN16` reader - Rising edge enabled 16"] +pub type REN16_R = crate::BitReader; +#[doc = "Field `REN16` writer - Rising edge enabled 16"] +pub type REN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN17` reader - Rising edge enabled 17"] +pub type REN17_R = crate::BitReader; +#[doc = "Field `REN17` writer - Rising edge enabled 17"] +pub type REN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN18` reader - Rising edge enabled 18"] +pub type REN18_R = crate::BitReader; +#[doc = "Field `REN18` writer - Rising edge enabled 18"] +pub type REN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN19` reader - Rising edge enabled 19"] +pub type REN19_R = crate::BitReader; +#[doc = "Field `REN19` writer - Rising edge enabled 19"] +pub type REN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN20` reader - Rising edge enabled 20"] +pub type REN20_R = crate::BitReader; +#[doc = "Field `REN20` writer - Rising edge enabled 20"] +pub type REN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN21` reader - Rising edge enabled 21"] +pub type REN21_R = crate::BitReader; +#[doc = "Field `REN21` writer - Rising edge enabled 21"] +pub type REN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN22` reader - Rising edge enabled 22"] +pub type REN22_R = crate::BitReader; +#[doc = "Field `REN22` writer - Rising edge enabled 22"] +pub type REN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN23` reader - Rising edge enabled 23"] +pub type REN23_R = crate::BitReader; +#[doc = "Field `REN23` writer - Rising edge enabled 23"] +pub type REN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN24` reader - Rising edge enabled 24"] +pub type REN24_R = crate::BitReader; +#[doc = "Field `REN24` writer - Rising edge enabled 24"] +pub type REN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN25` reader - Rising edge enabled 25"] +pub type REN25_R = crate::BitReader; +#[doc = "Field `REN25` writer - Rising edge enabled 25"] +pub type REN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN26` reader - Rising edge enabled 26"] +pub type REN26_R = crate::BitReader; +#[doc = "Field `REN26` writer - Rising edge enabled 26"] +pub type REN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN27` reader - Rising edge enabled 27"] +pub type REN27_R = crate::BitReader; +#[doc = "Field `REN27` writer - Rising edge enabled 27"] +pub type REN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN28` reader - Rising edge enabled 28"] +pub type REN28_R = crate::BitReader; +#[doc = "Field `REN28` writer - Rising edge enabled 28"] +pub type REN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN29` reader - Rising edge enabled 29"] +pub type REN29_R = crate::BitReader; +#[doc = "Field `REN29` writer - Rising edge enabled 29"] +pub type REN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN30` reader - Rising edge enabled 30"] +pub type REN30_R = crate::BitReader; +#[doc = "Field `REN30` writer - Rising edge enabled 30"] +pub type REN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN31` reader - Rising edge enabled 31"] +pub type REN31_R = crate::BitReader; +#[doc = "Field `REN31` writer - Rising edge enabled 31"] +pub type REN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Rising edge enabled 0"] + #[inline(always)] + pub fn ren0(&self) -> REN0_R { + REN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rising edge enabled 1"] + #[inline(always)] + pub fn ren1(&self) -> REN1_R { + REN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Rising edge enabled 2"] + #[inline(always)] + pub fn ren2(&self) -> REN2_R { + REN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising edge enabled 3"] + #[inline(always)] + pub fn ren3(&self) -> REN3_R { + REN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Rising edge enabled 4"] + #[inline(always)] + pub fn ren4(&self) -> REN4_R { + REN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Rising edge enabled 5"] + #[inline(always)] + pub fn ren5(&self) -> REN5_R { + REN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising edge enabled 6"] + #[inline(always)] + pub fn ren6(&self) -> REN6_R { + REN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Rising edge enabled 7"] + #[inline(always)] + pub fn ren7(&self) -> REN7_R { + REN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Rising edge enabled 8"] + #[inline(always)] + pub fn ren8(&self) -> REN8_R { + REN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising edge enabled 9"] + #[inline(always)] + pub fn ren9(&self) -> REN9_R { + REN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Rising edge enabled 10"] + #[inline(always)] + pub fn ren10(&self) -> REN10_R { + REN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Rising edge enabled 11"] + #[inline(always)] + pub fn ren11(&self) -> REN11_R { + REN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Rising edge enabled 12"] + #[inline(always)] + pub fn ren12(&self) -> REN12_R { + REN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Rising edge enabled 13"] + #[inline(always)] + pub fn ren13(&self) -> REN13_R { + REN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Rising edge enabled 14"] + #[inline(always)] + pub fn ren14(&self) -> REN14_R { + REN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Rising edge enabled 15"] + #[inline(always)] + pub fn ren15(&self) -> REN15_R { + REN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Rising edge enabled 16"] + #[inline(always)] + pub fn ren16(&self) -> REN16_R { + REN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Rising edge enabled 17"] + #[inline(always)] + pub fn ren17(&self) -> REN17_R { + REN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Rising edge enabled 18"] + #[inline(always)] + pub fn ren18(&self) -> REN18_R { + REN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Rising edge enabled 19"] + #[inline(always)] + pub fn ren19(&self) -> REN19_R { + REN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Rising edge enabled 20"] + #[inline(always)] + pub fn ren20(&self) -> REN20_R { + REN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Rising edge enabled 21"] + #[inline(always)] + pub fn ren21(&self) -> REN21_R { + REN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Rising edge enabled 22"] + #[inline(always)] + pub fn ren22(&self) -> REN22_R { + REN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Rising edge enabled 23"] + #[inline(always)] + pub fn ren23(&self) -> REN23_R { + REN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Rising edge enabled 24"] + #[inline(always)] + pub fn ren24(&self) -> REN24_R { + REN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Rising edge enabled 25"] + #[inline(always)] + pub fn ren25(&self) -> REN25_R { + REN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Rising edge enabled 26"] + #[inline(always)] + pub fn ren26(&self) -> REN26_R { + REN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Rising edge enabled 27"] + #[inline(always)] + pub fn ren27(&self) -> REN27_R { + REN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Rising edge enabled 28"] + #[inline(always)] + pub fn ren28(&self) -> REN28_R { + REN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Rising edge enabled 29"] + #[inline(always)] + pub fn ren29(&self) -> REN29_R { + REN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Rising edge enabled 30"] + #[inline(always)] + pub fn ren30(&self) -> REN30_R { + REN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Rising edge enabled 31"] + #[inline(always)] + pub fn ren31(&self) -> REN31_R { + REN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising edge enabled 0"] + #[inline(always)] + #[must_use] + pub fn ren0(&mut self) -> REN0_W<0> { + REN0_W::new(self) + } + #[doc = "Bit 1 - Rising edge enabled 1"] + #[inline(always)] + #[must_use] + pub fn ren1(&mut self) -> REN1_W<1> { + REN1_W::new(self) + } + #[doc = "Bit 2 - Rising edge enabled 2"] + #[inline(always)] + #[must_use] + pub fn ren2(&mut self) -> REN2_W<2> { + REN2_W::new(self) + } + #[doc = "Bit 3 - Rising edge enabled 3"] + #[inline(always)] + #[must_use] + pub fn ren3(&mut self) -> REN3_W<3> { + REN3_W::new(self) + } + #[doc = "Bit 4 - Rising edge enabled 4"] + #[inline(always)] + #[must_use] + pub fn ren4(&mut self) -> REN4_W<4> { + REN4_W::new(self) + } + #[doc = "Bit 5 - Rising edge enabled 5"] + #[inline(always)] + #[must_use] + pub fn ren5(&mut self) -> REN5_W<5> { + REN5_W::new(self) + } + #[doc = "Bit 6 - Rising edge enabled 6"] + #[inline(always)] + #[must_use] + pub fn ren6(&mut self) -> REN6_W<6> { + REN6_W::new(self) + } + #[doc = "Bit 7 - Rising edge enabled 7"] + #[inline(always)] + #[must_use] + pub fn ren7(&mut self) -> REN7_W<7> { + REN7_W::new(self) + } + #[doc = "Bit 8 - Rising edge enabled 8"] + #[inline(always)] + #[must_use] + pub fn ren8(&mut self) -> REN8_W<8> { + REN8_W::new(self) + } + #[doc = "Bit 9 - Rising edge enabled 9"] + #[inline(always)] + #[must_use] + pub fn ren9(&mut self) -> REN9_W<9> { + REN9_W::new(self) + } + #[doc = "Bit 10 - Rising edge enabled 10"] + #[inline(always)] + #[must_use] + pub fn ren10(&mut self) -> REN10_W<10> { + REN10_W::new(self) + } + #[doc = "Bit 11 - Rising edge enabled 11"] + #[inline(always)] + #[must_use] + pub fn ren11(&mut self) -> REN11_W<11> { + REN11_W::new(self) + } + #[doc = "Bit 12 - Rising edge enabled 12"] + #[inline(always)] + #[must_use] + pub fn ren12(&mut self) -> REN12_W<12> { + REN12_W::new(self) + } + #[doc = "Bit 13 - Rising edge enabled 13"] + #[inline(always)] + #[must_use] + pub fn ren13(&mut self) -> REN13_W<13> { + REN13_W::new(self) + } + #[doc = "Bit 14 - Rising edge enabled 14"] + #[inline(always)] + #[must_use] + pub fn ren14(&mut self) -> REN14_W<14> { + REN14_W::new(self) + } + #[doc = "Bit 15 - Rising edge enabled 15"] + #[inline(always)] + #[must_use] + pub fn ren15(&mut self) -> REN15_W<15> { + REN15_W::new(self) + } + #[doc = "Bit 16 - Rising edge enabled 16"] + #[inline(always)] + #[must_use] + pub fn ren16(&mut self) -> REN16_W<16> { + REN16_W::new(self) + } + #[doc = "Bit 17 - Rising edge enabled 17"] + #[inline(always)] + #[must_use] + pub fn ren17(&mut self) -> REN17_W<17> { + REN17_W::new(self) + } + #[doc = "Bit 18 - Rising edge enabled 18"] + #[inline(always)] + #[must_use] + pub fn ren18(&mut self) -> REN18_W<18> { + REN18_W::new(self) + } + #[doc = "Bit 19 - Rising edge enabled 19"] + #[inline(always)] + #[must_use] + pub fn ren19(&mut self) -> REN19_W<19> { + REN19_W::new(self) + } + #[doc = "Bit 20 - Rising edge enabled 20"] + #[inline(always)] + #[must_use] + pub fn ren20(&mut self) -> REN20_W<20> { + REN20_W::new(self) + } + #[doc = "Bit 21 - Rising edge enabled 21"] + #[inline(always)] + #[must_use] + pub fn ren21(&mut self) -> REN21_W<21> { + REN21_W::new(self) + } + #[doc = "Bit 22 - Rising edge enabled 22"] + #[inline(always)] + #[must_use] + pub fn ren22(&mut self) -> REN22_W<22> { + REN22_W::new(self) + } + #[doc = "Bit 23 - Rising edge enabled 23"] + #[inline(always)] + #[must_use] + pub fn ren23(&mut self) -> REN23_W<23> { + REN23_W::new(self) + } + #[doc = "Bit 24 - Rising edge enabled 24"] + #[inline(always)] + #[must_use] + pub fn ren24(&mut self) -> REN24_W<24> { + REN24_W::new(self) + } + #[doc = "Bit 25 - Rising edge enabled 25"] + #[inline(always)] + #[must_use] + pub fn ren25(&mut self) -> REN25_W<25> { + REN25_W::new(self) + } + #[doc = "Bit 26 - Rising edge enabled 26"] + #[inline(always)] + #[must_use] + pub fn ren26(&mut self) -> REN26_W<26> { + REN26_W::new(self) + } + #[doc = "Bit 27 - Rising edge enabled 27"] + #[inline(always)] + #[must_use] + pub fn ren27(&mut self) -> REN27_W<27> { + REN27_W::new(self) + } + #[doc = "Bit 28 - Rising edge enabled 28"] + #[inline(always)] + #[must_use] + pub fn ren28(&mut self) -> REN28_W<28> { + REN28_W::new(self) + } + #[doc = "Bit 29 - Rising edge enabled 29"] + #[inline(always)] + #[must_use] + pub fn ren29(&mut self) -> REN29_W<29> { + REN29_W::new(self) + } + #[doc = "Bit 30 - Rising edge enabled 30"] + #[inline(always)] + #[must_use] + pub fn ren30(&mut self) -> REN30_W<30> { + REN30_W::new(self) + } + #[doc = "Bit 31 - Rising edge enabled 31"] + #[inline(always)] + #[must_use] + pub fn ren31(&mut self) -> REN31_W<31> { + REN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren0](index.html) module"] +pub struct GPREN0_SPEC; +impl crate::RegisterSpec for GPREN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpren0::R](R) reader structure"] +impl crate::Readable for GPREN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpren0::W](W) writer structure"] +impl crate::Writable for GPREN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpren1.rs b/crates/bcm2711-lpa/src/gpio/gpren1.rs new file mode 100644 index 0000000..e5b0650 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpren1.rs @@ -0,0 +1,451 @@ +#[doc = "Register `GPREN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REN32` reader - Rising edge enabled 32"] +pub type REN32_R = crate::BitReader; +#[doc = "Field `REN32` writer - Rising edge enabled 32"] +pub type REN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN33` reader - Rising edge enabled 33"] +pub type REN33_R = crate::BitReader; +#[doc = "Field `REN33` writer - Rising edge enabled 33"] +pub type REN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN34` reader - Rising edge enabled 34"] +pub type REN34_R = crate::BitReader; +#[doc = "Field `REN34` writer - Rising edge enabled 34"] +pub type REN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN35` reader - Rising edge enabled 35"] +pub type REN35_R = crate::BitReader; +#[doc = "Field `REN35` writer - Rising edge enabled 35"] +pub type REN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN36` reader - Rising edge enabled 36"] +pub type REN36_R = crate::BitReader; +#[doc = "Field `REN36` writer - Rising edge enabled 36"] +pub type REN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN37` reader - Rising edge enabled 37"] +pub type REN37_R = crate::BitReader; +#[doc = "Field `REN37` writer - Rising edge enabled 37"] +pub type REN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN38` reader - Rising edge enabled 38"] +pub type REN38_R = crate::BitReader; +#[doc = "Field `REN38` writer - Rising edge enabled 38"] +pub type REN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN39` reader - Rising edge enabled 39"] +pub type REN39_R = crate::BitReader; +#[doc = "Field `REN39` writer - Rising edge enabled 39"] +pub type REN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN40` reader - Rising edge enabled 40"] +pub type REN40_R = crate::BitReader; +#[doc = "Field `REN40` writer - Rising edge enabled 40"] +pub type REN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN41` reader - Rising edge enabled 41"] +pub type REN41_R = crate::BitReader; +#[doc = "Field `REN41` writer - Rising edge enabled 41"] +pub type REN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN42` reader - Rising edge enabled 42"] +pub type REN42_R = crate::BitReader; +#[doc = "Field `REN42` writer - Rising edge enabled 42"] +pub type REN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN43` reader - Rising edge enabled 43"] +pub type REN43_R = crate::BitReader; +#[doc = "Field `REN43` writer - Rising edge enabled 43"] +pub type REN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN44` reader - Rising edge enabled 44"] +pub type REN44_R = crate::BitReader; +#[doc = "Field `REN44` writer - Rising edge enabled 44"] +pub type REN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN45` reader - Rising edge enabled 45"] +pub type REN45_R = crate::BitReader; +#[doc = "Field `REN45` writer - Rising edge enabled 45"] +pub type REN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN46` reader - Rising edge enabled 46"] +pub type REN46_R = crate::BitReader; +#[doc = "Field `REN46` writer - Rising edge enabled 46"] +pub type REN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN47` reader - Rising edge enabled 47"] +pub type REN47_R = crate::BitReader; +#[doc = "Field `REN47` writer - Rising edge enabled 47"] +pub type REN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN48` reader - Rising edge enabled 48"] +pub type REN48_R = crate::BitReader; +#[doc = "Field `REN48` writer - Rising edge enabled 48"] +pub type REN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN49` reader - Rising edge enabled 49"] +pub type REN49_R = crate::BitReader; +#[doc = "Field `REN49` writer - Rising edge enabled 49"] +pub type REN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN50` reader - Rising edge enabled 50"] +pub type REN50_R = crate::BitReader; +#[doc = "Field `REN50` writer - Rising edge enabled 50"] +pub type REN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN51` reader - Rising edge enabled 51"] +pub type REN51_R = crate::BitReader; +#[doc = "Field `REN51` writer - Rising edge enabled 51"] +pub type REN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN52` reader - Rising edge enabled 52"] +pub type REN52_R = crate::BitReader; +#[doc = "Field `REN52` writer - Rising edge enabled 52"] +pub type REN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN53` reader - Rising edge enabled 53"] +pub type REN53_R = crate::BitReader; +#[doc = "Field `REN53` writer - Rising edge enabled 53"] +pub type REN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN54` reader - Rising edge enabled 54"] +pub type REN54_R = crate::BitReader; +#[doc = "Field `REN54` writer - Rising edge enabled 54"] +pub type REN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN55` reader - Rising edge enabled 55"] +pub type REN55_R = crate::BitReader; +#[doc = "Field `REN55` writer - Rising edge enabled 55"] +pub type REN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN56` reader - Rising edge enabled 56"] +pub type REN56_R = crate::BitReader; +#[doc = "Field `REN56` writer - Rising edge enabled 56"] +pub type REN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN57` reader - Rising edge enabled 57"] +pub type REN57_R = crate::BitReader; +#[doc = "Field `REN57` writer - Rising edge enabled 57"] +pub type REN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Rising edge enabled 32"] + #[inline(always)] + pub fn ren32(&self) -> REN32_R { + REN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rising edge enabled 33"] + #[inline(always)] + pub fn ren33(&self) -> REN33_R { + REN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Rising edge enabled 34"] + #[inline(always)] + pub fn ren34(&self) -> REN34_R { + REN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising edge enabled 35"] + #[inline(always)] + pub fn ren35(&self) -> REN35_R { + REN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Rising edge enabled 36"] + #[inline(always)] + pub fn ren36(&self) -> REN36_R { + REN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Rising edge enabled 37"] + #[inline(always)] + pub fn ren37(&self) -> REN37_R { + REN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising edge enabled 38"] + #[inline(always)] + pub fn ren38(&self) -> REN38_R { + REN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Rising edge enabled 39"] + #[inline(always)] + pub fn ren39(&self) -> REN39_R { + REN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Rising edge enabled 40"] + #[inline(always)] + pub fn ren40(&self) -> REN40_R { + REN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising edge enabled 41"] + #[inline(always)] + pub fn ren41(&self) -> REN41_R { + REN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Rising edge enabled 42"] + #[inline(always)] + pub fn ren42(&self) -> REN42_R { + REN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Rising edge enabled 43"] + #[inline(always)] + pub fn ren43(&self) -> REN43_R { + REN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Rising edge enabled 44"] + #[inline(always)] + pub fn ren44(&self) -> REN44_R { + REN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Rising edge enabled 45"] + #[inline(always)] + pub fn ren45(&self) -> REN45_R { + REN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Rising edge enabled 46"] + #[inline(always)] + pub fn ren46(&self) -> REN46_R { + REN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Rising edge enabled 47"] + #[inline(always)] + pub fn ren47(&self) -> REN47_R { + REN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Rising edge enabled 48"] + #[inline(always)] + pub fn ren48(&self) -> REN48_R { + REN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Rising edge enabled 49"] + #[inline(always)] + pub fn ren49(&self) -> REN49_R { + REN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Rising edge enabled 50"] + #[inline(always)] + pub fn ren50(&self) -> REN50_R { + REN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Rising edge enabled 51"] + #[inline(always)] + pub fn ren51(&self) -> REN51_R { + REN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Rising edge enabled 52"] + #[inline(always)] + pub fn ren52(&self) -> REN52_R { + REN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Rising edge enabled 53"] + #[inline(always)] + pub fn ren53(&self) -> REN53_R { + REN53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Rising edge enabled 54"] + #[inline(always)] + pub fn ren54(&self) -> REN54_R { + REN54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Rising edge enabled 55"] + #[inline(always)] + pub fn ren55(&self) -> REN55_R { + REN55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Rising edge enabled 56"] + #[inline(always)] + pub fn ren56(&self) -> REN56_R { + REN56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Rising edge enabled 57"] + #[inline(always)] + pub fn ren57(&self) -> REN57_R { + REN57_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising edge enabled 32"] + #[inline(always)] + #[must_use] + pub fn ren32(&mut self) -> REN32_W<0> { + REN32_W::new(self) + } + #[doc = "Bit 1 - Rising edge enabled 33"] + #[inline(always)] + #[must_use] + pub fn ren33(&mut self) -> REN33_W<1> { + REN33_W::new(self) + } + #[doc = "Bit 2 - Rising edge enabled 34"] + #[inline(always)] + #[must_use] + pub fn ren34(&mut self) -> REN34_W<2> { + REN34_W::new(self) + } + #[doc = "Bit 3 - Rising edge enabled 35"] + #[inline(always)] + #[must_use] + pub fn ren35(&mut self) -> REN35_W<3> { + REN35_W::new(self) + } + #[doc = "Bit 4 - Rising edge enabled 36"] + #[inline(always)] + #[must_use] + pub fn ren36(&mut self) -> REN36_W<4> { + REN36_W::new(self) + } + #[doc = "Bit 5 - Rising edge enabled 37"] + #[inline(always)] + #[must_use] + pub fn ren37(&mut self) -> REN37_W<5> { + REN37_W::new(self) + } + #[doc = "Bit 6 - Rising edge enabled 38"] + #[inline(always)] + #[must_use] + pub fn ren38(&mut self) -> REN38_W<6> { + REN38_W::new(self) + } + #[doc = "Bit 7 - Rising edge enabled 39"] + #[inline(always)] + #[must_use] + pub fn ren39(&mut self) -> REN39_W<7> { + REN39_W::new(self) + } + #[doc = "Bit 8 - Rising edge enabled 40"] + #[inline(always)] + #[must_use] + pub fn ren40(&mut self) -> REN40_W<8> { + REN40_W::new(self) + } + #[doc = "Bit 9 - Rising edge enabled 41"] + #[inline(always)] + #[must_use] + pub fn ren41(&mut self) -> REN41_W<9> { + REN41_W::new(self) + } + #[doc = "Bit 10 - Rising edge enabled 42"] + #[inline(always)] + #[must_use] + pub fn ren42(&mut self) -> REN42_W<10> { + REN42_W::new(self) + } + #[doc = "Bit 11 - Rising edge enabled 43"] + #[inline(always)] + #[must_use] + pub fn ren43(&mut self) -> REN43_W<11> { + REN43_W::new(self) + } + #[doc = "Bit 12 - Rising edge enabled 44"] + #[inline(always)] + #[must_use] + pub fn ren44(&mut self) -> REN44_W<12> { + REN44_W::new(self) + } + #[doc = "Bit 13 - Rising edge enabled 45"] + #[inline(always)] + #[must_use] + pub fn ren45(&mut self) -> REN45_W<13> { + REN45_W::new(self) + } + #[doc = "Bit 14 - Rising edge enabled 46"] + #[inline(always)] + #[must_use] + pub fn ren46(&mut self) -> REN46_W<14> { + REN46_W::new(self) + } + #[doc = "Bit 15 - Rising edge enabled 47"] + #[inline(always)] + #[must_use] + pub fn ren47(&mut self) -> REN47_W<15> { + REN47_W::new(self) + } + #[doc = "Bit 16 - Rising edge enabled 48"] + #[inline(always)] + #[must_use] + pub fn ren48(&mut self) -> REN48_W<16> { + REN48_W::new(self) + } + #[doc = "Bit 17 - Rising edge enabled 49"] + #[inline(always)] + #[must_use] + pub fn ren49(&mut self) -> REN49_W<17> { + REN49_W::new(self) + } + #[doc = "Bit 18 - Rising edge enabled 50"] + #[inline(always)] + #[must_use] + pub fn ren50(&mut self) -> REN50_W<18> { + REN50_W::new(self) + } + #[doc = "Bit 19 - Rising edge enabled 51"] + #[inline(always)] + #[must_use] + pub fn ren51(&mut self) -> REN51_W<19> { + REN51_W::new(self) + } + #[doc = "Bit 20 - Rising edge enabled 52"] + #[inline(always)] + #[must_use] + pub fn ren52(&mut self) -> REN52_W<20> { + REN52_W::new(self) + } + #[doc = "Bit 21 - Rising edge enabled 53"] + #[inline(always)] + #[must_use] + pub fn ren53(&mut self) -> REN53_W<21> { + REN53_W::new(self) + } + #[doc = "Bit 22 - Rising edge enabled 54"] + #[inline(always)] + #[must_use] + pub fn ren54(&mut self) -> REN54_W<22> { + REN54_W::new(self) + } + #[doc = "Bit 23 - Rising edge enabled 55"] + #[inline(always)] + #[must_use] + pub fn ren55(&mut self) -> REN55_W<23> { + REN55_W::new(self) + } + #[doc = "Bit 24 - Rising edge enabled 56"] + #[inline(always)] + #[must_use] + pub fn ren56(&mut self) -> REN56_W<24> { + REN56_W::new(self) + } + #[doc = "Bit 25 - Rising edge enabled 57"] + #[inline(always)] + #[must_use] + pub fn ren57(&mut self) -> REN57_W<25> { + REN57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren1](index.html) module"] +pub struct GPREN1_SPEC; +impl crate::RegisterSpec for GPREN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpren1::R](R) reader structure"] +impl crate::Readable for GPREN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpren1::W](W) writer structure"] +impl crate::Writable for GPREN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpset0.rs b/crates/bcm2711-lpa/src/gpio/gpset0.rs new file mode 100644 index 0000000..49e2659 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpset0.rs @@ -0,0 +1,296 @@ +#[doc = "Register `GPSET0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SET0` writer - Set 0"] +pub type SET0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET1` writer - Set 1"] +pub type SET1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET2` writer - Set 2"] +pub type SET2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET3` writer - Set 3"] +pub type SET3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET4` writer - Set 4"] +pub type SET4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET5` writer - Set 5"] +pub type SET5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET6` writer - Set 6"] +pub type SET6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET7` writer - Set 7"] +pub type SET7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET8` writer - Set 8"] +pub type SET8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET9` writer - Set 9"] +pub type SET9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET10` writer - Set 10"] +pub type SET10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET11` writer - Set 11"] +pub type SET11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET12` writer - Set 12"] +pub type SET12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET13` writer - Set 13"] +pub type SET13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET14` writer - Set 14"] +pub type SET14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET15` writer - Set 15"] +pub type SET15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET16` writer - Set 16"] +pub type SET16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET17` writer - Set 17"] +pub type SET17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET18` writer - Set 18"] +pub type SET18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET19` writer - Set 19"] +pub type SET19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET20` writer - Set 20"] +pub type SET20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET21` writer - Set 21"] +pub type SET21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET22` writer - Set 22"] +pub type SET22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET23` writer - Set 23"] +pub type SET23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET24` writer - Set 24"] +pub type SET24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET25` writer - Set 25"] +pub type SET25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET26` writer - Set 26"] +pub type SET26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET27` writer - Set 27"] +pub type SET27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET28` writer - Set 28"] +pub type SET28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET29` writer - Set 29"] +pub type SET29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET30` writer - Set 30"] +pub type SET30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET31` writer - Set 31"] +pub type SET31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Set 0"] + #[inline(always)] + #[must_use] + pub fn set0(&mut self) -> SET0_W<0> { + SET0_W::new(self) + } + #[doc = "Bit 1 - Set 1"] + #[inline(always)] + #[must_use] + pub fn set1(&mut self) -> SET1_W<1> { + SET1_W::new(self) + } + #[doc = "Bit 2 - Set 2"] + #[inline(always)] + #[must_use] + pub fn set2(&mut self) -> SET2_W<2> { + SET2_W::new(self) + } + #[doc = "Bit 3 - Set 3"] + #[inline(always)] + #[must_use] + pub fn set3(&mut self) -> SET3_W<3> { + SET3_W::new(self) + } + #[doc = "Bit 4 - Set 4"] + #[inline(always)] + #[must_use] + pub fn set4(&mut self) -> SET4_W<4> { + SET4_W::new(self) + } + #[doc = "Bit 5 - Set 5"] + #[inline(always)] + #[must_use] + pub fn set5(&mut self) -> SET5_W<5> { + SET5_W::new(self) + } + #[doc = "Bit 6 - Set 6"] + #[inline(always)] + #[must_use] + pub fn set6(&mut self) -> SET6_W<6> { + SET6_W::new(self) + } + #[doc = "Bit 7 - Set 7"] + #[inline(always)] + #[must_use] + pub fn set7(&mut self) -> SET7_W<7> { + SET7_W::new(self) + } + #[doc = "Bit 8 - Set 8"] + #[inline(always)] + #[must_use] + pub fn set8(&mut self) -> SET8_W<8> { + SET8_W::new(self) + } + #[doc = "Bit 9 - Set 9"] + #[inline(always)] + #[must_use] + pub fn set9(&mut self) -> SET9_W<9> { + SET9_W::new(self) + } + #[doc = "Bit 10 - Set 10"] + #[inline(always)] + #[must_use] + pub fn set10(&mut self) -> SET10_W<10> { + SET10_W::new(self) + } + #[doc = "Bit 11 - Set 11"] + #[inline(always)] + #[must_use] + pub fn set11(&mut self) -> SET11_W<11> { + SET11_W::new(self) + } + #[doc = "Bit 12 - Set 12"] + #[inline(always)] + #[must_use] + pub fn set12(&mut self) -> SET12_W<12> { + SET12_W::new(self) + } + #[doc = "Bit 13 - Set 13"] + #[inline(always)] + #[must_use] + pub fn set13(&mut self) -> SET13_W<13> { + SET13_W::new(self) + } + #[doc = "Bit 14 - Set 14"] + #[inline(always)] + #[must_use] + pub fn set14(&mut self) -> SET14_W<14> { + SET14_W::new(self) + } + #[doc = "Bit 15 - Set 15"] + #[inline(always)] + #[must_use] + pub fn set15(&mut self) -> SET15_W<15> { + SET15_W::new(self) + } + #[doc = "Bit 16 - Set 16"] + #[inline(always)] + #[must_use] + pub fn set16(&mut self) -> SET16_W<16> { + SET16_W::new(self) + } + #[doc = "Bit 17 - Set 17"] + #[inline(always)] + #[must_use] + pub fn set17(&mut self) -> SET17_W<17> { + SET17_W::new(self) + } + #[doc = "Bit 18 - Set 18"] + #[inline(always)] + #[must_use] + pub fn set18(&mut self) -> SET18_W<18> { + SET18_W::new(self) + } + #[doc = "Bit 19 - Set 19"] + #[inline(always)] + #[must_use] + pub fn set19(&mut self) -> SET19_W<19> { + SET19_W::new(self) + } + #[doc = "Bit 20 - Set 20"] + #[inline(always)] + #[must_use] + pub fn set20(&mut self) -> SET20_W<20> { + SET20_W::new(self) + } + #[doc = "Bit 21 - Set 21"] + #[inline(always)] + #[must_use] + pub fn set21(&mut self) -> SET21_W<21> { + SET21_W::new(self) + } + #[doc = "Bit 22 - Set 22"] + #[inline(always)] + #[must_use] + pub fn set22(&mut self) -> SET22_W<22> { + SET22_W::new(self) + } + #[doc = "Bit 23 - Set 23"] + #[inline(always)] + #[must_use] + pub fn set23(&mut self) -> SET23_W<23> { + SET23_W::new(self) + } + #[doc = "Bit 24 - Set 24"] + #[inline(always)] + #[must_use] + pub fn set24(&mut self) -> SET24_W<24> { + SET24_W::new(self) + } + #[doc = "Bit 25 - Set 25"] + #[inline(always)] + #[must_use] + pub fn set25(&mut self) -> SET25_W<25> { + SET25_W::new(self) + } + #[doc = "Bit 26 - Set 26"] + #[inline(always)] + #[must_use] + pub fn set26(&mut self) -> SET26_W<26> { + SET26_W::new(self) + } + #[doc = "Bit 27 - Set 27"] + #[inline(always)] + #[must_use] + pub fn set27(&mut self) -> SET27_W<27> { + SET27_W::new(self) + } + #[doc = "Bit 28 - Set 28"] + #[inline(always)] + #[must_use] + pub fn set28(&mut self) -> SET28_W<28> { + SET28_W::new(self) + } + #[doc = "Bit 29 - Set 29"] + #[inline(always)] + #[must_use] + pub fn set29(&mut self) -> SET29_W<29> { + SET29_W::new(self) + } + #[doc = "Bit 30 - Set 30"] + #[inline(always)] + #[must_use] + pub fn set30(&mut self) -> SET30_W<30> { + SET30_W::new(self) + } + #[doc = "Bit 31 - Set 31"] + #[inline(always)] + #[must_use] + pub fn set31(&mut self) -> SET31_W<31> { + SET31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Set 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset0](index.html) module"] +pub struct GPSET0_SPEC; +impl crate::RegisterSpec for GPSET0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpset0::W](W) writer structure"] +impl crate::Writable for GPSET0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2711-lpa/src/gpio/gpset1.rs b/crates/bcm2711-lpa/src/gpio/gpset1.rs new file mode 100644 index 0000000..8e7b482 --- /dev/null +++ b/crates/bcm2711-lpa/src/gpio/gpset1.rs @@ -0,0 +1,248 @@ +#[doc = "Register `GPSET1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SET32` writer - Set 32"] +pub type SET32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET33` writer - Set 33"] +pub type SET33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET34` writer - Set 34"] +pub type SET34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET35` writer - Set 35"] +pub type SET35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET36` writer - Set 36"] +pub type SET36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET37` writer - Set 37"] +pub type SET37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET38` writer - Set 38"] +pub type SET38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET39` writer - Set 39"] +pub type SET39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET40` writer - Set 40"] +pub type SET40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET41` writer - Set 41"] +pub type SET41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET42` writer - Set 42"] +pub type SET42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET43` writer - Set 43"] +pub type SET43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET44` writer - Set 44"] +pub type SET44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET45` writer - Set 45"] +pub type SET45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET46` writer - Set 46"] +pub type SET46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET47` writer - Set 47"] +pub type SET47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET48` writer - Set 48"] +pub type SET48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET49` writer - Set 49"] +pub type SET49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET50` writer - Set 50"] +pub type SET50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET51` writer - Set 51"] +pub type SET51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET52` writer - Set 52"] +pub type SET52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET53` writer - Set 53"] +pub type SET53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET54` writer - Set 54"] +pub type SET54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET55` writer - Set 55"] +pub type SET55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET56` writer - Set 56"] +pub type SET56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET57` writer - Set 57"] +pub type SET57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Set 32"] + #[inline(always)] + #[must_use] + pub fn set32(&mut self) -> SET32_W<0> { + SET32_W::new(self) + } + #[doc = "Bit 1 - Set 33"] + #[inline(always)] + #[must_use] + pub fn set33(&mut self) -> SET33_W<1> { + SET33_W::new(self) + } + #[doc = "Bit 2 - Set 34"] + #[inline(always)] + #[must_use] + pub fn set34(&mut self) -> SET34_W<2> { + SET34_W::new(self) + } + #[doc = "Bit 3 - Set 35"] + #[inline(always)] + #[must_use] + pub fn set35(&mut self) -> SET35_W<3> { + SET35_W::new(self) + } + #[doc = "Bit 4 - Set 36"] + #[inline(always)] + #[must_use] + pub fn set36(&mut self) -> SET36_W<4> { + SET36_W::new(self) + } + #[doc = "Bit 5 - Set 37"] + #[inline(always)] + #[must_use] + pub fn set37(&mut self) -> SET37_W<5> { + SET37_W::new(self) + } + #[doc = "Bit 6 - Set 38"] + #[inline(always)] + #[must_use] + pub fn set38(&mut self) -> SET38_W<6> { + SET38_W::new(self) + } + #[doc = "Bit 7 - Set 39"] + #[inline(always)] + #[must_use] + pub fn set39(&mut self) -> SET39_W<7> { + SET39_W::new(self) + } + #[doc = "Bit 8 - Set 40"] + #[inline(always)] + #[must_use] + pub fn set40(&mut self) -> SET40_W<8> { + SET40_W::new(self) + } + #[doc = "Bit 9 - Set 41"] + #[inline(always)] + #[must_use] + pub fn set41(&mut self) -> SET41_W<9> { + SET41_W::new(self) + } + #[doc = "Bit 10 - Set 42"] + #[inline(always)] + #[must_use] + pub fn set42(&mut self) -> SET42_W<10> { + SET42_W::new(self) + } + #[doc = "Bit 11 - Set 43"] + #[inline(always)] + #[must_use] + pub fn set43(&mut self) -> SET43_W<11> { + SET43_W::new(self) + } + #[doc = "Bit 12 - Set 44"] + #[inline(always)] + #[must_use] + pub fn set44(&mut self) -> SET44_W<12> { + SET44_W::new(self) + } + #[doc = "Bit 13 - Set 45"] + #[inline(always)] + #[must_use] + pub fn set45(&mut self) -> SET45_W<13> { + SET45_W::new(self) + } + #[doc = "Bit 14 - Set 46"] + #[inline(always)] + #[must_use] + pub fn set46(&mut self) -> SET46_W<14> { + SET46_W::new(self) + } + #[doc = "Bit 15 - Set 47"] + #[inline(always)] + #[must_use] + pub fn set47(&mut self) -> SET47_W<15> { + SET47_W::new(self) + } + #[doc = "Bit 16 - Set 48"] + #[inline(always)] + #[must_use] + pub fn set48(&mut self) -> SET48_W<16> { + SET48_W::new(self) + } + #[doc = "Bit 17 - Set 49"] + #[inline(always)] + #[must_use] + pub fn set49(&mut self) -> SET49_W<17> { + SET49_W::new(self) + } + #[doc = "Bit 18 - Set 50"] + #[inline(always)] + #[must_use] + pub fn set50(&mut self) -> SET50_W<18> { + SET50_W::new(self) + } + #[doc = "Bit 19 - Set 51"] + #[inline(always)] + #[must_use] + pub fn set51(&mut self) -> SET51_W<19> { + SET51_W::new(self) + } + #[doc = "Bit 20 - Set 52"] + #[inline(always)] + #[must_use] + pub fn set52(&mut self) -> SET52_W<20> { + SET52_W::new(self) + } + #[doc = "Bit 21 - Set 53"] + #[inline(always)] + #[must_use] + pub fn set53(&mut self) -> SET53_W<21> { + SET53_W::new(self) + } + #[doc = "Bit 22 - Set 54"] + #[inline(always)] + #[must_use] + pub fn set54(&mut self) -> SET54_W<22> { + SET54_W::new(self) + } + #[doc = "Bit 23 - Set 55"] + #[inline(always)] + #[must_use] + pub fn set55(&mut self) -> SET55_W<23> { + SET55_W::new(self) + } + #[doc = "Bit 24 - Set 56"] + #[inline(always)] + #[must_use] + pub fn set56(&mut self) -> SET56_W<24> { + SET56_W::new(self) + } + #[doc = "Bit 25 - Set 57"] + #[inline(always)] + #[must_use] + pub fn set57(&mut self) -> SET57_W<25> { + SET57_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Set 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset1](index.html) module"] +pub struct GPSET1_SPEC; +impl crate::RegisterSpec for GPSET1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpset1::W](W) writer structure"] +impl crate::Writable for GPSET1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03ff_ffff; +} diff --git a/crates/bcm2711-lpa/src/interrupt.rs b/crates/bcm2711-lpa/src/interrupt.rs new file mode 100644 index 0000000..7778bf2 --- /dev/null +++ b/crates/bcm2711-lpa/src/interrupt.rs @@ -0,0 +1,107 @@ +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - Software generated interrupt 0"] + SGI0 = 0, + #[doc = "1 - Software generated interrupt 1"] + SGI1 = 1, + #[doc = "2 - Software generated interrupt 2"] + SGI2 = 2, + #[doc = "3 - Software generated interrupt 3"] + SGI3 = 3, + #[doc = "4 - Software generated interrupt 4"] + SGI4 = 4, + #[doc = "5 - Software generated interrupt 5"] + SGI5 = 5, + #[doc = "6 - Software generated interrupt 6"] + SGI6 = 6, + #[doc = "7 - Software generated interrupt 7"] + SGI7 = 7, + #[doc = "8 - Software generated interrupt 8"] + SGI8 = 8, + #[doc = "9 - Software generated interrupt 9"] + SGI9 = 9, + #[doc = "10 - Software generated interrupt 10"] + SGI10 = 10, + #[doc = "11 - Software generated interrupt 11"] + SGI11 = 11, + #[doc = "12 - Software generated interrupt 12"] + SGI12 = 12, + #[doc = "13 - Software generated interrupt 13"] + SGI13 = 13, + #[doc = "14 - Software generated interrupt 14"] + SGI14 = 14, + #[doc = "15 - Software generated interrupt 15"] + SGI15 = 15, + #[doc = "62 - OR of EMMC and EMMC2"] + EMMC = 62, + #[doc = "96 - Timer 0 matched"] + TIMER_0 = 96, + #[doc = "97 - Timer 1 matched"] + TIMER_1 = 97, + #[doc = "98 - Timer 2 matched"] + TIMER_2 = 98, + #[doc = "99 - Timer 3 matched"] + TIMER_3 = 99, + #[doc = "105 - USB interrupt"] + USB = 105, + #[doc = "125 - Interrupt from AUX"] + AUX = 125, + #[doc = "145 - Interrupt from bank 0"] + GPIO0 = 145, + #[doc = "146 - Interrupt from bank 1"] + GPIO1 = 146, + #[doc = "147 - Interrupt from bank 2"] + GPIO2 = 147, + #[doc = "148 - OR of all GPIO interrupts"] + GPIO = 148, + #[doc = "149 - OR of all I2C interrupts"] + I2C = 149, + #[doc = "150 - OR of all SPI interrupts except 1 and 2"] + SPI = 150, + #[doc = "153 - OR of all UART interrupts except 1"] + UART = 153, +} +#[doc = r" TryFromInterruptError"] +#[derive(Debug, Copy, Clone)] +pub struct TryFromInterruptError(()); +impl Interrupt { + #[doc = r" Attempt to convert a given value into an `Interrupt`"] + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 0 => Ok(Interrupt::SGI0), + 1 => Ok(Interrupt::SGI1), + 2 => Ok(Interrupt::SGI2), + 3 => Ok(Interrupt::SGI3), + 4 => Ok(Interrupt::SGI4), + 5 => Ok(Interrupt::SGI5), + 6 => Ok(Interrupt::SGI6), + 7 => Ok(Interrupt::SGI7), + 8 => Ok(Interrupt::SGI8), + 9 => Ok(Interrupt::SGI9), + 10 => Ok(Interrupt::SGI10), + 11 => Ok(Interrupt::SGI11), + 12 => Ok(Interrupt::SGI12), + 13 => Ok(Interrupt::SGI13), + 14 => Ok(Interrupt::SGI14), + 15 => Ok(Interrupt::SGI15), + 62 => Ok(Interrupt::EMMC), + 96 => Ok(Interrupt::TIMER_0), + 97 => Ok(Interrupt::TIMER_1), + 98 => Ok(Interrupt::TIMER_2), + 99 => Ok(Interrupt::TIMER_3), + 105 => Ok(Interrupt::USB), + 125 => Ok(Interrupt::AUX), + 145 => Ok(Interrupt::GPIO0), + 146 => Ok(Interrupt::GPIO1), + 147 => Ok(Interrupt::GPIO2), + 148 => Ok(Interrupt::GPIO), + 149 => Ok(Interrupt::I2C), + 150 => Ok(Interrupt::SPI), + 153 => Ok(Interrupt::UART), + _ => Err(TryFromInterruptError(())), + } + } +} diff --git a/crates/bcm2711-lpa/src/lib.rs b/crates/bcm2711-lpa/src/lib.rs new file mode 100644 index 0000000..8f40b81 --- /dev/null +++ b/crates/bcm2711-lpa/src/lib.rs @@ -0,0 +1,1248 @@ +#![doc = "Peripheral access API for BCM2711_LPA microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[doc(hidden)] +pub mod interrupt; +pub use self::interrupt::Interrupt; +#[doc = "Mailboxes for talking to/from VideoCore"] +pub struct VCMAILBOX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for VCMAILBOX {} +impl VCMAILBOX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const vcmailbox::RegisterBlock = 0xfe00_b880 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const vcmailbox::RegisterBlock { + Self::PTR + } +} +impl Deref for VCMAILBOX { + type Target = vcmailbox::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for VCMAILBOX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VCMAILBOX").finish() + } +} +#[doc = "Mailboxes for talking to/from VideoCore"] +pub mod vcmailbox; +#[doc = "Broadcom Clock Manager"] +pub struct CM_PCM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CM_PCM {} +impl CM_PCM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cm_pcm::RegisterBlock = 0xfe10_1098 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cm_pcm::RegisterBlock { + Self::PTR + } +} +impl Deref for CM_PCM { + type Target = cm_pcm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CM_PCM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CM_PCM").finish() + } +} +#[doc = "Broadcom Clock Manager"] +pub mod cm_pcm; +#[doc = "Broadcom Clock Manager"] +pub struct CM_PWM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CM_PWM {} +impl CM_PWM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cm_pcm::RegisterBlock = 0xfe10_10a0 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cm_pcm::RegisterBlock { + Self::PTR + } +} +impl Deref for CM_PWM { + type Target = cm_pcm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CM_PWM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CM_PWM").finish() + } +} +#[doc = "Broadcom Clock Manager"] +pub use self::cm_pcm as cm_pwm; +#[doc = "Pin level and mux control"] +pub struct GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO {} +impl GPIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio::RegisterBlock = 0xfe20_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio::RegisterBlock { + Self::PTR + } +} +impl Deref for GPIO { + type Target = gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO").finish() + } +} +#[doc = "Pin level and mux control"] +pub mod gpio; +#[doc = "Broadcom System Timer"] +pub struct SYSTMR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTMR {} +impl SYSTMR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const systmr::RegisterBlock = 0xfe00_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const systmr::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTMR { + type Target = systmr::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTMR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTMR").finish() + } +} +#[doc = "Broadcom System Timer"] +pub mod systmr; +#[doc = "ARM Prime Cell PL011"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0xfe20_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub mod uart0; +#[doc = "ARM Prime Cell PL011"] +pub struct UART2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART2 {} +impl UART2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0xfe20_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART2 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART2").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub use self::uart0 as uart2; +#[doc = "ARM Prime Cell PL011"] +pub struct UART3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART3 {} +impl UART3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0xfe20_1600 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART3 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART3").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub use self::uart0 as uart3; +#[doc = "ARM Prime Cell PL011"] +pub struct UART4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART4 {} +impl UART4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0xfe20_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART4 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART4").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub use self::uart0 as uart4; +#[doc = "ARM Prime Cell PL011"] +pub struct UART5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART5 {} +impl UART5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0xfe20_1a00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART5 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART5").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub use self::uart0 as uart5; +#[doc = "Broadcom SPI Controller"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0xfe20_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub mod spi0; +#[doc = "Broadcom SPI Controller"] +pub struct SPI3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI3 {} +impl SPI3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0xfe20_4600 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI3 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI3").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub use self::spi0 as spi3; +#[doc = "Broadcom SPI Controller"] +pub struct SPI4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI4 {} +impl SPI4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0xfe20_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI4 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI4").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub use self::spi0 as spi4; +#[doc = "Broadcom SPI Controller"] +pub struct SPI5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI5 {} +impl SPI5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0xfe20_4a00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI5 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI5").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub use self::spi0 as spi5; +#[doc = "Broadcom SPI Controller"] +pub struct SPI6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI6 {} +impl SPI6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0xfe20_4c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI6 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI6").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub use self::spi0 as spi6; +#[doc = "Interrupt status of new peripherals"] +pub struct PACTL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PACTL {} +impl PACTL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pactl::RegisterBlock = 0xfe20_4e00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pactl::RegisterBlock { + Self::PTR + } +} +impl Deref for PACTL { + type Target = pactl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PACTL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PACTL").finish() + } +} +#[doc = "Interrupt status of new peripherals"] +pub mod pactl; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC0 {} +impl BSC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0xfe20_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC0 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC0").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub mod bsc0; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC1 {} +impl BSC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0xfe80_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC1 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC1").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc1; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC3 {} +impl BSC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0xfe20_5600 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC3 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC3").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc3; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC4 {} +impl BSC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0xfe20_5800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC4 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC4").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc4; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC5 {} +impl BSC5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0xfe20_5a00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC5 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC5").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc5; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC6 {} +impl BSC6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0xfe20_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC6 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC6").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc6; +#[doc = "Broadcom PWM"] +pub struct PWM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM0 {} +impl PWM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0::RegisterBlock = 0xfe20_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM0 { + type Target = pwm0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0").finish() + } +} +#[doc = "Broadcom PWM"] +pub mod pwm0; +#[doc = "Broadcom PWM"] +pub struct PWM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM1 {} +impl PWM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0::RegisterBlock = 0xfe20_c800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM1 { + type Target = pwm0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM1").finish() + } +} +#[doc = "Broadcom PWM"] +pub use self::pwm0 as pwm1; +#[doc = "Three auxiliary peripherals"] +pub struct AUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AUX {} +impl AUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const aux::RegisterBlock = 0xfe21_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aux::RegisterBlock { + Self::PTR + } +} +impl Deref for AUX { + type Target = aux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AUX").finish() + } +} +#[doc = "Three auxiliary peripherals"] +pub mod aux; +#[doc = "Mini UART"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart1::RegisterBlock = 0xfe21_5040 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + Self::PTR + } +} +impl Deref for UART1 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "Mini UART"] +pub mod uart1; +#[doc = "Aux SPI"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0xfe21_5080 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI1 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "Aux SPI"] +pub mod spi1; +#[doc = "Aux SPI"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0xfe21_50c0 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI2 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2").finish() + } +} +#[doc = "Aux SPI"] +pub use self::spi1 as spi2; +#[doc = "Broadcom Legacy Interrupt Controller"] +pub struct LIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LIC {} +impl LIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lic::RegisterBlock = 0xff80_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lic::RegisterBlock { + Self::PTR + } +} +impl Deref for LIC { + type Target = lic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LIC").finish() + } +} +#[doc = "Broadcom Legacy Interrupt Controller"] +pub mod lic; +#[doc = "ARM GIC-400 Generic Interrupt Controller Distributor"] +pub struct GIC_DIST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GIC_DIST {} +impl GIC_DIST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gic_dist::RegisterBlock = 0xff84_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gic_dist::RegisterBlock { + Self::PTR + } +} +impl Deref for GIC_DIST { + type Target = gic_dist::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GIC_DIST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GIC_DIST").finish() + } +} +#[doc = "ARM GIC-400 Generic Interrupt Controller Distributor"] +pub mod gic_dist; +#[doc = "ARM GIC-400 Generic Interrupt Controller CPU Interface"] +pub struct GIC_CPU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GIC_CPU {} +impl GIC_CPU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gic_cpu::RegisterBlock = 0xff84_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gic_cpu::RegisterBlock { + Self::PTR + } +} +impl Deref for GIC_CPU { + type Target = gic_cpu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GIC_CPU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GIC_CPU").finish() + } +} +#[doc = "ARM GIC-400 Generic Interrupt Controller CPU Interface"] +pub mod gic_cpu; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_GLOBAL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_GLOBAL {} +impl USB_OTG_GLOBAL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_global::RegisterBlock = 0xfe98_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_global::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_GLOBAL { + type Target = usb_otg_global::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_GLOBAL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_GLOBAL").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_global; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_HOST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_HOST {} +impl USB_OTG_HOST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_host::RegisterBlock = 0xfe98_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_host::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_HOST { + type Target = usb_otg_host::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_HOST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_HOST").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_host; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_DEVICE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_DEVICE {} +impl USB_OTG_DEVICE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_device::RegisterBlock = 0xfe98_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_device::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_DEVICE { + type Target = usb_otg_device::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_DEVICE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_DEVICE").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_device; +#[doc = "USB on the go high speed power control"] +pub struct USB_OTG_PWRCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_PWRCLK {} +impl USB_OTG_PWRCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_pwrclk::RegisterBlock = 0xfe98_0e00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_pwrclk::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_PWRCLK { + type Target = usb_otg_pwrclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_PWRCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_PWRCLK").finish() + } +} +#[doc = "USB on the go high speed power control"] +pub mod usb_otg_pwrclk; +#[doc = "Arasan SD3.0 Host AHB eMMC 4.4"] +pub struct EMMC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EMMC {} +impl EMMC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const emmc::RegisterBlock = 0xfe30_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const emmc::RegisterBlock { + Self::PTR + } +} +impl Deref for EMMC { + type Target = emmc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EMMC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EMMC").finish() + } +} +#[doc = "Arasan SD3.0 Host AHB eMMC 4.4"] +pub mod emmc; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "VCMAILBOX"] + pub VCMAILBOX: VCMAILBOX, + #[doc = "CM_PCM"] + pub CM_PCM: CM_PCM, + #[doc = "CM_PWM"] + pub CM_PWM: CM_PWM, + #[doc = "GPIO"] + pub GPIO: GPIO, + #[doc = "SYSTMR"] + pub SYSTMR: SYSTMR, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "UART2"] + pub UART2: UART2, + #[doc = "UART3"] + pub UART3: UART3, + #[doc = "UART4"] + pub UART4: UART4, + #[doc = "UART5"] + pub UART5: UART5, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI3"] + pub SPI3: SPI3, + #[doc = "SPI4"] + pub SPI4: SPI4, + #[doc = "SPI5"] + pub SPI5: SPI5, + #[doc = "SPI6"] + pub SPI6: SPI6, + #[doc = "PACTL"] + pub PACTL: PACTL, + #[doc = "BSC0"] + pub BSC0: BSC0, + #[doc = "BSC1"] + pub BSC1: BSC1, + #[doc = "BSC3"] + pub BSC3: BSC3, + #[doc = "BSC4"] + pub BSC4: BSC4, + #[doc = "BSC5"] + pub BSC5: BSC5, + #[doc = "BSC6"] + pub BSC6: BSC6, + #[doc = "PWM0"] + pub PWM0: PWM0, + #[doc = "PWM1"] + pub PWM1: PWM1, + #[doc = "AUX"] + pub AUX: AUX, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "LIC"] + pub LIC: LIC, + #[doc = "GIC_DIST"] + pub GIC_DIST: GIC_DIST, + #[doc = "GIC_CPU"] + pub GIC_CPU: GIC_CPU, + #[doc = "USB_OTG_GLOBAL"] + pub USB_OTG_GLOBAL: USB_OTG_GLOBAL, + #[doc = "USB_OTG_HOST"] + pub USB_OTG_HOST: USB_OTG_HOST, + #[doc = "USB_OTG_DEVICE"] + pub USB_OTG_DEVICE: USB_OTG_DEVICE, + #[doc = "USB_OTG_PWRCLK"] + pub USB_OTG_PWRCLK: USB_OTG_PWRCLK, + #[doc = "EMMC"] + pub EMMC: EMMC, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + VCMAILBOX: VCMAILBOX { + _marker: PhantomData, + }, + CM_PCM: CM_PCM { + _marker: PhantomData, + }, + CM_PWM: CM_PWM { + _marker: PhantomData, + }, + GPIO: GPIO { + _marker: PhantomData, + }, + SYSTMR: SYSTMR { + _marker: PhantomData, + }, + UART0: UART0 { + _marker: PhantomData, + }, + UART2: UART2 { + _marker: PhantomData, + }, + UART3: UART3 { + _marker: PhantomData, + }, + UART4: UART4 { + _marker: PhantomData, + }, + UART5: UART5 { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + SPI3: SPI3 { + _marker: PhantomData, + }, + SPI4: SPI4 { + _marker: PhantomData, + }, + SPI5: SPI5 { + _marker: PhantomData, + }, + SPI6: SPI6 { + _marker: PhantomData, + }, + PACTL: PACTL { + _marker: PhantomData, + }, + BSC0: BSC0 { + _marker: PhantomData, + }, + BSC1: BSC1 { + _marker: PhantomData, + }, + BSC3: BSC3 { + _marker: PhantomData, + }, + BSC4: BSC4 { + _marker: PhantomData, + }, + BSC5: BSC5 { + _marker: PhantomData, + }, + BSC6: BSC6 { + _marker: PhantomData, + }, + PWM0: PWM0 { + _marker: PhantomData, + }, + PWM1: PWM1 { + _marker: PhantomData, + }, + AUX: AUX { + _marker: PhantomData, + }, + UART1: UART1 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + LIC: LIC { + _marker: PhantomData, + }, + GIC_DIST: GIC_DIST { + _marker: PhantomData, + }, + GIC_CPU: GIC_CPU { + _marker: PhantomData, + }, + USB_OTG_GLOBAL: USB_OTG_GLOBAL { + _marker: PhantomData, + }, + USB_OTG_HOST: USB_OTG_HOST { + _marker: PhantomData, + }, + USB_OTG_DEVICE: USB_OTG_DEVICE { + _marker: PhantomData, + }, + USB_OTG_PWRCLK: USB_OTG_PWRCLK { + _marker: PhantomData, + }, + EMMC: EMMC { + _marker: PhantomData, + }, + } + } +} diff --git a/crates/bcm2711-lpa/src/lic.rs b/crates/bcm2711-lpa/src/lic.rs new file mode 100644 index 0000000..bc15cd4 --- /dev/null +++ b/crates/bcm2711-lpa/src/lic.rs @@ -0,0 +1,65 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0200], + #[doc = "0x200 - Basic pending info"] + pub basic_pending: BASIC_PENDING, + #[doc = "0x204 - Pending state for interrupts 1 - 31"] + pub pending_1: PENDING_1, + #[doc = "0x208 - Pending state for interrupts 32 - 63"] + pub pending_2: PENDING_2, + #[doc = "0x20c - FIQ control"] + pub fiq_control: FIQ_CONTROL, + #[doc = "0x210 - Enable interrupts 1 - 31"] + pub enable_1: ENABLE_1, + #[doc = "0x214 - Enable interrupts 32 - 63"] + pub enable_2: ENABLE_2, + #[doc = "0x218 - Enable basic interrupts"] + pub enable_basic: ENABLE_BASIC, + #[doc = "0x21c - Disable interrupts 1 - 31"] + pub disable_1: DISABLE_1, + #[doc = "0x220 - Disable interrupts 32 - 63"] + pub disable_2: DISABLE_2, + #[doc = "0x224 - Disable basic interrupts"] + pub disable_basic: DISABLE_BASIC, +} +#[doc = "BASIC_PENDING (r) register accessor: an alias for `Reg`"] +pub type BASIC_PENDING = crate::Reg; +#[doc = "Basic pending info"] +pub mod basic_pending; +#[doc = "PENDING_1 (r) register accessor: an alias for `Reg`"] +pub type PENDING_1 = crate::Reg; +#[doc = "Pending state for interrupts 1 - 31"] +pub mod pending_1; +#[doc = "PENDING_2 (r) register accessor: an alias for `Reg`"] +pub type PENDING_2 = crate::Reg; +#[doc = "Pending state for interrupts 32 - 63"] +pub mod pending_2; +#[doc = "FIQ_CONTROL (rw) register accessor: an alias for `Reg`"] +pub type FIQ_CONTROL = crate::Reg; +#[doc = "FIQ control"] +pub mod fiq_control; +#[doc = "ENABLE_1 (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_1 = crate::Reg; +#[doc = "Enable interrupts 1 - 31"] +pub mod enable_1; +#[doc = "ENABLE_2 (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_2 = crate::Reg; +#[doc = "Enable interrupts 32 - 63"] +pub mod enable_2; +#[doc = "ENABLE_BASIC (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_BASIC = crate::Reg; +#[doc = "Enable basic interrupts"] +pub mod enable_basic; +#[doc = "DISABLE_1 (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_1 = crate::Reg; +#[doc = "Disable interrupts 1 - 31"] +pub mod disable_1; +#[doc = "DISABLE_2 (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_2 = crate::Reg; +#[doc = "Disable interrupts 32 - 63"] +pub mod disable_2; +#[doc = "DISABLE_BASIC (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_BASIC = crate::Reg; +#[doc = "Disable basic interrupts"] +pub mod disable_basic; diff --git a/crates/bcm2711-lpa/src/lic/basic_pending.rs b/crates/bcm2711-lpa/src/lic/basic_pending.rs new file mode 100644 index 0000000..10dd271 --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/basic_pending.rs @@ -0,0 +1,177 @@ +#[doc = "Register `BASIC_PENDING` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `PENDING_1` reader - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] +pub type PENDING_1_R = crate::BitReader; +#[doc = "Field `PENDING_2` reader - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] +pub type PENDING_2_R = crate::BitReader; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] + #[inline(always)] + pub fn pending_1(&self) -> PENDING_1_R { + PENDING_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] + #[inline(always)] + pub fn pending_2(&self) -> PENDING_2_R { + PENDING_2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[doc = "Basic pending info\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [basic_pending](index.html) module"] +pub struct BASIC_PENDING_SPEC; +impl crate::RegisterSpec for BASIC_PENDING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [basic_pending::R](R) reader structure"] +impl crate::Readable for BASIC_PENDING_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASIC_PENDING to value 0"] +impl crate::Resettable for BASIC_PENDING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/disable_1.rs b/crates/bcm2711-lpa/src/lic/disable_1.rs new file mode 100644 index 0000000..e575ff9 --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/disable_1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `DISABLE_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_1](index.html) module"] +pub struct DISABLE_1_SPEC; +impl crate::RegisterSpec for DISABLE_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_1::R](R) reader structure"] +impl crate::Readable for DISABLE_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_1::W](W) writer structure"] +impl crate::Writable for DISABLE_1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets DISABLE_1 to value 0"] +impl crate::Resettable for DISABLE_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/disable_2.rs b/crates/bcm2711-lpa/src/lic/disable_2.rs new file mode 100644 index 0000000..72f4f7a --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/disable_2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `DISABLE_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_2](index.html) module"] +pub struct DISABLE_2_SPEC; +impl crate::RegisterSpec for DISABLE_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_2::R](R) reader structure"] +impl crate::Readable for DISABLE_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_2::W](W) writer structure"] +impl crate::Writable for DISABLE_2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets DISABLE_2 to value 0"] +impl crate::Resettable for DISABLE_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/disable_basic.rs b/crates/bcm2711-lpa/src/lic/disable_basic.rs new file mode 100644 index 0000000..df73f14 --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/disable_basic.rs @@ -0,0 +1,187 @@ +#[doc = "Register `DISABLE_BASIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_BASIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_basic](index.html) module"] +pub struct DISABLE_BASIC_SPEC; +impl crate::RegisterSpec for DISABLE_BASIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_basic::R](R) reader structure"] +impl crate::Readable for DISABLE_BASIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_basic::W](W) writer structure"] +impl crate::Writable for DISABLE_BASIC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; +} +#[doc = "`reset()` method sets DISABLE_BASIC to value 0"] +impl crate::Resettable for DISABLE_BASIC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/enable_1.rs b/crates/bcm2711-lpa/src/lic/enable_1.rs new file mode 100644 index 0000000..bb6550a --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/enable_1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `ENABLE_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT0` writer - Interrupt 0"] +pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT1` writer - Interrupt 1"] +pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT2` writer - Interrupt 2"] +pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT3` writer - Interrupt 3"] +pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT4` writer - Interrupt 4"] +pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT5` writer - Interrupt 5"] +pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT6` writer - Interrupt 6"] +pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT7` writer - Interrupt 7"] +pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT8` writer - Interrupt 8"] +pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT9` writer - Interrupt 9"] +pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT10` writer - Interrupt 10"] +pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT11` writer - Interrupt 11"] +pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT12` writer - Interrupt 12"] +pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT13` writer - Interrupt 13"] +pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT14` writer - Interrupt 14"] +pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT15` writer - Interrupt 15"] +pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT16` writer - Interrupt 16"] +pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT17` writer - Interrupt 17"] +pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT18` writer - Interrupt 18"] +pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT19` writer - Interrupt 19"] +pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT20` writer - Interrupt 20"] +pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT21` writer - Interrupt 21"] +pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT22` writer - Interrupt 22"] +pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT23` writer - Interrupt 23"] +pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT24` writer - Interrupt 24"] +pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT25` writer - Interrupt 25"] +pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT26` writer - Interrupt 26"] +pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT27` writer - Interrupt 27"] +pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT28` writer - Interrupt 28"] +pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT29` writer - Interrupt 29"] +pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT30` writer - Interrupt 30"] +pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +#[doc = "Field `INT31` writer - Interrupt 31"] +pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + #[must_use] + pub fn int0(&mut self) -> INT0_W<0> { + INT0_W::new(self) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + #[must_use] + pub fn int1(&mut self) -> INT1_W<1> { + INT1_W::new(self) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + #[must_use] + pub fn int2(&mut self) -> INT2_W<2> { + INT2_W::new(self) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + #[must_use] + pub fn int3(&mut self) -> INT3_W<3> { + INT3_W::new(self) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + #[must_use] + pub fn int4(&mut self) -> INT4_W<4> { + INT4_W::new(self) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + #[must_use] + pub fn int5(&mut self) -> INT5_W<5> { + INT5_W::new(self) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + #[must_use] + pub fn int6(&mut self) -> INT6_W<6> { + INT6_W::new(self) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + #[must_use] + pub fn int7(&mut self) -> INT7_W<7> { + INT7_W::new(self) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + #[must_use] + pub fn int8(&mut self) -> INT8_W<8> { + INT8_W::new(self) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + #[must_use] + pub fn int9(&mut self) -> INT9_W<9> { + INT9_W::new(self) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + #[must_use] + pub fn int10(&mut self) -> INT10_W<10> { + INT10_W::new(self) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + #[must_use] + pub fn int11(&mut self) -> INT11_W<11> { + INT11_W::new(self) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + #[must_use] + pub fn int12(&mut self) -> INT12_W<12> { + INT12_W::new(self) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + #[must_use] + pub fn int13(&mut self) -> INT13_W<13> { + INT13_W::new(self) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + #[must_use] + pub fn int14(&mut self) -> INT14_W<14> { + INT14_W::new(self) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + #[must_use] + pub fn int15(&mut self) -> INT15_W<15> { + INT15_W::new(self) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + #[must_use] + pub fn int16(&mut self) -> INT16_W<16> { + INT16_W::new(self) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + #[must_use] + pub fn int17(&mut self) -> INT17_W<17> { + INT17_W::new(self) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + #[must_use] + pub fn int18(&mut self) -> INT18_W<18> { + INT18_W::new(self) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + #[must_use] + pub fn int19(&mut self) -> INT19_W<19> { + INT19_W::new(self) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + #[must_use] + pub fn int20(&mut self) -> INT20_W<20> { + INT20_W::new(self) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + #[must_use] + pub fn int21(&mut self) -> INT21_W<21> { + INT21_W::new(self) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + #[must_use] + pub fn int22(&mut self) -> INT22_W<22> { + INT22_W::new(self) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + #[must_use] + pub fn int23(&mut self) -> INT23_W<23> { + INT23_W::new(self) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + #[must_use] + pub fn int24(&mut self) -> INT24_W<24> { + INT24_W::new(self) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + #[must_use] + pub fn int25(&mut self) -> INT25_W<25> { + INT25_W::new(self) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + #[must_use] + pub fn int26(&mut self) -> INT26_W<26> { + INT26_W::new(self) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + #[must_use] + pub fn int27(&mut self) -> INT27_W<27> { + INT27_W::new(self) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + #[must_use] + pub fn int28(&mut self) -> INT28_W<28> { + INT28_W::new(self) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + #[must_use] + pub fn int29(&mut self) -> INT29_W<29> { + INT29_W::new(self) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + #[must_use] + pub fn int30(&mut self) -> INT30_W<30> { + INT30_W::new(self) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + #[must_use] + pub fn int31(&mut self) -> INT31_W<31> { + INT31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_1](index.html) module"] +pub struct ENABLE_1_SPEC; +impl crate::RegisterSpec for ENABLE_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_1::R](R) reader structure"] +impl crate::Readable for ENABLE_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_1::W](W) writer structure"] +impl crate::Writable for ENABLE_1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets ENABLE_1 to value 0"] +impl crate::Resettable for ENABLE_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/enable_2.rs b/crates/bcm2711-lpa/src/lic/enable_2.rs new file mode 100644 index 0000000..1f0dd90 --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/enable_2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `ENABLE_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT32` writer - Interrupt 32"] +pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT33` writer - Interrupt 33"] +pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT34` writer - Interrupt 34"] +pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT35` writer - Interrupt 35"] +pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT36` writer - Interrupt 36"] +pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT37` writer - Interrupt 37"] +pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT38` writer - Interrupt 38"] +pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT39` writer - Interrupt 39"] +pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT40` writer - Interrupt 40"] +pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT41` writer - Interrupt 41"] +pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT42` writer - Interrupt 42"] +pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT43` writer - Interrupt 43"] +pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT44` writer - Interrupt 44"] +pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT45` writer - Interrupt 45"] +pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT46` writer - Interrupt 46"] +pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT47` writer - Interrupt 47"] +pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT48` writer - Interrupt 48"] +pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT49` writer - Interrupt 49"] +pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT50` writer - Interrupt 50"] +pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT51` writer - Interrupt 51"] +pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT52` writer - Interrupt 52"] +pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT53` writer - Interrupt 53"] +pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT54` writer - Interrupt 54"] +pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT55` writer - Interrupt 55"] +pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT56` writer - Interrupt 56"] +pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT57` writer - Interrupt 57"] +pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT58` writer - Interrupt 58"] +pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT59` writer - Interrupt 59"] +pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT60` writer - Interrupt 60"] +pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT61` writer - Interrupt 61"] +pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT62` writer - Interrupt 62"] +pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +#[doc = "Field `INT63` writer - Interrupt 63"] +pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + #[must_use] + pub fn int32(&mut self) -> INT32_W<0> { + INT32_W::new(self) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + #[must_use] + pub fn int33(&mut self) -> INT33_W<1> { + INT33_W::new(self) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + #[must_use] + pub fn int34(&mut self) -> INT34_W<2> { + INT34_W::new(self) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + #[must_use] + pub fn int35(&mut self) -> INT35_W<3> { + INT35_W::new(self) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + #[must_use] + pub fn int36(&mut self) -> INT36_W<4> { + INT36_W::new(self) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + #[must_use] + pub fn int37(&mut self) -> INT37_W<5> { + INT37_W::new(self) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + #[must_use] + pub fn int38(&mut self) -> INT38_W<6> { + INT38_W::new(self) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + #[must_use] + pub fn int39(&mut self) -> INT39_W<7> { + INT39_W::new(self) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + #[must_use] + pub fn int40(&mut self) -> INT40_W<8> { + INT40_W::new(self) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + #[must_use] + pub fn int41(&mut self) -> INT41_W<9> { + INT41_W::new(self) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + #[must_use] + pub fn int42(&mut self) -> INT42_W<10> { + INT42_W::new(self) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + #[must_use] + pub fn int43(&mut self) -> INT43_W<11> { + INT43_W::new(self) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + #[must_use] + pub fn int44(&mut self) -> INT44_W<12> { + INT44_W::new(self) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + #[must_use] + pub fn int45(&mut self) -> INT45_W<13> { + INT45_W::new(self) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + #[must_use] + pub fn int46(&mut self) -> INT46_W<14> { + INT46_W::new(self) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + #[must_use] + pub fn int47(&mut self) -> INT47_W<15> { + INT47_W::new(self) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + #[must_use] + pub fn int48(&mut self) -> INT48_W<16> { + INT48_W::new(self) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + #[must_use] + pub fn int49(&mut self) -> INT49_W<17> { + INT49_W::new(self) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + #[must_use] + pub fn int50(&mut self) -> INT50_W<18> { + INT50_W::new(self) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + #[must_use] + pub fn int51(&mut self) -> INT51_W<19> { + INT51_W::new(self) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + #[must_use] + pub fn int52(&mut self) -> INT52_W<20> { + INT52_W::new(self) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + #[must_use] + pub fn int53(&mut self) -> INT53_W<21> { + INT53_W::new(self) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + #[must_use] + pub fn int54(&mut self) -> INT54_W<22> { + INT54_W::new(self) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + #[must_use] + pub fn int55(&mut self) -> INT55_W<23> { + INT55_W::new(self) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + #[must_use] + pub fn int56(&mut self) -> INT56_W<24> { + INT56_W::new(self) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + #[must_use] + pub fn int57(&mut self) -> INT57_W<25> { + INT57_W::new(self) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + #[must_use] + pub fn int58(&mut self) -> INT58_W<26> { + INT58_W::new(self) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + #[must_use] + pub fn int59(&mut self) -> INT59_W<27> { + INT59_W::new(self) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + #[must_use] + pub fn int60(&mut self) -> INT60_W<28> { + INT60_W::new(self) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + #[must_use] + pub fn int61(&mut self) -> INT61_W<29> { + INT61_W::new(self) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + #[must_use] + pub fn int62(&mut self) -> INT62_W<30> { + INT62_W::new(self) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + #[must_use] + pub fn int63(&mut self) -> INT63_W<31> { + INT63_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_2](index.html) module"] +pub struct ENABLE_2_SPEC; +impl crate::RegisterSpec for ENABLE_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_2::R](R) reader structure"] +impl crate::Readable for ENABLE_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_2::W](W) writer structure"] +impl crate::Writable for ENABLE_2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets ENABLE_2 to value 0"] +impl crate::Resettable for ENABLE_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/enable_basic.rs b/crates/bcm2711-lpa/src/lic/enable_basic.rs new file mode 100644 index 0000000..b401deb --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/enable_basic.rs @@ -0,0 +1,186 @@ +#[doc = "Register `ENABLE_BASIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_BASIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_basic](index.html) module"] +pub struct ENABLE_BASIC_SPEC; +impl crate::RegisterSpec for ENABLE_BASIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_basic::R](R) reader structure"] +impl crate::Readable for ENABLE_BASIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_basic::W](W) writer structure"] +impl crate::Writable for ENABLE_BASIC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; +} +#[doc = "`reset()` method sets ENABLE_BASIC to value 0"] +impl crate::Resettable for ENABLE_BASIC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/fiq_control.rs b/crates/bcm2711-lpa/src/lic/fiq_control.rs new file mode 100644 index 0000000..a54e91f --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/fiq_control.rs @@ -0,0 +1,1054 @@ +#[doc = "Register `FIQ_CONTROL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIQ_CONTROL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SOURCE` reader - FIQ Source"] +pub type SOURCE_R = crate::FieldReader; +#[doc = "FIQ Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SOURCE_A { + #[doc = "0: Interrupt 0"] + INT0 = 0, + #[doc = "1: Interrupt 1"] + INT1 = 1, + #[doc = "2: Interrupt 2"] + INT2 = 2, + #[doc = "3: Interrupt 3"] + INT3 = 3, + #[doc = "4: Interrupt 4"] + INT4 = 4, + #[doc = "5: Interrupt 5"] + INT5 = 5, + #[doc = "6: Interrupt 6"] + INT6 = 6, + #[doc = "7: Interrupt 7"] + INT7 = 7, + #[doc = "8: Interrupt 8"] + INT8 = 8, + #[doc = "9: Interrupt 9"] + INT9 = 9, + #[doc = "10: Interrupt 10"] + INT10 = 10, + #[doc = "11: Interrupt 11"] + INT11 = 11, + #[doc = "12: Interrupt 12"] + INT12 = 12, + #[doc = "13: Interrupt 13"] + INT13 = 13, + #[doc = "14: Interrupt 14"] + INT14 = 14, + #[doc = "15: Interrupt 15"] + INT15 = 15, + #[doc = "16: Interrupt 16"] + INT16 = 16, + #[doc = "17: Interrupt 17"] + INT17 = 17, + #[doc = "18: Interrupt 18"] + INT18 = 18, + #[doc = "19: Interrupt 19"] + INT19 = 19, + #[doc = "20: Interrupt 20"] + INT20 = 20, + #[doc = "21: Interrupt 21"] + INT21 = 21, + #[doc = "22: Interrupt 22"] + INT22 = 22, + #[doc = "23: Interrupt 23"] + INT23 = 23, + #[doc = "24: Interrupt 24"] + INT24 = 24, + #[doc = "25: Interrupt 25"] + INT25 = 25, + #[doc = "26: Interrupt 26"] + INT26 = 26, + #[doc = "27: Interrupt 27"] + INT27 = 27, + #[doc = "28: Interrupt 28"] + INT28 = 28, + #[doc = "29: Interrupt 29"] + INT29 = 29, + #[doc = "30: Interrupt 30"] + INT30 = 30, + #[doc = "31: Interrupt 31"] + INT31 = 31, + #[doc = "32: Interrupt 32"] + INT32 = 32, + #[doc = "33: Interrupt 33"] + INT33 = 33, + #[doc = "34: Interrupt 34"] + INT34 = 34, + #[doc = "35: Interrupt 35"] + INT35 = 35, + #[doc = "36: Interrupt 36"] + INT36 = 36, + #[doc = "37: Interrupt 37"] + INT37 = 37, + #[doc = "38: Interrupt 38"] + INT38 = 38, + #[doc = "39: Interrupt 39"] + INT39 = 39, + #[doc = "40: Interrupt 40"] + INT40 = 40, + #[doc = "41: Interrupt 41"] + INT41 = 41, + #[doc = "42: Interrupt 42"] + INT42 = 42, + #[doc = "43: Interrupt 43"] + INT43 = 43, + #[doc = "44: Interrupt 44"] + INT44 = 44, + #[doc = "45: Interrupt 45"] + INT45 = 45, + #[doc = "46: Interrupt 46"] + INT46 = 46, + #[doc = "47: Interrupt 47"] + INT47 = 47, + #[doc = "48: Interrupt 48"] + INT48 = 48, + #[doc = "49: Interrupt 49"] + INT49 = 49, + #[doc = "50: Interrupt 50"] + INT50 = 50, + #[doc = "51: Interrupt 51"] + INT51 = 51, + #[doc = "52: Interrupt 52"] + INT52 = 52, + #[doc = "53: Interrupt 53"] + INT53 = 53, + #[doc = "54: Interrupt 54"] + INT54 = 54, + #[doc = "55: Interrupt 55"] + INT55 = 55, + #[doc = "56: Interrupt 56"] + INT56 = 56, + #[doc = "57: Interrupt 57"] + INT57 = 57, + #[doc = "58: Interrupt 58"] + INT58 = 58, + #[doc = "59: Interrupt 59"] + INT59 = 59, + #[doc = "60: Interrupt 60"] + INT60 = 60, + #[doc = "61: Interrupt 61"] + INT61 = 61, + #[doc = "62: Interrupt 62"] + INT62 = 62, + #[doc = "63: Interrupt 63"] + INT63 = 63, + #[doc = "64: ARMC Timer"] + TIMER = 64, + #[doc = "65: Mailbox"] + MAILBOX = 65, + #[doc = "66: Doorbell 0"] + DOORBELL0 = 66, + #[doc = "67: Doorbell 1"] + DOORBELL1 = 67, + #[doc = "68: VPU0 halted"] + VPU0_HALTED = 68, + #[doc = "69: VPU1 halted"] + VPU1_HALTED = 69, + #[doc = "70: ARM address error"] + ARM_ADDRESS_ERROR = 70, + #[doc = "71: ARM AXI error"] + ARM_AXI_ERROR = 71, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SOURCE_A) -> Self { + variant as _ + } +} +impl SOURCE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SOURCE_A::INT0), + 1 => Some(SOURCE_A::INT1), + 2 => Some(SOURCE_A::INT2), + 3 => Some(SOURCE_A::INT3), + 4 => Some(SOURCE_A::INT4), + 5 => Some(SOURCE_A::INT5), + 6 => Some(SOURCE_A::INT6), + 7 => Some(SOURCE_A::INT7), + 8 => Some(SOURCE_A::INT8), + 9 => Some(SOURCE_A::INT9), + 10 => Some(SOURCE_A::INT10), + 11 => Some(SOURCE_A::INT11), + 12 => Some(SOURCE_A::INT12), + 13 => Some(SOURCE_A::INT13), + 14 => Some(SOURCE_A::INT14), + 15 => Some(SOURCE_A::INT15), + 16 => Some(SOURCE_A::INT16), + 17 => Some(SOURCE_A::INT17), + 18 => Some(SOURCE_A::INT18), + 19 => Some(SOURCE_A::INT19), + 20 => Some(SOURCE_A::INT20), + 21 => Some(SOURCE_A::INT21), + 22 => Some(SOURCE_A::INT22), + 23 => Some(SOURCE_A::INT23), + 24 => Some(SOURCE_A::INT24), + 25 => Some(SOURCE_A::INT25), + 26 => Some(SOURCE_A::INT26), + 27 => Some(SOURCE_A::INT27), + 28 => Some(SOURCE_A::INT28), + 29 => Some(SOURCE_A::INT29), + 30 => Some(SOURCE_A::INT30), + 31 => Some(SOURCE_A::INT31), + 32 => Some(SOURCE_A::INT32), + 33 => Some(SOURCE_A::INT33), + 34 => Some(SOURCE_A::INT34), + 35 => Some(SOURCE_A::INT35), + 36 => Some(SOURCE_A::INT36), + 37 => Some(SOURCE_A::INT37), + 38 => Some(SOURCE_A::INT38), + 39 => Some(SOURCE_A::INT39), + 40 => Some(SOURCE_A::INT40), + 41 => Some(SOURCE_A::INT41), + 42 => Some(SOURCE_A::INT42), + 43 => Some(SOURCE_A::INT43), + 44 => Some(SOURCE_A::INT44), + 45 => Some(SOURCE_A::INT45), + 46 => Some(SOURCE_A::INT46), + 47 => Some(SOURCE_A::INT47), + 48 => Some(SOURCE_A::INT48), + 49 => Some(SOURCE_A::INT49), + 50 => Some(SOURCE_A::INT50), + 51 => Some(SOURCE_A::INT51), + 52 => Some(SOURCE_A::INT52), + 53 => Some(SOURCE_A::INT53), + 54 => Some(SOURCE_A::INT54), + 55 => Some(SOURCE_A::INT55), + 56 => Some(SOURCE_A::INT56), + 57 => Some(SOURCE_A::INT57), + 58 => Some(SOURCE_A::INT58), + 59 => Some(SOURCE_A::INT59), + 60 => Some(SOURCE_A::INT60), + 61 => Some(SOURCE_A::INT61), + 62 => Some(SOURCE_A::INT62), + 63 => Some(SOURCE_A::INT63), + 64 => Some(SOURCE_A::TIMER), + 65 => Some(SOURCE_A::MAILBOX), + 66 => Some(SOURCE_A::DOORBELL0), + 67 => Some(SOURCE_A::DOORBELL1), + 68 => Some(SOURCE_A::VPU0_HALTED), + 69 => Some(SOURCE_A::VPU1_HALTED), + 70 => Some(SOURCE_A::ARM_ADDRESS_ERROR), + 71 => Some(SOURCE_A::ARM_AXI_ERROR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT0`"] + #[inline(always)] + pub fn is_int0(&self) -> bool { + *self == SOURCE_A::INT0 + } + #[doc = "Checks if the value of the field is `INT1`"] + #[inline(always)] + pub fn is_int1(&self) -> bool { + *self == SOURCE_A::INT1 + } + #[doc = "Checks if the value of the field is `INT2`"] + #[inline(always)] + pub fn is_int2(&self) -> bool { + *self == SOURCE_A::INT2 + } + #[doc = "Checks if the value of the field is `INT3`"] + #[inline(always)] + pub fn is_int3(&self) -> bool { + *self == SOURCE_A::INT3 + } + #[doc = "Checks if the value of the field is `INT4`"] + #[inline(always)] + pub fn is_int4(&self) -> bool { + *self == SOURCE_A::INT4 + } + #[doc = "Checks if the value of the field is `INT5`"] + #[inline(always)] + pub fn is_int5(&self) -> bool { + *self == SOURCE_A::INT5 + } + #[doc = "Checks if the value of the field is `INT6`"] + #[inline(always)] + pub fn is_int6(&self) -> bool { + *self == SOURCE_A::INT6 + } + #[doc = "Checks if the value of the field is `INT7`"] + #[inline(always)] + pub fn is_int7(&self) -> bool { + *self == SOURCE_A::INT7 + } + #[doc = "Checks if the value of the field is `INT8`"] + #[inline(always)] + pub fn is_int8(&self) -> bool { + *self == SOURCE_A::INT8 + } + #[doc = "Checks if the value of the field is `INT9`"] + #[inline(always)] + pub fn is_int9(&self) -> bool { + *self == SOURCE_A::INT9 + } + #[doc = "Checks if the value of the field is `INT10`"] + #[inline(always)] + pub fn is_int10(&self) -> bool { + *self == SOURCE_A::INT10 + } + #[doc = "Checks if the value of the field is `INT11`"] + #[inline(always)] + pub fn is_int11(&self) -> bool { + *self == SOURCE_A::INT11 + } + #[doc = "Checks if the value of the field is `INT12`"] + #[inline(always)] + pub fn is_int12(&self) -> bool { + *self == SOURCE_A::INT12 + } + #[doc = "Checks if the value of the field is `INT13`"] + #[inline(always)] + pub fn is_int13(&self) -> bool { + *self == SOURCE_A::INT13 + } + #[doc = "Checks if the value of the field is `INT14`"] + #[inline(always)] + pub fn is_int14(&self) -> bool { + *self == SOURCE_A::INT14 + } + #[doc = "Checks if the value of the field is `INT15`"] + #[inline(always)] + pub fn is_int15(&self) -> bool { + *self == SOURCE_A::INT15 + } + #[doc = "Checks if the value of the field is `INT16`"] + #[inline(always)] + pub fn is_int16(&self) -> bool { + *self == SOURCE_A::INT16 + } + #[doc = "Checks if the value of the field is `INT17`"] + #[inline(always)] + pub fn is_int17(&self) -> bool { + *self == SOURCE_A::INT17 + } + #[doc = "Checks if the value of the field is `INT18`"] + #[inline(always)] + pub fn is_int18(&self) -> bool { + *self == SOURCE_A::INT18 + } + #[doc = "Checks if the value of the field is `INT19`"] + #[inline(always)] + pub fn is_int19(&self) -> bool { + *self == SOURCE_A::INT19 + } + #[doc = "Checks if the value of the field is `INT20`"] + #[inline(always)] + pub fn is_int20(&self) -> bool { + *self == SOURCE_A::INT20 + } + #[doc = "Checks if the value of the field is `INT21`"] + #[inline(always)] + pub fn is_int21(&self) -> bool { + *self == SOURCE_A::INT21 + } + #[doc = "Checks if the value of the field is `INT22`"] + #[inline(always)] + pub fn is_int22(&self) -> bool { + *self == SOURCE_A::INT22 + } + #[doc = "Checks if the value of the field is `INT23`"] + #[inline(always)] + pub fn is_int23(&self) -> bool { + *self == SOURCE_A::INT23 + } + #[doc = "Checks if the value of the field is `INT24`"] + #[inline(always)] + pub fn is_int24(&self) -> bool { + *self == SOURCE_A::INT24 + } + #[doc = "Checks if the value of the field is `INT25`"] + #[inline(always)] + pub fn is_int25(&self) -> bool { + *self == SOURCE_A::INT25 + } + #[doc = "Checks if the value of the field is `INT26`"] + #[inline(always)] + pub fn is_int26(&self) -> bool { + *self == SOURCE_A::INT26 + } + #[doc = "Checks if the value of the field is `INT27`"] + #[inline(always)] + pub fn is_int27(&self) -> bool { + *self == SOURCE_A::INT27 + } + #[doc = "Checks if the value of the field is `INT28`"] + #[inline(always)] + pub fn is_int28(&self) -> bool { + *self == SOURCE_A::INT28 + } + #[doc = "Checks if the value of the field is `INT29`"] + #[inline(always)] + pub fn is_int29(&self) -> bool { + *self == SOURCE_A::INT29 + } + #[doc = "Checks if the value of the field is `INT30`"] + #[inline(always)] + pub fn is_int30(&self) -> bool { + *self == SOURCE_A::INT30 + } + #[doc = "Checks if the value of the field is `INT31`"] + #[inline(always)] + pub fn is_int31(&self) -> bool { + *self == SOURCE_A::INT31 + } + #[doc = "Checks if the value of the field is `INT32`"] + #[inline(always)] + pub fn is_int32(&self) -> bool { + *self == SOURCE_A::INT32 + } + #[doc = "Checks if the value of the field is `INT33`"] + #[inline(always)] + pub fn is_int33(&self) -> bool { + *self == SOURCE_A::INT33 + } + #[doc = "Checks if the value of the field is `INT34`"] + #[inline(always)] + pub fn is_int34(&self) -> bool { + *self == SOURCE_A::INT34 + } + #[doc = "Checks if the value of the field is `INT35`"] + #[inline(always)] + pub fn is_int35(&self) -> bool { + *self == SOURCE_A::INT35 + } + #[doc = "Checks if the value of the field is `INT36`"] + #[inline(always)] + pub fn is_int36(&self) -> bool { + *self == SOURCE_A::INT36 + } + #[doc = "Checks if the value of the field is `INT37`"] + #[inline(always)] + pub fn is_int37(&self) -> bool { + *self == SOURCE_A::INT37 + } + #[doc = "Checks if the value of the field is `INT38`"] + #[inline(always)] + pub fn is_int38(&self) -> bool { + *self == SOURCE_A::INT38 + } + #[doc = "Checks if the value of the field is `INT39`"] + #[inline(always)] + pub fn is_int39(&self) -> bool { + *self == SOURCE_A::INT39 + } + #[doc = "Checks if the value of the field is `INT40`"] + #[inline(always)] + pub fn is_int40(&self) -> bool { + *self == SOURCE_A::INT40 + } + #[doc = "Checks if the value of the field is `INT41`"] + #[inline(always)] + pub fn is_int41(&self) -> bool { + *self == SOURCE_A::INT41 + } + #[doc = "Checks if the value of the field is `INT42`"] + #[inline(always)] + pub fn is_int42(&self) -> bool { + *self == SOURCE_A::INT42 + } + #[doc = "Checks if the value of the field is `INT43`"] + #[inline(always)] + pub fn is_int43(&self) -> bool { + *self == SOURCE_A::INT43 + } + #[doc = "Checks if the value of the field is `INT44`"] + #[inline(always)] + pub fn is_int44(&self) -> bool { + *self == SOURCE_A::INT44 + } + #[doc = "Checks if the value of the field is `INT45`"] + #[inline(always)] + pub fn is_int45(&self) -> bool { + *self == SOURCE_A::INT45 + } + #[doc = "Checks if the value of the field is `INT46`"] + #[inline(always)] + pub fn is_int46(&self) -> bool { + *self == SOURCE_A::INT46 + } + #[doc = "Checks if the value of the field is `INT47`"] + #[inline(always)] + pub fn is_int47(&self) -> bool { + *self == SOURCE_A::INT47 + } + #[doc = "Checks if the value of the field is `INT48`"] + #[inline(always)] + pub fn is_int48(&self) -> bool { + *self == SOURCE_A::INT48 + } + #[doc = "Checks if the value of the field is `INT49`"] + #[inline(always)] + pub fn is_int49(&self) -> bool { + *self == SOURCE_A::INT49 + } + #[doc = "Checks if the value of the field is `INT50`"] + #[inline(always)] + pub fn is_int50(&self) -> bool { + *self == SOURCE_A::INT50 + } + #[doc = "Checks if the value of the field is `INT51`"] + #[inline(always)] + pub fn is_int51(&self) -> bool { + *self == SOURCE_A::INT51 + } + #[doc = "Checks if the value of the field is `INT52`"] + #[inline(always)] + pub fn is_int52(&self) -> bool { + *self == SOURCE_A::INT52 + } + #[doc = "Checks if the value of the field is `INT53`"] + #[inline(always)] + pub fn is_int53(&self) -> bool { + *self == SOURCE_A::INT53 + } + #[doc = "Checks if the value of the field is `INT54`"] + #[inline(always)] + pub fn is_int54(&self) -> bool { + *self == SOURCE_A::INT54 + } + #[doc = "Checks if the value of the field is `INT55`"] + #[inline(always)] + pub fn is_int55(&self) -> bool { + *self == SOURCE_A::INT55 + } + #[doc = "Checks if the value of the field is `INT56`"] + #[inline(always)] + pub fn is_int56(&self) -> bool { + *self == SOURCE_A::INT56 + } + #[doc = "Checks if the value of the field is `INT57`"] + #[inline(always)] + pub fn is_int57(&self) -> bool { + *self == SOURCE_A::INT57 + } + #[doc = "Checks if the value of the field is `INT58`"] + #[inline(always)] + pub fn is_int58(&self) -> bool { + *self == SOURCE_A::INT58 + } + #[doc = "Checks if the value of the field is `INT59`"] + #[inline(always)] + pub fn is_int59(&self) -> bool { + *self == SOURCE_A::INT59 + } + #[doc = "Checks if the value of the field is `INT60`"] + #[inline(always)] + pub fn is_int60(&self) -> bool { + *self == SOURCE_A::INT60 + } + #[doc = "Checks if the value of the field is `INT61`"] + #[inline(always)] + pub fn is_int61(&self) -> bool { + *self == SOURCE_A::INT61 + } + #[doc = "Checks if the value of the field is `INT62`"] + #[inline(always)] + pub fn is_int62(&self) -> bool { + *self == SOURCE_A::INT62 + } + #[doc = "Checks if the value of the field is `INT63`"] + #[inline(always)] + pub fn is_int63(&self) -> bool { + *self == SOURCE_A::INT63 + } + #[doc = "Checks if the value of the field is `TIMER`"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == SOURCE_A::TIMER + } + #[doc = "Checks if the value of the field is `MAILBOX`"] + #[inline(always)] + pub fn is_mailbox(&self) -> bool { + *self == SOURCE_A::MAILBOX + } + #[doc = "Checks if the value of the field is `DOORBELL0`"] + #[inline(always)] + pub fn is_doorbell0(&self) -> bool { + *self == SOURCE_A::DOORBELL0 + } + #[doc = "Checks if the value of the field is `DOORBELL1`"] + #[inline(always)] + pub fn is_doorbell1(&self) -> bool { + *self == SOURCE_A::DOORBELL1 + } + #[doc = "Checks if the value of the field is `VPU0_HALTED`"] + #[inline(always)] + pub fn is_vpu0_halted(&self) -> bool { + *self == SOURCE_A::VPU0_HALTED + } + #[doc = "Checks if the value of the field is `VPU1_HALTED`"] + #[inline(always)] + pub fn is_vpu1_halted(&self) -> bool { + *self == SOURCE_A::VPU1_HALTED + } + #[doc = "Checks if the value of the field is `ARM_ADDRESS_ERROR`"] + #[inline(always)] + pub fn is_arm_address_error(&self) -> bool { + *self == SOURCE_A::ARM_ADDRESS_ERROR + } + #[doc = "Checks if the value of the field is `ARM_AXI_ERROR`"] + #[inline(always)] + pub fn is_arm_axi_error(&self) -> bool { + *self == SOURCE_A::ARM_AXI_ERROR + } +} +#[doc = "Field `SOURCE` writer - FIQ Source"] +pub type SOURCE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, FIQ_CONTROL_SPEC, u8, SOURCE_A, 7, O>; +impl<'a, const O: u8> SOURCE_W<'a, O> { + #[doc = "Interrupt 0"] + #[inline(always)] + pub fn int0(self) -> &'a mut W { + self.variant(SOURCE_A::INT0) + } + #[doc = "Interrupt 1"] + #[inline(always)] + pub fn int1(self) -> &'a mut W { + self.variant(SOURCE_A::INT1) + } + #[doc = "Interrupt 2"] + #[inline(always)] + pub fn int2(self) -> &'a mut W { + self.variant(SOURCE_A::INT2) + } + #[doc = "Interrupt 3"] + #[inline(always)] + pub fn int3(self) -> &'a mut W { + self.variant(SOURCE_A::INT3) + } + #[doc = "Interrupt 4"] + #[inline(always)] + pub fn int4(self) -> &'a mut W { + self.variant(SOURCE_A::INT4) + } + #[doc = "Interrupt 5"] + #[inline(always)] + pub fn int5(self) -> &'a mut W { + self.variant(SOURCE_A::INT5) + } + #[doc = "Interrupt 6"] + #[inline(always)] + pub fn int6(self) -> &'a mut W { + self.variant(SOURCE_A::INT6) + } + #[doc = "Interrupt 7"] + #[inline(always)] + pub fn int7(self) -> &'a mut W { + self.variant(SOURCE_A::INT7) + } + #[doc = "Interrupt 8"] + #[inline(always)] + pub fn int8(self) -> &'a mut W { + self.variant(SOURCE_A::INT8) + } + #[doc = "Interrupt 9"] + #[inline(always)] + pub fn int9(self) -> &'a mut W { + self.variant(SOURCE_A::INT9) + } + #[doc = "Interrupt 10"] + #[inline(always)] + pub fn int10(self) -> &'a mut W { + self.variant(SOURCE_A::INT10) + } + #[doc = "Interrupt 11"] + #[inline(always)] + pub fn int11(self) -> &'a mut W { + self.variant(SOURCE_A::INT11) + } + #[doc = "Interrupt 12"] + #[inline(always)] + pub fn int12(self) -> &'a mut W { + self.variant(SOURCE_A::INT12) + } + #[doc = "Interrupt 13"] + #[inline(always)] + pub fn int13(self) -> &'a mut W { + self.variant(SOURCE_A::INT13) + } + #[doc = "Interrupt 14"] + #[inline(always)] + pub fn int14(self) -> &'a mut W { + self.variant(SOURCE_A::INT14) + } + #[doc = "Interrupt 15"] + #[inline(always)] + pub fn int15(self) -> &'a mut W { + self.variant(SOURCE_A::INT15) + } + #[doc = "Interrupt 16"] + #[inline(always)] + pub fn int16(self) -> &'a mut W { + self.variant(SOURCE_A::INT16) + } + #[doc = "Interrupt 17"] + #[inline(always)] + pub fn int17(self) -> &'a mut W { + self.variant(SOURCE_A::INT17) + } + #[doc = "Interrupt 18"] + #[inline(always)] + pub fn int18(self) -> &'a mut W { + self.variant(SOURCE_A::INT18) + } + #[doc = "Interrupt 19"] + #[inline(always)] + pub fn int19(self) -> &'a mut W { + self.variant(SOURCE_A::INT19) + } + #[doc = "Interrupt 20"] + #[inline(always)] + pub fn int20(self) -> &'a mut W { + self.variant(SOURCE_A::INT20) + } + #[doc = "Interrupt 21"] + #[inline(always)] + pub fn int21(self) -> &'a mut W { + self.variant(SOURCE_A::INT21) + } + #[doc = "Interrupt 22"] + #[inline(always)] + pub fn int22(self) -> &'a mut W { + self.variant(SOURCE_A::INT22) + } + #[doc = "Interrupt 23"] + #[inline(always)] + pub fn int23(self) -> &'a mut W { + self.variant(SOURCE_A::INT23) + } + #[doc = "Interrupt 24"] + #[inline(always)] + pub fn int24(self) -> &'a mut W { + self.variant(SOURCE_A::INT24) + } + #[doc = "Interrupt 25"] + #[inline(always)] + pub fn int25(self) -> &'a mut W { + self.variant(SOURCE_A::INT25) + } + #[doc = "Interrupt 26"] + #[inline(always)] + pub fn int26(self) -> &'a mut W { + self.variant(SOURCE_A::INT26) + } + #[doc = "Interrupt 27"] + #[inline(always)] + pub fn int27(self) -> &'a mut W { + self.variant(SOURCE_A::INT27) + } + #[doc = "Interrupt 28"] + #[inline(always)] + pub fn int28(self) -> &'a mut W { + self.variant(SOURCE_A::INT28) + } + #[doc = "Interrupt 29"] + #[inline(always)] + pub fn int29(self) -> &'a mut W { + self.variant(SOURCE_A::INT29) + } + #[doc = "Interrupt 30"] + #[inline(always)] + pub fn int30(self) -> &'a mut W { + self.variant(SOURCE_A::INT30) + } + #[doc = "Interrupt 31"] + #[inline(always)] + pub fn int31(self) -> &'a mut W { + self.variant(SOURCE_A::INT31) + } + #[doc = "Interrupt 32"] + #[inline(always)] + pub fn int32(self) -> &'a mut W { + self.variant(SOURCE_A::INT32) + } + #[doc = "Interrupt 33"] + #[inline(always)] + pub fn int33(self) -> &'a mut W { + self.variant(SOURCE_A::INT33) + } + #[doc = "Interrupt 34"] + #[inline(always)] + pub fn int34(self) -> &'a mut W { + self.variant(SOURCE_A::INT34) + } + #[doc = "Interrupt 35"] + #[inline(always)] + pub fn int35(self) -> &'a mut W { + self.variant(SOURCE_A::INT35) + } + #[doc = "Interrupt 36"] + #[inline(always)] + pub fn int36(self) -> &'a mut W { + self.variant(SOURCE_A::INT36) + } + #[doc = "Interrupt 37"] + #[inline(always)] + pub fn int37(self) -> &'a mut W { + self.variant(SOURCE_A::INT37) + } + #[doc = "Interrupt 38"] + #[inline(always)] + pub fn int38(self) -> &'a mut W { + self.variant(SOURCE_A::INT38) + } + #[doc = "Interrupt 39"] + #[inline(always)] + pub fn int39(self) -> &'a mut W { + self.variant(SOURCE_A::INT39) + } + #[doc = "Interrupt 40"] + #[inline(always)] + pub fn int40(self) -> &'a mut W { + self.variant(SOURCE_A::INT40) + } + #[doc = "Interrupt 41"] + #[inline(always)] + pub fn int41(self) -> &'a mut W { + self.variant(SOURCE_A::INT41) + } + #[doc = "Interrupt 42"] + #[inline(always)] + pub fn int42(self) -> &'a mut W { + self.variant(SOURCE_A::INT42) + } + #[doc = "Interrupt 43"] + #[inline(always)] + pub fn int43(self) -> &'a mut W { + self.variant(SOURCE_A::INT43) + } + #[doc = "Interrupt 44"] + #[inline(always)] + pub fn int44(self) -> &'a mut W { + self.variant(SOURCE_A::INT44) + } + #[doc = "Interrupt 45"] + #[inline(always)] + pub fn int45(self) -> &'a mut W { + self.variant(SOURCE_A::INT45) + } + #[doc = "Interrupt 46"] + #[inline(always)] + pub fn int46(self) -> &'a mut W { + self.variant(SOURCE_A::INT46) + } + #[doc = "Interrupt 47"] + #[inline(always)] + pub fn int47(self) -> &'a mut W { + self.variant(SOURCE_A::INT47) + } + #[doc = "Interrupt 48"] + #[inline(always)] + pub fn int48(self) -> &'a mut W { + self.variant(SOURCE_A::INT48) + } + #[doc = "Interrupt 49"] + #[inline(always)] + pub fn int49(self) -> &'a mut W { + self.variant(SOURCE_A::INT49) + } + #[doc = "Interrupt 50"] + #[inline(always)] + pub fn int50(self) -> &'a mut W { + self.variant(SOURCE_A::INT50) + } + #[doc = "Interrupt 51"] + #[inline(always)] + pub fn int51(self) -> &'a mut W { + self.variant(SOURCE_A::INT51) + } + #[doc = "Interrupt 52"] + #[inline(always)] + pub fn int52(self) -> &'a mut W { + self.variant(SOURCE_A::INT52) + } + #[doc = "Interrupt 53"] + #[inline(always)] + pub fn int53(self) -> &'a mut W { + self.variant(SOURCE_A::INT53) + } + #[doc = "Interrupt 54"] + #[inline(always)] + pub fn int54(self) -> &'a mut W { + self.variant(SOURCE_A::INT54) + } + #[doc = "Interrupt 55"] + #[inline(always)] + pub fn int55(self) -> &'a mut W { + self.variant(SOURCE_A::INT55) + } + #[doc = "Interrupt 56"] + #[inline(always)] + pub fn int56(self) -> &'a mut W { + self.variant(SOURCE_A::INT56) + } + #[doc = "Interrupt 57"] + #[inline(always)] + pub fn int57(self) -> &'a mut W { + self.variant(SOURCE_A::INT57) + } + #[doc = "Interrupt 58"] + #[inline(always)] + pub fn int58(self) -> &'a mut W { + self.variant(SOURCE_A::INT58) + } + #[doc = "Interrupt 59"] + #[inline(always)] + pub fn int59(self) -> &'a mut W { + self.variant(SOURCE_A::INT59) + } + #[doc = "Interrupt 60"] + #[inline(always)] + pub fn int60(self) -> &'a mut W { + self.variant(SOURCE_A::INT60) + } + #[doc = "Interrupt 61"] + #[inline(always)] + pub fn int61(self) -> &'a mut W { + self.variant(SOURCE_A::INT61) + } + #[doc = "Interrupt 62"] + #[inline(always)] + pub fn int62(self) -> &'a mut W { + self.variant(SOURCE_A::INT62) + } + #[doc = "Interrupt 63"] + #[inline(always)] + pub fn int63(self) -> &'a mut W { + self.variant(SOURCE_A::INT63) + } + #[doc = "ARMC Timer"] + #[inline(always)] + pub fn timer(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER) + } + #[doc = "Mailbox"] + #[inline(always)] + pub fn mailbox(self) -> &'a mut W { + self.variant(SOURCE_A::MAILBOX) + } + #[doc = "Doorbell 0"] + #[inline(always)] + pub fn doorbell0(self) -> &'a mut W { + self.variant(SOURCE_A::DOORBELL0) + } + #[doc = "Doorbell 1"] + #[inline(always)] + pub fn doorbell1(self) -> &'a mut W { + self.variant(SOURCE_A::DOORBELL1) + } + #[doc = "VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(self) -> &'a mut W { + self.variant(SOURCE_A::VPU0_HALTED) + } + #[doc = "VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(self) -> &'a mut W { + self.variant(SOURCE_A::VPU1_HALTED) + } + #[doc = "ARM address error"] + #[inline(always)] + pub fn arm_address_error(self) -> &'a mut W { + self.variant(SOURCE_A::ARM_ADDRESS_ERROR) + } + #[doc = "ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(self) -> &'a mut W { + self.variant(SOURCE_A::ARM_AXI_ERROR) + } +} +#[doc = "Field `ENABLE` reader - FIQ Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - FIQ Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIQ_CONTROL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - FIQ Source"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - FIQ Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - FIQ Source"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W<0> { + SOURCE_W::new(self) + } + #[doc = "Bit 7 - FIQ Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<7> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIQ control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fiq_control](index.html) module"] +pub struct FIQ_CONTROL_SPEC; +impl crate::RegisterSpec for FIQ_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fiq_control::R](R) reader structure"] +impl crate::Readable for FIQ_CONTROL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fiq_control::W](W) writer structure"] +impl crate::Writable for FIQ_CONTROL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIQ_CONTROL to value 0"] +impl crate::Resettable for FIQ_CONTROL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/pending_1.rs b/crates/bcm2711-lpa/src/lic/pending_1.rs new file mode 100644 index 0000000..0dbe7c6 --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/pending_1.rs @@ -0,0 +1,254 @@ +#[doc = "Register `PENDING_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INT0` reader - Interrupt 0"] +pub type INT0_R = crate::BitReader; +#[doc = "Field `INT1` reader - Interrupt 1"] +pub type INT1_R = crate::BitReader; +#[doc = "Field `INT2` reader - Interrupt 2"] +pub type INT2_R = crate::BitReader; +#[doc = "Field `INT3` reader - Interrupt 3"] +pub type INT3_R = crate::BitReader; +#[doc = "Field `INT4` reader - Interrupt 4"] +pub type INT4_R = crate::BitReader; +#[doc = "Field `INT5` reader - Interrupt 5"] +pub type INT5_R = crate::BitReader; +#[doc = "Field `INT6` reader - Interrupt 6"] +pub type INT6_R = crate::BitReader; +#[doc = "Field `INT7` reader - Interrupt 7"] +pub type INT7_R = crate::BitReader; +#[doc = "Field `INT8` reader - Interrupt 8"] +pub type INT8_R = crate::BitReader; +#[doc = "Field `INT9` reader - Interrupt 9"] +pub type INT9_R = crate::BitReader; +#[doc = "Field `INT10` reader - Interrupt 10"] +pub type INT10_R = crate::BitReader; +#[doc = "Field `INT11` reader - Interrupt 11"] +pub type INT11_R = crate::BitReader; +#[doc = "Field `INT12` reader - Interrupt 12"] +pub type INT12_R = crate::BitReader; +#[doc = "Field `INT13` reader - Interrupt 13"] +pub type INT13_R = crate::BitReader; +#[doc = "Field `INT14` reader - Interrupt 14"] +pub type INT14_R = crate::BitReader; +#[doc = "Field `INT15` reader - Interrupt 15"] +pub type INT15_R = crate::BitReader; +#[doc = "Field `INT16` reader - Interrupt 16"] +pub type INT16_R = crate::BitReader; +#[doc = "Field `INT17` reader - Interrupt 17"] +pub type INT17_R = crate::BitReader; +#[doc = "Field `INT18` reader - Interrupt 18"] +pub type INT18_R = crate::BitReader; +#[doc = "Field `INT19` reader - Interrupt 19"] +pub type INT19_R = crate::BitReader; +#[doc = "Field `INT20` reader - Interrupt 20"] +pub type INT20_R = crate::BitReader; +#[doc = "Field `INT21` reader - Interrupt 21"] +pub type INT21_R = crate::BitReader; +#[doc = "Field `INT22` reader - Interrupt 22"] +pub type INT22_R = crate::BitReader; +#[doc = "Field `INT23` reader - Interrupt 23"] +pub type INT23_R = crate::BitReader; +#[doc = "Field `INT24` reader - Interrupt 24"] +pub type INT24_R = crate::BitReader; +#[doc = "Field `INT25` reader - Interrupt 25"] +pub type INT25_R = crate::BitReader; +#[doc = "Field `INT26` reader - Interrupt 26"] +pub type INT26_R = crate::BitReader; +#[doc = "Field `INT27` reader - Interrupt 27"] +pub type INT27_R = crate::BitReader; +#[doc = "Field `INT28` reader - Interrupt 28"] +pub type INT28_R = crate::BitReader; +#[doc = "Field `INT29` reader - Interrupt 29"] +pub type INT29_R = crate::BitReader; +#[doc = "Field `INT30` reader - Interrupt 30"] +pub type INT30_R = crate::BitReader; +#[doc = "Field `INT31` reader - Interrupt 31"] +pub type INT31_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Interrupt 0"] + #[inline(always)] + pub fn int0(&self) -> INT0_R { + INT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 1"] + #[inline(always)] + pub fn int1(&self) -> INT1_R { + INT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 2"] + #[inline(always)] + pub fn int2(&self) -> INT2_R { + INT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 3"] + #[inline(always)] + pub fn int3(&self) -> INT3_R { + INT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 4"] + #[inline(always)] + pub fn int4(&self) -> INT4_R { + INT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 5"] + #[inline(always)] + pub fn int5(&self) -> INT5_R { + INT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 6"] + #[inline(always)] + pub fn int6(&self) -> INT6_R { + INT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 7"] + #[inline(always)] + pub fn int7(&self) -> INT7_R { + INT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 8"] + #[inline(always)] + pub fn int8(&self) -> INT8_R { + INT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 9"] + #[inline(always)] + pub fn int9(&self) -> INT9_R { + INT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 10"] + #[inline(always)] + pub fn int10(&self) -> INT10_R { + INT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 11"] + #[inline(always)] + pub fn int11(&self) -> INT11_R { + INT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 12"] + #[inline(always)] + pub fn int12(&self) -> INT12_R { + INT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 13"] + #[inline(always)] + pub fn int13(&self) -> INT13_R { + INT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 14"] + #[inline(always)] + pub fn int14(&self) -> INT14_R { + INT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 15"] + #[inline(always)] + pub fn int15(&self) -> INT15_R { + INT15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 16"] + #[inline(always)] + pub fn int16(&self) -> INT16_R { + INT16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 17"] + #[inline(always)] + pub fn int17(&self) -> INT17_R { + INT17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 18"] + #[inline(always)] + pub fn int18(&self) -> INT18_R { + INT18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 19"] + #[inline(always)] + pub fn int19(&self) -> INT19_R { + INT19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 20"] + #[inline(always)] + pub fn int20(&self) -> INT20_R { + INT20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 21"] + #[inline(always)] + pub fn int21(&self) -> INT21_R { + INT21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 22"] + #[inline(always)] + pub fn int22(&self) -> INT22_R { + INT22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 23"] + #[inline(always)] + pub fn int23(&self) -> INT23_R { + INT23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 24"] + #[inline(always)] + pub fn int24(&self) -> INT24_R { + INT24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 25"] + #[inline(always)] + pub fn int25(&self) -> INT25_R { + INT25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 26"] + #[inline(always)] + pub fn int26(&self) -> INT26_R { + INT26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 27"] + #[inline(always)] + pub fn int27(&self) -> INT27_R { + INT27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 28"] + #[inline(always)] + pub fn int28(&self) -> INT28_R { + INT28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 29"] + #[inline(always)] + pub fn int29(&self) -> INT29_R { + INT29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 30"] + #[inline(always)] + pub fn int30(&self) -> INT30_R { + INT30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 31"] + #[inline(always)] + pub fn int31(&self) -> INT31_R { + INT31_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Pending state for interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_1](index.html) module"] +pub struct PENDING_1_SPEC; +impl crate::RegisterSpec for PENDING_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pending_1::R](R) reader structure"] +impl crate::Readable for PENDING_1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDING_1 to value 0"] +impl crate::Resettable for PENDING_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/lic/pending_2.rs b/crates/bcm2711-lpa/src/lic/pending_2.rs new file mode 100644 index 0000000..6d8066c --- /dev/null +++ b/crates/bcm2711-lpa/src/lic/pending_2.rs @@ -0,0 +1,254 @@ +#[doc = "Register `PENDING_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INT32` reader - Interrupt 32"] +pub type INT32_R = crate::BitReader; +#[doc = "Field `INT33` reader - Interrupt 33"] +pub type INT33_R = crate::BitReader; +#[doc = "Field `INT34` reader - Interrupt 34"] +pub type INT34_R = crate::BitReader; +#[doc = "Field `INT35` reader - Interrupt 35"] +pub type INT35_R = crate::BitReader; +#[doc = "Field `INT36` reader - Interrupt 36"] +pub type INT36_R = crate::BitReader; +#[doc = "Field `INT37` reader - Interrupt 37"] +pub type INT37_R = crate::BitReader; +#[doc = "Field `INT38` reader - Interrupt 38"] +pub type INT38_R = crate::BitReader; +#[doc = "Field `INT39` reader - Interrupt 39"] +pub type INT39_R = crate::BitReader; +#[doc = "Field `INT40` reader - Interrupt 40"] +pub type INT40_R = crate::BitReader; +#[doc = "Field `INT41` reader - Interrupt 41"] +pub type INT41_R = crate::BitReader; +#[doc = "Field `INT42` reader - Interrupt 42"] +pub type INT42_R = crate::BitReader; +#[doc = "Field `INT43` reader - Interrupt 43"] +pub type INT43_R = crate::BitReader; +#[doc = "Field `INT44` reader - Interrupt 44"] +pub type INT44_R = crate::BitReader; +#[doc = "Field `INT45` reader - Interrupt 45"] +pub type INT45_R = crate::BitReader; +#[doc = "Field `INT46` reader - Interrupt 46"] +pub type INT46_R = crate::BitReader; +#[doc = "Field `INT47` reader - Interrupt 47"] +pub type INT47_R = crate::BitReader; +#[doc = "Field `INT48` reader - Interrupt 48"] +pub type INT48_R = crate::BitReader; +#[doc = "Field `INT49` reader - Interrupt 49"] +pub type INT49_R = crate::BitReader; +#[doc = "Field `INT50` reader - Interrupt 50"] +pub type INT50_R = crate::BitReader; +#[doc = "Field `INT51` reader - Interrupt 51"] +pub type INT51_R = crate::BitReader; +#[doc = "Field `INT52` reader - Interrupt 52"] +pub type INT52_R = crate::BitReader; +#[doc = "Field `INT53` reader - Interrupt 53"] +pub type INT53_R = crate::BitReader; +#[doc = "Field `INT54` reader - Interrupt 54"] +pub type INT54_R = crate::BitReader; +#[doc = "Field `INT55` reader - Interrupt 55"] +pub type INT55_R = crate::BitReader; +#[doc = "Field `INT56` reader - Interrupt 56"] +pub type INT56_R = crate::BitReader; +#[doc = "Field `INT57` reader - Interrupt 57"] +pub type INT57_R = crate::BitReader; +#[doc = "Field `INT58` reader - Interrupt 58"] +pub type INT58_R = crate::BitReader; +#[doc = "Field `INT59` reader - Interrupt 59"] +pub type INT59_R = crate::BitReader; +#[doc = "Field `INT60` reader - Interrupt 60"] +pub type INT60_R = crate::BitReader; +#[doc = "Field `INT61` reader - Interrupt 61"] +pub type INT61_R = crate::BitReader; +#[doc = "Field `INT62` reader - Interrupt 62"] +pub type INT62_R = crate::BitReader; +#[doc = "Field `INT63` reader - Interrupt 63"] +pub type INT63_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Interrupt 32"] + #[inline(always)] + pub fn int32(&self) -> INT32_R { + INT32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt 33"] + #[inline(always)] + pub fn int33(&self) -> INT33_R { + INT33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt 34"] + #[inline(always)] + pub fn int34(&self) -> INT34_R { + INT34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt 35"] + #[inline(always)] + pub fn int35(&self) -> INT35_R { + INT35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt 36"] + #[inline(always)] + pub fn int36(&self) -> INT36_R { + INT36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt 37"] + #[inline(always)] + pub fn int37(&self) -> INT37_R { + INT37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt 38"] + #[inline(always)] + pub fn int38(&self) -> INT38_R { + INT38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Interrupt 39"] + #[inline(always)] + pub fn int39(&self) -> INT39_R { + INT39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt 40"] + #[inline(always)] + pub fn int40(&self) -> INT40_R { + INT40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt 41"] + #[inline(always)] + pub fn int41(&self) -> INT41_R { + INT41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt 42"] + #[inline(always)] + pub fn int42(&self) -> INT42_R { + INT42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt 43"] + #[inline(always)] + pub fn int43(&self) -> INT43_R { + INT43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt 44"] + #[inline(always)] + pub fn int44(&self) -> INT44_R { + INT44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt 45"] + #[inline(always)] + pub fn int45(&self) -> INT45_R { + INT45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt 46"] + #[inline(always)] + pub fn int46(&self) -> INT46_R { + INT46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Interrupt 47"] + #[inline(always)] + pub fn int47(&self) -> INT47_R { + INT47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Interrupt 48"] + #[inline(always)] + pub fn int48(&self) -> INT48_R { + INT48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Interrupt 49"] + #[inline(always)] + pub fn int49(&self) -> INT49_R { + INT49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Interrupt 50"] + #[inline(always)] + pub fn int50(&self) -> INT50_R { + INT50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Interrupt 51"] + #[inline(always)] + pub fn int51(&self) -> INT51_R { + INT51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt 52"] + #[inline(always)] + pub fn int52(&self) -> INT52_R { + INT52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt 53"] + #[inline(always)] + pub fn int53(&self) -> INT53_R { + INT53_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Interrupt 54"] + #[inline(always)] + pub fn int54(&self) -> INT54_R { + INT54_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Interrupt 55"] + #[inline(always)] + pub fn int55(&self) -> INT55_R { + INT55_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt 56"] + #[inline(always)] + pub fn int56(&self) -> INT56_R { + INT56_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Interrupt 57"] + #[inline(always)] + pub fn int57(&self) -> INT57_R { + INT57_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt 58"] + #[inline(always)] + pub fn int58(&self) -> INT58_R { + INT58_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Interrupt 59"] + #[inline(always)] + pub fn int59(&self) -> INT59_R { + INT59_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Interrupt 60"] + #[inline(always)] + pub fn int60(&self) -> INT60_R { + INT60_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Interrupt 61"] + #[inline(always)] + pub fn int61(&self) -> INT61_R { + INT61_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Interrupt 62"] + #[inline(always)] + pub fn int62(&self) -> INT62_R { + INT62_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Interrupt 63"] + #[inline(always)] + pub fn int63(&self) -> INT63_R { + INT63_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Pending state for interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_2](index.html) module"] +pub struct PENDING_2_SPEC; +impl crate::RegisterSpec for PENDING_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pending_2::R](R) reader structure"] +impl crate::Readable for PENDING_2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDING_2 to value 0"] +impl crate::Resettable for PENDING_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pactl.rs b/crates/bcm2711-lpa/src/pactl.rs new file mode 100644 index 0000000..0c6b249 --- /dev/null +++ b/crates/bcm2711-lpa/src/pactl.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt status"] + pub cs: CS, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Interrupt status"] +pub mod cs; diff --git a/crates/bcm2711-lpa/src/pactl/cs.rs b/crates/bcm2711-lpa/src/pactl/cs.rs new file mode 100644 index 0000000..f574fd9 --- /dev/null +++ b/crates/bcm2711-lpa/src/pactl/cs.rs @@ -0,0 +1,365 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPI_0` reader - SPI0 interrupt active"] +pub type SPI_0_R = crate::BitReader; +#[doc = "Field `SPI_0` writer - SPI0 interrupt active"] +pub type SPI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 interrupt active"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 interrupt active"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 interrupt active"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 interrupt active"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `SPI_3` reader - SPI3 interrupt active"] +pub type SPI_3_R = crate::BitReader; +#[doc = "Field `SPI_3` writer - SPI3 interrupt active"] +pub type SPI_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `SPI_4` reader - SPI4 interrupt active"] +pub type SPI_4_R = crate::BitReader; +#[doc = "Field `SPI_4` writer - SPI4 interrupt active"] +pub type SPI_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `SPI_5` reader - SPI5 interrupt active"] +pub type SPI_5_R = crate::BitReader; +#[doc = "Field `SPI_5` writer - SPI5 interrupt active"] +pub type SPI_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `SPI_6` reader - SPI6 interrupt active"] +pub type SPI_6_R = crate::BitReader; +#[doc = "Field `SPI_6` writer - SPI6 interrupt active"] +pub type SPI_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_0` reader - I2C0 interrupt active"] +pub type I2C_0_R = crate::BitReader; +#[doc = "Field `I2C_0` writer - I2C0 interrupt active"] +pub type I2C_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_1` reader - I2C1 interrupt active"] +pub type I2C_1_R = crate::BitReader; +#[doc = "Field `I2C_1` writer - I2C1 interrupt active"] +pub type I2C_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_2` reader - I2C2 interrupt active"] +pub type I2C_2_R = crate::BitReader; +#[doc = "Field `I2C_2` writer - I2C2 interrupt active"] +pub type I2C_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_3` reader - I2C3 interrupt active"] +pub type I2C_3_R = crate::BitReader; +#[doc = "Field `I2C_3` writer - I2C3 interrupt active"] +pub type I2C_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_4` reader - I2C4 interrupt active"] +pub type I2C_4_R = crate::BitReader; +#[doc = "Field `I2C_4` writer - I2C4 interrupt active"] +pub type I2C_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_5` reader - I2C5 interrupt active"] +pub type I2C_5_R = crate::BitReader; +#[doc = "Field `I2C_5` writer - I2C5 interrupt active"] +pub type I2C_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_6` reader - I2C6 interrupt active"] +pub type I2C_6_R = crate::BitReader; +#[doc = "Field `I2C_6` writer - I2C6 interrupt active"] +pub type I2C_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `I2C_7` reader - I2C7 interrupt active"] +pub type I2C_7_R = crate::BitReader; +#[doc = "Field `I2C_7` writer - I2C7 interrupt active"] +pub type I2C_7_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `UART_5` reader - UART5 interrupt active"] +pub type UART_5_R = crate::BitReader; +#[doc = "Field `UART_5` writer - UART5 interrupt active"] +pub type UART_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `UART_4` reader - UART4 interrupt active"] +pub type UART_4_R = crate::BitReader; +#[doc = "Field `UART_4` writer - UART4 interrupt active"] +pub type UART_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `UART_3` reader - UART3 interrupt active"] +pub type UART_3_R = crate::BitReader; +#[doc = "Field `UART_3` writer - UART3 interrupt active"] +pub type UART_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `UART_2` reader - UART2 interrupt active"] +pub type UART_2_R = crate::BitReader; +#[doc = "Field `UART_2` writer - UART2 interrupt active"] +pub type UART_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `UART_0` reader - UART0 interrupt active"] +pub type UART_0_R = crate::BitReader; +#[doc = "Field `UART_0` writer - UART0 interrupt active"] +pub type UART_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - SPI0 interrupt active"] + #[inline(always)] + pub fn spi_0(&self) -> SPI_0_R { + SPI_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SPI3 interrupt active"] + #[inline(always)] + pub fn spi_3(&self) -> SPI_3_R { + SPI_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SPI4 interrupt active"] + #[inline(always)] + pub fn spi_4(&self) -> SPI_4_R { + SPI_4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - SPI5 interrupt active"] + #[inline(always)] + pub fn spi_5(&self) -> SPI_5_R { + SPI_5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - SPI6 interrupt active"] + #[inline(always)] + pub fn spi_6(&self) -> SPI_6_R { + SPI_6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - I2C0 interrupt active"] + #[inline(always)] + pub fn i2c_0(&self) -> I2C_0_R { + I2C_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - I2C1 interrupt active"] + #[inline(always)] + pub fn i2c_1(&self) -> I2C_1_R { + I2C_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - I2C2 interrupt active"] + #[inline(always)] + pub fn i2c_2(&self) -> I2C_2_R { + I2C_2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - I2C3 interrupt active"] + #[inline(always)] + pub fn i2c_3(&self) -> I2C_3_R { + I2C_3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - I2C4 interrupt active"] + #[inline(always)] + pub fn i2c_4(&self) -> I2C_4_R { + I2C_4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - I2C5 interrupt active"] + #[inline(always)] + pub fn i2c_5(&self) -> I2C_5_R { + I2C_5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - I2C6 interrupt active"] + #[inline(always)] + pub fn i2c_6(&self) -> I2C_6_R { + I2C_6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - I2C7 interrupt active"] + #[inline(always)] + pub fn i2c_7(&self) -> I2C_7_R { + I2C_7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - UART5 interrupt active"] + #[inline(always)] + pub fn uart_5(&self) -> UART_5_R { + UART_5_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - UART4 interrupt active"] + #[inline(always)] + pub fn uart_4(&self) -> UART_4_R { + UART_4_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - UART3 interrupt active"] + #[inline(always)] + pub fn uart_3(&self) -> UART_3_R { + UART_3_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - UART2 interrupt active"] + #[inline(always)] + pub fn uart_2(&self) -> UART_2_R { + UART_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - UART0 interrupt active"] + #[inline(always)] + pub fn uart_0(&self) -> UART_0_R { + UART_0_R::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SPI0 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_0(&mut self) -> SPI_0_W<0> { + SPI_0_W::new(self) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Bit 3 - SPI3 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_3(&mut self) -> SPI_3_W<3> { + SPI_3_W::new(self) + } + #[doc = "Bit 4 - SPI4 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_4(&mut self) -> SPI_4_W<4> { + SPI_4_W::new(self) + } + #[doc = "Bit 5 - SPI5 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_5(&mut self) -> SPI_5_W<5> { + SPI_5_W::new(self) + } + #[doc = "Bit 6 - SPI6 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_6(&mut self) -> SPI_6_W<6> { + SPI_6_W::new(self) + } + #[doc = "Bit 8 - I2C0 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_0(&mut self) -> I2C_0_W<8> { + I2C_0_W::new(self) + } + #[doc = "Bit 9 - I2C1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_1(&mut self) -> I2C_1_W<9> { + I2C_1_W::new(self) + } + #[doc = "Bit 10 - I2C2 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_2(&mut self) -> I2C_2_W<10> { + I2C_2_W::new(self) + } + #[doc = "Bit 11 - I2C3 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_3(&mut self) -> I2C_3_W<11> { + I2C_3_W::new(self) + } + #[doc = "Bit 12 - I2C4 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_4(&mut self) -> I2C_4_W<12> { + I2C_4_W::new(self) + } + #[doc = "Bit 13 - I2C5 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_5(&mut self) -> I2C_5_W<13> { + I2C_5_W::new(self) + } + #[doc = "Bit 14 - I2C6 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_6(&mut self) -> I2C_6_W<14> { + I2C_6_W::new(self) + } + #[doc = "Bit 15 - I2C7 interrupt active"] + #[inline(always)] + #[must_use] + pub fn i2c_7(&mut self) -> I2C_7_W<15> { + I2C_7_W::new(self) + } + #[doc = "Bit 16 - UART5 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_5(&mut self) -> UART_5_W<16> { + UART_5_W::new(self) + } + #[doc = "Bit 17 - UART4 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_4(&mut self) -> UART_4_W<17> { + UART_4_W::new(self) + } + #[doc = "Bit 18 - UART3 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_3(&mut self) -> UART_3_W<18> { + UART_3_W::new(self) + } + #[doc = "Bit 19 - UART2 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_2(&mut self) -> UART_2_W<19> { + UART_2_W::new(self) + } + #[doc = "Bit 20 - UART0 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_0(&mut self) -> UART_0_W<20> { + UART_0_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pwm0.rs b/crates/bcm2711-lpa/src/pwm0.rs new file mode 100644 index 0000000..4270433 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctl: CTL, + #[doc = "0x04 - Status"] + pub sta: STA, + #[doc = "0x08 - DMA control"] + pub dmac: DMAC, + _reserved3: [u8; 0x04], + #[doc = "0x10 - Range for channel 1"] + pub rng1: RNG1, + #[doc = "0x14 - Channel 1 data"] + pub dat1: DAT1, + #[doc = "0x18 - FIFO input"] + pub fif1: FIF1, + _reserved6: [u8; 0x04], + #[doc = "0x20 - Range for channel 2"] + pub rng2: RNG2, + #[doc = "0x24 - Channel 2 data"] + pub dat2: DAT2, +} +#[doc = "CTL (rw) register accessor: an alias for `Reg`"] +pub type CTL = crate::Reg; +#[doc = "Control"] +pub mod ctl; +#[doc = "STA (rw) register accessor: an alias for `Reg`"] +pub type STA = crate::Reg; +#[doc = "Status"] +pub mod sta; +#[doc = "DMAC (rw) register accessor: an alias for `Reg`"] +pub type DMAC = crate::Reg; +#[doc = "DMA control"] +pub mod dmac; +#[doc = "RNG1 (rw) register accessor: an alias for `Reg`"] +pub type RNG1 = crate::Reg; +#[doc = "Range for channel 1"] +pub mod rng1; +#[doc = "DAT1 (rw) register accessor: an alias for `Reg`"] +pub type DAT1 = crate::Reg; +#[doc = "Channel 1 data"] +pub mod dat1; +#[doc = "FIF1 (w) register accessor: an alias for `Reg`"] +pub type FIF1 = crate::Reg; +#[doc = "FIFO input"] +pub mod fif1; +#[doc = "RNG2 (rw) register accessor: an alias for `Reg`"] +pub type RNG2 = crate::Reg; +#[doc = "Range for channel 2"] +pub mod rng2; +#[doc = "DAT2 (rw) register accessor: an alias for `Reg`"] +pub type DAT2 = crate::Reg; +#[doc = "Channel 2 data"] +pub mod dat2; diff --git a/crates/bcm2711-lpa/src/pwm0/ctl.rs b/crates/bcm2711-lpa/src/pwm0/ctl.rs new file mode 100644 index 0000000..b41b326 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/ctl.rs @@ -0,0 +1,382 @@ +#[doc = "Register `CTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWEN1` reader - Enable channel 1"] +pub type PWEN1_R = crate::BitReader; +#[doc = "Field `PWEN1` writer - Enable channel 1"] +pub type PWEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MODE1` reader - Channel 1 mode"] +pub type MODE1_R = crate::BitReader; +#[doc = "Channel 1 mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE1_A { + #[doc = "0: `0`"] + PWM = 0, + #[doc = "1: `1`"] + SERIAL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE1_A) -> Self { + variant as u8 != 0 + } +} +impl MODE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE1_A { + match self.bits { + false => MODE1_A::PWM, + true => MODE1_A::SERIAL, + } + } + #[doc = "Checks if the value of the field is `PWM`"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == MODE1_A::PWM + } + #[doc = "Checks if the value of the field is `SERIAL`"] + #[inline(always)] + pub fn is_serial(&self) -> bool { + *self == MODE1_A::SERIAL + } +} +#[doc = "Field `MODE1` writer - Channel 1 mode"] +pub type MODE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE1_A, O>; +impl<'a, const O: u8> MODE1_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn pwm(self) -> &'a mut W { + self.variant(MODE1_A::PWM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn serial(self) -> &'a mut W { + self.variant(MODE1_A::SERIAL) + } +} +#[doc = "Field `RPTL1` reader - Repeat last value from FIFO for channel 1"] +pub type RPTL1_R = crate::BitReader; +#[doc = "Field `RPTL1` writer - Repeat last value from FIFO for channel 1"] +pub type RPTL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `SBIT1` reader - State when not transmitting on channel 1"] +pub type SBIT1_R = crate::BitReader; +#[doc = "Field `SBIT1` writer - State when not transmitting on channel 1"] +pub type SBIT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `POLA1` reader - Channel 1 polarity inverted"] +pub type POLA1_R = crate::BitReader; +#[doc = "Field `POLA1` writer - Channel 1 polarity inverted"] +pub type POLA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `USEF1` reader - Use FIFO for channel 1"] +pub type USEF1_R = crate::BitReader; +#[doc = "Field `USEF1` writer - Use FIFO for channel 1"] +pub type USEF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `CLRF1` reader - Clear FIFO"] +pub type CLRF1_R = crate::BitReader; +#[doc = "Field `CLRF1` writer - Clear FIFO"] +pub type CLRF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MSEN1` reader - M/S mode for channel 1"] +pub type MSEN1_R = crate::BitReader; +#[doc = "Field `MSEN1` writer - M/S mode for channel 1"] +pub type MSEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `PWEN2` reader - Enable channel 2"] +pub type PWEN2_R = crate::BitReader; +#[doc = "Field `PWEN2` writer - Enable channel 2"] +pub type PWEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MODE2` reader - Channel 2 mode"] +pub type MODE2_R = crate::BitReader; +#[doc = "Channel 2 mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE2_A { + #[doc = "0: `0`"] + PWM = 0, + #[doc = "1: `1`"] + SERIAL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE2_A) -> Self { + variant as u8 != 0 + } +} +impl MODE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE2_A { + match self.bits { + false => MODE2_A::PWM, + true => MODE2_A::SERIAL, + } + } + #[doc = "Checks if the value of the field is `PWM`"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == MODE2_A::PWM + } + #[doc = "Checks if the value of the field is `SERIAL`"] + #[inline(always)] + pub fn is_serial(&self) -> bool { + *self == MODE2_A::SERIAL + } +} +#[doc = "Field `MODE2` writer - Channel 2 mode"] +pub type MODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE2_A, O>; +impl<'a, const O: u8> MODE2_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn pwm(self) -> &'a mut W { + self.variant(MODE2_A::PWM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn serial(self) -> &'a mut W { + self.variant(MODE2_A::SERIAL) + } +} +#[doc = "Field `RPTL2` reader - Repeat last value from FIFO for channel 2"] +pub type RPTL2_R = crate::BitReader; +#[doc = "Field `RPTL2` writer - Repeat last value from FIFO for channel 2"] +pub type RPTL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `SBIT2` reader - State when not transmitting on channel 2"] +pub type SBIT2_R = crate::BitReader; +#[doc = "Field `SBIT2` writer - State when not transmitting on channel 2"] +pub type SBIT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `POLA2` reader - Channel 2 polarity inverted"] +pub type POLA2_R = crate::BitReader; +#[doc = "Field `POLA2` writer - Channel 2 polarity inverted"] +pub type POLA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `USEF2` reader - Use FIFO for channel 2"] +pub type USEF2_R = crate::BitReader; +#[doc = "Field `USEF2` writer - Use FIFO for channel 2"] +pub type USEF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MSEN2` reader - M/S mode for channel 2"] +pub type MSEN2_R = crate::BitReader; +#[doc = "Field `MSEN2` writer - M/S mode for channel 2"] +pub type MSEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn pwen1(&self) -> PWEN1_R { + PWEN1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 mode"] + #[inline(always)] + pub fn mode1(&self) -> MODE1_R { + MODE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] + #[inline(always)] + pub fn rptl1(&self) -> RPTL1_R { + RPTL1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - State when not transmitting on channel 1"] + #[inline(always)] + pub fn sbit1(&self) -> SBIT1_R { + SBIT1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 1 polarity inverted"] + #[inline(always)] + pub fn pola1(&self) -> POLA1_R { + POLA1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Use FIFO for channel 1"] + #[inline(always)] + pub fn usef1(&self) -> USEF1_R { + USEF1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Clear FIFO"] + #[inline(always)] + pub fn clrf1(&self) -> CLRF1_R { + CLRF1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - M/S mode for channel 1"] + #[inline(always)] + pub fn msen1(&self) -> MSEN1_R { + MSEN1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable channel 2"] + #[inline(always)] + pub fn pwen2(&self) -> PWEN2_R { + PWEN2_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 2 mode"] + #[inline(always)] + pub fn mode2(&self) -> MODE2_R { + MODE2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] + #[inline(always)] + pub fn rptl2(&self) -> RPTL2_R { + RPTL2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - State when not transmitting on channel 2"] + #[inline(always)] + pub fn sbit2(&self) -> SBIT2_R { + SBIT2_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 2 polarity inverted"] + #[inline(always)] + pub fn pola2(&self) -> POLA2_R { + POLA2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Use FIFO for channel 2"] + #[inline(always)] + pub fn usef2(&self) -> USEF2_R { + USEF2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - M/S mode for channel 2"] + #[inline(always)] + pub fn msen2(&self) -> MSEN2_R { + MSEN2_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + #[must_use] + pub fn pwen1(&mut self) -> PWEN1_W<0> { + PWEN1_W::new(self) + } + #[doc = "Bit 1 - Channel 1 mode"] + #[inline(always)] + #[must_use] + pub fn mode1(&mut self) -> MODE1_W<1> { + MODE1_W::new(self) + } + #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] + #[inline(always)] + #[must_use] + pub fn rptl1(&mut self) -> RPTL1_W<2> { + RPTL1_W::new(self) + } + #[doc = "Bit 3 - State when not transmitting on channel 1"] + #[inline(always)] + #[must_use] + pub fn sbit1(&mut self) -> SBIT1_W<3> { + SBIT1_W::new(self) + } + #[doc = "Bit 4 - Channel 1 polarity inverted"] + #[inline(always)] + #[must_use] + pub fn pola1(&mut self) -> POLA1_W<4> { + POLA1_W::new(self) + } + #[doc = "Bit 5 - Use FIFO for channel 1"] + #[inline(always)] + #[must_use] + pub fn usef1(&mut self) -> USEF1_W<5> { + USEF1_W::new(self) + } + #[doc = "Bit 6 - Clear FIFO"] + #[inline(always)] + #[must_use] + pub fn clrf1(&mut self) -> CLRF1_W<6> { + CLRF1_W::new(self) + } + #[doc = "Bit 7 - M/S mode for channel 1"] + #[inline(always)] + #[must_use] + pub fn msen1(&mut self) -> MSEN1_W<7> { + MSEN1_W::new(self) + } + #[doc = "Bit 8 - Enable channel 2"] + #[inline(always)] + #[must_use] + pub fn pwen2(&mut self) -> PWEN2_W<8> { + PWEN2_W::new(self) + } + #[doc = "Bit 9 - Channel 2 mode"] + #[inline(always)] + #[must_use] + pub fn mode2(&mut self) -> MODE2_W<9> { + MODE2_W::new(self) + } + #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] + #[inline(always)] + #[must_use] + pub fn rptl2(&mut self) -> RPTL2_W<10> { + RPTL2_W::new(self) + } + #[doc = "Bit 11 - State when not transmitting on channel 2"] + #[inline(always)] + #[must_use] + pub fn sbit2(&mut self) -> SBIT2_W<11> { + SBIT2_W::new(self) + } + #[doc = "Bit 12 - Channel 2 polarity inverted"] + #[inline(always)] + #[must_use] + pub fn pola2(&mut self) -> POLA2_W<12> { + POLA2_W::new(self) + } + #[doc = "Bit 13 - Use FIFO for channel 2"] + #[inline(always)] + #[must_use] + pub fn usef2(&mut self) -> USEF2_W<13> { + USEF2_W::new(self) + } + #[doc = "Bit 15 - M/S mode for channel 2"] + #[inline(always)] + #[must_use] + pub fn msen2(&mut self) -> MSEN2_W<15> { + MSEN2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"] +pub struct CTL_SPEC; +impl crate::RegisterSpec for CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctl::R](R) reader structure"] +impl crate::Readable for CTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"] +impl crate::Writable for CTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTL to value 0"] +impl crate::Resettable for CTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pwm0/dat1.rs b/crates/bcm2711-lpa/src/pwm0/dat1.rs new file mode 100644 index 0000000..c197492 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/dat1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel 1 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat1](index.html) module"] +pub struct DAT1_SPEC; +impl crate::RegisterSpec for DAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dat1::R](R) reader structure"] +impl crate::Readable for DAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dat1::W](W) writer structure"] +impl crate::Writable for DAT1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAT1 to value 0"] +impl crate::Resettable for DAT1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pwm0/dat2.rs b/crates/bcm2711-lpa/src/pwm0/dat2.rs new file mode 100644 index 0000000..b9e07a3 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/dat2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel 2 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat2](index.html) module"] +pub struct DAT2_SPEC; +impl crate::RegisterSpec for DAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dat2::R](R) reader structure"] +impl crate::Readable for DAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dat2::W](W) writer structure"] +impl crate::Writable for DAT2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAT2 to value 0"] +impl crate::Resettable for DAT2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pwm0/dmac.rs b/crates/bcm2711-lpa/src/pwm0/dmac.rs new file mode 100644 index 0000000..b201822 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/dmac.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DMAC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMAC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DREQ` reader - DMA threshold for DREQ signal"] +pub type DREQ_R = crate::FieldReader; +#[doc = "Field `DREQ` writer - DMA threshold for DREQ signal"] +pub type DREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +#[doc = "Field `PANIC` reader - DMA threshold for panic signal"] +pub type PANIC_R = crate::FieldReader; +#[doc = "Field `PANIC` writer - DMA threshold for panic signal"] +pub type PANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +#[doc = "Field `ENAB` reader - DMA enabled"] +pub type ENAB_R = crate::BitReader; +#[doc = "Field `ENAB` writer - DMA enabled"] +pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] + #[inline(always)] + pub fn dreq(&self) -> DREQ_R { + DREQ_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA threshold for panic signal"] + #[inline(always)] + pub fn panic(&self) -> PANIC_R { + PANIC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 31 - DMA enabled"] + #[inline(always)] + pub fn enab(&self) -> ENAB_R { + ENAB_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] + #[inline(always)] + #[must_use] + pub fn dreq(&mut self) -> DREQ_W<0> { + DREQ_W::new(self) + } + #[doc = "Bits 8:15 - DMA threshold for panic signal"] + #[inline(always)] + #[must_use] + pub fn panic(&mut self) -> PANIC_W<8> { + PANIC_W::new(self) + } + #[doc = "Bit 31 - DMA enabled"] + #[inline(always)] + #[must_use] + pub fn enab(&mut self) -> ENAB_W<31> { + ENAB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac](index.html) module"] +pub struct DMAC_SPEC; +impl crate::RegisterSpec for DMAC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmac::R](R) reader structure"] +impl crate::Readable for DMAC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmac::W](W) writer structure"] +impl crate::Writable for DMAC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMAC to value 0"] +impl crate::Resettable for DMAC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pwm0/fif1.rs b/crates/bcm2711-lpa/src/pwm0/fif1.rs new file mode 100644 index 0000000..e786328 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/fif1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FIF1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO input\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fif1](index.html) module"] +pub struct FIF1_SPEC; +impl crate::RegisterSpec for FIF1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fif1::W](W) writer structure"] +impl crate::Writable for FIF1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIF1 to value 0"] +impl crate::Resettable for FIF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/pwm0/rng1.rs b/crates/bcm2711-lpa/src/pwm0/rng1.rs new file mode 100644 index 0000000..b6f5446 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/rng1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RNG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RNG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Range for channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng1](index.html) module"] +pub struct RNG1_SPEC; +impl crate::RegisterSpec for RNG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rng1::R](R) reader structure"] +impl crate::Readable for RNG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rng1::W](W) writer structure"] +impl crate::Writable for RNG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG1 to value 0x20"] +impl crate::Resettable for RNG1_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/crates/bcm2711-lpa/src/pwm0/rng2.rs b/crates/bcm2711-lpa/src/pwm0/rng2.rs new file mode 100644 index 0000000..0cc95d5 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/rng2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RNG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RNG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Range for channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng2](index.html) module"] +pub struct RNG2_SPEC; +impl crate::RegisterSpec for RNG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rng2::R](R) reader structure"] +impl crate::Readable for RNG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rng2::W](W) writer structure"] +impl crate::Writable for RNG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG2 to value 0x20"] +impl crate::Resettable for RNG2_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/crates/bcm2711-lpa/src/pwm0/sta.rs b/crates/bcm2711-lpa/src/pwm0/sta.rs new file mode 100644 index 0000000..f0b99b7 --- /dev/null +++ b/crates/bcm2711-lpa/src/pwm0/sta.rs @@ -0,0 +1,260 @@ +#[doc = "Register `STA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FULL1` reader - FIFO full"] +pub type FULL1_R = crate::BitReader; +#[doc = "Field `FULL1` writer - FIFO full"] +pub type FULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `EMPT1` reader - FIFO empty"] +pub type EMPT1_R = crate::BitReader; +#[doc = "Field `EMPT1` writer - FIFO empty"] +pub type EMPT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `WERR1` reader - FIFO write error"] +pub type WERR1_R = crate::BitReader; +#[doc = "Field `WERR1` writer - FIFO write error"] +pub type WERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `RERR1` reader - FIFO read error"] +pub type RERR1_R = crate::BitReader; +#[doc = "Field `RERR1` writer - FIFO read error"] +pub type RERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO1` reader - Channel 1 gap occurred"] +pub type GAPO1_R = crate::BitReader; +#[doc = "Field `GAPO1` writer - Channel 1 gap occurred"] +pub type GAPO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO2` reader - Channel 2 gap occurred"] +pub type GAPO2_R = crate::BitReader; +#[doc = "Field `GAPO2` writer - Channel 2 gap occurred"] +pub type GAPO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO3` reader - Channel 3 gap occurred"] +pub type GAPO3_R = crate::BitReader; +#[doc = "Field `GAPO3` writer - Channel 3 gap occurred"] +pub type GAPO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO4` reader - Channel 4 gap occurred"] +pub type GAPO4_R = crate::BitReader; +#[doc = "Field `GAPO4` writer - Channel 4 gap occurred"] +pub type GAPO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Bus error"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Bus error"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA1` reader - Channel 1 state"] +pub type STA1_R = crate::BitReader; +#[doc = "Field `STA1` writer - Channel 1 state"] +pub type STA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA2` reader - Channel 2 state"] +pub type STA2_R = crate::BitReader; +#[doc = "Field `STA2` writer - Channel 2 state"] +pub type STA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA3` reader - Channel 3 state"] +pub type STA3_R = crate::BitReader; +#[doc = "Field `STA3` writer - Channel 3 state"] +pub type STA3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA4` reader - Channel 4 state"] +pub type STA4_R = crate::BitReader; +#[doc = "Field `STA4` writer - Channel 4 state"] +pub type STA4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - FIFO full"] + #[inline(always)] + pub fn full1(&self) -> FULL1_R { + FULL1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO empty"] + #[inline(always)] + pub fn empt1(&self) -> EMPT1_R { + EMPT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO write error"] + #[inline(always)] + pub fn werr1(&self) -> WERR1_R { + WERR1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO read error"] + #[inline(always)] + pub fn rerr1(&self) -> RERR1_R { + RERR1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 1 gap occurred"] + #[inline(always)] + pub fn gapo1(&self) -> GAPO1_R { + GAPO1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 2 gap occurred"] + #[inline(always)] + pub fn gapo2(&self) -> GAPO2_R { + GAPO2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 3 gap occurred"] + #[inline(always)] + pub fn gapo3(&self) -> GAPO3_R { + GAPO3_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 4 gap occurred"] + #[inline(always)] + pub fn gapo4(&self) -> GAPO4_R { + GAPO4_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Bus error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 1 state"] + #[inline(always)] + pub fn sta1(&self) -> STA1_R { + STA1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 2 state"] + #[inline(always)] + pub fn sta2(&self) -> STA2_R { + STA2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 3 state"] + #[inline(always)] + pub fn sta3(&self) -> STA3_R { + STA3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 4 state"] + #[inline(always)] + pub fn sta4(&self) -> STA4_R { + STA4_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FIFO full"] + #[inline(always)] + #[must_use] + pub fn full1(&mut self) -> FULL1_W<0> { + FULL1_W::new(self) + } + #[doc = "Bit 1 - FIFO empty"] + #[inline(always)] + #[must_use] + pub fn empt1(&mut self) -> EMPT1_W<1> { + EMPT1_W::new(self) + } + #[doc = "Bit 2 - FIFO write error"] + #[inline(always)] + #[must_use] + pub fn werr1(&mut self) -> WERR1_W<2> { + WERR1_W::new(self) + } + #[doc = "Bit 3 - FIFO read error"] + #[inline(always)] + #[must_use] + pub fn rerr1(&mut self) -> RERR1_W<3> { + RERR1_W::new(self) + } + #[doc = "Bit 4 - Channel 1 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo1(&mut self) -> GAPO1_W<4> { + GAPO1_W::new(self) + } + #[doc = "Bit 5 - Channel 2 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo2(&mut self) -> GAPO2_W<5> { + GAPO2_W::new(self) + } + #[doc = "Bit 6 - Channel 3 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo3(&mut self) -> GAPO3_W<6> { + GAPO3_W::new(self) + } + #[doc = "Bit 7 - Channel 4 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo4(&mut self) -> GAPO4_W<7> { + GAPO4_W::new(self) + } + #[doc = "Bit 8 - Bus error"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<8> { + BERR_W::new(self) + } + #[doc = "Bit 9 - Channel 1 state"] + #[inline(always)] + #[must_use] + pub fn sta1(&mut self) -> STA1_W<9> { + STA1_W::new(self) + } + #[doc = "Bit 10 - Channel 2 state"] + #[inline(always)] + #[must_use] + pub fn sta2(&mut self) -> STA2_W<10> { + STA2_W::new(self) + } + #[doc = "Bit 11 - Channel 3 state"] + #[inline(always)] + #[must_use] + pub fn sta3(&mut self) -> STA3_W<11> { + STA3_W::new(self) + } + #[doc = "Bit 12 - Channel 4 state"] + #[inline(always)] + #[must_use] + pub fn sta4(&mut self) -> STA4_W<12> { + STA4_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"] +pub struct STA_SPEC; +impl crate::RegisterSpec for STA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sta::R](R) reader structure"] +impl crate::Readable for STA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sta::W](W) writer structure"] +impl crate::Writable for STA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STA to value 0"] +impl crate::Resettable for STA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi0.rs b/crates/bcm2711-lpa/src/spi0.rs new file mode 100644 index 0000000..88737df --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control and Status"] + pub cs: CS, + #[doc = "0x04 - FIFO access"] + pub fifo: FIFO, + #[doc = "0x08 - Clock divider"] + pub clk: CLK, + #[doc = "0x0c - Data length"] + pub dlen: DLEN, + #[doc = "0x10 - LoSSI output hold delay"] + pub ltoh: LTOH, + #[doc = "0x14 - "] + pub dc: DC, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control and Status"] +pub mod cs; +#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +pub type FIFO = crate::Reg; +#[doc = "FIFO access"] +pub mod fifo; +#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +pub type CLK = crate::Reg; +#[doc = "Clock divider"] +pub mod clk; +#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +pub type DLEN = crate::Reg; +#[doc = "Data length"] +pub mod dlen; +#[doc = "LTOH (rw) register accessor: an alias for `Reg`"] +pub type LTOH = crate::Reg; +#[doc = "LoSSI output hold delay"] +pub mod ltoh; +#[doc = "DC (rw) register accessor: an alias for `Reg`"] +pub type DC = crate::Reg; +#[doc = ""] +pub mod dc; diff --git a/crates/bcm2711-lpa/src/spi0/clk.rs b/crates/bcm2711-lpa/src/spi0/clk.rs new file mode 100644 index 0000000..ef3272e --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0/clk.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CLK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CDIV` reader - Clock divider"] +pub type CDIV_R = crate::FieldReader; +#[doc = "Field `CDIV` writer - Clock divider"] +pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Clock divider"] + #[inline(always)] + pub fn cdiv(&self) -> CDIV_R { + CDIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Clock divider"] + #[inline(always)] + #[must_use] + pub fn cdiv(&mut self) -> CDIV_W<0> { + CDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clk::R](R) reader structure"] +impl crate::Readable for CLK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +impl crate::Writable for CLK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi0/cs.rs b/crates/bcm2711-lpa/src/spi0/cs.rs new file mode 100644 index 0000000..50227aa --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0/cs.rs @@ -0,0 +1,446 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CS` reader - Chip select"] +pub type CS_R = crate::FieldReader; +#[doc = "Field `CS` writer - Chip select"] +pub type CS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +#[doc = "Field `CPHA` reader - Clock phase"] +pub type CPHA_R = crate::BitReader; +#[doc = "Field `CPHA` writer - Clock phase"] +pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CPOL` reader - Clock polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Field `CPOL` writer - Clock polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CLEAR` reader - Clear the FIFO(s)"] +pub type CLEAR_R = crate::FieldReader; +#[doc = "Clear the FIFO(s)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CLEAR_A { + #[doc = "1: `1`"] + TX = 1, + #[doc = "2: `10`"] + RX = 2, + #[doc = "3: `11`"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_A) -> Self { + variant as _ + } +} +impl CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CLEAR_A::TX), + 2 => Some(CLEAR_A::RX), + 3 => Some(CLEAR_A::BOTH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + *self == CLEAR_A::TX + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + *self == CLEAR_A::RX + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == CLEAR_A::BOTH + } +} +#[doc = "Field `CLEAR` writer - Clear the FIFO(s)"] +pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, CLEAR_A, 2, O>; +impl<'a, const O: u8> CLEAR_W<'a, O> { + #[doc = "`1`"] + #[inline(always)] + pub fn tx(self) -> &'a mut W { + self.variant(CLEAR_A::TX) + } + #[doc = "`10`"] + #[inline(always)] + pub fn rx(self) -> &'a mut W { + self.variant(CLEAR_A::RX) + } + #[doc = "`11`"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(CLEAR_A::BOTH) + } +} +#[doc = "Field `CSPOL` reader - Chip select polarity"] +pub type CSPOL_R = crate::BitReader; +#[doc = "Field `CSPOL` writer - Chip select polarity"] +pub type CSPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `TA` reader - Transfer active"] +pub type TA_R = crate::BitReader; +#[doc = "Field `TA` writer - Transfer active"] +pub type TA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - Enable DMA"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - Enable DMA"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `INTD` reader - Interrupt on done"] +pub type INTD_R = crate::BitReader; +#[doc = "Field `INTD` writer - Interrupt on done"] +pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `INTR` reader - Interrupt on RX"] +pub type INTR_R = crate::BitReader; +#[doc = "Field `INTR` writer - Interrupt on RX"] +pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `ADCS` reader - Automatically deassert chip select"] +pub type ADCS_R = crate::BitReader; +#[doc = "Field `ADCS` writer - Automatically deassert chip select"] +pub type ADCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `REN` reader - Read enable"] +pub type REN_R = crate::BitReader; +#[doc = "Field `REN` writer - Read enable"] +pub type REN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LEN` reader - LoSSI enable"] +pub type LEN_R = crate::BitReader; +#[doc = "Field `LEN` writer - LoSSI enable"] +pub type LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LMONO` reader - "] +pub type LMONO_R = crate::BitReader; +#[doc = "Field `LMONO` writer - "] +pub type LMONO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `TE_EN` reader - "] +pub type TE_EN_R = crate::BitReader; +#[doc = "Field `TE_EN` writer - "] +pub type TE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DONE` reader - Transfer is done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `RXD` reader - RX FIFO contains data"] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXD` reader - TX FIFO can accept data"] +pub type TXD_R = crate::BitReader; +#[doc = "Field `RXR` reader - RX FIFO has data to be read"] +pub type RXR_R = crate::BitReader; +#[doc = "Field `RXF` reader - RX FIFO full"] +pub type RXF_R = crate::BitReader; +#[doc = "Field `CSPOL0` reader - Chip select 0 polarity"] +pub type CSPOL0_R = crate::BitReader; +#[doc = "Field `CSPOL0` writer - Chip select 0 polarity"] +pub type CSPOL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CSPOL1` reader - Chip select 1 polarity"] +pub type CSPOL1_R = crate::BitReader; +#[doc = "Field `CSPOL1` writer - Chip select 1 polarity"] +pub type CSPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CSPOL2` reader - Chip select 2 polarity"] +pub type CSPOL2_R = crate::BitReader; +#[doc = "Field `CSPOL2` writer - Chip select 2 polarity"] +pub type CSPOL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"] +pub type DMA_LEN_R = crate::BitReader; +#[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"] +pub type DMA_LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"] +pub type LEN_LONG_R = crate::BitReader; +#[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"] +pub type LEN_LONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Chip select"] + #[inline(always)] + pub fn cs(&self) -> CS_R { + CS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Clock phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clock polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Clear the FIFO(s)"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Chip select polarity"] + #[inline(always)] + pub fn cspol(&self) -> CSPOL_R { + CSPOL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transfer active"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable DMA"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on done"] + #[inline(always)] + pub fn intd(&self) -> INTD_R { + INTD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Automatically deassert chip select"] + #[inline(always)] + pub fn adcs(&self) -> ADCS_R { + ADCS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Read enable"] + #[inline(always)] + pub fn ren(&self) -> REN_R { + REN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LoSSI enable"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn lmono(&self) -> LMONO_R { + LMONO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn te_en(&self) -> TE_EN_R { + TE_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Transfer is done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - RX FIFO contains data"] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - TX FIFO can accept data"] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RX FIFO has data to be read"] + #[inline(always)] + pub fn rxr(&self) -> RXR_R { + RXR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - RX FIFO full"] + #[inline(always)] + pub fn rxf(&self) -> RXF_R { + RXF_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Chip select 0 polarity"] + #[inline(always)] + pub fn cspol0(&self) -> CSPOL0_R { + CSPOL0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Chip select 1 polarity"] + #[inline(always)] + pub fn cspol1(&self) -> CSPOL1_R { + CSPOL1_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Chip select 2 polarity"] + #[inline(always)] + pub fn cspol2(&self) -> CSPOL2_R { + CSPOL2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable DMA in LoSSI mode"] + #[inline(always)] + pub fn dma_len(&self) -> DMA_LEN_R { + DMA_LEN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Enable long data word in LoSSI mode"] + #[inline(always)] + pub fn len_long(&self) -> LEN_LONG_R { + LEN_LONG_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Chip select"] + #[inline(always)] + #[must_use] + pub fn cs(&mut self) -> CS_W<0> { + CS_W::new(self) + } + #[doc = "Bit 2 - Clock phase"] + #[inline(always)] + #[must_use] + pub fn cpha(&mut self) -> CPHA_W<2> { + CPHA_W::new(self) + } + #[doc = "Bit 3 - Clock polarity"] + #[inline(always)] + #[must_use] + pub fn cpol(&mut self) -> CPOL_W<3> { + CPOL_W::new(self) + } + #[doc = "Bits 4:5 - Clear the FIFO(s)"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<4> { + CLEAR_W::new(self) + } + #[doc = "Bit 6 - Chip select polarity"] + #[inline(always)] + #[must_use] + pub fn cspol(&mut self) -> CSPOL_W<6> { + CSPOL_W::new(self) + } + #[doc = "Bit 7 - Transfer active"] + #[inline(always)] + #[must_use] + pub fn ta(&mut self) -> TA_W<7> { + TA_W::new(self) + } + #[doc = "Bit 8 - Enable DMA"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<8> { + DMAEN_W::new(self) + } + #[doc = "Bit 9 - Interrupt on done"] + #[inline(always)] + #[must_use] + pub fn intd(&mut self) -> INTD_W<9> { + INTD_W::new(self) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W<10> { + INTR_W::new(self) + } + #[doc = "Bit 11 - Automatically deassert chip select"] + #[inline(always)] + #[must_use] + pub fn adcs(&mut self) -> ADCS_W<11> { + ADCS_W::new(self) + } + #[doc = "Bit 12 - Read enable"] + #[inline(always)] + #[must_use] + pub fn ren(&mut self) -> REN_W<12> { + REN_W::new(self) + } + #[doc = "Bit 13 - LoSSI enable"] + #[inline(always)] + #[must_use] + pub fn len(&mut self) -> LEN_W<13> { + LEN_W::new(self) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn lmono(&mut self) -> LMONO_W<14> { + LMONO_W::new(self) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn te_en(&mut self) -> TE_EN_W<15> { + TE_EN_W::new(self) + } + #[doc = "Bit 21 - Chip select 0 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol0(&mut self) -> CSPOL0_W<21> { + CSPOL0_W::new(self) + } + #[doc = "Bit 22 - Chip select 1 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol1(&mut self) -> CSPOL1_W<22> { + CSPOL1_W::new(self) + } + #[doc = "Bit 23 - Chip select 2 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol2(&mut self) -> CSPOL2_W<23> { + CSPOL2_W::new(self) + } + #[doc = "Bit 24 - Enable DMA in LoSSI mode"] + #[inline(always)] + #[must_use] + pub fn dma_len(&mut self) -> DMA_LEN_W<24> { + DMA_LEN_W::new(self) + } + #[doc = "Bit 25 - Enable long data word in LoSSI mode"] + #[inline(always)] + #[must_use] + pub fn len_long(&mut self) -> LEN_LONG_W<25> { + LEN_LONG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0x0004_1000"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_1000; +} diff --git a/crates/bcm2711-lpa/src/spi0/dc.rs b/crates/bcm2711-lpa/src/spi0/dc.rs new file mode 100644 index 0000000..281dd71 --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0/dc.rs @@ -0,0 +1,125 @@ +#[doc = "Register `DC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDREQ` reader - DMA Write request threshold"] +pub type TDREQ_R = crate::FieldReader; +#[doc = "Field `TDREQ` writer - DMA Write request threshold"] +pub type TDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `TPANIC` reader - DMA write panic threshold"] +pub type TPANIC_R = crate::FieldReader; +#[doc = "Field `TPANIC` writer - DMA write panic threshold"] +pub type TPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `RDREQ` reader - DMA read request threshold"] +pub type RDREQ_R = crate::FieldReader; +#[doc = "Field `RDREQ` writer - DMA read request threshold"] +pub type RDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `RPANIC` reader - DMA read panic threshold"] +pub type RPANIC_R = crate::FieldReader; +#[doc = "Field `RPANIC` writer - DMA read panic threshold"] +pub type RPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA Write request threshold"] + #[inline(always)] + pub fn tdreq(&self) -> TDREQ_R { + TDREQ_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA write panic threshold"] + #[inline(always)] + pub fn tpanic(&self) -> TPANIC_R { + TPANIC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA read request threshold"] + #[inline(always)] + pub fn rdreq(&self) -> RDREQ_R { + RDREQ_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA read panic threshold"] + #[inline(always)] + pub fn rpanic(&self) -> RPANIC_R { + RPANIC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA Write request threshold"] + #[inline(always)] + #[must_use] + pub fn tdreq(&mut self) -> TDREQ_W<0> { + TDREQ_W::new(self) + } + #[doc = "Bits 8:15 - DMA write panic threshold"] + #[inline(always)] + #[must_use] + pub fn tpanic(&mut self) -> TPANIC_W<8> { + TPANIC_W::new(self) + } + #[doc = "Bits 16:23 - DMA read request threshold"] + #[inline(always)] + #[must_use] + pub fn rdreq(&mut self) -> RDREQ_W<16> { + RDREQ_W::new(self) + } + #[doc = "Bits 24:31 - DMA read panic threshold"] + #[inline(always)] + #[must_use] + pub fn rpanic(&mut self) -> RPANIC_W<24> { + RPANIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc](index.html) module"] +pub struct DC_SPEC; +impl crate::RegisterSpec for DC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dc::R](R) reader structure"] +impl crate::Readable for DC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dc::W](W) writer structure"] +impl crate::Writable for DC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DC to value 0x3020_1050"] +impl crate::Resettable for DC_SPEC { + const RESET_VALUE: Self::Ux = 0x3020_1050; +} diff --git a/crates/bcm2711-lpa/src/spi0/dlen.rs b/crates/bcm2711-lpa/src/spi0/dlen.rs new file mode 100644 index 0000000..25e2771 --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0/dlen.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLEN` reader - Data length"] +pub type DLEN_R = crate::FieldReader; +#[doc = "Field `DLEN` writer - Data length"] +pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + pub fn dlen(&self) -> DLEN_R { + DLEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + #[must_use] + pub fn dlen(&mut self) -> DLEN_W<0> { + DLEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +pub struct DLEN_SPEC; +impl crate::RegisterSpec for DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dlen::R](R) reader structure"] +impl crate::Readable for DLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +impl crate::Writable for DLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLEN to value 0"] +impl crate::Resettable for DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi0/fifo.rs b/crates/bcm2711-lpa/src/spi0/fifo.rs new file mode 100644 index 0000000..46d2ece --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0/fifo.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FIFO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo::R](R) reader structure"] +impl crate::Readable for FIFO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi0/ltoh.rs b/crates/bcm2711-lpa/src/spi0/ltoh.rs new file mode 100644 index 0000000..5d0ab3f --- /dev/null +++ b/crates/bcm2711-lpa/src/spi0/ltoh.rs @@ -0,0 +1,80 @@ +#[doc = "Register `LTOH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LTOH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOH` reader - Output hold delay"] +pub type TOH_R = crate::FieldReader; +#[doc = "Field `TOH` writer - Output hold delay"] +pub type TOH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LTOH_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Output hold delay"] + #[inline(always)] + pub fn toh(&self) -> TOH_R { + TOH_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Output hold delay"] + #[inline(always)] + #[must_use] + pub fn toh(&mut self) -> TOH_W<0> { + TOH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LoSSI output hold delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ltoh](index.html) module"] +pub struct LTOH_SPEC; +impl crate::RegisterSpec for LTOH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ltoh::R](R) reader structure"] +impl crate::Readable for LTOH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ltoh::W](W) writer structure"] +impl crate::Writable for LTOH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LTOH to value 0x01"] +impl crate::Resettable for LTOH_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/crates/bcm2711-lpa/src/spi1.rs b/crates/bcm2711-lpa/src/spi1.rs new file mode 100644 index 0000000..1547fcc --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control 0"] + pub cntl0: CNTL0, + #[doc = "0x04 - Control 1"] + pub cntl1: CNTL1, + #[doc = "0x08 - Status"] + pub stat: STAT, + #[doc = "0x0c - Read the RXFIFO without removing an entry"] + pub peek: PEEK, + #[doc = "0x10..0x20 - Writing to the FIFO will deassert CS at the end of the access"] + pub io: [IO; 4], + #[doc = "0x20..0x30 - Writing to the FIFO will maintain CS at the end of the access"] + pub txhold: [TXHOLD; 4], +} +#[doc = "CNTL0 (rw) register accessor: an alias for `Reg`"] +pub type CNTL0 = crate::Reg; +#[doc = "Control 0"] +pub mod cntl0; +#[doc = "CNTL1 (rw) register accessor: an alias for `Reg`"] +pub type CNTL1 = crate::Reg; +#[doc = "Control 1"] +pub mod cntl1; +#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "PEEK (r) register accessor: an alias for `Reg`"] +pub type PEEK = crate::Reg; +#[doc = "Read the RXFIFO without removing an entry"] +pub mod peek; +#[doc = "IO (rw) register accessor: an alias for `Reg`"] +pub type IO = crate::Reg; +#[doc = "Writing to the FIFO will deassert CS at the end of the access"] +pub mod io; +#[doc = "TXHOLD (rw) register accessor: an alias for `Reg`"] +pub type TXHOLD = crate::Reg; +#[doc = "Writing to the FIFO will maintain CS at the end of the access"] +pub mod txhold; diff --git a/crates/bcm2711-lpa/src/spi1/cntl0.rs b/crates/bcm2711-lpa/src/spi1/cntl0.rs new file mode 100644 index 0000000..b9354b5 --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1/cntl0.rs @@ -0,0 +1,335 @@ +#[doc = "Register `CNTL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFT_LENGTH` reader - Number of bits to shift"] +pub type SHIFT_LENGTH_R = crate::FieldReader; +#[doc = "Field `SHIFT_LENGTH` writer - Number of bits to shift"] +pub type SHIFT_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 6, O>; +#[doc = "Field `MSB_FIRST` reader - Shift out the most significant bit (MSB) first"] +pub type MSB_FIRST_R = crate::BitReader; +#[doc = "Field `MSB_FIRST` writer - Shift out the most significant bit (MSB) first"] +pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `INVERT_CLK` reader - Idle clock high"] +pub type INVERT_CLK_R = crate::BitReader; +#[doc = "Field `INVERT_CLK` writer - Idle clock high"] +pub type INVERT_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `OUT_RISING` reader - Data is clocked out on rising edge of CLK"] +pub type OUT_RISING_R = crate::BitReader; +#[doc = "Field `OUT_RISING` writer - Data is clocked out on rising edge of CLK"] +pub type OUT_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `CLEAR_FIFOS` reader - Clear FIFOs"] +pub type CLEAR_FIFOS_R = crate::BitReader; +#[doc = "Field `CLEAR_FIFOS` writer - Clear FIFOs"] +pub type CLEAR_FIFOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `IN_RISING` reader - Data is clocked in on rising edge of CLK"] +pub type IN_RISING_R = crate::BitReader; +#[doc = "Field `IN_RISING` writer - Data is clocked in on rising edge of CLK"] +pub type IN_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable the interface"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable the interface"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `DOUT_HOLD_TIME` reader - Controls extra DOUT hold time in system clock cycles"] +pub type DOUT_HOLD_TIME_R = crate::FieldReader; +#[doc = "Controls extra DOUT hold time in system clock cycles\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DOUT_HOLD_TIME_A { + #[doc = "0: `0`"] + _0 = 0, + #[doc = "1: `1`"] + _1 = 1, + #[doc = "2: `10`"] + _4 = 2, + #[doc = "3: `11`"] + _7 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOUT_HOLD_TIME_A) -> Self { + variant as _ + } +} +impl DOUT_HOLD_TIME_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOUT_HOLD_TIME_A { + match self.bits { + 0 => DOUT_HOLD_TIME_A::_0, + 1 => DOUT_HOLD_TIME_A::_1, + 2 => DOUT_HOLD_TIME_A::_4, + 3 => DOUT_HOLD_TIME_A::_7, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_1 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_4 + } + #[doc = "Checks if the value of the field is `_7`"] + #[inline(always)] + pub fn is_7(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_7 + } +} +#[doc = "Field `DOUT_HOLD_TIME` writer - Controls extra DOUT hold time in system clock cycles"] +pub type DOUT_HOLD_TIME_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CNTL0_SPEC, u8, DOUT_HOLD_TIME_A, 2, O>; +impl<'a, const O: u8> DOUT_HOLD_TIME_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_0) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_1) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_4) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _7(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_7) + } +} +#[doc = "Field `VARIABLE_WIDTH` reader - Take shift length and data from FIFO"] +pub type VARIABLE_WIDTH_R = crate::BitReader; +#[doc = "Field `VARIABLE_WIDTH` writer - Take shift length and data from FIFO"] +pub type VARIABLE_WIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `VARIABLE_CS` reader - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] +pub type VARIABLE_CS_R = crate::BitReader; +#[doc = "Field `VARIABLE_CS` writer - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] +pub type VARIABLE_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `POST_INPUT` reader - Post input mode"] +pub type POST_INPUT_R = crate::BitReader; +#[doc = "Field `POST_INPUT` writer - Post input mode"] +pub type POST_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `CHIP_SELECTS` reader - The CS pattern when active"] +pub type CHIP_SELECTS_R = crate::FieldReader; +#[doc = "Field `CHIP_SELECTS` writer - The CS pattern when active"] +pub type CHIP_SELECTS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 3, O>; +#[doc = "Field `SPEED` reader - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Field `SPEED` writer - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] +pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:5 - Number of bits to shift"] + #[inline(always)] + pub fn shift_length(&self) -> SHIFT_LENGTH_R { + SHIFT_LENGTH_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] + #[inline(always)] + pub fn msb_first(&self) -> MSB_FIRST_R { + MSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Idle clock high"] + #[inline(always)] + pub fn invert_clk(&self) -> INVERT_CLK_R { + INVERT_CLK_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] + #[inline(always)] + pub fn out_rising(&self) -> OUT_RISING_R { + OUT_RISING_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Clear FIFOs"] + #[inline(always)] + pub fn clear_fifos(&self) -> CLEAR_FIFOS_R { + CLEAR_FIFOS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] + #[inline(always)] + pub fn in_rising(&self) -> IN_RISING_R { + IN_RISING_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable the interface"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] + #[inline(always)] + pub fn dout_hold_time(&self) -> DOUT_HOLD_TIME_R { + DOUT_HOLD_TIME_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Take shift length and data from FIFO"] + #[inline(always)] + pub fn variable_width(&self) -> VARIABLE_WIDTH_R { + VARIABLE_WIDTH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] + #[inline(always)] + pub fn variable_cs(&self) -> VARIABLE_CS_R { + VARIABLE_CS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Post input mode"] + #[inline(always)] + pub fn post_input(&self) -> POST_INPUT_R { + POST_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - The CS pattern when active"] + #[inline(always)] + pub fn chip_selects(&self) -> CHIP_SELECTS_R { + CHIP_SELECTS_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:5 - Number of bits to shift"] + #[inline(always)] + #[must_use] + pub fn shift_length(&mut self) -> SHIFT_LENGTH_W<0> { + SHIFT_LENGTH_W::new(self) + } + #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] + #[inline(always)] + #[must_use] + pub fn msb_first(&mut self) -> MSB_FIRST_W<6> { + MSB_FIRST_W::new(self) + } + #[doc = "Bit 7 - Idle clock high"] + #[inline(always)] + #[must_use] + pub fn invert_clk(&mut self) -> INVERT_CLK_W<7> { + INVERT_CLK_W::new(self) + } + #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] + #[inline(always)] + #[must_use] + pub fn out_rising(&mut self) -> OUT_RISING_W<8> { + OUT_RISING_W::new(self) + } + #[doc = "Bit 9 - Clear FIFOs"] + #[inline(always)] + #[must_use] + pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W<9> { + CLEAR_FIFOS_W::new(self) + } + #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] + #[inline(always)] + #[must_use] + pub fn in_rising(&mut self) -> IN_RISING_W<10> { + IN_RISING_W::new(self) + } + #[doc = "Bit 11 - Enable the interface"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<11> { + ENABLE_W::new(self) + } + #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] + #[inline(always)] + #[must_use] + pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W<12> { + DOUT_HOLD_TIME_W::new(self) + } + #[doc = "Bit 14 - Take shift length and data from FIFO"] + #[inline(always)] + #[must_use] + pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W<14> { + VARIABLE_WIDTH_W::new(self) + } + #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] + #[inline(always)] + #[must_use] + pub fn variable_cs(&mut self) -> VARIABLE_CS_W<15> { + VARIABLE_CS_W::new(self) + } + #[doc = "Bit 16 - Post input mode"] + #[inline(always)] + #[must_use] + pub fn post_input(&mut self) -> POST_INPUT_W<16> { + POST_INPUT_W::new(self) + } + #[doc = "Bits 17:19 - The CS pattern when active"] + #[inline(always)] + #[must_use] + pub fn chip_selects(&mut self) -> CHIP_SELECTS_W<17> { + CHIP_SELECTS_W::new(self) + } + #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W<20> { + SPEED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl0](index.html) module"] +pub struct CNTL0_SPEC; +impl crate::RegisterSpec for CNTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl0::R](R) reader structure"] +impl crate::Readable for CNTL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl0::W](W) writer structure"] +impl crate::Writable for CNTL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL0 to value 0x000e_0000"] +impl crate::Resettable for CNTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x000e_0000; +} diff --git a/crates/bcm2711-lpa/src/spi1/cntl1.rs b/crates/bcm2711-lpa/src/spi1/cntl1.rs new file mode 100644 index 0000000..c7d627b --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1/cntl1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CNTL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEEP_INPUT` reader - Don't clear the RX shift register before a new transaction"] +pub type KEEP_INPUT_R = crate::BitReader; +#[doc = "Field `KEEP_INPUT` writer - Don't clear the RX shift register before a new transaction"] +pub type KEEP_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `MSB_FIRST` reader - Shift the most significant bit first (MSB)"] +pub type MSB_FIRST_R = crate::BitReader; +#[doc = "Field `MSB_FIRST` writer - Shift the most significant bit first (MSB)"] +pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `DONE_ENABLE` reader - Enable DONE interrupt"] +pub type DONE_ENABLE_R = crate::BitReader; +#[doc = "Field `DONE_ENABLE` writer - Enable DONE interrupt"] +pub type DONE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `TXE_ENABLE` reader - Enable TX empty interrupt"] +pub type TXE_ENABLE_R = crate::BitReader; +#[doc = "Field `TXE_ENABLE` writer - Enable TX empty interrupt"] +pub type TXE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `CS_HIGH_TIME` reader - Additional SPI clock cycles where CS is high"] +pub type CS_HIGH_TIME_R = crate::FieldReader; +#[doc = "Field `CS_HIGH_TIME` writer - Additional SPI clock cycles where CS is high"] +pub type CS_HIGH_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL1_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] + #[inline(always)] + pub fn keep_input(&self) -> KEEP_INPUT_R { + KEEP_INPUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] + #[inline(always)] + pub fn msb_first(&self) -> MSB_FIRST_R { + MSB_FIRST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Enable DONE interrupt"] + #[inline(always)] + pub fn done_enable(&self) -> DONE_ENABLE_R { + DONE_ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable TX empty interrupt"] + #[inline(always)] + pub fn txe_enable(&self) -> TXE_ENABLE_R { + TXE_ENABLE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] + #[inline(always)] + pub fn cs_high_time(&self) -> CS_HIGH_TIME_R { + CS_HIGH_TIME_R::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] + #[inline(always)] + #[must_use] + pub fn keep_input(&mut self) -> KEEP_INPUT_W<0> { + KEEP_INPUT_W::new(self) + } + #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] + #[inline(always)] + #[must_use] + pub fn msb_first(&mut self) -> MSB_FIRST_W<1> { + MSB_FIRST_W::new(self) + } + #[doc = "Bit 6 - Enable DONE interrupt"] + #[inline(always)] + #[must_use] + pub fn done_enable(&mut self) -> DONE_ENABLE_W<6> { + DONE_ENABLE_W::new(self) + } + #[doc = "Bit 7 - Enable TX empty interrupt"] + #[inline(always)] + #[must_use] + pub fn txe_enable(&mut self) -> TXE_ENABLE_W<7> { + TXE_ENABLE_W::new(self) + } + #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] + #[inline(always)] + #[must_use] + pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W<8> { + CS_HIGH_TIME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl1](index.html) module"] +pub struct CNTL1_SPEC; +impl crate::RegisterSpec for CNTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl1::R](R) reader structure"] +impl crate::Readable for CNTL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl1::W](W) writer structure"] +impl crate::Writable for CNTL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL1 to value 0"] +impl crate::Resettable for CNTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi1/io.rs b/crates/bcm2711-lpa/src/spi1/io.rs new file mode 100644 index 0000000..365004d --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1/io.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IO%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IO%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO data access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +pub struct IO_SPEC; +impl crate::RegisterSpec for IO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [io::R](R) reader structure"] +impl crate::Readable for IO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +impl crate::Writable for IO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IO%s to value 0"] +impl crate::Resettable for IO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi1/peek.rs b/crates/bcm2711-lpa/src/spi1/peek.rs new file mode 100644 index 0000000..b4a7333 --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1/peek.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PEEK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Read the RXFIFO without removing an entry\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek](index.html) module"] +pub struct PEEK_SPEC; +impl crate::RegisterSpec for PEEK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek::R](R) reader structure"] +impl crate::Readable for PEEK_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PEEK to value 0"] +impl crate::Resettable for PEEK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi1/stat.rs b/crates/bcm2711-lpa/src/spi1/stat.rs new file mode 100644 index 0000000..0dd56f6 --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1/stat.rs @@ -0,0 +1,185 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIT_COUNT` reader - Number of bits left to be processed."] +pub type BIT_COUNT_R = crate::FieldReader; +#[doc = "Field `BIT_COUNT` writer - Number of bits left to be processed."] +pub type BIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 6, O>; +#[doc = "Field `BUSY` reader - Indicates a transfer is ongoing"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `BUSY` writer - Indicates a transfer is ongoing"] +pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_EMPTY` reader - RX FIFO is empty"] +pub type RX_EMPTY_R = crate::BitReader; +#[doc = "Field `RX_EMPTY` writer - RX FIFO is empty"] +pub type RX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_FULL` reader - RX FIFO is full"] +pub type RX_FULL_R = crate::BitReader; +#[doc = "Field `RX_FULL` writer - RX FIFO is full"] +pub type RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - TX FIFO is empty"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - TX FIFO is empty"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_FULL` reader - TX FIFO is full"] +pub type TX_FULL_R = crate::BitReader; +#[doc = "Field `TX_FULL` writer - TX FIFO is full"] +pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_LEVEL` reader - Number of entries in RX FIFO"] +pub type RX_LEVEL_R = crate::FieldReader; +#[doc = "Field `RX_LEVEL` writer - Number of entries in RX FIFO"] +pub type RX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_LEVEL` reader - Number of entries in TX FIFO"] +pub type TX_LEVEL_R = crate::FieldReader; +#[doc = "Field `TX_LEVEL` writer - Number of entries in TX FIFO"] +pub type TX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:5 - Number of bits left to be processed."] + #[inline(always)] + pub fn bit_count(&self) -> BIT_COUNT_R { + BIT_COUNT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Indicates a transfer is ongoing"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RX FIFO is empty"] + #[inline(always)] + pub fn rx_empty(&self) -> RX_EMPTY_R { + RX_EMPTY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is full"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TX FIFO is empty"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO is full"] + #[inline(always)] + pub fn tx_full(&self) -> TX_FULL_R { + TX_FULL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 16:19 - Number of entries in RX FIFO"] + #[inline(always)] + pub fn rx_level(&self) -> RX_LEVEL_R { + RX_LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Number of entries in TX FIFO"] + #[inline(always)] + pub fn tx_level(&self) -> TX_LEVEL_R { + TX_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Number of bits left to be processed."] + #[inline(always)] + #[must_use] + pub fn bit_count(&mut self) -> BIT_COUNT_W<0> { + BIT_COUNT_W::new(self) + } + #[doc = "Bit 6 - Indicates a transfer is ongoing"] + #[inline(always)] + #[must_use] + pub fn busy(&mut self) -> BUSY_W<6> { + BUSY_W::new(self) + } + #[doc = "Bit 7 - RX FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn rx_empty(&mut self) -> RX_EMPTY_W<7> { + RX_EMPTY_W::new(self) + } + #[doc = "Bit 8 - RX FIFO is full"] + #[inline(always)] + #[must_use] + pub fn rx_full(&mut self) -> RX_FULL_W<8> { + RX_FULL_W::new(self) + } + #[doc = "Bit 9 - TX FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<9> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 10 - TX FIFO is full"] + #[inline(always)] + #[must_use] + pub fn tx_full(&mut self) -> TX_FULL_W<10> { + TX_FULL_W::new(self) + } + #[doc = "Bits 16:19 - Number of entries in RX FIFO"] + #[inline(always)] + #[must_use] + pub fn rx_level(&mut self) -> RX_LEVEL_W<16> { + RX_LEVEL_W::new(self) + } + #[doc = "Bits 24:27 - Number of entries in TX FIFO"] + #[inline(always)] + #[must_use] + pub fn tx_level(&mut self) -> TX_LEVEL_W<24> { + TX_LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/spi1/txhold.rs b/crates/bcm2711-lpa/src/spi1/txhold.rs new file mode 100644 index 0000000..a2ca31b --- /dev/null +++ b/crates/bcm2711-lpa/src/spi1/txhold.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TXHOLD%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXHOLD%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO data access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXHOLD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txhold](index.html) module"] +pub struct TXHOLD_SPEC; +impl crate::RegisterSpec for TXHOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txhold::R](R) reader structure"] +impl crate::Readable for TXHOLD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txhold::W](W) writer structure"] +impl crate::Writable for TXHOLD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TXHOLD%s to value 0"] +impl crate::Resettable for TXHOLD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr.rs b/crates/bcm2711-lpa/src/systmr.rs new file mode 100644 index 0000000..859ea09 --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control / Status"] + pub cs: CS, + #[doc = "0x04 - Lower 32 bits for the free running counter"] + pub clo: CLO, + #[doc = "0x08 - Higher 32 bits for the free running counter"] + pub chi: CHI, + #[doc = "0x0c - Compare channel 0"] + pub c0: C0, + #[doc = "0x10 - Compare channel 1"] + pub c1: C1, + #[doc = "0x14 - Compare channel 2"] + pub c2: C2, + #[doc = "0x18 - Compare channel 3"] + pub c3: C3, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control / Status"] +pub mod cs; +#[doc = "CLO (r) register accessor: an alias for `Reg`"] +pub type CLO = crate::Reg; +#[doc = "Lower 32 bits for the free running counter"] +pub mod clo; +#[doc = "CHI (r) register accessor: an alias for `Reg`"] +pub type CHI = crate::Reg; +#[doc = "Higher 32 bits for the free running counter"] +pub mod chi; +#[doc = "C0 (rw) register accessor: an alias for `Reg`"] +pub type C0 = crate::Reg; +#[doc = "Compare channel 0"] +pub mod c0; +#[doc = "C1 (rw) register accessor: an alias for `Reg`"] +pub type C1 = crate::Reg; +#[doc = "Compare channel 1"] +pub mod c1; +#[doc = "C2 (rw) register accessor: an alias for `Reg`"] +pub type C2 = crate::Reg; +#[doc = "Compare channel 2"] +pub mod c2; +#[doc = "C3 (rw) register accessor: an alias for `Reg`"] +pub type C3 = crate::Reg; +#[doc = "Compare channel 3"] +pub mod c3; diff --git a/crates/bcm2711-lpa/src/systmr/c0.rs b/crates/bcm2711-lpa/src/systmr/c0.rs new file mode 100644 index 0000000..20b09d2 --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/c0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c0](index.html) module"] +pub struct C0_SPEC; +impl crate::RegisterSpec for C0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c0::R](R) reader structure"] +impl crate::Readable for C0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c0::W](W) writer structure"] +impl crate::Writable for C0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C0 to value 0"] +impl crate::Resettable for C0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr/c1.rs b/crates/bcm2711-lpa/src/systmr/c1.rs new file mode 100644 index 0000000..87cf5ed --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/c1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1](index.html) module"] +pub struct C1_SPEC; +impl crate::RegisterSpec for C1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c1::R](R) reader structure"] +impl crate::Readable for C1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c1::W](W) writer structure"] +impl crate::Writable for C1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C1 to value 0"] +impl crate::Resettable for C1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr/c2.rs b/crates/bcm2711-lpa/src/systmr/c2.rs new file mode 100644 index 0000000..8c9c84b --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/c2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c2](index.html) module"] +pub struct C2_SPEC; +impl crate::RegisterSpec for C2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c2::R](R) reader structure"] +impl crate::Readable for C2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c2::W](W) writer structure"] +impl crate::Writable for C2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C2 to value 0"] +impl crate::Resettable for C2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr/c3.rs b/crates/bcm2711-lpa/src/systmr/c3.rs new file mode 100644 index 0000000..0ac0aa2 --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/c3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c3](index.html) module"] +pub struct C3_SPEC; +impl crate::RegisterSpec for C3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c3::R](R) reader structure"] +impl crate::Readable for C3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c3::W](W) writer structure"] +impl crate::Writable for C3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C3 to value 0"] +impl crate::Resettable for C3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr/chi.rs b/crates/bcm2711-lpa/src/systmr/chi.rs new file mode 100644 index 0000000..9f162ef --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/chi.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CHI` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Higher 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chi](index.html) module"] +pub struct CHI_SPEC; +impl crate::RegisterSpec for CHI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chi::R](R) reader structure"] +impl crate::Readable for CHI_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHI to value 0"] +impl crate::Resettable for CHI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr/clo.rs b/crates/bcm2711-lpa/src/systmr/clo.rs new file mode 100644 index 0000000..0a4b01f --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/clo.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CLO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Lower 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clo](index.html) module"] +pub struct CLO_SPEC; +impl crate::RegisterSpec for CLO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clo::R](R) reader structure"] +impl crate::Readable for CLO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CLO to value 0"] +impl crate::Resettable for CLO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/systmr/cs.rs b/crates/bcm2711-lpa/src/systmr/cs.rs new file mode 100644 index 0000000..dcb8ec2 --- /dev/null +++ b/crates/bcm2711-lpa/src/systmr/cs.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0` reader - System timer match 0"] +pub type M0_R = crate::BitReader; +#[doc = "Field `M0` writer - System timer match 0"] +pub type M0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M1` reader - System timer match 1"] +pub type M1_R = crate::BitReader; +#[doc = "Field `M1` writer - System timer match 1"] +pub type M1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M2` reader - System timer match 2"] +pub type M2_R = crate::BitReader; +#[doc = "Field `M2` writer - System timer match 2"] +pub type M2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M3` reader - System timer match 3"] +pub type M3_R = crate::BitReader; +#[doc = "Field `M3` writer - System timer match 3"] +pub type M3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - System timer match 0"] + #[inline(always)] + pub fn m0(&self) -> M0_R { + M0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - System timer match 1"] + #[inline(always)] + pub fn m1(&self) -> M1_R { + M1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - System timer match 2"] + #[inline(always)] + pub fn m2(&self) -> M2_R { + M2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - System timer match 3"] + #[inline(always)] + pub fn m3(&self) -> M3_R { + M3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - System timer match 0"] + #[inline(always)] + #[must_use] + pub fn m0(&mut self) -> M0_W<0> { + M0_W::new(self) + } + #[doc = "Bit 1 - System timer match 1"] + #[inline(always)] + #[must_use] + pub fn m1(&mut self) -> M1_W<1> { + M1_W::new(self) + } + #[doc = "Bit 2 - System timer match 2"] + #[inline(always)] + #[must_use] + pub fn m2(&mut self) -> M2_W<2> { + M2_W::new(self) + } + #[doc = "Bit 3 - System timer match 3"] + #[inline(always)] + #[must_use] + pub fn m3(&mut self) -> M3_W<3> { + M3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0.rs b/crates/bcm2711-lpa/src/uart0.rs new file mode 100644 index 0000000..aade8a9 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Data Register"] + pub dr: DR, + _reserved_1_ecr: [u8; 0x04], + _reserved2: [u8; 0x10], + #[doc = "0x18 - Flag Register"] + pub fr: FR, + _reserved3: [u8; 0x08], + #[doc = "0x24 - Integer Baud Rate Register"] + pub ibrd: IBRD, + #[doc = "0x28 - Fractional Baud Rate Register"] + pub fbrd: FBRD, + #[doc = "0x2c - Line Control Register"] + pub lcr_h: LCR_H, + #[doc = "0x30 - Control Register"] + pub cr: CR, + #[doc = "0x34 - Interrupt FIFO Level Select Register"] + pub ifls: IFLS, + #[doc = "0x38 - Interrupt Mask set_Clear Register"] + pub imsc: IMSC, + #[doc = "0x3c - Raw Interrupt Status Register"] + pub ris: RIS, + #[doc = "0x40 - Masked Interrupt Status Register"] + pub mis: MIS, + #[doc = "0x44 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x48 - DMA Control Register"] + pub dmacr: DMACR, +} +impl RegisterBlock { + #[doc = "0x04 - Error Clear Register"] + #[inline(always)] + pub const fn ecr(&self) -> &ECR { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } + #[doc = "0x04 - Receive Status Register"] + #[inline(always)] + pub const fn rsr(&self) -> &RSR { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } +} +#[doc = "DR (rw) register accessor: an alias for `Reg`"] +pub type DR = crate::Reg; +#[doc = "Data Register"] +pub mod dr; +#[doc = "RSR (r) register accessor: an alias for `Reg`"] +pub type RSR = crate::Reg; +#[doc = "Receive Status Register"] +pub mod rsr; +#[doc = "ECR (w) register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Clear Register"] +pub mod ecr; +#[doc = "FR (rw) register accessor: an alias for `Reg`"] +pub type FR = crate::Reg; +#[doc = "Flag Register"] +pub mod fr; +#[doc = "IBRD (rw) register accessor: an alias for `Reg`"] +pub type IBRD = crate::Reg; +#[doc = "Integer Baud Rate Register"] +pub mod ibrd; +#[doc = "FBRD (rw) register accessor: an alias for `Reg`"] +pub type FBRD = crate::Reg; +#[doc = "Fractional Baud Rate Register"] +pub mod fbrd; +#[doc = "LCR_H (rw) register accessor: an alias for `Reg`"] +pub type LCR_H = crate::Reg; +#[doc = "Line Control Register"] +pub mod lcr_h; +#[doc = "CR (rw) register accessor: an alias for `Reg`"] +pub type CR = crate::Reg; +#[doc = "Control Register"] +pub mod cr; +#[doc = "IFLS (rw) register accessor: an alias for `Reg`"] +pub type IFLS = crate::Reg; +#[doc = "Interrupt FIFO Level Select Register"] +pub mod ifls; +#[doc = "IMSC (rw) register accessor: an alias for `Reg`"] +pub type IMSC = crate::Reg; +#[doc = "Interrupt Mask set_Clear Register"] +pub mod imsc; +#[doc = "RIS (r) register accessor: an alias for `Reg`"] +pub type RIS = crate::Reg; +#[doc = "Raw Interrupt Status Register"] +pub mod ris; +#[doc = "MIS (r) register accessor: an alias for `Reg`"] +pub type MIS = crate::Reg; +#[doc = "Masked Interrupt Status Register"] +pub mod mis; +#[doc = "ICR (w) register accessor: an alias for `Reg`"] +pub type ICR = crate::Reg; +#[doc = "Interrupt Clear Register"] +pub mod icr; +#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +pub type DMACR = crate::Reg; +#[doc = "DMA Control Register"] +pub mod dmacr; diff --git a/crates/bcm2711-lpa/src/uart0/cr.rs b/crates/bcm2711-lpa/src/uart0/cr.rs new file mode 100644 index 0000000..6c47a00 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/cr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `CR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UARTEN` reader - UARTEN"] +pub type UARTEN_R = crate::BitReader; +#[doc = "Field `UARTEN` writer - UARTEN"] +pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `SIREN` reader - SIREN"] +pub type SIREN_R = crate::BitReader; +#[doc = "Field `SIREN` writer - SIREN"] +pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `SIRLP` reader - SIRLP"] +pub type SIRLP_R = crate::BitReader; +#[doc = "Field `SIRLP` writer - SIRLP"] +pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `TXE` reader - TXE"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `TXE` writer - TXE"] +pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RXE` reader - RXE"] +pub type RXE_R = crate::BitReader; +#[doc = "Field `RXE` writer - RXE"] +pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `DTR` reader - DTR"] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - DTR"] +pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RTS` reader - RTS"] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - RTS"] +pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RTSEN` reader - RTSEN"] +pub type RTSEN_R = crate::BitReader; +#[doc = "Field `RTSEN` writer - RTSEN"] +pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `CTSEN` reader - CTSEN"] +pub type CTSEN_R = crate::BitReader; +#[doc = "Field `CTSEN` writer - CTSEN"] +pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UARTEN"] + #[inline(always)] + pub fn uarten(&self) -> UARTEN_R { + UARTEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SIREN"] + #[inline(always)] + pub fn siren(&self) -> SIREN_R { + SIREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SIRLP"] + #[inline(always)] + pub fn sirlp(&self) -> SIRLP_R { + SIRLP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - TXE"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RXE"] + #[inline(always)] + pub fn rxe(&self) -> RXE_R { + RXE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DTR"] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RTS"] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - RTSEN"] + #[inline(always)] + pub fn rtsen(&self) -> RTSEN_R { + RTSEN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CTSEN"] + #[inline(always)] + pub fn ctsen(&self) -> CTSEN_R { + CTSEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UARTEN"] + #[inline(always)] + #[must_use] + pub fn uarten(&mut self) -> UARTEN_W<0> { + UARTEN_W::new(self) + } + #[doc = "Bit 1 - SIREN"] + #[inline(always)] + #[must_use] + pub fn siren(&mut self) -> SIREN_W<1> { + SIREN_W::new(self) + } + #[doc = "Bit 2 - SIRLP"] + #[inline(always)] + #[must_use] + pub fn sirlp(&mut self) -> SIRLP_W<2> { + SIRLP_W::new(self) + } + #[doc = "Bit 8 - TXE"] + #[inline(always)] + #[must_use] + pub fn txe(&mut self) -> TXE_W<8> { + TXE_W::new(self) + } + #[doc = "Bit 9 - RXE"] + #[inline(always)] + #[must_use] + pub fn rxe(&mut self) -> RXE_W<9> { + RXE_W::new(self) + } + #[doc = "Bit 10 - DTR"] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W<10> { + DTR_W::new(self) + } + #[doc = "Bit 11 - RTS"] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W<11> { + RTS_W::new(self) + } + #[doc = "Bit 14 - RTSEN"] + #[inline(always)] + #[must_use] + pub fn rtsen(&mut self) -> RTSEN_W<14> { + RTSEN_W::new(self) + } + #[doc = "Bit 15 - CTSEN"] + #[inline(always)] + #[must_use] + pub fn ctsen(&mut self) -> CTSEN_W<15> { + CTSEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +pub struct CR_SPEC; +impl crate::RegisterSpec for CR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cr::R](R) reader structure"] +impl crate::Readable for CR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +impl crate::Writable for CR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CR to value 0"] +impl crate::Resettable for CR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/dmacr.rs b/crates/bcm2711-lpa/src/uart0/dmacr.rs new file mode 100644 index 0000000..8bd3632 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/dmacr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DMACR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMACR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXDMAE` reader - RXDMAE"] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `RXDMAE` writer - RXDMAE"] +pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +#[doc = "Field `TXDMAE` reader - TXDMAE"] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `TXDMAE` writer - TXDMAE"] +pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +#[doc = "Field `DMAONERR` reader - DMAONERR"] +pub type DMAONERR_R = crate::BitReader; +#[doc = "Field `DMAONERR` writer - DMAONERR"] +pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - RXDMAE"] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - TXDMAE"] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMAONERR"] + #[inline(always)] + pub fn dmaonerr(&self) -> DMAONERR_R { + DMAONERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RXDMAE"] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - TXDMAE"] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W<1> { + TXDMAE_W::new(self) + } + #[doc = "Bit 2 - DMAONERR"] + #[inline(always)] + #[must_use] + pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + DMAONERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"] +pub struct DMACR_SPEC; +impl crate::RegisterSpec for DMACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmacr::R](R) reader structure"] +impl crate::Readable for DMACR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +impl crate::Writable for DMACR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMACR to value 0"] +impl crate::Resettable for DMACR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/dr.rs b/crates/bcm2711-lpa/src/uart0/dr.rs new file mode 100644 index 0000000..236d30b --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/dr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - DATA"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - DATA"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>; +#[doc = "Field `FE` reader - FE"] +pub type FE_R = crate::BitReader; +#[doc = "Field `FE` writer - FE"] +pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `PE` reader - PE"] +pub type PE_R = crate::BitReader; +#[doc = "Field `PE` writer - PE"] +pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `BE` reader - BE"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - BE"] +pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `OE` reader - OE"] +pub type OE_R = crate::BitReader; +#[doc = "Field `OE` writer - OE"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:7 - DATA"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - FE"] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PE"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - BE"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - OE"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DATA"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Bit 8 - FE"] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W<8> { + FE_W::new(self) + } + #[doc = "Bit 9 - PE"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W<9> { + PE_W::new(self) + } + #[doc = "Bit 10 - BE"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W<10> { + BE_W::new(self) + } + #[doc = "Bit 11 - OE"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<11> { + OE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] +pub struct DR_SPEC; +impl crate::RegisterSpec for DR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dr::R](R) reader structure"] +impl crate::Readable for DR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] +impl crate::Writable for DR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DR to value 0"] +impl crate::Resettable for DR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/ecr.rs b/crates/bcm2711-lpa/src/uart0/ecr.rs new file mode 100644 index 0000000..f469e97 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/ecr.rs @@ -0,0 +1,76 @@ +#[doc = "Register `ECR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FE` writer - FE"] +pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `PE` writer - PE"] +pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `BE` writer - BE"] +pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `OE` writer - OE"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - FE"] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W<0> { + FE_W::new(self) + } + #[doc = "Bit 1 - PE"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W<1> { + PE_W::new(self) + } + #[doc = "Bit 2 - BE"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W<2> { + BE_W::new(self) + } + #[doc = "Bit 3 - OE"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<3> { + OE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"] +impl crate::Writable for ECR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/fbrd.rs b/crates/bcm2711-lpa/src/uart0/fbrd.rs new file mode 100644 index 0000000..14ae9a3 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/fbrd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FBRD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FBRD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDDIVFRAC` reader - BAUDDIVFRAC"] +pub type BAUDDIVFRAC_R = crate::FieldReader; +#[doc = "Field `BAUDDIVFRAC` writer - BAUDDIVFRAC"] +pub type BAUDDIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBRD_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - BAUDDIVFRAC"] + #[inline(always)] + pub fn bauddivfrac(&self) -> BAUDDIVFRAC_R { + BAUDDIVFRAC_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - BAUDDIVFRAC"] + #[inline(always)] + #[must_use] + pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W<0> { + BAUDDIVFRAC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbrd](index.html) module"] +pub struct FBRD_SPEC; +impl crate::RegisterSpec for FBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fbrd::R](R) reader structure"] +impl crate::Readable for FBRD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fbrd::W](W) writer structure"] +impl crate::Writable for FBRD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FBRD to value 0"] +impl crate::Resettable for FBRD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/fr.rs b/crates/bcm2711-lpa/src/uart0/fr.rs new file mode 100644 index 0000000..641becc --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/fr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `FR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - CTS"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `CTS` writer - CTS"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `DSR` reader - DSR"] +pub type DSR_R = crate::BitReader; +#[doc = "Field `DSR` writer - DSR"] +pub type DSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `DCD` reader - DCD"] +pub type DCD_R = crate::BitReader; +#[doc = "Field `DCD` writer - DCD"] +pub type DCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `BUSY` reader - BUSY"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `BUSY` writer - BUSY"] +pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RXFE` reader - RXFE"] +pub type RXFE_R = crate::BitReader; +#[doc = "Field `RXFE` writer - RXFE"] +pub type RXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `TXFF` reader - TXFF"] +pub type TXFF_R = crate::BitReader; +#[doc = "Field `TXFF` writer - TXFF"] +pub type TXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RXFF` reader - RXFF"] +pub type RXFF_R = crate::BitReader; +#[doc = "Field `RXFF` writer - RXFF"] +pub type RXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `TXFE` reader - TXFE"] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `TXFE` writer - TXFE"] +pub type TXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RI` reader - RI"] +pub type RI_R = crate::BitReader; +#[doc = "Field `RI` writer - RI"] +pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - CTS"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DSR"] + #[inline(always)] + pub fn dsr(&self) -> DSR_R { + DSR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCD"] + #[inline(always)] + pub fn dcd(&self) -> DCD_R { + DCD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BUSY"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXFE"] + #[inline(always)] + pub fn rxfe(&self) -> RXFE_R { + RXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXFF"] + #[inline(always)] + pub fn txff(&self) -> TXFF_R { + TXFF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RXFF"] + #[inline(always)] + pub fn rxff(&self) -> RXFF_R { + RXFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TXFE"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RI"] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CTS"] + #[inline(always)] + #[must_use] + pub fn cts(&mut self) -> CTS_W<0> { + CTS_W::new(self) + } + #[doc = "Bit 1 - DSR"] + #[inline(always)] + #[must_use] + pub fn dsr(&mut self) -> DSR_W<1> { + DSR_W::new(self) + } + #[doc = "Bit 2 - DCD"] + #[inline(always)] + #[must_use] + pub fn dcd(&mut self) -> DCD_W<2> { + DCD_W::new(self) + } + #[doc = "Bit 3 - BUSY"] + #[inline(always)] + #[must_use] + pub fn busy(&mut self) -> BUSY_W<3> { + BUSY_W::new(self) + } + #[doc = "Bit 4 - RXFE"] + #[inline(always)] + #[must_use] + pub fn rxfe(&mut self) -> RXFE_W<4> { + RXFE_W::new(self) + } + #[doc = "Bit 5 - TXFF"] + #[inline(always)] + #[must_use] + pub fn txff(&mut self) -> TXFF_W<5> { + TXFF_W::new(self) + } + #[doc = "Bit 6 - RXFF"] + #[inline(always)] + #[must_use] + pub fn rxff(&mut self) -> RXFF_W<6> { + RXFF_W::new(self) + } + #[doc = "Bit 7 - TXFE"] + #[inline(always)] + #[must_use] + pub fn txfe(&mut self) -> TXFE_W<7> { + TXFE_W::new(self) + } + #[doc = "Bit 8 - RI"] + #[inline(always)] + #[must_use] + pub fn ri(&mut self) -> RI_W<8> { + RI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +pub struct FR_SPEC; +impl crate::RegisterSpec for FR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fr::R](R) reader structure"] +impl crate::Readable for FR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] +impl crate::Writable for FR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FR to value 0"] +impl crate::Resettable for FR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/ibrd.rs b/crates/bcm2711-lpa/src/uart0/ibrd.rs new file mode 100644 index 0000000..65af80e --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/ibrd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IBRD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IBRD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDDIVINT` reader - BAUDDIVINT"] +pub type BAUDDIVINT_R = crate::FieldReader; +#[doc = "Field `BAUDDIVINT` writer - BAUDDIVINT"] +pub type BAUDDIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IBRD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - BAUDDIVINT"] + #[inline(always)] + pub fn bauddivint(&self) -> BAUDDIVINT_R { + BAUDDIVINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - BAUDDIVINT"] + #[inline(always)] + #[must_use] + pub fn bauddivint(&mut self) -> BAUDDIVINT_W<0> { + BAUDDIVINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Integer Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ibrd](index.html) module"] +pub struct IBRD_SPEC; +impl crate::RegisterSpec for IBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ibrd::R](R) reader structure"] +impl crate::Readable for IBRD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ibrd::W](W) writer structure"] +impl crate::Writable for IBRD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IBRD to value 0"] +impl crate::Resettable for IBRD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/icr.rs b/crates/bcm2711-lpa/src/uart0/icr.rs new file mode 100644 index 0000000..509869e --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/icr.rs @@ -0,0 +1,132 @@ +#[doc = "Register `ICR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIMIC` writer - RIMIC"] +pub type RIMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `CTSMIC` writer - CTSMIC"] +pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `DCDMIC` writer - DCDMIC"] +pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `DSRMIC` writer - DSRMIC"] +pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `RXIC` writer - RXIC"] +pub type RXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `TXIC` writer - TXIC"] +pub type TXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `RTIC` writer - RTIC"] +pub type RTIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `FEIC` writer - FEIC"] +pub type FEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `PEIC` writer - PEIC"] +pub type PEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `BEIC` writer - BEIC"] +pub type BEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `OEIC` writer - OEIC"] +pub type OEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - RIMIC"] + #[inline(always)] + #[must_use] + pub fn rimic(&mut self) -> RIMIC_W<0> { + RIMIC_W::new(self) + } + #[doc = "Bit 1 - CTSMIC"] + #[inline(always)] + #[must_use] + pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + CTSMIC_W::new(self) + } + #[doc = "Bit 2 - DCDMIC"] + #[inline(always)] + #[must_use] + pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + DCDMIC_W::new(self) + } + #[doc = "Bit 3 - DSRMIC"] + #[inline(always)] + #[must_use] + pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + DSRMIC_W::new(self) + } + #[doc = "Bit 4 - RXIC"] + #[inline(always)] + #[must_use] + pub fn rxic(&mut self) -> RXIC_W<4> { + RXIC_W::new(self) + } + #[doc = "Bit 5 - TXIC"] + #[inline(always)] + #[must_use] + pub fn txic(&mut self) -> TXIC_W<5> { + TXIC_W::new(self) + } + #[doc = "Bit 6 - RTIC"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W<6> { + RTIC_W::new(self) + } + #[doc = "Bit 7 - FEIC"] + #[inline(always)] + #[must_use] + pub fn feic(&mut self) -> FEIC_W<7> { + FEIC_W::new(self) + } + #[doc = "Bit 8 - PEIC"] + #[inline(always)] + #[must_use] + pub fn peic(&mut self) -> PEIC_W<8> { + PEIC_W::new(self) + } + #[doc = "Bit 9 - BEIC"] + #[inline(always)] + #[must_use] + pub fn beic(&mut self) -> BEIC_W<9> { + BEIC_W::new(self) + } + #[doc = "Bit 10 - OEIC"] + #[inline(always)] + #[must_use] + pub fn oeic(&mut self) -> OEIC_W<10> { + OEIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +pub struct ICR_SPEC; +impl crate::RegisterSpec for ICR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +impl crate::Writable for ICR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for ICR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/ifls.rs b/crates/bcm2711-lpa/src/uart0/ifls.rs new file mode 100644 index 0000000..0cfe8d5 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/ifls.rs @@ -0,0 +1,95 @@ +#[doc = "Register `IFLS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IFLS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXIFLSEL` reader - TXIFLSEL"] +pub type TXIFLSEL_R = crate::FieldReader; +#[doc = "Field `TXIFLSEL` writer - TXIFLSEL"] +pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +#[doc = "Field `RXIFLSEL` reader - RXIFLSEL"] +pub type RXIFLSEL_R = crate::FieldReader; +#[doc = "Field `RXIFLSEL` writer - RXIFLSEL"] +pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - TXIFLSEL"] + #[inline(always)] + pub fn txiflsel(&self) -> TXIFLSEL_R { + TXIFLSEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - RXIFLSEL"] + #[inline(always)] + pub fn rxiflsel(&self) -> RXIFLSEL_R { + RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - TXIFLSEL"] + #[inline(always)] + #[must_use] + pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + TXIFLSEL_W::new(self) + } + #[doc = "Bits 3:5 - RXIFLSEL"] + #[inline(always)] + #[must_use] + pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + RXIFLSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifls](index.html) module"] +pub struct IFLS_SPEC; +impl crate::RegisterSpec for IFLS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ifls::R](R) reader structure"] +impl crate::Readable for IFLS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ifls::W](W) writer structure"] +impl crate::Writable for IFLS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IFLS to value 0"] +impl crate::Resettable for IFLS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/imsc.rs b/crates/bcm2711-lpa/src/uart0/imsc.rs new file mode 100644 index 0000000..1b0fb46 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/imsc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `IMSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IMSC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIMIM` reader - RIMIM"] +pub type RIMIM_R = crate::BitReader; +#[doc = "Field `RIMIM` writer - RIMIM"] +pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `CTSMIM` reader - CTSMIM"] +pub type CTSMIM_R = crate::BitReader; +#[doc = "Field `CTSMIM` writer - CTSMIM"] +pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `DCDMIM` reader - DCDMIM"] +pub type DCDMIM_R = crate::BitReader; +#[doc = "Field `DCDMIM` writer - DCDMIM"] +pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `DSRMIM` reader - DSRMIM"] +pub type DSRMIM_R = crate::BitReader; +#[doc = "Field `DSRMIM` writer - DSRMIM"] +pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `RXIM` reader - RXIM"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `RXIM` writer - RXIM"] +pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `TXIM` reader - TXIM"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `TXIM` writer - TXIM"] +pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `RTIM` reader - RTIM"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `RTIM` writer - RTIM"] +pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `FEIM` reader - FEIM"] +pub type FEIM_R = crate::BitReader; +#[doc = "Field `FEIM` writer - FEIM"] +pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `PEIM` reader - PEIM"] +pub type PEIM_R = crate::BitReader; +#[doc = "Field `PEIM` writer - PEIM"] +pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `BEIM` reader - BEIM"] +pub type BEIM_R = crate::BitReader; +#[doc = "Field `BEIM` writer - BEIM"] +pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `OEIM` reader - OEIM"] +pub type OEIM_R = crate::BitReader; +#[doc = "Field `OEIM` writer - OEIM"] +pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - RIMIM"] + #[inline(always)] + pub fn rimim(&self) -> RIMIM_R { + RIMIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSMIM"] + #[inline(always)] + pub fn ctsmim(&self) -> CTSMIM_R { + CTSMIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDMIM"] + #[inline(always)] + pub fn dcdmim(&self) -> DCDMIM_R { + DCDMIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRMIM"] + #[inline(always)] + pub fn dsrmim(&self) -> DSRMIM_R { + DSRMIM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXIM"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXIM"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTIM"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FEIM"] + #[inline(always)] + pub fn feim(&self) -> FEIM_R { + FEIM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PEIM"] + #[inline(always)] + pub fn peim(&self) -> PEIM_R { + PEIM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BEIM"] + #[inline(always)] + pub fn beim(&self) -> BEIM_R { + BEIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OEIM"] + #[inline(always)] + pub fn oeim(&self) -> OEIM_R { + OEIM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RIMIM"] + #[inline(always)] + #[must_use] + pub fn rimim(&mut self) -> RIMIM_W<0> { + RIMIM_W::new(self) + } + #[doc = "Bit 1 - CTSMIM"] + #[inline(always)] + #[must_use] + pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + CTSMIM_W::new(self) + } + #[doc = "Bit 2 - DCDMIM"] + #[inline(always)] + #[must_use] + pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + DCDMIM_W::new(self) + } + #[doc = "Bit 3 - DSRMIM"] + #[inline(always)] + #[must_use] + pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + DSRMIM_W::new(self) + } + #[doc = "Bit 4 - RXIM"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W<4> { + RXIM_W::new(self) + } + #[doc = "Bit 5 - TXIM"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W<5> { + TXIM_W::new(self) + } + #[doc = "Bit 6 - RTIM"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W<6> { + RTIM_W::new(self) + } + #[doc = "Bit 7 - FEIM"] + #[inline(always)] + #[must_use] + pub fn feim(&mut self) -> FEIM_W<7> { + FEIM_W::new(self) + } + #[doc = "Bit 8 - PEIM"] + #[inline(always)] + #[must_use] + pub fn peim(&mut self) -> PEIM_W<8> { + PEIM_W::new(self) + } + #[doc = "Bit 9 - BEIM"] + #[inline(always)] + #[must_use] + pub fn beim(&mut self) -> BEIM_W<9> { + BEIM_W::new(self) + } + #[doc = "Bit 10 - OEIM"] + #[inline(always)] + #[must_use] + pub fn oeim(&mut self) -> OEIM_W<10> { + OEIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Mask set_Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"] +pub struct IMSC_SPEC; +impl crate::RegisterSpec for IMSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [imsc::R](R) reader structure"] +impl crate::Readable for IMSC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"] +impl crate::Writable for IMSC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMSC to value 0"] +impl crate::Resettable for IMSC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/lcr_h.rs b/crates/bcm2711-lpa/src/uart0/lcr_h.rs new file mode 100644 index 0000000..6e02317 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/lcr_h.rs @@ -0,0 +1,170 @@ +#[doc = "Register `LCR_H` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LCR_H` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BRK` reader - BRK"] +pub type BRK_R = crate::BitReader; +#[doc = "Field `BRK` writer - BRK"] +pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `PEN` reader - PEN"] +pub type PEN_R = crate::BitReader; +#[doc = "Field `PEN` writer - PEN"] +pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `EPS` reader - EPS"] +pub type EPS_R = crate::BitReader; +#[doc = "Field `EPS` writer - EPS"] +pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `STP2` reader - STP2"] +pub type STP2_R = crate::BitReader; +#[doc = "Field `STP2` writer - STP2"] +pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `FEN` reader - FEN"] +pub type FEN_R = crate::BitReader; +#[doc = "Field `FEN` writer - FEN"] +pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `WLEN` reader - WLEN"] +pub type WLEN_R = crate::FieldReader; +#[doc = "Field `WLEN` writer - WLEN"] +pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_H_SPEC, u8, u8, 2, O>; +#[doc = "Field `SPS` reader - SPS"] +pub type SPS_R = crate::BitReader; +#[doc = "Field `SPS` writer - SPS"] +pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - BRK"] + #[inline(always)] + pub fn brk(&self) -> BRK_R { + BRK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PEN"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - EPS"] + #[inline(always)] + pub fn eps(&self) -> EPS_R { + EPS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STP2"] + #[inline(always)] + pub fn stp2(&self) -> STP2_R { + STP2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - FEN"] + #[inline(always)] + pub fn fen(&self) -> FEN_R { + FEN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - WLEN"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - SPS"] + #[inline(always)] + pub fn sps(&self) -> SPS_R { + SPS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - BRK"] + #[inline(always)] + #[must_use] + pub fn brk(&mut self) -> BRK_W<0> { + BRK_W::new(self) + } + #[doc = "Bit 1 - PEN"] + #[inline(always)] + #[must_use] + pub fn pen(&mut self) -> PEN_W<1> { + PEN_W::new(self) + } + #[doc = "Bit 2 - EPS"] + #[inline(always)] + #[must_use] + pub fn eps(&mut self) -> EPS_W<2> { + EPS_W::new(self) + } + #[doc = "Bit 3 - STP2"] + #[inline(always)] + #[must_use] + pub fn stp2(&mut self) -> STP2_W<3> { + STP2_W::new(self) + } + #[doc = "Bit 4 - FEN"] + #[inline(always)] + #[must_use] + pub fn fen(&mut self) -> FEN_W<4> { + FEN_W::new(self) + } + #[doc = "Bits 5:6 - WLEN"] + #[inline(always)] + #[must_use] + pub fn wlen(&mut self) -> WLEN_W<5> { + WLEN_W::new(self) + } + #[doc = "Bit 7 - SPS"] + #[inline(always)] + #[must_use] + pub fn sps(&mut self) -> SPS_W<7> { + SPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_h](index.html) module"] +pub struct LCR_H_SPEC; +impl crate::RegisterSpec for LCR_H_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lcr_h::R](R) reader structure"] +impl crate::Readable for LCR_H_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lcr_h::W](W) writer structure"] +impl crate::Writable for LCR_H_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCR_H to value 0"] +impl crate::Resettable for LCR_H_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/mis.rs b/crates/bcm2711-lpa/src/uart0/mis.rs new file mode 100644 index 0000000..ce802e5 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/mis.rs @@ -0,0 +1,107 @@ +#[doc = "Register `MIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RIMMIS` reader - RIMMIS"] +pub type RIMMIS_R = crate::BitReader; +#[doc = "Field `CTSMMIS` reader - CTSMMIS"] +pub type CTSMMIS_R = crate::BitReader; +#[doc = "Field `DCDMMIS` reader - DCDMMIS"] +pub type DCDMMIS_R = crate::BitReader; +#[doc = "Field `DSRMMIS` reader - DSRMMIS"] +pub type DSRMMIS_R = crate::BitReader; +#[doc = "Field `RXMIS` reader - RXMIS"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `TXMIS` reader - TXMIS"] +pub type TXMIS_R = crate::BitReader; +#[doc = "Field `RTMIS` reader - RTMIS"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `FEMIS` reader - FEMIS"] +pub type FEMIS_R = crate::BitReader; +#[doc = "Field `PEMIS` reader - PEMIS"] +pub type PEMIS_R = crate::BitReader; +#[doc = "Field `BEMIS` reader - BEMIS"] +pub type BEMIS_R = crate::BitReader; +#[doc = "Field `OEMIS` reader - OEMIS"] +pub type OEMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RIMMIS"] + #[inline(always)] + pub fn rimmis(&self) -> RIMMIS_R { + RIMMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSMMIS"] + #[inline(always)] + pub fn ctsmmis(&self) -> CTSMMIS_R { + CTSMMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDMMIS"] + #[inline(always)] + pub fn dcdmmis(&self) -> DCDMMIS_R { + DCDMMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRMMIS"] + #[inline(always)] + pub fn dsrmmis(&self) -> DSRMMIS_R { + DSRMMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXMIS"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXMIS"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTMIS"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FEMIS"] + #[inline(always)] + pub fn femis(&self) -> FEMIS_R { + FEMIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PEMIS"] + #[inline(always)] + pub fn pemis(&self) -> PEMIS_R { + PEMIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BEMIS"] + #[inline(always)] + pub fn bemis(&self) -> BEMIS_R { + BEMIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OEMIS"] + #[inline(always)] + pub fn oemis(&self) -> OEMIS_R { + OEMIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Masked Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"] +pub struct MIS_SPEC; +impl crate::RegisterSpec for MIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mis::R](R) reader structure"] +impl crate::Readable for MIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MIS to value 0"] +impl crate::Resettable for MIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/ris.rs b/crates/bcm2711-lpa/src/uart0/ris.rs new file mode 100644 index 0000000..0ab6b9d --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/ris.rs @@ -0,0 +1,107 @@ +#[doc = "Register `RIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RIRMIS` reader - RIRMIS"] +pub type RIRMIS_R = crate::BitReader; +#[doc = "Field `CTSRMIS` reader - CTSRMIS"] +pub type CTSRMIS_R = crate::BitReader; +#[doc = "Field `DCDRMIS` reader - DCDRMIS"] +pub type DCDRMIS_R = crate::BitReader; +#[doc = "Field `DSRRMIS` reader - DSRRMIS"] +pub type DSRRMIS_R = crate::BitReader; +#[doc = "Field `RXRIS` reader - RXRIS"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `TXRIS` reader - TXRIS"] +pub type TXRIS_R = crate::BitReader; +#[doc = "Field `RTRIS` reader - RTRIS"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `FERIS` reader - FERIS"] +pub type FERIS_R = crate::BitReader; +#[doc = "Field `PERIS` reader - PERIS"] +pub type PERIS_R = crate::BitReader; +#[doc = "Field `BERIS` reader - BERIS"] +pub type BERIS_R = crate::BitReader; +#[doc = "Field `OERIS` reader - OERIS"] +pub type OERIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RIRMIS"] + #[inline(always)] + pub fn rirmis(&self) -> RIRMIS_R { + RIRMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSRMIS"] + #[inline(always)] + pub fn ctsrmis(&self) -> CTSRMIS_R { + CTSRMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDRMIS"] + #[inline(always)] + pub fn dcdrmis(&self) -> DCDRMIS_R { + DCDRMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRRMIS"] + #[inline(always)] + pub fn dsrrmis(&self) -> DSRRMIS_R { + DSRRMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXRIS"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXRIS"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTRIS"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FERIS"] + #[inline(always)] + pub fn feris(&self) -> FERIS_R { + FERIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PERIS"] + #[inline(always)] + pub fn peris(&self) -> PERIS_R { + PERIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BERIS"] + #[inline(always)] + pub fn beris(&self) -> BERIS_R { + BERIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OERIS"] + #[inline(always)] + pub fn oeris(&self) -> OERIS_R { + OERIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](index.html) module"] +pub struct RIS_SPEC; +impl crate::RegisterSpec for RIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ris::R](R) reader structure"] +impl crate::Readable for RIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RIS to value 0"] +impl crate::Resettable for RIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart0/rsr.rs b/crates/bcm2711-lpa/src/uart0/rsr.rs new file mode 100644 index 0000000..90a9e0d --- /dev/null +++ b/crates/bcm2711-lpa/src/uart0/rsr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `RSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FE` reader - FE"] +pub type FE_R = crate::BitReader; +#[doc = "Field `PE` reader - PE"] +pub type PE_R = crate::BitReader; +#[doc = "Field `BE` reader - BE"] +pub type BE_R = crate::BitReader; +#[doc = "Field `OE` reader - OE"] +pub type OE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - FE"] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PE"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BE"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - OE"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +pub struct RSR_SPEC; +impl crate::RegisterSpec for RSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rsr::R](R) reader structure"] +impl crate::Readable for RSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RSR to value 0"] +impl crate::Resettable for RSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1.rs b/crates/bcm2711-lpa/src/uart1.rs new file mode 100644 index 0000000..a87a1e5 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_io: [u8; 0x04], + _reserved_1_ier: [u8; 0x04], + #[doc = "0x08 - Interrupt Identify"] + pub iir: IIR, + #[doc = "0x0c - Line control"] + pub lcr: LCR, + #[doc = "0x10 - Modem Control"] + pub mcr: MCR, + #[doc = "0x14 - Line Status"] + pub lsr: LSR, + #[doc = "0x18 - Modem Status"] + pub msr: MSR, + #[doc = "0x1c - Scratch"] + pub scratch: SCRATCH, + _reserved8: [u8; 0x03], + #[doc = "0x20 - Control"] + pub cntl: CNTL, + #[doc = "0x24 - Status"] + pub stat: STAT, + #[doc = "0x28 - Baudrate"] + pub baud: BAUD, +} +impl RegisterBlock { + #[doc = "0x00 - Lower bits of baudrate when DLAB is set"] + #[inline(always)] + pub const fn baudl(&self) -> &BAUDL { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00 - I/O Data"] + #[inline(always)] + pub const fn io(&self) -> &IO { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x04 - High bits of baudrate when DLAB is set"] + #[inline(always)] + pub const fn baudh(&self) -> &BAUDH { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } + #[doc = "0x04 - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &IER { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } +} +#[doc = "IO (rw) register accessor: an alias for `Reg`"] +pub type IO = crate::Reg; +#[doc = "I/O Data"] +pub mod io; +#[doc = "BAUDL (rw) register accessor: an alias for `Reg`"] +pub type BAUDL = crate::Reg; +#[doc = "Lower bits of baudrate when DLAB is set"] +pub mod baudl; +#[doc = "IER (rw) register accessor: an alias for `Reg`"] +pub type IER = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "BAUDH (rw) register accessor: an alias for `Reg`"] +pub type BAUDH = crate::Reg; +#[doc = "High bits of baudrate when DLAB is set"] +pub mod baudh; +#[doc = "IIR (rw) register accessor: an alias for `Reg`"] +pub type IIR = crate::Reg; +#[doc = "Interrupt Identify"] +pub mod iir; +#[doc = "LCR (rw) register accessor: an alias for `Reg`"] +pub type LCR = crate::Reg; +#[doc = "Line control"] +pub mod lcr; +#[doc = "MCR (rw) register accessor: an alias for `Reg`"] +pub type MCR = crate::Reg; +#[doc = "Modem Control"] +pub mod mcr; +#[doc = "LSR (rw) register accessor: an alias for `Reg`"] +pub type LSR = crate::Reg; +#[doc = "Line Status"] +pub mod lsr; +#[doc = "MSR (rw) register accessor: an alias for `Reg`"] +pub type MSR = crate::Reg; +#[doc = "Modem Status"] +pub mod msr; +#[doc = "SCRATCH (rw) register accessor: an alias for `Reg`"] +pub type SCRATCH = crate::Reg; +#[doc = "Scratch"] +pub mod scratch; +#[doc = "CNTL (rw) register accessor: an alias for `Reg`"] +pub type CNTL = crate::Reg; +#[doc = "Control"] +pub mod cntl; +#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "Baudrate"] +pub mod baud; diff --git a/crates/bcm2711-lpa/src/uart1/baud.rs b/crates/bcm2711-lpa/src/uart1/baud.rs new file mode 100644 index 0000000..088c774 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/baud.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Baudrate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/baudh.rs b/crates/bcm2711-lpa/src/uart1/baudh.rs new file mode 100644 index 0000000..8c30695 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/baudh.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUDH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "High bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudh](index.html) module"] +pub struct BAUDH_SPEC; +impl crate::RegisterSpec for BAUDH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baudh::R](R) reader structure"] +impl crate::Readable for BAUDH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudh::W](W) writer structure"] +impl crate::Writable for BAUDH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUDH to value 0"] +impl crate::Resettable for BAUDH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/baudl.rs b/crates/bcm2711-lpa/src/uart1/baudl.rs new file mode 100644 index 0000000..ca7c9f0 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/baudl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUDL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lower bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudl](index.html) module"] +pub struct BAUDL_SPEC; +impl crate::RegisterSpec for BAUDL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baudl::R](R) reader structure"] +impl crate::Readable for BAUDL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudl::W](W) writer structure"] +impl crate::Writable for BAUDL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUDL to value 0"] +impl crate::Resettable for BAUDL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/cntl.rs b/crates/bcm2711-lpa/src/uart1/cntl.rs new file mode 100644 index 0000000..4125093 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/cntl.rs @@ -0,0 +1,291 @@ +#[doc = "Register `CNTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RX_ENABLE` reader - Enable receive"] +pub type RX_ENABLE_R = crate::BitReader; +#[doc = "Field `RX_ENABLE` writer - Enable receive"] +pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `TX_ENABLE` reader - Enable transmit"] +pub type TX_ENABLE_R = crate::BitReader; +#[doc = "Field `TX_ENABLE` writer - Enable transmit"] +pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `RTS_ENABLE` reader - Enable auto receive flow control with RTS"] +pub type RTS_ENABLE_R = crate::BitReader; +#[doc = "Field `RTS_ENABLE` writer - Enable auto receive flow control with RTS"] +pub type RTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `CTS_ENABLE` reader - Enable auto transmit flow control with CTS"] +pub type CTS_ENABLE_R = crate::BitReader; +#[doc = "Field `CTS_ENABLE` writer - Enable auto transmit flow control with CTS"] +pub type CTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `RTS_FIFO_LEVEL` reader - FIFO level to de-assert RTS"] +pub type RTS_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "FIFO level to de-assert RTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FIFO_LEVEL_A { + #[doc = "0: 3 empty spaces"] + _3EMPTY = 0, + #[doc = "1: 2 empty spaces"] + _2EMPTY = 1, + #[doc = "2: 1 empty spaces"] + _1EMPTY = 2, + #[doc = "3: 4 empty spaces"] + _4EMPTY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FIFO_LEVEL_A) -> Self { + variant as _ + } +} +impl RTS_FIFO_LEVEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FIFO_LEVEL_A { + match self.bits { + 0 => FIFO_LEVEL_A::_3EMPTY, + 1 => FIFO_LEVEL_A::_2EMPTY, + 2 => FIFO_LEVEL_A::_1EMPTY, + 3 => FIFO_LEVEL_A::_4EMPTY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_3EMPTY`"] + #[inline(always)] + pub fn is_3empty(&self) -> bool { + *self == FIFO_LEVEL_A::_3EMPTY + } + #[doc = "Checks if the value of the field is `_2EMPTY`"] + #[inline(always)] + pub fn is_2empty(&self) -> bool { + *self == FIFO_LEVEL_A::_2EMPTY + } + #[doc = "Checks if the value of the field is `_1EMPTY`"] + #[inline(always)] + pub fn is_1empty(&self) -> bool { + *self == FIFO_LEVEL_A::_1EMPTY + } + #[doc = "Checks if the value of the field is `_4EMPTY`"] + #[inline(always)] + pub fn is_4empty(&self) -> bool { + *self == FIFO_LEVEL_A::_4EMPTY + } +} +#[doc = "Field `RTS_FIFO_LEVEL` writer - FIFO level to de-assert RTS"] +pub type RTS_FIFO_LEVEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CNTL_SPEC, u8, FIFO_LEVEL_A, 2, O>; +impl<'a, const O: u8> RTS_FIFO_LEVEL_W<'a, O> { + #[doc = "3 empty spaces"] + #[inline(always)] + pub fn _3empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_3EMPTY) + } + #[doc = "2 empty spaces"] + #[inline(always)] + pub fn _2empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_2EMPTY) + } + #[doc = "1 empty spaces"] + #[inline(always)] + pub fn _1empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_1EMPTY) + } + #[doc = "4 empty spaces"] + #[inline(always)] + pub fn _4empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_4EMPTY) + } +} +#[doc = "Field `RTS_ASSERT` reader - RTS assert level"] +pub use CTS_ASSERT_R as RTS_ASSERT_R; +#[doc = "Field `RTS_ASSERT` writer - RTS assert level"] +pub use CTS_ASSERT_W as RTS_ASSERT_W; +#[doc = "Field `CTS_ASSERT` reader - CTS assert level"] +pub type CTS_ASSERT_R = crate::BitReader; +#[doc = "CTS assert level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ASSERT_LEVEL_A { + #[doc = "0: Assert high"] + HIGH = 0, + #[doc = "1: Assert low"] + LOW = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ASSERT_LEVEL_A) -> Self { + variant as u8 != 0 + } +} +impl CTS_ASSERT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ASSERT_LEVEL_A { + match self.bits { + false => ASSERT_LEVEL_A::HIGH, + true => ASSERT_LEVEL_A::LOW, + } + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == ASSERT_LEVEL_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == ASSERT_LEVEL_A::LOW + } +} +#[doc = "Field `CTS_ASSERT` writer - CTS assert level"] +pub type CTS_ASSERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, ASSERT_LEVEL_A, O>; +impl<'a, const O: u8> CTS_ASSERT_W<'a, O> { + #[doc = "Assert high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(ASSERT_LEVEL_A::HIGH) + } + #[doc = "Assert low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(ASSERT_LEVEL_A::LOW) + } +} +impl R { + #[doc = "Bit 0 - Enable receive"] + #[inline(always)] + pub fn rx_enable(&self) -> RX_ENABLE_R { + RX_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable transmit"] + #[inline(always)] + pub fn tx_enable(&self) -> TX_ENABLE_R { + TX_ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable auto receive flow control with RTS"] + #[inline(always)] + pub fn rts_enable(&self) -> RTS_ENABLE_R { + RTS_ENABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] + #[inline(always)] + pub fn cts_enable(&self) -> CTS_ENABLE_R { + CTS_ENABLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] + #[inline(always)] + pub fn rts_fifo_level(&self) -> RTS_FIFO_LEVEL_R { + RTS_FIFO_LEVEL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - RTS assert level"] + #[inline(always)] + pub fn rts_assert(&self) -> RTS_ASSERT_R { + RTS_ASSERT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS assert level"] + #[inline(always)] + pub fn cts_assert(&self) -> CTS_ASSERT_R { + CTS_ASSERT_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable receive"] + #[inline(always)] + #[must_use] + pub fn rx_enable(&mut self) -> RX_ENABLE_W<0> { + RX_ENABLE_W::new(self) + } + #[doc = "Bit 1 - Enable transmit"] + #[inline(always)] + #[must_use] + pub fn tx_enable(&mut self) -> TX_ENABLE_W<1> { + TX_ENABLE_W::new(self) + } + #[doc = "Bit 2 - Enable auto receive flow control with RTS"] + #[inline(always)] + #[must_use] + pub fn rts_enable(&mut self) -> RTS_ENABLE_W<2> { + RTS_ENABLE_W::new(self) + } + #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] + #[inline(always)] + #[must_use] + pub fn cts_enable(&mut self) -> CTS_ENABLE_W<3> { + CTS_ENABLE_W::new(self) + } + #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] + #[inline(always)] + #[must_use] + pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W<4> { + RTS_FIFO_LEVEL_W::new(self) + } + #[doc = "Bit 6 - RTS assert level"] + #[inline(always)] + #[must_use] + pub fn rts_assert(&mut self) -> RTS_ASSERT_W<6> { + RTS_ASSERT_W::new(self) + } + #[doc = "Bit 7 - CTS assert level"] + #[inline(always)] + #[must_use] + pub fn cts_assert(&mut self) -> CTS_ASSERT_W<7> { + CTS_ASSERT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] +pub struct CNTL_SPEC; +impl crate::RegisterSpec for CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl::R](R) reader structure"] +impl crate::Readable for CNTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] +impl crate::Writable for CNTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL to value 0"] +impl crate::Resettable for CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/ier.rs b/crates/bcm2711-lpa/src/uart1/ier.rs new file mode 100644 index 0000000..450afd5 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/ier.rs @@ -0,0 +1,95 @@ +#[doc = "Register `IER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO is empty"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Transmit FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<1> { + TX_READY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +pub struct IER_SPEC; +impl crate::RegisterSpec for IER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ier::R](R) reader structure"] +impl crate::Readable for IER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +impl crate::Writable for IER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/iir.rs b/crates/bcm2711-lpa/src/uart1/iir.rs new file mode 100644 index 0000000..6f66eac --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/iir.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `nPENDING` reader - No pending interrupt"] +pub type N_PENDING_R = crate::BitReader; +#[doc = "Field `nPENDING` writer - No pending interrupt"] +pub type N_PENDING_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - No pending interrupt"] + #[inline(always)] + pub fn n_pending(&self) -> N_PENDING_R { + N_PENDING_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO is empty"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - No pending interrupt"] + #[inline(always)] + #[must_use] + pub fn n_pending(&mut self) -> N_PENDING_W<0> { + N_PENDING_W::new(self) + } + #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<1> { + DATA_READY_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<2> { + TX_READY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Identify\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iir](index.html) module"] +pub struct IIR_SPEC; +impl crate::RegisterSpec for IIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [iir::R](R) reader structure"] +impl crate::Readable for IIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [iir::W](W) writer structure"] +impl crate::Writable for IIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IIR to value 0xb001"] +impl crate::Resettable for IIR_SPEC { + const RESET_VALUE: Self::Ux = 0xb001; +} diff --git a/crates/bcm2711-lpa/src/uart1/io.rs b/crates/bcm2711-lpa/src/uart1/io.rs new file mode 100644 index 0000000..84cd075 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/io.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - FIFO access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - FIFO access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I/O Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +pub struct IO_SPEC; +impl crate::RegisterSpec for IO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [io::R](R) reader structure"] +impl crate::Readable for IO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +impl crate::Writable for IO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IO to value 0"] +impl crate::Resettable for IO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/lcr.rs b/crates/bcm2711-lpa/src/uart1/lcr.rs new file mode 100644 index 0000000..16b3c2b --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/lcr.rs @@ -0,0 +1,158 @@ +#[doc = "Register `LCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_SIZE` reader - UART word size"] +pub type DATA_SIZE_R = crate::FieldReader; +#[doc = "UART word size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: 7 bit"] + _7BIT = 0, + #[doc = "3: 8 bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::_7BIT), + 3 => Some(MODE_A::_8BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_7BIT`"] + #[inline(always)] + pub fn is_7bit(&self) -> bool { + *self == MODE_A::_7BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == MODE_A::_8BIT + } +} +#[doc = "Field `DATA_SIZE` writer - UART word size"] +pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_SPEC, u8, MODE_A, 2, O>; +impl<'a, const O: u8> DATA_SIZE_W<'a, O> { + #[doc = "7 bit"] + #[inline(always)] + pub fn _7bit(self) -> &'a mut W { + self.variant(MODE_A::_7BIT) + } + #[doc = "8 bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(MODE_A::_8BIT) + } +} +#[doc = "Field `BREAK` reader - Pull TX low continuously to send break"] +pub type BREAK_R = crate::BitReader; +#[doc = "Field `BREAK` writer - Pull TX low continuously to send break"] +pub type BREAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +#[doc = "Field `DLAB` reader - First two registers are baudrate"] +pub type DLAB_R = crate::BitReader; +#[doc = "Field `DLAB` writer - First two registers are baudrate"] +pub type DLAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - UART word size"] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 6 - Pull TX low continuously to send break"] + #[inline(always)] + pub fn break_(&self) -> BREAK_R { + BREAK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - First two registers are baudrate"] + #[inline(always)] + pub fn dlab(&self) -> DLAB_R { + DLAB_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - UART word size"] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W<0> { + DATA_SIZE_W::new(self) + } + #[doc = "Bit 6 - Pull TX low continuously to send break"] + #[inline(always)] + #[must_use] + pub fn break_(&mut self) -> BREAK_W<6> { + BREAK_W::new(self) + } + #[doc = "Bit 7 - First two registers are baudrate"] + #[inline(always)] + #[must_use] + pub fn dlab(&mut self) -> DLAB_W<7> { + DLAB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](index.html) module"] +pub struct LCR_SPEC; +impl crate::RegisterSpec for LCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lcr::R](R) reader structure"] +impl crate::Readable for LCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lcr::W](W) writer structure"] +impl crate::Writable for LCR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCR to value 0"] +impl crate::Resettable for LCR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/lsr.rs b/crates/bcm2711-lpa/src/uart1/lsr.rs new file mode 100644 index 0000000..ba34ba7 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/lsr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `LSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least one byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least one byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] +pub type RX_OVERRUN_R = crate::BitReader; +#[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] +pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - Transmit FIFO has room for at least one byte"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - Transmit FIFO has room for at least one byte"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `TX_IDLE` reader - Transmit FIFO empty and all bits shifted out"] +pub type TX_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IDLE` writer - Transmit FIFO empty and all bits shifted out"] +pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least one byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive FIFO overrun"] + #[inline(always)] + pub fn rx_overrun(&self) -> RX_OVERRUN_R { + RX_OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least one byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Receive FIFO overrun"] + #[inline(always)] + #[must_use] + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<1> { + RX_OVERRUN_W::new(self) + } + #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<5> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] + #[inline(always)] + #[must_use] + pub fn tx_idle(&mut self) -> TX_IDLE_W<6> { + TX_IDLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +pub struct LSR_SPEC; +impl crate::RegisterSpec for LSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lsr::R](R) reader structure"] +impl crate::Readable for LSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +impl crate::Writable for LSR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LSR to value 0"] +impl crate::Resettable for LSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/mcr.rs b/crates/bcm2711-lpa/src/uart1/mcr.rs new file mode 100644 index 0000000..89de0a8 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/mcr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RTS` reader - RTS is low"] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - RTS is low"] +pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - RTS is low"] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - RTS is low"] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W<1> { + RTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Modem Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"] +pub struct MCR_SPEC; +impl crate::RegisterSpec for MCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcr::R](R) reader structure"] +impl crate::Readable for MCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"] +impl crate::Writable for MCR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for MCR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/msr.rs b/crates/bcm2711-lpa/src/uart1/msr.rs new file mode 100644 index 0000000..3960539 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/msr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - CTS is low"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `CTS` writer - CTS is low"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSR_SPEC, bool, O>; +impl R { + #[doc = "Bit 4 - CTS is low"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - CTS is low"] + #[inline(always)] + #[must_use] + pub fn cts(&mut self) -> CTS_W<4> { + CTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Modem Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](index.html) module"] +pub struct MSR_SPEC; +impl crate::RegisterSpec for MSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [msr::R](R) reader structure"] +impl crate::Readable for MSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [msr::W](W) writer structure"] +impl crate::Writable for MSR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MSR to value 0"] +impl crate::Resettable for MSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/scratch.rs b/crates/bcm2711-lpa/src/uart1/scratch.rs new file mode 100644 index 0000000..c85f068 --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/scratch.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCRATCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCRATCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scratch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch](index.html) module"] +pub struct SCRATCH_SPEC; +impl crate::RegisterSpec for SCRATCH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scratch::R](R) reader structure"] +impl crate::Readable for SCRATCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scratch::W](W) writer structure"] +impl crate::Writable for SCRATCH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCRATCH to value 0"] +impl crate::Resettable for SCRATCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/uart1/stat.rs b/crates/bcm2711-lpa/src/uart1/stat.rs new file mode 100644 index 0000000..114015e --- /dev/null +++ b/crates/bcm2711-lpa/src/uart1/stat.rs @@ -0,0 +1,245 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least one symbol"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least one symbol"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO has space for at least one symbol"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO has space for at least one symbol"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_IDLE` reader - Receiver is idle"] +pub type RX_IDLE_R = crate::BitReader; +#[doc = "Field `RX_IDLE` writer - Receiver is idle"] +pub type RX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_IDLE` reader - Transmitter is idle"] +pub type TX_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IDLE` writer - Transmitter is idle"] +pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] +pub type RX_OVERRUN_R = crate::BitReader; +#[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] +pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_FULL` reader - Transmit FIFO is full"] +pub type TX_FULL_R = crate::BitReader; +#[doc = "Field `TX_FULL` writer - Transmit FIFO is full"] +pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RTS_STATUS` reader - RTS state"] +pub type RTS_STATUS_R = crate::BitReader; +#[doc = "Field `RTS_STATUS` writer - RTS state"] +pub type RTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `CTS_STATUS` reader - CTS state"] +pub type CTS_STATUS_R = crate::BitReader; +#[doc = "Field `CTS_STATUS` writer - CTS state"] +pub type CTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - Transmit FIFO is completely empty"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - Transmit FIFO is completely empty"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_DONE` reader - Transmit FIFO is empty and transmitter is idle"] +pub type TX_DONE_R = crate::BitReader; +#[doc = "Field `TX_DONE` writer - Transmit FIFO is empty and transmitter is idle"] +pub type TX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_FIFO_LEVEL` reader - How many entries are filled in the RX FIFO"] +pub type RX_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "Field `RX_FIFO_LEVEL` writer - How many entries are filled in the RX FIFO"] +pub type RX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_FIFO_LEVEL` reader - How many entries are filled in the TX FIFO"] +pub type TX_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "Field `TX_FIFO_LEVEL` writer - How many entries are filled in the TX FIFO"] +pub type TX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least one symbol"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receiver is idle"] + #[inline(always)] + pub fn rx_idle(&self) -> RX_IDLE_R { + RX_IDLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmitter is idle"] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO overrun"] + #[inline(always)] + pub fn rx_overrun(&self) -> RX_OVERRUN_R { + RX_OVERRUN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO is full"] + #[inline(always)] + pub fn tx_full(&self) -> TX_FULL_R { + TX_FULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTS state"] + #[inline(always)] + pub fn rts_status(&self) -> RTS_STATUS_R { + RTS_STATUS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS state"] + #[inline(always)] + pub fn cts_status(&self) -> CTS_STATUS_R { + CTS_STATUS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit FIFO is completely empty"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] + #[inline(always)] + pub fn tx_done(&self) -> TX_DONE_R { + TX_DONE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] + #[inline(always)] + pub fn rx_fifo_level(&self) -> RX_FIFO_LEVEL_R { + RX_FIFO_LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] + #[inline(always)] + pub fn tx_fifo_level(&self) -> TX_FIFO_LEVEL_R { + TX_FIFO_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least one symbol"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<1> { + TX_READY_W::new(self) + } + #[doc = "Bit 2 - Receiver is idle"] + #[inline(always)] + #[must_use] + pub fn rx_idle(&mut self) -> RX_IDLE_W<2> { + RX_IDLE_W::new(self) + } + #[doc = "Bit 3 - Transmitter is idle"] + #[inline(always)] + #[must_use] + pub fn tx_idle(&mut self) -> TX_IDLE_W<3> { + TX_IDLE_W::new(self) + } + #[doc = "Bit 4 - Receive FIFO overrun"] + #[inline(always)] + #[must_use] + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<4> { + RX_OVERRUN_W::new(self) + } + #[doc = "Bit 5 - Transmit FIFO is full"] + #[inline(always)] + #[must_use] + pub fn tx_full(&mut self) -> TX_FULL_W<5> { + TX_FULL_W::new(self) + } + #[doc = "Bit 6 - RTS state"] + #[inline(always)] + #[must_use] + pub fn rts_status(&mut self) -> RTS_STATUS_W<6> { + RTS_STATUS_W::new(self) + } + #[doc = "Bit 7 - CTS state"] + #[inline(always)] + #[must_use] + pub fn cts_status(&mut self) -> CTS_STATUS_W<7> { + CTS_STATUS_W::new(self) + } + #[doc = "Bit 8 - Transmit FIFO is completely empty"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<8> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] + #[inline(always)] + #[must_use] + pub fn tx_done(&mut self) -> TX_DONE_W<9> { + TX_DONE_W::new(self) + } + #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W<16> { + RX_FIFO_LEVEL_W::new(self) + } + #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W<24> { + TX_FIFO_LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device.rs b/crates/bcm2711-lpa/src/usb_otg_device.rs new file mode 100644 index 0000000..8050e54 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device.rs @@ -0,0 +1,179 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS device configuration register"] + pub dcfg: DCFG, + #[doc = "0x04 - OTG_HS device control register"] + pub dctl: DCTL, + #[doc = "0x08 - OTG_HS device status register"] + pub dsts: DSTS, + _reserved3: [u8; 0x04], + #[doc = "0x10 - OTG_HS device IN endpoint common interrupt mask register"] + pub diepmsk: DIEPMSK, + #[doc = "0x14 - OTG_HS device OUT endpoint common interrupt mask register"] + pub doepmsk: DOEPMSK, + #[doc = "0x18 - OTG_HS device all endpoints interrupt register"] + pub daint: DAINT, + #[doc = "0x1c - OTG_HS all endpoints interrupt mask register"] + pub daintmsk: DAINTMSK, + _reserved7: [u8; 0x08], + #[doc = "0x28 - OTG_HS device VBUS discharge time register"] + pub dvbusdis: DVBUSDIS, + #[doc = "0x2c - OTG_HS device VBUS pulsing time register"] + pub dvbuspulse: DVBUSPULSE, + #[doc = "0x30 - OTG_HS Device threshold control register"] + pub dthrctl: DTHRCTL, + #[doc = "0x34 - OTG_HS device IN endpoint FIFO empty interrupt mask register"] + pub diepempmsk: DIEPEMPMSK, + #[doc = "0x38 - OTG_HS device each endpoint interrupt register"] + pub deachint: DEACHINT, + #[doc = "0x3c - OTG_HS device each endpoint interrupt register mask"] + pub deachintmsk: DEACHINTMSK, + #[doc = "0x40 - OTG_HS device each in endpoint-1 interrupt register"] + pub diepeachmsk1: DIEPEACHMSK1, + _reserved14: [u8; 0x3c], + #[doc = "0x80 - OTG_HS device each OUT endpoint-1 interrupt register"] + pub doepeachmsk1: DOEPEACHMSK1, + _reserved15: [u8; 0x7c], + #[doc = "0x100..0x11c - IN Endpoint %s"] + pub in_endpoint0: IN_ENDPOINT, + _reserved16: [u8; 0x04], + #[doc = "0x120..0x13c - IN Endpoint %s"] + pub in_endpoint1: IN_ENDPOINT, + _reserved17: [u8; 0x04], + #[doc = "0x140..0x15c - IN Endpoint %s"] + pub in_endpoint2: IN_ENDPOINT, + _reserved18: [u8; 0x04], + #[doc = "0x160..0x17c - IN Endpoint %s"] + pub in_endpoint3: IN_ENDPOINT, + _reserved19: [u8; 0x04], + #[doc = "0x180..0x19c - IN Endpoint %s"] + pub in_endpoint4: IN_ENDPOINT, + _reserved20: [u8; 0x04], + #[doc = "0x1a0..0x1bc - IN Endpoint %s"] + pub in_endpoint5: IN_ENDPOINT, + _reserved21: [u8; 0x04], + #[doc = "0x1c0..0x1dc - IN Endpoint %s"] + pub in_endpoint6: IN_ENDPOINT, + _reserved22: [u8; 0x04], + #[doc = "0x1e0..0x1fc - IN Endpoint %s"] + pub in_endpoint7: IN_ENDPOINT, + _reserved23: [u8; 0x04], + #[doc = "0x200..0x21c - IN Endpoint %s"] + pub in_endpoint8: IN_ENDPOINT, + _reserved24: [u8; 0x04], + #[doc = "0x220..0x23c - IN Endpoint %s"] + pub in_endpoint9: IN_ENDPOINT, + _reserved25: [u8; 0x04], + #[doc = "0x240..0x25c - IN Endpoint %s"] + pub in_endpoint10: IN_ENDPOINT, + _reserved26: [u8; 0x04], + #[doc = "0x260..0x27c - IN Endpoint %s"] + pub in_endpoint11: IN_ENDPOINT, + _reserved27: [u8; 0x84], + #[doc = "0x300..0x318 - OUT Endpoint %s"] + pub out_endpoint0: OUT_ENDPOINT, + _reserved28: [u8; 0x08], + #[doc = "0x320..0x338 - OUT Endpoint %s"] + pub out_endpoint1: OUT_ENDPOINT, + _reserved29: [u8; 0x08], + #[doc = "0x340..0x358 - OUT Endpoint %s"] + pub out_endpoint2: OUT_ENDPOINT, + _reserved30: [u8; 0x08], + #[doc = "0x360..0x378 - OUT Endpoint %s"] + pub out_endpoint3: OUT_ENDPOINT, + _reserved31: [u8; 0x08], + #[doc = "0x380..0x398 - OUT Endpoint %s"] + pub out_endpoint4: OUT_ENDPOINT, + _reserved32: [u8; 0x08], + #[doc = "0x3a0..0x3b8 - OUT Endpoint %s"] + pub out_endpoint5: OUT_ENDPOINT, + _reserved33: [u8; 0x08], + #[doc = "0x3c0..0x3d8 - OUT Endpoint %s"] + pub out_endpoint6: OUT_ENDPOINT, + _reserved34: [u8; 0x08], + #[doc = "0x3e0..0x3f8 - OUT Endpoint %s"] + pub out_endpoint7: OUT_ENDPOINT, + _reserved35: [u8; 0x08], + #[doc = "0x400..0x418 - OUT Endpoint %s"] + pub out_endpoint8: OUT_ENDPOINT, + _reserved36: [u8; 0x08], + #[doc = "0x420..0x438 - OUT Endpoint %s"] + pub out_endpoint9: OUT_ENDPOINT, + _reserved37: [u8; 0x08], + #[doc = "0x440..0x458 - OUT Endpoint %s"] + pub out_endpoint10: OUT_ENDPOINT, + _reserved38: [u8; 0x08], + #[doc = "0x460..0x478 - OUT Endpoint %s"] + pub out_endpoint11: OUT_ENDPOINT, +} +#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "OTG_HS device configuration register"] +pub mod dcfg; +#[doc = "DCTL (rw) register accessor: an alias for `Reg`"] +pub type DCTL = crate::Reg; +#[doc = "OTG_HS device control register"] +pub mod dctl; +#[doc = "DSTS (r) register accessor: an alias for `Reg`"] +pub type DSTS = crate::Reg; +#[doc = "OTG_HS device status register"] +pub mod dsts; +#[doc = "DIEPMSK (rw) register accessor: an alias for `Reg`"] +pub type DIEPMSK = crate::Reg; +#[doc = "OTG_HS device IN endpoint common interrupt mask register"] +pub mod diepmsk; +#[doc = "DOEPMSK (rw) register accessor: an alias for `Reg`"] +pub type DOEPMSK = crate::Reg; +#[doc = "OTG_HS device OUT endpoint common interrupt mask register"] +pub mod doepmsk; +#[doc = "DAINT (r) register accessor: an alias for `Reg`"] +pub type DAINT = crate::Reg; +#[doc = "OTG_HS device all endpoints interrupt register"] +pub mod daint; +#[doc = "DAINTMSK (rw) register accessor: an alias for `Reg`"] +pub type DAINTMSK = crate::Reg; +#[doc = "OTG_HS all endpoints interrupt mask register"] +pub mod daintmsk; +#[doc = "DVBUSDIS (rw) register accessor: an alias for `Reg`"] +pub type DVBUSDIS = crate::Reg; +#[doc = "OTG_HS device VBUS discharge time register"] +pub mod dvbusdis; +#[doc = "DVBUSPULSE (rw) register accessor: an alias for `Reg`"] +pub type DVBUSPULSE = crate::Reg; +#[doc = "OTG_HS device VBUS pulsing time register"] +pub mod dvbuspulse; +#[doc = "DTHRCTL (rw) register accessor: an alias for `Reg`"] +pub type DTHRCTL = crate::Reg; +#[doc = "OTG_HS Device threshold control register"] +pub mod dthrctl; +#[doc = "DIEPEMPMSK (rw) register accessor: an alias for `Reg`"] +pub type DIEPEMPMSK = crate::Reg; +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register"] +pub mod diepempmsk; +#[doc = "DEACHINT (rw) register accessor: an alias for `Reg`"] +pub type DEACHINT = crate::Reg; +#[doc = "OTG_HS device each endpoint interrupt register"] +pub mod deachint; +#[doc = "DEACHINTMSK (rw) register accessor: an alias for `Reg`"] +pub type DEACHINTMSK = crate::Reg; +#[doc = "OTG_HS device each endpoint interrupt register mask"] +pub mod deachintmsk; +#[doc = "DIEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +pub type DIEPEACHMSK1 = crate::Reg; +#[doc = "OTG_HS device each in endpoint-1 interrupt register"] +pub mod diepeachmsk1; +#[doc = "DOEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +pub type DOEPEACHMSK1 = crate::Reg; +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register"] +pub mod doepeachmsk1; +#[doc = "IN Endpoint %s"] +pub use self::in_endpoint::IN_ENDPOINT; +#[doc = r"Cluster"] +#[doc = "IN Endpoint %s"] +pub mod in_endpoint; +#[doc = "OUT Endpoint %s"] +pub use self::out_endpoint::OUT_ENDPOINT; +#[doc = r"Cluster"] +#[doc = "OUT Endpoint %s"] +pub mod out_endpoint; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/daint.rs b/crates/bcm2711-lpa/src/usb_otg_device/daint.rs new file mode 100644 index 0000000..14c25b3 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/daint.rs @@ -0,0 +1,44 @@ +#[doc = "Register `DAINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IEPINT` reader - IN endpoint interrupt bits"] +pub type IEPINT_R = crate::FieldReader; +#[doc = "Field `OEPINT` reader - OUT endpoint interrupt bits"] +pub type OEPINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - IN endpoint interrupt bits"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - OUT endpoint interrupt bits"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "OTG_HS device all endpoints interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](index.html) module"] +pub struct DAINT_SPEC; +impl crate::RegisterSpec for DAINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [daint::R](R) reader structure"] +impl crate::Readable for DAINT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DAINT to value 0"] +impl crate::Resettable for DAINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs new file mode 100644 index 0000000..bf7c858 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DAINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEPM` reader - IN EP interrupt mask bits"] +pub type IEPM_R = crate::FieldReader; +#[doc = "Field `IEPM` writer - IN EP interrupt mask bits"] +pub type IEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +#[doc = "Field `OEPM` reader - OUT EP interrupt mask bits"] +pub type OEPM_R = crate::FieldReader; +#[doc = "Field `OEPM` writer - OUT EP interrupt mask bits"] +pub type OEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN EP interrupt mask bits"] + #[inline(always)] + pub fn iepm(&self) -> IEPM_R { + IEPM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] + #[inline(always)] + pub fn oepm(&self) -> OEPM_R { + OEPM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN EP interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn iepm(&mut self) -> IEPM_W<0> { + IEPM_W::new(self) + } + #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn oepm(&mut self) -> OEPM_W<16> { + OEPM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS all endpoints interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](index.html) module"] +pub struct DAINTMSK_SPEC; +impl crate::RegisterSpec for DAINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [daintmsk::R](R) reader structure"] +impl crate::Readable for DAINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [daintmsk::W](W) writer structure"] +impl crate::Writable for DAINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAINTMSK to value 0"] +impl crate::Resettable for DAINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs b/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs new file mode 100644 index 0000000..ad6ef16 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSPD` reader - Device speed"] +pub type DSPD_R = crate::FieldReader; +#[doc = "Field `DSPD` writer - Device speed"] +pub type DSPD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `NZLSOHSK` reader - Nonzero-length status OUT handshake"] +pub type NZLSOHSK_R = crate::BitReader; +#[doc = "Field `NZLSOHSK` writer - Nonzero-length status OUT handshake"] +pub type NZLSOHSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCFG_SPEC, bool, O>; +#[doc = "Field `DAD` reader - Device address"] +pub type DAD_R = crate::FieldReader; +#[doc = "Field `DAD` writer - Device address"] +pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 7, O>; +#[doc = "Field `PFIVL` reader - Periodic (micro)frame interval"] +pub type PFIVL_R = crate::FieldReader; +#[doc = "Field `PFIVL` writer - Periodic (micro)frame interval"] +pub type PFIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `PERSCHIVL` reader - Periodic scheduling interval"] +pub type PERSCHIVL_R = crate::FieldReader; +#[doc = "Field `PERSCHIVL` writer - Periodic scheduling interval"] +pub type PERSCHIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:1 - Device speed"] + #[inline(always)] + pub fn dspd(&self) -> DSPD_R { + DSPD_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Nonzero-length status OUT handshake"] + #[inline(always)] + pub fn nzlsohsk(&self) -> NZLSOHSK_R { + NZLSOHSK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:10 - Device address"] + #[inline(always)] + pub fn dad(&self) -> DAD_R { + DAD_R::new(((self.bits >> 4) & 0x7f) as u8) + } + #[doc = "Bits 11:12 - Periodic (micro)frame interval"] + #[inline(always)] + pub fn pfivl(&self) -> PFIVL_R { + PFIVL_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bits 24:25 - Periodic scheduling interval"] + #[inline(always)] + pub fn perschivl(&self) -> PERSCHIVL_R { + PERSCHIVL_R::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Device speed"] + #[inline(always)] + #[must_use] + pub fn dspd(&mut self) -> DSPD_W<0> { + DSPD_W::new(self) + } + #[doc = "Bit 2 - Nonzero-length status OUT handshake"] + #[inline(always)] + #[must_use] + pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<2> { + NZLSOHSK_W::new(self) + } + #[doc = "Bits 4:10 - Device address"] + #[inline(always)] + #[must_use] + pub fn dad(&mut self) -> DAD_W<4> { + DAD_W::new(self) + } + #[doc = "Bits 11:12 - Periodic (micro)frame interval"] + #[inline(always)] + #[must_use] + pub fn pfivl(&mut self) -> PFIVL_W<11> { + PFIVL_W::new(self) + } + #[doc = "Bits 24:25 - Periodic scheduling interval"] + #[inline(always)] + #[must_use] + pub fn perschivl(&mut self) -> PERSCHIVL_W<24> { + PERSCHIVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCFG to value 0x0220_0000"] +impl crate::Resettable for DCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_0000; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs b/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs new file mode 100644 index 0000000..ed73ebd --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs @@ -0,0 +1,171 @@ +#[doc = "Register `DCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RWUSIG` reader - Remote wakeup signaling"] +pub type RWUSIG_R = crate::BitReader; +#[doc = "Field `RWUSIG` writer - Remote wakeup signaling"] +pub type RWUSIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `SDIS` reader - Soft disconnect"] +pub type SDIS_R = crate::BitReader; +#[doc = "Field `SDIS` writer - Soft disconnect"] +pub type SDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `GINSTS` reader - Global IN NAK status"] +pub type GINSTS_R = crate::BitReader; +#[doc = "Field `GONSTS` reader - Global OUT NAK status"] +pub type GONSTS_R = crate::BitReader; +#[doc = "Field `TCTL` reader - Test control"] +pub type TCTL_R = crate::FieldReader; +#[doc = "Field `TCTL` writer - Test control"] +pub type TCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTL_SPEC, u8, u8, 3, O>; +#[doc = "Field `SGINAK` writer - Set global IN NAK"] +pub type SGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `CGINAK` writer - Clear global IN NAK"] +pub type CGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `SGONAK` writer - Set global OUT NAK"] +pub type SGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `CGONAK` writer - Clear global OUT NAK"] +pub type CGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `POPRGDNE` reader - Power-on programming done"] +pub type POPRGDNE_R = crate::BitReader; +#[doc = "Field `POPRGDNE` writer - Power-on programming done"] +pub type POPRGDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Remote wakeup signaling"] + #[inline(always)] + pub fn rwusig(&self) -> RWUSIG_R { + RWUSIG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Soft disconnect"] + #[inline(always)] + pub fn sdis(&self) -> SDIS_R { + SDIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Global IN NAK status"] + #[inline(always)] + pub fn ginsts(&self) -> GINSTS_R { + GINSTS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Global OUT NAK status"] + #[inline(always)] + pub fn gonsts(&self) -> GONSTS_R { + GONSTS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Test control"] + #[inline(always)] + pub fn tctl(&self) -> TCTL_R { + TCTL_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 11 - Power-on programming done"] + #[inline(always)] + pub fn poprgdne(&self) -> POPRGDNE_R { + POPRGDNE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remote wakeup signaling"] + #[inline(always)] + #[must_use] + pub fn rwusig(&mut self) -> RWUSIG_W<0> { + RWUSIG_W::new(self) + } + #[doc = "Bit 1 - Soft disconnect"] + #[inline(always)] + #[must_use] + pub fn sdis(&mut self) -> SDIS_W<1> { + SDIS_W::new(self) + } + #[doc = "Bits 4:6 - Test control"] + #[inline(always)] + #[must_use] + pub fn tctl(&mut self) -> TCTL_W<4> { + TCTL_W::new(self) + } + #[doc = "Bit 7 - Set global IN NAK"] + #[inline(always)] + #[must_use] + pub fn sginak(&mut self) -> SGINAK_W<7> { + SGINAK_W::new(self) + } + #[doc = "Bit 8 - Clear global IN NAK"] + #[inline(always)] + #[must_use] + pub fn cginak(&mut self) -> CGINAK_W<8> { + CGINAK_W::new(self) + } + #[doc = "Bit 9 - Set global OUT NAK"] + #[inline(always)] + #[must_use] + pub fn sgonak(&mut self) -> SGONAK_W<9> { + SGONAK_W::new(self) + } + #[doc = "Bit 10 - Clear global OUT NAK"] + #[inline(always)] + #[must_use] + pub fn cgonak(&mut self) -> CGONAK_W<10> { + CGONAK_W::new(self) + } + #[doc = "Bit 11 - Power-on programming done"] + #[inline(always)] + #[must_use] + pub fn poprgdne(&mut self) -> POPRGDNE_W<11> { + POPRGDNE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](index.html) module"] +pub struct DCTL_SPEC; +impl crate::RegisterSpec for DCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dctl::R](R) reader structure"] +impl crate::Readable for DCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dctl::W](W) writer structure"] +impl crate::Writable for DCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCTL to value 0"] +impl crate::Resettable for DCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs b/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs new file mode 100644 index 0000000..b2e2a0b --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEACHINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEACHINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEP1INT` reader - IN endpoint 1interrupt bit"] +pub type IEP1INT_R = crate::BitReader; +#[doc = "Field `IEP1INT` writer - IN endpoint 1interrupt bit"] +pub type IEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +#[doc = "Field `OEP1INT` reader - OUT endpoint 1 interrupt bit"] +pub type OEP1INT_R = crate::BitReader; +#[doc = "Field `OEP1INT` writer - OUT endpoint 1 interrupt bit"] +pub type OEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - IN endpoint 1interrupt bit"] + #[inline(always)] + pub fn iep1int(&self) -> IEP1INT_R { + IEP1INT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] + #[inline(always)] + pub fn oep1int(&self) -> OEP1INT_R { + OEP1INT_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - IN endpoint 1interrupt bit"] + #[inline(always)] + #[must_use] + pub fn iep1int(&mut self) -> IEP1INT_W<1> { + IEP1INT_W::new(self) + } + #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] + #[inline(always)] + #[must_use] + pub fn oep1int(&mut self) -> OEP1INT_W<17> { + OEP1INT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each endpoint interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachint](index.html) module"] +pub struct DEACHINT_SPEC; +impl crate::RegisterSpec for DEACHINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deachint::R](R) reader structure"] +impl crate::Readable for DEACHINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [deachint::W](W) writer structure"] +impl crate::Writable for DEACHINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEACHINT to value 0"] +impl crate::Resettable for DEACHINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs new file mode 100644 index 0000000..635cecf --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEACHINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEACHINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEP1INTM` reader - IN Endpoint 1 interrupt mask bit"] +pub type IEP1INTM_R = crate::BitReader; +#[doc = "Field `IEP1INTM` writer - IN Endpoint 1 interrupt mask bit"] +pub type IEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +#[doc = "Field `OEP1INTM` reader - OUT Endpoint 1 interrupt mask bit"] +pub type OEP1INTM_R = crate::BitReader; +#[doc = "Field `OEP1INTM` writer - OUT Endpoint 1 interrupt mask bit"] +pub type OEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] + #[inline(always)] + pub fn iep1intm(&self) -> IEP1INTM_R { + IEP1INTM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] + #[inline(always)] + pub fn oep1intm(&self) -> OEP1INTM_R { + OEP1INTM_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] + #[inline(always)] + #[must_use] + pub fn iep1intm(&mut self) -> IEP1INTM_W<1> { + IEP1INTM_W::new(self) + } + #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] + #[inline(always)] + #[must_use] + pub fn oep1intm(&mut self) -> OEP1INTM_W<17> { + OEP1INTM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each endpoint interrupt register mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachintmsk](index.html) module"] +pub struct DEACHINTMSK_SPEC; +impl crate::RegisterSpec for DEACHINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deachintmsk::R](R) reader structure"] +impl crate::Readable for DEACHINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [deachintmsk::W](W) writer structure"] +impl crate::Writable for DEACHINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEACHINTMSK to value 0"] +impl crate::Resettable for DEACHINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs b/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs new file mode 100644 index 0000000..6e00947 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs @@ -0,0 +1,200 @@ +#[doc = "Register `DIEPEACHMSK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPEACHMSK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - FIFO underrun mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - FIFO underrun mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<13> { + NAKM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepeachmsk1](index.html) module"] +pub struct DIEPEACHMSK1_SPEC; +impl crate::RegisterSpec for DIEPEACHMSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepeachmsk1::R](R) reader structure"] +impl crate::Readable for DIEPEACHMSK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepeachmsk1::W](W) writer structure"] +impl crate::Writable for DIEPEACHMSK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPEACHMSK1 to value 0"] +impl crate::Resettable for DIEPEACHMSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs new file mode 100644 index 0000000..8e5b978 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs @@ -0,0 +1,81 @@ +#[doc = "Register `DIEPEMPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPEMPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXFEM` reader - IN EP Tx FIFO empty interrupt mask bits"] +pub type INEPTXFEM_R = crate::FieldReader; +#[doc = "Field `INEPTXFEM` writer - IN EP Tx FIFO empty interrupt mask bits"] +pub type INEPTXFEM_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, DIEPEMPMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] + #[inline(always)] + pub fn ineptxfem(&self) -> INEPTXFEM_R { + INEPTXFEM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn ineptxfem(&mut self) -> INEPTXFEM_W<0> { + INEPTXFEM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](index.html) module"] +pub struct DIEPEMPMSK_SPEC; +impl crate::RegisterSpec for DIEPEMPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepempmsk::R](R) reader structure"] +impl crate::Readable for DIEPEMPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepempmsk::W](W) writer structure"] +impl crate::Writable for DIEPEMPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPEMPMSK to value 0"] +impl crate::Resettable for DIEPEMPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs new file mode 100644 index 0000000..6411ce9 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs @@ -0,0 +1,185 @@ +#[doc = "Register `DIEPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - FIFO underrun mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - FIFO underrun mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"] +pub struct DIEPMSK_SPEC; +impl crate::RegisterSpec for DIEPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepmsk::R](R) reader structure"] +impl crate::Readable for DIEPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"] +impl crate::Writable for DIEPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPMSK to value 0"] +impl crate::Resettable for DIEPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs b/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs new file mode 100644 index 0000000..31a5ab1 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs @@ -0,0 +1,230 @@ +#[doc = "Register `DOEPEACHMSK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPEACHMSK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - OUT packet error mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - OUT packet error mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BERRM` reader - Bubble error interrupt mask"] +pub type BERRM_R = crate::BitReader; +#[doc = "Field `BERRM` writer - Bubble error interrupt mask"] +pub type BERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NYETM` reader - NYET interrupt mask"] +pub type NYETM_R = crate::BitReader; +#[doc = "Field `NYETM` writer - NYET interrupt mask"] +pub type NYETM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Bubble error interrupt mask"] + #[inline(always)] + pub fn berrm(&self) -> BERRM_R { + BERRM_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NYET interrupt mask"] + #[inline(always)] + pub fn nyetm(&self) -> NYETM_R { + NYETM_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Bit 12 - Bubble error interrupt mask"] + #[inline(always)] + #[must_use] + pub fn berrm(&mut self) -> BERRM_W<12> { + BERRM_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<13> { + NAKM_W::new(self) + } + #[doc = "Bit 14 - NYET interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nyetm(&mut self) -> NYETM_W<14> { + NYETM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepeachmsk1](index.html) module"] +pub struct DOEPEACHMSK1_SPEC; +impl crate::RegisterSpec for DOEPEACHMSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepeachmsk1::R](R) reader structure"] +impl crate::Readable for DOEPEACHMSK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepeachmsk1::W](W) writer structure"] +impl crate::Writable for DOEPEACHMSK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPEACHMSK1 to value 0"] +impl crate::Resettable for DOEPEACHMSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs new file mode 100644 index 0000000..46e5ca8 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs @@ -0,0 +1,170 @@ +#[doc = "Register `DOEPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `STUPM` reader - SETUP phase done mask"] +pub type STUPM_R = crate::BitReader; +#[doc = "Field `STUPM` writer - SETUP phase done mask"] +pub type STUPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `OTEPDM` reader - OUT token received when endpoint disabled mask"] +pub type OTEPDM_R = crate::BitReader; +#[doc = "Field `OTEPDM` writer - OUT token received when endpoint disabled mask"] +pub type OTEPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received mask"] +pub type B2BSTUP_R = crate::BitReader; +#[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received mask"] +pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `OPEM` reader - OUT packet error mask"] +pub type OPEM_R = crate::BitReader; +#[doc = "Field `OPEM` writer - OUT packet error mask"] +pub type OPEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `BOIM` reader - BNA interrupt mask"] +pub type BOIM_R = crate::BitReader; +#[doc = "Field `BOIM` writer - BNA interrupt mask"] +pub type BOIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - SETUP phase done mask"] + #[inline(always)] + pub fn stupm(&self) -> STUPM_R { + STUPM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] + #[inline(always)] + pub fn otepdm(&self) -> OTEPDM_R { + OTEPDM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] + #[inline(always)] + pub fn b2bstup(&self) -> B2BSTUP_R { + B2BSTUP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + pub fn opem(&self) -> OPEM_R { + OPEM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn boim(&self) -> BOIM_R { + BOIM_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - SETUP phase done mask"] + #[inline(always)] + #[must_use] + pub fn stupm(&mut self) -> STUPM_W<3> { + STUPM_W::new(self) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] + #[inline(always)] + #[must_use] + pub fn otepdm(&mut self) -> OTEPDM_W<4> { + OTEPDM_W::new(self) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] + #[inline(always)] + #[must_use] + pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + B2BSTUP_W::new(self) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + #[must_use] + pub fn opem(&mut self) -> OPEM_W<8> { + OPEM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn boim(&mut self) -> BOIM_W<9> { + BOIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](index.html) module"] +pub struct DOEPMSK_SPEC; +impl crate::RegisterSpec for DOEPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepmsk::R](R) reader structure"] +impl crate::Readable for DOEPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepmsk::W](W) writer structure"] +impl crate::Writable for DOEPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPMSK to value 0"] +impl crate::Resettable for DOEPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs b/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs new file mode 100644 index 0000000..ddf0900 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs @@ -0,0 +1,58 @@ +#[doc = "Register `DSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUSPSTS` reader - Suspend status"] +pub type SUSPSTS_R = crate::BitReader; +#[doc = "Field `ENUMSPD` reader - Enumerated speed"] +pub type ENUMSPD_R = crate::FieldReader; +#[doc = "Field `EERR` reader - Erratic error"] +pub type EERR_R = crate::BitReader; +#[doc = "Field `FNSOF` reader - Frame number of the received SOF"] +pub type FNSOF_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Suspend status"] + #[inline(always)] + pub fn suspsts(&self) -> SUSPSTS_R { + SUSPSTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Enumerated speed"] + #[inline(always)] + pub fn enumspd(&self) -> ENUMSPD_R { + ENUMSPD_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Erratic error"] + #[inline(always)] + pub fn eerr(&self) -> EERR_R { + EERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:21 - Frame number of the received SOF"] + #[inline(always)] + pub fn fnsof(&self) -> FNSOF_R { + FNSOF_R::new(((self.bits >> 8) & 0x3fff) as u16) + } +} +#[doc = "OTG_HS device status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](index.html) module"] +pub struct DSTS_SPEC; +impl crate::RegisterSpec for DSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dsts::R](R) reader structure"] +impl crate::Readable for DSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DSTS to value 0x10"] +impl crate::Resettable for DSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs b/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs new file mode 100644 index 0000000..ea85092 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DTHRCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DTHRCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NONISOTHREN` reader - Nonisochronous IN endpoints threshold enable"] +pub type NONISOTHREN_R = crate::BitReader; +#[doc = "Field `NONISOTHREN` writer - Nonisochronous IN endpoints threshold enable"] +pub type NONISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `ISOTHREN` reader - ISO IN endpoint threshold enable"] +pub type ISOTHREN_R = crate::BitReader; +#[doc = "Field `ISOTHREN` writer - ISO IN endpoint threshold enable"] +pub type ISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `TXTHRLEN` reader - Transmit threshold length"] +pub type TXTHRLEN_R = crate::FieldReader; +#[doc = "Field `TXTHRLEN` writer - Transmit threshold length"] +pub type TXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +#[doc = "Field `RXTHREN` reader - Receive threshold enable"] +pub type RXTHREN_R = crate::BitReader; +#[doc = "Field `RXTHREN` writer - Receive threshold enable"] +pub type RXTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `RXTHRLEN` reader - Receive threshold length"] +pub type RXTHRLEN_R = crate::FieldReader; +#[doc = "Field `RXTHRLEN` writer - Receive threshold length"] +pub type RXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +#[doc = "Field `ARPEN` reader - Arbiter parking enable"] +pub type ARPEN_R = crate::BitReader; +#[doc = "Field `ARPEN` writer - Arbiter parking enable"] +pub type ARPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] + #[inline(always)] + pub fn nonisothren(&self) -> NONISOTHREN_R { + NONISOTHREN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ISO IN endpoint threshold enable"] + #[inline(always)] + pub fn isothren(&self) -> ISOTHREN_R { + ISOTHREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:10 - Transmit threshold length"] + #[inline(always)] + pub fn txthrlen(&self) -> TXTHRLEN_R { + TXTHRLEN_R::new(((self.bits >> 2) & 0x01ff) as u16) + } + #[doc = "Bit 16 - Receive threshold enable"] + #[inline(always)] + pub fn rxthren(&self) -> RXTHREN_R { + RXTHREN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:25 - Receive threshold length"] + #[inline(always)] + pub fn rxthrlen(&self) -> RXTHRLEN_R { + RXTHRLEN_R::new(((self.bits >> 17) & 0x01ff) as u16) + } + #[doc = "Bit 27 - Arbiter parking enable"] + #[inline(always)] + pub fn arpen(&self) -> ARPEN_R { + ARPEN_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] + #[inline(always)] + #[must_use] + pub fn nonisothren(&mut self) -> NONISOTHREN_W<0> { + NONISOTHREN_W::new(self) + } + #[doc = "Bit 1 - ISO IN endpoint threshold enable"] + #[inline(always)] + #[must_use] + pub fn isothren(&mut self) -> ISOTHREN_W<1> { + ISOTHREN_W::new(self) + } + #[doc = "Bits 2:10 - Transmit threshold length"] + #[inline(always)] + #[must_use] + pub fn txthrlen(&mut self) -> TXTHRLEN_W<2> { + TXTHRLEN_W::new(self) + } + #[doc = "Bit 16 - Receive threshold enable"] + #[inline(always)] + #[must_use] + pub fn rxthren(&mut self) -> RXTHREN_W<16> { + RXTHREN_W::new(self) + } + #[doc = "Bits 17:25 - Receive threshold length"] + #[inline(always)] + #[must_use] + pub fn rxthrlen(&mut self) -> RXTHRLEN_W<17> { + RXTHRLEN_W::new(self) + } + #[doc = "Bit 27 - Arbiter parking enable"] + #[inline(always)] + #[must_use] + pub fn arpen(&mut self) -> ARPEN_W<27> { + ARPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Device threshold control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](index.html) module"] +pub struct DTHRCTL_SPEC; +impl crate::RegisterSpec for DTHRCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dthrctl::R](R) reader structure"] +impl crate::Readable for DTHRCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dthrctl::W](W) writer structure"] +impl crate::Writable for DTHRCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DTHRCTL to value 0"] +impl crate::Resettable for DTHRCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs b/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs new file mode 100644 index 0000000..403e00a --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DVBUSDIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DVBUSDIS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VBUSDT` reader - Device VBUS discharge time"] +pub type VBUSDT_R = crate::FieldReader; +#[doc = "Field `VBUSDT` writer - Device VBUS discharge time"] +pub type VBUSDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSDIS_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Device VBUS discharge time"] + #[inline(always)] + pub fn vbusdt(&self) -> VBUSDT_R { + VBUSDT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Device VBUS discharge time"] + #[inline(always)] + #[must_use] + pub fn vbusdt(&mut self) -> VBUSDT_W<0> { + VBUSDT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device VBUS discharge time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](index.html) module"] +pub struct DVBUSDIS_SPEC; +impl crate::RegisterSpec for DVBUSDIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dvbusdis::R](R) reader structure"] +impl crate::Readable for DVBUSDIS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dvbusdis::W](W) writer structure"] +impl crate::Writable for DVBUSDIS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DVBUSDIS to value 0x17d7"] +impl crate::Resettable for DVBUSDIS_SPEC { + const RESET_VALUE: Self::Ux = 0x17d7; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs b/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs new file mode 100644 index 0000000..4871f7b --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DVBUSPULSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DVBUSPULSE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DVBUSP` reader - Device VBUS pulsing time"] +pub type DVBUSP_R = crate::FieldReader; +#[doc = "Field `DVBUSP` writer - Device VBUS pulsing time"] +pub type DVBUSP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSPULSE_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Device VBUS pulsing time"] + #[inline(always)] + pub fn dvbusp(&self) -> DVBUSP_R { + DVBUSP_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Device VBUS pulsing time"] + #[inline(always)] + #[must_use] + pub fn dvbusp(&mut self) -> DVBUSP_W<0> { + DVBUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device VBUS pulsing time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](index.html) module"] +pub struct DVBUSPULSE_SPEC; +impl crate::RegisterSpec for DVBUSPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dvbuspulse::R](R) reader structure"] +impl crate::Readable for DVBUSPULSE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](W) writer structure"] +impl crate::Writable for DVBUSPULSE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DVBUSPULSE to value 0x05b8"] +impl crate::Resettable for DVBUSPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x05b8; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs new file mode 100644 index 0000000..5fd5349 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs @@ -0,0 +1,36 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct IN_ENDPOINT { + #[doc = "0x00 - Control"] + pub diepctl0: DIEPCTL0, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Interrupt"] + pub diepint: DIEPINT, + _reserved2: [u8; 0x04], + #[doc = "0x10 - Transfer size"] + pub dieptsiz: DIEPTSIZ, + #[doc = "0x14 - DMA address"] + pub diepdma: DIEPDMA, + #[doc = "0x18 - Transmit FIFO status"] + pub dtxfsts: DTXFSTS, +} +#[doc = "DIEPCTL0 (rw) register accessor: an alias for `Reg`"] +pub type DIEPCTL0 = crate::Reg; +#[doc = "Control"] +pub mod diepctl0; +#[doc = "DIEPINT (rw) register accessor: an alias for `Reg`"] +pub type DIEPINT = crate::Reg; +#[doc = "Interrupt"] +pub mod diepint; +#[doc = "DIEPTSIZ (rw) register accessor: an alias for `Reg`"] +pub type DIEPTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod dieptsiz; +#[doc = "DIEPDMA (rw) register accessor: an alias for `Reg`"] +pub type DIEPDMA = crate::Reg; +#[doc = "DMA address"] +pub mod diepdma; +#[doc = "DTXFSTS (r) register accessor: an alias for `Reg`"] +pub type DTXFSTS = crate::Reg; +#[doc = "Transmit FIFO status"] +pub mod dtxfsts; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs new file mode 100644 index 0000000..b8fa051 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs @@ -0,0 +1,216 @@ +#[doc = "Register `DIEPCTL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPCTL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `MPSIZ` writer - Maximum packet size"] +pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u16, u16, 11, O>; +#[doc = "Field `USBAEP` reader - USB active endpoint"] +pub type USBAEP_R = crate::BitReader; +#[doc = "Field `USBAEP` writer - USB active endpoint"] +pub type USBAEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EONUM_DPID` reader - Even/odd frame"] +pub type EONUM_DPID_R = crate::BitReader; +#[doc = "Field `NAKSTS` reader - NAK status"] +pub type NAKSTS_R = crate::BitReader; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `EPTYP` writer - Endpoint type"] +pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 2, O>; +#[doc = "Field `Stall` reader - STALL handshake"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `Stall` writer - STALL handshake"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `TXFNUM` reader - TxFIFO number"] +pub type TXFNUM_R = crate::FieldReader; +#[doc = "Field `TXFNUM` writer - TxFIFO number"] +pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `CNAK` writer - Clear NAK"] +pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SNAK` writer - Set NAK"] +pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SD0PID_SEVNFRM` writer - Set DATA0 PID"] +pub type SD0PID_SEVNFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SODDFRM` writer - Set odd frame"] +pub type SODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EPDIS` reader - Endpoint disable"] +pub type EPDIS_R = crate::BitReader; +#[doc = "Field `EPDIS` writer - Endpoint disable"] +pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EPENA` reader - Endpoint enable"] +pub type EPENA_R = crate::BitReader; +#[doc = "Field `EPENA` writer - Endpoint enable"] +pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + pub fn usbaep(&self) -> USBAEP_R { + USBAEP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Even/odd frame"] + #[inline(always)] + pub fn eonum_dpid(&self) -> EONUM_DPID_R { + EONUM_DPID_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NAK status"] + #[inline(always)] + pub fn naksts(&self) -> NAKSTS_R { + NAKSTS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:25 - TxFIFO number"] + #[inline(always)] + pub fn txfnum(&self) -> TXFNUM_R { + TXFNUM_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + pub fn epdis(&self) -> EPDIS_R { + EPDIS_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + pub fn epena(&self) -> EPENA_R { + EPENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + #[must_use] + pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + MPSIZ_W::new(self) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + #[must_use] + pub fn usbaep(&mut self) -> USBAEP_W<15> { + USBAEP_W::new(self) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + #[must_use] + pub fn eptyp(&mut self) -> EPTYP_W<18> { + EPTYP_W::new(self) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<21> { + STALL_W::new(self) + } + #[doc = "Bits 22:25 - TxFIFO number"] + #[inline(always)] + #[must_use] + pub fn txfnum(&mut self) -> TXFNUM_W<22> { + TXFNUM_W::new(self) + } + #[doc = "Bit 26 - Clear NAK"] + #[inline(always)] + #[must_use] + pub fn cnak(&mut self) -> CNAK_W<26> { + CNAK_W::new(self) + } + #[doc = "Bit 27 - Set NAK"] + #[inline(always)] + #[must_use] + pub fn snak(&mut self) -> SNAK_W<27> { + SNAK_W::new(self) + } + #[doc = "Bit 28 - Set DATA0 PID"] + #[inline(always)] + #[must_use] + pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<28> { + SD0PID_SEVNFRM_W::new(self) + } + #[doc = "Bit 29 - Set odd frame"] + #[inline(always)] + #[must_use] + pub fn soddfrm(&mut self) -> SODDFRM_W<29> { + SODDFRM_W::new(self) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + #[must_use] + pub fn epdis(&mut self) -> EPDIS_W<30> { + EPDIS_W::new(self) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + #[must_use] + pub fn epena(&mut self) -> EPENA_W<31> { + EPENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepctl0](index.html) module"] +pub struct DIEPCTL0_SPEC; +impl crate::RegisterSpec for DIEPCTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepctl0::R](R) reader structure"] +impl crate::Readable for DIEPCTL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepctl0::W](W) writer structure"] +impl crate::Writable for DIEPCTL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPCTL0 to value 0"] +impl crate::Resettable for DIEPCTL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs new file mode 100644 index 0000000..321905e --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DIEPDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepdma](index.html) module"] +pub struct DIEPDMA_SPEC; +impl crate::RegisterSpec for DIEPDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepdma::R](R) reader structure"] +impl crate::Readable for DIEPDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepdma::W](W) writer structure"] +impl crate::Writable for DIEPDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPDMA to value 0"] +impl crate::Resettable for DIEPDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs new file mode 100644 index 0000000..f85ca85 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs @@ -0,0 +1,222 @@ +#[doc = "Register `DIEPINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed interrupt"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed interrupt"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] +pub type EPDISD_R = crate::BitReader; +#[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] +pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `TOC` reader - Timeout condition"] +pub type TOC_R = crate::BitReader; +#[doc = "Field `TOC` writer - Timeout condition"] +pub type TOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `ITTXFE` reader - IN token received when TxFIFO is empty"] +pub type ITTXFE_R = crate::BitReader; +#[doc = "Field `ITTXFE` writer - IN token received when TxFIFO is empty"] +pub type ITTXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `INEPNE` reader - IN endpoint NAK effective"] +pub type INEPNE_R = crate::BitReader; +#[doc = "Field `INEPNE` writer - IN endpoint NAK effective"] +pub type INEPNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `TXFE` reader - Transmit FIFO empty"] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `TXFIFOUDRN` reader - Transmit Fifo Underrun"] +pub type TXFIFOUDRN_R = crate::BitReader; +#[doc = "Field `TXFIFOUDRN` writer - Transmit Fifo Underrun"] +pub type TXFIFOUDRN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `BNA` reader - Buffer not available interrupt"] +pub type BNA_R = crate::BitReader; +#[doc = "Field `BNA` writer - Buffer not available interrupt"] +pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `PKTDRPSTS` reader - Packet dropped status"] +pub type PKTDRPSTS_R = crate::BitReader; +#[doc = "Field `PKTDRPSTS` writer - Packet dropped status"] +pub type PKTDRPSTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Babble error interrupt"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Babble error interrupt"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `NAK` reader - NAK interrupt"] +pub type NAK_R = crate::BitReader; +#[doc = "Field `NAK` writer - NAK interrupt"] +pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + pub fn epdisd(&self) -> EPDISD_R { + EPDISD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO is empty"] + #[inline(always)] + pub fn ittxfe(&self) -> ITTXFE_R { + ITTXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective"] + #[inline(always)] + pub fn inepne(&self) -> INEPNE_R { + INEPNE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transmit FIFO empty"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit Fifo Underrun"] + #[inline(always)] + pub fn txfifoudrn(&self) -> TXFIFOUDRN_R { + TXFIFOUDRN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Buffer not available interrupt"] + #[inline(always)] + pub fn bna(&self) -> BNA_R { + BNA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Packet dropped status"] + #[inline(always)] + pub fn pktdrpsts(&self) -> PKTDRPSTS_R { + PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Babble error interrupt"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt"] + #[inline(always)] + pub fn nak(&self) -> NAK_R { + NAK_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + #[must_use] + pub fn epdisd(&mut self) -> EPDISD_W<1> { + EPDISD_W::new(self) + } + #[doc = "Bit 3 - Timeout condition"] + #[inline(always)] + #[must_use] + pub fn toc(&mut self) -> TOC_W<3> { + TOC_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO is empty"] + #[inline(always)] + #[must_use] + pub fn ittxfe(&mut self) -> ITTXFE_W<4> { + ITTXFE_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective"] + #[inline(always)] + #[must_use] + pub fn inepne(&mut self) -> INEPNE_W<6> { + INEPNE_W::new(self) + } + #[doc = "Bit 8 - Transmit Fifo Underrun"] + #[inline(always)] + #[must_use] + pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<8> { + TXFIFOUDRN_W::new(self) + } + #[doc = "Bit 9 - Buffer not available interrupt"] + #[inline(always)] + #[must_use] + pub fn bna(&mut self) -> BNA_W<9> { + BNA_W::new(self) + } + #[doc = "Bit 11 - Packet dropped status"] + #[inline(always)] + #[must_use] + pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<11> { + PKTDRPSTS_W::new(self) + } + #[doc = "Bit 12 - Babble error interrupt"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<12> { + BERR_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt"] + #[inline(always)] + #[must_use] + pub fn nak(&mut self) -> NAK_W<13> { + NAK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepint](index.html) module"] +pub struct DIEPINT_SPEC; +impl crate::RegisterSpec for DIEPINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepint::R](R) reader structure"] +impl crate::Readable for DIEPINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepint::W](W) writer structure"] +impl crate::Writable for DIEPINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPINT to value 0x80"] +impl crate::Resettable for DIEPINT_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs new file mode 100644 index 0000000..7f94dcb --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 7, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::FieldReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 19:20 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bits 19:20 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptsiz](index.html) module"] +pub struct DIEPTSIZ_SPEC; +impl crate::RegisterSpec for DIEPTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptsiz::R](R) reader structure"] +impl crate::Readable for DIEPTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptsiz::W](W) writer structure"] +impl crate::Writable for DIEPTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTSIZ to value 0"] +impl crate::Resettable for DIEPTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs new file mode 100644 index 0000000..c962826 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DTXFSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INEPTFSAV` reader - IN endpoint TxFIFO space avail"] +pub type INEPTFSAV_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - IN endpoint TxFIFO space avail"] + #[inline(always)] + pub fn ineptfsav(&self) -> INEPTFSAV_R { + INEPTFSAV_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Transmit FIFO status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtxfsts](index.html) module"] +pub struct DTXFSTS_SPEC; +impl crate::RegisterSpec for DTXFSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dtxfsts::R](R) reader structure"] +impl crate::Readable for DTXFSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DTXFSTS to value 0"] +impl crate::Resettable for DTXFSTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs new file mode 100644 index 0000000..a3a9e56 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs @@ -0,0 +1,30 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct OUT_ENDPOINT { + #[doc = "0x00 - Control"] + pub doepctl: DOEPCTL, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Interrupt"] + pub doepint: DOEPINT, + _reserved2: [u8; 0x04], + #[doc = "0x10 - Transfer size"] + pub doeptsiz: DOEPTSIZ, + #[doc = "0x14 - DMA address"] + pub doepdma: DOEPDMA, +} +#[doc = "DOEPCTL (rw) register accessor: an alias for `Reg`"] +pub type DOEPCTL = crate::Reg; +#[doc = "Control"] +pub mod doepctl; +#[doc = "DOEPINT (rw) register accessor: an alias for `Reg`"] +pub type DOEPINT = crate::Reg; +#[doc = "Interrupt"] +pub mod doepint; +#[doc = "DOEPTSIZ (rw) register accessor: an alias for `Reg`"] +pub type DOEPTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod doeptsiz; +#[doc = "DOEPDMA (rw) register accessor: an alias for `Reg`"] +pub type DOEPDMA = crate::Reg; +#[doc = "DMA address"] +pub mod doepdma; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs new file mode 100644 index 0000000..2f6baf5 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs @@ -0,0 +1,154 @@ +#[doc = "Register `DOEPCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `USBAEP` reader - USB active endpoint"] +pub type USBAEP_R = crate::BitReader; +#[doc = "Field `NAKSTS` reader - NAK status"] +pub type NAKSTS_R = crate::BitReader; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `SNPM` reader - Snoop mode"] +pub type SNPM_R = crate::BitReader; +#[doc = "Field `SNPM` writer - Snoop mode"] +pub type SNPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `Stall` reader - STALL handshake"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `Stall` writer - STALL handshake"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `CNAK` writer - Clear NAK"] +pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `SNAK` writer - Set NAK"] +pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `EPDIS` reader - Endpoint disable"] +pub type EPDIS_R = crate::BitReader; +#[doc = "Field `EPENA` writer - Endpoint enable"] +pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + pub fn usbaep(&self) -> USBAEP_R { + USBAEP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - NAK status"] + #[inline(always)] + pub fn naksts(&self) -> NAKSTS_R { + NAKSTS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Snoop mode"] + #[inline(always)] + pub fn snpm(&self) -> SNPM_R { + SNPM_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + pub fn epdis(&self) -> EPDIS_R { + EPDIS_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 20 - Snoop mode"] + #[inline(always)] + #[must_use] + pub fn snpm(&mut self) -> SNPM_W<20> { + SNPM_W::new(self) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<21> { + STALL_W::new(self) + } + #[doc = "Bit 26 - Clear NAK"] + #[inline(always)] + #[must_use] + pub fn cnak(&mut self) -> CNAK_W<26> { + CNAK_W::new(self) + } + #[doc = "Bit 27 - Set NAK"] + #[inline(always)] + #[must_use] + pub fn snak(&mut self) -> SNAK_W<27> { + SNAK_W::new(self) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + #[must_use] + pub fn epena(&mut self) -> EPENA_W<31> { + EPENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepctl](index.html) module"] +pub struct DOEPCTL_SPEC; +impl crate::RegisterSpec for DOEPCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepctl::R](R) reader structure"] +impl crate::Readable for DOEPCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepctl::W](W) writer structure"] +impl crate::Writable for DOEPCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPCTL to value 0x8000"] +impl crate::Resettable for DOEPCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs new file mode 100644 index 0000000..92089f0 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DOEPDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepdma](index.html) module"] +pub struct DOEPDMA_SPEC; +impl crate::RegisterSpec for DOEPDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepdma::R](R) reader structure"] +impl crate::Readable for DOEPDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepdma::W](W) writer structure"] +impl crate::Writable for DOEPDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPDMA to value 0"] +impl crate::Resettable for DOEPDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs new file mode 100644 index 0000000..365d667 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DOEPINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed interrupt"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed interrupt"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] +pub type EPDISD_R = crate::BitReader; +#[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] +pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `STUP` reader - SETUP phase done"] +pub type STUP_R = crate::BitReader; +#[doc = "Field `STUP` writer - SETUP phase done"] +pub type STUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `OTEPDIS` reader - OUT token received when endpoint disabled"] +pub type OTEPDIS_R = crate::BitReader; +#[doc = "Field `OTEPDIS` writer - OUT token received when endpoint disabled"] +pub type OTEPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received"] +pub type B2BSTUP_R = crate::BitReader; +#[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received"] +pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `NYET` reader - NYET interrupt"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - NYET interrupt"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + pub fn epdisd(&self) -> EPDISD_R { + EPDISD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - SETUP phase done"] + #[inline(always)] + pub fn stup(&self) -> STUP_R { + STUP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled"] + #[inline(always)] + pub fn otepdis(&self) -> OTEPDIS_R { + OTEPDIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received"] + #[inline(always)] + pub fn b2bstup(&self) -> B2BSTUP_R { + B2BSTUP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 14 - NYET interrupt"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + #[must_use] + pub fn epdisd(&mut self) -> EPDISD_W<1> { + EPDISD_W::new(self) + } + #[doc = "Bit 3 - SETUP phase done"] + #[inline(always)] + #[must_use] + pub fn stup(&mut self) -> STUP_W<3> { + STUP_W::new(self) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled"] + #[inline(always)] + #[must_use] + pub fn otepdis(&mut self) -> OTEPDIS_W<4> { + OTEPDIS_W::new(self) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received"] + #[inline(always)] + #[must_use] + pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + B2BSTUP_W::new(self) + } + #[doc = "Bit 14 - NYET interrupt"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<14> { + NYET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepint](index.html) module"] +pub struct DOEPINT_SPEC; +impl crate::RegisterSpec for DOEPINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepint::R](R) reader structure"] +impl crate::Readable for DOEPINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepint::W](W) writer structure"] +impl crate::Writable for DOEPINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPINT to value 0x80"] +impl crate::Resettable for DOEPINT_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs new file mode 100644 index 0000000..0f78e4d --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DOEPTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 7, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::BitReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPTSIZ_SPEC, bool, O>; +#[doc = "Field `STUPCNT` reader - SETUP packet count"] +pub type STUPCNT_R = crate::FieldReader; +#[doc = "Field `STUPCNT` writer - SETUP packet count"] +pub type STUPCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 19 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 29:30 - SETUP packet count"] + #[inline(always)] + pub fn stupcnt(&self) -> STUPCNT_R { + STUPCNT_R::new(((self.bits >> 29) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bit 19 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Bits 29:30 - SETUP packet count"] + #[inline(always)] + #[must_use] + pub fn stupcnt(&mut self) -> STUPCNT_W<29> { + STUPCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doeptsiz](index.html) module"] +pub struct DOEPTSIZ_SPEC; +impl crate::RegisterSpec for DOEPTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doeptsiz::R](R) reader structure"] +impl crate::Readable for DOEPTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doeptsiz::W](W) writer structure"] +impl crate::Writable for DOEPTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPTSIZ to value 0"] +impl crate::Resettable for DOEPTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global.rs b/crates/bcm2711-lpa/src/usb_otg_global.rs new file mode 100644 index 0000000..a6b35cb --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global.rs @@ -0,0 +1,198 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS control and status register"] + pub gotgctl: GOTGCTL, + #[doc = "0x04 - OTG_HS interrupt register"] + pub gotgint: GOTGINT, + #[doc = "0x08 - OTG_HS AHB configuration register"] + pub gahbcfg: GAHBCFG, + #[doc = "0x0c - OTG_HS USB configuration register"] + pub gusbcfg: GUSBCFG, + #[doc = "0x10 - OTG_HS reset register"] + pub grstctl: GRSTCTL, + #[doc = "0x14 - OTG_HS core interrupt register"] + pub gintsts: GINTSTS, + #[doc = "0x18 - OTG_HS interrupt mask register"] + pub gintmsk: GINTMSK, + _reserved_7_grxstsr: [u8; 0x04], + _reserved_8_grxstsp: [u8; 0x04], + #[doc = "0x24 - OTG_HS Receive FIFO size register"] + pub grxfsiz: GRXFSIZ, + _reserved_10_gnptxfsiz_host: [u8; 0x04], + #[doc = "0x2c - OTG_HS nonperiodic transmit FIFO/queue status register"] + pub gnptxsts: GNPTXSTS, + _reserved12: [u8; 0x08], + #[doc = "0x38 - OTG_HS general core configuration register"] + pub gccfg: GCCFG, + #[doc = "0x3c - OTG_HS core ID register"] + pub cid: CID, + #[doc = "0x40 - OTG_HS vendor ID register"] + pub vid: VID, + #[doc = "0x44 - Direction"] + pub hw_direction: HW_DIRECTION, + #[doc = "0x48 - Hardware Config 0"] + pub hw_config0: HW_CONFIG0, + _reserved17: [u8; 0xb4], + #[doc = "0x100 - OTG_HS Host periodic transmit FIFO size register"] + pub hptxfsiz: HPTXFSIZ, + #[doc = "0x104 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf1: DIEPTXF1, + #[doc = "0x108 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf2: DIEPTXF2, + _reserved20: [u8; 0x10], + #[doc = "0x11c - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf3: DIEPTXF3, + #[doc = "0x120 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf4: DIEPTXF4, + #[doc = "0x124 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf5: DIEPTXF5, + #[doc = "0x128 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf6: DIEPTXF6, + #[doc = "0x12c - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf7: DIEPTXF7, +} +impl RegisterBlock { + #[doc = "0x1c - OTG_HS Receive status debug read register (peripheral mode mode)"] + #[inline(always)] + pub const fn grxstsr_peripheral(&self) -> &GRXSTSR_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(28usize).cast() } + } + #[doc = "0x1c - OTG_HS Receive status debug read register (host mode)"] + #[inline(always)] + pub const fn grxstsr_host(&self) -> &GRXSTSR_HOST { + unsafe { &*(self as *const Self).cast::().add(28usize).cast() } + } + #[doc = "0x20 - OTG_HS status read and pop register (peripheral mode)"] + #[inline(always)] + pub const fn grxstsp_peripheral(&self) -> &GRXSTSP_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(32usize).cast() } + } + #[doc = "0x20 - OTG_HS status read and pop register (host mode)"] + #[inline(always)] + pub const fn grxstsp_host(&self) -> &GRXSTSP_HOST { + unsafe { &*(self as *const Self).cast::().add(32usize).cast() } + } + #[doc = "0x28 - Endpoint 0 transmit FIFO size (peripheral mode)"] + #[inline(always)] + pub const fn tx0fsiz_peripheral(&self) -> &TX0FSIZ_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(40usize).cast() } + } + #[doc = "0x28 - OTG_HS nonperiodic transmit FIFO size register (host mode)"] + #[inline(always)] + pub const fn gnptxfsiz_host(&self) -> &GNPTXFSIZ_HOST { + unsafe { &*(self as *const Self).cast::().add(40usize).cast() } + } +} +#[doc = "GOTGCTL (rw) register accessor: an alias for `Reg`"] +pub type GOTGCTL = crate::Reg; +#[doc = "OTG_HS control and status register"] +pub mod gotgctl; +#[doc = "GOTGINT (rw) register accessor: an alias for `Reg`"] +pub type GOTGINT = crate::Reg; +#[doc = "OTG_HS interrupt register"] +pub mod gotgint; +#[doc = "GAHBCFG (rw) register accessor: an alias for `Reg`"] +pub type GAHBCFG = crate::Reg; +#[doc = "OTG_HS AHB configuration register"] +pub mod gahbcfg; +#[doc = "GUSBCFG (rw) register accessor: an alias for `Reg`"] +pub type GUSBCFG = crate::Reg; +#[doc = "OTG_HS USB configuration register"] +pub mod gusbcfg; +#[doc = "GRSTCTL (rw) register accessor: an alias for `Reg`"] +pub type GRSTCTL = crate::Reg; +#[doc = "OTG_HS reset register"] +pub mod grstctl; +#[doc = "GINTSTS (rw) register accessor: an alias for `Reg`"] +pub type GINTSTS = crate::Reg; +#[doc = "OTG_HS core interrupt register"] +pub mod gintsts; +#[doc = "GINTMSK (rw) register accessor: an alias for `Reg`"] +pub type GINTMSK = crate::Reg; +#[doc = "OTG_HS interrupt mask register"] +pub mod gintmsk; +#[doc = "GRXSTSR_Host (r) register accessor: an alias for `Reg`"] +pub type GRXSTSR_HOST = crate::Reg; +#[doc = "OTG_HS Receive status debug read register (host mode)"] +pub mod grxstsr_host; +#[doc = "GRXSTSP_Host (r) register accessor: an alias for `Reg`"] +pub type GRXSTSP_HOST = crate::Reg; +#[doc = "OTG_HS status read and pop register (host mode)"] +pub mod grxstsp_host; +#[doc = "GRXFSIZ (rw) register accessor: an alias for `Reg`"] +pub type GRXFSIZ = crate::Reg; +#[doc = "OTG_HS Receive FIFO size register"] +pub mod grxfsiz; +#[doc = "GNPTXFSIZ_Host (rw) register accessor: an alias for `Reg`"] +pub type GNPTXFSIZ_HOST = crate::Reg; +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)"] +pub mod gnptxfsiz_host; +#[doc = "TX0FSIZ_Peripheral (rw) register accessor: an alias for `Reg`"] +pub type TX0FSIZ_PERIPHERAL = crate::Reg; +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)"] +pub mod tx0fsiz_peripheral; +#[doc = "GNPTXSTS (r) register accessor: an alias for `Reg`"] +pub type GNPTXSTS = crate::Reg; +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register"] +pub mod gnptxsts; +#[doc = "GCCFG (rw) register accessor: an alias for `Reg`"] +pub type GCCFG = crate::Reg; +#[doc = "OTG_HS general core configuration register"] +pub mod gccfg; +#[doc = "CID (rw) register accessor: an alias for `Reg`"] +pub type CID = crate::Reg; +#[doc = "OTG_HS core ID register"] +pub mod cid; +#[doc = "VID (r) register accessor: an alias for `Reg`"] +pub type VID = crate::Reg; +#[doc = "OTG_HS vendor ID register"] +pub mod vid; +#[doc = "HW_DIRECTION (r) register accessor: an alias for `Reg`"] +pub type HW_DIRECTION = crate::Reg; +#[doc = "Direction"] +pub mod hw_direction; +#[doc = "HW_CONFIG0 (r) register accessor: an alias for `Reg`"] +pub type HW_CONFIG0 = crate::Reg; +#[doc = "Hardware Config 0"] +pub mod hw_config0; +#[doc = "HPTXFSIZ (rw) register accessor: an alias for `Reg`"] +pub type HPTXFSIZ = crate::Reg; +#[doc = "OTG_HS Host periodic transmit FIFO size register"] +pub mod hptxfsiz; +#[doc = "DIEPTXF1 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF1 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf1; +#[doc = "DIEPTXF2 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF2 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf2; +#[doc = "DIEPTXF3 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF3 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf3; +#[doc = "DIEPTXF4 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF4 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf4; +#[doc = "DIEPTXF5 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF5 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf5; +#[doc = "DIEPTXF6 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF6 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf6; +#[doc = "DIEPTXF7 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF7 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf7; +#[doc = "GRXSTSR_Peripheral (r) register accessor: an alias for `Reg`"] +pub type GRXSTSR_PERIPHERAL = crate::Reg; +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)"] +pub mod grxstsr_peripheral; +#[doc = "GRXSTSP_Peripheral (r) register accessor: an alias for `Reg`"] +pub type GRXSTSP_PERIPHERAL = crate::Reg; +#[doc = "OTG_HS status read and pop register (peripheral mode)"] +pub mod grxstsp_peripheral; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/cid.rs b/crates/bcm2711-lpa/src/usb_otg_global/cid.rs new file mode 100644 index 0000000..5a8ef55 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/cid.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRODUCT_ID` reader - Product ID field"] +pub type PRODUCT_ID_R = crate::FieldReader; +#[doc = "Field `PRODUCT_ID` writer - Product ID field"] +pub type PRODUCT_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CID_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Product ID field"] + #[inline(always)] + pub fn product_id(&self) -> PRODUCT_ID_R { + PRODUCT_ID_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Product ID field"] + #[inline(always)] + #[must_use] + pub fn product_id(&mut self) -> PRODUCT_ID_W<0> { + PRODUCT_ID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS core ID register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +pub struct CID_SPEC; +impl crate::RegisterSpec for CID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid::R](R) reader structure"] +impl crate::Readable for CID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +impl crate::Writable for CID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CID to value 0x1200"] +impl crate::Resettable for CID_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs new file mode 100644 index 0000000..b79803c --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](index.html) module"] +pub struct DIEPTXF1_SPEC; +impl crate::RegisterSpec for DIEPTXF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf1::R](R) reader structure"] +impl crate::Readable for DIEPTXF1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf1::W](W) writer structure"] +impl crate::Writable for DIEPTXF1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF1 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF1_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs new file mode 100644 index 0000000..cdf9d1b --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](index.html) module"] +pub struct DIEPTXF2_SPEC; +impl crate::RegisterSpec for DIEPTXF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf2::R](R) reader structure"] +impl crate::Readable for DIEPTXF2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf2::W](W) writer structure"] +impl crate::Writable for DIEPTXF2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF2 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF2_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs new file mode 100644 index 0000000..8eaba75 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](index.html) module"] +pub struct DIEPTXF3_SPEC; +impl crate::RegisterSpec for DIEPTXF3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf3::R](R) reader structure"] +impl crate::Readable for DIEPTXF3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf3::W](W) writer structure"] +impl crate::Writable for DIEPTXF3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF3 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF3_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs new file mode 100644 index 0000000..6b30646 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](index.html) module"] +pub struct DIEPTXF4_SPEC; +impl crate::RegisterSpec for DIEPTXF4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf4::R](R) reader structure"] +impl crate::Readable for DIEPTXF4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf4::W](W) writer structure"] +impl crate::Writable for DIEPTXF4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF4 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF4_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs new file mode 100644 index 0000000..e2b7d98 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](index.html) module"] +pub struct DIEPTXF5_SPEC; +impl crate::RegisterSpec for DIEPTXF5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf5::R](R) reader structure"] +impl crate::Readable for DIEPTXF5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf5::W](W) writer structure"] +impl crate::Writable for DIEPTXF5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF5 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF5_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs new file mode 100644 index 0000000..da38751 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](index.html) module"] +pub struct DIEPTXF6_SPEC; +impl crate::RegisterSpec for DIEPTXF6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf6::R](R) reader structure"] +impl crate::Readable for DIEPTXF6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf6::W](W) writer structure"] +impl crate::Writable for DIEPTXF6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF6 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF6_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs new file mode 100644 index 0000000..811d528 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf7](index.html) module"] +pub struct DIEPTXF7_SPEC; +impl crate::RegisterSpec for DIEPTXF7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf7::R](R) reader structure"] +impl crate::Readable for DIEPTXF7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf7::W](W) writer structure"] +impl crate::Writable for DIEPTXF7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF7 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF7_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs b/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs new file mode 100644 index 0000000..987d389 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs @@ -0,0 +1,230 @@ +#[doc = "Register `GAHBCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAHBCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GINT` reader - Global interrupt mask"] +pub type GINT_R = crate::BitReader; +#[doc = "Field `GINT` writer - Global interrupt mask"] +pub type GINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `AXI_BURST` reader - Maximum AXI burst length"] +pub type AXI_BURST_R = crate::FieldReader; +#[doc = "Maximum AXI burst length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BURST_A { + #[doc = "0: `0`"] + _4 = 0, + #[doc = "1: `1`"] + _3 = 1, + #[doc = "2: `10`"] + _2 = 2, + #[doc = "3: `11`"] + _1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BURST_A) -> Self { + variant as _ + } +} +impl AXI_BURST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BURST_A { + match self.bits { + 0 => BURST_A::_4, + 1 => BURST_A::_3, + 2 => BURST_A::_2, + 3 => BURST_A::_1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == BURST_A::_4 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + *self == BURST_A::_3 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == BURST_A::_2 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == BURST_A::_1 + } +} +#[doc = "Field `AXI_BURST` writer - Maximum AXI burst length"] +pub type AXI_BURST_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GAHBCFG_SPEC, u8, BURST_A, 2, O>; +impl<'a, const O: u8> AXI_BURST_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(BURST_A::_4) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(BURST_A::_3) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(BURST_A::_2) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(BURST_A::_1) + } +} +#[doc = "Field `AXI_WAIT` reader - Wait for all AXI writes before signaling DMA"] +pub type AXI_WAIT_R = crate::BitReader; +#[doc = "Field `AXI_WAIT` writer - Wait for all AXI writes before signaling DMA"] +pub type AXI_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - DMA enable"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - DMA enable"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `TXFELVL` reader - TxFIFO empty level"] +pub type TXFELVL_R = crate::BitReader; +#[doc = "Field `TXFELVL` writer - TxFIFO empty level"] +pub type TXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `PTXFELVL` reader - Periodic TxFIFO empty level"] +pub type PTXFELVL_R = crate::BitReader; +#[doc = "Field `PTXFELVL` writer - Periodic TxFIFO empty level"] +pub type PTXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Global interrupt mask"] + #[inline(always)] + pub fn gint(&self) -> GINT_R { + GINT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Maximum AXI burst length"] + #[inline(always)] + pub fn axi_burst(&self) -> AXI_BURST_R { + AXI_BURST_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] + #[inline(always)] + pub fn axi_wait(&self) -> AXI_WAIT_R { + AXI_WAIT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DMA enable"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - TxFIFO empty level"] + #[inline(always)] + pub fn txfelvl(&self) -> TXFELVL_R { + TXFELVL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Periodic TxFIFO empty level"] + #[inline(always)] + pub fn ptxfelvl(&self) -> PTXFELVL_R { + PTXFELVL_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Global interrupt mask"] + #[inline(always)] + #[must_use] + pub fn gint(&mut self) -> GINT_W<0> { + GINT_W::new(self) + } + #[doc = "Bits 1:2 - Maximum AXI burst length"] + #[inline(always)] + #[must_use] + pub fn axi_burst(&mut self) -> AXI_BURST_W<1> { + AXI_BURST_W::new(self) + } + #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] + #[inline(always)] + #[must_use] + pub fn axi_wait(&mut self) -> AXI_WAIT_W<4> { + AXI_WAIT_W::new(self) + } + #[doc = "Bit 5 - DMA enable"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<5> { + DMAEN_W::new(self) + } + #[doc = "Bit 7 - TxFIFO empty level"] + #[inline(always)] + #[must_use] + pub fn txfelvl(&mut self) -> TXFELVL_W<7> { + TXFELVL_W::new(self) + } + #[doc = "Bit 8 - Periodic TxFIFO empty level"] + #[inline(always)] + #[must_use] + pub fn ptxfelvl(&mut self) -> PTXFELVL_W<8> { + PTXFELVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS AHB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](index.html) module"] +pub struct GAHBCFG_SPEC; +impl crate::RegisterSpec for GAHBCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gahbcfg::R](R) reader structure"] +impl crate::Readable for GAHBCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gahbcfg::W](W) writer structure"] +impl crate::Writable for GAHBCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAHBCFG to value 0"] +impl crate::Resettable for GAHBCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs b/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs new file mode 100644 index 0000000..4dbbf5c --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs @@ -0,0 +1,155 @@ +#[doc = "Register `GCCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GCCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWRDWN` reader - Power down"] +pub type PWRDWN_R = crate::BitReader; +#[doc = "Field `PWRDWN` writer - Power down"] +pub type PWRDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `I2CPADEN` reader - Enable I2C bus connection for the external I2C PHY interface"] +pub type I2CPADEN_R = crate::BitReader; +#[doc = "Field `I2CPADEN` writer - Enable I2C bus connection for the external I2C PHY interface"] +pub type I2CPADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `VBUSASEN` reader - Enable the VBUS sensing device"] +pub type VBUSASEN_R = crate::BitReader; +#[doc = "Field `VBUSASEN` writer - Enable the VBUS sensing device"] +pub type VBUSASEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `VBUSBSEN` reader - Enable the VBUS sensing device"] +pub type VBUSBSEN_R = crate::BitReader; +#[doc = "Field `VBUSBSEN` writer - Enable the VBUS sensing device"] +pub type VBUSBSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `SOFOUTEN` reader - SOF output enable"] +pub type SOFOUTEN_R = crate::BitReader; +#[doc = "Field `SOFOUTEN` writer - SOF output enable"] +pub type SOFOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `NOVBUSSENS` reader - VBUS sensing disable option"] +pub type NOVBUSSENS_R = crate::BitReader; +#[doc = "Field `NOVBUSSENS` writer - VBUS sensing disable option"] +pub type NOVBUSSENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +impl R { + #[doc = "Bit 16 - Power down"] + #[inline(always)] + pub fn pwrdwn(&self) -> PWRDWN_R { + PWRDWN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] + #[inline(always)] + pub fn i2cpaden(&self) -> I2CPADEN_R { + I2CPADEN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable the VBUS sensing device"] + #[inline(always)] + pub fn vbusasen(&self) -> VBUSASEN_R { + VBUSASEN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable the VBUS sensing device"] + #[inline(always)] + pub fn vbusbsen(&self) -> VBUSBSEN_R { + VBUSBSEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - SOF output enable"] + #[inline(always)] + pub fn sofouten(&self) -> SOFOUTEN_R { + SOFOUTEN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - VBUS sensing disable option"] + #[inline(always)] + pub fn novbussens(&self) -> NOVBUSSENS_R { + NOVBUSSENS_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Power down"] + #[inline(always)] + #[must_use] + pub fn pwrdwn(&mut self) -> PWRDWN_W<16> { + PWRDWN_W::new(self) + } + #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] + #[inline(always)] + #[must_use] + pub fn i2cpaden(&mut self) -> I2CPADEN_W<17> { + I2CPADEN_W::new(self) + } + #[doc = "Bit 18 - Enable the VBUS sensing device"] + #[inline(always)] + #[must_use] + pub fn vbusasen(&mut self) -> VBUSASEN_W<18> { + VBUSASEN_W::new(self) + } + #[doc = "Bit 19 - Enable the VBUS sensing device"] + #[inline(always)] + #[must_use] + pub fn vbusbsen(&mut self) -> VBUSBSEN_W<19> { + VBUSBSEN_W::new(self) + } + #[doc = "Bit 20 - SOF output enable"] + #[inline(always)] + #[must_use] + pub fn sofouten(&mut self) -> SOFOUTEN_W<20> { + SOFOUTEN_W::new(self) + } + #[doc = "Bit 21 - VBUS sensing disable option"] + #[inline(always)] + #[must_use] + pub fn novbussens(&mut self) -> NOVBUSSENS_W<21> { + NOVBUSSENS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS general core configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gccfg](index.html) module"] +pub struct GCCFG_SPEC; +impl crate::RegisterSpec for GCCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gccfg::R](R) reader structure"] +impl crate::Readable for GCCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gccfg::W](W) writer structure"] +impl crate::Writable for GCCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GCCFG to value 0"] +impl crate::Resettable for GCCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs new file mode 100644 index 0000000..d3fdb2d --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs @@ -0,0 +1,447 @@ +#[doc = "Register `GINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MMISM` reader - Mode mismatch interrupt mask"] +pub type MMISM_R = crate::BitReader; +#[doc = "Field `MMISM` writer - Mode mismatch interrupt mask"] +pub type MMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `OTGINT` reader - OTG interrupt mask"] +pub type OTGINT_R = crate::BitReader; +#[doc = "Field `OTGINT` writer - OTG interrupt mask"] +pub type OTGINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `SOFM` reader - Start of frame mask"] +pub type SOFM_R = crate::BitReader; +#[doc = "Field `SOFM` writer - Start of frame mask"] +pub type SOFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `RXFLVLM` reader - Receive FIFO nonempty mask"] +pub type RXFLVLM_R = crate::BitReader; +#[doc = "Field `RXFLVLM` writer - Receive FIFO nonempty mask"] +pub type RXFLVLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `NPTXFEM` reader - Nonperiodic TxFIFO empty mask"] +pub type NPTXFEM_R = crate::BitReader; +#[doc = "Field `NPTXFEM` writer - Nonperiodic TxFIFO empty mask"] +pub type NPTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `GINAKEFFM` reader - Global nonperiodic IN NAK effective mask"] +pub type GINAKEFFM_R = crate::BitReader; +#[doc = "Field `GINAKEFFM` writer - Global nonperiodic IN NAK effective mask"] +pub type GINAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `GONAKEFFM` reader - Global OUT NAK effective mask"] +pub type GONAKEFFM_R = crate::BitReader; +#[doc = "Field `GONAKEFFM` writer - Global OUT NAK effective mask"] +pub type GONAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ESUSPM` reader - Early suspend mask"] +pub type ESUSPM_R = crate::BitReader; +#[doc = "Field `ESUSPM` writer - Early suspend mask"] +pub type ESUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `USBSUSPM` reader - USB suspend mask"] +pub type USBSUSPM_R = crate::BitReader; +#[doc = "Field `USBSUSPM` writer - USB suspend mask"] +pub type USBSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `USBRST` reader - USB reset mask"] +pub type USBRST_R = crate::BitReader; +#[doc = "Field `USBRST` writer - USB reset mask"] +pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ENUMDNEM` reader - Enumeration done mask"] +pub type ENUMDNEM_R = crate::BitReader; +#[doc = "Field `ENUMDNEM` writer - Enumeration done mask"] +pub type ENUMDNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ISOODRPM` reader - Isochronous OUT packet dropped interrupt mask"] +pub type ISOODRPM_R = crate::BitReader; +#[doc = "Field `ISOODRPM` writer - Isochronous OUT packet dropped interrupt mask"] +pub type ISOODRPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `EOPFM` reader - End of periodic frame interrupt mask"] +pub type EOPFM_R = crate::BitReader; +#[doc = "Field `EOPFM` writer - End of periodic frame interrupt mask"] +pub type EOPFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `EPMISM` reader - Endpoint mismatch interrupt mask"] +pub type EPMISM_R = crate::BitReader; +#[doc = "Field `EPMISM` writer - Endpoint mismatch interrupt mask"] +pub type EPMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `IEPINT` reader - IN endpoints interrupt mask"] +pub type IEPINT_R = crate::BitReader; +#[doc = "Field `IEPINT` writer - IN endpoints interrupt mask"] +pub type IEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `OEPINT` reader - OUT endpoints interrupt mask"] +pub type OEPINT_R = crate::BitReader; +#[doc = "Field `OEPINT` writer - OUT endpoints interrupt mask"] +pub type OEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `IISOIXFRM` reader - Incomplete isochronous IN transfer mask"] +pub type IISOIXFRM_R = crate::BitReader; +#[doc = "Field `IISOIXFRM` writer - Incomplete isochronous IN transfer mask"] +pub type IISOIXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PXFRM_IISOOXFRM` reader - Incomplete periodic transfer mask"] +pub type PXFRM_IISOOXFRM_R = crate::BitReader; +#[doc = "Field `PXFRM_IISOOXFRM` writer - Incomplete periodic transfer mask"] +pub type PXFRM_IISOOXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `FSUSPM` reader - Data fetch suspended mask"] +pub type FSUSPM_R = crate::BitReader; +#[doc = "Field `FSUSPM` writer - Data fetch suspended mask"] +pub type FSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PRTIM` reader - Host port interrupt mask"] +pub type PRTIM_R = crate::BitReader; +#[doc = "Field `HCIM` reader - Host channels interrupt mask"] +pub type HCIM_R = crate::BitReader; +#[doc = "Field `HCIM` writer - Host channels interrupt mask"] +pub type HCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PTXFEM` reader - Periodic TxFIFO empty mask"] +pub type PTXFEM_R = crate::BitReader; +#[doc = "Field `PTXFEM` writer - Periodic TxFIFO empty mask"] +pub type PTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `CIDSCHGM` reader - Connector ID status change mask"] +pub type CIDSCHGM_R = crate::BitReader; +#[doc = "Field `CIDSCHGM` writer - Connector ID status change mask"] +pub type CIDSCHGM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `DISCINT` reader - Disconnect detected interrupt mask"] +pub type DISCINT_R = crate::BitReader; +#[doc = "Field `DISCINT` writer - Disconnect detected interrupt mask"] +pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `SRQIM` reader - Session request/new session detected interrupt mask"] +pub type SRQIM_R = crate::BitReader; +#[doc = "Field `SRQIM` writer - Session request/new session detected interrupt mask"] +pub type SRQIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `WUIM` reader - Resume/remote wakeup detected interrupt mask"] +pub type WUIM_R = crate::BitReader; +#[doc = "Field `WUIM` writer - Resume/remote wakeup detected interrupt mask"] +pub type WUIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Mode mismatch interrupt mask"] + #[inline(always)] + pub fn mmism(&self) -> MMISM_R { + MMISM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OTG interrupt mask"] + #[inline(always)] + pub fn otgint(&self) -> OTGINT_R { + OTGINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start of frame mask"] + #[inline(always)] + pub fn sofm(&self) -> SOFM_R { + SOFM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO nonempty mask"] + #[inline(always)] + pub fn rxflvlm(&self) -> RXFLVLM_R { + RXFLVLM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] + #[inline(always)] + pub fn nptxfem(&self) -> NPTXFEM_R { + NPTXFEM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] + #[inline(always)] + pub fn ginakeffm(&self) -> GINAKEFFM_R { + GINAKEFFM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global OUT NAK effective mask"] + #[inline(always)] + pub fn gonakeffm(&self) -> GONAKEFFM_R { + GONAKEFFM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Early suspend mask"] + #[inline(always)] + pub fn esuspm(&self) -> ESUSPM_R { + ESUSPM_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB suspend mask"] + #[inline(always)] + pub fn usbsuspm(&self) -> USBSUSPM_R { + USBSUSPM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - USB reset mask"] + #[inline(always)] + pub fn usbrst(&self) -> USBRST_R { + USBRST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enumeration done mask"] + #[inline(always)] + pub fn enumdnem(&self) -> ENUMDNEM_R { + ENUMDNEM_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] + #[inline(always)] + pub fn isoodrpm(&self) -> ISOODRPM_R { + ISOODRPM_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - End of periodic frame interrupt mask"] + #[inline(always)] + pub fn eopfm(&self) -> EOPFM_R { + EOPFM_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] + #[inline(always)] + pub fn epmism(&self) -> EPMISM_R { + EPMISM_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - IN endpoints interrupt mask"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OUT endpoints interrupt mask"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] + #[inline(always)] + pub fn iisoixfrm(&self) -> IISOIXFRM_R { + IISOIXFRM_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Incomplete periodic transfer mask"] + #[inline(always)] + pub fn pxfrm_iisooxfrm(&self) -> PXFRM_IISOOXFRM_R { + PXFRM_IISOOXFRM_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data fetch suspended mask"] + #[inline(always)] + pub fn fsuspm(&self) -> FSUSPM_R { + FSUSPM_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Host port interrupt mask"] + #[inline(always)] + pub fn prtim(&self) -> PRTIM_R { + PRTIM_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Host channels interrupt mask"] + #[inline(always)] + pub fn hcim(&self) -> HCIM_R { + HCIM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Periodic TxFIFO empty mask"] + #[inline(always)] + pub fn ptxfem(&self) -> PTXFEM_R { + PTXFEM_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Connector ID status change mask"] + #[inline(always)] + pub fn cidschgm(&self) -> CIDSCHGM_R { + CIDSCHGM_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Disconnect detected interrupt mask"] + #[inline(always)] + pub fn discint(&self) -> DISCINT_R { + DISCINT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Session request/new session detected interrupt mask"] + #[inline(always)] + pub fn srqim(&self) -> SRQIM_R { + SRQIM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] + #[inline(always)] + pub fn wuim(&self) -> WUIM_R { + WUIM_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Mode mismatch interrupt mask"] + #[inline(always)] + #[must_use] + pub fn mmism(&mut self) -> MMISM_W<1> { + MMISM_W::new(self) + } + #[doc = "Bit 2 - OTG interrupt mask"] + #[inline(always)] + #[must_use] + pub fn otgint(&mut self) -> OTGINT_W<2> { + OTGINT_W::new(self) + } + #[doc = "Bit 3 - Start of frame mask"] + #[inline(always)] + #[must_use] + pub fn sofm(&mut self) -> SOFM_W<3> { + SOFM_W::new(self) + } + #[doc = "Bit 4 - Receive FIFO nonempty mask"] + #[inline(always)] + #[must_use] + pub fn rxflvlm(&mut self) -> RXFLVLM_W<4> { + RXFLVLM_W::new(self) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn nptxfem(&mut self) -> NPTXFEM_W<5> { + NPTXFEM_W::new(self) + } + #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn ginakeffm(&mut self) -> GINAKEFFM_W<6> { + GINAKEFFM_W::new(self) + } + #[doc = "Bit 7 - Global OUT NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn gonakeffm(&mut self) -> GONAKEFFM_W<7> { + GONAKEFFM_W::new(self) + } + #[doc = "Bit 10 - Early suspend mask"] + #[inline(always)] + #[must_use] + pub fn esuspm(&mut self) -> ESUSPM_W<10> { + ESUSPM_W::new(self) + } + #[doc = "Bit 11 - USB suspend mask"] + #[inline(always)] + #[must_use] + pub fn usbsuspm(&mut self) -> USBSUSPM_W<11> { + USBSUSPM_W::new(self) + } + #[doc = "Bit 12 - USB reset mask"] + #[inline(always)] + #[must_use] + pub fn usbrst(&mut self) -> USBRST_W<12> { + USBRST_W::new(self) + } + #[doc = "Bit 13 - Enumeration done mask"] + #[inline(always)] + #[must_use] + pub fn enumdnem(&mut self) -> ENUMDNEM_W<13> { + ENUMDNEM_W::new(self) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] + #[inline(always)] + #[must_use] + pub fn isoodrpm(&mut self) -> ISOODRPM_W<14> { + ISOODRPM_W::new(self) + } + #[doc = "Bit 15 - End of periodic frame interrupt mask"] + #[inline(always)] + #[must_use] + pub fn eopfm(&mut self) -> EOPFM_W<15> { + EOPFM_W::new(self) + } + #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epmism(&mut self) -> EPMISM_W<17> { + EPMISM_W::new(self) + } + #[doc = "Bit 18 - IN endpoints interrupt mask"] + #[inline(always)] + #[must_use] + pub fn iepint(&mut self) -> IEPINT_W<18> { + IEPINT_W::new(self) + } + #[doc = "Bit 19 - OUT endpoints interrupt mask"] + #[inline(always)] + #[must_use] + pub fn oepint(&mut self) -> OEPINT_W<19> { + OEPINT_W::new(self) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] + #[inline(always)] + #[must_use] + pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<20> { + IISOIXFRM_W::new(self) + } + #[doc = "Bit 21 - Incomplete periodic transfer mask"] + #[inline(always)] + #[must_use] + pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<21> { + PXFRM_IISOOXFRM_W::new(self) + } + #[doc = "Bit 22 - Data fetch suspended mask"] + #[inline(always)] + #[must_use] + pub fn fsuspm(&mut self) -> FSUSPM_W<22> { + FSUSPM_W::new(self) + } + #[doc = "Bit 25 - Host channels interrupt mask"] + #[inline(always)] + #[must_use] + pub fn hcim(&mut self) -> HCIM_W<25> { + HCIM_W::new(self) + } + #[doc = "Bit 26 - Periodic TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ptxfem(&mut self) -> PTXFEM_W<26> { + PTXFEM_W::new(self) + } + #[doc = "Bit 28 - Connector ID status change mask"] + #[inline(always)] + #[must_use] + pub fn cidschgm(&mut self) -> CIDSCHGM_W<28> { + CIDSCHGM_W::new(self) + } + #[doc = "Bit 29 - Disconnect detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn discint(&mut self) -> DISCINT_W<29> { + DISCINT_W::new(self) + } + #[doc = "Bit 30 - Session request/new session detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn srqim(&mut self) -> SRQIM_W<30> { + SRQIM_W::new(self) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn wuim(&mut self) -> WUIM_W<31> { + WUIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](index.html) module"] +pub struct GINTMSK_SPEC; +impl crate::RegisterSpec for GINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gintmsk::R](R) reader structure"] +impl crate::Readable for GINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gintmsk::W](W) writer structure"] +impl crate::Writable for GINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GINTMSK to value 0"] +impl crate::Resettable for GINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs b/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs new file mode 100644 index 0000000..4dd3aa9 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs @@ -0,0 +1,367 @@ +#[doc = "Register `GINTSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GINTSTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMOD` reader - Current mode of operation"] +pub type CMOD_R = crate::BitReader; +#[doc = "Field `MMIS` reader - Mode mismatch interrupt"] +pub type MMIS_R = crate::BitReader; +#[doc = "Field `MMIS` writer - Mode mismatch interrupt"] +pub type MMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `OTGINT` reader - OTG interrupt"] +pub type OTGINT_R = crate::BitReader; +#[doc = "Field `SOF` reader - Start of frame"] +pub type SOF_R = crate::BitReader; +#[doc = "Field `SOF` writer - Start of frame"] +pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `RXFLVL` reader - RxFIFO nonempty"] +pub type RXFLVL_R = crate::BitReader; +#[doc = "Field `NPTXFE` reader - Nonperiodic TxFIFO empty"] +pub type NPTXFE_R = crate::BitReader; +#[doc = "Field `GINAKEFF` reader - Global IN nonperiodic NAK effective"] +pub type GINAKEFF_R = crate::BitReader; +#[doc = "Field `BOUTNAKEFF` reader - Global OUT NAK effective"] +pub type BOUTNAKEFF_R = crate::BitReader; +#[doc = "Field `ESUSP` reader - Early suspend"] +pub type ESUSP_R = crate::BitReader; +#[doc = "Field `ESUSP` writer - Early suspend"] +pub type ESUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `USBSUSP` reader - USB suspend"] +pub type USBSUSP_R = crate::BitReader; +#[doc = "Field `USBSUSP` writer - USB suspend"] +pub type USBSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `USBRST` reader - USB reset"] +pub type USBRST_R = crate::BitReader; +#[doc = "Field `USBRST` writer - USB reset"] +pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `ENUMDNE` reader - Enumeration done"] +pub type ENUMDNE_R = crate::BitReader; +#[doc = "Field `ENUMDNE` writer - Enumeration done"] +pub type ENUMDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `ISOODRP` reader - Isochronous OUT packet dropped interrupt"] +pub type ISOODRP_R = crate::BitReader; +#[doc = "Field `ISOODRP` writer - Isochronous OUT packet dropped interrupt"] +pub type ISOODRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `EOPF` reader - End of periodic frame interrupt"] +pub type EOPF_R = crate::BitReader; +#[doc = "Field `EOPF` writer - End of periodic frame interrupt"] +pub type EOPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `IEPINT` reader - IN endpoint interrupt"] +pub type IEPINT_R = crate::BitReader; +#[doc = "Field `OEPINT` reader - OUT endpoint interrupt"] +pub type OEPINT_R = crate::BitReader; +#[doc = "Field `IISOIXFR` reader - Incomplete isochronous IN transfer"] +pub type IISOIXFR_R = crate::BitReader; +#[doc = "Field `IISOIXFR` writer - Incomplete isochronous IN transfer"] +pub type IISOIXFR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `PXFR_INCOMPISOOUT` reader - Incomplete periodic transfer"] +pub type PXFR_INCOMPISOOUT_R = crate::BitReader; +#[doc = "Field `PXFR_INCOMPISOOUT` writer - Incomplete periodic transfer"] +pub type PXFR_INCOMPISOOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `DATAFSUSP` reader - Data fetch suspended"] +pub type DATAFSUSP_R = crate::BitReader; +#[doc = "Field `DATAFSUSP` writer - Data fetch suspended"] +pub type DATAFSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `HPRTINT` reader - Host port interrupt"] +pub type HPRTINT_R = crate::BitReader; +#[doc = "Field `HCINT` reader - Host channels interrupt"] +pub type HCINT_R = crate::BitReader; +#[doc = "Field `PTXFE` reader - Periodic TxFIFO empty"] +pub type PTXFE_R = crate::BitReader; +#[doc = "Field `CIDSCHG` reader - Connector ID status change"] +pub type CIDSCHG_R = crate::BitReader; +#[doc = "Field `CIDSCHG` writer - Connector ID status change"] +pub type CIDSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `DISCINT` reader - Disconnect detected interrupt"] +pub type DISCINT_R = crate::BitReader; +#[doc = "Field `DISCINT` writer - Disconnect detected interrupt"] +pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `SRQINT` reader - Session request/new session detected interrupt"] +pub type SRQINT_R = crate::BitReader; +#[doc = "Field `SRQINT` writer - Session request/new session detected interrupt"] +pub type SRQINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `WKUINT` reader - Resume/remote wakeup detected interrupt"] +pub type WKUINT_R = crate::BitReader; +#[doc = "Field `WKUINT` writer - Resume/remote wakeup detected interrupt"] +pub type WKUINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Current mode of operation"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mode mismatch interrupt"] + #[inline(always)] + pub fn mmis(&self) -> MMIS_R { + MMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OTG interrupt"] + #[inline(always)] + pub fn otgint(&self) -> OTGINT_R { + OTGINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start of frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RxFIFO nonempty"] + #[inline(always)] + pub fn rxflvl(&self) -> RXFLVL_R { + RXFLVL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty"] + #[inline(always)] + pub fn nptxfe(&self) -> NPTXFE_R { + NPTXFE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global IN nonperiodic NAK effective"] + #[inline(always)] + pub fn ginakeff(&self) -> GINAKEFF_R { + GINAKEFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global OUT NAK effective"] + #[inline(always)] + pub fn boutnakeff(&self) -> BOUTNAKEFF_R { + BOUTNAKEFF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Early suspend"] + #[inline(always)] + pub fn esusp(&self) -> ESUSP_R { + ESUSP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB suspend"] + #[inline(always)] + pub fn usbsusp(&self) -> USBSUSP_R { + USBSUSP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - USB reset"] + #[inline(always)] + pub fn usbrst(&self) -> USBRST_R { + USBRST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enumeration done"] + #[inline(always)] + pub fn enumdne(&self) -> ENUMDNE_R { + ENUMDNE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] + #[inline(always)] + pub fn isoodrp(&self) -> ISOODRP_R { + ISOODRP_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - End of periodic frame interrupt"] + #[inline(always)] + pub fn eopf(&self) -> EOPF_R { + EOPF_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 18 - IN endpoint interrupt"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OUT endpoint interrupt"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer"] + #[inline(always)] + pub fn iisoixfr(&self) -> IISOIXFR_R { + IISOIXFR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Incomplete periodic transfer"] + #[inline(always)] + pub fn pxfr_incompisoout(&self) -> PXFR_INCOMPISOOUT_R { + PXFR_INCOMPISOOUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data fetch suspended"] + #[inline(always)] + pub fn datafsusp(&self) -> DATAFSUSP_R { + DATAFSUSP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Host port interrupt"] + #[inline(always)] + pub fn hprtint(&self) -> HPRTINT_R { + HPRTINT_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Host channels interrupt"] + #[inline(always)] + pub fn hcint(&self) -> HCINT_R { + HCINT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Periodic TxFIFO empty"] + #[inline(always)] + pub fn ptxfe(&self) -> PTXFE_R { + PTXFE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Connector ID status change"] + #[inline(always)] + pub fn cidschg(&self) -> CIDSCHG_R { + CIDSCHG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Disconnect detected interrupt"] + #[inline(always)] + pub fn discint(&self) -> DISCINT_R { + DISCINT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Session request/new session detected interrupt"] + #[inline(always)] + pub fn srqint(&self) -> SRQINT_R { + SRQINT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] + #[inline(always)] + pub fn wkuint(&self) -> WKUINT_R { + WKUINT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Mode mismatch interrupt"] + #[inline(always)] + #[must_use] + pub fn mmis(&mut self) -> MMIS_W<1> { + MMIS_W::new(self) + } + #[doc = "Bit 3 - Start of frame"] + #[inline(always)] + #[must_use] + pub fn sof(&mut self) -> SOF_W<3> { + SOF_W::new(self) + } + #[doc = "Bit 10 - Early suspend"] + #[inline(always)] + #[must_use] + pub fn esusp(&mut self) -> ESUSP_W<10> { + ESUSP_W::new(self) + } + #[doc = "Bit 11 - USB suspend"] + #[inline(always)] + #[must_use] + pub fn usbsusp(&mut self) -> USBSUSP_W<11> { + USBSUSP_W::new(self) + } + #[doc = "Bit 12 - USB reset"] + #[inline(always)] + #[must_use] + pub fn usbrst(&mut self) -> USBRST_W<12> { + USBRST_W::new(self) + } + #[doc = "Bit 13 - Enumeration done"] + #[inline(always)] + #[must_use] + pub fn enumdne(&mut self) -> ENUMDNE_W<13> { + ENUMDNE_W::new(self) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] + #[inline(always)] + #[must_use] + pub fn isoodrp(&mut self) -> ISOODRP_W<14> { + ISOODRP_W::new(self) + } + #[doc = "Bit 15 - End of periodic frame interrupt"] + #[inline(always)] + #[must_use] + pub fn eopf(&mut self) -> EOPF_W<15> { + EOPF_W::new(self) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer"] + #[inline(always)] + #[must_use] + pub fn iisoixfr(&mut self) -> IISOIXFR_W<20> { + IISOIXFR_W::new(self) + } + #[doc = "Bit 21 - Incomplete periodic transfer"] + #[inline(always)] + #[must_use] + pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<21> { + PXFR_INCOMPISOOUT_W::new(self) + } + #[doc = "Bit 22 - Data fetch suspended"] + #[inline(always)] + #[must_use] + pub fn datafsusp(&mut self) -> DATAFSUSP_W<22> { + DATAFSUSP_W::new(self) + } + #[doc = "Bit 28 - Connector ID status change"] + #[inline(always)] + #[must_use] + pub fn cidschg(&mut self) -> CIDSCHG_W<28> { + CIDSCHG_W::new(self) + } + #[doc = "Bit 29 - Disconnect detected interrupt"] + #[inline(always)] + #[must_use] + pub fn discint(&mut self) -> DISCINT_W<29> { + DISCINT_W::new(self) + } + #[doc = "Bit 30 - Session request/new session detected interrupt"] + #[inline(always)] + #[must_use] + pub fn srqint(&mut self) -> SRQINT_W<30> { + SRQINT_W::new(self) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] + #[inline(always)] + #[must_use] + pub fn wkuint(&mut self) -> WKUINT_W<31> { + WKUINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS core interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](index.html) module"] +pub struct GINTSTS_SPEC; +impl crate::RegisterSpec for GINTSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gintsts::R](R) reader structure"] +impl crate::Readable for GINTSTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gintsts::W](W) writer structure"] +impl crate::Writable for GINTSTS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GINTSTS to value 0x0400_0020"] +impl crate::Resettable for GINTSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0020; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs b/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs new file mode 100644 index 0000000..89a5540 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs @@ -0,0 +1,97 @@ +#[doc = "Register `GNPTXFSIZ_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GNPTXFSIZ_Host` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NPTXFSA` reader - Nonperiodic transmit RAM start address"] +pub type NPTXFSA_R = crate::FieldReader; +#[doc = "Field `NPTXFSA` writer - Nonperiodic transmit RAM start address"] +pub type NPTXFSA_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +#[doc = "Field `NPTXFD` reader - Nonperiodic TxFIFO depth"] +pub type NPTXFD_R = crate::FieldReader; +#[doc = "Field `NPTXFD` writer - Nonperiodic TxFIFO depth"] +pub type NPTXFD_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] + #[inline(always)] + pub fn nptxfsa(&self) -> NPTXFSA_R { + NPTXFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] + #[inline(always)] + pub fn nptxfd(&self) -> NPTXFD_R { + NPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn nptxfsa(&mut self) -> NPTXFSA_W<0> { + NPTXFSA_W::new(self) + } + #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn nptxfd(&mut self) -> NPTXFD_W<16> { + NPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz_host](index.html) module"] +pub struct GNPTXFSIZ_HOST_SPEC; +impl crate::RegisterSpec for GNPTXFSIZ_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gnptxfsiz_host::R](R) reader structure"] +impl crate::Readable for GNPTXFSIZ_HOST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gnptxfsiz_host::W](W) writer structure"] +impl crate::Writable for GNPTXFSIZ_HOST_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GNPTXFSIZ_Host to value 0x0200"] +impl crate::Resettable for GNPTXFSIZ_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs b/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs new file mode 100644 index 0000000..65ffd12 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs @@ -0,0 +1,51 @@ +#[doc = "Register `GNPTXSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `NPTXFSAV` reader - Nonperiodic TxFIFO space available"] +pub type NPTXFSAV_R = crate::FieldReader; +#[doc = "Field `NPTQXSAV` reader - Nonperiodic transmit request queue space available"] +pub type NPTQXSAV_R = crate::FieldReader; +#[doc = "Field `NPTXQTOP` reader - Top of the nonperiodic transmit request queue"] +pub type NPTXQTOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Nonperiodic TxFIFO space available"] + #[inline(always)] + pub fn nptxfsav(&self) -> NPTXFSAV_R { + NPTXFSAV_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Nonperiodic transmit request queue space available"] + #[inline(always)] + pub fn nptqxsav(&self) -> NPTQXSAV_R { + NPTQXSAV_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:30 - Top of the nonperiodic transmit request queue"] + #[inline(always)] + pub fn nptxqtop(&self) -> NPTXQTOP_R { + NPTXQTOP_R::new(((self.bits >> 24) & 0x7f) as u8) + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](index.html) module"] +pub struct GNPTXSTS_SPEC; +impl crate::RegisterSpec for GNPTXSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gnptxsts::R](R) reader structure"] +impl crate::Readable for GNPTXSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GNPTXSTS to value 0x0008_0200"] +impl crate::Resettable for GNPTXSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0200; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs b/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs new file mode 100644 index 0000000..6576636 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs @@ -0,0 +1,167 @@ +#[doc = "Register `GOTGCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GOTGCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRQSCS` reader - Session request success"] +pub type SRQSCS_R = crate::BitReader; +#[doc = "Field `SRQ` reader - Session request"] +pub type SRQ_R = crate::BitReader; +#[doc = "Field `SRQ` writer - Session request"] +pub type SRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `HNGSCS` reader - Host negotiation success"] +pub type HNGSCS_R = crate::BitReader; +#[doc = "Field `HNPRQ` reader - HNP request"] +pub type HNPRQ_R = crate::BitReader; +#[doc = "Field `HNPRQ` writer - HNP request"] +pub type HNPRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `HSHNPEN` reader - Host set HNP enable"] +pub type HSHNPEN_R = crate::BitReader; +#[doc = "Field `HSHNPEN` writer - Host set HNP enable"] +pub type HSHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `DHNPEN` reader - Device HNP enabled"] +pub type DHNPEN_R = crate::BitReader; +#[doc = "Field `DHNPEN` writer - Device HNP enabled"] +pub type DHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `CIDSTS` reader - Connector ID status"] +pub type CIDSTS_R = crate::BitReader; +#[doc = "Field `DBCT` reader - Long/short debounce time"] +pub type DBCT_R = crate::BitReader; +#[doc = "Field `ASVLD` reader - A-session valid"] +pub type ASVLD_R = crate::BitReader; +#[doc = "Field `BSVLD` reader - B-session valid"] +pub type BSVLD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Session request success"] + #[inline(always)] + pub fn srqscs(&self) -> SRQSCS_R { + SRQSCS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Session request"] + #[inline(always)] + pub fn srq(&self) -> SRQ_R { + SRQ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Host negotiation success"] + #[inline(always)] + pub fn hngscs(&self) -> HNGSCS_R { + HNGSCS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HNP request"] + #[inline(always)] + pub fn hnprq(&self) -> HNPRQ_R { + HNPRQ_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Host set HNP enable"] + #[inline(always)] + pub fn hshnpen(&self) -> HSHNPEN_R { + HSHNPEN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Device HNP enabled"] + #[inline(always)] + pub fn dhnpen(&self) -> DHNPEN_R { + DHNPEN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Connector ID status"] + #[inline(always)] + pub fn cidsts(&self) -> CIDSTS_R { + CIDSTS_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Long/short debounce time"] + #[inline(always)] + pub fn dbct(&self) -> DBCT_R { + DBCT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - A-session valid"] + #[inline(always)] + pub fn asvld(&self) -> ASVLD_R { + ASVLD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - B-session valid"] + #[inline(always)] + pub fn bsvld(&self) -> BSVLD_R { + BSVLD_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Session request"] + #[inline(always)] + #[must_use] + pub fn srq(&mut self) -> SRQ_W<1> { + SRQ_W::new(self) + } + #[doc = "Bit 9 - HNP request"] + #[inline(always)] + #[must_use] + pub fn hnprq(&mut self) -> HNPRQ_W<9> { + HNPRQ_W::new(self) + } + #[doc = "Bit 10 - Host set HNP enable"] + #[inline(always)] + #[must_use] + pub fn hshnpen(&mut self) -> HSHNPEN_W<10> { + HSHNPEN_W::new(self) + } + #[doc = "Bit 11 - Device HNP enabled"] + #[inline(always)] + #[must_use] + pub fn dhnpen(&mut self) -> DHNPEN_W<11> { + DHNPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](index.html) module"] +pub struct GOTGCTL_SPEC; +impl crate::RegisterSpec for GOTGCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gotgctl::R](R) reader structure"] +impl crate::Readable for GOTGCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gotgctl::W](W) writer structure"] +impl crate::Writable for GOTGCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOTGCTL to value 0x0800"] +impl crate::Resettable for GOTGCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs b/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs new file mode 100644 index 0000000..b2c3ab9 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs @@ -0,0 +1,155 @@ +#[doc = "Register `GOTGINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GOTGINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEDET` reader - Session end detected"] +pub type SEDET_R = crate::BitReader; +#[doc = "Field `SEDET` writer - Session end detected"] +pub type SEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `SRSSCHG` reader - Session request success status change"] +pub type SRSSCHG_R = crate::BitReader; +#[doc = "Field `SRSSCHG` writer - Session request success status change"] +pub type SRSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `HNSSCHG` reader - Host negotiation success status change"] +pub type HNSSCHG_R = crate::BitReader; +#[doc = "Field `HNSSCHG` writer - Host negotiation success status change"] +pub type HNSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `HNGDET` reader - Host negotiation detected"] +pub type HNGDET_R = crate::BitReader; +#[doc = "Field `HNGDET` writer - Host negotiation detected"] +pub type HNGDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `ADTOCHG` reader - A-device timeout change"] +pub type ADTOCHG_R = crate::BitReader; +#[doc = "Field `ADTOCHG` writer - A-device timeout change"] +pub type ADTOCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `DBCDNE` reader - Debounce done"] +pub type DBCDNE_R = crate::BitReader; +#[doc = "Field `DBCDNE` writer - Debounce done"] +pub type DBCDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 2 - Session end detected"] + #[inline(always)] + pub fn sedet(&self) -> SEDET_R { + SEDET_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Session request success status change"] + #[inline(always)] + pub fn srsschg(&self) -> SRSSCHG_R { + SRSSCHG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Host negotiation success status change"] + #[inline(always)] + pub fn hnsschg(&self) -> HNSSCHG_R { + HNSSCHG_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Host negotiation detected"] + #[inline(always)] + pub fn hngdet(&self) -> HNGDET_R { + HNGDET_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - A-device timeout change"] + #[inline(always)] + pub fn adtochg(&self) -> ADTOCHG_R { + ADTOCHG_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Debounce done"] + #[inline(always)] + pub fn dbcdne(&self) -> DBCDNE_R { + DBCDNE_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Session end detected"] + #[inline(always)] + #[must_use] + pub fn sedet(&mut self) -> SEDET_W<2> { + SEDET_W::new(self) + } + #[doc = "Bit 8 - Session request success status change"] + #[inline(always)] + #[must_use] + pub fn srsschg(&mut self) -> SRSSCHG_W<8> { + SRSSCHG_W::new(self) + } + #[doc = "Bit 9 - Host negotiation success status change"] + #[inline(always)] + #[must_use] + pub fn hnsschg(&mut self) -> HNSSCHG_W<9> { + HNSSCHG_W::new(self) + } + #[doc = "Bit 17 - Host negotiation detected"] + #[inline(always)] + #[must_use] + pub fn hngdet(&mut self) -> HNGDET_W<17> { + HNGDET_W::new(self) + } + #[doc = "Bit 18 - A-device timeout change"] + #[inline(always)] + #[must_use] + pub fn adtochg(&mut self) -> ADTOCHG_W<18> { + ADTOCHG_W::new(self) + } + #[doc = "Bit 19 - Debounce done"] + #[inline(always)] + #[must_use] + pub fn dbcdne(&mut self) -> DBCDNE_W<19> { + DBCDNE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](index.html) module"] +pub struct GOTGINT_SPEC; +impl crate::RegisterSpec for GOTGINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gotgint::R](R) reader structure"] +impl crate::Readable for GOTGINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gotgint::W](W) writer structure"] +impl crate::Writable for GOTGINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOTGINT to value 0"] +impl crate::Resettable for GOTGINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs b/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs new file mode 100644 index 0000000..c3f83dc --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs @@ -0,0 +1,169 @@ +#[doc = "Register `GRSTCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GRSTCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CSRST` reader - Core soft reset"] +pub type CSRST_R = crate::BitReader; +#[doc = "Field `CSRST` writer - Core soft reset"] +pub type CSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `HSRST` reader - HCLK soft reset"] +pub type HSRST_R = crate::BitReader; +#[doc = "Field `HSRST` writer - HCLK soft reset"] +pub type HSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `FCRST` reader - Host frame counter reset"] +pub type FCRST_R = crate::BitReader; +#[doc = "Field `FCRST` writer - Host frame counter reset"] +pub type FCRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `RXFFLSH` reader - RxFIFO flush"] +pub type RXFFLSH_R = crate::BitReader; +#[doc = "Field `RXFFLSH` writer - RxFIFO flush"] +pub type RXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `TXFFLSH` reader - TxFIFO flush"] +pub type TXFFLSH_R = crate::BitReader; +#[doc = "Field `TXFFLSH` writer - TxFIFO flush"] +pub type TXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `TXFNUM` reader - TxFIFO number"] +pub type TXFNUM_R = crate::FieldReader; +#[doc = "Field `TXFNUM` writer - TxFIFO number"] +pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, u8, 5, O>; +#[doc = "Field `DMAREQ` reader - DMA request signal"] +pub type DMAREQ_R = crate::BitReader; +#[doc = "Field `AHBIDL` reader - AHB master idle"] +pub type AHBIDL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Core soft reset"] + #[inline(always)] + pub fn csrst(&self) -> CSRST_R { + CSRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HCLK soft reset"] + #[inline(always)] + pub fn hsrst(&self) -> HSRST_R { + HSRST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host frame counter reset"] + #[inline(always)] + pub fn fcrst(&self) -> FCRST_R { + FCRST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - RxFIFO flush"] + #[inline(always)] + pub fn rxfflsh(&self) -> RXFFLSH_R { + RXFFLSH_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TxFIFO flush"] + #[inline(always)] + pub fn txfflsh(&self) -> TXFFLSH_R { + TXFFLSH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:10 - TxFIFO number"] + #[inline(always)] + pub fn txfnum(&self) -> TXFNUM_R { + TXFNUM_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bit 30 - DMA request signal"] + #[inline(always)] + pub fn dmareq(&self) -> DMAREQ_R { + DMAREQ_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - AHB master idle"] + #[inline(always)] + pub fn ahbidl(&self) -> AHBIDL_R { + AHBIDL_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Core soft reset"] + #[inline(always)] + #[must_use] + pub fn csrst(&mut self) -> CSRST_W<0> { + CSRST_W::new(self) + } + #[doc = "Bit 1 - HCLK soft reset"] + #[inline(always)] + #[must_use] + pub fn hsrst(&mut self) -> HSRST_W<1> { + HSRST_W::new(self) + } + #[doc = "Bit 2 - Host frame counter reset"] + #[inline(always)] + #[must_use] + pub fn fcrst(&mut self) -> FCRST_W<2> { + FCRST_W::new(self) + } + #[doc = "Bit 4 - RxFIFO flush"] + #[inline(always)] + #[must_use] + pub fn rxfflsh(&mut self) -> RXFFLSH_W<4> { + RXFFLSH_W::new(self) + } + #[doc = "Bit 5 - TxFIFO flush"] + #[inline(always)] + #[must_use] + pub fn txfflsh(&mut self) -> TXFFLSH_W<5> { + TXFFLSH_W::new(self) + } + #[doc = "Bits 6:10 - TxFIFO number"] + #[inline(always)] + #[must_use] + pub fn txfnum(&mut self) -> TXFNUM_W<6> { + TXFNUM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"] +pub struct GRSTCTL_SPEC; +impl crate::RegisterSpec for GRSTCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grstctl::R](R) reader structure"] +impl crate::Readable for GRSTCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"] +impl crate::Writable for GRSTCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GRSTCTL to value 0x2000_0000"] +impl crate::Resettable for GRSTCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_0000; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs new file mode 100644 index 0000000..ec6ba8c --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GRXFSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GRXFSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFD` reader - RxFIFO depth"] +pub type RXFD_R = crate::FieldReader; +#[doc = "Field `RXFD` writer - RxFIFO depth"] +pub type RXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRXFSIZ_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - RxFIFO depth"] + #[inline(always)] + pub fn rxfd(&self) -> RXFD_R { + RXFD_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn rxfd(&mut self) -> RXFD_W<0> { + RXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Receive FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](index.html) module"] +pub struct GRXFSIZ_SPEC; +impl crate::RegisterSpec for GRXFSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxfsiz::R](R) reader structure"] +impl crate::Readable for GRXFSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [grxfsiz::W](W) writer structure"] +impl crate::Writable for GRXFSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GRXFSIZ to value 0x0200"] +impl crate::Resettable for GRXFSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs new file mode 100644 index 0000000..a0231ff --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GRXSTSP_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHNUM` reader - Channel number"] +pub type CHNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Channel number"] + #[inline(always)] + pub fn chnum(&self) -> CHNUM_R { + CHNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[doc = "OTG_HS status read and pop register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_host](index.html) module"] +pub struct GRXSTSP_HOST_SPEC; +impl crate::RegisterSpec for GRXSTSP_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsp_host::R](R) reader structure"] +impl crate::Readable for GRXSTSP_HOST_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSP_Host to value 0"] +impl crate::Resettable for GRXSTSP_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs new file mode 100644 index 0000000..5de1533 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GRXSTSP_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +#[doc = "Field `FRMNUM` reader - Frame number"] +pub type FRMNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:24 - Frame number"] + #[inline(always)] + pub fn frmnum(&self) -> FRMNUM_R { + FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } +} +#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_peripheral](index.html) module"] +pub struct GRXSTSP_PERIPHERAL_SPEC; +impl crate::RegisterSpec for GRXSTSP_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsp_peripheral::R](R) reader structure"] +impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSP_Peripheral to value 0"] +impl crate::Resettable for GRXSTSP_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs new file mode 100644 index 0000000..399a9f8 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GRXSTSR_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHNUM` reader - Channel number"] +pub type CHNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Channel number"] + #[inline(always)] + pub fn chnum(&self) -> CHNUM_R { + CHNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[doc = "OTG_HS Receive status debug read register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_host](index.html) module"] +pub struct GRXSTSR_HOST_SPEC; +impl crate::RegisterSpec for GRXSTSR_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsr_host::R](R) reader structure"] +impl crate::Readable for GRXSTSR_HOST_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSR_Host to value 0"] +impl crate::Resettable for GRXSTSR_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs new file mode 100644 index 0000000..89558d9 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GRXSTSR_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +#[doc = "Field `FRMNUM` reader - Frame number"] +pub type FRMNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:24 - Frame number"] + #[inline(always)] + pub fn frmnum(&self) -> FRMNUM_R { + FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } +} +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_peripheral](index.html) module"] +pub struct GRXSTSR_PERIPHERAL_SPEC; +impl crate::RegisterSpec for GRXSTSR_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsr_peripheral::R](R) reader structure"] +impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSR_Peripheral to value 0"] +impl crate::Resettable for GRXSTSR_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs b/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs new file mode 100644 index 0000000..a958441 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs @@ -0,0 +1,625 @@ +#[doc = "Register `GUSBCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GUSBCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOCAL` reader - FS timeout calibration"] +pub type TOCAL_R = crate::FieldReader; +#[doc = "Field `TOCAL` writer - FS timeout calibration"] +pub type TOCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `PHYIF` reader - PHY Interface width"] +pub type PHYIF_R = crate::BitReader; +#[doc = "PHY Interface width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYIF_A { + #[doc = "0: `0`"] + _8BIT = 0, + #[doc = "1: `1`"] + _16BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYIF_A) -> Self { + variant as u8 != 0 + } +} +impl PHYIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYIF_A { + match self.bits { + false => PHYIF_A::_8BIT, + true => PHYIF_A::_16BIT, + } + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == PHYIF_A::_8BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == PHYIF_A::_16BIT + } +} +#[doc = "Field `PHYIF` writer - PHY Interface width"] +pub type PHYIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYIF_A, O>; +impl<'a, const O: u8> PHYIF_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(PHYIF_A::_8BIT) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(PHYIF_A::_16BIT) + } +} +#[doc = "Field `PHYTYPE` reader - PHY Type"] +pub type PHYTYPE_R = crate::BitReader; +#[doc = "PHY Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYTYPE_A { + #[doc = "0: `0`"] + UTMI = 0, + #[doc = "1: `1`"] + ULPI = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYTYPE_A) -> Self { + variant as u8 != 0 + } +} +impl PHYTYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYTYPE_A { + match self.bits { + false => PHYTYPE_A::UTMI, + true => PHYTYPE_A::ULPI, + } + } + #[doc = "Checks if the value of the field is `UTMI`"] + #[inline(always)] + pub fn is_utmi(&self) -> bool { + *self == PHYTYPE_A::UTMI + } + #[doc = "Checks if the value of the field is `ULPI`"] + #[inline(always)] + pub fn is_ulpi(&self) -> bool { + *self == PHYTYPE_A::ULPI + } +} +#[doc = "Field `PHYTYPE` writer - PHY Type"] +pub type PHYTYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYTYPE_A, O>; +impl<'a, const O: u8> PHYTYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn utmi(self) -> &'a mut W { + self.variant(PHYTYPE_A::UTMI) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ulpi(self) -> &'a mut W { + self.variant(PHYTYPE_A::ULPI) + } +} +#[doc = "Field `FSIF` reader - Full speed interface"] +pub type FSIF_R = crate::BitReader; +#[doc = "Full speed interface\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FSIF_A { + #[doc = "0: `0`"] + _6PIN = 0, + #[doc = "1: `1`"] + _3PIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FSIF_A) -> Self { + variant as u8 != 0 + } +} +impl FSIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSIF_A { + match self.bits { + false => FSIF_A::_6PIN, + true => FSIF_A::_3PIN, + } + } + #[doc = "Checks if the value of the field is `_6PIN`"] + #[inline(always)] + pub fn is_6pin(&self) -> bool { + *self == FSIF_A::_6PIN + } + #[doc = "Checks if the value of the field is `_3PIN`"] + #[inline(always)] + pub fn is_3pin(&self) -> bool { + *self == FSIF_A::_3PIN + } +} +#[doc = "Field `FSIF` writer - Full speed interface"] +pub type FSIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, FSIF_A, O>; +impl<'a, const O: u8> FSIF_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _6pin(self) -> &'a mut W { + self.variant(FSIF_A::_6PIN) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _3pin(self) -> &'a mut W { + self.variant(FSIF_A::_3PIN) + } +} +#[doc = "Field `PHYSEL` reader - Transceiver select"] +pub type PHYSEL_R = crate::BitReader; +#[doc = "Transceiver select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYSEL_A { + #[doc = "0: `0`"] + USB20 = 0, + #[doc = "1: `1`"] + USB11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYSEL_A) -> Self { + variant as u8 != 0 + } +} +impl PHYSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYSEL_A { + match self.bits { + false => PHYSEL_A::USB20, + true => PHYSEL_A::USB11, + } + } + #[doc = "Checks if the value of the field is `USB20`"] + #[inline(always)] + pub fn is_usb20(&self) -> bool { + *self == PHYSEL_A::USB20 + } + #[doc = "Checks if the value of the field is `USB11`"] + #[inline(always)] + pub fn is_usb11(&self) -> bool { + *self == PHYSEL_A::USB11 + } +} +#[doc = "Field `PHYSEL` writer - Transceiver select"] +pub type PHYSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYSEL_A, O>; +impl<'a, const O: u8> PHYSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn usb20(self) -> &'a mut W { + self.variant(PHYSEL_A::USB20) + } + #[doc = "`1`"] + #[inline(always)] + pub fn usb11(self) -> &'a mut W { + self.variant(PHYSEL_A::USB11) + } +} +#[doc = "Field `DDRSEL` reader - ULPI data rate"] +pub type DDRSEL_R = crate::BitReader; +#[doc = "ULPI data rate\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DDRSEL_A { + #[doc = "0: `0`"] + SINGLE = 0, + #[doc = "1: `1`"] + DOUBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DDRSEL_A) -> Self { + variant as u8 != 0 + } +} +impl DDRSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DDRSEL_A { + match self.bits { + false => DDRSEL_A::SINGLE, + true => DDRSEL_A::DOUBLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == DDRSEL_A::SINGLE + } + #[doc = "Checks if the value of the field is `DOUBLE`"] + #[inline(always)] + pub fn is_double(&self) -> bool { + *self == DDRSEL_A::DOUBLE + } +} +#[doc = "Field `DDRSEL` writer - ULPI data rate"] +pub type DDRSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, DDRSEL_A, O>; +impl<'a, const O: u8> DDRSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(DDRSEL_A::SINGLE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn double(self) -> &'a mut W { + self.variant(DDRSEL_A::DOUBLE) + } +} +#[doc = "Field `SRPCAP` reader - SRP-capable"] +pub type SRPCAP_R = crate::BitReader; +#[doc = "Field `SRPCAP` writer - SRP-capable"] +pub type SRPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `HNPCAP` reader - HNP-capable"] +pub type HNPCAP_R = crate::BitReader; +#[doc = "Field `HNPCAP` writer - HNP-capable"] +pub type HNPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `TRDT` reader - USB turnaround time"] +pub type TRDT_R = crate::FieldReader; +#[doc = "Field `TRDT` writer - USB turnaround time"] +pub type TRDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 4, O>; +#[doc = "Field `PHYLPCS` reader - PHY Low-power clock select"] +pub type PHYLPCS_R = crate::BitReader; +#[doc = "Field `PHYLPCS` writer - PHY Low-power clock select"] +pub type PHYLPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIFSLS` reader - ULPI FS/LS select"] +pub type ULPIFSLS_R = crate::BitReader; +#[doc = "Field `ULPIFSLS` writer - ULPI FS/LS select"] +pub type ULPIFSLS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIAR` reader - ULPI Auto-resume"] +pub type ULPIAR_R = crate::BitReader; +#[doc = "Field `ULPIAR` writer - ULPI Auto-resume"] +pub type ULPIAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPICSM` reader - ULPI Clock SuspendM"] +pub type ULPICSM_R = crate::BitReader; +#[doc = "Field `ULPICSM` writer - ULPI Clock SuspendM"] +pub type ULPICSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIEVBUSD` reader - ULPI External VBUS Drive"] +pub type ULPIEVBUSD_R = crate::BitReader; +#[doc = "Field `ULPIEVBUSD` writer - ULPI External VBUS Drive"] +pub type ULPIEVBUSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIEVBUSI` reader - ULPI external VBUS indicator"] +pub type ULPIEVBUSI_R = crate::BitReader; +#[doc = "Field `ULPIEVBUSI` writer - ULPI external VBUS indicator"] +pub type ULPIEVBUSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `TSDPS` reader - TermSel DLine pulsing selection"] +pub type TSDPS_R = crate::BitReader; +#[doc = "Field `TSDPS` writer - TermSel DLine pulsing selection"] +pub type TSDPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `PCCI` reader - Indicator complement"] +pub type PCCI_R = crate::BitReader; +#[doc = "Field `PCCI` writer - Indicator complement"] +pub type PCCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `PTCI` reader - Indicator pass through"] +pub type PTCI_R = crate::BitReader; +#[doc = "Field `PTCI` writer - Indicator pass through"] +pub type PTCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIIPD` reader - ULPI interface protect disable"] +pub type ULPIIPD_R = crate::BitReader; +#[doc = "Field `ULPIIPD` writer - ULPI interface protect disable"] +pub type ULPIIPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `FHMOD` reader - Forced host mode"] +pub type FHMOD_R = crate::BitReader; +#[doc = "Field `FHMOD` writer - Forced host mode"] +pub type FHMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `FDMOD` reader - Forced peripheral mode"] +pub type FDMOD_R = crate::BitReader; +#[doc = "Field `FDMOD` writer - Forced peripheral mode"] +pub type FDMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `CTXPKT` reader - Corrupt Tx packet"] +pub type CTXPKT_R = crate::BitReader; +#[doc = "Field `CTXPKT` writer - Corrupt Tx packet"] +pub type CTXPKT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - FS timeout calibration"] + #[inline(always)] + pub fn tocal(&self) -> TOCAL_R { + TOCAL_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - PHY Interface width"] + #[inline(always)] + pub fn phyif(&self) -> PHYIF_R { + PHYIF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PHY Type"] + #[inline(always)] + pub fn phytype(&self) -> PHYTYPE_R { + PHYTYPE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Full speed interface"] + #[inline(always)] + pub fn fsif(&self) -> FSIF_R { + FSIF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transceiver select"] + #[inline(always)] + pub fn physel(&self) -> PHYSEL_R { + PHYSEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ULPI data rate"] + #[inline(always)] + pub fn ddrsel(&self) -> DDRSEL_R { + DDRSEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SRP-capable"] + #[inline(always)] + pub fn srpcap(&self) -> SRPCAP_R { + SRPCAP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HNP-capable"] + #[inline(always)] + pub fn hnpcap(&self) -> HNPCAP_R { + HNPCAP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - USB turnaround time"] + #[inline(always)] + pub fn trdt(&self) -> TRDT_R { + TRDT_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bit 15 - PHY Low-power clock select"] + #[inline(always)] + pub fn phylpcs(&self) -> PHYLPCS_R { + PHYLPCS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - ULPI FS/LS select"] + #[inline(always)] + pub fn ulpifsls(&self) -> ULPIFSLS_R { + ULPIFSLS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - ULPI Auto-resume"] + #[inline(always)] + pub fn ulpiar(&self) -> ULPIAR_R { + ULPIAR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - ULPI Clock SuspendM"] + #[inline(always)] + pub fn ulpicsm(&self) -> ULPICSM_R { + ULPICSM_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - ULPI External VBUS Drive"] + #[inline(always)] + pub fn ulpievbusd(&self) -> ULPIEVBUSD_R { + ULPIEVBUSD_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ULPI external VBUS indicator"] + #[inline(always)] + pub fn ulpievbusi(&self) -> ULPIEVBUSI_R { + ULPIEVBUSI_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - TermSel DLine pulsing selection"] + #[inline(always)] + pub fn tsdps(&self) -> TSDPS_R { + TSDPS_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Indicator complement"] + #[inline(always)] + pub fn pcci(&self) -> PCCI_R { + PCCI_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Indicator pass through"] + #[inline(always)] + pub fn ptci(&self) -> PTCI_R { + PTCI_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - ULPI interface protect disable"] + #[inline(always)] + pub fn ulpiipd(&self) -> ULPIIPD_R { + ULPIIPD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 29 - Forced host mode"] + #[inline(always)] + pub fn fhmod(&self) -> FHMOD_R { + FHMOD_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Forced peripheral mode"] + #[inline(always)] + pub fn fdmod(&self) -> FDMOD_R { + FDMOD_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Corrupt Tx packet"] + #[inline(always)] + pub fn ctxpkt(&self) -> CTXPKT_R { + CTXPKT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - FS timeout calibration"] + #[inline(always)] + #[must_use] + pub fn tocal(&mut self) -> TOCAL_W<0> { + TOCAL_W::new(self) + } + #[doc = "Bit 3 - PHY Interface width"] + #[inline(always)] + #[must_use] + pub fn phyif(&mut self) -> PHYIF_W<3> { + PHYIF_W::new(self) + } + #[doc = "Bit 4 - PHY Type"] + #[inline(always)] + #[must_use] + pub fn phytype(&mut self) -> PHYTYPE_W<4> { + PHYTYPE_W::new(self) + } + #[doc = "Bit 5 - Full speed interface"] + #[inline(always)] + #[must_use] + pub fn fsif(&mut self) -> FSIF_W<5> { + FSIF_W::new(self) + } + #[doc = "Bit 6 - Transceiver select"] + #[inline(always)] + #[must_use] + pub fn physel(&mut self) -> PHYSEL_W<6> { + PHYSEL_W::new(self) + } + #[doc = "Bit 7 - ULPI data rate"] + #[inline(always)] + #[must_use] + pub fn ddrsel(&mut self) -> DDRSEL_W<7> { + DDRSEL_W::new(self) + } + #[doc = "Bit 8 - SRP-capable"] + #[inline(always)] + #[must_use] + pub fn srpcap(&mut self) -> SRPCAP_W<8> { + SRPCAP_W::new(self) + } + #[doc = "Bit 9 - HNP-capable"] + #[inline(always)] + #[must_use] + pub fn hnpcap(&mut self) -> HNPCAP_W<9> { + HNPCAP_W::new(self) + } + #[doc = "Bits 10:13 - USB turnaround time"] + #[inline(always)] + #[must_use] + pub fn trdt(&mut self) -> TRDT_W<10> { + TRDT_W::new(self) + } + #[doc = "Bit 15 - PHY Low-power clock select"] + #[inline(always)] + #[must_use] + pub fn phylpcs(&mut self) -> PHYLPCS_W<15> { + PHYLPCS_W::new(self) + } + #[doc = "Bit 17 - ULPI FS/LS select"] + #[inline(always)] + #[must_use] + pub fn ulpifsls(&mut self) -> ULPIFSLS_W<17> { + ULPIFSLS_W::new(self) + } + #[doc = "Bit 18 - ULPI Auto-resume"] + #[inline(always)] + #[must_use] + pub fn ulpiar(&mut self) -> ULPIAR_W<18> { + ULPIAR_W::new(self) + } + #[doc = "Bit 19 - ULPI Clock SuspendM"] + #[inline(always)] + #[must_use] + pub fn ulpicsm(&mut self) -> ULPICSM_W<19> { + ULPICSM_W::new(self) + } + #[doc = "Bit 20 - ULPI External VBUS Drive"] + #[inline(always)] + #[must_use] + pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<20> { + ULPIEVBUSD_W::new(self) + } + #[doc = "Bit 21 - ULPI external VBUS indicator"] + #[inline(always)] + #[must_use] + pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<21> { + ULPIEVBUSI_W::new(self) + } + #[doc = "Bit 22 - TermSel DLine pulsing selection"] + #[inline(always)] + #[must_use] + pub fn tsdps(&mut self) -> TSDPS_W<22> { + TSDPS_W::new(self) + } + #[doc = "Bit 23 - Indicator complement"] + #[inline(always)] + #[must_use] + pub fn pcci(&mut self) -> PCCI_W<23> { + PCCI_W::new(self) + } + #[doc = "Bit 24 - Indicator pass through"] + #[inline(always)] + #[must_use] + pub fn ptci(&mut self) -> PTCI_W<24> { + PTCI_W::new(self) + } + #[doc = "Bit 25 - ULPI interface protect disable"] + #[inline(always)] + #[must_use] + pub fn ulpiipd(&mut self) -> ULPIIPD_W<25> { + ULPIIPD_W::new(self) + } + #[doc = "Bit 29 - Forced host mode"] + #[inline(always)] + #[must_use] + pub fn fhmod(&mut self) -> FHMOD_W<29> { + FHMOD_W::new(self) + } + #[doc = "Bit 30 - Forced peripheral mode"] + #[inline(always)] + #[must_use] + pub fn fdmod(&mut self) -> FDMOD_W<30> { + FDMOD_W::new(self) + } + #[doc = "Bit 31 - Corrupt Tx packet"] + #[inline(always)] + #[must_use] + pub fn ctxpkt(&mut self) -> CTXPKT_W<31> { + CTXPKT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS USB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](index.html) module"] +pub struct GUSBCFG_SPEC; +impl crate::RegisterSpec for GUSBCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gusbcfg::R](R) reader structure"] +impl crate::Readable for GUSBCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gusbcfg::W](W) writer structure"] +impl crate::Writable for GUSBCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GUSBCFG to value 0x0a00"] +impl crate::Resettable for GUSBCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0a00; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs b/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs new file mode 100644 index 0000000..c50a180 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs @@ -0,0 +1,95 @@ +#[doc = "Register `HPTXFSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPTXFSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTXSA` reader - Host periodic TxFIFO start address"] +pub type PTXSA_R = crate::FieldReader; +#[doc = "Field `PTXSA` writer - Host periodic TxFIFO start address"] +pub type PTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +#[doc = "Field `PTXFD` reader - Host periodic TxFIFO depth"] +pub type PTXFD_R = crate::FieldReader; +#[doc = "Field `PTXFD` writer - Host periodic TxFIFO depth"] +pub type PTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] + #[inline(always)] + pub fn ptxsa(&self) -> PTXSA_R { + PTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] + #[inline(always)] + pub fn ptxfd(&self) -> PTXFD_R { + PTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] + #[inline(always)] + #[must_use] + pub fn ptxsa(&mut self) -> PTXSA_W<0> { + PTXSA_W::new(self) + } + #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ptxfd(&mut self) -> PTXFD_W<16> { + PTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](index.html) module"] +pub struct HPTXFSIZ_SPEC; +impl crate::RegisterSpec for HPTXFSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hptxfsiz::R](R) reader structure"] +impl crate::Readable for HPTXFSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](W) writer structure"] +impl crate::Writable for HPTXFSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPTXFSIZ to value 0x0200_0600"] +impl crate::Resettable for HPTXFSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0600; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs b/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs new file mode 100644 index 0000000..13715b7 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs @@ -0,0 +1,348 @@ +#[doc = "Register `HW_CONFIG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OPERATING_MODE` reader - Operating Mode"] +pub type OPERATING_MODE_R = crate::FieldReader; +#[doc = "Operating Mode"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OPERATING_MODE_A { + #[doc = "0: `0`"] + HNP_SRP_CAPABLE = 0, + #[doc = "1: `1`"] + SRP_ONLY_CAPABLE = 1, + #[doc = "2: `10`"] + NO_HNP_SRP_CAPABLE = 2, + #[doc = "3: `11`"] + SRP_CAPABLE_DEVICE = 3, + #[doc = "4: `100`"] + NO_SRP_CAPABLE_DEVICE = 4, + #[doc = "5: `101`"] + SRP_CAPABLE_HOST = 5, + #[doc = "6: `110`"] + NO_SRP_CAPABLE_HOST = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OPERATING_MODE_A) -> Self { + variant as _ + } +} +impl OPERATING_MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OPERATING_MODE_A::HNP_SRP_CAPABLE), + 1 => Some(OPERATING_MODE_A::SRP_ONLY_CAPABLE), + 2 => Some(OPERATING_MODE_A::NO_HNP_SRP_CAPABLE), + 3 => Some(OPERATING_MODE_A::SRP_CAPABLE_DEVICE), + 4 => Some(OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE), + 5 => Some(OPERATING_MODE_A::SRP_CAPABLE_HOST), + 6 => Some(OPERATING_MODE_A::NO_SRP_CAPABLE_HOST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `HNP_SRP_CAPABLE`"] + #[inline(always)] + pub fn is_hnp_srp_capable(&self) -> bool { + *self == OPERATING_MODE_A::HNP_SRP_CAPABLE + } + #[doc = "Checks if the value of the field is `SRP_ONLY_CAPABLE`"] + #[inline(always)] + pub fn is_srp_only_capable(&self) -> bool { + *self == OPERATING_MODE_A::SRP_ONLY_CAPABLE + } + #[doc = "Checks if the value of the field is `NO_HNP_SRP_CAPABLE`"] + #[inline(always)] + pub fn is_no_hnp_srp_capable(&self) -> bool { + *self == OPERATING_MODE_A::NO_HNP_SRP_CAPABLE + } + #[doc = "Checks if the value of the field is `SRP_CAPABLE_DEVICE`"] + #[inline(always)] + pub fn is_srp_capable_device(&self) -> bool { + *self == OPERATING_MODE_A::SRP_CAPABLE_DEVICE + } + #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_DEVICE`"] + #[inline(always)] + pub fn is_no_srp_capable_device(&self) -> bool { + *self == OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE + } + #[doc = "Checks if the value of the field is `SRP_CAPABLE_HOST`"] + #[inline(always)] + pub fn is_srp_capable_host(&self) -> bool { + *self == OPERATING_MODE_A::SRP_CAPABLE_HOST + } + #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_HOST`"] + #[inline(always)] + pub fn is_no_srp_capable_host(&self) -> bool { + *self == OPERATING_MODE_A::NO_SRP_CAPABLE_HOST + } +} +#[doc = "Field `ARCHITECTURE` reader - Architecture"] +pub type ARCHITECTURE_R = crate::FieldReader; +#[doc = "Architecture"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ARCHITECTURE_A { + #[doc = "0: `0`"] + SLAVE_ONLY = 0, + #[doc = "1: `1`"] + EXTERNAL_DMA = 1, + #[doc = "2: `10`"] + INTERNAL_DMA = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ARCHITECTURE_A) -> Self { + variant as _ + } +} +impl ARCHITECTURE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ARCHITECTURE_A::SLAVE_ONLY), + 1 => Some(ARCHITECTURE_A::EXTERNAL_DMA), + 2 => Some(ARCHITECTURE_A::INTERNAL_DMA), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SLAVE_ONLY`"] + #[inline(always)] + pub fn is_slave_only(&self) -> bool { + *self == ARCHITECTURE_A::SLAVE_ONLY + } + #[doc = "Checks if the value of the field is `EXTERNAL_DMA`"] + #[inline(always)] + pub fn is_external_dma(&self) -> bool { + *self == ARCHITECTURE_A::EXTERNAL_DMA + } + #[doc = "Checks if the value of the field is `INTERNAL_DMA`"] + #[inline(always)] + pub fn is_internal_dma(&self) -> bool { + *self == ARCHITECTURE_A::INTERNAL_DMA + } +} +#[doc = "Field `POINT_TO_POINT` reader - Point to Point"] +pub type POINT_TO_POINT_R = crate::BitReader; +#[doc = "Field `HIGH_SPEED_PHY` reader - High Speed Physical"] +pub type HIGH_SPEED_PHY_R = crate::FieldReader; +#[doc = "High Speed Physical"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HIGH_SPEED_PHY_A { + #[doc = "0: `0`"] + NOT_SUPPORTED = 0, + #[doc = "1: `1`"] + UTMI = 1, + #[doc = "2: `10`"] + ULPI = 2, + #[doc = "3: `11`"] + UTMI_ULPI = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HIGH_SPEED_PHY_A) -> Self { + variant as _ + } +} +impl HIGH_SPEED_PHY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HIGH_SPEED_PHY_A { + match self.bits { + 0 => HIGH_SPEED_PHY_A::NOT_SUPPORTED, + 1 => HIGH_SPEED_PHY_A::UTMI, + 2 => HIGH_SPEED_PHY_A::ULPI, + 3 => HIGH_SPEED_PHY_A::UTMI_ULPI, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NOT_SUPPORTED`"] + #[inline(always)] + pub fn is_not_supported(&self) -> bool { + *self == HIGH_SPEED_PHY_A::NOT_SUPPORTED + } + #[doc = "Checks if the value of the field is `UTMI`"] + #[inline(always)] + pub fn is_utmi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::UTMI + } + #[doc = "Checks if the value of the field is `ULPI`"] + #[inline(always)] + pub fn is_ulpi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::ULPI + } + #[doc = "Checks if the value of the field is `UTMI_ULPI`"] + #[inline(always)] + pub fn is_utmi_ulpi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::UTMI_ULPI + } +} +#[doc = "Field `FULL_SPEED_PHY` reader - Full Speed Physical"] +pub type FULL_SPEED_PHY_R = crate::FieldReader; +#[doc = "Full Speed Physical"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FULL_SPEED_PHY_A { + #[doc = "0: `0`"] + PHY0 = 0, + #[doc = "1: `1`"] + DEDICATED = 1, + #[doc = "2: `10`"] + PHY2 = 2, + #[doc = "3: `11`"] + PHY3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FULL_SPEED_PHY_A) -> Self { + variant as _ + } +} +impl FULL_SPEED_PHY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FULL_SPEED_PHY_A { + match self.bits { + 0 => FULL_SPEED_PHY_A::PHY0, + 1 => FULL_SPEED_PHY_A::DEDICATED, + 2 => FULL_SPEED_PHY_A::PHY2, + 3 => FULL_SPEED_PHY_A::PHY3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PHY0`"] + #[inline(always)] + pub fn is_phy0(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY0 + } + #[doc = "Checks if the value of the field is `DEDICATED`"] + #[inline(always)] + pub fn is_dedicated(&self) -> bool { + *self == FULL_SPEED_PHY_A::DEDICATED + } + #[doc = "Checks if the value of the field is `PHY2`"] + #[inline(always)] + pub fn is_phy2(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY2 + } + #[doc = "Checks if the value of the field is `PHY3`"] + #[inline(always)] + pub fn is_phy3(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY3 + } +} +#[doc = "Field `DEVICE_END_POINT_COUNT` reader - Device end point count"] +pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; +#[doc = "Field `HOST_CHANNEL_COUNT` reader - Host channel count"] +pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; +#[doc = "Field `SUPPORTS_PERIODIC_ENDPOINTS` reader - Supports periodic endpoints"] +pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; +#[doc = "Field `DYNAMIC_FIFO` reader - Dynamic FIFO"] +pub type DYNAMIC_FIFO_R = crate::BitReader; +#[doc = "Field `MULTI_PROC_INT` reader - Multi proc int"] +pub type MULTI_PROC_INT_R = crate::BitReader; +#[doc = "Field `NON_PERIODIC_QUEUE_DEPTH` reader - Non periodic queue depth"] +pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `HOST_PERIODIC_QUEUE_DEPTH` reader - Host periodic queue depth"] +pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `DEVICE_TOKEN_QUEUE_DEPTH` reader - Device token queue depth"] +pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `ENABLE_IC_USB` reader - Enable IC USB"] +pub type ENABLE_IC_USB_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Operating Mode"] + #[inline(always)] + pub fn operating_mode(&self) -> OPERATING_MODE_R { + OPERATING_MODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Architecture"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Point to Point"] + #[inline(always)] + pub fn point_to_point(&self) -> POINT_TO_POINT_R { + POINT_TO_POINT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - High Speed Physical"] + #[inline(always)] + pub fn high_speed_phy(&self) -> HIGH_SPEED_PHY_R { + HIGH_SPEED_PHY_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Full Speed Physical"] + #[inline(always)] + pub fn full_speed_phy(&self) -> FULL_SPEED_PHY_R { + FULL_SPEED_PHY_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:13 - Device end point count"] + #[inline(always)] + pub fn device_end_point_count(&self) -> DEVICE_END_POINT_COUNT_R { + DEVICE_END_POINT_COUNT_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:17 - Host channel count"] + #[inline(always)] + pub fn host_channel_count(&self) -> HOST_CHANNEL_COUNT_R { + HOST_CHANNEL_COUNT_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bit 18 - Supports periodic endpoints"] + #[inline(always)] + pub fn supports_periodic_endpoints(&self) -> SUPPORTS_PERIODIC_ENDPOINTS_R { + SUPPORTS_PERIODIC_ENDPOINTS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Dynamic FIFO"] + #[inline(always)] + pub fn dynamic_fifo(&self) -> DYNAMIC_FIFO_R { + DYNAMIC_FIFO_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Multi proc int"] + #[inline(always)] + pub fn multi_proc_int(&self) -> MULTI_PROC_INT_R { + MULTI_PROC_INT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 22:23 - Non periodic queue depth"] + #[inline(always)] + pub fn non_periodic_queue_depth(&self) -> NON_PERIODIC_QUEUE_DEPTH_R { + NON_PERIODIC_QUEUE_DEPTH_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Host periodic queue depth"] + #[inline(always)] + pub fn host_periodic_queue_depth(&self) -> HOST_PERIODIC_QUEUE_DEPTH_R { + HOST_PERIODIC_QUEUE_DEPTH_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:30 - Device token queue depth"] + #[inline(always)] + pub fn device_token_queue_depth(&self) -> DEVICE_TOKEN_QUEUE_DEPTH_R { + DEVICE_TOKEN_QUEUE_DEPTH_R::new(((self.bits >> 26) & 0x1f) as u8) + } + #[doc = "Bit 31 - Enable IC USB"] + #[inline(always)] + pub fn enable_ic_usb(&self) -> ENABLE_IC_USB_R { + ENABLE_IC_USB_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Hardware Config 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_config0](index.html) module"] +pub struct HW_CONFIG0_SPEC; +impl crate::RegisterSpec for HW_CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hw_config0::R](R) reader structure"] +impl crate::Readable for HW_CONFIG0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs b/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs new file mode 100644 index 0000000..1ca29d0 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs @@ -0,0 +1,157 @@ +#[doc = "Register `HW_DIRECTION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DIRECTION[0-15]` reader - Direction %s"] +pub type DIRECTION_R = crate::FieldReader; +#[doc = "Direction %s"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + BIDIR = 0, + #[doc = "1: `1`"] + IN = 1, + #[doc = "2: `10`"] + OUT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as _ + } +} +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DIRECTION_A::BIDIR), + 1 => Some(DIRECTION_A::IN), + 2 => Some(DIRECTION_A::OUT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BIDIR`"] + #[inline(always)] + pub fn is_bidir(&self) -> bool { + *self == DIRECTION_A::BIDIR + } + #[doc = "Checks if the value of the field is `IN`"] + #[inline(always)] + pub fn is_in(&self) -> bool { + *self == DIRECTION_A::IN + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + *self == DIRECTION_A::OUT + } +} +impl R { + #[doc = "Direction [0-15]"] + #[inline(always)] + pub unsafe fn direction(&self, n: u8) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> (n * 2)) & 3) as u8) + } + #[doc = "Bits 0:1 - Direction 0"] + #[inline(always)] + pub fn direction0(&self) -> DIRECTION_R { + DIRECTION_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Direction 1"] + #[inline(always)] + pub fn direction1(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Direction 2"] + #[inline(always)] + pub fn direction2(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Direction 3"] + #[inline(always)] + pub fn direction3(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Direction 4"] + #[inline(always)] + pub fn direction4(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Direction 5"] + #[inline(always)] + pub fn direction5(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Direction 6"] + #[inline(always)] + pub fn direction6(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Direction 7"] + #[inline(always)] + pub fn direction7(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Direction 8"] + #[inline(always)] + pub fn direction8(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Direction 9"] + #[inline(always)] + pub fn direction9(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Direction 10"] + #[inline(always)] + pub fn direction10(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Direction 11"] + #[inline(always)] + pub fn direction11(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Direction 12"] + #[inline(always)] + pub fn direction12(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Direction 13"] + #[inline(always)] + pub fn direction13(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Direction 14"] + #[inline(always)] + pub fn direction14(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Direction 15"] + #[inline(always)] + pub fn direction15(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[doc = "Direction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_direction](index.html) module"] +pub struct HW_DIRECTION_SPEC; +impl crate::RegisterSpec for HW_DIRECTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hw_direction::R](R) reader structure"] +impl crate::Readable for HW_DIRECTION_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs b/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs new file mode 100644 index 0000000..8734146 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs @@ -0,0 +1,97 @@ +#[doc = "Register `TX0FSIZ_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TX0FSIZ_Peripheral` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TX0FSA` reader - Endpoint 0 transmit RAM start address"] +pub type TX0FSA_R = crate::FieldReader; +#[doc = "Field `TX0FSA` writer - Endpoint 0 transmit RAM start address"] +pub type TX0FSA_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +#[doc = "Field `TX0FD` reader - Endpoint 0 TxFIFO depth"] +pub type TX0FD_R = crate::FieldReader; +#[doc = "Field `TX0FD` writer - Endpoint 0 TxFIFO depth"] +pub type TX0FD_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] + #[inline(always)] + pub fn tx0fsa(&self) -> TX0FSA_R { + TX0FSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] + #[inline(always)] + pub fn tx0fd(&self) -> TX0FD_R { + TX0FD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn tx0fsa(&mut self) -> TX0FSA_W<0> { + TX0FSA_W::new(self) + } + #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn tx0fd(&mut self) -> TX0FD_W<16> { + TX0FD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx0fsiz_peripheral](index.html) module"] +pub struct TX0FSIZ_PERIPHERAL_SPEC; +impl crate::RegisterSpec for TX0FSIZ_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx0fsiz_peripheral::R](R) reader structure"] +impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tx0fsiz_peripheral::W](W) writer structure"] +impl crate::Writable for TX0FSIZ_PERIPHERAL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX0FSIZ_Peripheral to value 0x0200"] +impl crate::Resettable for TX0FSIZ_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/vid.rs b/crates/bcm2711-lpa/src/usb_otg_global/vid.rs new file mode 100644 index 0000000..ae468f7 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_global/vid.rs @@ -0,0 +1,24 @@ +#[doc = "Register `VID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "OTG_HS vendor ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vid](index.html) module"] +pub struct VID_SPEC; +impl crate::RegisterSpec for VID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vid::R](R) reader structure"] +impl crate::Readable for VID_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host.rs b/crates/bcm2711-lpa/src/usb_otg_host.rs new file mode 100644 index 0000000..c2b6fb8 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host.rs @@ -0,0 +1,89 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS host configuration register"] + pub hcfg: HCFG, + #[doc = "0x04 - OTG_HS Host frame interval register"] + pub hfir: HFIR, + #[doc = "0x08 - OTG_HS host frame number/frame time remaining register"] + pub hfnum: HFNUM, + _reserved3: [u8; 0x04], + #[doc = "0x10 - Host periodic transmit FIFO/queue status register"] + pub hptxsts: HPTXSTS, + #[doc = "0x14 - OTG_HS Host all channels interrupt register"] + pub haint: HAINT, + #[doc = "0x18 - OTG_HS host all channels interrupt mask register"] + pub haintmsk: HAINTMSK, + _reserved6: [u8; 0x24], + #[doc = "0x40 - OTG_HS host port control and status register"] + pub hprt: HPRT, + _reserved7: [u8; 0xbc], + #[doc = "0x100..0x118 - Host channel %s"] + pub host_channel0: HOST_CHANNEL, + _reserved8: [u8; 0x08], + #[doc = "0x120..0x138 - Host channel %s"] + pub host_channel1: HOST_CHANNEL, + _reserved9: [u8; 0x08], + #[doc = "0x140..0x158 - Host channel %s"] + pub host_channel2: HOST_CHANNEL, + _reserved10: [u8; 0x08], + #[doc = "0x160..0x178 - Host channel %s"] + pub host_channel3: HOST_CHANNEL, + _reserved11: [u8; 0x08], + #[doc = "0x180..0x198 - Host channel %s"] + pub host_channel4: HOST_CHANNEL, + _reserved12: [u8; 0x08], + #[doc = "0x1a0..0x1b8 - Host channel %s"] + pub host_channel5: HOST_CHANNEL, + _reserved13: [u8; 0x08], + #[doc = "0x1c0..0x1d8 - Host channel %s"] + pub host_channel6: HOST_CHANNEL, + _reserved14: [u8; 0x08], + #[doc = "0x1e0..0x1f8 - Host channel %s"] + pub host_channel7: HOST_CHANNEL, + _reserved15: [u8; 0x08], + #[doc = "0x200..0x218 - Host channel %s"] + pub host_channel8: HOST_CHANNEL, + _reserved16: [u8; 0x08], + #[doc = "0x220..0x238 - Host channel %s"] + pub host_channel9: HOST_CHANNEL, + _reserved17: [u8; 0x08], + #[doc = "0x240..0x258 - Host channel %s"] + pub host_channel10: HOST_CHANNEL, + _reserved18: [u8; 0x08], + #[doc = "0x260..0x278 - Host channel %s"] + pub host_channel11: HOST_CHANNEL, +} +#[doc = "HCFG (rw) register accessor: an alias for `Reg`"] +pub type HCFG = crate::Reg; +#[doc = "OTG_HS host configuration register"] +pub mod hcfg; +#[doc = "HFIR (rw) register accessor: an alias for `Reg`"] +pub type HFIR = crate::Reg; +#[doc = "OTG_HS Host frame interval register"] +pub mod hfir; +#[doc = "HFNUM (r) register accessor: an alias for `Reg`"] +pub type HFNUM = crate::Reg; +#[doc = "OTG_HS host frame number/frame time remaining register"] +pub mod hfnum; +#[doc = "HPTXSTS (rw) register accessor: an alias for `Reg`"] +pub type HPTXSTS = crate::Reg; +#[doc = "Host periodic transmit FIFO/queue status register"] +pub mod hptxsts; +#[doc = "HAINT (r) register accessor: an alias for `Reg`"] +pub type HAINT = crate::Reg; +#[doc = "OTG_HS Host all channels interrupt register"] +pub mod haint; +#[doc = "HAINTMSK (rw) register accessor: an alias for `Reg`"] +pub type HAINTMSK = crate::Reg; +#[doc = "OTG_HS host all channels interrupt mask register"] +pub mod haintmsk; +#[doc = "HPRT (rw) register accessor: an alias for `Reg`"] +pub type HPRT = crate::Reg; +#[doc = "OTG_HS host port control and status register"] +pub mod hprt; +#[doc = "Host channel %s"] +pub use self::host_channel::HOST_CHANNEL; +#[doc = r"Cluster"] +#[doc = "Host channel %s"] +pub mod host_channel; diff --git a/crates/bcm2711-lpa/src/usb_otg_host/haint.rs b/crates/bcm2711-lpa/src/usb_otg_host/haint.rs new file mode 100644 index 0000000..16455f3 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/haint.rs @@ -0,0 +1,37 @@ +#[doc = "Register `HAINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HAINT` reader - Channel interrupts"] +pub type HAINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Channel interrupts"] + #[inline(always)] + pub fn haint(&self) -> HAINT_R { + HAINT_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "OTG_HS Host all channels interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](index.html) module"] +pub struct HAINT_SPEC; +impl crate::RegisterSpec for HAINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [haint::R](R) reader structure"] +impl crate::Readable for HAINT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HAINT to value 0"] +impl crate::Resettable for HAINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs new file mode 100644 index 0000000..69df5e9 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HAINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HAINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HAINTM` reader - Channel interrupt mask"] +pub type HAINTM_R = crate::FieldReader; +#[doc = "Field `HAINTM` writer - Channel interrupt mask"] +pub type HAINTM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HAINTMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Channel interrupt mask"] + #[inline(always)] + pub fn haintm(&self) -> HAINTM_R { + HAINTM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Channel interrupt mask"] + #[inline(always)] + #[must_use] + pub fn haintm(&mut self) -> HAINTM_W<0> { + HAINTM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host all channels interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](index.html) module"] +pub struct HAINTMSK_SPEC; +impl crate::RegisterSpec for HAINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [haintmsk::R](R) reader structure"] +impl crate::Readable for HAINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [haintmsk::W](W) writer structure"] +impl crate::Writable for HAINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HAINTMSK to value 0"] +impl crate::Resettable for HAINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs b/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs new file mode 100644 index 0000000..17f4b01 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs @@ -0,0 +1,87 @@ +#[doc = "Register `HCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSLSPCS` reader - FS/LS PHY clock select"] +pub type FSLSPCS_R = crate::FieldReader; +#[doc = "Field `FSLSPCS` writer - FS/LS PHY clock select"] +pub type FSLSPCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `FSLSS` reader - FS- and LS-only support"] +pub type FSLSS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - FS/LS PHY clock select"] + #[inline(always)] + pub fn fslspcs(&self) -> FSLSPCS_R { + FSLSPCS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - FS- and LS-only support"] + #[inline(always)] + pub fn fslss(&self) -> FSLSS_R { + FSLSS_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - FS/LS PHY clock select"] + #[inline(always)] + #[must_use] + pub fn fslspcs(&mut self) -> FSLSPCS_W<0> { + FSLSPCS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"] +pub struct HCFG_SPEC; +impl crate::RegisterSpec for HCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcfg::R](R) reader structure"] +impl crate::Readable for HCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"] +impl crate::Writable for HCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCFG to value 0"] +impl crate::Resettable for HCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs b/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs new file mode 100644 index 0000000..9182ff2 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HFIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HFIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FRIVL` reader - Frame interval"] +pub type FRIVL_R = crate::FieldReader; +#[doc = "Field `FRIVL` writer - Frame interval"] +pub type FRIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFIR_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Frame interval"] + #[inline(always)] + pub fn frivl(&self) -> FRIVL_R { + FRIVL_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Frame interval"] + #[inline(always)] + #[must_use] + pub fn frivl(&mut self) -> FRIVL_W<0> { + FRIVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Host frame interval register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](index.html) module"] +pub struct HFIR_SPEC; +impl crate::RegisterSpec for HFIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfir::R](R) reader structure"] +impl crate::Readable for HFIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hfir::W](W) writer structure"] +impl crate::Writable for HFIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HFIR to value 0xea60"] +impl crate::Resettable for HFIR_SPEC { + const RESET_VALUE: Self::Ux = 0xea60; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs b/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs new file mode 100644 index 0000000..0df982a --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HFNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FRNUM` reader - Frame number"] +pub type FRNUM_R = crate::FieldReader; +#[doc = "Field `FTREM` reader - Frame time remaining"] +pub type FTREM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Frame number"] + #[inline(always)] + pub fn frnum(&self) -> FRNUM_R { + FRNUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Frame time remaining"] + #[inline(always)] + pub fn ftrem(&self) -> FTREM_R { + FTREM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "OTG_HS host frame number/frame time remaining register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](index.html) module"] +pub struct HFNUM_SPEC; +impl crate::RegisterSpec for HFNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfnum::R](R) reader structure"] +impl crate::Readable for HFNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HFNUM to value 0x3fff"] +impl crate::Resettable for HFNUM_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs new file mode 100644 index 0000000..ee4a815 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST_CHANNEL { + #[doc = "0x00 - Characteristics register"] + pub hcchar: HCCHAR, + #[doc = "0x04 - Split control register"] + pub hcsplt: HCSPLT, + #[doc = "0x08 - Interrupt register"] + pub hcint: HCINT, + #[doc = "0x0c - Interrupt mask"] + pub hcintmsk: HCINTMSK, + #[doc = "0x10 - Transfer size"] + pub hctsiz: HCTSIZ, + #[doc = "0x14 - DMA address"] + pub hcdma: HCDMA, +} +#[doc = "HCCHAR (rw) register accessor: an alias for `Reg`"] +pub type HCCHAR = crate::Reg; +#[doc = "Characteristics register"] +pub mod hcchar; +#[doc = "HCSPLT (rw) register accessor: an alias for `Reg`"] +pub type HCSPLT = crate::Reg; +#[doc = "Split control register"] +pub mod hcsplt; +#[doc = "HCINT (rw) register accessor: an alias for `Reg`"] +pub type HCINT = crate::Reg; +#[doc = "Interrupt register"] +pub mod hcint; +#[doc = "HCINTMSK (rw) register accessor: an alias for `Reg`"] +pub type HCINTMSK = crate::Reg; +#[doc = "Interrupt mask"] +pub mod hcintmsk; +#[doc = "HCTSIZ (rw) register accessor: an alias for `Reg`"] +pub type HCTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod hctsiz; +#[doc = "HCDMA (rw) register accessor: an alias for `Reg`"] +pub type HCDMA = crate::Reg; +#[doc = "DMA address"] +pub mod hcdma; diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs new file mode 100644 index 0000000..d73f560 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs @@ -0,0 +1,215 @@ +#[doc = "Register `HCCHAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCCHAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `MPSIZ` writer - Maximum packet size"] +pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u16, u16, 11, O>; +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `EPNUM` writer - Endpoint number"] +pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 4, O>; +#[doc = "Field `EPDIR` reader - Endpoint direction"] +pub type EPDIR_R = crate::BitReader; +#[doc = "Field `EPDIR` writer - Endpoint direction"] +pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `LSDEV` reader - Low-speed device"] +pub type LSDEV_R = crate::BitReader; +#[doc = "Field `LSDEV` writer - Low-speed device"] +pub type LSDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `EPTYP` writer - Endpoint type"] +pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +#[doc = "Field `MC` reader - Multi Count (MC) / Error Count (EC)"] +pub type MC_R = crate::FieldReader; +#[doc = "Field `MC` writer - Multi Count (MC) / Error Count (EC)"] +pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +#[doc = "Field `DAD` reader - Device address"] +pub type DAD_R = crate::FieldReader; +#[doc = "Field `DAD` writer - Device address"] +pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 7, O>; +#[doc = "Field `ODDFRM` reader - Odd frame"] +pub type ODDFRM_R = crate::BitReader; +#[doc = "Field `ODDFRM` writer - Odd frame"] +pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `CHDIS` reader - Channel disable"] +pub type CHDIS_R = crate::BitReader; +#[doc = "Field `CHDIS` writer - Channel disable"] +pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `CHENA` reader - Channel enable"] +pub type CHENA_R = crate::BitReader; +#[doc = "Field `CHENA` writer - Channel enable"] +pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:14 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8) + } + #[doc = "Bit 15 - Endpoint direction"] + #[inline(always)] + pub fn epdir(&self) -> EPDIR_R { + EPDIR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Low-speed device"] + #[inline(always)] + pub fn lsdev(&self) -> LSDEV_R { + LSDEV_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] + #[inline(always)] + pub fn mc(&self) -> MC_R { + MC_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:28 - Device address"] + #[inline(always)] + pub fn dad(&self) -> DAD_R { + DAD_R::new(((self.bits >> 22) & 0x7f) as u8) + } + #[doc = "Bit 29 - Odd frame"] + #[inline(always)] + pub fn oddfrm(&self) -> ODDFRM_R { + ODDFRM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Channel disable"] + #[inline(always)] + pub fn chdis(&self) -> CHDIS_R { + CHDIS_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Channel enable"] + #[inline(always)] + pub fn chena(&self) -> CHENA_R { + CHENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + #[must_use] + pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + MPSIZ_W::new(self) + } + #[doc = "Bits 11:14 - Endpoint number"] + #[inline(always)] + #[must_use] + pub fn epnum(&mut self) -> EPNUM_W<11> { + EPNUM_W::new(self) + } + #[doc = "Bit 15 - Endpoint direction"] + #[inline(always)] + #[must_use] + pub fn epdir(&mut self) -> EPDIR_W<15> { + EPDIR_W::new(self) + } + #[doc = "Bit 17 - Low-speed device"] + #[inline(always)] + #[must_use] + pub fn lsdev(&mut self) -> LSDEV_W<17> { + LSDEV_W::new(self) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + #[must_use] + pub fn eptyp(&mut self) -> EPTYP_W<18> { + EPTYP_W::new(self) + } + #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] + #[inline(always)] + #[must_use] + pub fn mc(&mut self) -> MC_W<20> { + MC_W::new(self) + } + #[doc = "Bits 22:28 - Device address"] + #[inline(always)] + #[must_use] + pub fn dad(&mut self) -> DAD_W<22> { + DAD_W::new(self) + } + #[doc = "Bit 29 - Odd frame"] + #[inline(always)] + #[must_use] + pub fn oddfrm(&mut self) -> ODDFRM_W<29> { + ODDFRM_W::new(self) + } + #[doc = "Bit 30 - Channel disable"] + #[inline(always)] + #[must_use] + pub fn chdis(&mut self) -> CHDIS_W<30> { + CHDIS_W::new(self) + } + #[doc = "Bit 31 - Channel enable"] + #[inline(always)] + #[must_use] + pub fn chena(&mut self) -> CHENA_W<31> { + CHENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Characteristics register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcchar](index.html) module"] +pub struct HCCHAR_SPEC; +impl crate::RegisterSpec for HCCHAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcchar::R](R) reader structure"] +impl crate::Readable for HCCHAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcchar::W](W) writer structure"] +impl crate::Writable for HCCHAR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCCHAR to value 0"] +impl crate::Resettable for HCCHAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs new file mode 100644 index 0000000..bfcef2a --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HCDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcdma](index.html) module"] +pub struct HCDMA_SPEC; +impl crate::RegisterSpec for HCDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcdma::R](R) reader structure"] +impl crate::Readable for HCDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcdma::W](W) writer structure"] +impl crate::Writable for HCDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCDMA to value 0"] +impl crate::Resettable for HCDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs new file mode 100644 index 0000000..a8ef9ea --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs @@ -0,0 +1,230 @@ +#[doc = "Register `HCINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `CHH` reader - Channel halted"] +pub type CHH_R = crate::BitReader; +#[doc = "Field `CHH` writer - Channel halted"] +pub type CHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `AHBERR` reader - AHB error"] +pub type AHBERR_R = crate::BitReader; +#[doc = "Field `AHBERR` writer - AHB error"] +pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `STALL` reader - STALL response received interrupt"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `STALL` writer - STALL response received interrupt"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `NAK` reader - NAK response received interrupt"] +pub type NAK_R = crate::BitReader; +#[doc = "Field `NAK` writer - NAK response received interrupt"] +pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `ACK` reader - ACK response received/transmitted interrupt"] +pub type ACK_R = crate::BitReader; +#[doc = "Field `ACK` writer - ACK response received/transmitted interrupt"] +pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `NYET` reader - Response received interrupt"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - Response received interrupt"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `TXERR` reader - Transaction error"] +pub type TXERR_R = crate::BitReader; +#[doc = "Field `TXERR` writer - Transaction error"] +pub type TXERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `BBERR` reader - Babble error"] +pub type BBERR_R = crate::BitReader; +#[doc = "Field `BBERR` writer - Babble error"] +pub type BBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `FRMOR` reader - Frame overrun"] +pub type FRMOR_R = crate::BitReader; +#[doc = "Field `FRMOR` writer - Frame overrun"] +pub type FRMOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `DTERR` reader - Data toggle error"] +pub type DTERR_R = crate::BitReader; +#[doc = "Field `DTERR` writer - Data toggle error"] +pub type DTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel halted"] + #[inline(always)] + pub fn chh(&self) -> CHH_R { + CHH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + pub fn ahberr(&self) -> AHBERR_R { + AHBERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STALL response received interrupt"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NAK response received interrupt"] + #[inline(always)] + pub fn nak(&self) -> NAK_R { + NAK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt"] + #[inline(always)] + pub fn ack(&self) -> ACK_R { + ACK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Response received interrupt"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transaction error"] + #[inline(always)] + pub fn txerr(&self) -> TXERR_R { + TXERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Babble error"] + #[inline(always)] + pub fn bberr(&self) -> BBERR_R { + BBERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame overrun"] + #[inline(always)] + pub fn frmor(&self) -> FRMOR_R { + FRMOR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data toggle error"] + #[inline(always)] + pub fn dterr(&self) -> DTERR_R { + DTERR_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Channel halted"] + #[inline(always)] + #[must_use] + pub fn chh(&mut self) -> CHH_W<1> { + CHH_W::new(self) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + #[must_use] + pub fn ahberr(&mut self) -> AHBERR_W<2> { + AHBERR_W::new(self) + } + #[doc = "Bit 3 - STALL response received interrupt"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<3> { + STALL_W::new(self) + } + #[doc = "Bit 4 - NAK response received interrupt"] + #[inline(always)] + #[must_use] + pub fn nak(&mut self) -> NAK_W<4> { + NAK_W::new(self) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt"] + #[inline(always)] + #[must_use] + pub fn ack(&mut self) -> ACK_W<5> { + ACK_W::new(self) + } + #[doc = "Bit 6 - Response received interrupt"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<6> { + NYET_W::new(self) + } + #[doc = "Bit 7 - Transaction error"] + #[inline(always)] + #[must_use] + pub fn txerr(&mut self) -> TXERR_W<7> { + TXERR_W::new(self) + } + #[doc = "Bit 8 - Babble error"] + #[inline(always)] + #[must_use] + pub fn bberr(&mut self) -> BBERR_W<8> { + BBERR_W::new(self) + } + #[doc = "Bit 9 - Frame overrun"] + #[inline(always)] + #[must_use] + pub fn frmor(&mut self) -> FRMOR_W<9> { + FRMOR_W::new(self) + } + #[doc = "Bit 10 - Data toggle error"] + #[inline(always)] + #[must_use] + pub fn dterr(&mut self) -> DTERR_W<10> { + DTERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcint](index.html) module"] +pub struct HCINT_SPEC; +impl crate::RegisterSpec for HCINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcint::R](R) reader structure"] +impl crate::Readable for HCINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcint::W](W) writer structure"] +impl crate::Writable for HCINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCINT to value 0"] +impl crate::Resettable for HCINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs new file mode 100644 index 0000000..e158cb4 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs @@ -0,0 +1,230 @@ +#[doc = "Register `HCINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `CHHM` reader - Channel halted mask"] +pub type CHHM_R = crate::BitReader; +#[doc = "Field `CHHM` writer - Channel halted mask"] +pub type CHHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `AHBERR` reader - AHB error"] +pub type AHBERR_R = crate::BitReader; +#[doc = "Field `AHBERR` writer - AHB error"] +pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `STALLM` reader - STALL response received interrupt mask"] +pub type STALLM_R = crate::BitReader; +#[doc = "Field `STALLM` writer - STALL response received interrupt mask"] +pub type STALLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK response received interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK response received interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `ACKM` reader - ACK response received/transmitted interrupt mask"] +pub type ACKM_R = crate::BitReader; +#[doc = "Field `ACKM` writer - ACK response received/transmitted interrupt mask"] +pub type ACKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `NYET` reader - response received interrupt mask"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - response received interrupt mask"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `TXERRM` reader - Transaction error mask"] +pub type TXERRM_R = crate::BitReader; +#[doc = "Field `TXERRM` writer - Transaction error mask"] +pub type TXERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `BBERRM` reader - Babble error mask"] +pub type BBERRM_R = crate::BitReader; +#[doc = "Field `BBERRM` writer - Babble error mask"] +pub type BBERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `FRMORM` reader - Frame overrun mask"] +pub type FRMORM_R = crate::BitReader; +#[doc = "Field `FRMORM` writer - Frame overrun mask"] +pub type FRMORM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `DTERRM` reader - Data toggle error mask"] +pub type DTERRM_R = crate::BitReader; +#[doc = "Field `DTERRM` writer - Data toggle error mask"] +pub type DTERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel halted mask"] + #[inline(always)] + pub fn chhm(&self) -> CHHM_R { + CHHM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + pub fn ahberr(&self) -> AHBERR_R { + AHBERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STALL response received interrupt mask"] + #[inline(always)] + pub fn stallm(&self) -> STALLM_R { + STALLM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NAK response received interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] + #[inline(always)] + pub fn ackm(&self) -> ACKM_R { + ACKM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - response received interrupt mask"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transaction error mask"] + #[inline(always)] + pub fn txerrm(&self) -> TXERRM_R { + TXERRM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Babble error mask"] + #[inline(always)] + pub fn bberrm(&self) -> BBERRM_R { + BBERRM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame overrun mask"] + #[inline(always)] + pub fn frmorm(&self) -> FRMORM_R { + FRMORM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data toggle error mask"] + #[inline(always)] + pub fn dterrm(&self) -> DTERRM_R { + DTERRM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Channel halted mask"] + #[inline(always)] + #[must_use] + pub fn chhm(&mut self) -> CHHM_W<1> { + CHHM_W::new(self) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + #[must_use] + pub fn ahberr(&mut self) -> AHBERR_W<2> { + AHBERR_W::new(self) + } + #[doc = "Bit 3 - STALL response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn stallm(&mut self) -> STALLM_W<3> { + STALLM_W::new(self) + } + #[doc = "Bit 4 - NAK response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<4> { + NAKM_W::new(self) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] + #[inline(always)] + #[must_use] + pub fn ackm(&mut self) -> ACKM_W<5> { + ACKM_W::new(self) + } + #[doc = "Bit 6 - response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<6> { + NYET_W::new(self) + } + #[doc = "Bit 7 - Transaction error mask"] + #[inline(always)] + #[must_use] + pub fn txerrm(&mut self) -> TXERRM_W<7> { + TXERRM_W::new(self) + } + #[doc = "Bit 8 - Babble error mask"] + #[inline(always)] + #[must_use] + pub fn bberrm(&mut self) -> BBERRM_W<8> { + BBERRM_W::new(self) + } + #[doc = "Bit 9 - Frame overrun mask"] + #[inline(always)] + #[must_use] + pub fn frmorm(&mut self) -> FRMORM_W<9> { + FRMORM_W::new(self) + } + #[doc = "Bit 10 - Data toggle error mask"] + #[inline(always)] + #[must_use] + pub fn dterrm(&mut self) -> DTERRM_W<10> { + DTERRM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcintmsk](index.html) module"] +pub struct HCINTMSK_SPEC; +impl crate::RegisterSpec for HCINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcintmsk::R](R) reader structure"] +impl crate::Readable for HCINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcintmsk::W](W) writer structure"] +impl crate::Writable for HCINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCINTMSK to value 0"] +impl crate::Resettable for HCINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs new file mode 100644 index 0000000..b20ca79 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs @@ -0,0 +1,140 @@ +#[doc = "Register `HCSPLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCSPLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRTADDR` reader - Port address"] +pub type PRTADDR_R = crate::FieldReader; +#[doc = "Field `PRTADDR` writer - Port address"] +pub type PRTADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +#[doc = "Field `HUBADDR` reader - Hub address"] +pub type HUBADDR_R = crate::FieldReader; +#[doc = "Field `HUBADDR` writer - Hub address"] +pub type HUBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +#[doc = "Field `XACTPOS` reader - XACTPOS"] +pub type XACTPOS_R = crate::FieldReader; +#[doc = "Field `XACTPOS` writer - XACTPOS"] +pub type XACTPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 2, O>; +#[doc = "Field `COMPLSPLT` reader - Do complete split"] +pub type COMPLSPLT_R = crate::BitReader; +#[doc = "Field `COMPLSPLT` writer - Do complete split"] +pub type COMPLSPLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +#[doc = "Field `SPLITEN` reader - Split enable"] +pub type SPLITEN_R = crate::BitReader; +#[doc = "Field `SPLITEN` writer - Split enable"] +pub type SPLITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Port address"] + #[inline(always)] + pub fn prtaddr(&self) -> PRTADDR_R { + PRTADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Hub address"] + #[inline(always)] + pub fn hubaddr(&self) -> HUBADDR_R { + HUBADDR_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:15 - XACTPOS"] + #[inline(always)] + pub fn xactpos(&self) -> XACTPOS_R { + XACTPOS_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - Do complete split"] + #[inline(always)] + pub fn complsplt(&self) -> COMPLSPLT_R { + COMPLSPLT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 31 - Split enable"] + #[inline(always)] + pub fn spliten(&self) -> SPLITEN_R { + SPLITEN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Port address"] + #[inline(always)] + #[must_use] + pub fn prtaddr(&mut self) -> PRTADDR_W<0> { + PRTADDR_W::new(self) + } + #[doc = "Bits 7:13 - Hub address"] + #[inline(always)] + #[must_use] + pub fn hubaddr(&mut self) -> HUBADDR_W<7> { + HUBADDR_W::new(self) + } + #[doc = "Bits 14:15 - XACTPOS"] + #[inline(always)] + #[must_use] + pub fn xactpos(&mut self) -> XACTPOS_W<14> { + XACTPOS_W::new(self) + } + #[doc = "Bit 16 - Do complete split"] + #[inline(always)] + #[must_use] + pub fn complsplt(&mut self) -> COMPLSPLT_W<16> { + COMPLSPLT_W::new(self) + } + #[doc = "Bit 31 - Split enable"] + #[inline(always)] + #[must_use] + pub fn spliten(&mut self) -> SPLITEN_W<31> { + SPLITEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Split control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcsplt](index.html) module"] +pub struct HCSPLT_SPEC; +impl crate::RegisterSpec for HCSPLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcsplt::R](R) reader structure"] +impl crate::Readable for HCSPLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcsplt::W](W) writer structure"] +impl crate::Writable for HCSPLT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCSPLT to value 0"] +impl crate::Resettable for HCSPLT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs new file mode 100644 index 0000000..a7361fd --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs @@ -0,0 +1,110 @@ +#[doc = "Register `HCTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u32, u32, 19, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::FieldReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u16, u16, 10, O>; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `DPID` writer - Data PID"] +pub type DPID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:18 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new(self.bits & 0x0007_ffff) + } + #[doc = "Bits 19:28 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 0x03ff) as u16) + } + #[doc = "Bits 29:30 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 29) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:18 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bits 19:28 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Bits 29:30 - Data PID"] + #[inline(always)] + #[must_use] + pub fn dpid(&mut self) -> DPID_W<29> { + DPID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctsiz](index.html) module"] +pub struct HCTSIZ_SPEC; +impl crate::RegisterSpec for HCTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hctsiz::R](R) reader structure"] +impl crate::Readable for HCTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hctsiz::W](W) writer structure"] +impl crate::Writable for HCTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCTSIZ to value 0"] +impl crate::Resettable for HCTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs b/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs new file mode 100644 index 0000000..cb893f3 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs @@ -0,0 +1,228 @@ +#[doc = "Register `HPRT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPRT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PCSTS` reader - Port connect status"] +pub type PCSTS_R = crate::BitReader; +#[doc = "Field `PCDET` reader - Port connect detected"] +pub type PCDET_R = crate::BitReader; +#[doc = "Field `PCDET` writer - Port connect detected"] +pub type PCDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PENA` reader - Port enable"] +pub type PENA_R = crate::BitReader; +#[doc = "Field `PENA` writer - Port enable"] +pub type PENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PENCHNG` reader - Port enable/disable change"] +pub type PENCHNG_R = crate::BitReader; +#[doc = "Field `PENCHNG` writer - Port enable/disable change"] +pub type PENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `POCA` reader - Port overcurrent active"] +pub type POCA_R = crate::BitReader; +#[doc = "Field `POCCHNG` reader - Port overcurrent change"] +pub type POCCHNG_R = crate::BitReader; +#[doc = "Field `POCCHNG` writer - Port overcurrent change"] +pub type POCCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PRES` reader - Port resume"] +pub type PRES_R = crate::BitReader; +#[doc = "Field `PRES` writer - Port resume"] +pub type PRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PSUSP` reader - Port suspend"] +pub type PSUSP_R = crate::BitReader; +#[doc = "Field `PSUSP` writer - Port suspend"] +pub type PSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PRST` reader - Port reset"] +pub type PRST_R = crate::BitReader; +#[doc = "Field `PRST` writer - Port reset"] +pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PLSTS` reader - Port line status"] +pub type PLSTS_R = crate::FieldReader; +#[doc = "Field `PPWR` reader - Port power"] +pub type PPWR_R = crate::BitReader; +#[doc = "Field `PPWR` writer - Port power"] +pub type PPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PTCTL` reader - Port test control"] +pub type PTCTL_R = crate::FieldReader; +#[doc = "Field `PTCTL` writer - Port test control"] +pub type PTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, u8, 4, O>; +#[doc = "Field `PSPD` reader - Port speed"] +pub type PSPD_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Port connect status"] + #[inline(always)] + pub fn pcsts(&self) -> PCSTS_R { + PCSTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port connect detected"] + #[inline(always)] + pub fn pcdet(&self) -> PCDET_R { + PCDET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port enable"] + #[inline(always)] + pub fn pena(&self) -> PENA_R { + PENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port enable/disable change"] + #[inline(always)] + pub fn penchng(&self) -> PENCHNG_R { + PENCHNG_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port overcurrent active"] + #[inline(always)] + pub fn poca(&self) -> POCA_R { + POCA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port overcurrent change"] + #[inline(always)] + pub fn pocchng(&self) -> POCCHNG_R { + POCCHNG_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port resume"] + #[inline(always)] + pub fn pres(&self) -> PRES_R { + PRES_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port suspend"] + #[inline(always)] + pub fn psusp(&self) -> PSUSP_R { + PSUSP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port reset"] + #[inline(always)] + pub fn prst(&self) -> PRST_R { + PRST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 10:11 - Port line status"] + #[inline(always)] + pub fn plsts(&self) -> PLSTS_R { + PLSTS_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Port power"] + #[inline(always)] + pub fn ppwr(&self) -> PPWR_R { + PPWR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - Port test control"] + #[inline(always)] + pub fn ptctl(&self) -> PTCTL_R { + PTCTL_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:18 - Port speed"] + #[inline(always)] + pub fn pspd(&self) -> PSPD_R { + PSPD_R::new(((self.bits >> 17) & 3) as u8) + } +} +impl W { + #[doc = "Bit 1 - Port connect detected"] + #[inline(always)] + #[must_use] + pub fn pcdet(&mut self) -> PCDET_W<1> { + PCDET_W::new(self) + } + #[doc = "Bit 2 - Port enable"] + #[inline(always)] + #[must_use] + pub fn pena(&mut self) -> PENA_W<2> { + PENA_W::new(self) + } + #[doc = "Bit 3 - Port enable/disable change"] + #[inline(always)] + #[must_use] + pub fn penchng(&mut self) -> PENCHNG_W<3> { + PENCHNG_W::new(self) + } + #[doc = "Bit 5 - Port overcurrent change"] + #[inline(always)] + #[must_use] + pub fn pocchng(&mut self) -> POCCHNG_W<5> { + POCCHNG_W::new(self) + } + #[doc = "Bit 6 - Port resume"] + #[inline(always)] + #[must_use] + pub fn pres(&mut self) -> PRES_W<6> { + PRES_W::new(self) + } + #[doc = "Bit 7 - Port suspend"] + #[inline(always)] + #[must_use] + pub fn psusp(&mut self) -> PSUSP_W<7> { + PSUSP_W::new(self) + } + #[doc = "Bit 8 - Port reset"] + #[inline(always)] + #[must_use] + pub fn prst(&mut self) -> PRST_W<8> { + PRST_W::new(self) + } + #[doc = "Bit 12 - Port power"] + #[inline(always)] + #[must_use] + pub fn ppwr(&mut self) -> PPWR_W<12> { + PPWR_W::new(self) + } + #[doc = "Bits 13:16 - Port test control"] + #[inline(always)] + #[must_use] + pub fn ptctl(&mut self) -> PTCTL_W<13> { + PTCTL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host port control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"] +pub struct HPRT_SPEC; +impl crate::RegisterSpec for HPRT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hprt::R](R) reader structure"] +impl crate::Readable for HPRT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"] +impl crate::Writable for HPRT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPRT to value 0"] +impl crate::Resettable for HPRT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs b/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs new file mode 100644 index 0000000..3cb5895 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs @@ -0,0 +1,94 @@ +#[doc = "Register `HPTXSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPTXSTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTXFSAVL` reader - Periodic transmit data FIFO space available"] +pub type PTXFSAVL_R = crate::FieldReader; +#[doc = "Field `PTXFSAVL` writer - Periodic transmit data FIFO space available"] +pub type PTXFSAVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXSTS_SPEC, u16, u16, 16, O>; +#[doc = "Field `PTXQSAV` reader - Periodic transmit request queue space available"] +pub type PTXQSAV_R = crate::FieldReader; +#[doc = "Field `PTXQTOP` reader - Top of the periodic transmit request queue"] +pub type PTXQTOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] + #[inline(always)] + pub fn ptxfsavl(&self) -> PTXFSAVL_R { + PTXFSAVL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Periodic transmit request queue space available"] + #[inline(always)] + pub fn ptxqsav(&self) -> PTXQSAV_R { + PTXQSAV_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Top of the periodic transmit request queue"] + #[inline(always)] + pub fn ptxqtop(&self) -> PTXQTOP_R { + PTXQTOP_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] + #[inline(always)] + #[must_use] + pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<0> { + PTXFSAVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Host periodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](index.html) module"] +pub struct HPTXSTS_SPEC; +impl crate::RegisterSpec for HPTXSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hptxsts::R](R) reader structure"] +impl crate::Readable for HPTXSTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hptxsts::W](W) writer structure"] +impl crate::Writable for HPTXSTS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPTXSTS to value 0x0008_0100"] +impl crate::Resettable for HPTXSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0100; +} diff --git a/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs b/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs new file mode 100644 index 0000000..67a9eb5 --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - power and clock gating control"] + pub pcgcctl: PCGCCTL, +} +#[doc = "PCGCCTL (rw) register accessor: an alias for `Reg`"] +pub type PCGCCTL = crate::Reg; +#[doc = "power and clock gating control"] +pub mod pcgcctl; diff --git a/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs b/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs new file mode 100644 index 0000000..061312d --- /dev/null +++ b/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs @@ -0,0 +1,293 @@ +#[doc = "Register `PCGCCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCGCCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STPPCLK` reader - Stop PHY clock"] +pub type STPPCLK_R = crate::BitReader; +#[doc = "Field `STPPCLK` writer - Stop PHY clock"] +pub type STPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `GATEHCLK` reader - Gate HCLK"] +pub type GATEHCLK_R = crate::BitReader; +#[doc = "Field `GATEHCLK` writer - Gate HCLK"] +pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PWRCLMP` reader - Power clamp"] +pub type PWRCLMP_R = crate::BitReader; +#[doc = "Field `PWRCLMP` writer - Power clamp"] +pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RSTPDWNMODULE` reader - Power down modules"] +pub type RSTPDWNMODULE_R = crate::BitReader; +#[doc = "Field `RSTPDWNMODULE` writer - Power down modules"] +pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PHYSUSP` reader - PHY Suspended"] +pub type PHYSUSP_R = crate::BitReader; +#[doc = "Field `PHYSUSP` writer - PHY Suspended"] +pub type PHYSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ENABLE_L1GATING` reader - Enable sleep clock gating"] +pub type ENABLE_L1GATING_R = crate::BitReader; +#[doc = "Field `ENABLE_L1GATING` writer - Enable sleep clock gating"] +pub type ENABLE_L1GATING_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PHYSLEEP` reader - PHY is in sleep mode"] +pub type PHYSLEEP_R = crate::BitReader; +#[doc = "Field `PHYSLEEP` writer - PHY is in sleep mode"] +pub type PHYSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `DEEPSLEEP` reader - PHY is in deep sleep"] +pub type DEEPSLEEP_R = crate::BitReader; +#[doc = "Field `DEEPSLEEP` writer - PHY is in deep sleep"] +pub type DEEPSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"] +pub type RESETAFTERSUSP_R = crate::BitReader; +#[doc = "Field `RESETAFTERSUSP` writer - Reset after suspend"] +pub type RESETAFTERSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESTOREMODE` reader - Restore mode"] +pub type RESTOREMODE_R = crate::BitReader; +#[doc = "Field `RESTOREMODE` writer - Restore mode"] +pub type RESTOREMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ENEXTNDEDHIBER` reader - Enable extended hibernation"] +pub type ENEXTNDEDHIBER_R = crate::BitReader; +#[doc = "Field `ENEXTNDEDHIBER` writer - Enable extended hibernation"] +pub type ENEXTNDEDHIBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `EXTNDEDHIBERNATIONCLAMP` reader - Extended hibernation clamp"] +pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; +#[doc = "Field `EXTNDEDHIBERNATIONCLAMP` writer - Extended hibernation clamp"] +pub type EXTNDEDHIBERNATIONCLAMP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `EXTNDEDHIBERNATIONSWITCH` reader - Extended hibernation switch"] +pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; +#[doc = "Field `EXTNDEDHIBERNATIONSWITCH` writer - Extended hibernation switch"] +pub type EXTNDEDHIBERNATIONSWITCH_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ESSREGRESTORED` reader - Essential register values restored"] +pub type ESSREGRESTORED_R = crate::BitReader; +#[doc = "Field `ESSREGRESTORED` writer - Essential register values restored"] +pub type ESSREGRESTORED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESTORE_VALUE` reader - Restore value"] +pub type RESTORE_VALUE_R = crate::FieldReader; +#[doc = "Field `RESTORE_VALUE` writer - Restore value"] +pub type RESTORE_VALUE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PCGCCTL_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bit 0 - Stop PHY clock"] + #[inline(always)] + pub fn stppclk(&self) -> STPPCLK_R { + STPPCLK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gate HCLK"] + #[inline(always)] + pub fn gatehclk(&self) -> GATEHCLK_R { + GATEHCLK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Power clamp"] + #[inline(always)] + pub fn pwrclmp(&self) -> PWRCLMP_R { + PWRCLMP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Power down modules"] + #[inline(always)] + pub fn rstpdwnmodule(&self) -> RSTPDWNMODULE_R { + RSTPDWNMODULE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PHY Suspended"] + #[inline(always)] + pub fn physusp(&self) -> PHYSUSP_R { + PHYSUSP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable sleep clock gating"] + #[inline(always)] + pub fn enable_l1gating(&self) -> ENABLE_L1GATING_R { + ENABLE_L1GATING_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - PHY is in sleep mode"] + #[inline(always)] + pub fn physleep(&self) -> PHYSLEEP_R { + PHYSLEEP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - PHY is in deep sleep"] + #[inline(always)] + pub fn deepsleep(&self) -> DEEPSLEEP_R { + DEEPSLEEP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reset after suspend"] + #[inline(always)] + pub fn resetaftersusp(&self) -> RESETAFTERSUSP_R { + RESETAFTERSUSP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Restore mode"] + #[inline(always)] + pub fn restoremode(&self) -> RESTOREMODE_R { + RESTOREMODE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable extended hibernation"] + #[inline(always)] + pub fn enextndedhiber(&self) -> ENEXTNDEDHIBER_R { + ENEXTNDEDHIBER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Extended hibernation clamp"] + #[inline(always)] + pub fn extndedhibernationclamp(&self) -> EXTNDEDHIBERNATIONCLAMP_R { + EXTNDEDHIBERNATIONCLAMP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Extended hibernation switch"] + #[inline(always)] + pub fn extndedhibernationswitch(&self) -> EXTNDEDHIBERNATIONSWITCH_R { + EXTNDEDHIBERNATIONSWITCH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Essential register values restored"] + #[inline(always)] + pub fn essregrestored(&self) -> ESSREGRESTORED_R { + ESSREGRESTORED_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:31 - Restore value"] + #[inline(always)] + pub fn restore_value(&self) -> RESTORE_VALUE_R { + RESTORE_VALUE_R::new((self.bits >> 14) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bit 0 - Stop PHY clock"] + #[inline(always)] + #[must_use] + pub fn stppclk(&mut self) -> STPPCLK_W<0> { + STPPCLK_W::new(self) + } + #[doc = "Bit 1 - Gate HCLK"] + #[inline(always)] + #[must_use] + pub fn gatehclk(&mut self) -> GATEHCLK_W<1> { + GATEHCLK_W::new(self) + } + #[doc = "Bit 2 - Power clamp"] + #[inline(always)] + #[must_use] + pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> { + PWRCLMP_W::new(self) + } + #[doc = "Bit 3 - Power down modules"] + #[inline(always)] + #[must_use] + pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> { + RSTPDWNMODULE_W::new(self) + } + #[doc = "Bit 4 - PHY Suspended"] + #[inline(always)] + #[must_use] + pub fn physusp(&mut self) -> PHYSUSP_W<4> { + PHYSUSP_W::new(self) + } + #[doc = "Bit 5 - Enable sleep clock gating"] + #[inline(always)] + #[must_use] + pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W<5> { + ENABLE_L1GATING_W::new(self) + } + #[doc = "Bit 6 - PHY is in sleep mode"] + #[inline(always)] + #[must_use] + pub fn physleep(&mut self) -> PHYSLEEP_W<6> { + PHYSLEEP_W::new(self) + } + #[doc = "Bit 7 - PHY is in deep sleep"] + #[inline(always)] + #[must_use] + pub fn deepsleep(&mut self) -> DEEPSLEEP_W<7> { + DEEPSLEEP_W::new(self) + } + #[doc = "Bit 8 - Reset after suspend"] + #[inline(always)] + #[must_use] + pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<8> { + RESETAFTERSUSP_W::new(self) + } + #[doc = "Bit 9 - Restore mode"] + #[inline(always)] + #[must_use] + pub fn restoremode(&mut self) -> RESTOREMODE_W<9> { + RESTOREMODE_W::new(self) + } + #[doc = "Bit 10 - Enable extended hibernation"] + #[inline(always)] + #[must_use] + pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W<10> { + ENEXTNDEDHIBER_W::new(self) + } + #[doc = "Bit 11 - Extended hibernation clamp"] + #[inline(always)] + #[must_use] + pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W<11> { + EXTNDEDHIBERNATIONCLAMP_W::new(self) + } + #[doc = "Bit 12 - Extended hibernation switch"] + #[inline(always)] + #[must_use] + pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W<12> { + EXTNDEDHIBERNATIONSWITCH_W::new(self) + } + #[doc = "Bit 13 - Essential register values restored"] + #[inline(always)] + #[must_use] + pub fn essregrestored(&mut self) -> ESSREGRESTORED_W<13> { + ESSREGRESTORED_W::new(self) + } + #[doc = "Bits 14:31 - Restore value"] + #[inline(always)] + #[must_use] + pub fn restore_value(&mut self) -> RESTORE_VALUE_W<14> { + RESTORE_VALUE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "power and clock gating control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"] +pub struct PCGCCTL_SPEC; +impl crate::RegisterSpec for PCGCCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"] +impl crate::Readable for PCGCCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"] +impl crate::Writable for PCGCCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCGCCTL to value 0x200b_8000"] +impl crate::Resettable for PCGCCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x200b_8000; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox.rs b/crates/bcm2711-lpa/src/vcmailbox.rs new file mode 100644 index 0000000..7490467 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox.rs @@ -0,0 +1,66 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Read messages from the VideoCore"] + pub read: READ, + _reserved1: [u8; 0x0c], + #[doc = "0x10 - "] + pub peek0: PEEK0, + #[doc = "0x14 - "] + pub sender0: SENDER0, + #[doc = "0x18 - "] + pub status0: STATUS0, + #[doc = "0x1c - "] + pub config0: CONFIG0, + #[doc = "0x20 - Write messages to the VideoCore"] + pub write: WRITE, + _reserved6: [u8; 0x0c], + #[doc = "0x30 - "] + pub peek1: PEEK1, + #[doc = "0x34 - "] + pub sender1: SENDER1, + #[doc = "0x38 - "] + pub status1: STATUS1, + #[doc = "0x3c - "] + pub config1: CONFIG1, +} +#[doc = "READ (r) register accessor: an alias for `Reg`"] +pub type READ = crate::Reg; +#[doc = "Read messages from the VideoCore"] +pub mod read; +#[doc = "PEEK0 (rw) register accessor: an alias for `Reg`"] +pub type PEEK0 = crate::Reg; +#[doc = ""] +pub mod peek0; +#[doc = "SENDER0 (rw) register accessor: an alias for `Reg`"] +pub type SENDER0 = crate::Reg; +#[doc = ""] +pub mod sender0; +#[doc = "STATUS0 (r) register accessor: an alias for `Reg`"] +pub type STATUS0 = crate::Reg; +#[doc = ""] +pub mod status0; +#[doc = "CONFIG0 (rw) register accessor: an alias for `Reg`"] +pub type CONFIG0 = crate::Reg; +#[doc = ""] +pub mod config0; +#[doc = "WRITE (w) register accessor: an alias for `Reg`"] +pub type WRITE = crate::Reg; +#[doc = "Write messages to the VideoCore"] +pub mod write; +#[doc = "PEEK1 (rw) register accessor: an alias for `Reg`"] +pub type PEEK1 = crate::Reg; +#[doc = ""] +pub mod peek1; +#[doc = "SENDER1 (rw) register accessor: an alias for `Reg`"] +pub type SENDER1 = crate::Reg; +#[doc = ""] +pub mod sender1; +#[doc = "STATUS1 (rw) register accessor: an alias for `Reg`"] +pub type STATUS1 = crate::Reg; +#[doc = ""] +pub mod status1; +#[doc = "CONFIG1 (rw) register accessor: an alias for `Reg`"] +pub type CONFIG1 = crate::Reg; +#[doc = ""] +pub mod config1; diff --git a/crates/bcm2711-lpa/src/vcmailbox/config0.rs b/crates/bcm2711-lpa/src/vcmailbox/config0.rs new file mode 100644 index 0000000..dce060f --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/config0.rs @@ -0,0 +1,76 @@ +#[doc = "Register `CONFIG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IRQEN` reader - Enable the interrupt when data is available"] +pub type IRQEN_R = crate::BitReader; +#[doc = "Field `IRQEN` writer - Enable the interrupt when data is available"] +pub type IRQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable the interrupt when data is available"] + #[inline(always)] + pub fn irqen(&self) -> IRQEN_R { + IRQEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the interrupt when data is available"] + #[inline(always)] + #[must_use] + pub fn irqen(&mut self) -> IRQEN_W<0> { + IRQEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config0](index.html) module"] +pub struct CONFIG0_SPEC; +impl crate::RegisterSpec for CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config0::R](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config0::W](W) writer structure"] +impl crate::Writable for CONFIG0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/config1.rs b/crates/bcm2711-lpa/src/vcmailbox/config1.rs new file mode 100644 index 0000000..3c238a6 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/config1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `CONFIG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config1](index.html) module"] +pub struct CONFIG1_SPEC; +impl crate::RegisterSpec for CONFIG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config1::R](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config1::W](W) writer structure"] +impl crate::Writable for CONFIG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/peek0.rs b/crates/bcm2711-lpa/src/vcmailbox/peek0.rs new file mode 100644 index 0000000..3b63843 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/peek0.rs @@ -0,0 +1,59 @@ +#[doc = "Register `PEEK0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PEEK0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek0](index.html) module"] +pub struct PEEK0_SPEC; +impl crate::RegisterSpec for PEEK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek0::R](R) reader structure"] +impl crate::Readable for PEEK0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peek0::W](W) writer structure"] +impl crate::Writable for PEEK0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/peek1.rs b/crates/bcm2711-lpa/src/vcmailbox/peek1.rs new file mode 100644 index 0000000..2431cc4 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/peek1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `PEEK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PEEK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek1](index.html) module"] +pub struct PEEK1_SPEC; +impl crate::RegisterSpec for PEEK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek1::R](R) reader structure"] +impl crate::Readable for PEEK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peek1::W](W) writer structure"] +impl crate::Writable for PEEK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/read.rs b/crates/bcm2711-lpa/src/vcmailbox/read.rs new file mode 100644 index 0000000..60b2d04 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/read.rs @@ -0,0 +1,24 @@ +#[doc = "Register `READ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Read messages from the VideoCore\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [read](index.html) module"] +pub struct READ_SPEC; +impl crate::RegisterSpec for READ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [read::R](R) reader structure"] +impl crate::Readable for READ_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/sender0.rs b/crates/bcm2711-lpa/src/vcmailbox/sender0.rs new file mode 100644 index 0000000..cbeb2f1 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/sender0.rs @@ -0,0 +1,59 @@ +#[doc = "Register `SENDER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SENDER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender0](index.html) module"] +pub struct SENDER0_SPEC; +impl crate::RegisterSpec for SENDER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sender0::R](R) reader structure"] +impl crate::Readable for SENDER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sender0::W](W) writer structure"] +impl crate::Writable for SENDER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/sender1.rs b/crates/bcm2711-lpa/src/vcmailbox/sender1.rs new file mode 100644 index 0000000..1537c2d --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/sender1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `SENDER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SENDER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender1](index.html) module"] +pub struct SENDER1_SPEC; +impl crate::RegisterSpec for SENDER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sender1::R](R) reader structure"] +impl crate::Readable for SENDER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sender1::W](W) writer structure"] +impl crate::Writable for SENDER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/status0.rs b/crates/bcm2711-lpa/src/vcmailbox/status0.rs new file mode 100644 index 0000000..035e2a4 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/status0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `STATUS0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EMPTY` reader - "] +pub type EMPTY_R = crate::BitReader; +#[doc = "Field `FULL` reader - "] +pub type FULL_R = crate::BitReader; +impl R { + #[doc = "Bit 30"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status0](index.html) module"] +pub struct STATUS0_SPEC; +impl crate::RegisterSpec for STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status0::R](R) reader structure"] +impl crate::Readable for STATUS0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/status1.rs b/crates/bcm2711-lpa/src/vcmailbox/status1.rs new file mode 100644 index 0000000..1a7b501 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/status1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `STATUS1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status1](index.html) module"] +pub struct STATUS1_SPEC; +impl crate::RegisterSpec for STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status1::R](R) reader structure"] +impl crate::Readable for STATUS1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status1::W](W) writer structure"] +impl crate::Writable for STATUS1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2711-lpa/src/vcmailbox/write.rs b/crates/bcm2711-lpa/src/vcmailbox/write.rs new file mode 100644 index 0000000..4e09735 --- /dev/null +++ b/crates/bcm2711-lpa/src/vcmailbox/write.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WRITE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write messages to the VideoCore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [write](index.html) module"] +pub struct WRITE_SPEC; +impl crate::RegisterSpec for WRITE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [write::W](W) writer structure"] +impl crate::Writable for WRITE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/.gitignore b/crates/bcm2835-lpa/.gitignore new file mode 100644 index 0000000..4fffb2f --- /dev/null +++ b/crates/bcm2835-lpa/.gitignore @@ -0,0 +1,2 @@ +/target +/Cargo.lock diff --git a/crates/bcm2835-lpa/Cargo.toml b/crates/bcm2835-lpa/Cargo.toml new file mode 100644 index 0000000..df22dc7 --- /dev/null +++ b/crates/bcm2835-lpa/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "bcm2835-lpa" +version = "0.1.0" +authors = ["Po-Yi Tsai "] +edition = "2021" +rust-version = "1.61.0" +description = "Peripheral access crate for BCM2835 found in the Raspberry Pi 1 and Zero." +repository = "https://github.com/abt8601/raspi-pacs" +license = "Unlicense" +keywords = ["raspberrypi", "bcm2835", "pac"] +categories = ["embedded", "hardware-support", "no-std", "no-std::no-alloc"] + +[dependencies] +critical-section = { version = "1.0", optional = true } +vcell = "0.1.0" +portable-atomic = { version = "0.3.16", default-features = false } + +[features] +rt = [] diff --git a/crates/bcm2835-lpa/README.md b/crates/bcm2835-lpa/README.md new file mode 100644 index 0000000..43ad433 --- /dev/null +++ b/crates/bcm2835-lpa/README.md @@ -0,0 +1,16 @@ +# bcm2835-lpa + +[![crates.io](https://img.shields.io/crates/v/bcm2835-lpa.svg)](https://crates.io/crates/bcm2835-lpa) +[![docs.rs](https://img.shields.io/docsrs/bcm2835-lpa)](https://docs.rs/bcm2835-lpa) + +Peripheral access crate for BCM2835 found in the Raspberry Pi 1 and Zero. + +This crate is generated by [`svd2rust`](https://crates.io/crates/svd2rust) +from the +[SVD file](https://github.com/abt8601/broadcom-peripherals/blob/6bc44a4fd5c956249b9d8815f66a9df41b5791b1/svd/gen/bcm2835_lpa.svd) +in +[`abt8601/broadcom-peripherals@6bc44a4`](https://github.com/abt8601/broadcom-peripherals/tree/6bc44a4fd5c956249b9d8815f66a9df41b5791b1), +which is based on that in +[`adafruit/broadcom-peripherals@d3a6b50`](https://github.com/adafruit/broadcom-peripherals/tree/d3a6b50a21e7dd49ba4bfa0374da3407594caa50). +(The SVD files in these two repositories are identical, +save that that in the former has the missing tags required by `svd2rust`.) diff --git a/crates/bcm2835-lpa/src/aux.rs b/crates/bcm2835-lpa/src/aux.rs new file mode 100644 index 0000000..5380cb2 --- /dev/null +++ b/crates/bcm2835-lpa/src/aux.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt status"] + pub irq: IRQ, + #[doc = "0x04 - Enable sub-peripherals"] + pub enables: ENABLES, +} +#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +pub type IRQ = crate::Reg; +#[doc = "Interrupt status"] +pub mod irq; +#[doc = "ENABLES (rw) register accessor: an alias for `Reg`"] +pub type ENABLES = crate::Reg; +#[doc = "Enable sub-peripherals"] +pub mod enables; diff --git a/crates/bcm2835-lpa/src/aux/enables.rs b/crates/bcm2835-lpa/src/aux/enables.rs new file mode 100644 index 0000000..eb9fc6d --- /dev/null +++ b/crates/bcm2835-lpa/src/aux/enables.rs @@ -0,0 +1,110 @@ +#[doc = "Register `ENABLES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLES` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UART_1` reader - UART1 enabled"] +pub type UART_1_R = crate::BitReader; +#[doc = "Field `UART_1` writer - UART1 enabled"] +pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 enabled"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 enabled"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 enabled"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 enabled"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UART1 enabled"] + #[inline(always)] + pub fn uart_1(&self) -> UART_1_R { + UART_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 enabled"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 enabled"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART1 enabled"] + #[inline(always)] + #[must_use] + pub fn uart_1(&mut self) -> UART_1_W<0> { + UART_1_W::new(self) + } + #[doc = "Bit 1 - SPI1 enabled"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 enabled"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"] +pub struct ENABLES_SPEC; +impl crate::RegisterSpec for ENABLES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enables::R](R) reader structure"] +impl crate::Readable for ENABLES_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"] +impl crate::Writable for ENABLES_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLES to value 0"] +impl crate::Resettable for ENABLES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/aux/irq.rs b/crates/bcm2835-lpa/src/aux/irq.rs new file mode 100644 index 0000000..a59c319 --- /dev/null +++ b/crates/bcm2835-lpa/src/aux/irq.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IRQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UART_1` reader - UART1 interrupt active"] +pub type UART_1_R = crate::BitReader; +#[doc = "Field `UART_1` writer - UART1 interrupt active"] +pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 interrupt active"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 interrupt active"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 interrupt active"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 interrupt active"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UART1 interrupt active"] + #[inline(always)] + pub fn uart_1(&self) -> UART_1_R { + UART_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_1(&mut self) -> UART_1_W<0> { + UART_1_W::new(self) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"] +pub struct IRQ_SPEC; +impl crate::RegisterSpec for IRQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq::R](R) reader structure"] +impl crate::Readable for IRQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +impl crate::Writable for IRQ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRQ to value 0"] +impl crate::Resettable for IRQ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/bsc0.rs b/crates/bcm2835-lpa/src/bsc0.rs new file mode 100644 index 0000000..8ccfb52 --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub c: C, + #[doc = "0x04 - Status"] + pub s: S, + #[doc = "0x08 - Data length"] + pub dlen: DLEN, + #[doc = "0x0c - Slave address"] + pub a: A, + #[doc = "0x10 - Data FIFO"] + pub fifo: FIFO, + #[doc = "0x14 - Clock divider"] + pub div: DIV, + #[doc = "0x18 - Data delay (Values must be under CDIV / 2)"] + pub del: DEL, + #[doc = "0x1c - Clock stretch timeout (broken on 283x)"] + pub clkt: CLKT, +} +#[doc = "C (rw) register accessor: an alias for `Reg`"] +pub type C = crate::Reg; +#[doc = "Control"] +pub mod c; +#[doc = "S (rw) register accessor: an alias for `Reg`"] +pub type S = crate::Reg; +#[doc = "Status"] +pub mod s; +#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +pub type DLEN = crate::Reg; +#[doc = "Data length"] +pub mod dlen; +#[doc = "A (rw) register accessor: an alias for `Reg`"] +pub type A = crate::Reg; +#[doc = "Slave address"] +pub mod a; +#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +pub type FIFO = crate::Reg; +#[doc = "Data FIFO"] +pub mod fifo; +#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +pub type DIV = crate::Reg; +#[doc = "Clock divider"] +pub mod div; +#[doc = "DEL (rw) register accessor: an alias for `Reg`"] +pub type DEL = crate::Reg; +#[doc = "Data delay (Values must be under CDIV / 2)"] +pub mod del; +#[doc = "CLKT (rw) register accessor: an alias for `Reg`"] +pub type CLKT = crate::Reg; +#[doc = "Clock stretch timeout (broken on 283x)"] +pub mod clkt; diff --git a/crates/bcm2835-lpa/src/bsc0/a.rs b/crates/bcm2835-lpa/src/bsc0/a.rs new file mode 100644 index 0000000..d98d147 --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/a.rs @@ -0,0 +1,80 @@ +#[doc = "Register `A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Slave address"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Slave address"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, A_SPEC, u8, u8, 7, O>; +impl R { + #[doc = "Bits 0:6 - Slave address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Slave address"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<0> { + ADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [a](index.html) module"] +pub struct A_SPEC; +impl crate::RegisterSpec for A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [a::R](R) reader structure"] +impl crate::Readable for A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [a::W](W) writer structure"] +impl crate::Writable for A_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A to value 0"] +impl crate::Resettable for A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/bsc0/c.rs b/crates/bcm2835-lpa/src/bsc0/c.rs new file mode 100644 index 0000000..f62d48d --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/c.rs @@ -0,0 +1,170 @@ +#[doc = "Register `C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READ` reader - Transfer is read"] +pub type READ_R = crate::BitReader; +#[doc = "Field `READ` writer - Transfer is read"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `CLEAR` reader - Clear the FIFO"] +pub type CLEAR_R = crate::FieldReader; +#[doc = "Field `CLEAR` writer - Clear the FIFO"] +pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, C_SPEC, u8, u8, 2, O>; +#[doc = "Field `ST` reader - Start transfer"] +pub type ST_R = crate::BitReader; +#[doc = "Field `ST` writer - Start transfer"] +pub type ST_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTD` reader - Interrupt on done"] +pub type INTD_R = crate::BitReader; +#[doc = "Field `INTD` writer - Interrupt on done"] +pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTT` reader - Interrupt on TX"] +pub type INTT_R = crate::BitReader; +#[doc = "Field `INTT` writer - Interrupt on TX"] +pub type INTT_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTR` reader - Interrupt on RX"] +pub type INTR_R = crate::BitReader; +#[doc = "Field `INTR` writer - Interrupt on RX"] +pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `I2CEN` reader - I2C Enable"] +pub type I2CEN_R = crate::BitReader; +#[doc = "Field `I2CEN` writer - I2C Enable"] +pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer is read"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:5 - Clear the FIFO"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Start transfer"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt on done"] + #[inline(always)] + pub fn intd(&self) -> INTD_R { + INTD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on TX"] + #[inline(always)] + pub fn intt(&self) -> INTT_R { + INTT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 15 - I2C Enable"] + #[inline(always)] + pub fn i2cen(&self) -> I2CEN_R { + I2CEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer is read"] + #[inline(always)] + #[must_use] + pub fn read(&mut self) -> READ_W<0> { + READ_W::new(self) + } + #[doc = "Bits 4:5 - Clear the FIFO"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<4> { + CLEAR_W::new(self) + } + #[doc = "Bit 7 - Start transfer"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> ST_W<7> { + ST_W::new(self) + } + #[doc = "Bit 8 - Interrupt on done"] + #[inline(always)] + #[must_use] + pub fn intd(&mut self) -> INTD_W<8> { + INTD_W::new(self) + } + #[doc = "Bit 9 - Interrupt on TX"] + #[inline(always)] + #[must_use] + pub fn intt(&mut self) -> INTT_W<9> { + INTT_W::new(self) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W<10> { + INTR_W::new(self) + } + #[doc = "Bit 15 - I2C Enable"] + #[inline(always)] + #[must_use] + pub fn i2cen(&mut self) -> I2CEN_W<15> { + I2CEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c](index.html) module"] +pub struct C_SPEC; +impl crate::RegisterSpec for C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c::R](R) reader structure"] +impl crate::Readable for C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c::W](W) writer structure"] +impl crate::Writable for C_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C to value 0"] +impl crate::Resettable for C_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/bsc0/clkt.rs b/crates/bcm2835-lpa/src/bsc0/clkt.rs new file mode 100644 index 0000000..15bc5c4 --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/clkt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CLKT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"] +pub type TOUT_R = crate::FieldReader; +#[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"] +pub type TOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] + #[inline(always)] + pub fn tout(&self) -> TOUT_R { + TOUT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] + #[inline(always)] + #[must_use] + pub fn tout(&mut self) -> TOUT_W<0> { + TOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock stretch timeout (broken on 283x)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkt](index.html) module"] +pub struct CLKT_SPEC; +impl crate::RegisterSpec for CLKT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkt::R](R) reader structure"] +impl crate::Readable for CLKT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkt::W](W) writer structure"] +impl crate::Writable for CLKT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKT to value 0"] +impl crate::Resettable for CLKT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/bsc0/del.rs b/crates/bcm2835-lpa/src/bsc0/del.rs new file mode 100644 index 0000000..c39336b --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/del.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REDL` reader - Delay before reading after a rising edge"] +pub type REDL_R = crate::FieldReader; +#[doc = "Field `REDL` writer - Delay before reading after a rising edge"] +pub type REDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +#[doc = "Field `FEDL` reader - Delay before reading after a falling edge"] +pub type FEDL_R = crate::FieldReader; +#[doc = "Field `FEDL` writer - Delay before reading after a falling edge"] +pub type FEDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Delay before reading after a rising edge"] + #[inline(always)] + pub fn redl(&self) -> REDL_R { + REDL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Delay before reading after a falling edge"] + #[inline(always)] + pub fn fedl(&self) -> FEDL_R { + FEDL_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Delay before reading after a rising edge"] + #[inline(always)] + #[must_use] + pub fn redl(&mut self) -> REDL_W<0> { + REDL_W::new(self) + } + #[doc = "Bits 16:31 - Delay before reading after a falling edge"] + #[inline(always)] + #[must_use] + pub fn fedl(&mut self) -> FEDL_W<16> { + FEDL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data delay (Values must be under CDIV / 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [del](index.html) module"] +pub struct DEL_SPEC; +impl crate::RegisterSpec for DEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [del::R](R) reader structure"] +impl crate::Readable for DEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [del::W](W) writer structure"] +impl crate::Writable for DEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEL to value 0x0030_0030"] +impl crate::Resettable for DEL_SPEC { + const RESET_VALUE: Self::Ux = 0x0030_0030; +} diff --git a/crates/bcm2835-lpa/src/bsc0/div.rs b/crates/bcm2835-lpa/src/bsc0/div.rs new file mode 100644 index 0000000..ce0aa5a --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/div.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CDIV` reader - Divide the source clock"] +pub type CDIV_R = crate::FieldReader; +#[doc = "Field `CDIV` writer - Divide the source clock"] +pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Divide the source clock"] + #[inline(always)] + pub fn cdiv(&self) -> CDIV_R { + CDIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Divide the source clock"] + #[inline(always)] + #[must_use] + pub fn cdiv(&mut self) -> CDIV_W<0> { + CDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [div::R](R) reader structure"] +impl crate::Readable for DIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIV to value 0x05dc"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: Self::Ux = 0x05dc; +} diff --git a/crates/bcm2835-lpa/src/bsc0/dlen.rs b/crates/bcm2835-lpa/src/bsc0/dlen.rs new file mode 100644 index 0000000..25e2771 --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/dlen.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLEN` reader - Data length"] +pub type DLEN_R = crate::FieldReader; +#[doc = "Field `DLEN` writer - Data length"] +pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + pub fn dlen(&self) -> DLEN_R { + DLEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + #[must_use] + pub fn dlen(&mut self) -> DLEN_W<0> { + DLEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +pub struct DLEN_SPEC; +impl crate::RegisterSpec for DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dlen::R](R) reader structure"] +impl crate::Readable for DLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +impl crate::Writable for DLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLEN to value 0"] +impl crate::Resettable for DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/bsc0/fifo.rs b/crates/bcm2835-lpa/src/bsc0/fifo.rs new file mode 100644 index 0000000..f85912b --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/fifo.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FIFO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Access the FIFO"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Access the FIFO"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Access the FIFO"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Access the FIFO"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo::R](R) reader structure"] +impl crate::Readable for FIFO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/bsc0/s.rs b/crates/bcm2835-lpa/src/bsc0/s.rs new file mode 100644 index 0000000..45f365b --- /dev/null +++ b/crates/bcm2835-lpa/src/bsc0/s.rs @@ -0,0 +1,159 @@ +#[doc = "Register `S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TA` reader - Transfer active"] +pub type TA_R = crate::BitReader; +#[doc = "Field `DONE` reader - Transfer done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Transfer done"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +#[doc = "Field `TXW` reader - FIFO needs to be written"] +pub type TXW_R = crate::BitReader; +#[doc = "Field `RXR` reader - FIFO needs to be read"] +pub type RXR_R = crate::BitReader; +#[doc = "Field `TXD` reader - FIFO has space for at least one byte"] +pub type TXD_R = crate::BitReader; +#[doc = "Field `RXD` reader - FIFO contains at least one byte"] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXE` reader - FIFO is empty. Nothing to transmit"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `RXF` reader - FIFO is full. Can't receive anything else"] +pub type RXF_R = crate::BitReader; +#[doc = "Field `ERR` reader - Error: No ack"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Error: No ack"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +#[doc = "Field `CLKT` reader - Clock stretch timeout"] +pub type CLKT_R = crate::BitReader; +#[doc = "Field `CLKT` writer - Clock stretch timeout"] +pub type CLKT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer active"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO needs to be written"] + #[inline(always)] + pub fn txw(&self) -> TXW_R { + TXW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO needs to be read"] + #[inline(always)] + pub fn rxr(&self) -> RXR_R { + RXR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - FIFO has space for at least one byte"] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - FIFO contains at least one byte"] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - FIFO is empty. Nothing to transmit"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FIFO is full. Can't receive anything else"] + #[inline(always)] + pub fn rxf(&self) -> RXF_R { + RXF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Error: No ack"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Clock stretch timeout"] + #[inline(always)] + pub fn clkt(&self) -> CLKT_R { + CLKT_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<1> { + DONE_W::new(self) + } + #[doc = "Bit 8 - Error: No ack"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<8> { + ERR_W::new(self) + } + #[doc = "Bit 9 - Clock stretch timeout"] + #[inline(always)] + #[must_use] + pub fn clkt(&mut self) -> CLKT_W<9> { + CLKT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s](index.html) module"] +pub struct S_SPEC; +impl crate::RegisterSpec for S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s::R](R) reader structure"] +impl crate::Readable for S_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s::W](W) writer structure"] +impl crate::Writable for S_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0302; +} +#[doc = "`reset()` method sets S to value 0x50"] +impl crate::Resettable for S_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/crates/bcm2835-lpa/src/cm_pcm.rs b/crates/bcm2835-lpa/src/cm_pcm.rs new file mode 100644 index 0000000..0c60fcd --- /dev/null +++ b/crates/bcm2835-lpa/src/cm_pcm.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control / Status"] + pub cs: CS, + #[doc = "0x04 - Clock divisor"] + pub div: DIV, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control / Status"] +pub mod cs; +#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +pub type DIV = crate::Reg; +#[doc = "Clock divisor"] +pub mod div; diff --git a/crates/bcm2835-lpa/src/cm_pcm/cs.rs b/crates/bcm2835-lpa/src/cm_pcm/cs.rs new file mode 100644 index 0000000..67ddd60 --- /dev/null +++ b/crates/bcm2835-lpa/src/cm_pcm/cs.rs @@ -0,0 +1,288 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Clock source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "1: `1`"] + XOSC = 1, + #[doc = "2: `10`"] + TEST0 = 2, + #[doc = "3: `11`"] + TEST1 = 3, + #[doc = "4: `100`"] + PLLA = 4, + #[doc = "5: `101`"] + PLLB = 5, + #[doc = "6: `110`"] + PLLC = 6, + #[doc = "7: `111`"] + HDMI = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(SRC_A::XOSC), + 2 => Some(SRC_A::TEST0), + 3 => Some(SRC_A::TEST1), + 4 => Some(SRC_A::PLLA), + 5 => Some(SRC_A::PLLB), + 6 => Some(SRC_A::PLLC), + 7 => Some(SRC_A::HDMI), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + *self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `TEST0`"] + #[inline(always)] + pub fn is_test0(&self) -> bool { + *self == SRC_A::TEST0 + } + #[doc = "Checks if the value of the field is `TEST1`"] + #[inline(always)] + pub fn is_test1(&self) -> bool { + *self == SRC_A::TEST1 + } + #[doc = "Checks if the value of the field is `PLLA`"] + #[inline(always)] + pub fn is_plla(&self) -> bool { + *self == SRC_A::PLLA + } + #[doc = "Checks if the value of the field is `PLLB`"] + #[inline(always)] + pub fn is_pllb(&self) -> bool { + *self == SRC_A::PLLB + } + #[doc = "Checks if the value of the field is `PLLC`"] + #[inline(always)] + pub fn is_pllc(&self) -> bool { + *self == SRC_A::PLLC + } + #[doc = "Checks if the value of the field is `HDMI`"] + #[inline(always)] + pub fn is_hdmi(&self) -> bool { + *self == SRC_A::HDMI + } +} +#[doc = "Field `SRC` writer - Clock source"] +pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, SRC_A, 4, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "`1`"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "`10`"] + #[inline(always)] + pub fn test0(self) -> &'a mut W { + self.variant(SRC_A::TEST0) + } + #[doc = "`11`"] + #[inline(always)] + pub fn test1(self) -> &'a mut W { + self.variant(SRC_A::TEST1) + } + #[doc = "`100`"] + #[inline(always)] + pub fn plla(self) -> &'a mut W { + self.variant(SRC_A::PLLA) + } + #[doc = "`101`"] + #[inline(always)] + pub fn pllb(self) -> &'a mut W { + self.variant(SRC_A::PLLB) + } + #[doc = "`110`"] + #[inline(always)] + pub fn pllc(self) -> &'a mut W { + self.variant(SRC_A::PLLC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn hdmi(self) -> &'a mut W { + self.variant(SRC_A::HDMI) + } +} +#[doc = "Field `ENAB` reader - Enable the clock generator. (Switch SRC first.)"] +pub type ENAB_R = crate::BitReader; +#[doc = "Field `ENAB` writer - Enable the clock generator. (Switch SRC first.)"] +pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `KILL` reader - Stop and reset the generator"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Stop and reset the generator"] +pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `BUSY` reader - Indicates the clock generator is running"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `FLIP` reader - Generate an edge on output. (For testing)"] +pub type FLIP_R = crate::BitReader; +#[doc = "Field `FLIP` writer - Generate an edge on output. (For testing)"] +pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `MASH` reader - MASH control, stage count"] +pub type MASH_R = crate::FieldReader; +#[doc = "Field `MASH` writer - MASH control, stage count"] +pub type MASH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:3 - Clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] + #[inline(always)] + pub fn enab(&self) -> ENAB_R { + ENAB_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stop and reset the generator"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Indicates the clock generator is running"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Generate an edge on output. (For testing)"] + #[inline(always)] + pub fn flip(&self) -> FLIP_R { + FLIP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:10 - MASH control, stage count"] + #[inline(always)] + pub fn mash(&self) -> MASH_R { + MASH_R::new(((self.bits >> 9) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Clock source"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] + #[inline(always)] + #[must_use] + pub fn enab(&mut self) -> ENAB_W<4> { + ENAB_W::new(self) + } + #[doc = "Bit 5 - Stop and reset the generator"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W<5> { + KILL_W::new(self) + } + #[doc = "Bit 8 - Generate an edge on output. (For testing)"] + #[inline(always)] + #[must_use] + pub fn flip(&mut self) -> FLIP_W<8> { + FLIP_W::new(self) + } + #[doc = "Bits 9:10 - MASH control, stage count"] + #[inline(always)] + #[must_use] + pub fn mash(&mut self) -> MASH_W<9> { + MASH_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/cm_pcm/div.rs b/crates/bcm2835-lpa/src/cm_pcm/div.rs new file mode 100644 index 0000000..a0c99f8 --- /dev/null +++ b/crates/bcm2835-lpa/src/cm_pcm/div.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVF` reader - Fractional part of divisor"] +pub type DIVF_R = crate::FieldReader; +#[doc = "Field `DIVF` writer - Fractional part of divisor"] +pub type DIVF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +#[doc = "Field `DIVI` reader - Integer part of divisor"] +pub type DIVI_R = crate::FieldReader; +#[doc = "Field `DIVI` writer - Integer part of divisor"] +pub type DIVI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:11 - Fractional part of divisor"] + #[inline(always)] + pub fn divf(&self) -> DIVF_R { + DIVF_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - Integer part of divisor"] + #[inline(always)] + pub fn divi(&self) -> DIVI_R { + DIVI_R::new(((self.bits >> 12) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Fractional part of divisor"] + #[inline(always)] + #[must_use] + pub fn divf(&mut self) -> DIVF_W<0> { + DIVF_W::new(self) + } + #[doc = "Bits 12:23 - Integer part of divisor"] + #[inline(always)] + #[must_use] + pub fn divi(&mut self) -> DIVI_W<12> { + DIVI_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [div::R](R) reader structure"] +impl crate::Readable for DIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIV to value 0"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc.rs b/crates/bcm2835-lpa/src/emmc.rs new file mode 100644 index 0000000..e4be2cf --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc.rs @@ -0,0 +1,165 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Argument for ACMD23 command"] + pub arg2: ARG2, + #[doc = "0x04 - Numer and size in bytes for data block to be transferred"] + pub blksizecnt: BLKSIZECNT, + #[doc = "0x08 - Argument for everything but ACMD23"] + pub arg1: ARG1, + #[doc = "0x0c - Issue commands to the card"] + pub cmdtm: CMDTM, + #[doc = "0x10 - Status bits of the response"] + pub resp0: RESP0, + #[doc = "0x14 - Bits 63:32 of CMD2 and CMD10 responses"] + pub resp1: RESP1, + #[doc = "0x18 - Bits 95:64 of CMD2 and CMD10 responses"] + pub resp2: RESP2, + #[doc = "0x1c - Bits 127:96 of CMD2 and CMD10 responses"] + pub resp3: RESP3, + #[doc = "0x20 - Data to/from the card"] + pub data: DATA, + #[doc = "0x24 - Status info for debugging"] + pub status: STATUS, + #[doc = "0x28 - Control"] + pub control0: CONTROL0, + #[doc = "0x2c - Configure"] + pub control1: CONTROL1, + #[doc = "0x30 - Interrupt flags"] + pub interrupt: INTERRUPT, + #[doc = "0x34 - Mask interrupts that change in INTERRUPT"] + pub irpt_mask: IRPT_MASK, + #[doc = "0x38 - Enable interrupt to core"] + pub irpt_en: IRPT_EN, + #[doc = "0x3c - Control 2"] + pub control2: CONTROL2, + _reserved16: [u8; 0x10], + #[doc = "0x50 - Force an interrupt"] + pub force_irpt: FORCE_IRPT, + _reserved17: [u8; 0x1c], + #[doc = "0x70 - Number of SD clock cycles to wait for boot"] + pub boot_timeout: BOOT_TIMEOUT, + #[doc = "0x74 - What submodules are accessed by the debug bus"] + pub dbg_sel: DBG_SEL, + _reserved19: [u8; 0x08], + #[doc = "0x80 - Fine tune DMA request generation"] + pub exrdfifo_cfg: EXRDFIFO_CFG, + #[doc = "0x84 - Enable the extension data register"] + pub exrdfifo_en: EXRDFIFO_EN, + #[doc = "0x88 - Sample clock delay step duration"] + pub tune_step: TUNE_STEP, + #[doc = "0x8c - Sample clock delay step count for SDR"] + pub tune_steps_std: TUNE_STEPS_STD, + #[doc = "0x90 - Sample clock delay step count for DDR"] + pub tune_steps_ddr: TUNE_STEPS_DDR, + _reserved24: [u8; 0x5c], + #[doc = "0xf0 - Interrupts in SPI mode depend on CS"] + pub spi_int_spt: SPI_INT_SPT, + _reserved25: [u8; 0x08], + #[doc = "0xfc - Version information and slot interrupt status"] + pub slotisr_ver: SLOTISR_VER, +} +#[doc = "ARG2 (rw) register accessor: an alias for `Reg`"] +pub type ARG2 = crate::Reg; +#[doc = "Argument for ACMD23 command"] +pub mod arg2; +#[doc = "BLKSIZECNT (rw) register accessor: an alias for `Reg`"] +pub type BLKSIZECNT = crate::Reg; +#[doc = "Numer and size in bytes for data block to be transferred"] +pub mod blksizecnt; +#[doc = "ARG1 (rw) register accessor: an alias for `Reg`"] +pub type ARG1 = crate::Reg; +#[doc = "Argument for everything but ACMD23"] +pub mod arg1; +#[doc = "CMDTM (rw) register accessor: an alias for `Reg`"] +pub type CMDTM = crate::Reg; +#[doc = "Issue commands to the card"] +pub mod cmdtm; +#[doc = "RESP0 (rw) register accessor: an alias for `Reg`"] +pub type RESP0 = crate::Reg; +#[doc = "Status bits of the response"] +pub mod resp0; +#[doc = "RESP1 (rw) register accessor: an alias for `Reg`"] +pub type RESP1 = crate::Reg; +#[doc = "Bits 63:32 of CMD2 and CMD10 responses"] +pub mod resp1; +#[doc = "RESP2 (rw) register accessor: an alias for `Reg`"] +pub type RESP2 = crate::Reg; +#[doc = "Bits 95:64 of CMD2 and CMD10 responses"] +pub mod resp2; +#[doc = "RESP3 (rw) register accessor: an alias for `Reg`"] +pub type RESP3 = crate::Reg; +#[doc = "Bits 127:96 of CMD2 and CMD10 responses"] +pub mod resp3; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data to/from the card"] +pub mod data; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status info for debugging"] +pub mod status; +#[doc = "CONTROL0 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL0 = crate::Reg; +#[doc = "Control"] +pub mod control0; +#[doc = "CONTROL1 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL1 = crate::Reg; +#[doc = "Configure"] +pub mod control1; +#[doc = "INTERRUPT (rw) register accessor: an alias for `Reg`"] +pub type INTERRUPT = crate::Reg; +#[doc = "Interrupt flags"] +pub mod interrupt; +#[doc = "IRPT_MASK (rw) register accessor: an alias for `Reg`"] +pub type IRPT_MASK = crate::Reg; +#[doc = "Mask interrupts that change in INTERRUPT"] +pub mod irpt_mask; +#[doc = "IRPT_EN (rw) register accessor: an alias for `Reg`"] +pub type IRPT_EN = crate::Reg; +#[doc = "Enable interrupt to core"] +pub mod irpt_en; +#[doc = "CONTROL2 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL2 = crate::Reg; +#[doc = "Control 2"] +pub mod control2; +#[doc = "FORCE_IRPT (rw) register accessor: an alias for `Reg`"] +pub type FORCE_IRPT = crate::Reg; +#[doc = "Force an interrupt"] +pub mod force_irpt; +#[doc = "BOOT_TIMEOUT (rw) register accessor: an alias for `Reg`"] +pub type BOOT_TIMEOUT = crate::Reg; +#[doc = "Number of SD clock cycles to wait for boot"] +pub mod boot_timeout; +#[doc = "DBG_SEL (rw) register accessor: an alias for `Reg`"] +pub type DBG_SEL = crate::Reg; +#[doc = "What submodules are accessed by the debug bus"] +pub mod dbg_sel; +#[doc = "EXRDFIFO_CFG (rw) register accessor: an alias for `Reg`"] +pub type EXRDFIFO_CFG = crate::Reg; +#[doc = "Fine tune DMA request generation"] +pub mod exrdfifo_cfg; +#[doc = "EXRDFIFO_EN (rw) register accessor: an alias for `Reg`"] +pub type EXRDFIFO_EN = crate::Reg; +#[doc = "Enable the extension data register"] +pub mod exrdfifo_en; +#[doc = "TUNE_STEP (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEP = crate::Reg; +#[doc = "Sample clock delay step duration"] +pub mod tune_step; +#[doc = "TUNE_STEPS_STD (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEPS_STD = crate::Reg; +#[doc = "Sample clock delay step count for SDR"] +pub mod tune_steps_std; +#[doc = "TUNE_STEPS_DDR (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEPS_DDR = crate::Reg; +#[doc = "Sample clock delay step count for DDR"] +pub mod tune_steps_ddr; +#[doc = "SPI_INT_SPT (rw) register accessor: an alias for `Reg`"] +pub type SPI_INT_SPT = crate::Reg; +#[doc = "Interrupts in SPI mode depend on CS"] +pub mod spi_int_spt; +#[doc = "SLOTISR_VER (rw) register accessor: an alias for `Reg`"] +pub type SLOTISR_VER = crate::Reg; +#[doc = "Version information and slot interrupt status"] +pub mod slotisr_ver; diff --git a/crates/bcm2835-lpa/src/emmc/arg1.rs b/crates/bcm2835-lpa/src/emmc/arg1.rs new file mode 100644 index 0000000..4a25300 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/arg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ARG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ARG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Argument for everything but ACMD23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg1](index.html) module"] +pub struct ARG1_SPEC; +impl crate::RegisterSpec for ARG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [arg1::R](R) reader structure"] +impl crate::Readable for ARG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [arg1::W](W) writer structure"] +impl crate::Writable for ARG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARG1 to value 0"] +impl crate::Resettable for ARG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/arg2.rs b/crates/bcm2835-lpa/src/emmc/arg2.rs new file mode 100644 index 0000000..b295b35 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/arg2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ARG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ARG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Argument for ACMD23 command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg2](index.html) module"] +pub struct ARG2_SPEC; +impl crate::RegisterSpec for ARG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [arg2::R](R) reader structure"] +impl crate::Readable for ARG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [arg2::W](W) writer structure"] +impl crate::Writable for ARG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARG2 to value 0"] +impl crate::Resettable for ARG2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/blksizecnt.rs b/crates/bcm2835-lpa/src/emmc/blksizecnt.rs new file mode 100644 index 0000000..f3dabd8 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/blksizecnt.rs @@ -0,0 +1,95 @@ +#[doc = "Register `BLKSIZECNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BLKSIZECNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BLKSIZE` reader - Block size in bytes"] +pub type BLKSIZE_R = crate::FieldReader; +#[doc = "Field `BLKSIZE` writer - Block size in bytes"] +pub type BLKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 10, O>; +#[doc = "Field `BLKCNT` reader - Number of blocks to be transferred"] +pub type BLKCNT_R = crate::FieldReader; +#[doc = "Field `BLKCNT` writer - Number of blocks to be transferred"] +pub type BLKCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:9 - Block size in bytes"] + #[inline(always)] + pub fn blksize(&self) -> BLKSIZE_R { + BLKSIZE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:31 - Number of blocks to be transferred"] + #[inline(always)] + pub fn blkcnt(&self) -> BLKCNT_R { + BLKCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Block size in bytes"] + #[inline(always)] + #[must_use] + pub fn blksize(&mut self) -> BLKSIZE_W<0> { + BLKSIZE_W::new(self) + } + #[doc = "Bits 16:31 - Number of blocks to be transferred"] + #[inline(always)] + #[must_use] + pub fn blkcnt(&mut self) -> BLKCNT_W<16> { + BLKCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Numer and size in bytes for data block to be transferred\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blksizecnt](index.html) module"] +pub struct BLKSIZECNT_SPEC; +impl crate::RegisterSpec for BLKSIZECNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [blksizecnt::R](R) reader structure"] +impl crate::Readable for BLKSIZECNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [blksizecnt::W](W) writer structure"] +impl crate::Writable for BLKSIZECNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLKSIZECNT to value 0"] +impl crate::Resettable for BLKSIZECNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/boot_timeout.rs b/crates/bcm2835-lpa/src/emmc/boot_timeout.rs new file mode 100644 index 0000000..5a9943a --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/boot_timeout.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BOOT_TIMEOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOOT_TIMEOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Number of SD clock cycles to wait for boot\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_timeout](index.html) module"] +pub struct BOOT_TIMEOUT_SPEC; +impl crate::RegisterSpec for BOOT_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [boot_timeout::R](R) reader structure"] +impl crate::Readable for BOOT_TIMEOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [boot_timeout::W](W) writer structure"] +impl crate::Writable for BOOT_TIMEOUT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOOT_TIMEOUT to value 0"] +impl crate::Resettable for BOOT_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/cmdtm.rs b/crates/bcm2835-lpa/src/emmc/cmdtm.rs new file mode 100644 index 0000000..e30a873 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/cmdtm.rs @@ -0,0 +1,520 @@ +#[doc = "Register `CMDTM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMDTM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TM_BLKCNT_EN` reader - Enable block counter"] +pub type TM_BLKCNT_EN_R = crate::BitReader; +#[doc = "Field `TM_BLKCNT_EN` writer - Enable block counter"] +pub type TM_BLKCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `TM_AUTO_CMD_EN` reader - Command after completion"] +pub type TM_AUTO_CMD_EN_R = crate::FieldReader; +#[doc = "Command after completion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TM_AUTO_CMD_EN_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + CMD12 = 1, + #[doc = "2: `10`"] + CMD23 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TM_AUTO_CMD_EN_A) -> Self { + variant as _ + } +} +impl TM_AUTO_CMD_EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TM_AUTO_CMD_EN_A::NONE), + 1 => Some(TM_AUTO_CMD_EN_A::CMD12), + 2 => Some(TM_AUTO_CMD_EN_A::CMD23), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::NONE + } + #[doc = "Checks if the value of the field is `CMD12`"] + #[inline(always)] + pub fn is_cmd12(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::CMD12 + } + #[doc = "Checks if the value of the field is `CMD23`"] + #[inline(always)] + pub fn is_cmd23(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::CMD23 + } +} +#[doc = "Field `TM_AUTO_CMD_EN` writer - Command after completion"] +pub type TM_AUTO_CMD_EN_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, TM_AUTO_CMD_EN_A, 2, O>; +impl<'a, const O: u8> TM_AUTO_CMD_EN_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::NONE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn cmd12(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::CMD12) + } + #[doc = "`10`"] + #[inline(always)] + pub fn cmd23(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::CMD23) + } +} +#[doc = "Field `TM_DAT_DIR` reader - Direction of data transfer"] +pub type TM_DAT_DIR_R = crate::BitReader; +#[doc = "Direction of data transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TM_DAT_DIR_A { + #[doc = "0: `0`"] + HOST_TO_CARD = 0, + #[doc = "1: `1`"] + CARD_TO_HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TM_DAT_DIR_A) -> Self { + variant as u8 != 0 + } +} +impl TM_DAT_DIR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TM_DAT_DIR_A { + match self.bits { + false => TM_DAT_DIR_A::HOST_TO_CARD, + true => TM_DAT_DIR_A::CARD_TO_HOST, + } + } + #[doc = "Checks if the value of the field is `HOST_TO_CARD`"] + #[inline(always)] + pub fn is_host_to_card(&self) -> bool { + *self == TM_DAT_DIR_A::HOST_TO_CARD + } + #[doc = "Checks if the value of the field is `CARD_TO_HOST`"] + #[inline(always)] + pub fn is_card_to_host(&self) -> bool { + *self == TM_DAT_DIR_A::CARD_TO_HOST + } +} +#[doc = "Field `TM_DAT_DIR` writer - Direction of data transfer"] +pub type TM_DAT_DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, TM_DAT_DIR_A, O>; +impl<'a, const O: u8> TM_DAT_DIR_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn host_to_card(self) -> &'a mut W { + self.variant(TM_DAT_DIR_A::HOST_TO_CARD) + } + #[doc = "`1`"] + #[inline(always)] + pub fn card_to_host(self) -> &'a mut W { + self.variant(TM_DAT_DIR_A::CARD_TO_HOST) + } +} +#[doc = "Field `TM_MULTI_BLOCK` reader - Type of data transfer"] +pub type TM_MULTI_BLOCK_R = crate::BitReader; +#[doc = "Type of data transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TM_MULTI_BLOCK_A { + #[doc = "0: `0`"] + SINGLE = 0, + #[doc = "1: `1`"] + MULTIPLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TM_MULTI_BLOCK_A) -> Self { + variant as u8 != 0 + } +} +impl TM_MULTI_BLOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TM_MULTI_BLOCK_A { + match self.bits { + false => TM_MULTI_BLOCK_A::SINGLE, + true => TM_MULTI_BLOCK_A::MULTIPLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == TM_MULTI_BLOCK_A::SINGLE + } + #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[inline(always)] + pub fn is_multiple(&self) -> bool { + *self == TM_MULTI_BLOCK_A::MULTIPLE + } +} +#[doc = "Field `TM_MULTI_BLOCK` writer - Type of data transfer"] +pub type TM_MULTI_BLOCK_W<'a, const O: u8> = + crate::BitWriter<'a, u32, CMDTM_SPEC, TM_MULTI_BLOCK_A, O>; +impl<'a, const O: u8> TM_MULTI_BLOCK_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(TM_MULTI_BLOCK_A::SINGLE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn multiple(self) -> &'a mut W { + self.variant(TM_MULTI_BLOCK_A::MULTIPLE) + } +} +#[doc = "Field `CMD_RSPNS_TYPE` reader - Type of expected response"] +pub type CMD_RSPNS_TYPE_R = crate::FieldReader; +#[doc = "Type of expected response\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RESPONSE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _136BITS = 1, + #[doc = "2: `10`"] + _48BITS = 2, + #[doc = "3: `11`"] + _48BITS_USING_BUSY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESPONSE_A) -> Self { + variant as _ + } +} +impl CMD_RSPNS_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESPONSE_A { + match self.bits { + 0 => RESPONSE_A::NONE, + 1 => RESPONSE_A::_136BITS, + 2 => RESPONSE_A::_48BITS, + 3 => RESPONSE_A::_48BITS_USING_BUSY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == RESPONSE_A::NONE + } + #[doc = "Checks if the value of the field is `_136BITS`"] + #[inline(always)] + pub fn is_136bits(&self) -> bool { + *self == RESPONSE_A::_136BITS + } + #[doc = "Checks if the value of the field is `_48BITS`"] + #[inline(always)] + pub fn is_48bits(&self) -> bool { + *self == RESPONSE_A::_48BITS + } + #[doc = "Checks if the value of the field is `_48BITS_USING_BUSY`"] + #[inline(always)] + pub fn is_48bits_using_busy(&self) -> bool { + *self == RESPONSE_A::_48BITS_USING_BUSY + } +} +#[doc = "Field `CMD_RSPNS_TYPE` writer - Type of expected response"] +pub type CMD_RSPNS_TYPE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, RESPONSE_A, 2, O>; +impl<'a, const O: u8> CMD_RSPNS_TYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESPONSE_A::NONE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _136bits(self) -> &'a mut W { + self.variant(RESPONSE_A::_136BITS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _48bits(self) -> &'a mut W { + self.variant(RESPONSE_A::_48BITS) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _48bits_using_busy(self) -> &'a mut W { + self.variant(RESPONSE_A::_48BITS_USING_BUSY) + } +} +#[doc = "Field `CMD_CRCCHK_EN` reader - Check the responses CRC"] +pub type CMD_CRCCHK_EN_R = crate::BitReader; +#[doc = "Field `CMD_CRCCHK_EN` writer - Check the responses CRC"] +pub type CMD_CRCCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_IXCHK_EN` reader - Check that the response has the same command index"] +pub type CMD_IXCHK_EN_R = crate::BitReader; +#[doc = "Field `CMD_IXCHK_EN` writer - Check that the response has the same command index"] +pub type CMD_IXCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_ISDATA` reader - Command involves data"] +pub type CMD_ISDATA_R = crate::BitReader; +#[doc = "Field `CMD_ISDATA` writer - Command involves data"] +pub type CMD_ISDATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_TYPE` reader - Type of command to be issued"] +pub type CMD_TYPE_R = crate::FieldReader; +#[doc = "Type of command to be issued\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMD_TYPE_A { + #[doc = "0: `0`"] + NORMAL = 0, + #[doc = "1: `1`"] + SUSPEND = 1, + #[doc = "2: `10`"] + RESUME = 2, + #[doc = "3: `11`"] + ABORT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_TYPE_A) -> Self { + variant as _ + } +} +impl CMD_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMD_TYPE_A { + match self.bits { + 0 => CMD_TYPE_A::NORMAL, + 1 => CMD_TYPE_A::SUSPEND, + 2 => CMD_TYPE_A::RESUME, + 3 => CMD_TYPE_A::ABORT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NORMAL`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CMD_TYPE_A::NORMAL + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == CMD_TYPE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + *self == CMD_TYPE_A::RESUME + } + #[doc = "Checks if the value of the field is `ABORT`"] + #[inline(always)] + pub fn is_abort(&self) -> bool { + *self == CMD_TYPE_A::ABORT + } +} +#[doc = "Field `CMD_TYPE` writer - Type of command to be issued"] +pub type CMD_TYPE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, CMD_TYPE_A, 2, O>; +impl<'a, const O: u8> CMD_TYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn normal(self) -> &'a mut W { + self.variant(CMD_TYPE_A::NORMAL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_TYPE_A::SUSPEND) + } + #[doc = "`10`"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_TYPE_A::RESUME) + } + #[doc = "`11`"] + #[inline(always)] + pub fn abort(self) -> &'a mut W { + self.variant(CMD_TYPE_A::ABORT) + } +} +#[doc = "Field `CMD_INDEX` reader - Command index to be issued"] +pub type CMD_INDEX_R = crate::FieldReader; +#[doc = "Field `CMD_INDEX` writer - Command index to be issued"] +pub type CMD_INDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bit 1 - Enable block counter"] + #[inline(always)] + pub fn tm_blkcnt_en(&self) -> TM_BLKCNT_EN_R { + TM_BLKCNT_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Command after completion"] + #[inline(always)] + pub fn tm_auto_cmd_en(&self) -> TM_AUTO_CMD_EN_R { + TM_AUTO_CMD_EN_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Direction of data transfer"] + #[inline(always)] + pub fn tm_dat_dir(&self) -> TM_DAT_DIR_R { + TM_DAT_DIR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Type of data transfer"] + #[inline(always)] + pub fn tm_multi_block(&self) -> TM_MULTI_BLOCK_R { + TM_MULTI_BLOCK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 16:17 - Type of expected response"] + #[inline(always)] + pub fn cmd_rspns_type(&self) -> CMD_RSPNS_TYPE_R { + CMD_RSPNS_TYPE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 19 - Check the responses CRC"] + #[inline(always)] + pub fn cmd_crcchk_en(&self) -> CMD_CRCCHK_EN_R { + CMD_CRCCHK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Check that the response has the same command index"] + #[inline(always)] + pub fn cmd_ixchk_en(&self) -> CMD_IXCHK_EN_R { + CMD_IXCHK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Command involves data"] + #[inline(always)] + pub fn cmd_isdata(&self) -> CMD_ISDATA_R { + CMD_ISDATA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:23 - Type of command to be issued"] + #[inline(always)] + pub fn cmd_type(&self) -> CMD_TYPE_R { + CMD_TYPE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:29 - Command index to be issued"] + #[inline(always)] + pub fn cmd_index(&self) -> CMD_INDEX_R { + CMD_INDEX_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable block counter"] + #[inline(always)] + #[must_use] + pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W<1> { + TM_BLKCNT_EN_W::new(self) + } + #[doc = "Bits 2:3 - Command after completion"] + #[inline(always)] + #[must_use] + pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W<2> { + TM_AUTO_CMD_EN_W::new(self) + } + #[doc = "Bit 4 - Direction of data transfer"] + #[inline(always)] + #[must_use] + pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W<4> { + TM_DAT_DIR_W::new(self) + } + #[doc = "Bit 5 - Type of data transfer"] + #[inline(always)] + #[must_use] + pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W<5> { + TM_MULTI_BLOCK_W::new(self) + } + #[doc = "Bits 16:17 - Type of expected response"] + #[inline(always)] + #[must_use] + pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W<16> { + CMD_RSPNS_TYPE_W::new(self) + } + #[doc = "Bit 19 - Check the responses CRC"] + #[inline(always)] + #[must_use] + pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W<19> { + CMD_CRCCHK_EN_W::new(self) + } + #[doc = "Bit 20 - Check that the response has the same command index"] + #[inline(always)] + #[must_use] + pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W<20> { + CMD_IXCHK_EN_W::new(self) + } + #[doc = "Bit 21 - Command involves data"] + #[inline(always)] + #[must_use] + pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W<21> { + CMD_ISDATA_W::new(self) + } + #[doc = "Bits 22:23 - Type of command to be issued"] + #[inline(always)] + #[must_use] + pub fn cmd_type(&mut self) -> CMD_TYPE_W<22> { + CMD_TYPE_W::new(self) + } + #[doc = "Bits 24:29 - Command index to be issued"] + #[inline(always)] + #[must_use] + pub fn cmd_index(&mut self) -> CMD_INDEX_W<24> { + CMD_INDEX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Issue commands to the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdtm](index.html) module"] +pub struct CMDTM_SPEC; +impl crate::RegisterSpec for CMDTM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cmdtm::R](R) reader structure"] +impl crate::Readable for CMDTM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmdtm::W](W) writer structure"] +impl crate::Writable for CMDTM_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMDTM to value 0"] +impl crate::Resettable for CMDTM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/control0.rs b/crates/bcm2835-lpa/src/emmc/control0.rs new file mode 100644 index 0000000..948b94b --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/control0.rs @@ -0,0 +1,215 @@ +#[doc = "Register `CONTROL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HCTL_DWIDTH` reader - Use 4 data lines"] +pub type HCTL_DWIDTH_R = crate::BitReader; +#[doc = "Field `HCTL_DWIDTH` writer - Use 4 data lines"] +pub type HCTL_DWIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `HCTL_HS_EN` reader - Enable high speed mode"] +pub type HCTL_HS_EN_R = crate::BitReader; +#[doc = "Field `HCTL_HS_EN` writer - Enable high speed mode"] +pub type HCTL_HS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `HCTL_8BIT` reader - Use 8 data lines"] +pub type HCTL_8BIT_R = crate::BitReader; +#[doc = "Field `HCTL_8BIT` writer - Use 8 data lines"] +pub type HCTL_8BIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_STOP` reader - Stop the current transaction at the next block gap"] +pub type GAP_STOP_R = crate::BitReader; +#[doc = "Field `GAP_STOP` writer - Stop the current transaction at the next block gap"] +pub type GAP_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_RESTART` reader - Restart a transaction stopped by GAP_STOP"] +pub type GAP_RESTART_R = crate::BitReader; +#[doc = "Field `GAP_RESTART` writer - Restart a transaction stopped by GAP_STOP"] +pub type GAP_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `READWAIT_EN` reader - Use DAT2 read/wait protocol"] +pub type READWAIT_EN_R = crate::BitReader; +#[doc = "Field `READWAIT_EN` writer - Use DAT2 read/wait protocol"] +pub type READWAIT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_IEN` reader - Enable interrupt on block gap"] +pub type GAP_IEN_R = crate::BitReader; +#[doc = "Field `GAP_IEN` writer - Enable interrupt on block gap"] +pub type GAP_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `SPI_MODE` reader - Enable SPI mode"] +pub type SPI_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MODE` writer - Enable SPI mode"] +pub type SPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `BOOT_EN` reader - Boot mode enabled"] +pub type BOOT_EN_R = crate::BitReader; +#[doc = "Field `BOOT_EN` writer - Boot mode enabled"] +pub type BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `ALT_BOOT_EN` reader - Enable alternate boot mode"] +pub type ALT_BOOT_EN_R = crate::BitReader; +#[doc = "Field `ALT_BOOT_EN` writer - Enable alternate boot mode"] +pub type ALT_BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Use 4 data lines"] + #[inline(always)] + pub fn hctl_dwidth(&self) -> HCTL_DWIDTH_R { + HCTL_DWIDTH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable high speed mode"] + #[inline(always)] + pub fn hctl_hs_en(&self) -> HCTL_HS_EN_R { + HCTL_HS_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Use 8 data lines"] + #[inline(always)] + pub fn hctl_8bit(&self) -> HCTL_8BIT_R { + HCTL_8BIT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - Stop the current transaction at the next block gap"] + #[inline(always)] + pub fn gap_stop(&self) -> GAP_STOP_R { + GAP_STOP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] + #[inline(always)] + pub fn gap_restart(&self) -> GAP_RESTART_R { + GAP_RESTART_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Use DAT2 read/wait protocol"] + #[inline(always)] + pub fn readwait_en(&self) -> READWAIT_EN_R { + READWAIT_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable interrupt on block gap"] + #[inline(always)] + pub fn gap_ien(&self) -> GAP_IEN_R { + GAP_IEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable SPI mode"] + #[inline(always)] + pub fn spi_mode(&self) -> SPI_MODE_R { + SPI_MODE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Boot mode enabled"] + #[inline(always)] + pub fn boot_en(&self) -> BOOT_EN_R { + BOOT_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enable alternate boot mode"] + #[inline(always)] + pub fn alt_boot_en(&self) -> ALT_BOOT_EN_R { + ALT_BOOT_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Use 4 data lines"] + #[inline(always)] + #[must_use] + pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W<1> { + HCTL_DWIDTH_W::new(self) + } + #[doc = "Bit 2 - Enable high speed mode"] + #[inline(always)] + #[must_use] + pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W<2> { + HCTL_HS_EN_W::new(self) + } + #[doc = "Bit 5 - Use 8 data lines"] + #[inline(always)] + #[must_use] + pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W<5> { + HCTL_8BIT_W::new(self) + } + #[doc = "Bit 16 - Stop the current transaction at the next block gap"] + #[inline(always)] + #[must_use] + pub fn gap_stop(&mut self) -> GAP_STOP_W<16> { + GAP_STOP_W::new(self) + } + #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] + #[inline(always)] + #[must_use] + pub fn gap_restart(&mut self) -> GAP_RESTART_W<17> { + GAP_RESTART_W::new(self) + } + #[doc = "Bit 18 - Use DAT2 read/wait protocol"] + #[inline(always)] + #[must_use] + pub fn readwait_en(&mut self) -> READWAIT_EN_W<18> { + READWAIT_EN_W::new(self) + } + #[doc = "Bit 19 - Enable interrupt on block gap"] + #[inline(always)] + #[must_use] + pub fn gap_ien(&mut self) -> GAP_IEN_W<19> { + GAP_IEN_W::new(self) + } + #[doc = "Bit 20 - Enable SPI mode"] + #[inline(always)] + #[must_use] + pub fn spi_mode(&mut self) -> SPI_MODE_W<20> { + SPI_MODE_W::new(self) + } + #[doc = "Bit 21 - Boot mode enabled"] + #[inline(always)] + #[must_use] + pub fn boot_en(&mut self) -> BOOT_EN_W<21> { + BOOT_EN_W::new(self) + } + #[doc = "Bit 22 - Enable alternate boot mode"] + #[inline(always)] + #[must_use] + pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W<22> { + ALT_BOOT_EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control0](index.html) module"] +pub struct CONTROL0_SPEC; +impl crate::RegisterSpec for CONTROL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control0::R](R) reader structure"] +impl crate::Readable for CONTROL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control0::W](W) writer structure"] +impl crate::Writable for CONTROL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL0 to value 0"] +impl crate::Resettable for CONTROL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/control1.rs b/crates/bcm2835-lpa/src/emmc/control1.rs new file mode 100644 index 0000000..1dc7cb3 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/control1.rs @@ -0,0 +1,253 @@ +#[doc = "Register `CONTROL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLK_INTLEN` reader - Enable internal clock"] +pub type CLK_INTLEN_R = crate::BitReader; +#[doc = "Field `CLK_INTLEN` writer - Enable internal clock"] +pub type CLK_INTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `CLK_STABLE` reader - SD Clock stable"] +pub type CLK_STABLE_R = crate::BitReader; +#[doc = "Field `CLK_EN` reader - SD Clock enable"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - SD Clock enable"] +pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `CLK_GENSEL` reader - Mode of clock generation"] +pub type CLK_GENSEL_R = crate::BitReader; +#[doc = "Mode of clock generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CLK_GENSEL_A { + #[doc = "0: `0`"] + DIVIDED = 0, + #[doc = "1: `1`"] + PROGRAMMABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLK_GENSEL_A) -> Self { + variant as u8 != 0 + } +} +impl CLK_GENSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLK_GENSEL_A { + match self.bits { + false => CLK_GENSEL_A::DIVIDED, + true => CLK_GENSEL_A::PROGRAMMABLE, + } + } + #[doc = "Checks if the value of the field is `DIVIDED`"] + #[inline(always)] + pub fn is_divided(&self) -> bool { + *self == CLK_GENSEL_A::DIVIDED + } + #[doc = "Checks if the value of the field is `PROGRAMMABLE`"] + #[inline(always)] + pub fn is_programmable(&self) -> bool { + *self == CLK_GENSEL_A::PROGRAMMABLE + } +} +#[doc = "Field `CLK_GENSEL` writer - Mode of clock generation"] +pub type CLK_GENSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, CLK_GENSEL_A, O>; +impl<'a, const O: u8> CLK_GENSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn divided(self) -> &'a mut W { + self.variant(CLK_GENSEL_A::DIVIDED) + } + #[doc = "`1`"] + #[inline(always)] + pub fn programmable(self) -> &'a mut W { + self.variant(CLK_GENSEL_A::PROGRAMMABLE) + } +} +#[doc = "Field `CLK_FREQ_MS2` reader - Clock base divider MSBs"] +pub type CLK_FREQ_MS2_R = crate::FieldReader; +#[doc = "Field `CLK_FREQ_MS2` writer - Clock base divider MSBs"] +pub type CLK_FREQ_MS2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 2, O>; +#[doc = "Field `CLK_FREQ8` reader - Clock base divider LSB"] +pub type CLK_FREQ8_R = crate::FieldReader; +#[doc = "Field `CLK_FREQ8` writer - Clock base divider LSB"] +pub type CLK_FREQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 8, O>; +#[doc = "Field `DATA_TOUNIT` reader - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] +pub type DATA_TOUNIT_R = crate::FieldReader; +#[doc = "Field `DATA_TOUNIT` writer - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] +pub type DATA_TOUNIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 4, O>; +#[doc = "Field `SRST_HC` reader - Reset the complete host circuit"] +pub type SRST_HC_R = crate::BitReader; +#[doc = "Field `SRST_HC` writer - Reset the complete host circuit"] +pub type SRST_HC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `SRST_CMD` reader - Reset the command handling circuit"] +pub type SRST_CMD_R = crate::BitReader; +#[doc = "Field `SRST_CMD` writer - Reset the command handling circuit"] +pub type SRST_CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `SRST_DATA` reader - Reset the data handling circuit"] +pub type SRST_DATA_R = crate::BitReader; +#[doc = "Field `SRST_DATA` writer - Reset the data handling circuit"] +pub type SRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable internal clock"] + #[inline(always)] + pub fn clk_intlen(&self) -> CLK_INTLEN_R { + CLK_INTLEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SD Clock stable"] + #[inline(always)] + pub fn clk_stable(&self) -> CLK_STABLE_R { + CLK_STABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SD Clock enable"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Mode of clock generation"] + #[inline(always)] + pub fn clk_gensel(&self) -> CLK_GENSEL_R { + CLK_GENSEL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Clock base divider MSBs"] + #[inline(always)] + pub fn clk_freq_ms2(&self) -> CLK_FREQ_MS2_R { + CLK_FREQ_MS2_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:15 - Clock base divider LSB"] + #[inline(always)] + pub fn clk_freq8(&self) -> CLK_FREQ8_R { + CLK_FREQ8_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] + #[inline(always)] + pub fn data_tounit(&self) -> DATA_TOUNIT_R { + DATA_TOUNIT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 24 - Reset the complete host circuit"] + #[inline(always)] + pub fn srst_hc(&self) -> SRST_HC_R { + SRST_HC_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reset the command handling circuit"] + #[inline(always)] + pub fn srst_cmd(&self) -> SRST_CMD_R { + SRST_CMD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reset the data handling circuit"] + #[inline(always)] + pub fn srst_data(&self) -> SRST_DATA_R { + SRST_DATA_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable internal clock"] + #[inline(always)] + #[must_use] + pub fn clk_intlen(&mut self) -> CLK_INTLEN_W<0> { + CLK_INTLEN_W::new(self) + } + #[doc = "Bit 2 - SD Clock enable"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W<2> { + CLK_EN_W::new(self) + } + #[doc = "Bit 5 - Mode of clock generation"] + #[inline(always)] + #[must_use] + pub fn clk_gensel(&mut self) -> CLK_GENSEL_W<5> { + CLK_GENSEL_W::new(self) + } + #[doc = "Bits 6:7 - Clock base divider MSBs"] + #[inline(always)] + #[must_use] + pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W<6> { + CLK_FREQ_MS2_W::new(self) + } + #[doc = "Bits 8:15 - Clock base divider LSB"] + #[inline(always)] + #[must_use] + pub fn clk_freq8(&mut self) -> CLK_FREQ8_W<8> { + CLK_FREQ8_W::new(self) + } + #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] + #[inline(always)] + #[must_use] + pub fn data_tounit(&mut self) -> DATA_TOUNIT_W<16> { + DATA_TOUNIT_W::new(self) + } + #[doc = "Bit 24 - Reset the complete host circuit"] + #[inline(always)] + #[must_use] + pub fn srst_hc(&mut self) -> SRST_HC_W<24> { + SRST_HC_W::new(self) + } + #[doc = "Bit 25 - Reset the command handling circuit"] + #[inline(always)] + #[must_use] + pub fn srst_cmd(&mut self) -> SRST_CMD_W<25> { + SRST_CMD_W::new(self) + } + #[doc = "Bit 26 - Reset the data handling circuit"] + #[inline(always)] + #[must_use] + pub fn srst_data(&mut self) -> SRST_DATA_W<26> { + SRST_DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configure\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control1](index.html) module"] +pub struct CONTROL1_SPEC; +impl crate::RegisterSpec for CONTROL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control1::R](R) reader structure"] +impl crate::Readable for CONTROL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control1::W](W) writer structure"] +impl crate::Writable for CONTROL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL1 to value 0"] +impl crate::Resettable for CONTROL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/control2.rs b/crates/bcm2835-lpa/src/emmc/control2.rs new file mode 100644 index 0000000..1bc9076 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/control2.rs @@ -0,0 +1,240 @@ +#[doc = "Register `CONTROL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ACNOX_ERR` reader - Auto command not executed due to an error"] +pub type ACNOX_ERR_R = crate::BitReader; +#[doc = "Field `ACTO_ERR` reader - Auto command timeout"] +pub type ACTO_ERR_R = crate::BitReader; +#[doc = "Field `ACCRC_ERR` reader - Command CRC error during auto command"] +pub type ACCRC_ERR_R = crate::BitReader; +#[doc = "Field `ACEND_ERR` reader - End bit is not 1 during auto command"] +pub type ACEND_ERR_R = crate::BitReader; +#[doc = "Field `ACBAD_ERR` reader - Command index error during auto command"] +pub type ACBAD_ERR_R = crate::BitReader; +#[doc = "Field `NOTC12_ERR` reader - Error during auto CMD12"] +pub type NOTC12_ERR_R = crate::BitReader; +#[doc = "Field `UHSMODE` reader - Select the speed of the SD card"] +pub type UHSMODE_R = crate::FieldReader; +#[doc = "Select the speed of the SD card\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum UHSMODE_A { + #[doc = "0: `0`"] + SDR12 = 0, + #[doc = "1: `1`"] + SDR25 = 1, + #[doc = "2: `10`"] + SDR50 = 2, + #[doc = "3: `11`"] + SDR104 = 3, + #[doc = "4: `100`"] + DDR50 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: UHSMODE_A) -> Self { + variant as _ + } +} +impl UHSMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(UHSMODE_A::SDR12), + 1 => Some(UHSMODE_A::SDR25), + 2 => Some(UHSMODE_A::SDR50), + 3 => Some(UHSMODE_A::SDR104), + 4 => Some(UHSMODE_A::DDR50), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SDR12`"] + #[inline(always)] + pub fn is_sdr12(&self) -> bool { + *self == UHSMODE_A::SDR12 + } + #[doc = "Checks if the value of the field is `SDR25`"] + #[inline(always)] + pub fn is_sdr25(&self) -> bool { + *self == UHSMODE_A::SDR25 + } + #[doc = "Checks if the value of the field is `SDR50`"] + #[inline(always)] + pub fn is_sdr50(&self) -> bool { + *self == UHSMODE_A::SDR50 + } + #[doc = "Checks if the value of the field is `SDR104`"] + #[inline(always)] + pub fn is_sdr104(&self) -> bool { + *self == UHSMODE_A::SDR104 + } + #[doc = "Checks if the value of the field is `DDR50`"] + #[inline(always)] + pub fn is_ddr50(&self) -> bool { + *self == UHSMODE_A::DDR50 + } +} +#[doc = "Field `UHSMODE` writer - Select the speed of the SD card"] +pub type UHSMODE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONTROL2_SPEC, u8, UHSMODE_A, 3, O>; +impl<'a, const O: u8> UHSMODE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn sdr12(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR12) + } + #[doc = "`1`"] + #[inline(always)] + pub fn sdr25(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR25) + } + #[doc = "`10`"] + #[inline(always)] + pub fn sdr50(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR50) + } + #[doc = "`11`"] + #[inline(always)] + pub fn sdr104(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR104) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ddr50(self) -> &'a mut W { + self.variant(UHSMODE_A::DDR50) + } +} +#[doc = "Field `TUNEON` reader - SD Clock tune in progress"] +pub type TUNEON_R = crate::BitReader; +#[doc = "Field `TUNEON` writer - SD Clock tune in progress"] +pub type TUNEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +#[doc = "Field `TUNED` reader - Tuned clock is used for sampling data"] +pub type TUNED_R = crate::BitReader; +#[doc = "Field `TUNED` writer - Tuned clock is used for sampling data"] +pub type TUNED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Auto command not executed due to an error"] + #[inline(always)] + pub fn acnox_err(&self) -> ACNOX_ERR_R { + ACNOX_ERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Auto command timeout"] + #[inline(always)] + pub fn acto_err(&self) -> ACTO_ERR_R { + ACTO_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Command CRC error during auto command"] + #[inline(always)] + pub fn accrc_err(&self) -> ACCRC_ERR_R { + ACCRC_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End bit is not 1 during auto command"] + #[inline(always)] + pub fn acend_err(&self) -> ACEND_ERR_R { + ACEND_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Command index error during auto command"] + #[inline(always)] + pub fn acbad_err(&self) -> ACBAD_ERR_R { + ACBAD_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - Error during auto CMD12"] + #[inline(always)] + pub fn notc12_err(&self) -> NOTC12_ERR_R { + NOTC12_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 16:18 - Select the speed of the SD card"] + #[inline(always)] + pub fn uhsmode(&self) -> UHSMODE_R { + UHSMODE_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 22 - SD Clock tune in progress"] + #[inline(always)] + pub fn tuneon(&self) -> TUNEON_R { + TUNEON_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Tuned clock is used for sampling data"] + #[inline(always)] + pub fn tuned(&self) -> TUNED_R { + TUNED_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bits 16:18 - Select the speed of the SD card"] + #[inline(always)] + #[must_use] + pub fn uhsmode(&mut self) -> UHSMODE_W<16> { + UHSMODE_W::new(self) + } + #[doc = "Bit 22 - SD Clock tune in progress"] + #[inline(always)] + #[must_use] + pub fn tuneon(&mut self) -> TUNEON_W<22> { + TUNEON_W::new(self) + } + #[doc = "Bit 23 - Tuned clock is used for sampling data"] + #[inline(always)] + #[must_use] + pub fn tuned(&mut self) -> TUNED_W<23> { + TUNED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control2](index.html) module"] +pub struct CONTROL2_SPEC; +impl crate::RegisterSpec for CONTROL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control2::R](R) reader structure"] +impl crate::Readable for CONTROL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control2::W](W) writer structure"] +impl crate::Writable for CONTROL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL2 to value 0"] +impl crate::Resettable for CONTROL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/data.rs b/crates/bcm2835-lpa/src/emmc/data.rs new file mode 100644 index 0000000..8c082b8 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/data.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data to/from the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/dbg_sel.rs b/crates/bcm2835-lpa/src/emmc/dbg_sel.rs new file mode 100644 index 0000000..c489a27 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/dbg_sel.rs @@ -0,0 +1,126 @@ +#[doc = "Register `DBG_SEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBG_SEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SELECT` reader - "] +pub type SELECT_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SELECT_A { + #[doc = "0: `0`"] + RECEIVER_FIFO = 0, + #[doc = "1: `1`"] + OTHERS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl SELECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SELECT_A { + match self.bits { + false => SELECT_A::RECEIVER_FIFO, + true => SELECT_A::OTHERS, + } + } + #[doc = "Checks if the value of the field is `RECEIVER_FIFO`"] + #[inline(always)] + pub fn is_receiver_fifo(&self) -> bool { + *self == SELECT_A::RECEIVER_FIFO + } + #[doc = "Checks if the value of the field is `OTHERS`"] + #[inline(always)] + pub fn is_others(&self) -> bool { + *self == SELECT_A::OTHERS + } +} +#[doc = "Field `SELECT` writer - "] +pub type SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DBG_SEL_SPEC, SELECT_A, O>; +impl<'a, const O: u8> SELECT_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn receiver_fifo(self) -> &'a mut W { + self.variant(SELECT_A::RECEIVER_FIFO) + } + #[doc = "`1`"] + #[inline(always)] + pub fn others(self) -> &'a mut W { + self.variant(SELECT_A::OTHERS) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W<0> { + SELECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "What submodules are accessed by the debug bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbg_sel](index.html) module"] +pub struct DBG_SEL_SPEC; +impl crate::RegisterSpec for DBG_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbg_sel::R](R) reader structure"] +impl crate::Readable for DBG_SEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbg_sel::W](W) writer structure"] +impl crate::Writable for DBG_SEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBG_SEL to value 0"] +impl crate::Resettable for DBG_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs b/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs new file mode 100644 index 0000000..1c7e3be --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EXRDFIFO_CFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXRDFIFO_CFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RD_THRSH` reader - Read threshold in 32 bit words"] +pub type RD_THRSH_R = crate::FieldReader; +#[doc = "Field `RD_THRSH` writer - Read threshold in 32 bit words"] +pub type RD_THRSH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXRDFIFO_CFG_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Read threshold in 32 bit words"] + #[inline(always)] + pub fn rd_thrsh(&self) -> RD_THRSH_R { + RD_THRSH_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Read threshold in 32 bit words"] + #[inline(always)] + #[must_use] + pub fn rd_thrsh(&mut self) -> RD_THRSH_W<0> { + RD_THRSH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fine tune DMA request generation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_cfg](index.html) module"] +pub struct EXRDFIFO_CFG_SPEC; +impl crate::RegisterSpec for EXRDFIFO_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [exrdfifo_cfg::R](R) reader structure"] +impl crate::Readable for EXRDFIFO_CFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [exrdfifo_cfg::W](W) writer structure"] +impl crate::Writable for EXRDFIFO_CFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXRDFIFO_CFG to value 0"] +impl crate::Resettable for EXRDFIFO_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs b/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs new file mode 100644 index 0000000..26c7adc --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EXRDFIFO_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXRDFIFO_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable the extension FIFO"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable the extension FIFO"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXRDFIFO_EN_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable the extension FIFO"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the extension FIFO"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable the extension data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_en](index.html) module"] +pub struct EXRDFIFO_EN_SPEC; +impl crate::RegisterSpec for EXRDFIFO_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [exrdfifo_en::R](R) reader structure"] +impl crate::Readable for EXRDFIFO_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [exrdfifo_en::W](W) writer structure"] +impl crate::Writable for EXRDFIFO_EN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXRDFIFO_EN to value 0"] +impl crate::Resettable for EXRDFIFO_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/force_irpt.rs b/crates/bcm2835-lpa/src/emmc/force_irpt.rs new file mode 100644 index 0000000..eca9ec6 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/force_irpt.rs @@ -0,0 +1,320 @@ +#[doc = "Register `FORCE_IRPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORCE_IRPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Force an interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [force_irpt](index.html) module"] +pub struct FORCE_IRPT_SPEC; +impl crate::RegisterSpec for FORCE_IRPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [force_irpt::R](R) reader structure"] +impl crate::Readable for FORCE_IRPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [force_irpt::W](W) writer structure"] +impl crate::Writable for FORCE_IRPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FORCE_IRPT to value 0"] +impl crate::Resettable for FORCE_IRPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/interrupt.rs b/crates/bcm2835-lpa/src/emmc/interrupt.rs new file mode 100644 index 0000000..c687814 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/interrupt.rs @@ -0,0 +1,327 @@ +#[doc = "Register `INTERRUPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTERRUPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ERR` reader - An error has occured"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - An error has occured"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt flags\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"] +pub struct INTERRUPT_SPEC; +impl crate::RegisterSpec for INTERRUPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [interrupt::R](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"] +impl crate::Writable for INTERRUPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTERRUPT to value 0"] +impl crate::Resettable for INTERRUPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/irpt_en.rs b/crates/bcm2835-lpa/src/emmc/irpt_en.rs new file mode 100644 index 0000000..0e71317 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/irpt_en.rs @@ -0,0 +1,320 @@ +#[doc = "Register `IRPT_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRPT_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt to core\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_en](index.html) module"] +pub struct IRPT_EN_SPEC; +impl crate::RegisterSpec for IRPT_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irpt_en::R](R) reader structure"] +impl crate::Readable for IRPT_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irpt_en::W](W) writer structure"] +impl crate::Writable for IRPT_EN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRPT_EN to value 0"] +impl crate::Resettable for IRPT_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/irpt_mask.rs b/crates/bcm2835-lpa/src/emmc/irpt_mask.rs new file mode 100644 index 0000000..87a9fdd --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/irpt_mask.rs @@ -0,0 +1,320 @@ +#[doc = "Register `IRPT_MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRPT_MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Mask interrupts that change in INTERRUPT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_mask](index.html) module"] +pub struct IRPT_MASK_SPEC; +impl crate::RegisterSpec for IRPT_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irpt_mask::R](R) reader structure"] +impl crate::Readable for IRPT_MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irpt_mask::W](W) writer structure"] +impl crate::Writable for IRPT_MASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRPT_MASK to value 0"] +impl crate::Resettable for IRPT_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/resp0.rs b/crates/bcm2835-lpa/src/emmc/resp0.rs new file mode 100644 index 0000000..1022d1a --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/resp0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status bits of the response\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp0](index.html) module"] +pub struct RESP0_SPEC; +impl crate::RegisterSpec for RESP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp0::R](R) reader structure"] +impl crate::Readable for RESP0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp0::W](W) writer structure"] +impl crate::Writable for RESP0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP0 to value 0"] +impl crate::Resettable for RESP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/resp1.rs b/crates/bcm2835-lpa/src/emmc/resp1.rs new file mode 100644 index 0000000..d1e9b42 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/resp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp1](index.html) module"] +pub struct RESP1_SPEC; +impl crate::RegisterSpec for RESP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp1::R](R) reader structure"] +impl crate::Readable for RESP1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp1::W](W) writer structure"] +impl crate::Writable for RESP1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP1 to value 0"] +impl crate::Resettable for RESP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/resp2.rs b/crates/bcm2835-lpa/src/emmc/resp2.rs new file mode 100644 index 0000000..418942a --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/resp2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp2](index.html) module"] +pub struct RESP2_SPEC; +impl crate::RegisterSpec for RESP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp2::R](R) reader structure"] +impl crate::Readable for RESP2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp2::W](W) writer structure"] +impl crate::Writable for RESP2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP2 to value 0"] +impl crate::Resettable for RESP2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/resp3.rs b/crates/bcm2835-lpa/src/emmc/resp3.rs new file mode 100644 index 0000000..36b2c80 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/resp3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp3](index.html) module"] +pub struct RESP3_SPEC; +impl crate::RegisterSpec for RESP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp3::R](R) reader structure"] +impl crate::Readable for RESP3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp3::W](W) writer structure"] +impl crate::Writable for RESP3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP3 to value 0"] +impl crate::Resettable for RESP3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs b/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs new file mode 100644 index 0000000..6016436 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SLOTISR_VER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLOTISR_VER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_STATUS` reader - OR of interrupt and wakeup signals for each slot"] +pub type SLOT_STATUS_R = crate::FieldReader; +#[doc = "Field `SLOT_STATUS` writer - OR of interrupt and wakeup signals for each slot"] +pub type SLOT_STATUS_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +#[doc = "Field `SDVERSION` reader - Host controller specification version"] +pub type SDVERSION_R = crate::FieldReader; +#[doc = "Field `SDVERSION` writer - Host controller specification version"] +pub type SDVERSION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +#[doc = "Field `VENDOR` reader - Vendor version number"] +pub type VENDOR_R = crate::FieldReader; +#[doc = "Field `VENDOR` writer - Vendor version number"] +pub type VENDOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] + #[inline(always)] + pub fn slot_status(&self) -> SLOT_STATUS_R { + SLOT_STATUS_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Host controller specification version"] + #[inline(always)] + pub fn sdversion(&self) -> SDVERSION_R { + SDVERSION_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Vendor version number"] + #[inline(always)] + pub fn vendor(&self) -> VENDOR_R { + VENDOR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] + #[inline(always)] + #[must_use] + pub fn slot_status(&mut self) -> SLOT_STATUS_W<0> { + SLOT_STATUS_W::new(self) + } + #[doc = "Bits 16:23 - Host controller specification version"] + #[inline(always)] + #[must_use] + pub fn sdversion(&mut self) -> SDVERSION_W<16> { + SDVERSION_W::new(self) + } + #[doc = "Bits 24:31 - Vendor version number"] + #[inline(always)] + #[must_use] + pub fn vendor(&mut self) -> VENDOR_W<24> { + VENDOR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Version information and slot interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slotisr_ver](index.html) module"] +pub struct SLOTISR_VER_SPEC; +impl crate::RegisterSpec for SLOTISR_VER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [slotisr_ver::R](R) reader structure"] +impl crate::Readable for SLOTISR_VER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [slotisr_ver::W](W) writer structure"] +impl crate::Writable for SLOTISR_VER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLOTISR_VER to value 0"] +impl crate::Resettable for SLOTISR_VER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs b/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs new file mode 100644 index 0000000..bce7edc --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SPI_INT_SPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SPI_INT_SPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SELECT` reader - "] +pub type SELECT_R = crate::FieldReader; +#[doc = "Field `SELECT` writer - "] +pub type SELECT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_INT_SPT_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W<0> { + SELECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupts in SPI mode depend on CS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_int_spt](index.html) module"] +pub struct SPI_INT_SPT_SPEC; +impl crate::RegisterSpec for SPI_INT_SPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [spi_int_spt::R](R) reader structure"] +impl crate::Readable for SPI_INT_SPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [spi_int_spt::W](W) writer structure"] +impl crate::Writable for SPI_INT_SPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_INT_SPT to value 0"] +impl crate::Resettable for SPI_INT_SPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/status.rs b/crates/bcm2835-lpa/src/emmc/status.rs new file mode 100644 index 0000000..0b86ab0 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/status.rs @@ -0,0 +1,215 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_INHIBIT` reader - Command line still in use"] +pub type CMD_INHIBIT_R = crate::BitReader; +#[doc = "Field `CMD_INHIBIT` writer - Command line still in use"] +pub type CMD_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_INHIBIT` reader - Data lines still in use"] +pub type DAT_INHIBIT_R = crate::BitReader; +#[doc = "Field `DAT_INHIBIT` writer - Data lines still in use"] +pub type DAT_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_ACTIVE` reader - At least one data line is active"] +pub type DAT_ACTIVE_R = crate::BitReader; +#[doc = "Field `DAT_ACTIVE` writer - At least one data line is active"] +pub type DAT_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `WRITE_TRANSFER` reader - Write transfer is active"] +pub type WRITE_TRANSFER_R = crate::BitReader; +#[doc = "Field `WRITE_TRANSFER` writer - Write transfer is active"] +pub type WRITE_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `READ_TRANSFER` reader - Read transfer is active"] +pub type READ_TRANSFER_R = crate::BitReader; +#[doc = "Field `READ_TRANSFER` writer - Read transfer is active"] +pub type READ_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFFER_WRITE_ENABLE` reader - The buffer has space for new data"] +pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; +#[doc = "Field `BUFFER_WRITE_ENABLE` writer - The buffer has space for new data"] +pub type BUFFER_WRITE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFFER_READ_ENABLE` reader - New data is available to read"] +pub type BUFFER_READ_ENABLE_R = crate::BitReader; +#[doc = "Field `BUFFER_READ_ENABLE` writer - New data is available to read"] +pub type BUFFER_READ_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_LEVEL0` reader - Value of DAT\\[3:0\\]"] +pub type DAT_LEVEL0_R = crate::FieldReader; +#[doc = "Field `DAT_LEVEL0` writer - Value of DAT\\[3:0\\]"] +pub type DAT_LEVEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +#[doc = "Field `CMD_LEVEL` reader - Value of CMD"] +pub type CMD_LEVEL_R = crate::BitReader; +#[doc = "Field `CMD_LEVEL` writer - Value of CMD"] +pub type CMD_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_LEVEL1` reader - Value of DAT\\[7:4\\]"] +pub type DAT_LEVEL1_R = crate::FieldReader; +#[doc = "Field `DAT_LEVEL1` writer - Value of DAT\\[7:4\\]"] +pub type DAT_LEVEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Command line still in use"] + #[inline(always)] + pub fn cmd_inhibit(&self) -> CMD_INHIBIT_R { + CMD_INHIBIT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data lines still in use"] + #[inline(always)] + pub fn dat_inhibit(&self) -> DAT_INHIBIT_R { + DAT_INHIBIT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - At least one data line is active"] + #[inline(always)] + pub fn dat_active(&self) -> DAT_ACTIVE_R { + DAT_ACTIVE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Write transfer is active"] + #[inline(always)] + pub fn write_transfer(&self) -> WRITE_TRANSFER_R { + WRITE_TRANSFER_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Read transfer is active"] + #[inline(always)] + pub fn read_transfer(&self) -> READ_TRANSFER_R { + READ_TRANSFER_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The buffer has space for new data"] + #[inline(always)] + pub fn buffer_write_enable(&self) -> BUFFER_WRITE_ENABLE_R { + BUFFER_WRITE_ENABLE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - New data is available to read"] + #[inline(always)] + pub fn buffer_read_enable(&self) -> BUFFER_READ_ENABLE_R { + BUFFER_READ_ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] + #[inline(always)] + pub fn dat_level0(&self) -> DAT_LEVEL0_R { + DAT_LEVEL0_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - Value of CMD"] + #[inline(always)] + pub fn cmd_level(&self) -> CMD_LEVEL_R { + CMD_LEVEL_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] + #[inline(always)] + pub fn dat_level1(&self) -> DAT_LEVEL1_R { + DAT_LEVEL1_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Command line still in use"] + #[inline(always)] + #[must_use] + pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W<0> { + CMD_INHIBIT_W::new(self) + } + #[doc = "Bit 1 - Data lines still in use"] + #[inline(always)] + #[must_use] + pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W<1> { + DAT_INHIBIT_W::new(self) + } + #[doc = "Bit 2 - At least one data line is active"] + #[inline(always)] + #[must_use] + pub fn dat_active(&mut self) -> DAT_ACTIVE_W<2> { + DAT_ACTIVE_W::new(self) + } + #[doc = "Bit 8 - Write transfer is active"] + #[inline(always)] + #[must_use] + pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W<8> { + WRITE_TRANSFER_W::new(self) + } + #[doc = "Bit 9 - Read transfer is active"] + #[inline(always)] + #[must_use] + pub fn read_transfer(&mut self) -> READ_TRANSFER_W<9> { + READ_TRANSFER_W::new(self) + } + #[doc = "Bit 10 - The buffer has space for new data"] + #[inline(always)] + #[must_use] + pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W<10> { + BUFFER_WRITE_ENABLE_W::new(self) + } + #[doc = "Bit 11 - New data is available to read"] + #[inline(always)] + #[must_use] + pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W<11> { + BUFFER_READ_ENABLE_W::new(self) + } + #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn dat_level0(&mut self) -> DAT_LEVEL0_W<20> { + DAT_LEVEL0_W::new(self) + } + #[doc = "Bit 24 - Value of CMD"] + #[inline(always)] + #[must_use] + pub fn cmd_level(&mut self) -> CMD_LEVEL_W<24> { + CMD_LEVEL_W::new(self) + } + #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] + #[inline(always)] + #[must_use] + pub fn dat_level1(&mut self) -> DAT_LEVEL1_W<25> { + DAT_LEVEL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status info for debugging\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/tune_step.rs b/crates/bcm2835-lpa/src/emmc/tune_step.rs new file mode 100644 index 0000000..2f0169b --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/tune_step.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DELAY` reader - "] +pub type DELAY_R = crate::FieldReader; +#[doc = "Field `DELAY` writer - "] +pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEP_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn delay(&self) -> DELAY_R { + DELAY_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2"] + #[inline(always)] + #[must_use] + pub fn delay(&mut self) -> DELAY_W<0> { + DELAY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step duration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_step](index.html) module"] +pub struct TUNE_STEP_SPEC; +impl crate::RegisterSpec for TUNE_STEP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_step::R](R) reader structure"] +impl crate::Readable for TUNE_STEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_step::W](W) writer structure"] +impl crate::Writable for TUNE_STEP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEP to value 0"] +impl crate::Resettable for TUNE_STEP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs b/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs new file mode 100644 index 0000000..a8fea76 --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEPS_DDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEPS_DDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STEPS` reader - "] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - "] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_DDR_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<0> { + STEPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step count for DDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_ddr](index.html) module"] +pub struct TUNE_STEPS_DDR_SPEC; +impl crate::RegisterSpec for TUNE_STEPS_DDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_steps_ddr::R](R) reader structure"] +impl crate::Readable for TUNE_STEPS_DDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_steps_ddr::W](W) writer structure"] +impl crate::Writable for TUNE_STEPS_DDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEPS_DDR to value 0"] +impl crate::Resettable for TUNE_STEPS_DDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs b/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs new file mode 100644 index 0000000..c04740c --- /dev/null +++ b/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEPS_STD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEPS_STD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STEPS` reader - "] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - "] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_STD_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<0> { + STEPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step count for SDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_std](index.html) module"] +pub struct TUNE_STEPS_STD_SPEC; +impl crate::RegisterSpec for TUNE_STEPS_STD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_steps_std::R](R) reader structure"] +impl crate::Readable for TUNE_STEPS_STD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_steps_std::W](W) writer structure"] +impl crate::Writable for TUNE_STEPS_STD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEPS_STD to value 0"] +impl crate::Resettable for TUNE_STEPS_STD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/generic.rs b/crates/bcm2835-lpa/src/generic.rs new file mode 100644 index 0000000..f10ca73 --- /dev/null +++ b/crates/bcm2835-lpa/src/generic.rs @@ -0,0 +1,695 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc(hidden)] +pub struct FieldReaderRaw { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReaderRaw +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitReaderRaw { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReaderRaw { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = FieldReaderRaw; +#[doc = " Bit-wise field reader"] +pub type BitReader = BitReaderRaw; +impl FieldReader +where + U: Copy, +{ + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy, + U: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&U::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc(hidden)] +pub struct Safe; +#[doc(hidden)] +pub struct Unsafe; +#[doc(hidden)] +pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> +where + REG: Writable + RegisterSpec, + N: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(N, FI, Safety)>, +} +impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> + FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + } + }; +} +macro_rules! impl_bit_proxy { + ($ writer : ident) => { + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, + { + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w.bits |= (U::from(value) & U::one()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + unsafe { self.bits(N::from(variant)) } + } +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bits(N::from(variant)) + } +} +impl_bit_proxy!(BitWriter); +impl_bit_proxy!(BitWriter1S); +impl_bit_proxy!(BitWriter0C); +impl_bit_proxy!(BitWriter1C); +impl_bit_proxy!(BitWriter0S); +impl_bit_proxy!(BitWriter1T); +impl_bit_proxy!(BitWriter0T); +impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +mod atomic; +use atomic::AtomicOperations; +impl Reg +where + REG::Ux: AtomicOperations + Default + core::ops::Not, +{ + #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn set_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: Default::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_or(self.register.as_ptr(), bits); + } + #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn clear_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: !REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_and(self.register.as_ptr(), bits); + } + #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn toggle_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: Default::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_xor(self.register.as_ptr(), bits); + } +} diff --git a/crates/bcm2835-lpa/src/generic/atomic.rs b/crates/bcm2835-lpa/src/generic/atomic.rs new file mode 100644 index 0000000..acee997 --- /dev/null +++ b/crates/bcm2835-lpa/src/generic/atomic.rs @@ -0,0 +1,27 @@ +use portable_atomic::Ordering; +pub trait AtomicOperations { + unsafe fn atomic_or(ptr: *mut Self, val: Self); + unsafe fn atomic_and(ptr: *mut Self, val: Self); + unsafe fn atomic_xor(ptr: *mut Self, val: Self); +} +macro_rules! impl_atomics { + ($ U : ty , $ Atomic : ty) => { + impl AtomicOperations for $U { + unsafe fn atomic_or(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).or(val, Ordering::SeqCst); + } + unsafe fn atomic_and(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).and(val, Ordering::SeqCst); + } + unsafe fn atomic_xor(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).xor(val, Ordering::SeqCst); + } + } + }; +} +impl_atomics!(u8, portable_atomic::AtomicU8); +impl_atomics!(u16, portable_atomic::AtomicU16); +#[cfg(not(target_pointer_width = "16"))] +impl_atomics!(u32, portable_atomic::AtomicU32); +#[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))] +impl_atomics!(u64, portable_atomic::AtomicU64); diff --git a/crates/bcm2835-lpa/src/gpio.rs b/crates/bcm2835-lpa/src/gpio.rs new file mode 100644 index 0000000..e643036 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio.rs @@ -0,0 +1,206 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - GPIO Function Select 0"] + pub gpfsel0: GPFSEL0, + #[doc = "0x04 - GPIO Function Select 1"] + pub gpfsel1: GPFSEL1, + #[doc = "0x08 - GPIO Function Select 2"] + pub gpfsel2: GPFSEL2, + #[doc = "0x0c - GPIO Function Select 3"] + pub gpfsel3: GPFSEL3, + #[doc = "0x10 - GPIO Function Select 4"] + pub gpfsel4: GPFSEL4, + #[doc = "0x14 - GPIO Function Select 5"] + pub gpfsel5: GPFSEL5, + _reserved6: [u8; 0x04], + #[doc = "0x1c - GPIO Pin Output Set 0"] + pub gpset0: GPSET0, + #[doc = "0x20 - GPIO Pin Output Set 1"] + pub gpset1: GPSET1, + _reserved8: [u8; 0x04], + #[doc = "0x28 - GPIO Pin Output Clear 0"] + pub gpclr0: GPCLR0, + #[doc = "0x2c - GPIO Pin Output Clear 1"] + pub gpclr1: GPCLR1, + _reserved10: [u8; 0x04], + #[doc = "0x34 - GPIO Pin Level 0"] + pub gplev0: GPLEV0, + #[doc = "0x38 - GPIO Pin Level 1"] + pub gplev1: GPLEV1, + _reserved12: [u8; 0x04], + #[doc = "0x40 - GPIO Pin Event Detect Status 0"] + pub gpeds0: GPEDS0, + #[doc = "0x44 - GPIO Pin Event Detect Status 1"] + pub gpeds1: GPEDS1, + _reserved14: [u8; 0x04], + #[doc = "0x4c - GPIO Pin Rising Edge Detect Enable 0"] + pub gpren0: GPREN0, + #[doc = "0x50 - GPIO Pin Rising Edge Detect Enable 1"] + pub gpren1: GPREN1, + _reserved16: [u8; 0x04], + #[doc = "0x58 - GPIO Pin Falling Edge Detect Enable 0"] + pub gpfen0: GPFEN0, + #[doc = "0x5c - GPIO Pin Falling Edge Detect Enable 1"] + pub gpfen1: GPFEN1, + _reserved18: [u8; 0x04], + #[doc = "0x64 - GPIO Pin High Detect Enable 0"] + pub gphen0: GPHEN0, + #[doc = "0x68 - GPIO Pin High Detect Enable 1"] + pub gphen1: GPHEN1, + _reserved20: [u8; 0x04], + #[doc = "0x70 - GPIO Pin Low Detect Enable 0"] + pub gplen0: GPLEN0, + #[doc = "0x74 - GPIO Pin Low Detect Enable 1"] + pub gplen1: GPLEN1, + _reserved22: [u8; 0x04], + #[doc = "0x7c - GPIO Pin Async. Rising Edge Detect 0"] + pub gparen0: GPAREN0, + #[doc = "0x80 - GPIO Pin Async. Rising Edge Detect 1"] + pub gparen1: GPAREN1, + _reserved24: [u8; 0x04], + #[doc = "0x88 - GPIO Pin Async. Falling Edge Detect 0"] + pub gpafen0: GPAFEN0, + #[doc = "0x8c - GPIO Pin Async. Falling Edge Detect 1"] + pub gpafen1: GPAFEN1, + _reserved26: [u8; 0x40], + #[doc = "0xd0 - Undocumented multiplexing bits"] + pub extra_mux: EXTRA_MUX, + _reserved27: [u8; 0x10], + #[doc = "0xe4 - GPIO Pull-up / Pull-down Register 0"] + pub gpio_pup_pdn_cntrl_reg0: GPIO_PUP_PDN_CNTRL_REG0, + #[doc = "0xe8 - GPIO Pull-up / Pull-down Register 1"] + pub gpio_pup_pdn_cntrl_reg1: GPIO_PUP_PDN_CNTRL_REG1, + #[doc = "0xec - GPIO Pull-up / Pull-down Register 2"] + pub gpio_pup_pdn_cntrl_reg2: GPIO_PUP_PDN_CNTRL_REG2, + #[doc = "0xf0 - GPIO Pull-up / Pull-down Register 3"] + pub gpio_pup_pdn_cntrl_reg3: GPIO_PUP_PDN_CNTRL_REG3, +} +#[doc = "GPFSEL0 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL0 = crate::Reg; +#[doc = "GPIO Function Select 0"] +pub mod gpfsel0; +#[doc = "GPFSEL1 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL1 = crate::Reg; +#[doc = "GPIO Function Select 1"] +pub mod gpfsel1; +#[doc = "GPFSEL2 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL2 = crate::Reg; +#[doc = "GPIO Function Select 2"] +pub mod gpfsel2; +#[doc = "GPFSEL3 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL3 = crate::Reg; +#[doc = "GPIO Function Select 3"] +pub mod gpfsel3; +#[doc = "GPFSEL4 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL4 = crate::Reg; +#[doc = "GPIO Function Select 4"] +pub mod gpfsel4; +#[doc = "GPFSEL5 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL5 = crate::Reg; +#[doc = "GPIO Function Select 5"] +pub mod gpfsel5; +#[doc = "GPSET0 (w) register accessor: an alias for `Reg`"] +pub type GPSET0 = crate::Reg; +#[doc = "GPIO Pin Output Set 0"] +pub mod gpset0; +#[doc = "GPSET1 (w) register accessor: an alias for `Reg`"] +pub type GPSET1 = crate::Reg; +#[doc = "GPIO Pin Output Set 1"] +pub mod gpset1; +#[doc = "GPCLR0 (w) register accessor: an alias for `Reg`"] +pub type GPCLR0 = crate::Reg; +#[doc = "GPIO Pin Output Clear 0"] +pub mod gpclr0; +#[doc = "GPCLR1 (w) register accessor: an alias for `Reg`"] +pub type GPCLR1 = crate::Reg; +#[doc = "GPIO Pin Output Clear 1"] +pub mod gpclr1; +#[doc = "GPLEV0 (r) register accessor: an alias for `Reg`"] +pub type GPLEV0 = crate::Reg; +#[doc = "GPIO Pin Level 0"] +pub mod gplev0; +#[doc = "GPLEV1 (r) register accessor: an alias for `Reg`"] +pub type GPLEV1 = crate::Reg; +#[doc = "GPIO Pin Level 1"] +pub mod gplev1; +#[doc = "GPEDS0 (rw) register accessor: an alias for `Reg`"] +pub type GPEDS0 = crate::Reg; +#[doc = "GPIO Pin Event Detect Status 0"] +pub mod gpeds0; +#[doc = "GPEDS1 (rw) register accessor: an alias for `Reg`"] +pub type GPEDS1 = crate::Reg; +#[doc = "GPIO Pin Event Detect Status 1"] +pub mod gpeds1; +#[doc = "GPREN0 (rw) register accessor: an alias for `Reg`"] +pub type GPREN0 = crate::Reg; +#[doc = "GPIO Pin Rising Edge Detect Enable 0"] +pub mod gpren0; +#[doc = "GPREN1 (rw) register accessor: an alias for `Reg`"] +pub type GPREN1 = crate::Reg; +#[doc = "GPIO Pin Rising Edge Detect Enable 1"] +pub mod gpren1; +#[doc = "GPFEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPFEN0 = crate::Reg; +#[doc = "GPIO Pin Falling Edge Detect Enable 0"] +pub mod gpfen0; +#[doc = "GPFEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPFEN1 = crate::Reg; +#[doc = "GPIO Pin Falling Edge Detect Enable 1"] +pub mod gpfen1; +#[doc = "GPHEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPHEN0 = crate::Reg; +#[doc = "GPIO Pin High Detect Enable 0"] +pub mod gphen0; +#[doc = "GPHEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPHEN1 = crate::Reg; +#[doc = "GPIO Pin High Detect Enable 1"] +pub mod gphen1; +#[doc = "GPLEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPLEN0 = crate::Reg; +#[doc = "GPIO Pin Low Detect Enable 0"] +pub mod gplen0; +#[doc = "GPLEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPLEN1 = crate::Reg; +#[doc = "GPIO Pin Low Detect Enable 1"] +pub mod gplen1; +#[doc = "GPAREN0 (rw) register accessor: an alias for `Reg`"] +pub type GPAREN0 = crate::Reg; +#[doc = "GPIO Pin Async. Rising Edge Detect 0"] +pub mod gparen0; +#[doc = "GPAREN1 (rw) register accessor: an alias for `Reg`"] +pub type GPAREN1 = crate::Reg; +#[doc = "GPIO Pin Async. Rising Edge Detect 1"] +pub mod gparen1; +#[doc = "GPAFEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPAFEN0 = crate::Reg; +#[doc = "GPIO Pin Async. Falling Edge Detect 0"] +pub mod gpafen0; +#[doc = "GPAFEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPAFEN1 = crate::Reg; +#[doc = "GPIO Pin Async. Falling Edge Detect 1"] +pub mod gpafen1; +#[doc = "EXTRA_MUX (rw) register accessor: an alias for `Reg`"] +pub type EXTRA_MUX = crate::Reg; +#[doc = "Undocumented multiplexing bits"] +pub mod extra_mux; +#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG0 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 0"] +pub mod gpio_pup_pdn_cntrl_reg0; +#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG1 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 1"] +pub mod gpio_pup_pdn_cntrl_reg1; +#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG2 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 2"] +pub mod gpio_pup_pdn_cntrl_reg2; +#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG3 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 3"] +pub mod gpio_pup_pdn_cntrl_reg3; diff --git a/crates/bcm2835-lpa/src/gpio/extra_mux.rs b/crates/bcm2835-lpa/src/gpio/extra_mux.rs new file mode 100644 index 0000000..a35ba4f --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/extra_mux.rs @@ -0,0 +1,122 @@ +#[doc = "Register `EXTRA_MUX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTRA_MUX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDIO` reader - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +pub type SDIO_R = crate::BitReader; +#[doc = "Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SDIO_A { + #[doc = "0: Connect the newer SD host"] + SDHOST = 0, + #[doc = "1: Connect Arasan SD/EMMC host"] + ARASAN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SDIO_A) -> Self { + variant as u8 != 0 + } +} +impl SDIO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDIO_A { + match self.bits { + false => SDIO_A::SDHOST, + true => SDIO_A::ARASAN, + } + } + #[doc = "Checks if the value of the field is `SDHOST`"] + #[inline(always)] + pub fn is_sdhost(&self) -> bool { + *self == SDIO_A::SDHOST + } + #[doc = "Checks if the value of the field is `ARASAN`"] + #[inline(always)] + pub fn is_arasan(&self) -> bool { + *self == SDIO_A::ARASAN + } +} +#[doc = "Field `SDIO` writer - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +pub type SDIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTRA_MUX_SPEC, SDIO_A, O>; +impl<'a, const O: u8> SDIO_W<'a, O> { + #[doc = "Connect the newer SD host"] + #[inline(always)] + pub fn sdhost(self) -> &'a mut W { + self.variant(SDIO_A::SDHOST) + } + #[doc = "Connect Arasan SD/EMMC host"] + #[inline(always)] + pub fn arasan(self) -> &'a mut W { + self.variant(SDIO_A::ARASAN) + } +} +impl R { + #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] + #[inline(always)] + pub fn sdio(&self) -> SDIO_R { + SDIO_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] + #[inline(always)] + #[must_use] + pub fn sdio(&mut self) -> SDIO_W<1> { + SDIO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Undocumented multiplexing bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extra_mux](index.html) module"] +pub struct EXTRA_MUX_SPEC; +impl crate::RegisterSpec for EXTRA_MUX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [extra_mux::R](R) reader structure"] +impl crate::Readable for EXTRA_MUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extra_mux::W](W) writer structure"] +impl crate::Writable for EXTRA_MUX_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpafen0.rs b/crates/bcm2835-lpa/src/gpio/gpafen0.rs new file mode 100644 index 0000000..5c84fd8 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpafen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPAFEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAFEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AFEN0` reader - Async falling enabled 0"] +pub type AFEN0_R = crate::BitReader; +#[doc = "Field `AFEN0` writer - Async falling enabled 0"] +pub type AFEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN1` reader - Async falling enabled 1"] +pub type AFEN1_R = crate::BitReader; +#[doc = "Field `AFEN1` writer - Async falling enabled 1"] +pub type AFEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN2` reader - Async falling enabled 2"] +pub type AFEN2_R = crate::BitReader; +#[doc = "Field `AFEN2` writer - Async falling enabled 2"] +pub type AFEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN3` reader - Async falling enabled 3"] +pub type AFEN3_R = crate::BitReader; +#[doc = "Field `AFEN3` writer - Async falling enabled 3"] +pub type AFEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN4` reader - Async falling enabled 4"] +pub type AFEN4_R = crate::BitReader; +#[doc = "Field `AFEN4` writer - Async falling enabled 4"] +pub type AFEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN5` reader - Async falling enabled 5"] +pub type AFEN5_R = crate::BitReader; +#[doc = "Field `AFEN5` writer - Async falling enabled 5"] +pub type AFEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN6` reader - Async falling enabled 6"] +pub type AFEN6_R = crate::BitReader; +#[doc = "Field `AFEN6` writer - Async falling enabled 6"] +pub type AFEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN7` reader - Async falling enabled 7"] +pub type AFEN7_R = crate::BitReader; +#[doc = "Field `AFEN7` writer - Async falling enabled 7"] +pub type AFEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN8` reader - Async falling enabled 8"] +pub type AFEN8_R = crate::BitReader; +#[doc = "Field `AFEN8` writer - Async falling enabled 8"] +pub type AFEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN9` reader - Async falling enabled 9"] +pub type AFEN9_R = crate::BitReader; +#[doc = "Field `AFEN9` writer - Async falling enabled 9"] +pub type AFEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN10` reader - Async falling enabled 10"] +pub type AFEN10_R = crate::BitReader; +#[doc = "Field `AFEN10` writer - Async falling enabled 10"] +pub type AFEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN11` reader - Async falling enabled 11"] +pub type AFEN11_R = crate::BitReader; +#[doc = "Field `AFEN11` writer - Async falling enabled 11"] +pub type AFEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN12` reader - Async falling enabled 12"] +pub type AFEN12_R = crate::BitReader; +#[doc = "Field `AFEN12` writer - Async falling enabled 12"] +pub type AFEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN13` reader - Async falling enabled 13"] +pub type AFEN13_R = crate::BitReader; +#[doc = "Field `AFEN13` writer - Async falling enabled 13"] +pub type AFEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN14` reader - Async falling enabled 14"] +pub type AFEN14_R = crate::BitReader; +#[doc = "Field `AFEN14` writer - Async falling enabled 14"] +pub type AFEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN15` reader - Async falling enabled 15"] +pub type AFEN15_R = crate::BitReader; +#[doc = "Field `AFEN15` writer - Async falling enabled 15"] +pub type AFEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN16` reader - Async falling enabled 16"] +pub type AFEN16_R = crate::BitReader; +#[doc = "Field `AFEN16` writer - Async falling enabled 16"] +pub type AFEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN17` reader - Async falling enabled 17"] +pub type AFEN17_R = crate::BitReader; +#[doc = "Field `AFEN17` writer - Async falling enabled 17"] +pub type AFEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN18` reader - Async falling enabled 18"] +pub type AFEN18_R = crate::BitReader; +#[doc = "Field `AFEN18` writer - Async falling enabled 18"] +pub type AFEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN19` reader - Async falling enabled 19"] +pub type AFEN19_R = crate::BitReader; +#[doc = "Field `AFEN19` writer - Async falling enabled 19"] +pub type AFEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN20` reader - Async falling enabled 20"] +pub type AFEN20_R = crate::BitReader; +#[doc = "Field `AFEN20` writer - Async falling enabled 20"] +pub type AFEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN21` reader - Async falling enabled 21"] +pub type AFEN21_R = crate::BitReader; +#[doc = "Field `AFEN21` writer - Async falling enabled 21"] +pub type AFEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN22` reader - Async falling enabled 22"] +pub type AFEN22_R = crate::BitReader; +#[doc = "Field `AFEN22` writer - Async falling enabled 22"] +pub type AFEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN23` reader - Async falling enabled 23"] +pub type AFEN23_R = crate::BitReader; +#[doc = "Field `AFEN23` writer - Async falling enabled 23"] +pub type AFEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN24` reader - Async falling enabled 24"] +pub type AFEN24_R = crate::BitReader; +#[doc = "Field `AFEN24` writer - Async falling enabled 24"] +pub type AFEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN25` reader - Async falling enabled 25"] +pub type AFEN25_R = crate::BitReader; +#[doc = "Field `AFEN25` writer - Async falling enabled 25"] +pub type AFEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN26` reader - Async falling enabled 26"] +pub type AFEN26_R = crate::BitReader; +#[doc = "Field `AFEN26` writer - Async falling enabled 26"] +pub type AFEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN27` reader - Async falling enabled 27"] +pub type AFEN27_R = crate::BitReader; +#[doc = "Field `AFEN27` writer - Async falling enabled 27"] +pub type AFEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN28` reader - Async falling enabled 28"] +pub type AFEN28_R = crate::BitReader; +#[doc = "Field `AFEN28` writer - Async falling enabled 28"] +pub type AFEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN29` reader - Async falling enabled 29"] +pub type AFEN29_R = crate::BitReader; +#[doc = "Field `AFEN29` writer - Async falling enabled 29"] +pub type AFEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN30` reader - Async falling enabled 30"] +pub type AFEN30_R = crate::BitReader; +#[doc = "Field `AFEN30` writer - Async falling enabled 30"] +pub type AFEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN31` reader - Async falling enabled 31"] +pub type AFEN31_R = crate::BitReader; +#[doc = "Field `AFEN31` writer - Async falling enabled 31"] +pub type AFEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async falling enabled 0"] + #[inline(always)] + pub fn afen0(&self) -> AFEN0_R { + AFEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async falling enabled 1"] + #[inline(always)] + pub fn afen1(&self) -> AFEN1_R { + AFEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async falling enabled 2"] + #[inline(always)] + pub fn afen2(&self) -> AFEN2_R { + AFEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async falling enabled 3"] + #[inline(always)] + pub fn afen3(&self) -> AFEN3_R { + AFEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async falling enabled 4"] + #[inline(always)] + pub fn afen4(&self) -> AFEN4_R { + AFEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async falling enabled 5"] + #[inline(always)] + pub fn afen5(&self) -> AFEN5_R { + AFEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async falling enabled 6"] + #[inline(always)] + pub fn afen6(&self) -> AFEN6_R { + AFEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async falling enabled 7"] + #[inline(always)] + pub fn afen7(&self) -> AFEN7_R { + AFEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async falling enabled 8"] + #[inline(always)] + pub fn afen8(&self) -> AFEN8_R { + AFEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async falling enabled 9"] + #[inline(always)] + pub fn afen9(&self) -> AFEN9_R { + AFEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async falling enabled 10"] + #[inline(always)] + pub fn afen10(&self) -> AFEN10_R { + AFEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async falling enabled 11"] + #[inline(always)] + pub fn afen11(&self) -> AFEN11_R { + AFEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async falling enabled 12"] + #[inline(always)] + pub fn afen12(&self) -> AFEN12_R { + AFEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async falling enabled 13"] + #[inline(always)] + pub fn afen13(&self) -> AFEN13_R { + AFEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async falling enabled 14"] + #[inline(always)] + pub fn afen14(&self) -> AFEN14_R { + AFEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async falling enabled 15"] + #[inline(always)] + pub fn afen15(&self) -> AFEN15_R { + AFEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async falling enabled 16"] + #[inline(always)] + pub fn afen16(&self) -> AFEN16_R { + AFEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async falling enabled 17"] + #[inline(always)] + pub fn afen17(&self) -> AFEN17_R { + AFEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async falling enabled 18"] + #[inline(always)] + pub fn afen18(&self) -> AFEN18_R { + AFEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async falling enabled 19"] + #[inline(always)] + pub fn afen19(&self) -> AFEN19_R { + AFEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async falling enabled 20"] + #[inline(always)] + pub fn afen20(&self) -> AFEN20_R { + AFEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async falling enabled 21"] + #[inline(always)] + pub fn afen21(&self) -> AFEN21_R { + AFEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async falling enabled 22"] + #[inline(always)] + pub fn afen22(&self) -> AFEN22_R { + AFEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async falling enabled 23"] + #[inline(always)] + pub fn afen23(&self) -> AFEN23_R { + AFEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async falling enabled 24"] + #[inline(always)] + pub fn afen24(&self) -> AFEN24_R { + AFEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async falling enabled 25"] + #[inline(always)] + pub fn afen25(&self) -> AFEN25_R { + AFEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Async falling enabled 26"] + #[inline(always)] + pub fn afen26(&self) -> AFEN26_R { + AFEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Async falling enabled 27"] + #[inline(always)] + pub fn afen27(&self) -> AFEN27_R { + AFEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Async falling enabled 28"] + #[inline(always)] + pub fn afen28(&self) -> AFEN28_R { + AFEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Async falling enabled 29"] + #[inline(always)] + pub fn afen29(&self) -> AFEN29_R { + AFEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Async falling enabled 30"] + #[inline(always)] + pub fn afen30(&self) -> AFEN30_R { + AFEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Async falling enabled 31"] + #[inline(always)] + pub fn afen31(&self) -> AFEN31_R { + AFEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async falling enabled 0"] + #[inline(always)] + #[must_use] + pub fn afen0(&mut self) -> AFEN0_W<0> { + AFEN0_W::new(self) + } + #[doc = "Bit 1 - Async falling enabled 1"] + #[inline(always)] + #[must_use] + pub fn afen1(&mut self) -> AFEN1_W<1> { + AFEN1_W::new(self) + } + #[doc = "Bit 2 - Async falling enabled 2"] + #[inline(always)] + #[must_use] + pub fn afen2(&mut self) -> AFEN2_W<2> { + AFEN2_W::new(self) + } + #[doc = "Bit 3 - Async falling enabled 3"] + #[inline(always)] + #[must_use] + pub fn afen3(&mut self) -> AFEN3_W<3> { + AFEN3_W::new(self) + } + #[doc = "Bit 4 - Async falling enabled 4"] + #[inline(always)] + #[must_use] + pub fn afen4(&mut self) -> AFEN4_W<4> { + AFEN4_W::new(self) + } + #[doc = "Bit 5 - Async falling enabled 5"] + #[inline(always)] + #[must_use] + pub fn afen5(&mut self) -> AFEN5_W<5> { + AFEN5_W::new(self) + } + #[doc = "Bit 6 - Async falling enabled 6"] + #[inline(always)] + #[must_use] + pub fn afen6(&mut self) -> AFEN6_W<6> { + AFEN6_W::new(self) + } + #[doc = "Bit 7 - Async falling enabled 7"] + #[inline(always)] + #[must_use] + pub fn afen7(&mut self) -> AFEN7_W<7> { + AFEN7_W::new(self) + } + #[doc = "Bit 8 - Async falling enabled 8"] + #[inline(always)] + #[must_use] + pub fn afen8(&mut self) -> AFEN8_W<8> { + AFEN8_W::new(self) + } + #[doc = "Bit 9 - Async falling enabled 9"] + #[inline(always)] + #[must_use] + pub fn afen9(&mut self) -> AFEN9_W<9> { + AFEN9_W::new(self) + } + #[doc = "Bit 10 - Async falling enabled 10"] + #[inline(always)] + #[must_use] + pub fn afen10(&mut self) -> AFEN10_W<10> { + AFEN10_W::new(self) + } + #[doc = "Bit 11 - Async falling enabled 11"] + #[inline(always)] + #[must_use] + pub fn afen11(&mut self) -> AFEN11_W<11> { + AFEN11_W::new(self) + } + #[doc = "Bit 12 - Async falling enabled 12"] + #[inline(always)] + #[must_use] + pub fn afen12(&mut self) -> AFEN12_W<12> { + AFEN12_W::new(self) + } + #[doc = "Bit 13 - Async falling enabled 13"] + #[inline(always)] + #[must_use] + pub fn afen13(&mut self) -> AFEN13_W<13> { + AFEN13_W::new(self) + } + #[doc = "Bit 14 - Async falling enabled 14"] + #[inline(always)] + #[must_use] + pub fn afen14(&mut self) -> AFEN14_W<14> { + AFEN14_W::new(self) + } + #[doc = "Bit 15 - Async falling enabled 15"] + #[inline(always)] + #[must_use] + pub fn afen15(&mut self) -> AFEN15_W<15> { + AFEN15_W::new(self) + } + #[doc = "Bit 16 - Async falling enabled 16"] + #[inline(always)] + #[must_use] + pub fn afen16(&mut self) -> AFEN16_W<16> { + AFEN16_W::new(self) + } + #[doc = "Bit 17 - Async falling enabled 17"] + #[inline(always)] + #[must_use] + pub fn afen17(&mut self) -> AFEN17_W<17> { + AFEN17_W::new(self) + } + #[doc = "Bit 18 - Async falling enabled 18"] + #[inline(always)] + #[must_use] + pub fn afen18(&mut self) -> AFEN18_W<18> { + AFEN18_W::new(self) + } + #[doc = "Bit 19 - Async falling enabled 19"] + #[inline(always)] + #[must_use] + pub fn afen19(&mut self) -> AFEN19_W<19> { + AFEN19_W::new(self) + } + #[doc = "Bit 20 - Async falling enabled 20"] + #[inline(always)] + #[must_use] + pub fn afen20(&mut self) -> AFEN20_W<20> { + AFEN20_W::new(self) + } + #[doc = "Bit 21 - Async falling enabled 21"] + #[inline(always)] + #[must_use] + pub fn afen21(&mut self) -> AFEN21_W<21> { + AFEN21_W::new(self) + } + #[doc = "Bit 22 - Async falling enabled 22"] + #[inline(always)] + #[must_use] + pub fn afen22(&mut self) -> AFEN22_W<22> { + AFEN22_W::new(self) + } + #[doc = "Bit 23 - Async falling enabled 23"] + #[inline(always)] + #[must_use] + pub fn afen23(&mut self) -> AFEN23_W<23> { + AFEN23_W::new(self) + } + #[doc = "Bit 24 - Async falling enabled 24"] + #[inline(always)] + #[must_use] + pub fn afen24(&mut self) -> AFEN24_W<24> { + AFEN24_W::new(self) + } + #[doc = "Bit 25 - Async falling enabled 25"] + #[inline(always)] + #[must_use] + pub fn afen25(&mut self) -> AFEN25_W<25> { + AFEN25_W::new(self) + } + #[doc = "Bit 26 - Async falling enabled 26"] + #[inline(always)] + #[must_use] + pub fn afen26(&mut self) -> AFEN26_W<26> { + AFEN26_W::new(self) + } + #[doc = "Bit 27 - Async falling enabled 27"] + #[inline(always)] + #[must_use] + pub fn afen27(&mut self) -> AFEN27_W<27> { + AFEN27_W::new(self) + } + #[doc = "Bit 28 - Async falling enabled 28"] + #[inline(always)] + #[must_use] + pub fn afen28(&mut self) -> AFEN28_W<28> { + AFEN28_W::new(self) + } + #[doc = "Bit 29 - Async falling enabled 29"] + #[inline(always)] + #[must_use] + pub fn afen29(&mut self) -> AFEN29_W<29> { + AFEN29_W::new(self) + } + #[doc = "Bit 30 - Async falling enabled 30"] + #[inline(always)] + #[must_use] + pub fn afen30(&mut self) -> AFEN30_W<30> { + AFEN30_W::new(self) + } + #[doc = "Bit 31 - Async falling enabled 31"] + #[inline(always)] + #[must_use] + pub fn afen31(&mut self) -> AFEN31_W<31> { + AFEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen0](index.html) module"] +pub struct GPAFEN0_SPEC; +impl crate::RegisterSpec for GPAFEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpafen0::R](R) reader structure"] +impl crate::Readable for GPAFEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpafen0::W](W) writer structure"] +impl crate::Writable for GPAFEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpafen1.rs b/crates/bcm2835-lpa/src/gpio/gpafen1.rs new file mode 100644 index 0000000..a87edeb --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpafen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPAFEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAFEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AFEN32` reader - Async falling enabled 32"] +pub type AFEN32_R = crate::BitReader; +#[doc = "Field `AFEN32` writer - Async falling enabled 32"] +pub type AFEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN33` reader - Async falling enabled 33"] +pub type AFEN33_R = crate::BitReader; +#[doc = "Field `AFEN33` writer - Async falling enabled 33"] +pub type AFEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN34` reader - Async falling enabled 34"] +pub type AFEN34_R = crate::BitReader; +#[doc = "Field `AFEN34` writer - Async falling enabled 34"] +pub type AFEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN35` reader - Async falling enabled 35"] +pub type AFEN35_R = crate::BitReader; +#[doc = "Field `AFEN35` writer - Async falling enabled 35"] +pub type AFEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN36` reader - Async falling enabled 36"] +pub type AFEN36_R = crate::BitReader; +#[doc = "Field `AFEN36` writer - Async falling enabled 36"] +pub type AFEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN37` reader - Async falling enabled 37"] +pub type AFEN37_R = crate::BitReader; +#[doc = "Field `AFEN37` writer - Async falling enabled 37"] +pub type AFEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN38` reader - Async falling enabled 38"] +pub type AFEN38_R = crate::BitReader; +#[doc = "Field `AFEN38` writer - Async falling enabled 38"] +pub type AFEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN39` reader - Async falling enabled 39"] +pub type AFEN39_R = crate::BitReader; +#[doc = "Field `AFEN39` writer - Async falling enabled 39"] +pub type AFEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN40` reader - Async falling enabled 40"] +pub type AFEN40_R = crate::BitReader; +#[doc = "Field `AFEN40` writer - Async falling enabled 40"] +pub type AFEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN41` reader - Async falling enabled 41"] +pub type AFEN41_R = crate::BitReader; +#[doc = "Field `AFEN41` writer - Async falling enabled 41"] +pub type AFEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN42` reader - Async falling enabled 42"] +pub type AFEN42_R = crate::BitReader; +#[doc = "Field `AFEN42` writer - Async falling enabled 42"] +pub type AFEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN43` reader - Async falling enabled 43"] +pub type AFEN43_R = crate::BitReader; +#[doc = "Field `AFEN43` writer - Async falling enabled 43"] +pub type AFEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN44` reader - Async falling enabled 44"] +pub type AFEN44_R = crate::BitReader; +#[doc = "Field `AFEN44` writer - Async falling enabled 44"] +pub type AFEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN45` reader - Async falling enabled 45"] +pub type AFEN45_R = crate::BitReader; +#[doc = "Field `AFEN45` writer - Async falling enabled 45"] +pub type AFEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN46` reader - Async falling enabled 46"] +pub type AFEN46_R = crate::BitReader; +#[doc = "Field `AFEN46` writer - Async falling enabled 46"] +pub type AFEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN47` reader - Async falling enabled 47"] +pub type AFEN47_R = crate::BitReader; +#[doc = "Field `AFEN47` writer - Async falling enabled 47"] +pub type AFEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN48` reader - Async falling enabled 48"] +pub type AFEN48_R = crate::BitReader; +#[doc = "Field `AFEN48` writer - Async falling enabled 48"] +pub type AFEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN49` reader - Async falling enabled 49"] +pub type AFEN49_R = crate::BitReader; +#[doc = "Field `AFEN49` writer - Async falling enabled 49"] +pub type AFEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN50` reader - Async falling enabled 50"] +pub type AFEN50_R = crate::BitReader; +#[doc = "Field `AFEN50` writer - Async falling enabled 50"] +pub type AFEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN51` reader - Async falling enabled 51"] +pub type AFEN51_R = crate::BitReader; +#[doc = "Field `AFEN51` writer - Async falling enabled 51"] +pub type AFEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN52` reader - Async falling enabled 52"] +pub type AFEN52_R = crate::BitReader; +#[doc = "Field `AFEN52` writer - Async falling enabled 52"] +pub type AFEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN53` reader - Async falling enabled 53"] +pub type AFEN53_R = crate::BitReader; +#[doc = "Field `AFEN53` writer - Async falling enabled 53"] +pub type AFEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async falling enabled 32"] + #[inline(always)] + pub fn afen32(&self) -> AFEN32_R { + AFEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async falling enabled 33"] + #[inline(always)] + pub fn afen33(&self) -> AFEN33_R { + AFEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async falling enabled 34"] + #[inline(always)] + pub fn afen34(&self) -> AFEN34_R { + AFEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async falling enabled 35"] + #[inline(always)] + pub fn afen35(&self) -> AFEN35_R { + AFEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async falling enabled 36"] + #[inline(always)] + pub fn afen36(&self) -> AFEN36_R { + AFEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async falling enabled 37"] + #[inline(always)] + pub fn afen37(&self) -> AFEN37_R { + AFEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async falling enabled 38"] + #[inline(always)] + pub fn afen38(&self) -> AFEN38_R { + AFEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async falling enabled 39"] + #[inline(always)] + pub fn afen39(&self) -> AFEN39_R { + AFEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async falling enabled 40"] + #[inline(always)] + pub fn afen40(&self) -> AFEN40_R { + AFEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async falling enabled 41"] + #[inline(always)] + pub fn afen41(&self) -> AFEN41_R { + AFEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async falling enabled 42"] + #[inline(always)] + pub fn afen42(&self) -> AFEN42_R { + AFEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async falling enabled 43"] + #[inline(always)] + pub fn afen43(&self) -> AFEN43_R { + AFEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async falling enabled 44"] + #[inline(always)] + pub fn afen44(&self) -> AFEN44_R { + AFEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async falling enabled 45"] + #[inline(always)] + pub fn afen45(&self) -> AFEN45_R { + AFEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async falling enabled 46"] + #[inline(always)] + pub fn afen46(&self) -> AFEN46_R { + AFEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async falling enabled 47"] + #[inline(always)] + pub fn afen47(&self) -> AFEN47_R { + AFEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async falling enabled 48"] + #[inline(always)] + pub fn afen48(&self) -> AFEN48_R { + AFEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async falling enabled 49"] + #[inline(always)] + pub fn afen49(&self) -> AFEN49_R { + AFEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async falling enabled 50"] + #[inline(always)] + pub fn afen50(&self) -> AFEN50_R { + AFEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async falling enabled 51"] + #[inline(always)] + pub fn afen51(&self) -> AFEN51_R { + AFEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async falling enabled 52"] + #[inline(always)] + pub fn afen52(&self) -> AFEN52_R { + AFEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async falling enabled 53"] + #[inline(always)] + pub fn afen53(&self) -> AFEN53_R { + AFEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async falling enabled 32"] + #[inline(always)] + #[must_use] + pub fn afen32(&mut self) -> AFEN32_W<0> { + AFEN32_W::new(self) + } + #[doc = "Bit 1 - Async falling enabled 33"] + #[inline(always)] + #[must_use] + pub fn afen33(&mut self) -> AFEN33_W<1> { + AFEN33_W::new(self) + } + #[doc = "Bit 2 - Async falling enabled 34"] + #[inline(always)] + #[must_use] + pub fn afen34(&mut self) -> AFEN34_W<2> { + AFEN34_W::new(self) + } + #[doc = "Bit 3 - Async falling enabled 35"] + #[inline(always)] + #[must_use] + pub fn afen35(&mut self) -> AFEN35_W<3> { + AFEN35_W::new(self) + } + #[doc = "Bit 4 - Async falling enabled 36"] + #[inline(always)] + #[must_use] + pub fn afen36(&mut self) -> AFEN36_W<4> { + AFEN36_W::new(self) + } + #[doc = "Bit 5 - Async falling enabled 37"] + #[inline(always)] + #[must_use] + pub fn afen37(&mut self) -> AFEN37_W<5> { + AFEN37_W::new(self) + } + #[doc = "Bit 6 - Async falling enabled 38"] + #[inline(always)] + #[must_use] + pub fn afen38(&mut self) -> AFEN38_W<6> { + AFEN38_W::new(self) + } + #[doc = "Bit 7 - Async falling enabled 39"] + #[inline(always)] + #[must_use] + pub fn afen39(&mut self) -> AFEN39_W<7> { + AFEN39_W::new(self) + } + #[doc = "Bit 8 - Async falling enabled 40"] + #[inline(always)] + #[must_use] + pub fn afen40(&mut self) -> AFEN40_W<8> { + AFEN40_W::new(self) + } + #[doc = "Bit 9 - Async falling enabled 41"] + #[inline(always)] + #[must_use] + pub fn afen41(&mut self) -> AFEN41_W<9> { + AFEN41_W::new(self) + } + #[doc = "Bit 10 - Async falling enabled 42"] + #[inline(always)] + #[must_use] + pub fn afen42(&mut self) -> AFEN42_W<10> { + AFEN42_W::new(self) + } + #[doc = "Bit 11 - Async falling enabled 43"] + #[inline(always)] + #[must_use] + pub fn afen43(&mut self) -> AFEN43_W<11> { + AFEN43_W::new(self) + } + #[doc = "Bit 12 - Async falling enabled 44"] + #[inline(always)] + #[must_use] + pub fn afen44(&mut self) -> AFEN44_W<12> { + AFEN44_W::new(self) + } + #[doc = "Bit 13 - Async falling enabled 45"] + #[inline(always)] + #[must_use] + pub fn afen45(&mut self) -> AFEN45_W<13> { + AFEN45_W::new(self) + } + #[doc = "Bit 14 - Async falling enabled 46"] + #[inline(always)] + #[must_use] + pub fn afen46(&mut self) -> AFEN46_W<14> { + AFEN46_W::new(self) + } + #[doc = "Bit 15 - Async falling enabled 47"] + #[inline(always)] + #[must_use] + pub fn afen47(&mut self) -> AFEN47_W<15> { + AFEN47_W::new(self) + } + #[doc = "Bit 16 - Async falling enabled 48"] + #[inline(always)] + #[must_use] + pub fn afen48(&mut self) -> AFEN48_W<16> { + AFEN48_W::new(self) + } + #[doc = "Bit 17 - Async falling enabled 49"] + #[inline(always)] + #[must_use] + pub fn afen49(&mut self) -> AFEN49_W<17> { + AFEN49_W::new(self) + } + #[doc = "Bit 18 - Async falling enabled 50"] + #[inline(always)] + #[must_use] + pub fn afen50(&mut self) -> AFEN50_W<18> { + AFEN50_W::new(self) + } + #[doc = "Bit 19 - Async falling enabled 51"] + #[inline(always)] + #[must_use] + pub fn afen51(&mut self) -> AFEN51_W<19> { + AFEN51_W::new(self) + } + #[doc = "Bit 20 - Async falling enabled 52"] + #[inline(always)] + #[must_use] + pub fn afen52(&mut self) -> AFEN52_W<20> { + AFEN52_W::new(self) + } + #[doc = "Bit 21 - Async falling enabled 53"] + #[inline(always)] + #[must_use] + pub fn afen53(&mut self) -> AFEN53_W<21> { + AFEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen1](index.html) module"] +pub struct GPAFEN1_SPEC; +impl crate::RegisterSpec for GPAFEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpafen1::R](R) reader structure"] +impl crate::Readable for GPAFEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpafen1::W](W) writer structure"] +impl crate::Writable for GPAFEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gparen0.rs b/crates/bcm2835-lpa/src/gpio/gparen0.rs new file mode 100644 index 0000000..f4ef746 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gparen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPAREN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAREN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AREN0` reader - Async rising enabled 0"] +pub type AREN0_R = crate::BitReader; +#[doc = "Field `AREN0` writer - Async rising enabled 0"] +pub type AREN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN1` reader - Async rising enabled 1"] +pub type AREN1_R = crate::BitReader; +#[doc = "Field `AREN1` writer - Async rising enabled 1"] +pub type AREN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN2` reader - Async rising enabled 2"] +pub type AREN2_R = crate::BitReader; +#[doc = "Field `AREN2` writer - Async rising enabled 2"] +pub type AREN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN3` reader - Async rising enabled 3"] +pub type AREN3_R = crate::BitReader; +#[doc = "Field `AREN3` writer - Async rising enabled 3"] +pub type AREN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN4` reader - Async rising enabled 4"] +pub type AREN4_R = crate::BitReader; +#[doc = "Field `AREN4` writer - Async rising enabled 4"] +pub type AREN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN5` reader - Async rising enabled 5"] +pub type AREN5_R = crate::BitReader; +#[doc = "Field `AREN5` writer - Async rising enabled 5"] +pub type AREN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN6` reader - Async rising enabled 6"] +pub type AREN6_R = crate::BitReader; +#[doc = "Field `AREN6` writer - Async rising enabled 6"] +pub type AREN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN7` reader - Async rising enabled 7"] +pub type AREN7_R = crate::BitReader; +#[doc = "Field `AREN7` writer - Async rising enabled 7"] +pub type AREN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN8` reader - Async rising enabled 8"] +pub type AREN8_R = crate::BitReader; +#[doc = "Field `AREN8` writer - Async rising enabled 8"] +pub type AREN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN9` reader - Async rising enabled 9"] +pub type AREN9_R = crate::BitReader; +#[doc = "Field `AREN9` writer - Async rising enabled 9"] +pub type AREN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN10` reader - Async rising enabled 10"] +pub type AREN10_R = crate::BitReader; +#[doc = "Field `AREN10` writer - Async rising enabled 10"] +pub type AREN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN11` reader - Async rising enabled 11"] +pub type AREN11_R = crate::BitReader; +#[doc = "Field `AREN11` writer - Async rising enabled 11"] +pub type AREN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN12` reader - Async rising enabled 12"] +pub type AREN12_R = crate::BitReader; +#[doc = "Field `AREN12` writer - Async rising enabled 12"] +pub type AREN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN13` reader - Async rising enabled 13"] +pub type AREN13_R = crate::BitReader; +#[doc = "Field `AREN13` writer - Async rising enabled 13"] +pub type AREN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN14` reader - Async rising enabled 14"] +pub type AREN14_R = crate::BitReader; +#[doc = "Field `AREN14` writer - Async rising enabled 14"] +pub type AREN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN15` reader - Async rising enabled 15"] +pub type AREN15_R = crate::BitReader; +#[doc = "Field `AREN15` writer - Async rising enabled 15"] +pub type AREN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN16` reader - Async rising enabled 16"] +pub type AREN16_R = crate::BitReader; +#[doc = "Field `AREN16` writer - Async rising enabled 16"] +pub type AREN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN17` reader - Async rising enabled 17"] +pub type AREN17_R = crate::BitReader; +#[doc = "Field `AREN17` writer - Async rising enabled 17"] +pub type AREN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN18` reader - Async rising enabled 18"] +pub type AREN18_R = crate::BitReader; +#[doc = "Field `AREN18` writer - Async rising enabled 18"] +pub type AREN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN19` reader - Async rising enabled 19"] +pub type AREN19_R = crate::BitReader; +#[doc = "Field `AREN19` writer - Async rising enabled 19"] +pub type AREN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN20` reader - Async rising enabled 20"] +pub type AREN20_R = crate::BitReader; +#[doc = "Field `AREN20` writer - Async rising enabled 20"] +pub type AREN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN21` reader - Async rising enabled 21"] +pub type AREN21_R = crate::BitReader; +#[doc = "Field `AREN21` writer - Async rising enabled 21"] +pub type AREN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN22` reader - Async rising enabled 22"] +pub type AREN22_R = crate::BitReader; +#[doc = "Field `AREN22` writer - Async rising enabled 22"] +pub type AREN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN23` reader - Async rising enabled 23"] +pub type AREN23_R = crate::BitReader; +#[doc = "Field `AREN23` writer - Async rising enabled 23"] +pub type AREN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN24` reader - Async rising enabled 24"] +pub type AREN24_R = crate::BitReader; +#[doc = "Field `AREN24` writer - Async rising enabled 24"] +pub type AREN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN25` reader - Async rising enabled 25"] +pub type AREN25_R = crate::BitReader; +#[doc = "Field `AREN25` writer - Async rising enabled 25"] +pub type AREN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN26` reader - Async rising enabled 26"] +pub type AREN26_R = crate::BitReader; +#[doc = "Field `AREN26` writer - Async rising enabled 26"] +pub type AREN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN27` reader - Async rising enabled 27"] +pub type AREN27_R = crate::BitReader; +#[doc = "Field `AREN27` writer - Async rising enabled 27"] +pub type AREN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN28` reader - Async rising enabled 28"] +pub type AREN28_R = crate::BitReader; +#[doc = "Field `AREN28` writer - Async rising enabled 28"] +pub type AREN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN29` reader - Async rising enabled 29"] +pub type AREN29_R = crate::BitReader; +#[doc = "Field `AREN29` writer - Async rising enabled 29"] +pub type AREN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN30` reader - Async rising enabled 30"] +pub type AREN30_R = crate::BitReader; +#[doc = "Field `AREN30` writer - Async rising enabled 30"] +pub type AREN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN31` reader - Async rising enabled 31"] +pub type AREN31_R = crate::BitReader; +#[doc = "Field `AREN31` writer - Async rising enabled 31"] +pub type AREN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async rising enabled 0"] + #[inline(always)] + pub fn aren0(&self) -> AREN0_R { + AREN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async rising enabled 1"] + #[inline(always)] + pub fn aren1(&self) -> AREN1_R { + AREN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async rising enabled 2"] + #[inline(always)] + pub fn aren2(&self) -> AREN2_R { + AREN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async rising enabled 3"] + #[inline(always)] + pub fn aren3(&self) -> AREN3_R { + AREN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async rising enabled 4"] + #[inline(always)] + pub fn aren4(&self) -> AREN4_R { + AREN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async rising enabled 5"] + #[inline(always)] + pub fn aren5(&self) -> AREN5_R { + AREN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async rising enabled 6"] + #[inline(always)] + pub fn aren6(&self) -> AREN6_R { + AREN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async rising enabled 7"] + #[inline(always)] + pub fn aren7(&self) -> AREN7_R { + AREN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async rising enabled 8"] + #[inline(always)] + pub fn aren8(&self) -> AREN8_R { + AREN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async rising enabled 9"] + #[inline(always)] + pub fn aren9(&self) -> AREN9_R { + AREN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async rising enabled 10"] + #[inline(always)] + pub fn aren10(&self) -> AREN10_R { + AREN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async rising enabled 11"] + #[inline(always)] + pub fn aren11(&self) -> AREN11_R { + AREN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async rising enabled 12"] + #[inline(always)] + pub fn aren12(&self) -> AREN12_R { + AREN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async rising enabled 13"] + #[inline(always)] + pub fn aren13(&self) -> AREN13_R { + AREN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async rising enabled 14"] + #[inline(always)] + pub fn aren14(&self) -> AREN14_R { + AREN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async rising enabled 15"] + #[inline(always)] + pub fn aren15(&self) -> AREN15_R { + AREN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async rising enabled 16"] + #[inline(always)] + pub fn aren16(&self) -> AREN16_R { + AREN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async rising enabled 17"] + #[inline(always)] + pub fn aren17(&self) -> AREN17_R { + AREN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async rising enabled 18"] + #[inline(always)] + pub fn aren18(&self) -> AREN18_R { + AREN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async rising enabled 19"] + #[inline(always)] + pub fn aren19(&self) -> AREN19_R { + AREN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async rising enabled 20"] + #[inline(always)] + pub fn aren20(&self) -> AREN20_R { + AREN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async rising enabled 21"] + #[inline(always)] + pub fn aren21(&self) -> AREN21_R { + AREN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async rising enabled 22"] + #[inline(always)] + pub fn aren22(&self) -> AREN22_R { + AREN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async rising enabled 23"] + #[inline(always)] + pub fn aren23(&self) -> AREN23_R { + AREN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async rising enabled 24"] + #[inline(always)] + pub fn aren24(&self) -> AREN24_R { + AREN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async rising enabled 25"] + #[inline(always)] + pub fn aren25(&self) -> AREN25_R { + AREN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Async rising enabled 26"] + #[inline(always)] + pub fn aren26(&self) -> AREN26_R { + AREN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Async rising enabled 27"] + #[inline(always)] + pub fn aren27(&self) -> AREN27_R { + AREN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Async rising enabled 28"] + #[inline(always)] + pub fn aren28(&self) -> AREN28_R { + AREN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Async rising enabled 29"] + #[inline(always)] + pub fn aren29(&self) -> AREN29_R { + AREN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Async rising enabled 30"] + #[inline(always)] + pub fn aren30(&self) -> AREN30_R { + AREN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Async rising enabled 31"] + #[inline(always)] + pub fn aren31(&self) -> AREN31_R { + AREN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async rising enabled 0"] + #[inline(always)] + #[must_use] + pub fn aren0(&mut self) -> AREN0_W<0> { + AREN0_W::new(self) + } + #[doc = "Bit 1 - Async rising enabled 1"] + #[inline(always)] + #[must_use] + pub fn aren1(&mut self) -> AREN1_W<1> { + AREN1_W::new(self) + } + #[doc = "Bit 2 - Async rising enabled 2"] + #[inline(always)] + #[must_use] + pub fn aren2(&mut self) -> AREN2_W<2> { + AREN2_W::new(self) + } + #[doc = "Bit 3 - Async rising enabled 3"] + #[inline(always)] + #[must_use] + pub fn aren3(&mut self) -> AREN3_W<3> { + AREN3_W::new(self) + } + #[doc = "Bit 4 - Async rising enabled 4"] + #[inline(always)] + #[must_use] + pub fn aren4(&mut self) -> AREN4_W<4> { + AREN4_W::new(self) + } + #[doc = "Bit 5 - Async rising enabled 5"] + #[inline(always)] + #[must_use] + pub fn aren5(&mut self) -> AREN5_W<5> { + AREN5_W::new(self) + } + #[doc = "Bit 6 - Async rising enabled 6"] + #[inline(always)] + #[must_use] + pub fn aren6(&mut self) -> AREN6_W<6> { + AREN6_W::new(self) + } + #[doc = "Bit 7 - Async rising enabled 7"] + #[inline(always)] + #[must_use] + pub fn aren7(&mut self) -> AREN7_W<7> { + AREN7_W::new(self) + } + #[doc = "Bit 8 - Async rising enabled 8"] + #[inline(always)] + #[must_use] + pub fn aren8(&mut self) -> AREN8_W<8> { + AREN8_W::new(self) + } + #[doc = "Bit 9 - Async rising enabled 9"] + #[inline(always)] + #[must_use] + pub fn aren9(&mut self) -> AREN9_W<9> { + AREN9_W::new(self) + } + #[doc = "Bit 10 - Async rising enabled 10"] + #[inline(always)] + #[must_use] + pub fn aren10(&mut self) -> AREN10_W<10> { + AREN10_W::new(self) + } + #[doc = "Bit 11 - Async rising enabled 11"] + #[inline(always)] + #[must_use] + pub fn aren11(&mut self) -> AREN11_W<11> { + AREN11_W::new(self) + } + #[doc = "Bit 12 - Async rising enabled 12"] + #[inline(always)] + #[must_use] + pub fn aren12(&mut self) -> AREN12_W<12> { + AREN12_W::new(self) + } + #[doc = "Bit 13 - Async rising enabled 13"] + #[inline(always)] + #[must_use] + pub fn aren13(&mut self) -> AREN13_W<13> { + AREN13_W::new(self) + } + #[doc = "Bit 14 - Async rising enabled 14"] + #[inline(always)] + #[must_use] + pub fn aren14(&mut self) -> AREN14_W<14> { + AREN14_W::new(self) + } + #[doc = "Bit 15 - Async rising enabled 15"] + #[inline(always)] + #[must_use] + pub fn aren15(&mut self) -> AREN15_W<15> { + AREN15_W::new(self) + } + #[doc = "Bit 16 - Async rising enabled 16"] + #[inline(always)] + #[must_use] + pub fn aren16(&mut self) -> AREN16_W<16> { + AREN16_W::new(self) + } + #[doc = "Bit 17 - Async rising enabled 17"] + #[inline(always)] + #[must_use] + pub fn aren17(&mut self) -> AREN17_W<17> { + AREN17_W::new(self) + } + #[doc = "Bit 18 - Async rising enabled 18"] + #[inline(always)] + #[must_use] + pub fn aren18(&mut self) -> AREN18_W<18> { + AREN18_W::new(self) + } + #[doc = "Bit 19 - Async rising enabled 19"] + #[inline(always)] + #[must_use] + pub fn aren19(&mut self) -> AREN19_W<19> { + AREN19_W::new(self) + } + #[doc = "Bit 20 - Async rising enabled 20"] + #[inline(always)] + #[must_use] + pub fn aren20(&mut self) -> AREN20_W<20> { + AREN20_W::new(self) + } + #[doc = "Bit 21 - Async rising enabled 21"] + #[inline(always)] + #[must_use] + pub fn aren21(&mut self) -> AREN21_W<21> { + AREN21_W::new(self) + } + #[doc = "Bit 22 - Async rising enabled 22"] + #[inline(always)] + #[must_use] + pub fn aren22(&mut self) -> AREN22_W<22> { + AREN22_W::new(self) + } + #[doc = "Bit 23 - Async rising enabled 23"] + #[inline(always)] + #[must_use] + pub fn aren23(&mut self) -> AREN23_W<23> { + AREN23_W::new(self) + } + #[doc = "Bit 24 - Async rising enabled 24"] + #[inline(always)] + #[must_use] + pub fn aren24(&mut self) -> AREN24_W<24> { + AREN24_W::new(self) + } + #[doc = "Bit 25 - Async rising enabled 25"] + #[inline(always)] + #[must_use] + pub fn aren25(&mut self) -> AREN25_W<25> { + AREN25_W::new(self) + } + #[doc = "Bit 26 - Async rising enabled 26"] + #[inline(always)] + #[must_use] + pub fn aren26(&mut self) -> AREN26_W<26> { + AREN26_W::new(self) + } + #[doc = "Bit 27 - Async rising enabled 27"] + #[inline(always)] + #[must_use] + pub fn aren27(&mut self) -> AREN27_W<27> { + AREN27_W::new(self) + } + #[doc = "Bit 28 - Async rising enabled 28"] + #[inline(always)] + #[must_use] + pub fn aren28(&mut self) -> AREN28_W<28> { + AREN28_W::new(self) + } + #[doc = "Bit 29 - Async rising enabled 29"] + #[inline(always)] + #[must_use] + pub fn aren29(&mut self) -> AREN29_W<29> { + AREN29_W::new(self) + } + #[doc = "Bit 30 - Async rising enabled 30"] + #[inline(always)] + #[must_use] + pub fn aren30(&mut self) -> AREN30_W<30> { + AREN30_W::new(self) + } + #[doc = "Bit 31 - Async rising enabled 31"] + #[inline(always)] + #[must_use] + pub fn aren31(&mut self) -> AREN31_W<31> { + AREN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen0](index.html) module"] +pub struct GPAREN0_SPEC; +impl crate::RegisterSpec for GPAREN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gparen0::R](R) reader structure"] +impl crate::Readable for GPAREN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gparen0::W](W) writer structure"] +impl crate::Writable for GPAREN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gparen1.rs b/crates/bcm2835-lpa/src/gpio/gparen1.rs new file mode 100644 index 0000000..158f1ef --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gparen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPAREN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAREN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AREN32` reader - Async rising enabled 32"] +pub type AREN32_R = crate::BitReader; +#[doc = "Field `AREN32` writer - Async rising enabled 32"] +pub type AREN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN33` reader - Async rising enabled 33"] +pub type AREN33_R = crate::BitReader; +#[doc = "Field `AREN33` writer - Async rising enabled 33"] +pub type AREN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN34` reader - Async rising enabled 34"] +pub type AREN34_R = crate::BitReader; +#[doc = "Field `AREN34` writer - Async rising enabled 34"] +pub type AREN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN35` reader - Async rising enabled 35"] +pub type AREN35_R = crate::BitReader; +#[doc = "Field `AREN35` writer - Async rising enabled 35"] +pub type AREN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN36` reader - Async rising enabled 36"] +pub type AREN36_R = crate::BitReader; +#[doc = "Field `AREN36` writer - Async rising enabled 36"] +pub type AREN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN37` reader - Async rising enabled 37"] +pub type AREN37_R = crate::BitReader; +#[doc = "Field `AREN37` writer - Async rising enabled 37"] +pub type AREN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN38` reader - Async rising enabled 38"] +pub type AREN38_R = crate::BitReader; +#[doc = "Field `AREN38` writer - Async rising enabled 38"] +pub type AREN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN39` reader - Async rising enabled 39"] +pub type AREN39_R = crate::BitReader; +#[doc = "Field `AREN39` writer - Async rising enabled 39"] +pub type AREN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN40` reader - Async rising enabled 40"] +pub type AREN40_R = crate::BitReader; +#[doc = "Field `AREN40` writer - Async rising enabled 40"] +pub type AREN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN41` reader - Async rising enabled 41"] +pub type AREN41_R = crate::BitReader; +#[doc = "Field `AREN41` writer - Async rising enabled 41"] +pub type AREN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN42` reader - Async rising enabled 42"] +pub type AREN42_R = crate::BitReader; +#[doc = "Field `AREN42` writer - Async rising enabled 42"] +pub type AREN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN43` reader - Async rising enabled 43"] +pub type AREN43_R = crate::BitReader; +#[doc = "Field `AREN43` writer - Async rising enabled 43"] +pub type AREN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN44` reader - Async rising enabled 44"] +pub type AREN44_R = crate::BitReader; +#[doc = "Field `AREN44` writer - Async rising enabled 44"] +pub type AREN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN45` reader - Async rising enabled 45"] +pub type AREN45_R = crate::BitReader; +#[doc = "Field `AREN45` writer - Async rising enabled 45"] +pub type AREN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN46` reader - Async rising enabled 46"] +pub type AREN46_R = crate::BitReader; +#[doc = "Field `AREN46` writer - Async rising enabled 46"] +pub type AREN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN47` reader - Async rising enabled 47"] +pub type AREN47_R = crate::BitReader; +#[doc = "Field `AREN47` writer - Async rising enabled 47"] +pub type AREN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN48` reader - Async rising enabled 48"] +pub type AREN48_R = crate::BitReader; +#[doc = "Field `AREN48` writer - Async rising enabled 48"] +pub type AREN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN49` reader - Async rising enabled 49"] +pub type AREN49_R = crate::BitReader; +#[doc = "Field `AREN49` writer - Async rising enabled 49"] +pub type AREN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN50` reader - Async rising enabled 50"] +pub type AREN50_R = crate::BitReader; +#[doc = "Field `AREN50` writer - Async rising enabled 50"] +pub type AREN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN51` reader - Async rising enabled 51"] +pub type AREN51_R = crate::BitReader; +#[doc = "Field `AREN51` writer - Async rising enabled 51"] +pub type AREN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN52` reader - Async rising enabled 52"] +pub type AREN52_R = crate::BitReader; +#[doc = "Field `AREN52` writer - Async rising enabled 52"] +pub type AREN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN53` reader - Async rising enabled 53"] +pub type AREN53_R = crate::BitReader; +#[doc = "Field `AREN53` writer - Async rising enabled 53"] +pub type AREN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async rising enabled 32"] + #[inline(always)] + pub fn aren32(&self) -> AREN32_R { + AREN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async rising enabled 33"] + #[inline(always)] + pub fn aren33(&self) -> AREN33_R { + AREN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async rising enabled 34"] + #[inline(always)] + pub fn aren34(&self) -> AREN34_R { + AREN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async rising enabled 35"] + #[inline(always)] + pub fn aren35(&self) -> AREN35_R { + AREN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async rising enabled 36"] + #[inline(always)] + pub fn aren36(&self) -> AREN36_R { + AREN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async rising enabled 37"] + #[inline(always)] + pub fn aren37(&self) -> AREN37_R { + AREN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async rising enabled 38"] + #[inline(always)] + pub fn aren38(&self) -> AREN38_R { + AREN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async rising enabled 39"] + #[inline(always)] + pub fn aren39(&self) -> AREN39_R { + AREN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async rising enabled 40"] + #[inline(always)] + pub fn aren40(&self) -> AREN40_R { + AREN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async rising enabled 41"] + #[inline(always)] + pub fn aren41(&self) -> AREN41_R { + AREN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async rising enabled 42"] + #[inline(always)] + pub fn aren42(&self) -> AREN42_R { + AREN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async rising enabled 43"] + #[inline(always)] + pub fn aren43(&self) -> AREN43_R { + AREN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async rising enabled 44"] + #[inline(always)] + pub fn aren44(&self) -> AREN44_R { + AREN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async rising enabled 45"] + #[inline(always)] + pub fn aren45(&self) -> AREN45_R { + AREN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async rising enabled 46"] + #[inline(always)] + pub fn aren46(&self) -> AREN46_R { + AREN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async rising enabled 47"] + #[inline(always)] + pub fn aren47(&self) -> AREN47_R { + AREN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async rising enabled 48"] + #[inline(always)] + pub fn aren48(&self) -> AREN48_R { + AREN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async rising enabled 49"] + #[inline(always)] + pub fn aren49(&self) -> AREN49_R { + AREN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async rising enabled 50"] + #[inline(always)] + pub fn aren50(&self) -> AREN50_R { + AREN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async rising enabled 51"] + #[inline(always)] + pub fn aren51(&self) -> AREN51_R { + AREN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async rising enabled 52"] + #[inline(always)] + pub fn aren52(&self) -> AREN52_R { + AREN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async rising enabled 53"] + #[inline(always)] + pub fn aren53(&self) -> AREN53_R { + AREN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async rising enabled 32"] + #[inline(always)] + #[must_use] + pub fn aren32(&mut self) -> AREN32_W<0> { + AREN32_W::new(self) + } + #[doc = "Bit 1 - Async rising enabled 33"] + #[inline(always)] + #[must_use] + pub fn aren33(&mut self) -> AREN33_W<1> { + AREN33_W::new(self) + } + #[doc = "Bit 2 - Async rising enabled 34"] + #[inline(always)] + #[must_use] + pub fn aren34(&mut self) -> AREN34_W<2> { + AREN34_W::new(self) + } + #[doc = "Bit 3 - Async rising enabled 35"] + #[inline(always)] + #[must_use] + pub fn aren35(&mut self) -> AREN35_W<3> { + AREN35_W::new(self) + } + #[doc = "Bit 4 - Async rising enabled 36"] + #[inline(always)] + #[must_use] + pub fn aren36(&mut self) -> AREN36_W<4> { + AREN36_W::new(self) + } + #[doc = "Bit 5 - Async rising enabled 37"] + #[inline(always)] + #[must_use] + pub fn aren37(&mut self) -> AREN37_W<5> { + AREN37_W::new(self) + } + #[doc = "Bit 6 - Async rising enabled 38"] + #[inline(always)] + #[must_use] + pub fn aren38(&mut self) -> AREN38_W<6> { + AREN38_W::new(self) + } + #[doc = "Bit 7 - Async rising enabled 39"] + #[inline(always)] + #[must_use] + pub fn aren39(&mut self) -> AREN39_W<7> { + AREN39_W::new(self) + } + #[doc = "Bit 8 - Async rising enabled 40"] + #[inline(always)] + #[must_use] + pub fn aren40(&mut self) -> AREN40_W<8> { + AREN40_W::new(self) + } + #[doc = "Bit 9 - Async rising enabled 41"] + #[inline(always)] + #[must_use] + pub fn aren41(&mut self) -> AREN41_W<9> { + AREN41_W::new(self) + } + #[doc = "Bit 10 - Async rising enabled 42"] + #[inline(always)] + #[must_use] + pub fn aren42(&mut self) -> AREN42_W<10> { + AREN42_W::new(self) + } + #[doc = "Bit 11 - Async rising enabled 43"] + #[inline(always)] + #[must_use] + pub fn aren43(&mut self) -> AREN43_W<11> { + AREN43_W::new(self) + } + #[doc = "Bit 12 - Async rising enabled 44"] + #[inline(always)] + #[must_use] + pub fn aren44(&mut self) -> AREN44_W<12> { + AREN44_W::new(self) + } + #[doc = "Bit 13 - Async rising enabled 45"] + #[inline(always)] + #[must_use] + pub fn aren45(&mut self) -> AREN45_W<13> { + AREN45_W::new(self) + } + #[doc = "Bit 14 - Async rising enabled 46"] + #[inline(always)] + #[must_use] + pub fn aren46(&mut self) -> AREN46_W<14> { + AREN46_W::new(self) + } + #[doc = "Bit 15 - Async rising enabled 47"] + #[inline(always)] + #[must_use] + pub fn aren47(&mut self) -> AREN47_W<15> { + AREN47_W::new(self) + } + #[doc = "Bit 16 - Async rising enabled 48"] + #[inline(always)] + #[must_use] + pub fn aren48(&mut self) -> AREN48_W<16> { + AREN48_W::new(self) + } + #[doc = "Bit 17 - Async rising enabled 49"] + #[inline(always)] + #[must_use] + pub fn aren49(&mut self) -> AREN49_W<17> { + AREN49_W::new(self) + } + #[doc = "Bit 18 - Async rising enabled 50"] + #[inline(always)] + #[must_use] + pub fn aren50(&mut self) -> AREN50_W<18> { + AREN50_W::new(self) + } + #[doc = "Bit 19 - Async rising enabled 51"] + #[inline(always)] + #[must_use] + pub fn aren51(&mut self) -> AREN51_W<19> { + AREN51_W::new(self) + } + #[doc = "Bit 20 - Async rising enabled 52"] + #[inline(always)] + #[must_use] + pub fn aren52(&mut self) -> AREN52_W<20> { + AREN52_W::new(self) + } + #[doc = "Bit 21 - Async rising enabled 53"] + #[inline(always)] + #[must_use] + pub fn aren53(&mut self) -> AREN53_W<21> { + AREN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen1](index.html) module"] +pub struct GPAREN1_SPEC; +impl crate::RegisterSpec for GPAREN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gparen1::R](R) reader structure"] +impl crate::Readable for GPAREN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gparen1::W](W) writer structure"] +impl crate::Writable for GPAREN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpclr0.rs b/crates/bcm2835-lpa/src/gpio/gpclr0.rs new file mode 100644 index 0000000..1a6b2cd --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpclr0.rs @@ -0,0 +1,296 @@ +#[doc = "Register `GPCLR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLR0` writer - Clear 0"] +pub type CLR0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR1` writer - Clear 1"] +pub type CLR1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR2` writer - Clear 2"] +pub type CLR2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR3` writer - Clear 3"] +pub type CLR3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR4` writer - Clear 4"] +pub type CLR4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR5` writer - Clear 5"] +pub type CLR5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR6` writer - Clear 6"] +pub type CLR6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR7` writer - Clear 7"] +pub type CLR7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR8` writer - Clear 8"] +pub type CLR8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR9` writer - Clear 9"] +pub type CLR9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR10` writer - Clear 10"] +pub type CLR10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR11` writer - Clear 11"] +pub type CLR11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR12` writer - Clear 12"] +pub type CLR12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR13` writer - Clear 13"] +pub type CLR13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR14` writer - Clear 14"] +pub type CLR14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR15` writer - Clear 15"] +pub type CLR15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR16` writer - Clear 16"] +pub type CLR16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR17` writer - Clear 17"] +pub type CLR17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR18` writer - Clear 18"] +pub type CLR18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR19` writer - Clear 19"] +pub type CLR19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR20` writer - Clear 20"] +pub type CLR20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR21` writer - Clear 21"] +pub type CLR21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR22` writer - Clear 22"] +pub type CLR22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR23` writer - Clear 23"] +pub type CLR23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR24` writer - Clear 24"] +pub type CLR24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR25` writer - Clear 25"] +pub type CLR25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR26` writer - Clear 26"] +pub type CLR26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR27` writer - Clear 27"] +pub type CLR27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR28` writer - Clear 28"] +pub type CLR28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR29` writer - Clear 29"] +pub type CLR29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR30` writer - Clear 30"] +pub type CLR30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR31` writer - Clear 31"] +pub type CLR31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Clear 0"] + #[inline(always)] + #[must_use] + pub fn clr0(&mut self) -> CLR0_W<0> { + CLR0_W::new(self) + } + #[doc = "Bit 1 - Clear 1"] + #[inline(always)] + #[must_use] + pub fn clr1(&mut self) -> CLR1_W<1> { + CLR1_W::new(self) + } + #[doc = "Bit 2 - Clear 2"] + #[inline(always)] + #[must_use] + pub fn clr2(&mut self) -> CLR2_W<2> { + CLR2_W::new(self) + } + #[doc = "Bit 3 - Clear 3"] + #[inline(always)] + #[must_use] + pub fn clr3(&mut self) -> CLR3_W<3> { + CLR3_W::new(self) + } + #[doc = "Bit 4 - Clear 4"] + #[inline(always)] + #[must_use] + pub fn clr4(&mut self) -> CLR4_W<4> { + CLR4_W::new(self) + } + #[doc = "Bit 5 - Clear 5"] + #[inline(always)] + #[must_use] + pub fn clr5(&mut self) -> CLR5_W<5> { + CLR5_W::new(self) + } + #[doc = "Bit 6 - Clear 6"] + #[inline(always)] + #[must_use] + pub fn clr6(&mut self) -> CLR6_W<6> { + CLR6_W::new(self) + } + #[doc = "Bit 7 - Clear 7"] + #[inline(always)] + #[must_use] + pub fn clr7(&mut self) -> CLR7_W<7> { + CLR7_W::new(self) + } + #[doc = "Bit 8 - Clear 8"] + #[inline(always)] + #[must_use] + pub fn clr8(&mut self) -> CLR8_W<8> { + CLR8_W::new(self) + } + #[doc = "Bit 9 - Clear 9"] + #[inline(always)] + #[must_use] + pub fn clr9(&mut self) -> CLR9_W<9> { + CLR9_W::new(self) + } + #[doc = "Bit 10 - Clear 10"] + #[inline(always)] + #[must_use] + pub fn clr10(&mut self) -> CLR10_W<10> { + CLR10_W::new(self) + } + #[doc = "Bit 11 - Clear 11"] + #[inline(always)] + #[must_use] + pub fn clr11(&mut self) -> CLR11_W<11> { + CLR11_W::new(self) + } + #[doc = "Bit 12 - Clear 12"] + #[inline(always)] + #[must_use] + pub fn clr12(&mut self) -> CLR12_W<12> { + CLR12_W::new(self) + } + #[doc = "Bit 13 - Clear 13"] + #[inline(always)] + #[must_use] + pub fn clr13(&mut self) -> CLR13_W<13> { + CLR13_W::new(self) + } + #[doc = "Bit 14 - Clear 14"] + #[inline(always)] + #[must_use] + pub fn clr14(&mut self) -> CLR14_W<14> { + CLR14_W::new(self) + } + #[doc = "Bit 15 - Clear 15"] + #[inline(always)] + #[must_use] + pub fn clr15(&mut self) -> CLR15_W<15> { + CLR15_W::new(self) + } + #[doc = "Bit 16 - Clear 16"] + #[inline(always)] + #[must_use] + pub fn clr16(&mut self) -> CLR16_W<16> { + CLR16_W::new(self) + } + #[doc = "Bit 17 - Clear 17"] + #[inline(always)] + #[must_use] + pub fn clr17(&mut self) -> CLR17_W<17> { + CLR17_W::new(self) + } + #[doc = "Bit 18 - Clear 18"] + #[inline(always)] + #[must_use] + pub fn clr18(&mut self) -> CLR18_W<18> { + CLR18_W::new(self) + } + #[doc = "Bit 19 - Clear 19"] + #[inline(always)] + #[must_use] + pub fn clr19(&mut self) -> CLR19_W<19> { + CLR19_W::new(self) + } + #[doc = "Bit 20 - Clear 20"] + #[inline(always)] + #[must_use] + pub fn clr20(&mut self) -> CLR20_W<20> { + CLR20_W::new(self) + } + #[doc = "Bit 21 - Clear 21"] + #[inline(always)] + #[must_use] + pub fn clr21(&mut self) -> CLR21_W<21> { + CLR21_W::new(self) + } + #[doc = "Bit 22 - Clear 22"] + #[inline(always)] + #[must_use] + pub fn clr22(&mut self) -> CLR22_W<22> { + CLR22_W::new(self) + } + #[doc = "Bit 23 - Clear 23"] + #[inline(always)] + #[must_use] + pub fn clr23(&mut self) -> CLR23_W<23> { + CLR23_W::new(self) + } + #[doc = "Bit 24 - Clear 24"] + #[inline(always)] + #[must_use] + pub fn clr24(&mut self) -> CLR24_W<24> { + CLR24_W::new(self) + } + #[doc = "Bit 25 - Clear 25"] + #[inline(always)] + #[must_use] + pub fn clr25(&mut self) -> CLR25_W<25> { + CLR25_W::new(self) + } + #[doc = "Bit 26 - Clear 26"] + #[inline(always)] + #[must_use] + pub fn clr26(&mut self) -> CLR26_W<26> { + CLR26_W::new(self) + } + #[doc = "Bit 27 - Clear 27"] + #[inline(always)] + #[must_use] + pub fn clr27(&mut self) -> CLR27_W<27> { + CLR27_W::new(self) + } + #[doc = "Bit 28 - Clear 28"] + #[inline(always)] + #[must_use] + pub fn clr28(&mut self) -> CLR28_W<28> { + CLR28_W::new(self) + } + #[doc = "Bit 29 - Clear 29"] + #[inline(always)] + #[must_use] + pub fn clr29(&mut self) -> CLR29_W<29> { + CLR29_W::new(self) + } + #[doc = "Bit 30 - Clear 30"] + #[inline(always)] + #[must_use] + pub fn clr30(&mut self) -> CLR30_W<30> { + CLR30_W::new(self) + } + #[doc = "Bit 31 - Clear 31"] + #[inline(always)] + #[must_use] + pub fn clr31(&mut self) -> CLR31_W<31> { + CLR31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Clear 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr0](index.html) module"] +pub struct GPCLR0_SPEC; +impl crate::RegisterSpec for GPCLR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpclr0::W](W) writer structure"] +impl crate::Writable for GPCLR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpclr1.rs b/crates/bcm2835-lpa/src/gpio/gpclr1.rs new file mode 100644 index 0000000..84ce196 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpclr1.rs @@ -0,0 +1,216 @@ +#[doc = "Register `GPCLR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLR32` writer - Clear 32"] +pub type CLR32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR33` writer - Clear 33"] +pub type CLR33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR34` writer - Clear 34"] +pub type CLR34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR35` writer - Clear 35"] +pub type CLR35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR36` writer - Clear 36"] +pub type CLR36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR37` writer - Clear 37"] +pub type CLR37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR38` writer - Clear 38"] +pub type CLR38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR39` writer - Clear 39"] +pub type CLR39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR40` writer - Clear 40"] +pub type CLR40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR41` writer - Clear 41"] +pub type CLR41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR42` writer - Clear 42"] +pub type CLR42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR43` writer - Clear 43"] +pub type CLR43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR44` writer - Clear 44"] +pub type CLR44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR45` writer - Clear 45"] +pub type CLR45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR46` writer - Clear 46"] +pub type CLR46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR47` writer - Clear 47"] +pub type CLR47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR48` writer - Clear 48"] +pub type CLR48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR49` writer - Clear 49"] +pub type CLR49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR50` writer - Clear 50"] +pub type CLR50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR51` writer - Clear 51"] +pub type CLR51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR52` writer - Clear 52"] +pub type CLR52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR53` writer - Clear 53"] +pub type CLR53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Clear 32"] + #[inline(always)] + #[must_use] + pub fn clr32(&mut self) -> CLR32_W<0> { + CLR32_W::new(self) + } + #[doc = "Bit 1 - Clear 33"] + #[inline(always)] + #[must_use] + pub fn clr33(&mut self) -> CLR33_W<1> { + CLR33_W::new(self) + } + #[doc = "Bit 2 - Clear 34"] + #[inline(always)] + #[must_use] + pub fn clr34(&mut self) -> CLR34_W<2> { + CLR34_W::new(self) + } + #[doc = "Bit 3 - Clear 35"] + #[inline(always)] + #[must_use] + pub fn clr35(&mut self) -> CLR35_W<3> { + CLR35_W::new(self) + } + #[doc = "Bit 4 - Clear 36"] + #[inline(always)] + #[must_use] + pub fn clr36(&mut self) -> CLR36_W<4> { + CLR36_W::new(self) + } + #[doc = "Bit 5 - Clear 37"] + #[inline(always)] + #[must_use] + pub fn clr37(&mut self) -> CLR37_W<5> { + CLR37_W::new(self) + } + #[doc = "Bit 6 - Clear 38"] + #[inline(always)] + #[must_use] + pub fn clr38(&mut self) -> CLR38_W<6> { + CLR38_W::new(self) + } + #[doc = "Bit 7 - Clear 39"] + #[inline(always)] + #[must_use] + pub fn clr39(&mut self) -> CLR39_W<7> { + CLR39_W::new(self) + } + #[doc = "Bit 8 - Clear 40"] + #[inline(always)] + #[must_use] + pub fn clr40(&mut self) -> CLR40_W<8> { + CLR40_W::new(self) + } + #[doc = "Bit 9 - Clear 41"] + #[inline(always)] + #[must_use] + pub fn clr41(&mut self) -> CLR41_W<9> { + CLR41_W::new(self) + } + #[doc = "Bit 10 - Clear 42"] + #[inline(always)] + #[must_use] + pub fn clr42(&mut self) -> CLR42_W<10> { + CLR42_W::new(self) + } + #[doc = "Bit 11 - Clear 43"] + #[inline(always)] + #[must_use] + pub fn clr43(&mut self) -> CLR43_W<11> { + CLR43_W::new(self) + } + #[doc = "Bit 12 - Clear 44"] + #[inline(always)] + #[must_use] + pub fn clr44(&mut self) -> CLR44_W<12> { + CLR44_W::new(self) + } + #[doc = "Bit 13 - Clear 45"] + #[inline(always)] + #[must_use] + pub fn clr45(&mut self) -> CLR45_W<13> { + CLR45_W::new(self) + } + #[doc = "Bit 14 - Clear 46"] + #[inline(always)] + #[must_use] + pub fn clr46(&mut self) -> CLR46_W<14> { + CLR46_W::new(self) + } + #[doc = "Bit 15 - Clear 47"] + #[inline(always)] + #[must_use] + pub fn clr47(&mut self) -> CLR47_W<15> { + CLR47_W::new(self) + } + #[doc = "Bit 16 - Clear 48"] + #[inline(always)] + #[must_use] + pub fn clr48(&mut self) -> CLR48_W<16> { + CLR48_W::new(self) + } + #[doc = "Bit 17 - Clear 49"] + #[inline(always)] + #[must_use] + pub fn clr49(&mut self) -> CLR49_W<17> { + CLR49_W::new(self) + } + #[doc = "Bit 18 - Clear 50"] + #[inline(always)] + #[must_use] + pub fn clr50(&mut self) -> CLR50_W<18> { + CLR50_W::new(self) + } + #[doc = "Bit 19 - Clear 51"] + #[inline(always)] + #[must_use] + pub fn clr51(&mut self) -> CLR51_W<19> { + CLR51_W::new(self) + } + #[doc = "Bit 20 - Clear 52"] + #[inline(always)] + #[must_use] + pub fn clr52(&mut self) -> CLR52_W<20> { + CLR52_W::new(self) + } + #[doc = "Bit 21 - Clear 53"] + #[inline(always)] + #[must_use] + pub fn clr53(&mut self) -> CLR53_W<21> { + CLR53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Clear 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr1](index.html) module"] +pub struct GPCLR1_SPEC; +impl crate::RegisterSpec for GPCLR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpclr1::W](W) writer structure"] +impl crate::Writable for GPCLR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpeds0.rs b/crates/bcm2835-lpa/src/gpio/gpeds0.rs new file mode 100644 index 0000000..7aadf5b --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpeds0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPEDS0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPEDS0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EDS0` reader - Event detected 0"] +pub type EDS0_R = crate::BitReader; +#[doc = "Field `EDS0` writer - Event detected 0"] +pub type EDS0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS1` reader - Event detected 1"] +pub type EDS1_R = crate::BitReader; +#[doc = "Field `EDS1` writer - Event detected 1"] +pub type EDS1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS2` reader - Event detected 2"] +pub type EDS2_R = crate::BitReader; +#[doc = "Field `EDS2` writer - Event detected 2"] +pub type EDS2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS3` reader - Event detected 3"] +pub type EDS3_R = crate::BitReader; +#[doc = "Field `EDS3` writer - Event detected 3"] +pub type EDS3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS4` reader - Event detected 4"] +pub type EDS4_R = crate::BitReader; +#[doc = "Field `EDS4` writer - Event detected 4"] +pub type EDS4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS5` reader - Event detected 5"] +pub type EDS5_R = crate::BitReader; +#[doc = "Field `EDS5` writer - Event detected 5"] +pub type EDS5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS6` reader - Event detected 6"] +pub type EDS6_R = crate::BitReader; +#[doc = "Field `EDS6` writer - Event detected 6"] +pub type EDS6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS7` reader - Event detected 7"] +pub type EDS7_R = crate::BitReader; +#[doc = "Field `EDS7` writer - Event detected 7"] +pub type EDS7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS8` reader - Event detected 8"] +pub type EDS8_R = crate::BitReader; +#[doc = "Field `EDS8` writer - Event detected 8"] +pub type EDS8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS9` reader - Event detected 9"] +pub type EDS9_R = crate::BitReader; +#[doc = "Field `EDS9` writer - Event detected 9"] +pub type EDS9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS10` reader - Event detected 10"] +pub type EDS10_R = crate::BitReader; +#[doc = "Field `EDS10` writer - Event detected 10"] +pub type EDS10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS11` reader - Event detected 11"] +pub type EDS11_R = crate::BitReader; +#[doc = "Field `EDS11` writer - Event detected 11"] +pub type EDS11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS12` reader - Event detected 12"] +pub type EDS12_R = crate::BitReader; +#[doc = "Field `EDS12` writer - Event detected 12"] +pub type EDS12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS13` reader - Event detected 13"] +pub type EDS13_R = crate::BitReader; +#[doc = "Field `EDS13` writer - Event detected 13"] +pub type EDS13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS14` reader - Event detected 14"] +pub type EDS14_R = crate::BitReader; +#[doc = "Field `EDS14` writer - Event detected 14"] +pub type EDS14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS15` reader - Event detected 15"] +pub type EDS15_R = crate::BitReader; +#[doc = "Field `EDS15` writer - Event detected 15"] +pub type EDS15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS16` reader - Event detected 16"] +pub type EDS16_R = crate::BitReader; +#[doc = "Field `EDS16` writer - Event detected 16"] +pub type EDS16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS17` reader - Event detected 17"] +pub type EDS17_R = crate::BitReader; +#[doc = "Field `EDS17` writer - Event detected 17"] +pub type EDS17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS18` reader - Event detected 18"] +pub type EDS18_R = crate::BitReader; +#[doc = "Field `EDS18` writer - Event detected 18"] +pub type EDS18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS19` reader - Event detected 19"] +pub type EDS19_R = crate::BitReader; +#[doc = "Field `EDS19` writer - Event detected 19"] +pub type EDS19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS20` reader - Event detected 20"] +pub type EDS20_R = crate::BitReader; +#[doc = "Field `EDS20` writer - Event detected 20"] +pub type EDS20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS21` reader - Event detected 21"] +pub type EDS21_R = crate::BitReader; +#[doc = "Field `EDS21` writer - Event detected 21"] +pub type EDS21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS22` reader - Event detected 22"] +pub type EDS22_R = crate::BitReader; +#[doc = "Field `EDS22` writer - Event detected 22"] +pub type EDS22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS23` reader - Event detected 23"] +pub type EDS23_R = crate::BitReader; +#[doc = "Field `EDS23` writer - Event detected 23"] +pub type EDS23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS24` reader - Event detected 24"] +pub type EDS24_R = crate::BitReader; +#[doc = "Field `EDS24` writer - Event detected 24"] +pub type EDS24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS25` reader - Event detected 25"] +pub type EDS25_R = crate::BitReader; +#[doc = "Field `EDS25` writer - Event detected 25"] +pub type EDS25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS26` reader - Event detected 26"] +pub type EDS26_R = crate::BitReader; +#[doc = "Field `EDS26` writer - Event detected 26"] +pub type EDS26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS27` reader - Event detected 27"] +pub type EDS27_R = crate::BitReader; +#[doc = "Field `EDS27` writer - Event detected 27"] +pub type EDS27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS28` reader - Event detected 28"] +pub type EDS28_R = crate::BitReader; +#[doc = "Field `EDS28` writer - Event detected 28"] +pub type EDS28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS29` reader - Event detected 29"] +pub type EDS29_R = crate::BitReader; +#[doc = "Field `EDS29` writer - Event detected 29"] +pub type EDS29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS30` reader - Event detected 30"] +pub type EDS30_R = crate::BitReader; +#[doc = "Field `EDS30` writer - Event detected 30"] +pub type EDS30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS31` reader - Event detected 31"] +pub type EDS31_R = crate::BitReader; +#[doc = "Field `EDS31` writer - Event detected 31"] +pub type EDS31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Event detected 0"] + #[inline(always)] + pub fn eds0(&self) -> EDS0_R { + EDS0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Event detected 1"] + #[inline(always)] + pub fn eds1(&self) -> EDS1_R { + EDS1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Event detected 2"] + #[inline(always)] + pub fn eds2(&self) -> EDS2_R { + EDS2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Event detected 3"] + #[inline(always)] + pub fn eds3(&self) -> EDS3_R { + EDS3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Event detected 4"] + #[inline(always)] + pub fn eds4(&self) -> EDS4_R { + EDS4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Event detected 5"] + #[inline(always)] + pub fn eds5(&self) -> EDS5_R { + EDS5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Event detected 6"] + #[inline(always)] + pub fn eds6(&self) -> EDS6_R { + EDS6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Event detected 7"] + #[inline(always)] + pub fn eds7(&self) -> EDS7_R { + EDS7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Event detected 8"] + #[inline(always)] + pub fn eds8(&self) -> EDS8_R { + EDS8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Event detected 9"] + #[inline(always)] + pub fn eds9(&self) -> EDS9_R { + EDS9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Event detected 10"] + #[inline(always)] + pub fn eds10(&self) -> EDS10_R { + EDS10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Event detected 11"] + #[inline(always)] + pub fn eds11(&self) -> EDS11_R { + EDS11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Event detected 12"] + #[inline(always)] + pub fn eds12(&self) -> EDS12_R { + EDS12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Event detected 13"] + #[inline(always)] + pub fn eds13(&self) -> EDS13_R { + EDS13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Event detected 14"] + #[inline(always)] + pub fn eds14(&self) -> EDS14_R { + EDS14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Event detected 15"] + #[inline(always)] + pub fn eds15(&self) -> EDS15_R { + EDS15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Event detected 16"] + #[inline(always)] + pub fn eds16(&self) -> EDS16_R { + EDS16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Event detected 17"] + #[inline(always)] + pub fn eds17(&self) -> EDS17_R { + EDS17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event detected 18"] + #[inline(always)] + pub fn eds18(&self) -> EDS18_R { + EDS18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Event detected 19"] + #[inline(always)] + pub fn eds19(&self) -> EDS19_R { + EDS19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Event detected 20"] + #[inline(always)] + pub fn eds20(&self) -> EDS20_R { + EDS20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event detected 21"] + #[inline(always)] + pub fn eds21(&self) -> EDS21_R { + EDS21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Event detected 22"] + #[inline(always)] + pub fn eds22(&self) -> EDS22_R { + EDS22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Event detected 23"] + #[inline(always)] + pub fn eds23(&self) -> EDS23_R { + EDS23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Event detected 24"] + #[inline(always)] + pub fn eds24(&self) -> EDS24_R { + EDS24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Event detected 25"] + #[inline(always)] + pub fn eds25(&self) -> EDS25_R { + EDS25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Event detected 26"] + #[inline(always)] + pub fn eds26(&self) -> EDS26_R { + EDS26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Event detected 27"] + #[inline(always)] + pub fn eds27(&self) -> EDS27_R { + EDS27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Event detected 28"] + #[inline(always)] + pub fn eds28(&self) -> EDS28_R { + EDS28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Event detected 29"] + #[inline(always)] + pub fn eds29(&self) -> EDS29_R { + EDS29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Event detected 30"] + #[inline(always)] + pub fn eds30(&self) -> EDS30_R { + EDS30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Event detected 31"] + #[inline(always)] + pub fn eds31(&self) -> EDS31_R { + EDS31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event detected 0"] + #[inline(always)] + #[must_use] + pub fn eds0(&mut self) -> EDS0_W<0> { + EDS0_W::new(self) + } + #[doc = "Bit 1 - Event detected 1"] + #[inline(always)] + #[must_use] + pub fn eds1(&mut self) -> EDS1_W<1> { + EDS1_W::new(self) + } + #[doc = "Bit 2 - Event detected 2"] + #[inline(always)] + #[must_use] + pub fn eds2(&mut self) -> EDS2_W<2> { + EDS2_W::new(self) + } + #[doc = "Bit 3 - Event detected 3"] + #[inline(always)] + #[must_use] + pub fn eds3(&mut self) -> EDS3_W<3> { + EDS3_W::new(self) + } + #[doc = "Bit 4 - Event detected 4"] + #[inline(always)] + #[must_use] + pub fn eds4(&mut self) -> EDS4_W<4> { + EDS4_W::new(self) + } + #[doc = "Bit 5 - Event detected 5"] + #[inline(always)] + #[must_use] + pub fn eds5(&mut self) -> EDS5_W<5> { + EDS5_W::new(self) + } + #[doc = "Bit 6 - Event detected 6"] + #[inline(always)] + #[must_use] + pub fn eds6(&mut self) -> EDS6_W<6> { + EDS6_W::new(self) + } + #[doc = "Bit 7 - Event detected 7"] + #[inline(always)] + #[must_use] + pub fn eds7(&mut self) -> EDS7_W<7> { + EDS7_W::new(self) + } + #[doc = "Bit 8 - Event detected 8"] + #[inline(always)] + #[must_use] + pub fn eds8(&mut self) -> EDS8_W<8> { + EDS8_W::new(self) + } + #[doc = "Bit 9 - Event detected 9"] + #[inline(always)] + #[must_use] + pub fn eds9(&mut self) -> EDS9_W<9> { + EDS9_W::new(self) + } + #[doc = "Bit 10 - Event detected 10"] + #[inline(always)] + #[must_use] + pub fn eds10(&mut self) -> EDS10_W<10> { + EDS10_W::new(self) + } + #[doc = "Bit 11 - Event detected 11"] + #[inline(always)] + #[must_use] + pub fn eds11(&mut self) -> EDS11_W<11> { + EDS11_W::new(self) + } + #[doc = "Bit 12 - Event detected 12"] + #[inline(always)] + #[must_use] + pub fn eds12(&mut self) -> EDS12_W<12> { + EDS12_W::new(self) + } + #[doc = "Bit 13 - Event detected 13"] + #[inline(always)] + #[must_use] + pub fn eds13(&mut self) -> EDS13_W<13> { + EDS13_W::new(self) + } + #[doc = "Bit 14 - Event detected 14"] + #[inline(always)] + #[must_use] + pub fn eds14(&mut self) -> EDS14_W<14> { + EDS14_W::new(self) + } + #[doc = "Bit 15 - Event detected 15"] + #[inline(always)] + #[must_use] + pub fn eds15(&mut self) -> EDS15_W<15> { + EDS15_W::new(self) + } + #[doc = "Bit 16 - Event detected 16"] + #[inline(always)] + #[must_use] + pub fn eds16(&mut self) -> EDS16_W<16> { + EDS16_W::new(self) + } + #[doc = "Bit 17 - Event detected 17"] + #[inline(always)] + #[must_use] + pub fn eds17(&mut self) -> EDS17_W<17> { + EDS17_W::new(self) + } + #[doc = "Bit 18 - Event detected 18"] + #[inline(always)] + #[must_use] + pub fn eds18(&mut self) -> EDS18_W<18> { + EDS18_W::new(self) + } + #[doc = "Bit 19 - Event detected 19"] + #[inline(always)] + #[must_use] + pub fn eds19(&mut self) -> EDS19_W<19> { + EDS19_W::new(self) + } + #[doc = "Bit 20 - Event detected 20"] + #[inline(always)] + #[must_use] + pub fn eds20(&mut self) -> EDS20_W<20> { + EDS20_W::new(self) + } + #[doc = "Bit 21 - Event detected 21"] + #[inline(always)] + #[must_use] + pub fn eds21(&mut self) -> EDS21_W<21> { + EDS21_W::new(self) + } + #[doc = "Bit 22 - Event detected 22"] + #[inline(always)] + #[must_use] + pub fn eds22(&mut self) -> EDS22_W<22> { + EDS22_W::new(self) + } + #[doc = "Bit 23 - Event detected 23"] + #[inline(always)] + #[must_use] + pub fn eds23(&mut self) -> EDS23_W<23> { + EDS23_W::new(self) + } + #[doc = "Bit 24 - Event detected 24"] + #[inline(always)] + #[must_use] + pub fn eds24(&mut self) -> EDS24_W<24> { + EDS24_W::new(self) + } + #[doc = "Bit 25 - Event detected 25"] + #[inline(always)] + #[must_use] + pub fn eds25(&mut self) -> EDS25_W<25> { + EDS25_W::new(self) + } + #[doc = "Bit 26 - Event detected 26"] + #[inline(always)] + #[must_use] + pub fn eds26(&mut self) -> EDS26_W<26> { + EDS26_W::new(self) + } + #[doc = "Bit 27 - Event detected 27"] + #[inline(always)] + #[must_use] + pub fn eds27(&mut self) -> EDS27_W<27> { + EDS27_W::new(self) + } + #[doc = "Bit 28 - Event detected 28"] + #[inline(always)] + #[must_use] + pub fn eds28(&mut self) -> EDS28_W<28> { + EDS28_W::new(self) + } + #[doc = "Bit 29 - Event detected 29"] + #[inline(always)] + #[must_use] + pub fn eds29(&mut self) -> EDS29_W<29> { + EDS29_W::new(self) + } + #[doc = "Bit 30 - Event detected 30"] + #[inline(always)] + #[must_use] + pub fn eds30(&mut self) -> EDS30_W<30> { + EDS30_W::new(self) + } + #[doc = "Bit 31 - Event detected 31"] + #[inline(always)] + #[must_use] + pub fn eds31(&mut self) -> EDS31_W<31> { + EDS31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Event Detect Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds0](index.html) module"] +pub struct GPEDS0_SPEC; +impl crate::RegisterSpec for GPEDS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpeds0::R](R) reader structure"] +impl crate::Readable for GPEDS0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpeds0::W](W) writer structure"] +impl crate::Writable for GPEDS0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpeds1.rs b/crates/bcm2835-lpa/src/gpio/gpeds1.rs new file mode 100644 index 0000000..bcef23a --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpeds1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPEDS1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPEDS1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EDS32` reader - Event detected 32"] +pub type EDS32_R = crate::BitReader; +#[doc = "Field `EDS32` writer - Event detected 32"] +pub type EDS32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS33` reader - Event detected 33"] +pub type EDS33_R = crate::BitReader; +#[doc = "Field `EDS33` writer - Event detected 33"] +pub type EDS33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS34` reader - Event detected 34"] +pub type EDS34_R = crate::BitReader; +#[doc = "Field `EDS34` writer - Event detected 34"] +pub type EDS34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS35` reader - Event detected 35"] +pub type EDS35_R = crate::BitReader; +#[doc = "Field `EDS35` writer - Event detected 35"] +pub type EDS35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS36` reader - Event detected 36"] +pub type EDS36_R = crate::BitReader; +#[doc = "Field `EDS36` writer - Event detected 36"] +pub type EDS36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS37` reader - Event detected 37"] +pub type EDS37_R = crate::BitReader; +#[doc = "Field `EDS37` writer - Event detected 37"] +pub type EDS37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS38` reader - Event detected 38"] +pub type EDS38_R = crate::BitReader; +#[doc = "Field `EDS38` writer - Event detected 38"] +pub type EDS38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS39` reader - Event detected 39"] +pub type EDS39_R = crate::BitReader; +#[doc = "Field `EDS39` writer - Event detected 39"] +pub type EDS39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS40` reader - Event detected 40"] +pub type EDS40_R = crate::BitReader; +#[doc = "Field `EDS40` writer - Event detected 40"] +pub type EDS40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS41` reader - Event detected 41"] +pub type EDS41_R = crate::BitReader; +#[doc = "Field `EDS41` writer - Event detected 41"] +pub type EDS41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS42` reader - Event detected 42"] +pub type EDS42_R = crate::BitReader; +#[doc = "Field `EDS42` writer - Event detected 42"] +pub type EDS42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS43` reader - Event detected 43"] +pub type EDS43_R = crate::BitReader; +#[doc = "Field `EDS43` writer - Event detected 43"] +pub type EDS43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS44` reader - Event detected 44"] +pub type EDS44_R = crate::BitReader; +#[doc = "Field `EDS44` writer - Event detected 44"] +pub type EDS44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS45` reader - Event detected 45"] +pub type EDS45_R = crate::BitReader; +#[doc = "Field `EDS45` writer - Event detected 45"] +pub type EDS45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS46` reader - Event detected 46"] +pub type EDS46_R = crate::BitReader; +#[doc = "Field `EDS46` writer - Event detected 46"] +pub type EDS46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS47` reader - Event detected 47"] +pub type EDS47_R = crate::BitReader; +#[doc = "Field `EDS47` writer - Event detected 47"] +pub type EDS47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS48` reader - Event detected 48"] +pub type EDS48_R = crate::BitReader; +#[doc = "Field `EDS48` writer - Event detected 48"] +pub type EDS48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS49` reader - Event detected 49"] +pub type EDS49_R = crate::BitReader; +#[doc = "Field `EDS49` writer - Event detected 49"] +pub type EDS49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS50` reader - Event detected 50"] +pub type EDS50_R = crate::BitReader; +#[doc = "Field `EDS50` writer - Event detected 50"] +pub type EDS50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS51` reader - Event detected 51"] +pub type EDS51_R = crate::BitReader; +#[doc = "Field `EDS51` writer - Event detected 51"] +pub type EDS51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS52` reader - Event detected 52"] +pub type EDS52_R = crate::BitReader; +#[doc = "Field `EDS52` writer - Event detected 52"] +pub type EDS52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS53` reader - Event detected 53"] +pub type EDS53_R = crate::BitReader; +#[doc = "Field `EDS53` writer - Event detected 53"] +pub type EDS53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Event detected 32"] + #[inline(always)] + pub fn eds32(&self) -> EDS32_R { + EDS32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Event detected 33"] + #[inline(always)] + pub fn eds33(&self) -> EDS33_R { + EDS33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Event detected 34"] + #[inline(always)] + pub fn eds34(&self) -> EDS34_R { + EDS34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Event detected 35"] + #[inline(always)] + pub fn eds35(&self) -> EDS35_R { + EDS35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Event detected 36"] + #[inline(always)] + pub fn eds36(&self) -> EDS36_R { + EDS36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Event detected 37"] + #[inline(always)] + pub fn eds37(&self) -> EDS37_R { + EDS37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Event detected 38"] + #[inline(always)] + pub fn eds38(&self) -> EDS38_R { + EDS38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Event detected 39"] + #[inline(always)] + pub fn eds39(&self) -> EDS39_R { + EDS39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Event detected 40"] + #[inline(always)] + pub fn eds40(&self) -> EDS40_R { + EDS40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Event detected 41"] + #[inline(always)] + pub fn eds41(&self) -> EDS41_R { + EDS41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Event detected 42"] + #[inline(always)] + pub fn eds42(&self) -> EDS42_R { + EDS42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Event detected 43"] + #[inline(always)] + pub fn eds43(&self) -> EDS43_R { + EDS43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Event detected 44"] + #[inline(always)] + pub fn eds44(&self) -> EDS44_R { + EDS44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Event detected 45"] + #[inline(always)] + pub fn eds45(&self) -> EDS45_R { + EDS45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Event detected 46"] + #[inline(always)] + pub fn eds46(&self) -> EDS46_R { + EDS46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Event detected 47"] + #[inline(always)] + pub fn eds47(&self) -> EDS47_R { + EDS47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Event detected 48"] + #[inline(always)] + pub fn eds48(&self) -> EDS48_R { + EDS48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Event detected 49"] + #[inline(always)] + pub fn eds49(&self) -> EDS49_R { + EDS49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event detected 50"] + #[inline(always)] + pub fn eds50(&self) -> EDS50_R { + EDS50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Event detected 51"] + #[inline(always)] + pub fn eds51(&self) -> EDS51_R { + EDS51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Event detected 52"] + #[inline(always)] + pub fn eds52(&self) -> EDS52_R { + EDS52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event detected 53"] + #[inline(always)] + pub fn eds53(&self) -> EDS53_R { + EDS53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event detected 32"] + #[inline(always)] + #[must_use] + pub fn eds32(&mut self) -> EDS32_W<0> { + EDS32_W::new(self) + } + #[doc = "Bit 1 - Event detected 33"] + #[inline(always)] + #[must_use] + pub fn eds33(&mut self) -> EDS33_W<1> { + EDS33_W::new(self) + } + #[doc = "Bit 2 - Event detected 34"] + #[inline(always)] + #[must_use] + pub fn eds34(&mut self) -> EDS34_W<2> { + EDS34_W::new(self) + } + #[doc = "Bit 3 - Event detected 35"] + #[inline(always)] + #[must_use] + pub fn eds35(&mut self) -> EDS35_W<3> { + EDS35_W::new(self) + } + #[doc = "Bit 4 - Event detected 36"] + #[inline(always)] + #[must_use] + pub fn eds36(&mut self) -> EDS36_W<4> { + EDS36_W::new(self) + } + #[doc = "Bit 5 - Event detected 37"] + #[inline(always)] + #[must_use] + pub fn eds37(&mut self) -> EDS37_W<5> { + EDS37_W::new(self) + } + #[doc = "Bit 6 - Event detected 38"] + #[inline(always)] + #[must_use] + pub fn eds38(&mut self) -> EDS38_W<6> { + EDS38_W::new(self) + } + #[doc = "Bit 7 - Event detected 39"] + #[inline(always)] + #[must_use] + pub fn eds39(&mut self) -> EDS39_W<7> { + EDS39_W::new(self) + } + #[doc = "Bit 8 - Event detected 40"] + #[inline(always)] + #[must_use] + pub fn eds40(&mut self) -> EDS40_W<8> { + EDS40_W::new(self) + } + #[doc = "Bit 9 - Event detected 41"] + #[inline(always)] + #[must_use] + pub fn eds41(&mut self) -> EDS41_W<9> { + EDS41_W::new(self) + } + #[doc = "Bit 10 - Event detected 42"] + #[inline(always)] + #[must_use] + pub fn eds42(&mut self) -> EDS42_W<10> { + EDS42_W::new(self) + } + #[doc = "Bit 11 - Event detected 43"] + #[inline(always)] + #[must_use] + pub fn eds43(&mut self) -> EDS43_W<11> { + EDS43_W::new(self) + } + #[doc = "Bit 12 - Event detected 44"] + #[inline(always)] + #[must_use] + pub fn eds44(&mut self) -> EDS44_W<12> { + EDS44_W::new(self) + } + #[doc = "Bit 13 - Event detected 45"] + #[inline(always)] + #[must_use] + pub fn eds45(&mut self) -> EDS45_W<13> { + EDS45_W::new(self) + } + #[doc = "Bit 14 - Event detected 46"] + #[inline(always)] + #[must_use] + pub fn eds46(&mut self) -> EDS46_W<14> { + EDS46_W::new(self) + } + #[doc = "Bit 15 - Event detected 47"] + #[inline(always)] + #[must_use] + pub fn eds47(&mut self) -> EDS47_W<15> { + EDS47_W::new(self) + } + #[doc = "Bit 16 - Event detected 48"] + #[inline(always)] + #[must_use] + pub fn eds48(&mut self) -> EDS48_W<16> { + EDS48_W::new(self) + } + #[doc = "Bit 17 - Event detected 49"] + #[inline(always)] + #[must_use] + pub fn eds49(&mut self) -> EDS49_W<17> { + EDS49_W::new(self) + } + #[doc = "Bit 18 - Event detected 50"] + #[inline(always)] + #[must_use] + pub fn eds50(&mut self) -> EDS50_W<18> { + EDS50_W::new(self) + } + #[doc = "Bit 19 - Event detected 51"] + #[inline(always)] + #[must_use] + pub fn eds51(&mut self) -> EDS51_W<19> { + EDS51_W::new(self) + } + #[doc = "Bit 20 - Event detected 52"] + #[inline(always)] + #[must_use] + pub fn eds52(&mut self) -> EDS52_W<20> { + EDS52_W::new(self) + } + #[doc = "Bit 21 - Event detected 53"] + #[inline(always)] + #[must_use] + pub fn eds53(&mut self) -> EDS53_W<21> { + EDS53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Event Detect Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds1](index.html) module"] +pub struct GPEDS1_SPEC; +impl crate::RegisterSpec for GPEDS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpeds1::R](R) reader structure"] +impl crate::Readable for GPEDS1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpeds1::W](W) writer structure"] +impl crate::Writable for GPEDS1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfen0.rs b/crates/bcm2835-lpa/src/gpio/gpfen0.rs new file mode 100644 index 0000000..58ded22 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPFEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FEN0` reader - Falling edge enabled 0"] +pub type FEN0_R = crate::BitReader; +#[doc = "Field `FEN0` writer - Falling edge enabled 0"] +pub type FEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN1` reader - Falling edge enabled 1"] +pub type FEN1_R = crate::BitReader; +#[doc = "Field `FEN1` writer - Falling edge enabled 1"] +pub type FEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN2` reader - Falling edge enabled 2"] +pub type FEN2_R = crate::BitReader; +#[doc = "Field `FEN2` writer - Falling edge enabled 2"] +pub type FEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN3` reader - Falling edge enabled 3"] +pub type FEN3_R = crate::BitReader; +#[doc = "Field `FEN3` writer - Falling edge enabled 3"] +pub type FEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN4` reader - Falling edge enabled 4"] +pub type FEN4_R = crate::BitReader; +#[doc = "Field `FEN4` writer - Falling edge enabled 4"] +pub type FEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN5` reader - Falling edge enabled 5"] +pub type FEN5_R = crate::BitReader; +#[doc = "Field `FEN5` writer - Falling edge enabled 5"] +pub type FEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN6` reader - Falling edge enabled 6"] +pub type FEN6_R = crate::BitReader; +#[doc = "Field `FEN6` writer - Falling edge enabled 6"] +pub type FEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN7` reader - Falling edge enabled 7"] +pub type FEN7_R = crate::BitReader; +#[doc = "Field `FEN7` writer - Falling edge enabled 7"] +pub type FEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN8` reader - Falling edge enabled 8"] +pub type FEN8_R = crate::BitReader; +#[doc = "Field `FEN8` writer - Falling edge enabled 8"] +pub type FEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN9` reader - Falling edge enabled 9"] +pub type FEN9_R = crate::BitReader; +#[doc = "Field `FEN9` writer - Falling edge enabled 9"] +pub type FEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN10` reader - Falling edge enabled 10"] +pub type FEN10_R = crate::BitReader; +#[doc = "Field `FEN10` writer - Falling edge enabled 10"] +pub type FEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN11` reader - Falling edge enabled 11"] +pub type FEN11_R = crate::BitReader; +#[doc = "Field `FEN11` writer - Falling edge enabled 11"] +pub type FEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN12` reader - Falling edge enabled 12"] +pub type FEN12_R = crate::BitReader; +#[doc = "Field `FEN12` writer - Falling edge enabled 12"] +pub type FEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN13` reader - Falling edge enabled 13"] +pub type FEN13_R = crate::BitReader; +#[doc = "Field `FEN13` writer - Falling edge enabled 13"] +pub type FEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN14` reader - Falling edge enabled 14"] +pub type FEN14_R = crate::BitReader; +#[doc = "Field `FEN14` writer - Falling edge enabled 14"] +pub type FEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN15` reader - Falling edge enabled 15"] +pub type FEN15_R = crate::BitReader; +#[doc = "Field `FEN15` writer - Falling edge enabled 15"] +pub type FEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN16` reader - Falling edge enabled 16"] +pub type FEN16_R = crate::BitReader; +#[doc = "Field `FEN16` writer - Falling edge enabled 16"] +pub type FEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN17` reader - Falling edge enabled 17"] +pub type FEN17_R = crate::BitReader; +#[doc = "Field `FEN17` writer - Falling edge enabled 17"] +pub type FEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN18` reader - Falling edge enabled 18"] +pub type FEN18_R = crate::BitReader; +#[doc = "Field `FEN18` writer - Falling edge enabled 18"] +pub type FEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN19` reader - Falling edge enabled 19"] +pub type FEN19_R = crate::BitReader; +#[doc = "Field `FEN19` writer - Falling edge enabled 19"] +pub type FEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN20` reader - Falling edge enabled 20"] +pub type FEN20_R = crate::BitReader; +#[doc = "Field `FEN20` writer - Falling edge enabled 20"] +pub type FEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN21` reader - Falling edge enabled 21"] +pub type FEN21_R = crate::BitReader; +#[doc = "Field `FEN21` writer - Falling edge enabled 21"] +pub type FEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN22` reader - Falling edge enabled 22"] +pub type FEN22_R = crate::BitReader; +#[doc = "Field `FEN22` writer - Falling edge enabled 22"] +pub type FEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN23` reader - Falling edge enabled 23"] +pub type FEN23_R = crate::BitReader; +#[doc = "Field `FEN23` writer - Falling edge enabled 23"] +pub type FEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN24` reader - Falling edge enabled 24"] +pub type FEN24_R = crate::BitReader; +#[doc = "Field `FEN24` writer - Falling edge enabled 24"] +pub type FEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN25` reader - Falling edge enabled 25"] +pub type FEN25_R = crate::BitReader; +#[doc = "Field `FEN25` writer - Falling edge enabled 25"] +pub type FEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN26` reader - Falling edge enabled 26"] +pub type FEN26_R = crate::BitReader; +#[doc = "Field `FEN26` writer - Falling edge enabled 26"] +pub type FEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN27` reader - Falling edge enabled 27"] +pub type FEN27_R = crate::BitReader; +#[doc = "Field `FEN27` writer - Falling edge enabled 27"] +pub type FEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN28` reader - Falling edge enabled 28"] +pub type FEN28_R = crate::BitReader; +#[doc = "Field `FEN28` writer - Falling edge enabled 28"] +pub type FEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN29` reader - Falling edge enabled 29"] +pub type FEN29_R = crate::BitReader; +#[doc = "Field `FEN29` writer - Falling edge enabled 29"] +pub type FEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN30` reader - Falling edge enabled 30"] +pub type FEN30_R = crate::BitReader; +#[doc = "Field `FEN30` writer - Falling edge enabled 30"] +pub type FEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN31` reader - Falling edge enabled 31"] +pub type FEN31_R = crate::BitReader; +#[doc = "Field `FEN31` writer - Falling edge enabled 31"] +pub type FEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Falling edge enabled 0"] + #[inline(always)] + pub fn fen0(&self) -> FEN0_R { + FEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling edge enabled 1"] + #[inline(always)] + pub fn fen1(&self) -> FEN1_R { + FEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Falling edge enabled 2"] + #[inline(always)] + pub fn fen2(&self) -> FEN2_R { + FEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Falling edge enabled 3"] + #[inline(always)] + pub fn fen3(&self) -> FEN3_R { + FEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling edge enabled 4"] + #[inline(always)] + pub fn fen4(&self) -> FEN4_R { + FEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Falling edge enabled 5"] + #[inline(always)] + pub fn fen5(&self) -> FEN5_R { + FEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Falling edge enabled 6"] + #[inline(always)] + pub fn fen6(&self) -> FEN6_R { + FEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling edge enabled 7"] + #[inline(always)] + pub fn fen7(&self) -> FEN7_R { + FEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Falling edge enabled 8"] + #[inline(always)] + pub fn fen8(&self) -> FEN8_R { + FEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Falling edge enabled 9"] + #[inline(always)] + pub fn fen9(&self) -> FEN9_R { + FEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling edge enabled 10"] + #[inline(always)] + pub fn fen10(&self) -> FEN10_R { + FEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Falling edge enabled 11"] + #[inline(always)] + pub fn fen11(&self) -> FEN11_R { + FEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Falling edge enabled 12"] + #[inline(always)] + pub fn fen12(&self) -> FEN12_R { + FEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Falling edge enabled 13"] + #[inline(always)] + pub fn fen13(&self) -> FEN13_R { + FEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Falling edge enabled 14"] + #[inline(always)] + pub fn fen14(&self) -> FEN14_R { + FEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Falling edge enabled 15"] + #[inline(always)] + pub fn fen15(&self) -> FEN15_R { + FEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Falling edge enabled 16"] + #[inline(always)] + pub fn fen16(&self) -> FEN16_R { + FEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Falling edge enabled 17"] + #[inline(always)] + pub fn fen17(&self) -> FEN17_R { + FEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Falling edge enabled 18"] + #[inline(always)] + pub fn fen18(&self) -> FEN18_R { + FEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Falling edge enabled 19"] + #[inline(always)] + pub fn fen19(&self) -> FEN19_R { + FEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Falling edge enabled 20"] + #[inline(always)] + pub fn fen20(&self) -> FEN20_R { + FEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Falling edge enabled 21"] + #[inline(always)] + pub fn fen21(&self) -> FEN21_R { + FEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Falling edge enabled 22"] + #[inline(always)] + pub fn fen22(&self) -> FEN22_R { + FEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Falling edge enabled 23"] + #[inline(always)] + pub fn fen23(&self) -> FEN23_R { + FEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Falling edge enabled 24"] + #[inline(always)] + pub fn fen24(&self) -> FEN24_R { + FEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Falling edge enabled 25"] + #[inline(always)] + pub fn fen25(&self) -> FEN25_R { + FEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Falling edge enabled 26"] + #[inline(always)] + pub fn fen26(&self) -> FEN26_R { + FEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Falling edge enabled 27"] + #[inline(always)] + pub fn fen27(&self) -> FEN27_R { + FEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Falling edge enabled 28"] + #[inline(always)] + pub fn fen28(&self) -> FEN28_R { + FEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Falling edge enabled 29"] + #[inline(always)] + pub fn fen29(&self) -> FEN29_R { + FEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Falling edge enabled 30"] + #[inline(always)] + pub fn fen30(&self) -> FEN30_R { + FEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Falling edge enabled 31"] + #[inline(always)] + pub fn fen31(&self) -> FEN31_R { + FEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Falling edge enabled 0"] + #[inline(always)] + #[must_use] + pub fn fen0(&mut self) -> FEN0_W<0> { + FEN0_W::new(self) + } + #[doc = "Bit 1 - Falling edge enabled 1"] + #[inline(always)] + #[must_use] + pub fn fen1(&mut self) -> FEN1_W<1> { + FEN1_W::new(self) + } + #[doc = "Bit 2 - Falling edge enabled 2"] + #[inline(always)] + #[must_use] + pub fn fen2(&mut self) -> FEN2_W<2> { + FEN2_W::new(self) + } + #[doc = "Bit 3 - Falling edge enabled 3"] + #[inline(always)] + #[must_use] + pub fn fen3(&mut self) -> FEN3_W<3> { + FEN3_W::new(self) + } + #[doc = "Bit 4 - Falling edge enabled 4"] + #[inline(always)] + #[must_use] + pub fn fen4(&mut self) -> FEN4_W<4> { + FEN4_W::new(self) + } + #[doc = "Bit 5 - Falling edge enabled 5"] + #[inline(always)] + #[must_use] + pub fn fen5(&mut self) -> FEN5_W<5> { + FEN5_W::new(self) + } + #[doc = "Bit 6 - Falling edge enabled 6"] + #[inline(always)] + #[must_use] + pub fn fen6(&mut self) -> FEN6_W<6> { + FEN6_W::new(self) + } + #[doc = "Bit 7 - Falling edge enabled 7"] + #[inline(always)] + #[must_use] + pub fn fen7(&mut self) -> FEN7_W<7> { + FEN7_W::new(self) + } + #[doc = "Bit 8 - Falling edge enabled 8"] + #[inline(always)] + #[must_use] + pub fn fen8(&mut self) -> FEN8_W<8> { + FEN8_W::new(self) + } + #[doc = "Bit 9 - Falling edge enabled 9"] + #[inline(always)] + #[must_use] + pub fn fen9(&mut self) -> FEN9_W<9> { + FEN9_W::new(self) + } + #[doc = "Bit 10 - Falling edge enabled 10"] + #[inline(always)] + #[must_use] + pub fn fen10(&mut self) -> FEN10_W<10> { + FEN10_W::new(self) + } + #[doc = "Bit 11 - Falling edge enabled 11"] + #[inline(always)] + #[must_use] + pub fn fen11(&mut self) -> FEN11_W<11> { + FEN11_W::new(self) + } + #[doc = "Bit 12 - Falling edge enabled 12"] + #[inline(always)] + #[must_use] + pub fn fen12(&mut self) -> FEN12_W<12> { + FEN12_W::new(self) + } + #[doc = "Bit 13 - Falling edge enabled 13"] + #[inline(always)] + #[must_use] + pub fn fen13(&mut self) -> FEN13_W<13> { + FEN13_W::new(self) + } + #[doc = "Bit 14 - Falling edge enabled 14"] + #[inline(always)] + #[must_use] + pub fn fen14(&mut self) -> FEN14_W<14> { + FEN14_W::new(self) + } + #[doc = "Bit 15 - Falling edge enabled 15"] + #[inline(always)] + #[must_use] + pub fn fen15(&mut self) -> FEN15_W<15> { + FEN15_W::new(self) + } + #[doc = "Bit 16 - Falling edge enabled 16"] + #[inline(always)] + #[must_use] + pub fn fen16(&mut self) -> FEN16_W<16> { + FEN16_W::new(self) + } + #[doc = "Bit 17 - Falling edge enabled 17"] + #[inline(always)] + #[must_use] + pub fn fen17(&mut self) -> FEN17_W<17> { + FEN17_W::new(self) + } + #[doc = "Bit 18 - Falling edge enabled 18"] + #[inline(always)] + #[must_use] + pub fn fen18(&mut self) -> FEN18_W<18> { + FEN18_W::new(self) + } + #[doc = "Bit 19 - Falling edge enabled 19"] + #[inline(always)] + #[must_use] + pub fn fen19(&mut self) -> FEN19_W<19> { + FEN19_W::new(self) + } + #[doc = "Bit 20 - Falling edge enabled 20"] + #[inline(always)] + #[must_use] + pub fn fen20(&mut self) -> FEN20_W<20> { + FEN20_W::new(self) + } + #[doc = "Bit 21 - Falling edge enabled 21"] + #[inline(always)] + #[must_use] + pub fn fen21(&mut self) -> FEN21_W<21> { + FEN21_W::new(self) + } + #[doc = "Bit 22 - Falling edge enabled 22"] + #[inline(always)] + #[must_use] + pub fn fen22(&mut self) -> FEN22_W<22> { + FEN22_W::new(self) + } + #[doc = "Bit 23 - Falling edge enabled 23"] + #[inline(always)] + #[must_use] + pub fn fen23(&mut self) -> FEN23_W<23> { + FEN23_W::new(self) + } + #[doc = "Bit 24 - Falling edge enabled 24"] + #[inline(always)] + #[must_use] + pub fn fen24(&mut self) -> FEN24_W<24> { + FEN24_W::new(self) + } + #[doc = "Bit 25 - Falling edge enabled 25"] + #[inline(always)] + #[must_use] + pub fn fen25(&mut self) -> FEN25_W<25> { + FEN25_W::new(self) + } + #[doc = "Bit 26 - Falling edge enabled 26"] + #[inline(always)] + #[must_use] + pub fn fen26(&mut self) -> FEN26_W<26> { + FEN26_W::new(self) + } + #[doc = "Bit 27 - Falling edge enabled 27"] + #[inline(always)] + #[must_use] + pub fn fen27(&mut self) -> FEN27_W<27> { + FEN27_W::new(self) + } + #[doc = "Bit 28 - Falling edge enabled 28"] + #[inline(always)] + #[must_use] + pub fn fen28(&mut self) -> FEN28_W<28> { + FEN28_W::new(self) + } + #[doc = "Bit 29 - Falling edge enabled 29"] + #[inline(always)] + #[must_use] + pub fn fen29(&mut self) -> FEN29_W<29> { + FEN29_W::new(self) + } + #[doc = "Bit 30 - Falling edge enabled 30"] + #[inline(always)] + #[must_use] + pub fn fen30(&mut self) -> FEN30_W<30> { + FEN30_W::new(self) + } + #[doc = "Bit 31 - Falling edge enabled 31"] + #[inline(always)] + #[must_use] + pub fn fen31(&mut self) -> FEN31_W<31> { + FEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen0](index.html) module"] +pub struct GPFEN0_SPEC; +impl crate::RegisterSpec for GPFEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfen0::R](R) reader structure"] +impl crate::Readable for GPFEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfen0::W](W) writer structure"] +impl crate::Writable for GPFEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfen1.rs b/crates/bcm2835-lpa/src/gpio/gpfen1.rs new file mode 100644 index 0000000..4e4498a --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPFEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FEN32` reader - Falling edge enabled 32"] +pub type FEN32_R = crate::BitReader; +#[doc = "Field `FEN32` writer - Falling edge enabled 32"] +pub type FEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN33` reader - Falling edge enabled 33"] +pub type FEN33_R = crate::BitReader; +#[doc = "Field `FEN33` writer - Falling edge enabled 33"] +pub type FEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN34` reader - Falling edge enabled 34"] +pub type FEN34_R = crate::BitReader; +#[doc = "Field `FEN34` writer - Falling edge enabled 34"] +pub type FEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN35` reader - Falling edge enabled 35"] +pub type FEN35_R = crate::BitReader; +#[doc = "Field `FEN35` writer - Falling edge enabled 35"] +pub type FEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN36` reader - Falling edge enabled 36"] +pub type FEN36_R = crate::BitReader; +#[doc = "Field `FEN36` writer - Falling edge enabled 36"] +pub type FEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN37` reader - Falling edge enabled 37"] +pub type FEN37_R = crate::BitReader; +#[doc = "Field `FEN37` writer - Falling edge enabled 37"] +pub type FEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN38` reader - Falling edge enabled 38"] +pub type FEN38_R = crate::BitReader; +#[doc = "Field `FEN38` writer - Falling edge enabled 38"] +pub type FEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN39` reader - Falling edge enabled 39"] +pub type FEN39_R = crate::BitReader; +#[doc = "Field `FEN39` writer - Falling edge enabled 39"] +pub type FEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN40` reader - Falling edge enabled 40"] +pub type FEN40_R = crate::BitReader; +#[doc = "Field `FEN40` writer - Falling edge enabled 40"] +pub type FEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN41` reader - Falling edge enabled 41"] +pub type FEN41_R = crate::BitReader; +#[doc = "Field `FEN41` writer - Falling edge enabled 41"] +pub type FEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN42` reader - Falling edge enabled 42"] +pub type FEN42_R = crate::BitReader; +#[doc = "Field `FEN42` writer - Falling edge enabled 42"] +pub type FEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN43` reader - Falling edge enabled 43"] +pub type FEN43_R = crate::BitReader; +#[doc = "Field `FEN43` writer - Falling edge enabled 43"] +pub type FEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN44` reader - Falling edge enabled 44"] +pub type FEN44_R = crate::BitReader; +#[doc = "Field `FEN44` writer - Falling edge enabled 44"] +pub type FEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN45` reader - Falling edge enabled 45"] +pub type FEN45_R = crate::BitReader; +#[doc = "Field `FEN45` writer - Falling edge enabled 45"] +pub type FEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN46` reader - Falling edge enabled 46"] +pub type FEN46_R = crate::BitReader; +#[doc = "Field `FEN46` writer - Falling edge enabled 46"] +pub type FEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN47` reader - Falling edge enabled 47"] +pub type FEN47_R = crate::BitReader; +#[doc = "Field `FEN47` writer - Falling edge enabled 47"] +pub type FEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN48` reader - Falling edge enabled 48"] +pub type FEN48_R = crate::BitReader; +#[doc = "Field `FEN48` writer - Falling edge enabled 48"] +pub type FEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN49` reader - Falling edge enabled 49"] +pub type FEN49_R = crate::BitReader; +#[doc = "Field `FEN49` writer - Falling edge enabled 49"] +pub type FEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN50` reader - Falling edge enabled 50"] +pub type FEN50_R = crate::BitReader; +#[doc = "Field `FEN50` writer - Falling edge enabled 50"] +pub type FEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN51` reader - Falling edge enabled 51"] +pub type FEN51_R = crate::BitReader; +#[doc = "Field `FEN51` writer - Falling edge enabled 51"] +pub type FEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN52` reader - Falling edge enabled 52"] +pub type FEN52_R = crate::BitReader; +#[doc = "Field `FEN52` writer - Falling edge enabled 52"] +pub type FEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN53` reader - Falling edge enabled 53"] +pub type FEN53_R = crate::BitReader; +#[doc = "Field `FEN53` writer - Falling edge enabled 53"] +pub type FEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Falling edge enabled 32"] + #[inline(always)] + pub fn fen32(&self) -> FEN32_R { + FEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling edge enabled 33"] + #[inline(always)] + pub fn fen33(&self) -> FEN33_R { + FEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Falling edge enabled 34"] + #[inline(always)] + pub fn fen34(&self) -> FEN34_R { + FEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Falling edge enabled 35"] + #[inline(always)] + pub fn fen35(&self) -> FEN35_R { + FEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling edge enabled 36"] + #[inline(always)] + pub fn fen36(&self) -> FEN36_R { + FEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Falling edge enabled 37"] + #[inline(always)] + pub fn fen37(&self) -> FEN37_R { + FEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Falling edge enabled 38"] + #[inline(always)] + pub fn fen38(&self) -> FEN38_R { + FEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling edge enabled 39"] + #[inline(always)] + pub fn fen39(&self) -> FEN39_R { + FEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Falling edge enabled 40"] + #[inline(always)] + pub fn fen40(&self) -> FEN40_R { + FEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Falling edge enabled 41"] + #[inline(always)] + pub fn fen41(&self) -> FEN41_R { + FEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling edge enabled 42"] + #[inline(always)] + pub fn fen42(&self) -> FEN42_R { + FEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Falling edge enabled 43"] + #[inline(always)] + pub fn fen43(&self) -> FEN43_R { + FEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Falling edge enabled 44"] + #[inline(always)] + pub fn fen44(&self) -> FEN44_R { + FEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Falling edge enabled 45"] + #[inline(always)] + pub fn fen45(&self) -> FEN45_R { + FEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Falling edge enabled 46"] + #[inline(always)] + pub fn fen46(&self) -> FEN46_R { + FEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Falling edge enabled 47"] + #[inline(always)] + pub fn fen47(&self) -> FEN47_R { + FEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Falling edge enabled 48"] + #[inline(always)] + pub fn fen48(&self) -> FEN48_R { + FEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Falling edge enabled 49"] + #[inline(always)] + pub fn fen49(&self) -> FEN49_R { + FEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Falling edge enabled 50"] + #[inline(always)] + pub fn fen50(&self) -> FEN50_R { + FEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Falling edge enabled 51"] + #[inline(always)] + pub fn fen51(&self) -> FEN51_R { + FEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Falling edge enabled 52"] + #[inline(always)] + pub fn fen52(&self) -> FEN52_R { + FEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Falling edge enabled 53"] + #[inline(always)] + pub fn fen53(&self) -> FEN53_R { + FEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Falling edge enabled 32"] + #[inline(always)] + #[must_use] + pub fn fen32(&mut self) -> FEN32_W<0> { + FEN32_W::new(self) + } + #[doc = "Bit 1 - Falling edge enabled 33"] + #[inline(always)] + #[must_use] + pub fn fen33(&mut self) -> FEN33_W<1> { + FEN33_W::new(self) + } + #[doc = "Bit 2 - Falling edge enabled 34"] + #[inline(always)] + #[must_use] + pub fn fen34(&mut self) -> FEN34_W<2> { + FEN34_W::new(self) + } + #[doc = "Bit 3 - Falling edge enabled 35"] + #[inline(always)] + #[must_use] + pub fn fen35(&mut self) -> FEN35_W<3> { + FEN35_W::new(self) + } + #[doc = "Bit 4 - Falling edge enabled 36"] + #[inline(always)] + #[must_use] + pub fn fen36(&mut self) -> FEN36_W<4> { + FEN36_W::new(self) + } + #[doc = "Bit 5 - Falling edge enabled 37"] + #[inline(always)] + #[must_use] + pub fn fen37(&mut self) -> FEN37_W<5> { + FEN37_W::new(self) + } + #[doc = "Bit 6 - Falling edge enabled 38"] + #[inline(always)] + #[must_use] + pub fn fen38(&mut self) -> FEN38_W<6> { + FEN38_W::new(self) + } + #[doc = "Bit 7 - Falling edge enabled 39"] + #[inline(always)] + #[must_use] + pub fn fen39(&mut self) -> FEN39_W<7> { + FEN39_W::new(self) + } + #[doc = "Bit 8 - Falling edge enabled 40"] + #[inline(always)] + #[must_use] + pub fn fen40(&mut self) -> FEN40_W<8> { + FEN40_W::new(self) + } + #[doc = "Bit 9 - Falling edge enabled 41"] + #[inline(always)] + #[must_use] + pub fn fen41(&mut self) -> FEN41_W<9> { + FEN41_W::new(self) + } + #[doc = "Bit 10 - Falling edge enabled 42"] + #[inline(always)] + #[must_use] + pub fn fen42(&mut self) -> FEN42_W<10> { + FEN42_W::new(self) + } + #[doc = "Bit 11 - Falling edge enabled 43"] + #[inline(always)] + #[must_use] + pub fn fen43(&mut self) -> FEN43_W<11> { + FEN43_W::new(self) + } + #[doc = "Bit 12 - Falling edge enabled 44"] + #[inline(always)] + #[must_use] + pub fn fen44(&mut self) -> FEN44_W<12> { + FEN44_W::new(self) + } + #[doc = "Bit 13 - Falling edge enabled 45"] + #[inline(always)] + #[must_use] + pub fn fen45(&mut self) -> FEN45_W<13> { + FEN45_W::new(self) + } + #[doc = "Bit 14 - Falling edge enabled 46"] + #[inline(always)] + #[must_use] + pub fn fen46(&mut self) -> FEN46_W<14> { + FEN46_W::new(self) + } + #[doc = "Bit 15 - Falling edge enabled 47"] + #[inline(always)] + #[must_use] + pub fn fen47(&mut self) -> FEN47_W<15> { + FEN47_W::new(self) + } + #[doc = "Bit 16 - Falling edge enabled 48"] + #[inline(always)] + #[must_use] + pub fn fen48(&mut self) -> FEN48_W<16> { + FEN48_W::new(self) + } + #[doc = "Bit 17 - Falling edge enabled 49"] + #[inline(always)] + #[must_use] + pub fn fen49(&mut self) -> FEN49_W<17> { + FEN49_W::new(self) + } + #[doc = "Bit 18 - Falling edge enabled 50"] + #[inline(always)] + #[must_use] + pub fn fen50(&mut self) -> FEN50_W<18> { + FEN50_W::new(self) + } + #[doc = "Bit 19 - Falling edge enabled 51"] + #[inline(always)] + #[must_use] + pub fn fen51(&mut self) -> FEN51_W<19> { + FEN51_W::new(self) + } + #[doc = "Bit 20 - Falling edge enabled 52"] + #[inline(always)] + #[must_use] + pub fn fen52(&mut self) -> FEN52_W<20> { + FEN52_W::new(self) + } + #[doc = "Bit 21 - Falling edge enabled 53"] + #[inline(always)] + #[must_use] + pub fn fen53(&mut self) -> FEN53_W<21> { + FEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen1](index.html) module"] +pub struct GPFEN1_SPEC; +impl crate::RegisterSpec for GPFEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfen1::R](R) reader structure"] +impl crate::Readable for GPFEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfen1::W](W) writer structure"] +impl crate::Writable for GPFEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel0.rs b/crates/bcm2835-lpa/src/gpio/gpfsel0.rs new file mode 100644 index 0000000..4109144 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfsel0.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL0` reader - Function Select 0"] +pub type FSEL0_R = crate::FieldReader; +#[doc = "Function Select 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL0_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA0"] + SDA0 = 4, + #[doc = "5: Pin is connected to SA5"] + SA5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL0_A) -> Self { + variant as _ + } +} +impl FSEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL0_A { + match self.bits { + 0 => FSEL0_A::INPUT, + 1 => FSEL0_A::OUTPUT, + 4 => FSEL0_A::SDA0, + 5 => FSEL0_A::SA5, + 6 => FSEL0_A::RESERVED2, + 7 => FSEL0_A::RESERVED3, + 3 => FSEL0_A::RESERVED4, + 2 => FSEL0_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL0_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL0_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL0_A::SDA0 + } + #[doc = "Checks if the value of the field is `SA5`"] + #[inline(always)] + pub fn is_sa5(&self) -> bool { + *self == FSEL0_A::SA5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL0_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL0_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL0_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL0_A::RESERVED5 + } +} +#[doc = "Field `FSEL0` writer - Function Select 0"] +pub type FSEL0_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL0_A, 3, O>; +impl<'a, const O: u8> FSEL0_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL0_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL0_A::OUTPUT) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL0_A::SDA0) + } + #[doc = "Pin is connected to SA5"] + #[inline(always)] + pub fn sa5(self) -> &'a mut W { + self.variant(FSEL0_A::SA5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED5) + } +} +#[doc = "Field `FSEL1` reader - Function Select 1"] +pub type FSEL1_R = crate::FieldReader; +#[doc = "Function Select 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL1_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL0"] + SCL0 = 4, + #[doc = "5: Pin is connected to SA4"] + SA4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL1_A) -> Self { + variant as _ + } +} +impl FSEL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL1_A { + match self.bits { + 0 => FSEL1_A::INPUT, + 1 => FSEL1_A::OUTPUT, + 4 => FSEL1_A::SCL0, + 5 => FSEL1_A::SA4, + 6 => FSEL1_A::RESERVED2, + 7 => FSEL1_A::RESERVED3, + 3 => FSEL1_A::RESERVED4, + 2 => FSEL1_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL1_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL1_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL1_A::SCL0 + } + #[doc = "Checks if the value of the field is `SA4`"] + #[inline(always)] + pub fn is_sa4(&self) -> bool { + *self == FSEL1_A::SA4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL1_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL1_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL1_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL1_A::RESERVED5 + } +} +#[doc = "Field `FSEL1` writer - Function Select 1"] +pub type FSEL1_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL1_A, 3, O>; +impl<'a, const O: u8> FSEL1_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL1_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL1_A::OUTPUT) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL1_A::SCL0) + } + #[doc = "Pin is connected to SA4"] + #[inline(always)] + pub fn sa4(self) -> &'a mut W { + self.variant(FSEL1_A::SA4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED5) + } +} +#[doc = "Field `FSEL2` reader - Function Select 2"] +pub type FSEL2_R = crate::FieldReader; +#[doc = "Function Select 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL2_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA1"] + SDA1 = 4, + #[doc = "5: Pin is connected to SA3"] + SA3 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL2_A) -> Self { + variant as _ + } +} +impl FSEL2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL2_A { + match self.bits { + 0 => FSEL2_A::INPUT, + 1 => FSEL2_A::OUTPUT, + 4 => FSEL2_A::SDA1, + 5 => FSEL2_A::SA3, + 6 => FSEL2_A::RESERVED2, + 7 => FSEL2_A::RESERVED3, + 3 => FSEL2_A::RESERVED4, + 2 => FSEL2_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL2_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL2_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA1`"] + #[inline(always)] + pub fn is_sda1(&self) -> bool { + *self == FSEL2_A::SDA1 + } + #[doc = "Checks if the value of the field is `SA3`"] + #[inline(always)] + pub fn is_sa3(&self) -> bool { + *self == FSEL2_A::SA3 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL2_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL2_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL2_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL2_A::RESERVED5 + } +} +#[doc = "Field `FSEL2` writer - Function Select 2"] +pub type FSEL2_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL2_A, 3, O>; +impl<'a, const O: u8> FSEL2_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL2_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL2_A::OUTPUT) + } + #[doc = "Pin is connected to SDA1"] + #[inline(always)] + pub fn sda1(self) -> &'a mut W { + self.variant(FSEL2_A::SDA1) + } + #[doc = "Pin is connected to SA3"] + #[inline(always)] + pub fn sa3(self) -> &'a mut W { + self.variant(FSEL2_A::SA3) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED5) + } +} +#[doc = "Field `FSEL3` reader - Function Select 3"] +pub type FSEL3_R = crate::FieldReader; +#[doc = "Function Select 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL3_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL1"] + SCL1 = 4, + #[doc = "5: Pin is connected to SA2"] + SA2 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL3_A) -> Self { + variant as _ + } +} +impl FSEL3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL3_A { + match self.bits { + 0 => FSEL3_A::INPUT, + 1 => FSEL3_A::OUTPUT, + 4 => FSEL3_A::SCL1, + 5 => FSEL3_A::SA2, + 6 => FSEL3_A::RESERVED2, + 7 => FSEL3_A::RESERVED3, + 3 => FSEL3_A::RESERVED4, + 2 => FSEL3_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL3_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL3_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL1`"] + #[inline(always)] + pub fn is_scl1(&self) -> bool { + *self == FSEL3_A::SCL1 + } + #[doc = "Checks if the value of the field is `SA2`"] + #[inline(always)] + pub fn is_sa2(&self) -> bool { + *self == FSEL3_A::SA2 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL3_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL3_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL3_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL3_A::RESERVED5 + } +} +#[doc = "Field `FSEL3` writer - Function Select 3"] +pub type FSEL3_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL3_A, 3, O>; +impl<'a, const O: u8> FSEL3_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL3_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL3_A::OUTPUT) + } + #[doc = "Pin is connected to SCL1"] + #[inline(always)] + pub fn scl1(self) -> &'a mut W { + self.variant(FSEL3_A::SCL1) + } + #[doc = "Pin is connected to SA2"] + #[inline(always)] + pub fn sa2(self) -> &'a mut W { + self.variant(FSEL3_A::SA2) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED5) + } +} +#[doc = "Field `FSEL4` reader - Function Select 4"] +pub type FSEL4_R = crate::FieldReader; +#[doc = "Function Select 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL4_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SA1"] + SA1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TDI"] + ARM_TDI = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL4_A) -> Self { + variant as _ + } +} +impl FSEL4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL4_A { + match self.bits { + 0 => FSEL4_A::INPUT, + 1 => FSEL4_A::OUTPUT, + 4 => FSEL4_A::GPCLK0, + 5 => FSEL4_A::SA1, + 6 => FSEL4_A::RESERVED2, + 7 => FSEL4_A::RESERVED3, + 3 => FSEL4_A::RESERVED4, + 2 => FSEL4_A::ARM_TDI, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL4_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL4_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL4_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SA1`"] + #[inline(always)] + pub fn is_sa1(&self) -> bool { + *self == FSEL4_A::SA1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL4_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL4_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL4_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[inline(always)] + pub fn is_arm_tdi(&self) -> bool { + *self == FSEL4_A::ARM_TDI + } +} +#[doc = "Field `FSEL4` writer - Function Select 4"] +pub type FSEL4_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL4_A, 3, O>; +impl<'a, const O: u8> FSEL4_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL4_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL4_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL4_A::GPCLK0) + } + #[doc = "Pin is connected to SA1"] + #[inline(always)] + pub fn sa1(self) -> &'a mut W { + self.variant(FSEL4_A::SA1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL4_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL4_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL4_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TDI"] + #[inline(always)] + pub fn arm_tdi(self) -> &'a mut W { + self.variant(FSEL4_A::ARM_TDI) + } +} +#[doc = "Field `FSEL5` reader - Function Select 5"] +pub type FSEL5_R = crate::FieldReader; +#[doc = "Function Select 5"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL5_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SA0"] + SA0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TDO"] + ARM_TDO = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL5_A) -> Self { + variant as _ + } +} +impl FSEL5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL5_A { + match self.bits { + 0 => FSEL5_A::INPUT, + 1 => FSEL5_A::OUTPUT, + 4 => FSEL5_A::GPCLK1, + 5 => FSEL5_A::SA0, + 6 => FSEL5_A::RESERVED2, + 7 => FSEL5_A::RESERVED3, + 3 => FSEL5_A::RESERVED4, + 2 => FSEL5_A::ARM_TDO, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL5_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL5_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL5_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SA0`"] + #[inline(always)] + pub fn is_sa0(&self) -> bool { + *self == FSEL5_A::SA0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL5_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL5_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL5_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[inline(always)] + pub fn is_arm_tdo(&self) -> bool { + *self == FSEL5_A::ARM_TDO + } +} +#[doc = "Field `FSEL5` writer - Function Select 5"] +pub type FSEL5_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL5_A, 3, O>; +impl<'a, const O: u8> FSEL5_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL5_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL5_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL5_A::GPCLK1) + } + #[doc = "Pin is connected to SA0"] + #[inline(always)] + pub fn sa0(self) -> &'a mut W { + self.variant(FSEL5_A::SA0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL5_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL5_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL5_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TDO"] + #[inline(always)] + pub fn arm_tdo(self) -> &'a mut W { + self.variant(FSEL5_A::ARM_TDO) + } +} +#[doc = "Field `FSEL6` reader - Function Select 6"] +pub type FSEL6_R = crate::FieldReader; +#[doc = "Function Select 6"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL6_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK2"] + GPCLK2 = 4, + #[doc = "5: Pin is connected to SOE_N"] + SOE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_RTCK"] + ARM_RTCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL6_A) -> Self { + variant as _ + } +} +impl FSEL6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL6_A { + match self.bits { + 0 => FSEL6_A::INPUT, + 1 => FSEL6_A::OUTPUT, + 4 => FSEL6_A::GPCLK2, + 5 => FSEL6_A::SOE_N, + 6 => FSEL6_A::RESERVED2, + 7 => FSEL6_A::RESERVED3, + 3 => FSEL6_A::RESERVED4, + 2 => FSEL6_A::ARM_RTCK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL6_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL6_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK2`"] + #[inline(always)] + pub fn is_gpclk2(&self) -> bool { + *self == FSEL6_A::GPCLK2 + } + #[doc = "Checks if the value of the field is `SOE_N`"] + #[inline(always)] + pub fn is_soe_n(&self) -> bool { + *self == FSEL6_A::SOE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL6_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL6_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL6_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[inline(always)] + pub fn is_arm_rtck(&self) -> bool { + *self == FSEL6_A::ARM_RTCK + } +} +#[doc = "Field `FSEL6` writer - Function Select 6"] +pub type FSEL6_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL6_A, 3, O>; +impl<'a, const O: u8> FSEL6_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL6_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL6_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK2"] + #[inline(always)] + pub fn gpclk2(self) -> &'a mut W { + self.variant(FSEL6_A::GPCLK2) + } + #[doc = "Pin is connected to SOE_N"] + #[inline(always)] + pub fn soe_n(self) -> &'a mut W { + self.variant(FSEL6_A::SOE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL6_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL6_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL6_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_RTCK"] + #[inline(always)] + pub fn arm_rtck(self) -> &'a mut W { + self.variant(FSEL6_A::ARM_RTCK) + } +} +#[doc = "Field `FSEL7` reader - Function Select 7"] +pub type FSEL7_R = crate::FieldReader; +#[doc = "Function Select 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL7_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE1_N"] + SPI0_CE1_N = 4, + #[doc = "5: Pin is connected to SWE_N"] + SWE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL7_A) -> Self { + variant as _ + } +} +impl FSEL7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL7_A { + match self.bits { + 0 => FSEL7_A::INPUT, + 1 => FSEL7_A::OUTPUT, + 4 => FSEL7_A::SPI0_CE1_N, + 5 => FSEL7_A::SWE_N, + 6 => FSEL7_A::RESERVED2, + 7 => FSEL7_A::RESERVED3, + 3 => FSEL7_A::RESERVED4, + 2 => FSEL7_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL7_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL7_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[inline(always)] + pub fn is_spi0_ce1_n(&self) -> bool { + *self == FSEL7_A::SPI0_CE1_N + } + #[doc = "Checks if the value of the field is `SWE_N`"] + #[inline(always)] + pub fn is_swe_n(&self) -> bool { + *self == FSEL7_A::SWE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL7_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL7_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL7_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL7_A::RESERVED5 + } +} +#[doc = "Field `FSEL7` writer - Function Select 7"] +pub type FSEL7_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL7_A, 3, O>; +impl<'a, const O: u8> FSEL7_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL7_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL7_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE1_N"] + #[inline(always)] + pub fn spi0_ce1_n(self) -> &'a mut W { + self.variant(FSEL7_A::SPI0_CE1_N) + } + #[doc = "Pin is connected to SWE_N"] + #[inline(always)] + pub fn swe_n(self) -> &'a mut W { + self.variant(FSEL7_A::SWE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED5) + } +} +#[doc = "Field `FSEL8` reader - Function Select 8"] +pub type FSEL8_R = crate::FieldReader; +#[doc = "Function Select 8"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL8_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE0_N"] + SPI0_CE0_N = 4, + #[doc = "5: Pin is connected to SD0"] + SD0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL8_A) -> Self { + variant as _ + } +} +impl FSEL8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL8_A { + match self.bits { + 0 => FSEL8_A::INPUT, + 1 => FSEL8_A::OUTPUT, + 4 => FSEL8_A::SPI0_CE0_N, + 5 => FSEL8_A::SD0, + 6 => FSEL8_A::RESERVED2, + 7 => FSEL8_A::RESERVED3, + 3 => FSEL8_A::RESERVED4, + 2 => FSEL8_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL8_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL8_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[inline(always)] + pub fn is_spi0_ce0_n(&self) -> bool { + *self == FSEL8_A::SPI0_CE0_N + } + #[doc = "Checks if the value of the field is `SD0`"] + #[inline(always)] + pub fn is_sd0(&self) -> bool { + *self == FSEL8_A::SD0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL8_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL8_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL8_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL8_A::RESERVED5 + } +} +#[doc = "Field `FSEL8` writer - Function Select 8"] +pub type FSEL8_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL8_A, 3, O>; +impl<'a, const O: u8> FSEL8_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL8_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL8_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE0_N"] + #[inline(always)] + pub fn spi0_ce0_n(self) -> &'a mut W { + self.variant(FSEL8_A::SPI0_CE0_N) + } + #[doc = "Pin is connected to SD0"] + #[inline(always)] + pub fn sd0(self) -> &'a mut W { + self.variant(FSEL8_A::SD0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED5) + } +} +#[doc = "Field `FSEL9` reader - Function Select 9"] +pub type FSEL9_R = crate::FieldReader; +#[doc = "Function Select 9"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL9_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MISO"] + SPI0_MISO = 4, + #[doc = "5: Pin is connected to SD1"] + SD1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL9_A) -> Self { + variant as _ + } +} +impl FSEL9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL9_A { + match self.bits { + 0 => FSEL9_A::INPUT, + 1 => FSEL9_A::OUTPUT, + 4 => FSEL9_A::SPI0_MISO, + 5 => FSEL9_A::SD1, + 6 => FSEL9_A::RESERVED2, + 7 => FSEL9_A::RESERVED3, + 3 => FSEL9_A::RESERVED4, + 2 => FSEL9_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL9_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL9_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[inline(always)] + pub fn is_spi0_miso(&self) -> bool { + *self == FSEL9_A::SPI0_MISO + } + #[doc = "Checks if the value of the field is `SD1`"] + #[inline(always)] + pub fn is_sd1(&self) -> bool { + *self == FSEL9_A::SD1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL9_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL9_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL9_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL9_A::RESERVED5 + } +} +#[doc = "Field `FSEL9` writer - Function Select 9"] +pub type FSEL9_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL9_A, 3, O>; +impl<'a, const O: u8> FSEL9_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL9_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL9_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MISO"] + #[inline(always)] + pub fn spi0_miso(self) -> &'a mut W { + self.variant(FSEL9_A::SPI0_MISO) + } + #[doc = "Pin is connected to SD1"] + #[inline(always)] + pub fn sd1(self) -> &'a mut W { + self.variant(FSEL9_A::SD1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 0"] + #[inline(always)] + pub fn fsel0(&self) -> FSEL0_R { + FSEL0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 1"] + #[inline(always)] + pub fn fsel1(&self) -> FSEL1_R { + FSEL1_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 2"] + #[inline(always)] + pub fn fsel2(&self) -> FSEL2_R { + FSEL2_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 3"] + #[inline(always)] + pub fn fsel3(&self) -> FSEL3_R { + FSEL3_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 4"] + #[inline(always)] + pub fn fsel4(&self) -> FSEL4_R { + FSEL4_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 5"] + #[inline(always)] + pub fn fsel5(&self) -> FSEL5_R { + FSEL5_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 6"] + #[inline(always)] + pub fn fsel6(&self) -> FSEL6_R { + FSEL6_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 7"] + #[inline(always)] + pub fn fsel7(&self) -> FSEL7_R { + FSEL7_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 8"] + #[inline(always)] + pub fn fsel8(&self) -> FSEL8_R { + FSEL8_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 9"] + #[inline(always)] + pub fn fsel9(&self) -> FSEL9_R { + FSEL9_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 0"] + #[inline(always)] + #[must_use] + pub fn fsel0(&mut self) -> FSEL0_W<0> { + FSEL0_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 1"] + #[inline(always)] + #[must_use] + pub fn fsel1(&mut self) -> FSEL1_W<3> { + FSEL1_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 2"] + #[inline(always)] + #[must_use] + pub fn fsel2(&mut self) -> FSEL2_W<6> { + FSEL2_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 3"] + #[inline(always)] + #[must_use] + pub fn fsel3(&mut self) -> FSEL3_W<9> { + FSEL3_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 4"] + #[inline(always)] + #[must_use] + pub fn fsel4(&mut self) -> FSEL4_W<12> { + FSEL4_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 5"] + #[inline(always)] + #[must_use] + pub fn fsel5(&mut self) -> FSEL5_W<15> { + FSEL5_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 6"] + #[inline(always)] + #[must_use] + pub fn fsel6(&mut self) -> FSEL6_W<18> { + FSEL6_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 7"] + #[inline(always)] + #[must_use] + pub fn fsel7(&mut self) -> FSEL7_W<21> { + FSEL7_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 8"] + #[inline(always)] + #[must_use] + pub fn fsel8(&mut self) -> FSEL8_W<24> { + FSEL8_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 9"] + #[inline(always)] + #[must_use] + pub fn fsel9(&mut self) -> FSEL9_W<27> { + FSEL9_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel0](index.html) module"] +pub struct GPFSEL0_SPEC; +impl crate::RegisterSpec for GPFSEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel0::R](R) reader structure"] +impl crate::Readable for GPFSEL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel0::W](W) writer structure"] +impl crate::Writable for GPFSEL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel1.rs b/crates/bcm2835-lpa/src/gpio/gpfsel1.rs new file mode 100644 index 0000000..170dd75 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfsel1.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL10` reader - Function Select 10"] +pub type FSEL10_R = crate::FieldReader; +#[doc = "Function Select 10"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL10_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MOSI"] + SPI0_MOSI = 4, + #[doc = "5: Pin is connected to SD2"] + SD2 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL10_A) -> Self { + variant as _ + } +} +impl FSEL10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL10_A { + match self.bits { + 0 => FSEL10_A::INPUT, + 1 => FSEL10_A::OUTPUT, + 4 => FSEL10_A::SPI0_MOSI, + 5 => FSEL10_A::SD2, + 6 => FSEL10_A::RESERVED2, + 7 => FSEL10_A::RESERVED3, + 3 => FSEL10_A::RESERVED4, + 2 => FSEL10_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL10_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL10_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[inline(always)] + pub fn is_spi0_mosi(&self) -> bool { + *self == FSEL10_A::SPI0_MOSI + } + #[doc = "Checks if the value of the field is `SD2`"] + #[inline(always)] + pub fn is_sd2(&self) -> bool { + *self == FSEL10_A::SD2 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL10_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL10_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL10_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL10_A::RESERVED5 + } +} +#[doc = "Field `FSEL10` writer - Function Select 10"] +pub type FSEL10_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL10_A, 3, O>; +impl<'a, const O: u8> FSEL10_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL10_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL10_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MOSI"] + #[inline(always)] + pub fn spi0_mosi(self) -> &'a mut W { + self.variant(FSEL10_A::SPI0_MOSI) + } + #[doc = "Pin is connected to SD2"] + #[inline(always)] + pub fn sd2(self) -> &'a mut W { + self.variant(FSEL10_A::SD2) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED5) + } +} +#[doc = "Field `FSEL11` reader - Function Select 11"] +pub type FSEL11_R = crate::FieldReader; +#[doc = "Function Select 11"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL11_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_SCLK"] + SPI0_SCLK = 4, + #[doc = "5: Pin is connected to SD3"] + SD3 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL11_A) -> Self { + variant as _ + } +} +impl FSEL11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL11_A { + match self.bits { + 0 => FSEL11_A::INPUT, + 1 => FSEL11_A::OUTPUT, + 4 => FSEL11_A::SPI0_SCLK, + 5 => FSEL11_A::SD3, + 6 => FSEL11_A::RESERVED2, + 7 => FSEL11_A::RESERVED3, + 3 => FSEL11_A::RESERVED4, + 2 => FSEL11_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL11_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL11_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[inline(always)] + pub fn is_spi0_sclk(&self) -> bool { + *self == FSEL11_A::SPI0_SCLK + } + #[doc = "Checks if the value of the field is `SD3`"] + #[inline(always)] + pub fn is_sd3(&self) -> bool { + *self == FSEL11_A::SD3 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL11_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL11_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL11_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL11_A::RESERVED5 + } +} +#[doc = "Field `FSEL11` writer - Function Select 11"] +pub type FSEL11_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL11_A, 3, O>; +impl<'a, const O: u8> FSEL11_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL11_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL11_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_SCLK"] + #[inline(always)] + pub fn spi0_sclk(self) -> &'a mut W { + self.variant(FSEL11_A::SPI0_SCLK) + } + #[doc = "Pin is connected to SD3"] + #[inline(always)] + pub fn sd3(self) -> &'a mut W { + self.variant(FSEL11_A::SD3) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED5) + } +} +#[doc = "Field `FSEL12` reader - Function Select 12"] +pub type FSEL12_R = crate::FieldReader; +#[doc = "Function Select 12"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL12_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_0"] + PWM0_0 = 4, + #[doc = "5: Pin is connected to SD4"] + SD4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TMS"] + ARM_TMS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL12_A) -> Self { + variant as _ + } +} +impl FSEL12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL12_A { + match self.bits { + 0 => FSEL12_A::INPUT, + 1 => FSEL12_A::OUTPUT, + 4 => FSEL12_A::PWM0_0, + 5 => FSEL12_A::SD4, + 6 => FSEL12_A::RESERVED2, + 7 => FSEL12_A::RESERVED3, + 3 => FSEL12_A::RESERVED4, + 2 => FSEL12_A::ARM_TMS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL12_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL12_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL12_A::PWM0_0 + } + #[doc = "Checks if the value of the field is `SD4`"] + #[inline(always)] + pub fn is_sd4(&self) -> bool { + *self == FSEL12_A::SD4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL12_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL12_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL12_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[inline(always)] + pub fn is_arm_tms(&self) -> bool { + *self == FSEL12_A::ARM_TMS + } +} +#[doc = "Field `FSEL12` writer - Function Select 12"] +pub type FSEL12_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL12_A, 3, O>; +impl<'a, const O: u8> FSEL12_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL12_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL12_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL12_A::PWM0_0) + } + #[doc = "Pin is connected to SD4"] + #[inline(always)] + pub fn sd4(self) -> &'a mut W { + self.variant(FSEL12_A::SD4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL12_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL12_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL12_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TMS"] + #[inline(always)] + pub fn arm_tms(self) -> &'a mut W { + self.variant(FSEL12_A::ARM_TMS) + } +} +#[doc = "Field `FSEL13` reader - Function Select 13"] +pub type FSEL13_R = crate::FieldReader; +#[doc = "Function Select 13"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL13_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SD5"] + SD5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TCK"] + ARM_TCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL13_A) -> Self { + variant as _ + } +} +impl FSEL13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL13_A { + match self.bits { + 0 => FSEL13_A::INPUT, + 1 => FSEL13_A::OUTPUT, + 4 => FSEL13_A::PWM0_1, + 5 => FSEL13_A::SD5, + 6 => FSEL13_A::RESERVED2, + 7 => FSEL13_A::RESERVED3, + 3 => FSEL13_A::RESERVED4, + 2 => FSEL13_A::ARM_TCK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL13_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL13_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL13_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SD5`"] + #[inline(always)] + pub fn is_sd5(&self) -> bool { + *self == FSEL13_A::SD5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL13_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL13_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL13_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[inline(always)] + pub fn is_arm_tck(&self) -> bool { + *self == FSEL13_A::ARM_TCK + } +} +#[doc = "Field `FSEL13` writer - Function Select 13"] +pub type FSEL13_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL13_A, 3, O>; +impl<'a, const O: u8> FSEL13_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL13_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL13_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL13_A::PWM0_1) + } + #[doc = "Pin is connected to SD5"] + #[inline(always)] + pub fn sd5(self) -> &'a mut W { + self.variant(FSEL13_A::SD5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL13_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL13_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL13_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TCK"] + #[inline(always)] + pub fn arm_tck(self) -> &'a mut W { + self.variant(FSEL13_A::ARM_TCK) + } +} +#[doc = "Field `FSEL14` reader - Function Select 14"] +pub type FSEL14_R = crate::FieldReader; +#[doc = "Function Select 14"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL14_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to TXD0"] + TXD0 = 4, + #[doc = "5: Pin is connected to SD6"] + SD6 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL14_A) -> Self { + variant as _ + } +} +impl FSEL14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL14_A { + match self.bits { + 0 => FSEL14_A::INPUT, + 1 => FSEL14_A::OUTPUT, + 4 => FSEL14_A::TXD0, + 5 => FSEL14_A::SD6, + 6 => FSEL14_A::RESERVED2, + 7 => FSEL14_A::RESERVED3, + 3 => FSEL14_A::RESERVED4, + 2 => FSEL14_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL14_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL14_A::OUTPUT + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL14_A::TXD0 + } + #[doc = "Checks if the value of the field is `SD6`"] + #[inline(always)] + pub fn is_sd6(&self) -> bool { + *self == FSEL14_A::SD6 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL14_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL14_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL14_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL14_A::TXD1 + } +} +#[doc = "Field `FSEL14` writer - Function Select 14"] +pub type FSEL14_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL14_A, 3, O>; +impl<'a, const O: u8> FSEL14_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL14_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL14_A::OUTPUT) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL14_A::TXD0) + } + #[doc = "Pin is connected to SD6"] + #[inline(always)] + pub fn sd6(self) -> &'a mut W { + self.variant(FSEL14_A::SD6) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL14_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL14_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL14_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL14_A::TXD1) + } +} +#[doc = "Field `FSEL15` reader - Function Select 15"] +pub type FSEL15_R = crate::FieldReader; +#[doc = "Function Select 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL15_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to RXD0"] + RXD0 = 4, + #[doc = "5: Pin is connected to SD7"] + SD7 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL15_A) -> Self { + variant as _ + } +} +impl FSEL15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL15_A { + match self.bits { + 0 => FSEL15_A::INPUT, + 1 => FSEL15_A::OUTPUT, + 4 => FSEL15_A::RXD0, + 5 => FSEL15_A::SD7, + 6 => FSEL15_A::RESERVED2, + 7 => FSEL15_A::RESERVED3, + 3 => FSEL15_A::RESERVED4, + 2 => FSEL15_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL15_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL15_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL15_A::RXD0 + } + #[doc = "Checks if the value of the field is `SD7`"] + #[inline(always)] + pub fn is_sd7(&self) -> bool { + *self == FSEL15_A::SD7 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL15_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL15_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL15_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL15_A::RXD1 + } +} +#[doc = "Field `FSEL15` writer - Function Select 15"] +pub type FSEL15_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL15_A, 3, O>; +impl<'a, const O: u8> FSEL15_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL15_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL15_A::OUTPUT) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL15_A::RXD0) + } + #[doc = "Pin is connected to SD7"] + #[inline(always)] + pub fn sd7(self) -> &'a mut W { + self.variant(FSEL15_A::SD7) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL15_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL15_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL15_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL15_A::RXD1) + } +} +#[doc = "Field `FSEL16` reader - Function Select 16"] +pub type FSEL16_R = crate::FieldReader; +#[doc = "Function Select 16"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL16_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD8"] + SD8 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to CTS0"] + CTS0 = 7, + #[doc = "3: Pin is connected to SPI1_CE2_N"] + SPI1_CE2_N = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL16_A) -> Self { + variant as _ + } +} +impl FSEL16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL16_A { + match self.bits { + 0 => FSEL16_A::INPUT, + 1 => FSEL16_A::OUTPUT, + 4 => FSEL16_A::RESERVED0, + 5 => FSEL16_A::SD8, + 6 => FSEL16_A::RESERVED2, + 7 => FSEL16_A::CTS0, + 3 => FSEL16_A::SPI1_CE2_N, + 2 => FSEL16_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL16_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL16_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL16_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD8`"] + #[inline(always)] + pub fn is_sd8(&self) -> bool { + *self == FSEL16_A::SD8 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL16_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL16_A::CTS0 + } + #[doc = "Checks if the value of the field is `SPI1_CE2_N`"] + #[inline(always)] + pub fn is_spi1_ce2_n(&self) -> bool { + *self == FSEL16_A::SPI1_CE2_N + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL16_A::CTS1 + } +} +#[doc = "Field `FSEL16` writer - Function Select 16"] +pub type FSEL16_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL16_A, 3, O>; +impl<'a, const O: u8> FSEL16_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL16_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL16_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL16_A::RESERVED0) + } + #[doc = "Pin is connected to SD8"] + #[inline(always)] + pub fn sd8(self) -> &'a mut W { + self.variant(FSEL16_A::SD8) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL16_A::RESERVED2) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL16_A::CTS0) + } + #[doc = "Pin is connected to SPI1_CE2_N"] + #[inline(always)] + pub fn spi1_ce2_n(self) -> &'a mut W { + self.variant(FSEL16_A::SPI1_CE2_N) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL16_A::CTS1) + } +} +#[doc = "Field `FSEL17` reader - Function Select 17"] +pub type FSEL17_R = crate::FieldReader; +#[doc = "Function Select 17"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL17_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD9"] + SD9 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to RTS0"] + RTS0 = 7, + #[doc = "3: Pin is connected to SPI1_CE1_N"] + SPI1_CE1_N = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL17_A) -> Self { + variant as _ + } +} +impl FSEL17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL17_A { + match self.bits { + 0 => FSEL17_A::INPUT, + 1 => FSEL17_A::OUTPUT, + 4 => FSEL17_A::RESERVED0, + 5 => FSEL17_A::SD9, + 6 => FSEL17_A::RESERVED2, + 7 => FSEL17_A::RTS0, + 3 => FSEL17_A::SPI1_CE1_N, + 2 => FSEL17_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL17_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL17_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL17_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD9`"] + #[inline(always)] + pub fn is_sd9(&self) -> bool { + *self == FSEL17_A::SD9 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL17_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL17_A::RTS0 + } + #[doc = "Checks if the value of the field is `SPI1_CE1_N`"] + #[inline(always)] + pub fn is_spi1_ce1_n(&self) -> bool { + *self == FSEL17_A::SPI1_CE1_N + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL17_A::RTS1 + } +} +#[doc = "Field `FSEL17` writer - Function Select 17"] +pub type FSEL17_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL17_A, 3, O>; +impl<'a, const O: u8> FSEL17_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL17_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL17_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL17_A::RESERVED0) + } + #[doc = "Pin is connected to SD9"] + #[inline(always)] + pub fn sd9(self) -> &'a mut W { + self.variant(FSEL17_A::SD9) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL17_A::RESERVED2) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL17_A::RTS0) + } + #[doc = "Pin is connected to SPI1_CE1_N"] + #[inline(always)] + pub fn spi1_ce1_n(self) -> &'a mut W { + self.variant(FSEL17_A::SPI1_CE1_N) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL17_A::RTS1) + } +} +#[doc = "Field `FSEL18` reader - Function Select 18"] +pub type FSEL18_R = crate::FieldReader; +#[doc = "Function Select 18"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL18_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_CLK"] + PCM_CLK = 4, + #[doc = "5: Pin is connected to SD10"] + SD10 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_CE0_N"] + SPI1_CE0_N = 3, + #[doc = "2: Pin is connected to PWM0_0"] + PWM0_0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL18_A) -> Self { + variant as _ + } +} +impl FSEL18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL18_A { + match self.bits { + 0 => FSEL18_A::INPUT, + 1 => FSEL18_A::OUTPUT, + 4 => FSEL18_A::PCM_CLK, + 5 => FSEL18_A::SD10, + 6 => FSEL18_A::RESERVED2, + 7 => FSEL18_A::RESERVED3, + 3 => FSEL18_A::SPI1_CE0_N, + 2 => FSEL18_A::PWM0_0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL18_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL18_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[inline(always)] + pub fn is_pcm_clk(&self) -> bool { + *self == FSEL18_A::PCM_CLK + } + #[doc = "Checks if the value of the field is `SD10`"] + #[inline(always)] + pub fn is_sd10(&self) -> bool { + *self == FSEL18_A::SD10 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL18_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL18_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_CE0_N`"] + #[inline(always)] + pub fn is_spi1_ce0_n(&self) -> bool { + *self == FSEL18_A::SPI1_CE0_N + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL18_A::PWM0_0 + } +} +#[doc = "Field `FSEL18` writer - Function Select 18"] +pub type FSEL18_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL18_A, 3, O>; +impl<'a, const O: u8> FSEL18_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL18_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL18_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_CLK"] + #[inline(always)] + pub fn pcm_clk(self) -> &'a mut W { + self.variant(FSEL18_A::PCM_CLK) + } + #[doc = "Pin is connected to SD10"] + #[inline(always)] + pub fn sd10(self) -> &'a mut W { + self.variant(FSEL18_A::SD10) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL18_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL18_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_CE0_N"] + #[inline(always)] + pub fn spi1_ce0_n(self) -> &'a mut W { + self.variant(FSEL18_A::SPI1_CE0_N) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL18_A::PWM0_0) + } +} +#[doc = "Field `FSEL19` reader - Function Select 19"] +pub type FSEL19_R = crate::FieldReader; +#[doc = "Function Select 19"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL19_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_FS"] + PCM_FS = 4, + #[doc = "5: Pin is connected to SD11"] + SD11 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_MISO"] + SPI1_MISO = 3, + #[doc = "2: Pin is connected to PWM0_1"] + PWM0_1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL19_A) -> Self { + variant as _ + } +} +impl FSEL19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL19_A { + match self.bits { + 0 => FSEL19_A::INPUT, + 1 => FSEL19_A::OUTPUT, + 4 => FSEL19_A::PCM_FS, + 5 => FSEL19_A::SD11, + 6 => FSEL19_A::RESERVED2, + 7 => FSEL19_A::RESERVED3, + 3 => FSEL19_A::SPI1_MISO, + 2 => FSEL19_A::PWM0_1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL19_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL19_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_FS`"] + #[inline(always)] + pub fn is_pcm_fs(&self) -> bool { + *self == FSEL19_A::PCM_FS + } + #[doc = "Checks if the value of the field is `SD11`"] + #[inline(always)] + pub fn is_sd11(&self) -> bool { + *self == FSEL19_A::SD11 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL19_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL19_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_MISO`"] + #[inline(always)] + pub fn is_spi1_miso(&self) -> bool { + *self == FSEL19_A::SPI1_MISO + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL19_A::PWM0_1 + } +} +#[doc = "Field `FSEL19` writer - Function Select 19"] +pub type FSEL19_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL19_A, 3, O>; +impl<'a, const O: u8> FSEL19_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL19_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL19_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_FS"] + #[inline(always)] + pub fn pcm_fs(self) -> &'a mut W { + self.variant(FSEL19_A::PCM_FS) + } + #[doc = "Pin is connected to SD11"] + #[inline(always)] + pub fn sd11(self) -> &'a mut W { + self.variant(FSEL19_A::SD11) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL19_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL19_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_MISO"] + #[inline(always)] + pub fn spi1_miso(self) -> &'a mut W { + self.variant(FSEL19_A::SPI1_MISO) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL19_A::PWM0_1) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 10"] + #[inline(always)] + pub fn fsel10(&self) -> FSEL10_R { + FSEL10_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 11"] + #[inline(always)] + pub fn fsel11(&self) -> FSEL11_R { + FSEL11_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 12"] + #[inline(always)] + pub fn fsel12(&self) -> FSEL12_R { + FSEL12_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 13"] + #[inline(always)] + pub fn fsel13(&self) -> FSEL13_R { + FSEL13_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 14"] + #[inline(always)] + pub fn fsel14(&self) -> FSEL14_R { + FSEL14_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 15"] + #[inline(always)] + pub fn fsel15(&self) -> FSEL15_R { + FSEL15_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 16"] + #[inline(always)] + pub fn fsel16(&self) -> FSEL16_R { + FSEL16_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 17"] + #[inline(always)] + pub fn fsel17(&self) -> FSEL17_R { + FSEL17_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 18"] + #[inline(always)] + pub fn fsel18(&self) -> FSEL18_R { + FSEL18_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 19"] + #[inline(always)] + pub fn fsel19(&self) -> FSEL19_R { + FSEL19_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 10"] + #[inline(always)] + #[must_use] + pub fn fsel10(&mut self) -> FSEL10_W<0> { + FSEL10_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 11"] + #[inline(always)] + #[must_use] + pub fn fsel11(&mut self) -> FSEL11_W<3> { + FSEL11_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 12"] + #[inline(always)] + #[must_use] + pub fn fsel12(&mut self) -> FSEL12_W<6> { + FSEL12_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 13"] + #[inline(always)] + #[must_use] + pub fn fsel13(&mut self) -> FSEL13_W<9> { + FSEL13_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 14"] + #[inline(always)] + #[must_use] + pub fn fsel14(&mut self) -> FSEL14_W<12> { + FSEL14_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 15"] + #[inline(always)] + #[must_use] + pub fn fsel15(&mut self) -> FSEL15_W<15> { + FSEL15_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 16"] + #[inline(always)] + #[must_use] + pub fn fsel16(&mut self) -> FSEL16_W<18> { + FSEL16_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 17"] + #[inline(always)] + #[must_use] + pub fn fsel17(&mut self) -> FSEL17_W<21> { + FSEL17_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 18"] + #[inline(always)] + #[must_use] + pub fn fsel18(&mut self) -> FSEL18_W<24> { + FSEL18_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 19"] + #[inline(always)] + #[must_use] + pub fn fsel19(&mut self) -> FSEL19_W<27> { + FSEL19_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel1](index.html) module"] +pub struct GPFSEL1_SPEC; +impl crate::RegisterSpec for GPFSEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel1::R](R) reader structure"] +impl crate::Readable for GPFSEL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel1::W](W) writer structure"] +impl crate::Writable for GPFSEL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel2.rs b/crates/bcm2835-lpa/src/gpio/gpfsel2.rs new file mode 100644 index 0000000..8bc92dc --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfsel2.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL20` reader - Function Select 20"] +pub type FSEL20_R = crate::FieldReader; +#[doc = "Function Select 20"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL20_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_DIN"] + PCM_DIN = 4, + #[doc = "5: Pin is connected to SD12"] + SD12 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_MOSI"] + SPI1_MOSI = 3, + #[doc = "2: Pin is connected to GPCLK0"] + GPCLK0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL20_A) -> Self { + variant as _ + } +} +impl FSEL20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL20_A { + match self.bits { + 0 => FSEL20_A::INPUT, + 1 => FSEL20_A::OUTPUT, + 4 => FSEL20_A::PCM_DIN, + 5 => FSEL20_A::SD12, + 6 => FSEL20_A::RESERVED2, + 7 => FSEL20_A::RESERVED3, + 3 => FSEL20_A::SPI1_MOSI, + 2 => FSEL20_A::GPCLK0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL20_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL20_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[inline(always)] + pub fn is_pcm_din(&self) -> bool { + *self == FSEL20_A::PCM_DIN + } + #[doc = "Checks if the value of the field is `SD12`"] + #[inline(always)] + pub fn is_sd12(&self) -> bool { + *self == FSEL20_A::SD12 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL20_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL20_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_MOSI`"] + #[inline(always)] + pub fn is_spi1_mosi(&self) -> bool { + *self == FSEL20_A::SPI1_MOSI + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL20_A::GPCLK0 + } +} +#[doc = "Field `FSEL20` writer - Function Select 20"] +pub type FSEL20_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL20_A, 3, O>; +impl<'a, const O: u8> FSEL20_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL20_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL20_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_DIN"] + #[inline(always)] + pub fn pcm_din(self) -> &'a mut W { + self.variant(FSEL20_A::PCM_DIN) + } + #[doc = "Pin is connected to SD12"] + #[inline(always)] + pub fn sd12(self) -> &'a mut W { + self.variant(FSEL20_A::SD12) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL20_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL20_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_MOSI"] + #[inline(always)] + pub fn spi1_mosi(self) -> &'a mut W { + self.variant(FSEL20_A::SPI1_MOSI) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL20_A::GPCLK0) + } +} +#[doc = "Field `FSEL21` reader - Function Select 21"] +pub type FSEL21_R = crate::FieldReader; +#[doc = "Function Select 21"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL21_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_DOUT"] + PCM_DOUT = 4, + #[doc = "5: Pin is connected to SD13"] + SD13 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_SCLK"] + SPI1_SCLK = 3, + #[doc = "2: Pin is connected to GPCLK1"] + GPCLK1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL21_A) -> Self { + variant as _ + } +} +impl FSEL21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL21_A { + match self.bits { + 0 => FSEL21_A::INPUT, + 1 => FSEL21_A::OUTPUT, + 4 => FSEL21_A::PCM_DOUT, + 5 => FSEL21_A::SD13, + 6 => FSEL21_A::RESERVED2, + 7 => FSEL21_A::RESERVED3, + 3 => FSEL21_A::SPI1_SCLK, + 2 => FSEL21_A::GPCLK1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL21_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL21_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[inline(always)] + pub fn is_pcm_dout(&self) -> bool { + *self == FSEL21_A::PCM_DOUT + } + #[doc = "Checks if the value of the field is `SD13`"] + #[inline(always)] + pub fn is_sd13(&self) -> bool { + *self == FSEL21_A::SD13 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL21_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL21_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_SCLK`"] + #[inline(always)] + pub fn is_spi1_sclk(&self) -> bool { + *self == FSEL21_A::SPI1_SCLK + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL21_A::GPCLK1 + } +} +#[doc = "Field `FSEL21` writer - Function Select 21"] +pub type FSEL21_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL21_A, 3, O>; +impl<'a, const O: u8> FSEL21_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL21_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL21_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_DOUT"] + #[inline(always)] + pub fn pcm_dout(self) -> &'a mut W { + self.variant(FSEL21_A::PCM_DOUT) + } + #[doc = "Pin is connected to SD13"] + #[inline(always)] + pub fn sd13(self) -> &'a mut W { + self.variant(FSEL21_A::SD13) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL21_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL21_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_SCLK"] + #[inline(always)] + pub fn spi1_sclk(self) -> &'a mut W { + self.variant(FSEL21_A::SPI1_SCLK) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL21_A::GPCLK1) + } +} +#[doc = "Field `FSEL22` reader - Function Select 22"] +pub type FSEL22_R = crate::FieldReader; +#[doc = "Function Select 22"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL22_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD14"] + SD14 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Pin is connected to ARM_TRST"] + ARM_TRST = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL22_A) -> Self { + variant as _ + } +} +impl FSEL22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL22_A { + match self.bits { + 0 => FSEL22_A::INPUT, + 1 => FSEL22_A::OUTPUT, + 4 => FSEL22_A::RESERVED0, + 5 => FSEL22_A::SD14, + 6 => FSEL22_A::RESERVED2, + 7 => FSEL22_A::SD1_CLK, + 3 => FSEL22_A::ARM_TRST, + 2 => FSEL22_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL22_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL22_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL22_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD14`"] + #[inline(always)] + pub fn is_sd14(&self) -> bool { + *self == FSEL22_A::SD14 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL22_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL22_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `ARM_TRST`"] + #[inline(always)] + pub fn is_arm_trst(&self) -> bool { + *self == FSEL22_A::ARM_TRST + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL22_A::RESERVED5 + } +} +#[doc = "Field `FSEL22` writer - Function Select 22"] +pub type FSEL22_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL22_A, 3, O>; +impl<'a, const O: u8> FSEL22_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL22_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL22_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL22_A::RESERVED0) + } + #[doc = "Pin is connected to SD14"] + #[inline(always)] + pub fn sd14(self) -> &'a mut W { + self.variant(FSEL22_A::SD14) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL22_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL22_A::SD1_CLK) + } + #[doc = "Pin is connected to ARM_TRST"] + #[inline(always)] + pub fn arm_trst(self) -> &'a mut W { + self.variant(FSEL22_A::ARM_TRST) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL22_A::RESERVED5) + } +} +#[doc = "Field `FSEL23` reader - Function Select 23"] +pub type FSEL23_R = crate::FieldReader; +#[doc = "Function Select 23"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL23_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD15"] + SD15 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Pin is connected to ARM_RTCK"] + ARM_RTCK = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL23_A) -> Self { + variant as _ + } +} +impl FSEL23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL23_A { + match self.bits { + 0 => FSEL23_A::INPUT, + 1 => FSEL23_A::OUTPUT, + 4 => FSEL23_A::RESERVED0, + 5 => FSEL23_A::SD15, + 6 => FSEL23_A::RESERVED2, + 7 => FSEL23_A::SD1_CMD, + 3 => FSEL23_A::ARM_RTCK, + 2 => FSEL23_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL23_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL23_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL23_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD15`"] + #[inline(always)] + pub fn is_sd15(&self) -> bool { + *self == FSEL23_A::SD15 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL23_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL23_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[inline(always)] + pub fn is_arm_rtck(&self) -> bool { + *self == FSEL23_A::ARM_RTCK + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL23_A::RESERVED5 + } +} +#[doc = "Field `FSEL23` writer - Function Select 23"] +pub type FSEL23_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL23_A, 3, O>; +impl<'a, const O: u8> FSEL23_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL23_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL23_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL23_A::RESERVED0) + } + #[doc = "Pin is connected to SD15"] + #[inline(always)] + pub fn sd15(self) -> &'a mut W { + self.variant(FSEL23_A::SD15) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL23_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL23_A::SD1_CMD) + } + #[doc = "Pin is connected to ARM_RTCK"] + #[inline(always)] + pub fn arm_rtck(self) -> &'a mut W { + self.variant(FSEL23_A::ARM_RTCK) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL23_A::RESERVED5) + } +} +#[doc = "Field `FSEL24` reader - Function Select 24"] +pub type FSEL24_R = crate::FieldReader; +#[doc = "Function Select 24"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL24_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD16"] + SD16 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Pin is connected to ARM_TDO"] + ARM_TDO = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL24_A) -> Self { + variant as _ + } +} +impl FSEL24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL24_A { + match self.bits { + 0 => FSEL24_A::INPUT, + 1 => FSEL24_A::OUTPUT, + 4 => FSEL24_A::RESERVED0, + 5 => FSEL24_A::SD16, + 6 => FSEL24_A::RESERVED2, + 7 => FSEL24_A::SD1_DAT0, + 3 => FSEL24_A::ARM_TDO, + 2 => FSEL24_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL24_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL24_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL24_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD16`"] + #[inline(always)] + pub fn is_sd16(&self) -> bool { + *self == FSEL24_A::SD16 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL24_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL24_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[inline(always)] + pub fn is_arm_tdo(&self) -> bool { + *self == FSEL24_A::ARM_TDO + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL24_A::RESERVED5 + } +} +#[doc = "Field `FSEL24` writer - Function Select 24"] +pub type FSEL24_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL24_A, 3, O>; +impl<'a, const O: u8> FSEL24_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL24_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL24_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL24_A::RESERVED0) + } + #[doc = "Pin is connected to SD16"] + #[inline(always)] + pub fn sd16(self) -> &'a mut W { + self.variant(FSEL24_A::SD16) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL24_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL24_A::SD1_DAT0) + } + #[doc = "Pin is connected to ARM_TDO"] + #[inline(always)] + pub fn arm_tdo(self) -> &'a mut W { + self.variant(FSEL24_A::ARM_TDO) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL24_A::RESERVED5) + } +} +#[doc = "Field `FSEL25` reader - Function Select 25"] +pub type FSEL25_R = crate::FieldReader; +#[doc = "Function Select 25"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL25_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD17"] + SD17 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Pin is connected to ARM_TCK"] + ARM_TCK = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL25_A) -> Self { + variant as _ + } +} +impl FSEL25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL25_A { + match self.bits { + 0 => FSEL25_A::INPUT, + 1 => FSEL25_A::OUTPUT, + 4 => FSEL25_A::RESERVED0, + 5 => FSEL25_A::SD17, + 6 => FSEL25_A::RESERVED2, + 7 => FSEL25_A::SD1_DAT1, + 3 => FSEL25_A::ARM_TCK, + 2 => FSEL25_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL25_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL25_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL25_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD17`"] + #[inline(always)] + pub fn is_sd17(&self) -> bool { + *self == FSEL25_A::SD17 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL25_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL25_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[inline(always)] + pub fn is_arm_tck(&self) -> bool { + *self == FSEL25_A::ARM_TCK + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL25_A::RESERVED5 + } +} +#[doc = "Field `FSEL25` writer - Function Select 25"] +pub type FSEL25_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL25_A, 3, O>; +impl<'a, const O: u8> FSEL25_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL25_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL25_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL25_A::RESERVED0) + } + #[doc = "Pin is connected to SD17"] + #[inline(always)] + pub fn sd17(self) -> &'a mut W { + self.variant(FSEL25_A::SD17) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL25_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL25_A::SD1_DAT1) + } + #[doc = "Pin is connected to ARM_TCK"] + #[inline(always)] + pub fn arm_tck(self) -> &'a mut W { + self.variant(FSEL25_A::ARM_TCK) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL25_A::RESERVED5) + } +} +#[doc = "Field `FSEL26` reader - Function Select 26"] +pub type FSEL26_R = crate::FieldReader; +#[doc = "Function Select 26"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL26_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Pin is connected to ARM_TDI"] + ARM_TDI = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL26_A) -> Self { + variant as _ + } +} +impl FSEL26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL26_A { + match self.bits { + 0 => FSEL26_A::INPUT, + 1 => FSEL26_A::OUTPUT, + 4 => FSEL26_A::RESERVED0, + 5 => FSEL26_A::RESERVED1, + 6 => FSEL26_A::RESERVED2, + 7 => FSEL26_A::SD1_DAT2, + 3 => FSEL26_A::ARM_TDI, + 2 => FSEL26_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL26_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL26_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL26_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL26_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL26_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL26_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[inline(always)] + pub fn is_arm_tdi(&self) -> bool { + *self == FSEL26_A::ARM_TDI + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL26_A::RESERVED5 + } +} +#[doc = "Field `FSEL26` writer - Function Select 26"] +pub type FSEL26_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL26_A, 3, O>; +impl<'a, const O: u8> FSEL26_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL26_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL26_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL26_A::SD1_DAT2) + } + #[doc = "Pin is connected to ARM_TDI"] + #[inline(always)] + pub fn arm_tdi(self) -> &'a mut W { + self.variant(FSEL26_A::ARM_TDI) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED5) + } +} +#[doc = "Field `FSEL27` reader - Function Select 27"] +pub type FSEL27_R = crate::FieldReader; +#[doc = "Function Select 27"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL27_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Pin is connected to ARM_TMS"] + ARM_TMS = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL27_A) -> Self { + variant as _ + } +} +impl FSEL27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL27_A { + match self.bits { + 0 => FSEL27_A::INPUT, + 1 => FSEL27_A::OUTPUT, + 4 => FSEL27_A::RESERVED0, + 5 => FSEL27_A::RESERVED1, + 6 => FSEL27_A::RESERVED2, + 7 => FSEL27_A::SD1_DAT3, + 3 => FSEL27_A::ARM_TMS, + 2 => FSEL27_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL27_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL27_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL27_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL27_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL27_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL27_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[inline(always)] + pub fn is_arm_tms(&self) -> bool { + *self == FSEL27_A::ARM_TMS + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL27_A::RESERVED5 + } +} +#[doc = "Field `FSEL27` writer - Function Select 27"] +pub type FSEL27_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL27_A, 3, O>; +impl<'a, const O: u8> FSEL27_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL27_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL27_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL27_A::SD1_DAT3) + } + #[doc = "Pin is connected to ARM_TMS"] + #[inline(always)] + pub fn arm_tms(self) -> &'a mut W { + self.variant(FSEL27_A::ARM_TMS) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED5) + } +} +#[doc = "Field `FSEL28` reader - Function Select 28"] +pub type FSEL28_R = crate::FieldReader; +#[doc = "Function Select 28"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL28_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA0"] + SDA0 = 4, + #[doc = "5: Pin is connected to SA5"] + SA5 = 5, + #[doc = "6: Pin is connected to PCM_CLK"] + PCM_CLK = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL28_A) -> Self { + variant as _ + } +} +impl FSEL28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL28_A { + match self.bits { + 0 => FSEL28_A::INPUT, + 1 => FSEL28_A::OUTPUT, + 4 => FSEL28_A::SDA0, + 5 => FSEL28_A::SA5, + 6 => FSEL28_A::PCM_CLK, + 7 => FSEL28_A::RESERVED3, + 3 => FSEL28_A::RESERVED4, + 2 => FSEL28_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL28_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL28_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL28_A::SDA0 + } + #[doc = "Checks if the value of the field is `SA5`"] + #[inline(always)] + pub fn is_sa5(&self) -> bool { + *self == FSEL28_A::SA5 + } + #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[inline(always)] + pub fn is_pcm_clk(&self) -> bool { + *self == FSEL28_A::PCM_CLK + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL28_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL28_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL28_A::RESERVED5 + } +} +#[doc = "Field `FSEL28` writer - Function Select 28"] +pub type FSEL28_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL28_A, 3, O>; +impl<'a, const O: u8> FSEL28_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL28_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL28_A::OUTPUT) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL28_A::SDA0) + } + #[doc = "Pin is connected to SA5"] + #[inline(always)] + pub fn sa5(self) -> &'a mut W { + self.variant(FSEL28_A::SA5) + } + #[doc = "Pin is connected to PCM_CLK"] + #[inline(always)] + pub fn pcm_clk(self) -> &'a mut W { + self.variant(FSEL28_A::PCM_CLK) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED5) + } +} +#[doc = "Field `FSEL29` reader - Function Select 29"] +pub type FSEL29_R = crate::FieldReader; +#[doc = "Function Select 29"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL29_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL0"] + SCL0 = 4, + #[doc = "5: Pin is connected to SA4"] + SA4 = 5, + #[doc = "6: Pin is connected to PCM_FS"] + PCM_FS = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL29_A) -> Self { + variant as _ + } +} +impl FSEL29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL29_A { + match self.bits { + 0 => FSEL29_A::INPUT, + 1 => FSEL29_A::OUTPUT, + 4 => FSEL29_A::SCL0, + 5 => FSEL29_A::SA4, + 6 => FSEL29_A::PCM_FS, + 7 => FSEL29_A::RESERVED3, + 3 => FSEL29_A::RESERVED4, + 2 => FSEL29_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL29_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL29_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL29_A::SCL0 + } + #[doc = "Checks if the value of the field is `SA4`"] + #[inline(always)] + pub fn is_sa4(&self) -> bool { + *self == FSEL29_A::SA4 + } + #[doc = "Checks if the value of the field is `PCM_FS`"] + #[inline(always)] + pub fn is_pcm_fs(&self) -> bool { + *self == FSEL29_A::PCM_FS + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL29_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL29_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL29_A::RESERVED5 + } +} +#[doc = "Field `FSEL29` writer - Function Select 29"] +pub type FSEL29_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL29_A, 3, O>; +impl<'a, const O: u8> FSEL29_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL29_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL29_A::OUTPUT) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL29_A::SCL0) + } + #[doc = "Pin is connected to SA4"] + #[inline(always)] + pub fn sa4(self) -> &'a mut W { + self.variant(FSEL29_A::SA4) + } + #[doc = "Pin is connected to PCM_FS"] + #[inline(always)] + pub fn pcm_fs(self) -> &'a mut W { + self.variant(FSEL29_A::PCM_FS) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 20"] + #[inline(always)] + pub fn fsel20(&self) -> FSEL20_R { + FSEL20_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 21"] + #[inline(always)] + pub fn fsel21(&self) -> FSEL21_R { + FSEL21_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 22"] + #[inline(always)] + pub fn fsel22(&self) -> FSEL22_R { + FSEL22_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 23"] + #[inline(always)] + pub fn fsel23(&self) -> FSEL23_R { + FSEL23_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 24"] + #[inline(always)] + pub fn fsel24(&self) -> FSEL24_R { + FSEL24_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 25"] + #[inline(always)] + pub fn fsel25(&self) -> FSEL25_R { + FSEL25_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 26"] + #[inline(always)] + pub fn fsel26(&self) -> FSEL26_R { + FSEL26_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 27"] + #[inline(always)] + pub fn fsel27(&self) -> FSEL27_R { + FSEL27_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 28"] + #[inline(always)] + pub fn fsel28(&self) -> FSEL28_R { + FSEL28_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 29"] + #[inline(always)] + pub fn fsel29(&self) -> FSEL29_R { + FSEL29_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 20"] + #[inline(always)] + #[must_use] + pub fn fsel20(&mut self) -> FSEL20_W<0> { + FSEL20_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 21"] + #[inline(always)] + #[must_use] + pub fn fsel21(&mut self) -> FSEL21_W<3> { + FSEL21_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 22"] + #[inline(always)] + #[must_use] + pub fn fsel22(&mut self) -> FSEL22_W<6> { + FSEL22_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 23"] + #[inline(always)] + #[must_use] + pub fn fsel23(&mut self) -> FSEL23_W<9> { + FSEL23_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 24"] + #[inline(always)] + #[must_use] + pub fn fsel24(&mut self) -> FSEL24_W<12> { + FSEL24_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 25"] + #[inline(always)] + #[must_use] + pub fn fsel25(&mut self) -> FSEL25_W<15> { + FSEL25_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 26"] + #[inline(always)] + #[must_use] + pub fn fsel26(&mut self) -> FSEL26_W<18> { + FSEL26_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 27"] + #[inline(always)] + #[must_use] + pub fn fsel27(&mut self) -> FSEL27_W<21> { + FSEL27_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 28"] + #[inline(always)] + #[must_use] + pub fn fsel28(&mut self) -> FSEL28_W<24> { + FSEL28_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 29"] + #[inline(always)] + #[must_use] + pub fn fsel29(&mut self) -> FSEL29_W<27> { + FSEL29_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel2](index.html) module"] +pub struct GPFSEL2_SPEC; +impl crate::RegisterSpec for GPFSEL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel2::R](R) reader structure"] +impl crate::Readable for GPFSEL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel2::W](W) writer structure"] +impl crate::Writable for GPFSEL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel3.rs b/crates/bcm2835-lpa/src/gpio/gpfsel3.rs new file mode 100644 index 0000000..d3f9c4f --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfsel3.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL30` reader - Function Select 30"] +pub type FSEL30_R = crate::FieldReader; +#[doc = "Function Select 30"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL30_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA3"] + SA3 = 5, + #[doc = "6: Pin is connected to PCM_DIN"] + PCM_DIN = 6, + #[doc = "7: Pin is connected to CTS0"] + CTS0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL30_A) -> Self { + variant as _ + } +} +impl FSEL30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL30_A { + match self.bits { + 0 => FSEL30_A::INPUT, + 1 => FSEL30_A::OUTPUT, + 4 => FSEL30_A::RESERVED0, + 5 => FSEL30_A::SA3, + 6 => FSEL30_A::PCM_DIN, + 7 => FSEL30_A::CTS0, + 3 => FSEL30_A::RESERVED4, + 2 => FSEL30_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL30_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL30_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL30_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA3`"] + #[inline(always)] + pub fn is_sa3(&self) -> bool { + *self == FSEL30_A::SA3 + } + #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[inline(always)] + pub fn is_pcm_din(&self) -> bool { + *self == FSEL30_A::PCM_DIN + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL30_A::CTS0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL30_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL30_A::CTS1 + } +} +#[doc = "Field `FSEL30` writer - Function Select 30"] +pub type FSEL30_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL30_A, 3, O>; +impl<'a, const O: u8> FSEL30_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL30_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL30_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL30_A::RESERVED0) + } + #[doc = "Pin is connected to SA3"] + #[inline(always)] + pub fn sa3(self) -> &'a mut W { + self.variant(FSEL30_A::SA3) + } + #[doc = "Pin is connected to PCM_DIN"] + #[inline(always)] + pub fn pcm_din(self) -> &'a mut W { + self.variant(FSEL30_A::PCM_DIN) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL30_A::CTS0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL30_A::RESERVED4) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL30_A::CTS1) + } +} +#[doc = "Field `FSEL31` reader - Function Select 31"] +pub type FSEL31_R = crate::FieldReader; +#[doc = "Function Select 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL31_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA2"] + SA2 = 5, + #[doc = "6: Pin is connected to PCM_DOUT"] + PCM_DOUT = 6, + #[doc = "7: Pin is connected to RTS0"] + RTS0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL31_A) -> Self { + variant as _ + } +} +impl FSEL31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL31_A { + match self.bits { + 0 => FSEL31_A::INPUT, + 1 => FSEL31_A::OUTPUT, + 4 => FSEL31_A::RESERVED0, + 5 => FSEL31_A::SA2, + 6 => FSEL31_A::PCM_DOUT, + 7 => FSEL31_A::RTS0, + 3 => FSEL31_A::RESERVED4, + 2 => FSEL31_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL31_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL31_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL31_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA2`"] + #[inline(always)] + pub fn is_sa2(&self) -> bool { + *self == FSEL31_A::SA2 + } + #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[inline(always)] + pub fn is_pcm_dout(&self) -> bool { + *self == FSEL31_A::PCM_DOUT + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL31_A::RTS0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL31_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL31_A::RTS1 + } +} +#[doc = "Field `FSEL31` writer - Function Select 31"] +pub type FSEL31_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL31_A, 3, O>; +impl<'a, const O: u8> FSEL31_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL31_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL31_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL31_A::RESERVED0) + } + #[doc = "Pin is connected to SA2"] + #[inline(always)] + pub fn sa2(self) -> &'a mut W { + self.variant(FSEL31_A::SA2) + } + #[doc = "Pin is connected to PCM_DOUT"] + #[inline(always)] + pub fn pcm_dout(self) -> &'a mut W { + self.variant(FSEL31_A::PCM_DOUT) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL31_A::RTS0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL31_A::RESERVED4) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL31_A::RTS1) + } +} +#[doc = "Field `FSEL32` reader - Function Select 32"] +pub type FSEL32_R = crate::FieldReader; +#[doc = "Function Select 32"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL32_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SA1"] + SA1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to TXD0"] + TXD0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL32_A) -> Self { + variant as _ + } +} +impl FSEL32_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL32_A { + match self.bits { + 0 => FSEL32_A::INPUT, + 1 => FSEL32_A::OUTPUT, + 4 => FSEL32_A::GPCLK0, + 5 => FSEL32_A::SA1, + 6 => FSEL32_A::RESERVED2, + 7 => FSEL32_A::TXD0, + 3 => FSEL32_A::RESERVED4, + 2 => FSEL32_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL32_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL32_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL32_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SA1`"] + #[inline(always)] + pub fn is_sa1(&self) -> bool { + *self == FSEL32_A::SA1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL32_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL32_A::TXD0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL32_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL32_A::TXD1 + } +} +#[doc = "Field `FSEL32` writer - Function Select 32"] +pub type FSEL32_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL32_A, 3, O>; +impl<'a, const O: u8> FSEL32_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL32_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL32_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL32_A::GPCLK0) + } + #[doc = "Pin is connected to SA1"] + #[inline(always)] + pub fn sa1(self) -> &'a mut W { + self.variant(FSEL32_A::SA1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL32_A::RESERVED2) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL32_A::TXD0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL32_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL32_A::TXD1) + } +} +#[doc = "Field `FSEL33` reader - Function Select 33"] +pub type FSEL33_R = crate::FieldReader; +#[doc = "Function Select 33"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL33_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA0"] + SA0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to RXD0"] + RXD0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL33_A) -> Self { + variant as _ + } +} +impl FSEL33_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL33_A { + match self.bits { + 0 => FSEL33_A::INPUT, + 1 => FSEL33_A::OUTPUT, + 4 => FSEL33_A::RESERVED0, + 5 => FSEL33_A::SA0, + 6 => FSEL33_A::RESERVED2, + 7 => FSEL33_A::RXD0, + 3 => FSEL33_A::RESERVED4, + 2 => FSEL33_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL33_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL33_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL33_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA0`"] + #[inline(always)] + pub fn is_sa0(&self) -> bool { + *self == FSEL33_A::SA0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL33_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL33_A::RXD0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL33_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL33_A::RXD1 + } +} +#[doc = "Field `FSEL33` writer - Function Select 33"] +pub type FSEL33_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL33_A, 3, O>; +impl<'a, const O: u8> FSEL33_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL33_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL33_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED0) + } + #[doc = "Pin is connected to SA0"] + #[inline(always)] + pub fn sa0(self) -> &'a mut W { + self.variant(FSEL33_A::SA0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED2) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL33_A::RXD0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL33_A::RXD1) + } +} +#[doc = "Field `FSEL34` reader - Function Select 34"] +pub type FSEL34_R = crate::FieldReader; +#[doc = "Function Select 34"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL34_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SOE_N"] + SOE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL34_A) -> Self { + variant as _ + } +} +impl FSEL34_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL34_A { + match self.bits { + 0 => FSEL34_A::INPUT, + 1 => FSEL34_A::OUTPUT, + 4 => FSEL34_A::GPCLK0, + 5 => FSEL34_A::SOE_N, + 6 => FSEL34_A::RESERVED2, + 7 => FSEL34_A::RESERVED3, + 3 => FSEL34_A::RESERVED4, + 2 => FSEL34_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL34_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL34_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL34_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SOE_N`"] + #[inline(always)] + pub fn is_soe_n(&self) -> bool { + *self == FSEL34_A::SOE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL34_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL34_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL34_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL34_A::RESERVED5 + } +} +#[doc = "Field `FSEL34` writer - Function Select 34"] +pub type FSEL34_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL34_A, 3, O>; +impl<'a, const O: u8> FSEL34_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL34_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL34_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL34_A::GPCLK0) + } + #[doc = "Pin is connected to SOE_N"] + #[inline(always)] + pub fn soe_n(self) -> &'a mut W { + self.variant(FSEL34_A::SOE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED5) + } +} +#[doc = "Field `FSEL35` reader - Function Select 35"] +pub type FSEL35_R = crate::FieldReader; +#[doc = "Function Select 35"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL35_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE1_N"] + SPI0_CE1_N = 4, + #[doc = "5: Pin is connected to SWE_N"] + SWE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL35_A) -> Self { + variant as _ + } +} +impl FSEL35_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL35_A { + match self.bits { + 0 => FSEL35_A::INPUT, + 1 => FSEL35_A::OUTPUT, + 4 => FSEL35_A::SPI0_CE1_N, + 5 => FSEL35_A::SWE_N, + 6 => FSEL35_A::RESERVED2, + 7 => FSEL35_A::RESERVED3, + 3 => FSEL35_A::RESERVED4, + 2 => FSEL35_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL35_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL35_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[inline(always)] + pub fn is_spi0_ce1_n(&self) -> bool { + *self == FSEL35_A::SPI0_CE1_N + } + #[doc = "Checks if the value of the field is `SWE_N`"] + #[inline(always)] + pub fn is_swe_n(&self) -> bool { + *self == FSEL35_A::SWE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL35_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL35_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL35_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL35_A::RESERVED5 + } +} +#[doc = "Field `FSEL35` writer - Function Select 35"] +pub type FSEL35_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL35_A, 3, O>; +impl<'a, const O: u8> FSEL35_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL35_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL35_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE1_N"] + #[inline(always)] + pub fn spi0_ce1_n(self) -> &'a mut W { + self.variant(FSEL35_A::SPI0_CE1_N) + } + #[doc = "Pin is connected to SWE_N"] + #[inline(always)] + pub fn swe_n(self) -> &'a mut W { + self.variant(FSEL35_A::SWE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED5) + } +} +#[doc = "Field `FSEL36` reader - Function Select 36"] +pub type FSEL36_R = crate::FieldReader; +#[doc = "Function Select 36"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL36_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE0_N"] + SPI0_CE0_N = 4, + #[doc = "5: Pin is connected to SD0"] + SD0 = 5, + #[doc = "6: Pin is connected to TXD0"] + TXD0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL36_A) -> Self { + variant as _ + } +} +impl FSEL36_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL36_A { + match self.bits { + 0 => FSEL36_A::INPUT, + 1 => FSEL36_A::OUTPUT, + 4 => FSEL36_A::SPI0_CE0_N, + 5 => FSEL36_A::SD0, + 6 => FSEL36_A::TXD0, + 7 => FSEL36_A::RESERVED3, + 3 => FSEL36_A::RESERVED4, + 2 => FSEL36_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL36_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL36_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[inline(always)] + pub fn is_spi0_ce0_n(&self) -> bool { + *self == FSEL36_A::SPI0_CE0_N + } + #[doc = "Checks if the value of the field is `SD0`"] + #[inline(always)] + pub fn is_sd0(&self) -> bool { + *self == FSEL36_A::SD0 + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL36_A::TXD0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL36_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL36_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL36_A::RESERVED5 + } +} +#[doc = "Field `FSEL36` writer - Function Select 36"] +pub type FSEL36_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL36_A, 3, O>; +impl<'a, const O: u8> FSEL36_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL36_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL36_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE0_N"] + #[inline(always)] + pub fn spi0_ce0_n(self) -> &'a mut W { + self.variant(FSEL36_A::SPI0_CE0_N) + } + #[doc = "Pin is connected to SD0"] + #[inline(always)] + pub fn sd0(self) -> &'a mut W { + self.variant(FSEL36_A::SD0) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL36_A::TXD0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL36_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL36_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL36_A::RESERVED5) + } +} +#[doc = "Field `FSEL37` reader - Function Select 37"] +pub type FSEL37_R = crate::FieldReader; +#[doc = "Function Select 37"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL37_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MISO"] + SPI0_MISO = 4, + #[doc = "5: Pin is connected to SD1"] + SD1 = 5, + #[doc = "6: Pin is connected to RXD0"] + RXD0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL37_A) -> Self { + variant as _ + } +} +impl FSEL37_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL37_A { + match self.bits { + 0 => FSEL37_A::INPUT, + 1 => FSEL37_A::OUTPUT, + 4 => FSEL37_A::SPI0_MISO, + 5 => FSEL37_A::SD1, + 6 => FSEL37_A::RXD0, + 7 => FSEL37_A::RESERVED3, + 3 => FSEL37_A::RESERVED4, + 2 => FSEL37_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL37_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL37_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[inline(always)] + pub fn is_spi0_miso(&self) -> bool { + *self == FSEL37_A::SPI0_MISO + } + #[doc = "Checks if the value of the field is `SD1`"] + #[inline(always)] + pub fn is_sd1(&self) -> bool { + *self == FSEL37_A::SD1 + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL37_A::RXD0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL37_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL37_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL37_A::RESERVED5 + } +} +#[doc = "Field `FSEL37` writer - Function Select 37"] +pub type FSEL37_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL37_A, 3, O>; +impl<'a, const O: u8> FSEL37_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL37_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL37_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MISO"] + #[inline(always)] + pub fn spi0_miso(self) -> &'a mut W { + self.variant(FSEL37_A::SPI0_MISO) + } + #[doc = "Pin is connected to SD1"] + #[inline(always)] + pub fn sd1(self) -> &'a mut W { + self.variant(FSEL37_A::SD1) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL37_A::RXD0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL37_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL37_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL37_A::RESERVED5) + } +} +#[doc = "Field `FSEL38` reader - Function Select 38"] +pub type FSEL38_R = crate::FieldReader; +#[doc = "Function Select 38"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL38_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MOSI"] + SPI0_MOSI = 4, + #[doc = "5: Pin is connected to SD2"] + SD2 = 5, + #[doc = "6: Pin is connected to CTS0"] + CTS0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL38_A) -> Self { + variant as _ + } +} +impl FSEL38_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL38_A { + match self.bits { + 0 => FSEL38_A::INPUT, + 1 => FSEL38_A::OUTPUT, + 4 => FSEL38_A::SPI0_MOSI, + 5 => FSEL38_A::SD2, + 6 => FSEL38_A::CTS0, + 7 => FSEL38_A::RESERVED3, + 3 => FSEL38_A::RESERVED4, + 2 => FSEL38_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL38_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL38_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[inline(always)] + pub fn is_spi0_mosi(&self) -> bool { + *self == FSEL38_A::SPI0_MOSI + } + #[doc = "Checks if the value of the field is `SD2`"] + #[inline(always)] + pub fn is_sd2(&self) -> bool { + *self == FSEL38_A::SD2 + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL38_A::CTS0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL38_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL38_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL38_A::RESERVED5 + } +} +#[doc = "Field `FSEL38` writer - Function Select 38"] +pub type FSEL38_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL38_A, 3, O>; +impl<'a, const O: u8> FSEL38_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL38_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL38_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MOSI"] + #[inline(always)] + pub fn spi0_mosi(self) -> &'a mut W { + self.variant(FSEL38_A::SPI0_MOSI) + } + #[doc = "Pin is connected to SD2"] + #[inline(always)] + pub fn sd2(self) -> &'a mut W { + self.variant(FSEL38_A::SD2) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL38_A::CTS0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL38_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL38_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL38_A::RESERVED5) + } +} +#[doc = "Field `FSEL39` reader - Function Select 39"] +pub type FSEL39_R = crate::FieldReader; +#[doc = "Function Select 39"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL39_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_SCLK"] + SPI0_SCLK = 4, + #[doc = "5: Pin is connected to SD3"] + SD3 = 5, + #[doc = "6: Pin is connected to RTS0"] + RTS0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL39_A) -> Self { + variant as _ + } +} +impl FSEL39_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL39_A { + match self.bits { + 0 => FSEL39_A::INPUT, + 1 => FSEL39_A::OUTPUT, + 4 => FSEL39_A::SPI0_SCLK, + 5 => FSEL39_A::SD3, + 6 => FSEL39_A::RTS0, + 7 => FSEL39_A::RESERVED3, + 3 => FSEL39_A::RESERVED4, + 2 => FSEL39_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL39_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL39_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[inline(always)] + pub fn is_spi0_sclk(&self) -> bool { + *self == FSEL39_A::SPI0_SCLK + } + #[doc = "Checks if the value of the field is `SD3`"] + #[inline(always)] + pub fn is_sd3(&self) -> bool { + *self == FSEL39_A::SD3 + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL39_A::RTS0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL39_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL39_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL39_A::RESERVED5 + } +} +#[doc = "Field `FSEL39` writer - Function Select 39"] +pub type FSEL39_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL39_A, 3, O>; +impl<'a, const O: u8> FSEL39_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL39_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL39_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_SCLK"] + #[inline(always)] + pub fn spi0_sclk(self) -> &'a mut W { + self.variant(FSEL39_A::SPI0_SCLK) + } + #[doc = "Pin is connected to SD3"] + #[inline(always)] + pub fn sd3(self) -> &'a mut W { + self.variant(FSEL39_A::SD3) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL39_A::RTS0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL39_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL39_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL39_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 30"] + #[inline(always)] + pub fn fsel30(&self) -> FSEL30_R { + FSEL30_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 31"] + #[inline(always)] + pub fn fsel31(&self) -> FSEL31_R { + FSEL31_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 32"] + #[inline(always)] + pub fn fsel32(&self) -> FSEL32_R { + FSEL32_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 33"] + #[inline(always)] + pub fn fsel33(&self) -> FSEL33_R { + FSEL33_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 34"] + #[inline(always)] + pub fn fsel34(&self) -> FSEL34_R { + FSEL34_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 35"] + #[inline(always)] + pub fn fsel35(&self) -> FSEL35_R { + FSEL35_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 36"] + #[inline(always)] + pub fn fsel36(&self) -> FSEL36_R { + FSEL36_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 37"] + #[inline(always)] + pub fn fsel37(&self) -> FSEL37_R { + FSEL37_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 38"] + #[inline(always)] + pub fn fsel38(&self) -> FSEL38_R { + FSEL38_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 39"] + #[inline(always)] + pub fn fsel39(&self) -> FSEL39_R { + FSEL39_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 30"] + #[inline(always)] + #[must_use] + pub fn fsel30(&mut self) -> FSEL30_W<0> { + FSEL30_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 31"] + #[inline(always)] + #[must_use] + pub fn fsel31(&mut self) -> FSEL31_W<3> { + FSEL31_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 32"] + #[inline(always)] + #[must_use] + pub fn fsel32(&mut self) -> FSEL32_W<6> { + FSEL32_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 33"] + #[inline(always)] + #[must_use] + pub fn fsel33(&mut self) -> FSEL33_W<9> { + FSEL33_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 34"] + #[inline(always)] + #[must_use] + pub fn fsel34(&mut self) -> FSEL34_W<12> { + FSEL34_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 35"] + #[inline(always)] + #[must_use] + pub fn fsel35(&mut self) -> FSEL35_W<15> { + FSEL35_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 36"] + #[inline(always)] + #[must_use] + pub fn fsel36(&mut self) -> FSEL36_W<18> { + FSEL36_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 37"] + #[inline(always)] + #[must_use] + pub fn fsel37(&mut self) -> FSEL37_W<21> { + FSEL37_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 38"] + #[inline(always)] + #[must_use] + pub fn fsel38(&mut self) -> FSEL38_W<24> { + FSEL38_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 39"] + #[inline(always)] + #[must_use] + pub fn fsel39(&mut self) -> FSEL39_W<27> { + FSEL39_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel3](index.html) module"] +pub struct GPFSEL3_SPEC; +impl crate::RegisterSpec for GPFSEL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel3::R](R) reader structure"] +impl crate::Readable for GPFSEL3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel3::W](W) writer structure"] +impl crate::Writable for GPFSEL3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel4.rs b/crates/bcm2835-lpa/src/gpio/gpfsel4.rs new file mode 100644 index 0000000..16bf84a --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfsel4.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL40` reader - Function Select 40"] +pub type FSEL40_R = crate::FieldReader; +#[doc = "Function Select 40"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL40_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_0"] + PWM0_0 = 4, + #[doc = "5: Pin is connected to SD4"] + SD4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL40_A) -> Self { + variant as _ + } +} +impl FSEL40_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL40_A { + match self.bits { + 0 => FSEL40_A::INPUT, + 1 => FSEL40_A::OUTPUT, + 4 => FSEL40_A::PWM0_0, + 5 => FSEL40_A::SD4, + 6 => FSEL40_A::RESERVED2, + 7 => FSEL40_A::RESERVED3, + 3 => FSEL40_A::RESERVED4, + 2 => FSEL40_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL40_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL40_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL40_A::PWM0_0 + } + #[doc = "Checks if the value of the field is `SD4`"] + #[inline(always)] + pub fn is_sd4(&self) -> bool { + *self == FSEL40_A::SD4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL40_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL40_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL40_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL40_A::TXD1 + } +} +#[doc = "Field `FSEL40` writer - Function Select 40"] +pub type FSEL40_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL40_A, 3, O>; +impl<'a, const O: u8> FSEL40_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL40_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL40_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL40_A::PWM0_0) + } + #[doc = "Pin is connected to SD4"] + #[inline(always)] + pub fn sd4(self) -> &'a mut W { + self.variant(FSEL40_A::SD4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL40_A::TXD1) + } +} +#[doc = "Field `FSEL41` reader - Function Select 41"] +pub type FSEL41_R = crate::FieldReader; +#[doc = "Function Select 41"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL41_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SD5"] + SD5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL41_A) -> Self { + variant as _ + } +} +impl FSEL41_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL41_A { + match self.bits { + 0 => FSEL41_A::INPUT, + 1 => FSEL41_A::OUTPUT, + 4 => FSEL41_A::PWM0_1, + 5 => FSEL41_A::SD5, + 6 => FSEL41_A::RESERVED2, + 7 => FSEL41_A::RESERVED3, + 3 => FSEL41_A::RESERVED4, + 2 => FSEL41_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL41_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL41_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL41_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SD5`"] + #[inline(always)] + pub fn is_sd5(&self) -> bool { + *self == FSEL41_A::SD5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL41_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL41_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL41_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL41_A::RXD1 + } +} +#[doc = "Field `FSEL41` writer - Function Select 41"] +pub type FSEL41_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL41_A, 3, O>; +impl<'a, const O: u8> FSEL41_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL41_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL41_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL41_A::PWM0_1) + } + #[doc = "Pin is connected to SD5"] + #[inline(always)] + pub fn sd5(self) -> &'a mut W { + self.variant(FSEL41_A::SD5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL41_A::RXD1) + } +} +#[doc = "Field `FSEL42` reader - Function Select 42"] +pub type FSEL42_R = crate::FieldReader; +#[doc = "Function Select 42"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL42_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SD6"] + SD6 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL42_A) -> Self { + variant as _ + } +} +impl FSEL42_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL42_A { + match self.bits { + 0 => FSEL42_A::INPUT, + 1 => FSEL42_A::OUTPUT, + 4 => FSEL42_A::GPCLK1, + 5 => FSEL42_A::SD6, + 6 => FSEL42_A::RESERVED2, + 7 => FSEL42_A::RESERVED3, + 3 => FSEL42_A::RESERVED4, + 2 => FSEL42_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL42_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL42_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL42_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SD6`"] + #[inline(always)] + pub fn is_sd6(&self) -> bool { + *self == FSEL42_A::SD6 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL42_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL42_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL42_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL42_A::CTS1 + } +} +#[doc = "Field `FSEL42` writer - Function Select 42"] +pub type FSEL42_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL42_A, 3, O>; +impl<'a, const O: u8> FSEL42_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL42_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL42_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL42_A::GPCLK1) + } + #[doc = "Pin is connected to SD6"] + #[inline(always)] + pub fn sd6(self) -> &'a mut W { + self.variant(FSEL42_A::SD6) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED4) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL42_A::CTS1) + } +} +#[doc = "Field `FSEL43` reader - Function Select 43"] +pub type FSEL43_R = crate::FieldReader; +#[doc = "Function Select 43"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL43_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK2"] + GPCLK2 = 4, + #[doc = "5: Pin is connected to SD7"] + SD7 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL43_A) -> Self { + variant as _ + } +} +impl FSEL43_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL43_A { + match self.bits { + 0 => FSEL43_A::INPUT, + 1 => FSEL43_A::OUTPUT, + 4 => FSEL43_A::GPCLK2, + 5 => FSEL43_A::SD7, + 6 => FSEL43_A::RESERVED2, + 7 => FSEL43_A::RESERVED3, + 3 => FSEL43_A::RESERVED4, + 2 => FSEL43_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL43_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL43_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK2`"] + #[inline(always)] + pub fn is_gpclk2(&self) -> bool { + *self == FSEL43_A::GPCLK2 + } + #[doc = "Checks if the value of the field is `SD7`"] + #[inline(always)] + pub fn is_sd7(&self) -> bool { + *self == FSEL43_A::SD7 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL43_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL43_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL43_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL43_A::RTS1 + } +} +#[doc = "Field `FSEL43` writer - Function Select 43"] +pub type FSEL43_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL43_A, 3, O>; +impl<'a, const O: u8> FSEL43_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL43_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL43_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK2"] + #[inline(always)] + pub fn gpclk2(self) -> &'a mut W { + self.variant(FSEL43_A::GPCLK2) + } + #[doc = "Pin is connected to SD7"] + #[inline(always)] + pub fn sd7(self) -> &'a mut W { + self.variant(FSEL43_A::SD7) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED4) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL43_A::RTS1) + } +} +#[doc = "Field `FSEL44` reader - Function Select 44"] +pub type FSEL44_R = crate::FieldReader; +#[doc = "Function Select 44"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL44_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SDA0"] + SDA0 = 5, + #[doc = "6: Pin is connected to SDA1"] + SDA1 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL44_A) -> Self { + variant as _ + } +} +impl FSEL44_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL44_A { + match self.bits { + 0 => FSEL44_A::INPUT, + 1 => FSEL44_A::OUTPUT, + 4 => FSEL44_A::GPCLK1, + 5 => FSEL44_A::SDA0, + 6 => FSEL44_A::SDA1, + 7 => FSEL44_A::RESERVED3, + 3 => FSEL44_A::RESERVED4, + 2 => FSEL44_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL44_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL44_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL44_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL44_A::SDA0 + } + #[doc = "Checks if the value of the field is `SDA1`"] + #[inline(always)] + pub fn is_sda1(&self) -> bool { + *self == FSEL44_A::SDA1 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL44_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL44_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL44_A::RESERVED5 + } +} +#[doc = "Field `FSEL44` writer - Function Select 44"] +pub type FSEL44_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL44_A, 3, O>; +impl<'a, const O: u8> FSEL44_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL44_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL44_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL44_A::GPCLK1) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL44_A::SDA0) + } + #[doc = "Pin is connected to SDA1"] + #[inline(always)] + pub fn sda1(self) -> &'a mut W { + self.variant(FSEL44_A::SDA1) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED5) + } +} +#[doc = "Field `FSEL45` reader - Function Select 45"] +pub type FSEL45_R = crate::FieldReader; +#[doc = "Function Select 45"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL45_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SCL0"] + SCL0 = 5, + #[doc = "6: Pin is connected to SCL1"] + SCL1 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL45_A) -> Self { + variant as _ + } +} +impl FSEL45_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL45_A { + match self.bits { + 0 => FSEL45_A::INPUT, + 1 => FSEL45_A::OUTPUT, + 4 => FSEL45_A::PWM0_1, + 5 => FSEL45_A::SCL0, + 6 => FSEL45_A::SCL1, + 7 => FSEL45_A::RESERVED3, + 3 => FSEL45_A::RESERVED4, + 2 => FSEL45_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL45_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL45_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL45_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL45_A::SCL0 + } + #[doc = "Checks if the value of the field is `SCL1`"] + #[inline(always)] + pub fn is_scl1(&self) -> bool { + *self == FSEL45_A::SCL1 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL45_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL45_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL45_A::RESERVED5 + } +} +#[doc = "Field `FSEL45` writer - Function Select 45"] +pub type FSEL45_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL45_A, 3, O>; +impl<'a, const O: u8> FSEL45_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL45_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL45_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL45_A::PWM0_1) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL45_A::SCL0) + } + #[doc = "Pin is connected to SCL1"] + #[inline(always)] + pub fn scl1(self) -> &'a mut W { + self.variant(FSEL45_A::SCL1) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED5) + } +} +#[doc = "Field `FSEL46` reader - Function Select 46"] +pub type FSEL46_R = crate::FieldReader; +#[doc = "Function Select 46"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL46_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL46_A) -> Self { + variant as _ + } +} +impl FSEL46_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL46_A { + match self.bits { + 0 => FSEL46_A::INPUT, + 1 => FSEL46_A::OUTPUT, + 4 => FSEL46_A::RESERVED0, + 5 => FSEL46_A::RESERVED1, + 6 => FSEL46_A::RESERVED2, + 7 => FSEL46_A::RESERVED3, + 3 => FSEL46_A::RESERVED4, + 2 => FSEL46_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL46_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL46_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL46_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL46_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL46_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL46_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL46_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL46_A::RESERVED5 + } +} +#[doc = "Field `FSEL46` writer - Function Select 46"] +pub type FSEL46_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL46_A, 3, O>; +impl<'a, const O: u8> FSEL46_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL46_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL46_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED5) + } +} +#[doc = "Field `FSEL47` reader - Function Select 47"] +pub type FSEL47_R = crate::FieldReader; +#[doc = "Function Select 47"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL47_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL47_A) -> Self { + variant as _ + } +} +impl FSEL47_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL47_A { + match self.bits { + 0 => FSEL47_A::INPUT, + 1 => FSEL47_A::OUTPUT, + 4 => FSEL47_A::RESERVED0, + 5 => FSEL47_A::RESERVED1, + 6 => FSEL47_A::RESERVED2, + 7 => FSEL47_A::RESERVED3, + 3 => FSEL47_A::RESERVED4, + 2 => FSEL47_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL47_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL47_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL47_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL47_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL47_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL47_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL47_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL47_A::RESERVED5 + } +} +#[doc = "Field `FSEL47` writer - Function Select 47"] +pub type FSEL47_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL47_A, 3, O>; +impl<'a, const O: u8> FSEL47_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL47_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL47_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED5) + } +} +#[doc = "Field `FSEL48` reader - Function Select 48"] +pub type FSEL48_R = crate::FieldReader; +#[doc = "Function Select 48"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL48_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL48_A) -> Self { + variant as _ + } +} +impl FSEL48_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL48_A { + match self.bits { + 0 => FSEL48_A::INPUT, + 1 => FSEL48_A::OUTPUT, + 4 => FSEL48_A::RESERVED0, + 5 => FSEL48_A::RESERVED1, + 6 => FSEL48_A::RESERVED2, + 7 => FSEL48_A::SD1_CLK, + 3 => FSEL48_A::RESERVED4, + 2 => FSEL48_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL48_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL48_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL48_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL48_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL48_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL48_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL48_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL48_A::RESERVED5 + } +} +#[doc = "Field `FSEL48` writer - Function Select 48"] +pub type FSEL48_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL48_A, 3, O>; +impl<'a, const O: u8> FSEL48_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL48_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL48_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL48_A::SD1_CLK) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED5) + } +} +#[doc = "Field `FSEL49` reader - Function Select 49"] +pub type FSEL49_R = crate::FieldReader; +#[doc = "Function Select 49"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL49_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL49_A) -> Self { + variant as _ + } +} +impl FSEL49_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL49_A { + match self.bits { + 0 => FSEL49_A::INPUT, + 1 => FSEL49_A::OUTPUT, + 4 => FSEL49_A::RESERVED0, + 5 => FSEL49_A::RESERVED1, + 6 => FSEL49_A::RESERVED2, + 7 => FSEL49_A::SD1_CMD, + 3 => FSEL49_A::RESERVED4, + 2 => FSEL49_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL49_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL49_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL49_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL49_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL49_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL49_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL49_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL49_A::RESERVED5 + } +} +#[doc = "Field `FSEL49` writer - Function Select 49"] +pub type FSEL49_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL49_A, 3, O>; +impl<'a, const O: u8> FSEL49_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL49_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL49_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL49_A::SD1_CMD) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 40"] + #[inline(always)] + pub fn fsel40(&self) -> FSEL40_R { + FSEL40_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 41"] + #[inline(always)] + pub fn fsel41(&self) -> FSEL41_R { + FSEL41_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 42"] + #[inline(always)] + pub fn fsel42(&self) -> FSEL42_R { + FSEL42_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 43"] + #[inline(always)] + pub fn fsel43(&self) -> FSEL43_R { + FSEL43_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 44"] + #[inline(always)] + pub fn fsel44(&self) -> FSEL44_R { + FSEL44_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 45"] + #[inline(always)] + pub fn fsel45(&self) -> FSEL45_R { + FSEL45_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 46"] + #[inline(always)] + pub fn fsel46(&self) -> FSEL46_R { + FSEL46_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 47"] + #[inline(always)] + pub fn fsel47(&self) -> FSEL47_R { + FSEL47_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 48"] + #[inline(always)] + pub fn fsel48(&self) -> FSEL48_R { + FSEL48_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 49"] + #[inline(always)] + pub fn fsel49(&self) -> FSEL49_R { + FSEL49_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 40"] + #[inline(always)] + #[must_use] + pub fn fsel40(&mut self) -> FSEL40_W<0> { + FSEL40_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 41"] + #[inline(always)] + #[must_use] + pub fn fsel41(&mut self) -> FSEL41_W<3> { + FSEL41_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 42"] + #[inline(always)] + #[must_use] + pub fn fsel42(&mut self) -> FSEL42_W<6> { + FSEL42_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 43"] + #[inline(always)] + #[must_use] + pub fn fsel43(&mut self) -> FSEL43_W<9> { + FSEL43_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 44"] + #[inline(always)] + #[must_use] + pub fn fsel44(&mut self) -> FSEL44_W<12> { + FSEL44_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 45"] + #[inline(always)] + #[must_use] + pub fn fsel45(&mut self) -> FSEL45_W<15> { + FSEL45_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 46"] + #[inline(always)] + #[must_use] + pub fn fsel46(&mut self) -> FSEL46_W<18> { + FSEL46_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 47"] + #[inline(always)] + #[must_use] + pub fn fsel47(&mut self) -> FSEL47_W<21> { + FSEL47_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 48"] + #[inline(always)] + #[must_use] + pub fn fsel48(&mut self) -> FSEL48_W<24> { + FSEL48_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 49"] + #[inline(always)] + #[must_use] + pub fn fsel49(&mut self) -> FSEL49_W<27> { + FSEL49_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel4](index.html) module"] +pub struct GPFSEL4_SPEC; +impl crate::RegisterSpec for GPFSEL4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel4::R](R) reader structure"] +impl crate::Readable for GPFSEL4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel4::W](W) writer structure"] +impl crate::Writable for GPFSEL4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel5.rs b/crates/bcm2835-lpa/src/gpio/gpfsel5.rs new file mode 100644 index 0000000..7195017 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpfsel5.rs @@ -0,0 +1,629 @@ +#[doc = "Register `GPFSEL5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL50` reader - Function Select 50"] +pub type FSEL50_R = crate::FieldReader; +#[doc = "Function Select 50"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL50_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL50_A) -> Self { + variant as _ + } +} +impl FSEL50_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL50_A { + match self.bits { + 0 => FSEL50_A::INPUT, + 1 => FSEL50_A::OUTPUT, + 4 => FSEL50_A::RESERVED0, + 5 => FSEL50_A::RESERVED1, + 6 => FSEL50_A::RESERVED2, + 7 => FSEL50_A::SD1_DAT0, + 3 => FSEL50_A::RESERVED4, + 2 => FSEL50_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL50_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL50_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL50_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL50_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL50_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL50_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL50_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL50_A::RESERVED5 + } +} +#[doc = "Field `FSEL50` writer - Function Select 50"] +pub type FSEL50_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL50_A, 3, O>; +impl<'a, const O: u8> FSEL50_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL50_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL50_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL50_A::SD1_DAT0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED5) + } +} +#[doc = "Field `FSEL51` reader - Function Select 51"] +pub type FSEL51_R = crate::FieldReader; +#[doc = "Function Select 51"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL51_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL51_A) -> Self { + variant as _ + } +} +impl FSEL51_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL51_A { + match self.bits { + 0 => FSEL51_A::INPUT, + 1 => FSEL51_A::OUTPUT, + 4 => FSEL51_A::RESERVED0, + 5 => FSEL51_A::RESERVED1, + 6 => FSEL51_A::RESERVED2, + 7 => FSEL51_A::SD1_DAT1, + 3 => FSEL51_A::RESERVED4, + 2 => FSEL51_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL51_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL51_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL51_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL51_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL51_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL51_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL51_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL51_A::RESERVED5 + } +} +#[doc = "Field `FSEL51` writer - Function Select 51"] +pub type FSEL51_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL51_A, 3, O>; +impl<'a, const O: u8> FSEL51_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL51_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL51_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL51_A::SD1_DAT1) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED5) + } +} +#[doc = "Field `FSEL52` reader - Function Select 52"] +pub type FSEL52_R = crate::FieldReader; +#[doc = "Function Select 52"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL52_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL52_A) -> Self { + variant as _ + } +} +impl FSEL52_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL52_A { + match self.bits { + 0 => FSEL52_A::INPUT, + 1 => FSEL52_A::OUTPUT, + 4 => FSEL52_A::RESERVED0, + 5 => FSEL52_A::RESERVED1, + 6 => FSEL52_A::RESERVED2, + 7 => FSEL52_A::SD1_DAT2, + 3 => FSEL52_A::RESERVED4, + 2 => FSEL52_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL52_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL52_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL52_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL52_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL52_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL52_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL52_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL52_A::RESERVED5 + } +} +#[doc = "Field `FSEL52` writer - Function Select 52"] +pub type FSEL52_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL52_A, 3, O>; +impl<'a, const O: u8> FSEL52_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL52_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL52_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL52_A::SD1_DAT2) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED5) + } +} +#[doc = "Field `FSEL53` reader - Function Select 53"] +pub type FSEL53_R = crate::FieldReader; +#[doc = "Function Select 53"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL53_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL53_A) -> Self { + variant as _ + } +} +impl FSEL53_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL53_A { + match self.bits { + 0 => FSEL53_A::INPUT, + 1 => FSEL53_A::OUTPUT, + 4 => FSEL53_A::RESERVED0, + 5 => FSEL53_A::RESERVED1, + 6 => FSEL53_A::RESERVED2, + 7 => FSEL53_A::SD1_DAT3, + 3 => FSEL53_A::RESERVED4, + 2 => FSEL53_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL53_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL53_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL53_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL53_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL53_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL53_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL53_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL53_A::RESERVED5 + } +} +#[doc = "Field `FSEL53` writer - Function Select 53"] +pub type FSEL53_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL53_A, 3, O>; +impl<'a, const O: u8> FSEL53_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL53_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL53_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL53_A::SD1_DAT3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 50"] + #[inline(always)] + pub fn fsel50(&self) -> FSEL50_R { + FSEL50_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 51"] + #[inline(always)] + pub fn fsel51(&self) -> FSEL51_R { + FSEL51_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 52"] + #[inline(always)] + pub fn fsel52(&self) -> FSEL52_R { + FSEL52_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 53"] + #[inline(always)] + pub fn fsel53(&self) -> FSEL53_R { + FSEL53_R::new(((self.bits >> 9) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 50"] + #[inline(always)] + #[must_use] + pub fn fsel50(&mut self) -> FSEL50_W<0> { + FSEL50_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 51"] + #[inline(always)] + #[must_use] + pub fn fsel51(&mut self) -> FSEL51_W<3> { + FSEL51_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 52"] + #[inline(always)] + #[must_use] + pub fn fsel52(&mut self) -> FSEL52_W<6> { + FSEL52_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 53"] + #[inline(always)] + #[must_use] + pub fn fsel53(&mut self) -> FSEL53_W<9> { + FSEL53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel5](index.html) module"] +pub struct GPFSEL5_SPEC; +impl crate::RegisterSpec for GPFSEL5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel5::R](R) reader structure"] +impl crate::Readable for GPFSEL5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel5::W](W) writer structure"] +impl crate::Writable for GPFSEL5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gphen0.rs b/crates/bcm2835-lpa/src/gpio/gphen0.rs new file mode 100644 index 0000000..b45a414 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gphen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPHEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPHEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HEN0` reader - High detect enabled 0"] +pub type HEN0_R = crate::BitReader; +#[doc = "Field `HEN0` writer - High detect enabled 0"] +pub type HEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN1` reader - High detect enabled 1"] +pub type HEN1_R = crate::BitReader; +#[doc = "Field `HEN1` writer - High detect enabled 1"] +pub type HEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN2` reader - High detect enabled 2"] +pub type HEN2_R = crate::BitReader; +#[doc = "Field `HEN2` writer - High detect enabled 2"] +pub type HEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN3` reader - High detect enabled 3"] +pub type HEN3_R = crate::BitReader; +#[doc = "Field `HEN3` writer - High detect enabled 3"] +pub type HEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN4` reader - High detect enabled 4"] +pub type HEN4_R = crate::BitReader; +#[doc = "Field `HEN4` writer - High detect enabled 4"] +pub type HEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN5` reader - High detect enabled 5"] +pub type HEN5_R = crate::BitReader; +#[doc = "Field `HEN5` writer - High detect enabled 5"] +pub type HEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN6` reader - High detect enabled 6"] +pub type HEN6_R = crate::BitReader; +#[doc = "Field `HEN6` writer - High detect enabled 6"] +pub type HEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN7` reader - High detect enabled 7"] +pub type HEN7_R = crate::BitReader; +#[doc = "Field `HEN7` writer - High detect enabled 7"] +pub type HEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN8` reader - High detect enabled 8"] +pub type HEN8_R = crate::BitReader; +#[doc = "Field `HEN8` writer - High detect enabled 8"] +pub type HEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN9` reader - High detect enabled 9"] +pub type HEN9_R = crate::BitReader; +#[doc = "Field `HEN9` writer - High detect enabled 9"] +pub type HEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN10` reader - High detect enabled 10"] +pub type HEN10_R = crate::BitReader; +#[doc = "Field `HEN10` writer - High detect enabled 10"] +pub type HEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN11` reader - High detect enabled 11"] +pub type HEN11_R = crate::BitReader; +#[doc = "Field `HEN11` writer - High detect enabled 11"] +pub type HEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN12` reader - High detect enabled 12"] +pub type HEN12_R = crate::BitReader; +#[doc = "Field `HEN12` writer - High detect enabled 12"] +pub type HEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN13` reader - High detect enabled 13"] +pub type HEN13_R = crate::BitReader; +#[doc = "Field `HEN13` writer - High detect enabled 13"] +pub type HEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN14` reader - High detect enabled 14"] +pub type HEN14_R = crate::BitReader; +#[doc = "Field `HEN14` writer - High detect enabled 14"] +pub type HEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN15` reader - High detect enabled 15"] +pub type HEN15_R = crate::BitReader; +#[doc = "Field `HEN15` writer - High detect enabled 15"] +pub type HEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN16` reader - High detect enabled 16"] +pub type HEN16_R = crate::BitReader; +#[doc = "Field `HEN16` writer - High detect enabled 16"] +pub type HEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN17` reader - High detect enabled 17"] +pub type HEN17_R = crate::BitReader; +#[doc = "Field `HEN17` writer - High detect enabled 17"] +pub type HEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN18` reader - High detect enabled 18"] +pub type HEN18_R = crate::BitReader; +#[doc = "Field `HEN18` writer - High detect enabled 18"] +pub type HEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN19` reader - High detect enabled 19"] +pub type HEN19_R = crate::BitReader; +#[doc = "Field `HEN19` writer - High detect enabled 19"] +pub type HEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN20` reader - High detect enabled 20"] +pub type HEN20_R = crate::BitReader; +#[doc = "Field `HEN20` writer - High detect enabled 20"] +pub type HEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN21` reader - High detect enabled 21"] +pub type HEN21_R = crate::BitReader; +#[doc = "Field `HEN21` writer - High detect enabled 21"] +pub type HEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN22` reader - High detect enabled 22"] +pub type HEN22_R = crate::BitReader; +#[doc = "Field `HEN22` writer - High detect enabled 22"] +pub type HEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN23` reader - High detect enabled 23"] +pub type HEN23_R = crate::BitReader; +#[doc = "Field `HEN23` writer - High detect enabled 23"] +pub type HEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN24` reader - High detect enabled 24"] +pub type HEN24_R = crate::BitReader; +#[doc = "Field `HEN24` writer - High detect enabled 24"] +pub type HEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN25` reader - High detect enabled 25"] +pub type HEN25_R = crate::BitReader; +#[doc = "Field `HEN25` writer - High detect enabled 25"] +pub type HEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN26` reader - High detect enabled 26"] +pub type HEN26_R = crate::BitReader; +#[doc = "Field `HEN26` writer - High detect enabled 26"] +pub type HEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN27` reader - High detect enabled 27"] +pub type HEN27_R = crate::BitReader; +#[doc = "Field `HEN27` writer - High detect enabled 27"] +pub type HEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN28` reader - High detect enabled 28"] +pub type HEN28_R = crate::BitReader; +#[doc = "Field `HEN28` writer - High detect enabled 28"] +pub type HEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN29` reader - High detect enabled 29"] +pub type HEN29_R = crate::BitReader; +#[doc = "Field `HEN29` writer - High detect enabled 29"] +pub type HEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN30` reader - High detect enabled 30"] +pub type HEN30_R = crate::BitReader; +#[doc = "Field `HEN30` writer - High detect enabled 30"] +pub type HEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN31` reader - High detect enabled 31"] +pub type HEN31_R = crate::BitReader; +#[doc = "Field `HEN31` writer - High detect enabled 31"] +pub type HEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - High detect enabled 0"] + #[inline(always)] + pub fn hen0(&self) -> HEN0_R { + HEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - High detect enabled 1"] + #[inline(always)] + pub fn hen1(&self) -> HEN1_R { + HEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - High detect enabled 2"] + #[inline(always)] + pub fn hen2(&self) -> HEN2_R { + HEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - High detect enabled 3"] + #[inline(always)] + pub fn hen3(&self) -> HEN3_R { + HEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - High detect enabled 4"] + #[inline(always)] + pub fn hen4(&self) -> HEN4_R { + HEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - High detect enabled 5"] + #[inline(always)] + pub fn hen5(&self) -> HEN5_R { + HEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - High detect enabled 6"] + #[inline(always)] + pub fn hen6(&self) -> HEN6_R { + HEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - High detect enabled 7"] + #[inline(always)] + pub fn hen7(&self) -> HEN7_R { + HEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - High detect enabled 8"] + #[inline(always)] + pub fn hen8(&self) -> HEN8_R { + HEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High detect enabled 9"] + #[inline(always)] + pub fn hen9(&self) -> HEN9_R { + HEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High detect enabled 10"] + #[inline(always)] + pub fn hen10(&self) -> HEN10_R { + HEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - High detect enabled 11"] + #[inline(always)] + pub fn hen11(&self) -> HEN11_R { + HEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - High detect enabled 12"] + #[inline(always)] + pub fn hen12(&self) -> HEN12_R { + HEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - High detect enabled 13"] + #[inline(always)] + pub fn hen13(&self) -> HEN13_R { + HEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High detect enabled 14"] + #[inline(always)] + pub fn hen14(&self) -> HEN14_R { + HEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - High detect enabled 15"] + #[inline(always)] + pub fn hen15(&self) -> HEN15_R { + HEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High detect enabled 16"] + #[inline(always)] + pub fn hen16(&self) -> HEN16_R { + HEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - High detect enabled 17"] + #[inline(always)] + pub fn hen17(&self) -> HEN17_R { + HEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - High detect enabled 18"] + #[inline(always)] + pub fn hen18(&self) -> HEN18_R { + HEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - High detect enabled 19"] + #[inline(always)] + pub fn hen19(&self) -> HEN19_R { + HEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - High detect enabled 20"] + #[inline(always)] + pub fn hen20(&self) -> HEN20_R { + HEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - High detect enabled 21"] + #[inline(always)] + pub fn hen21(&self) -> HEN21_R { + HEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - High detect enabled 22"] + #[inline(always)] + pub fn hen22(&self) -> HEN22_R { + HEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - High detect enabled 23"] + #[inline(always)] + pub fn hen23(&self) -> HEN23_R { + HEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - High detect enabled 24"] + #[inline(always)] + pub fn hen24(&self) -> HEN24_R { + HEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - High detect enabled 25"] + #[inline(always)] + pub fn hen25(&self) -> HEN25_R { + HEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - High detect enabled 26"] + #[inline(always)] + pub fn hen26(&self) -> HEN26_R { + HEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - High detect enabled 27"] + #[inline(always)] + pub fn hen27(&self) -> HEN27_R { + HEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - High detect enabled 28"] + #[inline(always)] + pub fn hen28(&self) -> HEN28_R { + HEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - High detect enabled 29"] + #[inline(always)] + pub fn hen29(&self) -> HEN29_R { + HEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - High detect enabled 30"] + #[inline(always)] + pub fn hen30(&self) -> HEN30_R { + HEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - High detect enabled 31"] + #[inline(always)] + pub fn hen31(&self) -> HEN31_R { + HEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - High detect enabled 0"] + #[inline(always)] + #[must_use] + pub fn hen0(&mut self) -> HEN0_W<0> { + HEN0_W::new(self) + } + #[doc = "Bit 1 - High detect enabled 1"] + #[inline(always)] + #[must_use] + pub fn hen1(&mut self) -> HEN1_W<1> { + HEN1_W::new(self) + } + #[doc = "Bit 2 - High detect enabled 2"] + #[inline(always)] + #[must_use] + pub fn hen2(&mut self) -> HEN2_W<2> { + HEN2_W::new(self) + } + #[doc = "Bit 3 - High detect enabled 3"] + #[inline(always)] + #[must_use] + pub fn hen3(&mut self) -> HEN3_W<3> { + HEN3_W::new(self) + } + #[doc = "Bit 4 - High detect enabled 4"] + #[inline(always)] + #[must_use] + pub fn hen4(&mut self) -> HEN4_W<4> { + HEN4_W::new(self) + } + #[doc = "Bit 5 - High detect enabled 5"] + #[inline(always)] + #[must_use] + pub fn hen5(&mut self) -> HEN5_W<5> { + HEN5_W::new(self) + } + #[doc = "Bit 6 - High detect enabled 6"] + #[inline(always)] + #[must_use] + pub fn hen6(&mut self) -> HEN6_W<6> { + HEN6_W::new(self) + } + #[doc = "Bit 7 - High detect enabled 7"] + #[inline(always)] + #[must_use] + pub fn hen7(&mut self) -> HEN7_W<7> { + HEN7_W::new(self) + } + #[doc = "Bit 8 - High detect enabled 8"] + #[inline(always)] + #[must_use] + pub fn hen8(&mut self) -> HEN8_W<8> { + HEN8_W::new(self) + } + #[doc = "Bit 9 - High detect enabled 9"] + #[inline(always)] + #[must_use] + pub fn hen9(&mut self) -> HEN9_W<9> { + HEN9_W::new(self) + } + #[doc = "Bit 10 - High detect enabled 10"] + #[inline(always)] + #[must_use] + pub fn hen10(&mut self) -> HEN10_W<10> { + HEN10_W::new(self) + } + #[doc = "Bit 11 - High detect enabled 11"] + #[inline(always)] + #[must_use] + pub fn hen11(&mut self) -> HEN11_W<11> { + HEN11_W::new(self) + } + #[doc = "Bit 12 - High detect enabled 12"] + #[inline(always)] + #[must_use] + pub fn hen12(&mut self) -> HEN12_W<12> { + HEN12_W::new(self) + } + #[doc = "Bit 13 - High detect enabled 13"] + #[inline(always)] + #[must_use] + pub fn hen13(&mut self) -> HEN13_W<13> { + HEN13_W::new(self) + } + #[doc = "Bit 14 - High detect enabled 14"] + #[inline(always)] + #[must_use] + pub fn hen14(&mut self) -> HEN14_W<14> { + HEN14_W::new(self) + } + #[doc = "Bit 15 - High detect enabled 15"] + #[inline(always)] + #[must_use] + pub fn hen15(&mut self) -> HEN15_W<15> { + HEN15_W::new(self) + } + #[doc = "Bit 16 - High detect enabled 16"] + #[inline(always)] + #[must_use] + pub fn hen16(&mut self) -> HEN16_W<16> { + HEN16_W::new(self) + } + #[doc = "Bit 17 - High detect enabled 17"] + #[inline(always)] + #[must_use] + pub fn hen17(&mut self) -> HEN17_W<17> { + HEN17_W::new(self) + } + #[doc = "Bit 18 - High detect enabled 18"] + #[inline(always)] + #[must_use] + pub fn hen18(&mut self) -> HEN18_W<18> { + HEN18_W::new(self) + } + #[doc = "Bit 19 - High detect enabled 19"] + #[inline(always)] + #[must_use] + pub fn hen19(&mut self) -> HEN19_W<19> { + HEN19_W::new(self) + } + #[doc = "Bit 20 - High detect enabled 20"] + #[inline(always)] + #[must_use] + pub fn hen20(&mut self) -> HEN20_W<20> { + HEN20_W::new(self) + } + #[doc = "Bit 21 - High detect enabled 21"] + #[inline(always)] + #[must_use] + pub fn hen21(&mut self) -> HEN21_W<21> { + HEN21_W::new(self) + } + #[doc = "Bit 22 - High detect enabled 22"] + #[inline(always)] + #[must_use] + pub fn hen22(&mut self) -> HEN22_W<22> { + HEN22_W::new(self) + } + #[doc = "Bit 23 - High detect enabled 23"] + #[inline(always)] + #[must_use] + pub fn hen23(&mut self) -> HEN23_W<23> { + HEN23_W::new(self) + } + #[doc = "Bit 24 - High detect enabled 24"] + #[inline(always)] + #[must_use] + pub fn hen24(&mut self) -> HEN24_W<24> { + HEN24_W::new(self) + } + #[doc = "Bit 25 - High detect enabled 25"] + #[inline(always)] + #[must_use] + pub fn hen25(&mut self) -> HEN25_W<25> { + HEN25_W::new(self) + } + #[doc = "Bit 26 - High detect enabled 26"] + #[inline(always)] + #[must_use] + pub fn hen26(&mut self) -> HEN26_W<26> { + HEN26_W::new(self) + } + #[doc = "Bit 27 - High detect enabled 27"] + #[inline(always)] + #[must_use] + pub fn hen27(&mut self) -> HEN27_W<27> { + HEN27_W::new(self) + } + #[doc = "Bit 28 - High detect enabled 28"] + #[inline(always)] + #[must_use] + pub fn hen28(&mut self) -> HEN28_W<28> { + HEN28_W::new(self) + } + #[doc = "Bit 29 - High detect enabled 29"] + #[inline(always)] + #[must_use] + pub fn hen29(&mut self) -> HEN29_W<29> { + HEN29_W::new(self) + } + #[doc = "Bit 30 - High detect enabled 30"] + #[inline(always)] + #[must_use] + pub fn hen30(&mut self) -> HEN30_W<30> { + HEN30_W::new(self) + } + #[doc = "Bit 31 - High detect enabled 31"] + #[inline(always)] + #[must_use] + pub fn hen31(&mut self) -> HEN31_W<31> { + HEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin High Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen0](index.html) module"] +pub struct GPHEN0_SPEC; +impl crate::RegisterSpec for GPHEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gphen0::R](R) reader structure"] +impl crate::Readable for GPHEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gphen0::W](W) writer structure"] +impl crate::Writable for GPHEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gphen1.rs b/crates/bcm2835-lpa/src/gpio/gphen1.rs new file mode 100644 index 0000000..23c512c --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gphen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPHEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPHEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HEN32` reader - High detect enabled 32"] +pub type HEN32_R = crate::BitReader; +#[doc = "Field `HEN32` writer - High detect enabled 32"] +pub type HEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN33` reader - High detect enabled 33"] +pub type HEN33_R = crate::BitReader; +#[doc = "Field `HEN33` writer - High detect enabled 33"] +pub type HEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN34` reader - High detect enabled 34"] +pub type HEN34_R = crate::BitReader; +#[doc = "Field `HEN34` writer - High detect enabled 34"] +pub type HEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN35` reader - High detect enabled 35"] +pub type HEN35_R = crate::BitReader; +#[doc = "Field `HEN35` writer - High detect enabled 35"] +pub type HEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN36` reader - High detect enabled 36"] +pub type HEN36_R = crate::BitReader; +#[doc = "Field `HEN36` writer - High detect enabled 36"] +pub type HEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN37` reader - High detect enabled 37"] +pub type HEN37_R = crate::BitReader; +#[doc = "Field `HEN37` writer - High detect enabled 37"] +pub type HEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN38` reader - High detect enabled 38"] +pub type HEN38_R = crate::BitReader; +#[doc = "Field `HEN38` writer - High detect enabled 38"] +pub type HEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN39` reader - High detect enabled 39"] +pub type HEN39_R = crate::BitReader; +#[doc = "Field `HEN39` writer - High detect enabled 39"] +pub type HEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN40` reader - High detect enabled 40"] +pub type HEN40_R = crate::BitReader; +#[doc = "Field `HEN40` writer - High detect enabled 40"] +pub type HEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN41` reader - High detect enabled 41"] +pub type HEN41_R = crate::BitReader; +#[doc = "Field `HEN41` writer - High detect enabled 41"] +pub type HEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN42` reader - High detect enabled 42"] +pub type HEN42_R = crate::BitReader; +#[doc = "Field `HEN42` writer - High detect enabled 42"] +pub type HEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN43` reader - High detect enabled 43"] +pub type HEN43_R = crate::BitReader; +#[doc = "Field `HEN43` writer - High detect enabled 43"] +pub type HEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN44` reader - High detect enabled 44"] +pub type HEN44_R = crate::BitReader; +#[doc = "Field `HEN44` writer - High detect enabled 44"] +pub type HEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN45` reader - High detect enabled 45"] +pub type HEN45_R = crate::BitReader; +#[doc = "Field `HEN45` writer - High detect enabled 45"] +pub type HEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN46` reader - High detect enabled 46"] +pub type HEN46_R = crate::BitReader; +#[doc = "Field `HEN46` writer - High detect enabled 46"] +pub type HEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN47` reader - High detect enabled 47"] +pub type HEN47_R = crate::BitReader; +#[doc = "Field `HEN47` writer - High detect enabled 47"] +pub type HEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN48` reader - High detect enabled 48"] +pub type HEN48_R = crate::BitReader; +#[doc = "Field `HEN48` writer - High detect enabled 48"] +pub type HEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN49` reader - High detect enabled 49"] +pub type HEN49_R = crate::BitReader; +#[doc = "Field `HEN49` writer - High detect enabled 49"] +pub type HEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN50` reader - High detect enabled 50"] +pub type HEN50_R = crate::BitReader; +#[doc = "Field `HEN50` writer - High detect enabled 50"] +pub type HEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN51` reader - High detect enabled 51"] +pub type HEN51_R = crate::BitReader; +#[doc = "Field `HEN51` writer - High detect enabled 51"] +pub type HEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN52` reader - High detect enabled 52"] +pub type HEN52_R = crate::BitReader; +#[doc = "Field `HEN52` writer - High detect enabled 52"] +pub type HEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN53` reader - High detect enabled 53"] +pub type HEN53_R = crate::BitReader; +#[doc = "Field `HEN53` writer - High detect enabled 53"] +pub type HEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - High detect enabled 32"] + #[inline(always)] + pub fn hen32(&self) -> HEN32_R { + HEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - High detect enabled 33"] + #[inline(always)] + pub fn hen33(&self) -> HEN33_R { + HEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - High detect enabled 34"] + #[inline(always)] + pub fn hen34(&self) -> HEN34_R { + HEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - High detect enabled 35"] + #[inline(always)] + pub fn hen35(&self) -> HEN35_R { + HEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - High detect enabled 36"] + #[inline(always)] + pub fn hen36(&self) -> HEN36_R { + HEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - High detect enabled 37"] + #[inline(always)] + pub fn hen37(&self) -> HEN37_R { + HEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - High detect enabled 38"] + #[inline(always)] + pub fn hen38(&self) -> HEN38_R { + HEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - High detect enabled 39"] + #[inline(always)] + pub fn hen39(&self) -> HEN39_R { + HEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - High detect enabled 40"] + #[inline(always)] + pub fn hen40(&self) -> HEN40_R { + HEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High detect enabled 41"] + #[inline(always)] + pub fn hen41(&self) -> HEN41_R { + HEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High detect enabled 42"] + #[inline(always)] + pub fn hen42(&self) -> HEN42_R { + HEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - High detect enabled 43"] + #[inline(always)] + pub fn hen43(&self) -> HEN43_R { + HEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - High detect enabled 44"] + #[inline(always)] + pub fn hen44(&self) -> HEN44_R { + HEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - High detect enabled 45"] + #[inline(always)] + pub fn hen45(&self) -> HEN45_R { + HEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High detect enabled 46"] + #[inline(always)] + pub fn hen46(&self) -> HEN46_R { + HEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - High detect enabled 47"] + #[inline(always)] + pub fn hen47(&self) -> HEN47_R { + HEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High detect enabled 48"] + #[inline(always)] + pub fn hen48(&self) -> HEN48_R { + HEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - High detect enabled 49"] + #[inline(always)] + pub fn hen49(&self) -> HEN49_R { + HEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - High detect enabled 50"] + #[inline(always)] + pub fn hen50(&self) -> HEN50_R { + HEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - High detect enabled 51"] + #[inline(always)] + pub fn hen51(&self) -> HEN51_R { + HEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - High detect enabled 52"] + #[inline(always)] + pub fn hen52(&self) -> HEN52_R { + HEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - High detect enabled 53"] + #[inline(always)] + pub fn hen53(&self) -> HEN53_R { + HEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - High detect enabled 32"] + #[inline(always)] + #[must_use] + pub fn hen32(&mut self) -> HEN32_W<0> { + HEN32_W::new(self) + } + #[doc = "Bit 1 - High detect enabled 33"] + #[inline(always)] + #[must_use] + pub fn hen33(&mut self) -> HEN33_W<1> { + HEN33_W::new(self) + } + #[doc = "Bit 2 - High detect enabled 34"] + #[inline(always)] + #[must_use] + pub fn hen34(&mut self) -> HEN34_W<2> { + HEN34_W::new(self) + } + #[doc = "Bit 3 - High detect enabled 35"] + #[inline(always)] + #[must_use] + pub fn hen35(&mut self) -> HEN35_W<3> { + HEN35_W::new(self) + } + #[doc = "Bit 4 - High detect enabled 36"] + #[inline(always)] + #[must_use] + pub fn hen36(&mut self) -> HEN36_W<4> { + HEN36_W::new(self) + } + #[doc = "Bit 5 - High detect enabled 37"] + #[inline(always)] + #[must_use] + pub fn hen37(&mut self) -> HEN37_W<5> { + HEN37_W::new(self) + } + #[doc = "Bit 6 - High detect enabled 38"] + #[inline(always)] + #[must_use] + pub fn hen38(&mut self) -> HEN38_W<6> { + HEN38_W::new(self) + } + #[doc = "Bit 7 - High detect enabled 39"] + #[inline(always)] + #[must_use] + pub fn hen39(&mut self) -> HEN39_W<7> { + HEN39_W::new(self) + } + #[doc = "Bit 8 - High detect enabled 40"] + #[inline(always)] + #[must_use] + pub fn hen40(&mut self) -> HEN40_W<8> { + HEN40_W::new(self) + } + #[doc = "Bit 9 - High detect enabled 41"] + #[inline(always)] + #[must_use] + pub fn hen41(&mut self) -> HEN41_W<9> { + HEN41_W::new(self) + } + #[doc = "Bit 10 - High detect enabled 42"] + #[inline(always)] + #[must_use] + pub fn hen42(&mut self) -> HEN42_W<10> { + HEN42_W::new(self) + } + #[doc = "Bit 11 - High detect enabled 43"] + #[inline(always)] + #[must_use] + pub fn hen43(&mut self) -> HEN43_W<11> { + HEN43_W::new(self) + } + #[doc = "Bit 12 - High detect enabled 44"] + #[inline(always)] + #[must_use] + pub fn hen44(&mut self) -> HEN44_W<12> { + HEN44_W::new(self) + } + #[doc = "Bit 13 - High detect enabled 45"] + #[inline(always)] + #[must_use] + pub fn hen45(&mut self) -> HEN45_W<13> { + HEN45_W::new(self) + } + #[doc = "Bit 14 - High detect enabled 46"] + #[inline(always)] + #[must_use] + pub fn hen46(&mut self) -> HEN46_W<14> { + HEN46_W::new(self) + } + #[doc = "Bit 15 - High detect enabled 47"] + #[inline(always)] + #[must_use] + pub fn hen47(&mut self) -> HEN47_W<15> { + HEN47_W::new(self) + } + #[doc = "Bit 16 - High detect enabled 48"] + #[inline(always)] + #[must_use] + pub fn hen48(&mut self) -> HEN48_W<16> { + HEN48_W::new(self) + } + #[doc = "Bit 17 - High detect enabled 49"] + #[inline(always)] + #[must_use] + pub fn hen49(&mut self) -> HEN49_W<17> { + HEN49_W::new(self) + } + #[doc = "Bit 18 - High detect enabled 50"] + #[inline(always)] + #[must_use] + pub fn hen50(&mut self) -> HEN50_W<18> { + HEN50_W::new(self) + } + #[doc = "Bit 19 - High detect enabled 51"] + #[inline(always)] + #[must_use] + pub fn hen51(&mut self) -> HEN51_W<19> { + HEN51_W::new(self) + } + #[doc = "Bit 20 - High detect enabled 52"] + #[inline(always)] + #[must_use] + pub fn hen52(&mut self) -> HEN52_W<20> { + HEN52_W::new(self) + } + #[doc = "Bit 21 - High detect enabled 53"] + #[inline(always)] + #[must_use] + pub fn hen53(&mut self) -> HEN53_W<21> { + HEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin High Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen1](index.html) module"] +pub struct GPHEN1_SPEC; +impl crate::RegisterSpec for GPHEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gphen1::R](R) reader structure"] +impl crate::Readable for GPHEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gphen1::W](W) writer structure"] +impl crate::Writable for GPHEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs new file mode 100644 index 0000000..12b55c2 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs @@ -0,0 +1,363 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL0` reader - Resistor select for 0"] +pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; +#[doc = "Resistor select for 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BP_PULL_A { + #[doc = "0: No pull"] + NONE = 0, + #[doc = "1: Pull up"] + UP = 1, + #[doc = "2: Pull down"] + DOWN = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BP_PULL_A) -> Self { + variant as _ + } +} +impl GPIO_PUP_PDN_CNTRL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(BP_PULL_A::NONE), + 1 => Some(BP_PULL_A::UP), + 2 => Some(BP_PULL_A::DOWN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == BP_PULL_A::NONE + } + #[doc = "Checks if the value of the field is `UP`"] + #[inline(always)] + pub fn is_up(&self) -> bool { + *self == BP_PULL_A::UP + } + #[doc = "Checks if the value of the field is `DOWN`"] + #[inline(always)] + pub fn is_down(&self) -> bool { + *self == BP_PULL_A::DOWN + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL0` writer - Resistor select for 0"] +pub type GPIO_PUP_PDN_CNTRL0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG0_SPEC, u8, BP_PULL_A, 2, O>; +impl<'a, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, O> { + #[doc = "No pull"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BP_PULL_A::NONE) + } + #[doc = "Pull up"] + #[inline(always)] + pub fn up(self) -> &'a mut W { + self.variant(BP_PULL_A::UP) + } + #[doc = "Pull down"] + #[inline(always)] + pub fn down(self) -> &'a mut W { + self.variant(BP_PULL_A::DOWN) + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL1` reader - Resistor select for 1"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL1_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL2` reader - Resistor select for 2"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL2_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL3` reader - Resistor select for 3"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL3_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL4` reader - Resistor select for 4"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL4_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL5` reader - Resistor select for 5"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL5_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL6` reader - Resistor select for 6"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL6_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL7` reader - Resistor select for 7"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL7_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL8` reader - Resistor select for 8"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL8_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL9` reader - Resistor select for 9"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL9_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL10` reader - Resistor select for 10"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL10_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL11` reader - Resistor select for 11"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL11_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL12` reader - Resistor select for 12"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL12_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL13` reader - Resistor select for 13"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL13_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL14` reader - Resistor select for 14"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL14_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL15` reader - Resistor select for 15"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL15_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL1` writer - Resistor select for 1"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL1_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL2` writer - Resistor select for 2"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL2_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL3` writer - Resistor select for 3"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL3_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL4` writer - Resistor select for 4"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL4_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL5` writer - Resistor select for 5"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL5_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL6` writer - Resistor select for 6"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL6_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL7` writer - Resistor select for 7"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL7_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL8` writer - Resistor select for 8"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL8_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL9` writer - Resistor select for 9"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL9_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL10` writer - Resistor select for 10"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL10_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL11` writer - Resistor select for 11"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL11_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL12` writer - Resistor select for 12"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL12_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL13` writer - Resistor select for 13"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL13_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL14` writer - Resistor select for 14"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL14_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL15` writer - Resistor select for 15"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL15_W; +impl R { + #[doc = "Bits 0:1 - Resistor select for 0"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl0(&self) -> GPIO_PUP_PDN_CNTRL0_R { + GPIO_PUP_PDN_CNTRL0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 1"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl1(&self) -> GPIO_PUP_PDN_CNTRL1_R { + GPIO_PUP_PDN_CNTRL1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 2"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl2(&self) -> GPIO_PUP_PDN_CNTRL2_R { + GPIO_PUP_PDN_CNTRL2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 3"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl3(&self) -> GPIO_PUP_PDN_CNTRL3_R { + GPIO_PUP_PDN_CNTRL3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 4"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl4(&self) -> GPIO_PUP_PDN_CNTRL4_R { + GPIO_PUP_PDN_CNTRL4_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 5"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl5(&self) -> GPIO_PUP_PDN_CNTRL5_R { + GPIO_PUP_PDN_CNTRL5_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 6"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl6(&self) -> GPIO_PUP_PDN_CNTRL6_R { + GPIO_PUP_PDN_CNTRL6_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 7"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl7(&self) -> GPIO_PUP_PDN_CNTRL7_R { + GPIO_PUP_PDN_CNTRL7_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 8"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl8(&self) -> GPIO_PUP_PDN_CNTRL8_R { + GPIO_PUP_PDN_CNTRL8_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 9"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl9(&self) -> GPIO_PUP_PDN_CNTRL9_R { + GPIO_PUP_PDN_CNTRL9_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 10"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl10(&self) -> GPIO_PUP_PDN_CNTRL10_R { + GPIO_PUP_PDN_CNTRL10_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 11"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl11(&self) -> GPIO_PUP_PDN_CNTRL11_R { + GPIO_PUP_PDN_CNTRL11_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 12"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl12(&self) -> GPIO_PUP_PDN_CNTRL12_R { + GPIO_PUP_PDN_CNTRL12_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 13"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl13(&self) -> GPIO_PUP_PDN_CNTRL13_R { + GPIO_PUP_PDN_CNTRL13_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 14"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl14(&self) -> GPIO_PUP_PDN_CNTRL14_R { + GPIO_PUP_PDN_CNTRL14_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 15"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl15(&self) -> GPIO_PUP_PDN_CNTRL15_R { + GPIO_PUP_PDN_CNTRL15_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 0"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl0(&mut self) -> GPIO_PUP_PDN_CNTRL0_W<0> { + GPIO_PUP_PDN_CNTRL0_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 1"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl1(&mut self) -> GPIO_PUP_PDN_CNTRL1_W<2> { + GPIO_PUP_PDN_CNTRL1_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 2"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl2(&mut self) -> GPIO_PUP_PDN_CNTRL2_W<4> { + GPIO_PUP_PDN_CNTRL2_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 3"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl3(&mut self) -> GPIO_PUP_PDN_CNTRL3_W<6> { + GPIO_PUP_PDN_CNTRL3_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 4"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl4(&mut self) -> GPIO_PUP_PDN_CNTRL4_W<8> { + GPIO_PUP_PDN_CNTRL4_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 5"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl5(&mut self) -> GPIO_PUP_PDN_CNTRL5_W<10> { + GPIO_PUP_PDN_CNTRL5_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 6"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl6(&mut self) -> GPIO_PUP_PDN_CNTRL6_W<12> { + GPIO_PUP_PDN_CNTRL6_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 7"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl7(&mut self) -> GPIO_PUP_PDN_CNTRL7_W<14> { + GPIO_PUP_PDN_CNTRL7_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 8"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl8(&mut self) -> GPIO_PUP_PDN_CNTRL8_W<16> { + GPIO_PUP_PDN_CNTRL8_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 9"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl9(&mut self) -> GPIO_PUP_PDN_CNTRL9_W<18> { + GPIO_PUP_PDN_CNTRL9_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 10"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl10(&mut self) -> GPIO_PUP_PDN_CNTRL10_W<20> { + GPIO_PUP_PDN_CNTRL10_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 11"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl11(&mut self) -> GPIO_PUP_PDN_CNTRL11_W<22> { + GPIO_PUP_PDN_CNTRL11_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 12"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl12(&mut self) -> GPIO_PUP_PDN_CNTRL12_W<24> { + GPIO_PUP_PDN_CNTRL12_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 13"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl13(&mut self) -> GPIO_PUP_PDN_CNTRL13_W<26> { + GPIO_PUP_PDN_CNTRL13_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 14"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl14(&mut self) -> GPIO_PUP_PDN_CNTRL14_W<28> { + GPIO_PUP_PDN_CNTRL14_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 15"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl15(&mut self) -> GPIO_PUP_PDN_CNTRL15_W<30> { + GPIO_PUP_PDN_CNTRL15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg0](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG0_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg0::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg0::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs new file mode 100644 index 0000000..49faec3 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs @@ -0,0 +1,319 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` reader - Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL16_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] +pub type GPIO_PUP_PDN_CNTRL16_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` reader - Resistor select for 17"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL17_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] +pub type GPIO_PUP_PDN_CNTRL17_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` reader - Resistor select for 18"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL18_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] +pub type GPIO_PUP_PDN_CNTRL18_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` reader - Resistor select for 19"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL19_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] +pub type GPIO_PUP_PDN_CNTRL19_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` reader - Resistor select for 20"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL20_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] +pub type GPIO_PUP_PDN_CNTRL20_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` reader - Resistor select for 21"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL21_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] +pub type GPIO_PUP_PDN_CNTRL21_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` reader - Resistor select for 22"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL22_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] +pub type GPIO_PUP_PDN_CNTRL22_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` reader - Resistor select for 23"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL23_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] +pub type GPIO_PUP_PDN_CNTRL23_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` reader - Resistor select for 24"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL24_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] +pub type GPIO_PUP_PDN_CNTRL24_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` reader - Resistor select for 25"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL25_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] +pub type GPIO_PUP_PDN_CNTRL25_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` reader - Resistor select for 26"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL26_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] +pub type GPIO_PUP_PDN_CNTRL26_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` reader - Resistor select for 27"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL27_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] +pub type GPIO_PUP_PDN_CNTRL27_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` reader - Resistor select for 28"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL28_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] +pub type GPIO_PUP_PDN_CNTRL28_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` reader - Resistor select for 29"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL29_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] +pub type GPIO_PUP_PDN_CNTRL29_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` reader - Resistor select for 30"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL30_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] +pub type GPIO_PUP_PDN_CNTRL30_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL31` reader - Resistor select for 31"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL31_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL31` writer - Resistor select for 31"] +pub type GPIO_PUP_PDN_CNTRL31_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 16"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl16(&self) -> GPIO_PUP_PDN_CNTRL16_R { + GPIO_PUP_PDN_CNTRL16_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 17"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl17(&self) -> GPIO_PUP_PDN_CNTRL17_R { + GPIO_PUP_PDN_CNTRL17_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 18"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl18(&self) -> GPIO_PUP_PDN_CNTRL18_R { + GPIO_PUP_PDN_CNTRL18_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 19"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl19(&self) -> GPIO_PUP_PDN_CNTRL19_R { + GPIO_PUP_PDN_CNTRL19_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 20"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl20(&self) -> GPIO_PUP_PDN_CNTRL20_R { + GPIO_PUP_PDN_CNTRL20_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 21"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl21(&self) -> GPIO_PUP_PDN_CNTRL21_R { + GPIO_PUP_PDN_CNTRL21_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 22"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl22(&self) -> GPIO_PUP_PDN_CNTRL22_R { + GPIO_PUP_PDN_CNTRL22_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 23"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl23(&self) -> GPIO_PUP_PDN_CNTRL23_R { + GPIO_PUP_PDN_CNTRL23_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 24"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl24(&self) -> GPIO_PUP_PDN_CNTRL24_R { + GPIO_PUP_PDN_CNTRL24_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 25"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl25(&self) -> GPIO_PUP_PDN_CNTRL25_R { + GPIO_PUP_PDN_CNTRL25_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 26"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl26(&self) -> GPIO_PUP_PDN_CNTRL26_R { + GPIO_PUP_PDN_CNTRL26_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 27"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl27(&self) -> GPIO_PUP_PDN_CNTRL27_R { + GPIO_PUP_PDN_CNTRL27_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 28"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl28(&self) -> GPIO_PUP_PDN_CNTRL28_R { + GPIO_PUP_PDN_CNTRL28_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 29"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl29(&self) -> GPIO_PUP_PDN_CNTRL29_R { + GPIO_PUP_PDN_CNTRL29_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 30"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl30(&self) -> GPIO_PUP_PDN_CNTRL30_R { + GPIO_PUP_PDN_CNTRL30_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 31"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl31(&self) -> GPIO_PUP_PDN_CNTRL31_R { + GPIO_PUP_PDN_CNTRL31_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 16"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl16(&mut self) -> GPIO_PUP_PDN_CNTRL16_W<0> { + GPIO_PUP_PDN_CNTRL16_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 17"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl17(&mut self) -> GPIO_PUP_PDN_CNTRL17_W<2> { + GPIO_PUP_PDN_CNTRL17_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 18"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl18(&mut self) -> GPIO_PUP_PDN_CNTRL18_W<4> { + GPIO_PUP_PDN_CNTRL18_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 19"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl19(&mut self) -> GPIO_PUP_PDN_CNTRL19_W<6> { + GPIO_PUP_PDN_CNTRL19_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 20"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl20(&mut self) -> GPIO_PUP_PDN_CNTRL20_W<8> { + GPIO_PUP_PDN_CNTRL20_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 21"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl21(&mut self) -> GPIO_PUP_PDN_CNTRL21_W<10> { + GPIO_PUP_PDN_CNTRL21_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 22"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl22(&mut self) -> GPIO_PUP_PDN_CNTRL22_W<12> { + GPIO_PUP_PDN_CNTRL22_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 23"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl23(&mut self) -> GPIO_PUP_PDN_CNTRL23_W<14> { + GPIO_PUP_PDN_CNTRL23_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 24"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl24(&mut self) -> GPIO_PUP_PDN_CNTRL24_W<16> { + GPIO_PUP_PDN_CNTRL24_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 25"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl25(&mut self) -> GPIO_PUP_PDN_CNTRL25_W<18> { + GPIO_PUP_PDN_CNTRL25_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 26"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl26(&mut self) -> GPIO_PUP_PDN_CNTRL26_W<20> { + GPIO_PUP_PDN_CNTRL26_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 27"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl27(&mut self) -> GPIO_PUP_PDN_CNTRL27_W<22> { + GPIO_PUP_PDN_CNTRL27_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 28"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl28(&mut self) -> GPIO_PUP_PDN_CNTRL28_W<24> { + GPIO_PUP_PDN_CNTRL28_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 29"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl29(&mut self) -> GPIO_PUP_PDN_CNTRL29_W<26> { + GPIO_PUP_PDN_CNTRL29_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 30"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl30(&mut self) -> GPIO_PUP_PDN_CNTRL30_W<28> { + GPIO_PUP_PDN_CNTRL30_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 31"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl31(&mut self) -> GPIO_PUP_PDN_CNTRL31_W<30> { + GPIO_PUP_PDN_CNTRL31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg1](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG1_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg1::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg1::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs new file mode 100644 index 0000000..67047c9 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs @@ -0,0 +1,319 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` reader - Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL32_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] +pub type GPIO_PUP_PDN_CNTRL32_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` reader - Resistor select for 33"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL33_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] +pub type GPIO_PUP_PDN_CNTRL33_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` reader - Resistor select for 34"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL34_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] +pub type GPIO_PUP_PDN_CNTRL34_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` reader - Resistor select for 35"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL35_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] +pub type GPIO_PUP_PDN_CNTRL35_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` reader - Resistor select for 36"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL36_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] +pub type GPIO_PUP_PDN_CNTRL36_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` reader - Resistor select for 37"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL37_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] +pub type GPIO_PUP_PDN_CNTRL37_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` reader - Resistor select for 38"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL38_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] +pub type GPIO_PUP_PDN_CNTRL38_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` reader - Resistor select for 39"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL39_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] +pub type GPIO_PUP_PDN_CNTRL39_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` reader - Resistor select for 40"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL40_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] +pub type GPIO_PUP_PDN_CNTRL40_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` reader - Resistor select for 41"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL41_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] +pub type GPIO_PUP_PDN_CNTRL41_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` reader - Resistor select for 42"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL42_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] +pub type GPIO_PUP_PDN_CNTRL42_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` reader - Resistor select for 43"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL43_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] +pub type GPIO_PUP_PDN_CNTRL43_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` reader - Resistor select for 44"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL44_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] +pub type GPIO_PUP_PDN_CNTRL44_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` reader - Resistor select for 45"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL45_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] +pub type GPIO_PUP_PDN_CNTRL45_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` reader - Resistor select for 46"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL46_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] +pub type GPIO_PUP_PDN_CNTRL46_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL47` reader - Resistor select for 47"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL47_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL47` writer - Resistor select for 47"] +pub type GPIO_PUP_PDN_CNTRL47_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 32"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl32(&self) -> GPIO_PUP_PDN_CNTRL32_R { + GPIO_PUP_PDN_CNTRL32_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 33"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl33(&self) -> GPIO_PUP_PDN_CNTRL33_R { + GPIO_PUP_PDN_CNTRL33_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 34"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl34(&self) -> GPIO_PUP_PDN_CNTRL34_R { + GPIO_PUP_PDN_CNTRL34_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 35"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl35(&self) -> GPIO_PUP_PDN_CNTRL35_R { + GPIO_PUP_PDN_CNTRL35_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 36"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl36(&self) -> GPIO_PUP_PDN_CNTRL36_R { + GPIO_PUP_PDN_CNTRL36_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 37"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl37(&self) -> GPIO_PUP_PDN_CNTRL37_R { + GPIO_PUP_PDN_CNTRL37_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 38"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl38(&self) -> GPIO_PUP_PDN_CNTRL38_R { + GPIO_PUP_PDN_CNTRL38_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 39"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl39(&self) -> GPIO_PUP_PDN_CNTRL39_R { + GPIO_PUP_PDN_CNTRL39_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 40"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl40(&self) -> GPIO_PUP_PDN_CNTRL40_R { + GPIO_PUP_PDN_CNTRL40_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 41"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl41(&self) -> GPIO_PUP_PDN_CNTRL41_R { + GPIO_PUP_PDN_CNTRL41_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 42"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl42(&self) -> GPIO_PUP_PDN_CNTRL42_R { + GPIO_PUP_PDN_CNTRL42_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 43"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl43(&self) -> GPIO_PUP_PDN_CNTRL43_R { + GPIO_PUP_PDN_CNTRL43_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 44"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl44(&self) -> GPIO_PUP_PDN_CNTRL44_R { + GPIO_PUP_PDN_CNTRL44_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 45"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl45(&self) -> GPIO_PUP_PDN_CNTRL45_R { + GPIO_PUP_PDN_CNTRL45_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 46"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl46(&self) -> GPIO_PUP_PDN_CNTRL46_R { + GPIO_PUP_PDN_CNTRL46_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 47"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl47(&self) -> GPIO_PUP_PDN_CNTRL47_R { + GPIO_PUP_PDN_CNTRL47_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 32"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl32(&mut self) -> GPIO_PUP_PDN_CNTRL32_W<0> { + GPIO_PUP_PDN_CNTRL32_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 33"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl33(&mut self) -> GPIO_PUP_PDN_CNTRL33_W<2> { + GPIO_PUP_PDN_CNTRL33_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 34"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl34(&mut self) -> GPIO_PUP_PDN_CNTRL34_W<4> { + GPIO_PUP_PDN_CNTRL34_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 35"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl35(&mut self) -> GPIO_PUP_PDN_CNTRL35_W<6> { + GPIO_PUP_PDN_CNTRL35_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 36"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl36(&mut self) -> GPIO_PUP_PDN_CNTRL36_W<8> { + GPIO_PUP_PDN_CNTRL36_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 37"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl37(&mut self) -> GPIO_PUP_PDN_CNTRL37_W<10> { + GPIO_PUP_PDN_CNTRL37_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 38"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl38(&mut self) -> GPIO_PUP_PDN_CNTRL38_W<12> { + GPIO_PUP_PDN_CNTRL38_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 39"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl39(&mut self) -> GPIO_PUP_PDN_CNTRL39_W<14> { + GPIO_PUP_PDN_CNTRL39_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 40"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl40(&mut self) -> GPIO_PUP_PDN_CNTRL40_W<16> { + GPIO_PUP_PDN_CNTRL40_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 41"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl41(&mut self) -> GPIO_PUP_PDN_CNTRL41_W<18> { + GPIO_PUP_PDN_CNTRL41_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 42"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl42(&mut self) -> GPIO_PUP_PDN_CNTRL42_W<20> { + GPIO_PUP_PDN_CNTRL42_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 43"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl43(&mut self) -> GPIO_PUP_PDN_CNTRL43_W<22> { + GPIO_PUP_PDN_CNTRL43_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 44"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl44(&mut self) -> GPIO_PUP_PDN_CNTRL44_W<24> { + GPIO_PUP_PDN_CNTRL44_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 45"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl45(&mut self) -> GPIO_PUP_PDN_CNTRL45_W<26> { + GPIO_PUP_PDN_CNTRL45_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 46"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl46(&mut self) -> GPIO_PUP_PDN_CNTRL46_W<28> { + GPIO_PUP_PDN_CNTRL46_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 47"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl47(&mut self) -> GPIO_PUP_PDN_CNTRL47_W<30> { + GPIO_PUP_PDN_CNTRL47_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg2](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG2_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg2::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg2::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs new file mode 100644 index 0000000..61b9329 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs @@ -0,0 +1,159 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` reader - Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL48_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] +pub type GPIO_PUP_PDN_CNTRL48_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` reader - Resistor select for 49"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL49_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] +pub type GPIO_PUP_PDN_CNTRL49_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` reader - Resistor select for 50"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL50_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] +pub type GPIO_PUP_PDN_CNTRL50_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` reader - Resistor select for 51"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL51_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] +pub type GPIO_PUP_PDN_CNTRL51_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` reader - Resistor select for 52"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL52_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] +pub type GPIO_PUP_PDN_CNTRL52_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` reader - Resistor select for 53"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL53_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] +pub type GPIO_PUP_PDN_CNTRL53_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 48"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl48(&self) -> GPIO_PUP_PDN_CNTRL48_R { + GPIO_PUP_PDN_CNTRL48_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 49"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl49(&self) -> GPIO_PUP_PDN_CNTRL49_R { + GPIO_PUP_PDN_CNTRL49_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 50"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl50(&self) -> GPIO_PUP_PDN_CNTRL50_R { + GPIO_PUP_PDN_CNTRL50_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 51"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl51(&self) -> GPIO_PUP_PDN_CNTRL51_R { + GPIO_PUP_PDN_CNTRL51_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 52"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl52(&self) -> GPIO_PUP_PDN_CNTRL52_R { + GPIO_PUP_PDN_CNTRL52_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 53"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl53(&self) -> GPIO_PUP_PDN_CNTRL53_R { + GPIO_PUP_PDN_CNTRL53_R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 48"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl48(&mut self) -> GPIO_PUP_PDN_CNTRL48_W<0> { + GPIO_PUP_PDN_CNTRL48_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 49"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl49(&mut self) -> GPIO_PUP_PDN_CNTRL49_W<2> { + GPIO_PUP_PDN_CNTRL49_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 50"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl50(&mut self) -> GPIO_PUP_PDN_CNTRL50_W<4> { + GPIO_PUP_PDN_CNTRL50_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 51"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl51(&mut self) -> GPIO_PUP_PDN_CNTRL51_W<6> { + GPIO_PUP_PDN_CNTRL51_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 52"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl52(&mut self) -> GPIO_PUP_PDN_CNTRL52_W<8> { + GPIO_PUP_PDN_CNTRL52_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 53"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl53(&mut self) -> GPIO_PUP_PDN_CNTRL53_W<10> { + GPIO_PUP_PDN_CNTRL53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg3](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG3_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg3::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg3::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gplen0.rs b/crates/bcm2835-lpa/src/gpio/gplen0.rs new file mode 100644 index 0000000..54f51bd --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gplen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPLEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPLEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEN0` reader - Low detect enabled 0"] +pub type LEN0_R = crate::BitReader; +#[doc = "Field `LEN0` writer - Low detect enabled 0"] +pub type LEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN1` reader - Low detect enabled 1"] +pub type LEN1_R = crate::BitReader; +#[doc = "Field `LEN1` writer - Low detect enabled 1"] +pub type LEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN2` reader - Low detect enabled 2"] +pub type LEN2_R = crate::BitReader; +#[doc = "Field `LEN2` writer - Low detect enabled 2"] +pub type LEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN3` reader - Low detect enabled 3"] +pub type LEN3_R = crate::BitReader; +#[doc = "Field `LEN3` writer - Low detect enabled 3"] +pub type LEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN4` reader - Low detect enabled 4"] +pub type LEN4_R = crate::BitReader; +#[doc = "Field `LEN4` writer - Low detect enabled 4"] +pub type LEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN5` reader - Low detect enabled 5"] +pub type LEN5_R = crate::BitReader; +#[doc = "Field `LEN5` writer - Low detect enabled 5"] +pub type LEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN6` reader - Low detect enabled 6"] +pub type LEN6_R = crate::BitReader; +#[doc = "Field `LEN6` writer - Low detect enabled 6"] +pub type LEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN7` reader - Low detect enabled 7"] +pub type LEN7_R = crate::BitReader; +#[doc = "Field `LEN7` writer - Low detect enabled 7"] +pub type LEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN8` reader - Low detect enabled 8"] +pub type LEN8_R = crate::BitReader; +#[doc = "Field `LEN8` writer - Low detect enabled 8"] +pub type LEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN9` reader - Low detect enabled 9"] +pub type LEN9_R = crate::BitReader; +#[doc = "Field `LEN9` writer - Low detect enabled 9"] +pub type LEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN10` reader - Low detect enabled 10"] +pub type LEN10_R = crate::BitReader; +#[doc = "Field `LEN10` writer - Low detect enabled 10"] +pub type LEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN11` reader - Low detect enabled 11"] +pub type LEN11_R = crate::BitReader; +#[doc = "Field `LEN11` writer - Low detect enabled 11"] +pub type LEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN12` reader - Low detect enabled 12"] +pub type LEN12_R = crate::BitReader; +#[doc = "Field `LEN12` writer - Low detect enabled 12"] +pub type LEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN13` reader - Low detect enabled 13"] +pub type LEN13_R = crate::BitReader; +#[doc = "Field `LEN13` writer - Low detect enabled 13"] +pub type LEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN14` reader - Low detect enabled 14"] +pub type LEN14_R = crate::BitReader; +#[doc = "Field `LEN14` writer - Low detect enabled 14"] +pub type LEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN15` reader - Low detect enabled 15"] +pub type LEN15_R = crate::BitReader; +#[doc = "Field `LEN15` writer - Low detect enabled 15"] +pub type LEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN16` reader - Low detect enabled 16"] +pub type LEN16_R = crate::BitReader; +#[doc = "Field `LEN16` writer - Low detect enabled 16"] +pub type LEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN17` reader - Low detect enabled 17"] +pub type LEN17_R = crate::BitReader; +#[doc = "Field `LEN17` writer - Low detect enabled 17"] +pub type LEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN18` reader - Low detect enabled 18"] +pub type LEN18_R = crate::BitReader; +#[doc = "Field `LEN18` writer - Low detect enabled 18"] +pub type LEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN19` reader - Low detect enabled 19"] +pub type LEN19_R = crate::BitReader; +#[doc = "Field `LEN19` writer - Low detect enabled 19"] +pub type LEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN20` reader - Low detect enabled 20"] +pub type LEN20_R = crate::BitReader; +#[doc = "Field `LEN20` writer - Low detect enabled 20"] +pub type LEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN21` reader - Low detect enabled 21"] +pub type LEN21_R = crate::BitReader; +#[doc = "Field `LEN21` writer - Low detect enabled 21"] +pub type LEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN22` reader - Low detect enabled 22"] +pub type LEN22_R = crate::BitReader; +#[doc = "Field `LEN22` writer - Low detect enabled 22"] +pub type LEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN23` reader - Low detect enabled 23"] +pub type LEN23_R = crate::BitReader; +#[doc = "Field `LEN23` writer - Low detect enabled 23"] +pub type LEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN24` reader - Low detect enabled 24"] +pub type LEN24_R = crate::BitReader; +#[doc = "Field `LEN24` writer - Low detect enabled 24"] +pub type LEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN25` reader - Low detect enabled 25"] +pub type LEN25_R = crate::BitReader; +#[doc = "Field `LEN25` writer - Low detect enabled 25"] +pub type LEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN26` reader - Low detect enabled 26"] +pub type LEN26_R = crate::BitReader; +#[doc = "Field `LEN26` writer - Low detect enabled 26"] +pub type LEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN27` reader - Low detect enabled 27"] +pub type LEN27_R = crate::BitReader; +#[doc = "Field `LEN27` writer - Low detect enabled 27"] +pub type LEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN28` reader - Low detect enabled 28"] +pub type LEN28_R = crate::BitReader; +#[doc = "Field `LEN28` writer - Low detect enabled 28"] +pub type LEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN29` reader - Low detect enabled 29"] +pub type LEN29_R = crate::BitReader; +#[doc = "Field `LEN29` writer - Low detect enabled 29"] +pub type LEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN30` reader - Low detect enabled 30"] +pub type LEN30_R = crate::BitReader; +#[doc = "Field `LEN30` writer - Low detect enabled 30"] +pub type LEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN31` reader - Low detect enabled 31"] +pub type LEN31_R = crate::BitReader; +#[doc = "Field `LEN31` writer - Low detect enabled 31"] +pub type LEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Low detect enabled 0"] + #[inline(always)] + pub fn len0(&self) -> LEN0_R { + LEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low detect enabled 1"] + #[inline(always)] + pub fn len1(&self) -> LEN1_R { + LEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Low detect enabled 2"] + #[inline(always)] + pub fn len2(&self) -> LEN2_R { + LEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Low detect enabled 3"] + #[inline(always)] + pub fn len3(&self) -> LEN3_R { + LEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Low detect enabled 4"] + #[inline(always)] + pub fn len4(&self) -> LEN4_R { + LEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Low detect enabled 5"] + #[inline(always)] + pub fn len5(&self) -> LEN5_R { + LEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Low detect enabled 6"] + #[inline(always)] + pub fn len6(&self) -> LEN6_R { + LEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Low detect enabled 7"] + #[inline(always)] + pub fn len7(&self) -> LEN7_R { + LEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Low detect enabled 8"] + #[inline(always)] + pub fn len8(&self) -> LEN8_R { + LEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low detect enabled 9"] + #[inline(always)] + pub fn len9(&self) -> LEN9_R { + LEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Low detect enabled 10"] + #[inline(always)] + pub fn len10(&self) -> LEN10_R { + LEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low detect enabled 11"] + #[inline(always)] + pub fn len11(&self) -> LEN11_R { + LEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low detect enabled 12"] + #[inline(always)] + pub fn len12(&self) -> LEN12_R { + LEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Low detect enabled 13"] + #[inline(always)] + pub fn len13(&self) -> LEN13_R { + LEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Low detect enabled 14"] + #[inline(always)] + pub fn len14(&self) -> LEN14_R { + LEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Low detect enabled 15"] + #[inline(always)] + pub fn len15(&self) -> LEN15_R { + LEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Low detect enabled 16"] + #[inline(always)] + pub fn len16(&self) -> LEN16_R { + LEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Low detect enabled 17"] + #[inline(always)] + pub fn len17(&self) -> LEN17_R { + LEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Low detect enabled 18"] + #[inline(always)] + pub fn len18(&self) -> LEN18_R { + LEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Low detect enabled 19"] + #[inline(always)] + pub fn len19(&self) -> LEN19_R { + LEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low detect enabled 20"] + #[inline(always)] + pub fn len20(&self) -> LEN20_R { + LEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Low detect enabled 21"] + #[inline(always)] + pub fn len21(&self) -> LEN21_R { + LEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Low detect enabled 22"] + #[inline(always)] + pub fn len22(&self) -> LEN22_R { + LEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Low detect enabled 23"] + #[inline(always)] + pub fn len23(&self) -> LEN23_R { + LEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Low detect enabled 24"] + #[inline(always)] + pub fn len24(&self) -> LEN24_R { + LEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Low detect enabled 25"] + #[inline(always)] + pub fn len25(&self) -> LEN25_R { + LEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Low detect enabled 26"] + #[inline(always)] + pub fn len26(&self) -> LEN26_R { + LEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Low detect enabled 27"] + #[inline(always)] + pub fn len27(&self) -> LEN27_R { + LEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Low detect enabled 28"] + #[inline(always)] + pub fn len28(&self) -> LEN28_R { + LEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Low detect enabled 29"] + #[inline(always)] + pub fn len29(&self) -> LEN29_R { + LEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Low detect enabled 30"] + #[inline(always)] + pub fn len30(&self) -> LEN30_R { + LEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Low detect enabled 31"] + #[inline(always)] + pub fn len31(&self) -> LEN31_R { + LEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Low detect enabled 0"] + #[inline(always)] + #[must_use] + pub fn len0(&mut self) -> LEN0_W<0> { + LEN0_W::new(self) + } + #[doc = "Bit 1 - Low detect enabled 1"] + #[inline(always)] + #[must_use] + pub fn len1(&mut self) -> LEN1_W<1> { + LEN1_W::new(self) + } + #[doc = "Bit 2 - Low detect enabled 2"] + #[inline(always)] + #[must_use] + pub fn len2(&mut self) -> LEN2_W<2> { + LEN2_W::new(self) + } + #[doc = "Bit 3 - Low detect enabled 3"] + #[inline(always)] + #[must_use] + pub fn len3(&mut self) -> LEN3_W<3> { + LEN3_W::new(self) + } + #[doc = "Bit 4 - Low detect enabled 4"] + #[inline(always)] + #[must_use] + pub fn len4(&mut self) -> LEN4_W<4> { + LEN4_W::new(self) + } + #[doc = "Bit 5 - Low detect enabled 5"] + #[inline(always)] + #[must_use] + pub fn len5(&mut self) -> LEN5_W<5> { + LEN5_W::new(self) + } + #[doc = "Bit 6 - Low detect enabled 6"] + #[inline(always)] + #[must_use] + pub fn len6(&mut self) -> LEN6_W<6> { + LEN6_W::new(self) + } + #[doc = "Bit 7 - Low detect enabled 7"] + #[inline(always)] + #[must_use] + pub fn len7(&mut self) -> LEN7_W<7> { + LEN7_W::new(self) + } + #[doc = "Bit 8 - Low detect enabled 8"] + #[inline(always)] + #[must_use] + pub fn len8(&mut self) -> LEN8_W<8> { + LEN8_W::new(self) + } + #[doc = "Bit 9 - Low detect enabled 9"] + #[inline(always)] + #[must_use] + pub fn len9(&mut self) -> LEN9_W<9> { + LEN9_W::new(self) + } + #[doc = "Bit 10 - Low detect enabled 10"] + #[inline(always)] + #[must_use] + pub fn len10(&mut self) -> LEN10_W<10> { + LEN10_W::new(self) + } + #[doc = "Bit 11 - Low detect enabled 11"] + #[inline(always)] + #[must_use] + pub fn len11(&mut self) -> LEN11_W<11> { + LEN11_W::new(self) + } + #[doc = "Bit 12 - Low detect enabled 12"] + #[inline(always)] + #[must_use] + pub fn len12(&mut self) -> LEN12_W<12> { + LEN12_W::new(self) + } + #[doc = "Bit 13 - Low detect enabled 13"] + #[inline(always)] + #[must_use] + pub fn len13(&mut self) -> LEN13_W<13> { + LEN13_W::new(self) + } + #[doc = "Bit 14 - Low detect enabled 14"] + #[inline(always)] + #[must_use] + pub fn len14(&mut self) -> LEN14_W<14> { + LEN14_W::new(self) + } + #[doc = "Bit 15 - Low detect enabled 15"] + #[inline(always)] + #[must_use] + pub fn len15(&mut self) -> LEN15_W<15> { + LEN15_W::new(self) + } + #[doc = "Bit 16 - Low detect enabled 16"] + #[inline(always)] + #[must_use] + pub fn len16(&mut self) -> LEN16_W<16> { + LEN16_W::new(self) + } + #[doc = "Bit 17 - Low detect enabled 17"] + #[inline(always)] + #[must_use] + pub fn len17(&mut self) -> LEN17_W<17> { + LEN17_W::new(self) + } + #[doc = "Bit 18 - Low detect enabled 18"] + #[inline(always)] + #[must_use] + pub fn len18(&mut self) -> LEN18_W<18> { + LEN18_W::new(self) + } + #[doc = "Bit 19 - Low detect enabled 19"] + #[inline(always)] + #[must_use] + pub fn len19(&mut self) -> LEN19_W<19> { + LEN19_W::new(self) + } + #[doc = "Bit 20 - Low detect enabled 20"] + #[inline(always)] + #[must_use] + pub fn len20(&mut self) -> LEN20_W<20> { + LEN20_W::new(self) + } + #[doc = "Bit 21 - Low detect enabled 21"] + #[inline(always)] + #[must_use] + pub fn len21(&mut self) -> LEN21_W<21> { + LEN21_W::new(self) + } + #[doc = "Bit 22 - Low detect enabled 22"] + #[inline(always)] + #[must_use] + pub fn len22(&mut self) -> LEN22_W<22> { + LEN22_W::new(self) + } + #[doc = "Bit 23 - Low detect enabled 23"] + #[inline(always)] + #[must_use] + pub fn len23(&mut self) -> LEN23_W<23> { + LEN23_W::new(self) + } + #[doc = "Bit 24 - Low detect enabled 24"] + #[inline(always)] + #[must_use] + pub fn len24(&mut self) -> LEN24_W<24> { + LEN24_W::new(self) + } + #[doc = "Bit 25 - Low detect enabled 25"] + #[inline(always)] + #[must_use] + pub fn len25(&mut self) -> LEN25_W<25> { + LEN25_W::new(self) + } + #[doc = "Bit 26 - Low detect enabled 26"] + #[inline(always)] + #[must_use] + pub fn len26(&mut self) -> LEN26_W<26> { + LEN26_W::new(self) + } + #[doc = "Bit 27 - Low detect enabled 27"] + #[inline(always)] + #[must_use] + pub fn len27(&mut self) -> LEN27_W<27> { + LEN27_W::new(self) + } + #[doc = "Bit 28 - Low detect enabled 28"] + #[inline(always)] + #[must_use] + pub fn len28(&mut self) -> LEN28_W<28> { + LEN28_W::new(self) + } + #[doc = "Bit 29 - Low detect enabled 29"] + #[inline(always)] + #[must_use] + pub fn len29(&mut self) -> LEN29_W<29> { + LEN29_W::new(self) + } + #[doc = "Bit 30 - Low detect enabled 30"] + #[inline(always)] + #[must_use] + pub fn len30(&mut self) -> LEN30_W<30> { + LEN30_W::new(self) + } + #[doc = "Bit 31 - Low detect enabled 31"] + #[inline(always)] + #[must_use] + pub fn len31(&mut self) -> LEN31_W<31> { + LEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Low Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen0](index.html) module"] +pub struct GPLEN0_SPEC; +impl crate::RegisterSpec for GPLEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplen0::R](R) reader structure"] +impl crate::Readable for GPLEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gplen0::W](W) writer structure"] +impl crate::Writable for GPLEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gplen1.rs b/crates/bcm2835-lpa/src/gpio/gplen1.rs new file mode 100644 index 0000000..070e4d4 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gplen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPLEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPLEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEN32` reader - Low detect enabled 32"] +pub type LEN32_R = crate::BitReader; +#[doc = "Field `LEN32` writer - Low detect enabled 32"] +pub type LEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN33` reader - Low detect enabled 33"] +pub type LEN33_R = crate::BitReader; +#[doc = "Field `LEN33` writer - Low detect enabled 33"] +pub type LEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN34` reader - Low detect enabled 34"] +pub type LEN34_R = crate::BitReader; +#[doc = "Field `LEN34` writer - Low detect enabled 34"] +pub type LEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN35` reader - Low detect enabled 35"] +pub type LEN35_R = crate::BitReader; +#[doc = "Field `LEN35` writer - Low detect enabled 35"] +pub type LEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN36` reader - Low detect enabled 36"] +pub type LEN36_R = crate::BitReader; +#[doc = "Field `LEN36` writer - Low detect enabled 36"] +pub type LEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN37` reader - Low detect enabled 37"] +pub type LEN37_R = crate::BitReader; +#[doc = "Field `LEN37` writer - Low detect enabled 37"] +pub type LEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN38` reader - Low detect enabled 38"] +pub type LEN38_R = crate::BitReader; +#[doc = "Field `LEN38` writer - Low detect enabled 38"] +pub type LEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN39` reader - Low detect enabled 39"] +pub type LEN39_R = crate::BitReader; +#[doc = "Field `LEN39` writer - Low detect enabled 39"] +pub type LEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN40` reader - Low detect enabled 40"] +pub type LEN40_R = crate::BitReader; +#[doc = "Field `LEN40` writer - Low detect enabled 40"] +pub type LEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN41` reader - Low detect enabled 41"] +pub type LEN41_R = crate::BitReader; +#[doc = "Field `LEN41` writer - Low detect enabled 41"] +pub type LEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN42` reader - Low detect enabled 42"] +pub type LEN42_R = crate::BitReader; +#[doc = "Field `LEN42` writer - Low detect enabled 42"] +pub type LEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN43` reader - Low detect enabled 43"] +pub type LEN43_R = crate::BitReader; +#[doc = "Field `LEN43` writer - Low detect enabled 43"] +pub type LEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN44` reader - Low detect enabled 44"] +pub type LEN44_R = crate::BitReader; +#[doc = "Field `LEN44` writer - Low detect enabled 44"] +pub type LEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN45` reader - Low detect enabled 45"] +pub type LEN45_R = crate::BitReader; +#[doc = "Field `LEN45` writer - Low detect enabled 45"] +pub type LEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN46` reader - Low detect enabled 46"] +pub type LEN46_R = crate::BitReader; +#[doc = "Field `LEN46` writer - Low detect enabled 46"] +pub type LEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN47` reader - Low detect enabled 47"] +pub type LEN47_R = crate::BitReader; +#[doc = "Field `LEN47` writer - Low detect enabled 47"] +pub type LEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN48` reader - Low detect enabled 48"] +pub type LEN48_R = crate::BitReader; +#[doc = "Field `LEN48` writer - Low detect enabled 48"] +pub type LEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN49` reader - Low detect enabled 49"] +pub type LEN49_R = crate::BitReader; +#[doc = "Field `LEN49` writer - Low detect enabled 49"] +pub type LEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN50` reader - Low detect enabled 50"] +pub type LEN50_R = crate::BitReader; +#[doc = "Field `LEN50` writer - Low detect enabled 50"] +pub type LEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN51` reader - Low detect enabled 51"] +pub type LEN51_R = crate::BitReader; +#[doc = "Field `LEN51` writer - Low detect enabled 51"] +pub type LEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN52` reader - Low detect enabled 52"] +pub type LEN52_R = crate::BitReader; +#[doc = "Field `LEN52` writer - Low detect enabled 52"] +pub type LEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN53` reader - Low detect enabled 53"] +pub type LEN53_R = crate::BitReader; +#[doc = "Field `LEN53` writer - Low detect enabled 53"] +pub type LEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Low detect enabled 32"] + #[inline(always)] + pub fn len32(&self) -> LEN32_R { + LEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low detect enabled 33"] + #[inline(always)] + pub fn len33(&self) -> LEN33_R { + LEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Low detect enabled 34"] + #[inline(always)] + pub fn len34(&self) -> LEN34_R { + LEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Low detect enabled 35"] + #[inline(always)] + pub fn len35(&self) -> LEN35_R { + LEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Low detect enabled 36"] + #[inline(always)] + pub fn len36(&self) -> LEN36_R { + LEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Low detect enabled 37"] + #[inline(always)] + pub fn len37(&self) -> LEN37_R { + LEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Low detect enabled 38"] + #[inline(always)] + pub fn len38(&self) -> LEN38_R { + LEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Low detect enabled 39"] + #[inline(always)] + pub fn len39(&self) -> LEN39_R { + LEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Low detect enabled 40"] + #[inline(always)] + pub fn len40(&self) -> LEN40_R { + LEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low detect enabled 41"] + #[inline(always)] + pub fn len41(&self) -> LEN41_R { + LEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Low detect enabled 42"] + #[inline(always)] + pub fn len42(&self) -> LEN42_R { + LEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low detect enabled 43"] + #[inline(always)] + pub fn len43(&self) -> LEN43_R { + LEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low detect enabled 44"] + #[inline(always)] + pub fn len44(&self) -> LEN44_R { + LEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Low detect enabled 45"] + #[inline(always)] + pub fn len45(&self) -> LEN45_R { + LEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Low detect enabled 46"] + #[inline(always)] + pub fn len46(&self) -> LEN46_R { + LEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Low detect enabled 47"] + #[inline(always)] + pub fn len47(&self) -> LEN47_R { + LEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Low detect enabled 48"] + #[inline(always)] + pub fn len48(&self) -> LEN48_R { + LEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Low detect enabled 49"] + #[inline(always)] + pub fn len49(&self) -> LEN49_R { + LEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Low detect enabled 50"] + #[inline(always)] + pub fn len50(&self) -> LEN50_R { + LEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Low detect enabled 51"] + #[inline(always)] + pub fn len51(&self) -> LEN51_R { + LEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low detect enabled 52"] + #[inline(always)] + pub fn len52(&self) -> LEN52_R { + LEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Low detect enabled 53"] + #[inline(always)] + pub fn len53(&self) -> LEN53_R { + LEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Low detect enabled 32"] + #[inline(always)] + #[must_use] + pub fn len32(&mut self) -> LEN32_W<0> { + LEN32_W::new(self) + } + #[doc = "Bit 1 - Low detect enabled 33"] + #[inline(always)] + #[must_use] + pub fn len33(&mut self) -> LEN33_W<1> { + LEN33_W::new(self) + } + #[doc = "Bit 2 - Low detect enabled 34"] + #[inline(always)] + #[must_use] + pub fn len34(&mut self) -> LEN34_W<2> { + LEN34_W::new(self) + } + #[doc = "Bit 3 - Low detect enabled 35"] + #[inline(always)] + #[must_use] + pub fn len35(&mut self) -> LEN35_W<3> { + LEN35_W::new(self) + } + #[doc = "Bit 4 - Low detect enabled 36"] + #[inline(always)] + #[must_use] + pub fn len36(&mut self) -> LEN36_W<4> { + LEN36_W::new(self) + } + #[doc = "Bit 5 - Low detect enabled 37"] + #[inline(always)] + #[must_use] + pub fn len37(&mut self) -> LEN37_W<5> { + LEN37_W::new(self) + } + #[doc = "Bit 6 - Low detect enabled 38"] + #[inline(always)] + #[must_use] + pub fn len38(&mut self) -> LEN38_W<6> { + LEN38_W::new(self) + } + #[doc = "Bit 7 - Low detect enabled 39"] + #[inline(always)] + #[must_use] + pub fn len39(&mut self) -> LEN39_W<7> { + LEN39_W::new(self) + } + #[doc = "Bit 8 - Low detect enabled 40"] + #[inline(always)] + #[must_use] + pub fn len40(&mut self) -> LEN40_W<8> { + LEN40_W::new(self) + } + #[doc = "Bit 9 - Low detect enabled 41"] + #[inline(always)] + #[must_use] + pub fn len41(&mut self) -> LEN41_W<9> { + LEN41_W::new(self) + } + #[doc = "Bit 10 - Low detect enabled 42"] + #[inline(always)] + #[must_use] + pub fn len42(&mut self) -> LEN42_W<10> { + LEN42_W::new(self) + } + #[doc = "Bit 11 - Low detect enabled 43"] + #[inline(always)] + #[must_use] + pub fn len43(&mut self) -> LEN43_W<11> { + LEN43_W::new(self) + } + #[doc = "Bit 12 - Low detect enabled 44"] + #[inline(always)] + #[must_use] + pub fn len44(&mut self) -> LEN44_W<12> { + LEN44_W::new(self) + } + #[doc = "Bit 13 - Low detect enabled 45"] + #[inline(always)] + #[must_use] + pub fn len45(&mut self) -> LEN45_W<13> { + LEN45_W::new(self) + } + #[doc = "Bit 14 - Low detect enabled 46"] + #[inline(always)] + #[must_use] + pub fn len46(&mut self) -> LEN46_W<14> { + LEN46_W::new(self) + } + #[doc = "Bit 15 - Low detect enabled 47"] + #[inline(always)] + #[must_use] + pub fn len47(&mut self) -> LEN47_W<15> { + LEN47_W::new(self) + } + #[doc = "Bit 16 - Low detect enabled 48"] + #[inline(always)] + #[must_use] + pub fn len48(&mut self) -> LEN48_W<16> { + LEN48_W::new(self) + } + #[doc = "Bit 17 - Low detect enabled 49"] + #[inline(always)] + #[must_use] + pub fn len49(&mut self) -> LEN49_W<17> { + LEN49_W::new(self) + } + #[doc = "Bit 18 - Low detect enabled 50"] + #[inline(always)] + #[must_use] + pub fn len50(&mut self) -> LEN50_W<18> { + LEN50_W::new(self) + } + #[doc = "Bit 19 - Low detect enabled 51"] + #[inline(always)] + #[must_use] + pub fn len51(&mut self) -> LEN51_W<19> { + LEN51_W::new(self) + } + #[doc = "Bit 20 - Low detect enabled 52"] + #[inline(always)] + #[must_use] + pub fn len52(&mut self) -> LEN52_W<20> { + LEN52_W::new(self) + } + #[doc = "Bit 21 - Low detect enabled 53"] + #[inline(always)] + #[must_use] + pub fn len53(&mut self) -> LEN53_W<21> { + LEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Low Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen1](index.html) module"] +pub struct GPLEN1_SPEC; +impl crate::RegisterSpec for GPLEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplen1::R](R) reader structure"] +impl crate::Readable for GPLEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gplen1::W](W) writer structure"] +impl crate::Writable for GPLEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gplev0.rs b/crates/bcm2835-lpa/src/gpio/gplev0.rs new file mode 100644 index 0000000..e6f9b94 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gplev0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `GPLEV0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LEV0` reader - Level 0"] +pub type LEV0_R = crate::BitReader; +#[doc = "Field `LEV1` reader - Level 1"] +pub type LEV1_R = crate::BitReader; +#[doc = "Field `LEV2` reader - Level 2"] +pub type LEV2_R = crate::BitReader; +#[doc = "Field `LEV3` reader - Level 3"] +pub type LEV3_R = crate::BitReader; +#[doc = "Field `LEV4` reader - Level 4"] +pub type LEV4_R = crate::BitReader; +#[doc = "Field `LEV5` reader - Level 5"] +pub type LEV5_R = crate::BitReader; +#[doc = "Field `LEV6` reader - Level 6"] +pub type LEV6_R = crate::BitReader; +#[doc = "Field `LEV7` reader - Level 7"] +pub type LEV7_R = crate::BitReader; +#[doc = "Field `LEV8` reader - Level 8"] +pub type LEV8_R = crate::BitReader; +#[doc = "Field `LEV9` reader - Level 9"] +pub type LEV9_R = crate::BitReader; +#[doc = "Field `LEV10` reader - Level 10"] +pub type LEV10_R = crate::BitReader; +#[doc = "Field `LEV11` reader - Level 11"] +pub type LEV11_R = crate::BitReader; +#[doc = "Field `LEV12` reader - Level 12"] +pub type LEV12_R = crate::BitReader; +#[doc = "Field `LEV13` reader - Level 13"] +pub type LEV13_R = crate::BitReader; +#[doc = "Field `LEV14` reader - Level 14"] +pub type LEV14_R = crate::BitReader; +#[doc = "Field `LEV15` reader - Level 15"] +pub type LEV15_R = crate::BitReader; +#[doc = "Field `LEV16` reader - Level 16"] +pub type LEV16_R = crate::BitReader; +#[doc = "Field `LEV17` reader - Level 17"] +pub type LEV17_R = crate::BitReader; +#[doc = "Field `LEV18` reader - Level 18"] +pub type LEV18_R = crate::BitReader; +#[doc = "Field `LEV19` reader - Level 19"] +pub type LEV19_R = crate::BitReader; +#[doc = "Field `LEV20` reader - Level 20"] +pub type LEV20_R = crate::BitReader; +#[doc = "Field `LEV21` reader - Level 21"] +pub type LEV21_R = crate::BitReader; +#[doc = "Field `LEV22` reader - Level 22"] +pub type LEV22_R = crate::BitReader; +#[doc = "Field `LEV23` reader - Level 23"] +pub type LEV23_R = crate::BitReader; +#[doc = "Field `LEV24` reader - Level 24"] +pub type LEV24_R = crate::BitReader; +#[doc = "Field `LEV25` reader - Level 25"] +pub type LEV25_R = crate::BitReader; +#[doc = "Field `LEV26` reader - Level 26"] +pub type LEV26_R = crate::BitReader; +#[doc = "Field `LEV27` reader - Level 27"] +pub type LEV27_R = crate::BitReader; +#[doc = "Field `LEV28` reader - Level 28"] +pub type LEV28_R = crate::BitReader; +#[doc = "Field `LEV29` reader - Level 29"] +pub type LEV29_R = crate::BitReader; +#[doc = "Field `LEV30` reader - Level 30"] +pub type LEV30_R = crate::BitReader; +#[doc = "Field `LEV31` reader - Level 31"] +pub type LEV31_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Level 0"] + #[inline(always)] + pub fn lev0(&self) -> LEV0_R { + LEV0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 1"] + #[inline(always)] + pub fn lev1(&self) -> LEV1_R { + LEV1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 2"] + #[inline(always)] + pub fn lev2(&self) -> LEV2_R { + LEV2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 3"] + #[inline(always)] + pub fn lev3(&self) -> LEV3_R { + LEV3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Level 4"] + #[inline(always)] + pub fn lev4(&self) -> LEV4_R { + LEV4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Level 5"] + #[inline(always)] + pub fn lev5(&self) -> LEV5_R { + LEV5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Level 6"] + #[inline(always)] + pub fn lev6(&self) -> LEV6_R { + LEV6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Level 7"] + #[inline(always)] + pub fn lev7(&self) -> LEV7_R { + LEV7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Level 8"] + #[inline(always)] + pub fn lev8(&self) -> LEV8_R { + LEV8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Level 9"] + #[inline(always)] + pub fn lev9(&self) -> LEV9_R { + LEV9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Level 10"] + #[inline(always)] + pub fn lev10(&self) -> LEV10_R { + LEV10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Level 11"] + #[inline(always)] + pub fn lev11(&self) -> LEV11_R { + LEV11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Level 12"] + #[inline(always)] + pub fn lev12(&self) -> LEV12_R { + LEV12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Level 13"] + #[inline(always)] + pub fn lev13(&self) -> LEV13_R { + LEV13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Level 14"] + #[inline(always)] + pub fn lev14(&self) -> LEV14_R { + LEV14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Level 15"] + #[inline(always)] + pub fn lev15(&self) -> LEV15_R { + LEV15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Level 16"] + #[inline(always)] + pub fn lev16(&self) -> LEV16_R { + LEV16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Level 17"] + #[inline(always)] + pub fn lev17(&self) -> LEV17_R { + LEV17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Level 18"] + #[inline(always)] + pub fn lev18(&self) -> LEV18_R { + LEV18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Level 19"] + #[inline(always)] + pub fn lev19(&self) -> LEV19_R { + LEV19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Level 20"] + #[inline(always)] + pub fn lev20(&self) -> LEV20_R { + LEV20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Level 21"] + #[inline(always)] + pub fn lev21(&self) -> LEV21_R { + LEV21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Level 22"] + #[inline(always)] + pub fn lev22(&self) -> LEV22_R { + LEV22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Level 23"] + #[inline(always)] + pub fn lev23(&self) -> LEV23_R { + LEV23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Level 24"] + #[inline(always)] + pub fn lev24(&self) -> LEV24_R { + LEV24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Level 25"] + #[inline(always)] + pub fn lev25(&self) -> LEV25_R { + LEV25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Level 26"] + #[inline(always)] + pub fn lev26(&self) -> LEV26_R { + LEV26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Level 27"] + #[inline(always)] + pub fn lev27(&self) -> LEV27_R { + LEV27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Level 28"] + #[inline(always)] + pub fn lev28(&self) -> LEV28_R { + LEV28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Level 29"] + #[inline(always)] + pub fn lev29(&self) -> LEV29_R { + LEV29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Level 30"] + #[inline(always)] + pub fn lev30(&self) -> LEV30_R { + LEV30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Level 31"] + #[inline(always)] + pub fn lev31(&self) -> LEV31_R { + LEV31_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "GPIO Pin Level 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev0](index.html) module"] +pub struct GPLEV0_SPEC; +impl crate::RegisterSpec for GPLEV0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplev0::R](R) reader structure"] +impl crate::Readable for GPLEV0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/gpio/gplev1.rs b/crates/bcm2835-lpa/src/gpio/gplev1.rs new file mode 100644 index 0000000..5323ce3 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gplev1.rs @@ -0,0 +1,180 @@ +#[doc = "Register `GPLEV1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LEV32` reader - Level 32"] +pub type LEV32_R = crate::BitReader; +#[doc = "Field `LEV33` reader - Level 33"] +pub type LEV33_R = crate::BitReader; +#[doc = "Field `LEV34` reader - Level 34"] +pub type LEV34_R = crate::BitReader; +#[doc = "Field `LEV35` reader - Level 35"] +pub type LEV35_R = crate::BitReader; +#[doc = "Field `LEV36` reader - Level 36"] +pub type LEV36_R = crate::BitReader; +#[doc = "Field `LEV37` reader - Level 37"] +pub type LEV37_R = crate::BitReader; +#[doc = "Field `LEV38` reader - Level 38"] +pub type LEV38_R = crate::BitReader; +#[doc = "Field `LEV39` reader - Level 39"] +pub type LEV39_R = crate::BitReader; +#[doc = "Field `LEV40` reader - Level 40"] +pub type LEV40_R = crate::BitReader; +#[doc = "Field `LEV41` reader - Level 41"] +pub type LEV41_R = crate::BitReader; +#[doc = "Field `LEV42` reader - Level 42"] +pub type LEV42_R = crate::BitReader; +#[doc = "Field `LEV43` reader - Level 43"] +pub type LEV43_R = crate::BitReader; +#[doc = "Field `LEV44` reader - Level 44"] +pub type LEV44_R = crate::BitReader; +#[doc = "Field `LEV45` reader - Level 45"] +pub type LEV45_R = crate::BitReader; +#[doc = "Field `LEV46` reader - Level 46"] +pub type LEV46_R = crate::BitReader; +#[doc = "Field `LEV47` reader - Level 47"] +pub type LEV47_R = crate::BitReader; +#[doc = "Field `LEV48` reader - Level 48"] +pub type LEV48_R = crate::BitReader; +#[doc = "Field `LEV49` reader - Level 49"] +pub type LEV49_R = crate::BitReader; +#[doc = "Field `LEV50` reader - Level 50"] +pub type LEV50_R = crate::BitReader; +#[doc = "Field `LEV51` reader - Level 51"] +pub type LEV51_R = crate::BitReader; +#[doc = "Field `LEV52` reader - Level 52"] +pub type LEV52_R = crate::BitReader; +#[doc = "Field `LEV53` reader - Level 53"] +pub type LEV53_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Level 32"] + #[inline(always)] + pub fn lev32(&self) -> LEV32_R { + LEV32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 33"] + #[inline(always)] + pub fn lev33(&self) -> LEV33_R { + LEV33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 34"] + #[inline(always)] + pub fn lev34(&self) -> LEV34_R { + LEV34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 35"] + #[inline(always)] + pub fn lev35(&self) -> LEV35_R { + LEV35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Level 36"] + #[inline(always)] + pub fn lev36(&self) -> LEV36_R { + LEV36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Level 37"] + #[inline(always)] + pub fn lev37(&self) -> LEV37_R { + LEV37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Level 38"] + #[inline(always)] + pub fn lev38(&self) -> LEV38_R { + LEV38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Level 39"] + #[inline(always)] + pub fn lev39(&self) -> LEV39_R { + LEV39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Level 40"] + #[inline(always)] + pub fn lev40(&self) -> LEV40_R { + LEV40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Level 41"] + #[inline(always)] + pub fn lev41(&self) -> LEV41_R { + LEV41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Level 42"] + #[inline(always)] + pub fn lev42(&self) -> LEV42_R { + LEV42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Level 43"] + #[inline(always)] + pub fn lev43(&self) -> LEV43_R { + LEV43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Level 44"] + #[inline(always)] + pub fn lev44(&self) -> LEV44_R { + LEV44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Level 45"] + #[inline(always)] + pub fn lev45(&self) -> LEV45_R { + LEV45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Level 46"] + #[inline(always)] + pub fn lev46(&self) -> LEV46_R { + LEV46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Level 47"] + #[inline(always)] + pub fn lev47(&self) -> LEV47_R { + LEV47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Level 48"] + #[inline(always)] + pub fn lev48(&self) -> LEV48_R { + LEV48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Level 49"] + #[inline(always)] + pub fn lev49(&self) -> LEV49_R { + LEV49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Level 50"] + #[inline(always)] + pub fn lev50(&self) -> LEV50_R { + LEV50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Level 51"] + #[inline(always)] + pub fn lev51(&self) -> LEV51_R { + LEV51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Level 52"] + #[inline(always)] + pub fn lev52(&self) -> LEV52_R { + LEV52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Level 53"] + #[inline(always)] + pub fn lev53(&self) -> LEV53_R { + LEV53_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[doc = "GPIO Pin Level 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev1](index.html) module"] +pub struct GPLEV1_SPEC; +impl crate::RegisterSpec for GPLEV1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplev1::R](R) reader structure"] +impl crate::Readable for GPLEV1_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpren0.rs b/crates/bcm2835-lpa/src/gpio/gpren0.rs new file mode 100644 index 0000000..af4f16c --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpren0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPREN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REN0` reader - Rising edge enabled 0"] +pub type REN0_R = crate::BitReader; +#[doc = "Field `REN0` writer - Rising edge enabled 0"] +pub type REN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN1` reader - Rising edge enabled 1"] +pub type REN1_R = crate::BitReader; +#[doc = "Field `REN1` writer - Rising edge enabled 1"] +pub type REN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN2` reader - Rising edge enabled 2"] +pub type REN2_R = crate::BitReader; +#[doc = "Field `REN2` writer - Rising edge enabled 2"] +pub type REN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN3` reader - Rising edge enabled 3"] +pub type REN3_R = crate::BitReader; +#[doc = "Field `REN3` writer - Rising edge enabled 3"] +pub type REN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN4` reader - Rising edge enabled 4"] +pub type REN4_R = crate::BitReader; +#[doc = "Field `REN4` writer - Rising edge enabled 4"] +pub type REN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN5` reader - Rising edge enabled 5"] +pub type REN5_R = crate::BitReader; +#[doc = "Field `REN5` writer - Rising edge enabled 5"] +pub type REN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN6` reader - Rising edge enabled 6"] +pub type REN6_R = crate::BitReader; +#[doc = "Field `REN6` writer - Rising edge enabled 6"] +pub type REN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN7` reader - Rising edge enabled 7"] +pub type REN7_R = crate::BitReader; +#[doc = "Field `REN7` writer - Rising edge enabled 7"] +pub type REN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN8` reader - Rising edge enabled 8"] +pub type REN8_R = crate::BitReader; +#[doc = "Field `REN8` writer - Rising edge enabled 8"] +pub type REN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN9` reader - Rising edge enabled 9"] +pub type REN9_R = crate::BitReader; +#[doc = "Field `REN9` writer - Rising edge enabled 9"] +pub type REN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN10` reader - Rising edge enabled 10"] +pub type REN10_R = crate::BitReader; +#[doc = "Field `REN10` writer - Rising edge enabled 10"] +pub type REN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN11` reader - Rising edge enabled 11"] +pub type REN11_R = crate::BitReader; +#[doc = "Field `REN11` writer - Rising edge enabled 11"] +pub type REN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN12` reader - Rising edge enabled 12"] +pub type REN12_R = crate::BitReader; +#[doc = "Field `REN12` writer - Rising edge enabled 12"] +pub type REN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN13` reader - Rising edge enabled 13"] +pub type REN13_R = crate::BitReader; +#[doc = "Field `REN13` writer - Rising edge enabled 13"] +pub type REN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN14` reader - Rising edge enabled 14"] +pub type REN14_R = crate::BitReader; +#[doc = "Field `REN14` writer - Rising edge enabled 14"] +pub type REN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN15` reader - Rising edge enabled 15"] +pub type REN15_R = crate::BitReader; +#[doc = "Field `REN15` writer - Rising edge enabled 15"] +pub type REN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN16` reader - Rising edge enabled 16"] +pub type REN16_R = crate::BitReader; +#[doc = "Field `REN16` writer - Rising edge enabled 16"] +pub type REN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN17` reader - Rising edge enabled 17"] +pub type REN17_R = crate::BitReader; +#[doc = "Field `REN17` writer - Rising edge enabled 17"] +pub type REN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN18` reader - Rising edge enabled 18"] +pub type REN18_R = crate::BitReader; +#[doc = "Field `REN18` writer - Rising edge enabled 18"] +pub type REN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN19` reader - Rising edge enabled 19"] +pub type REN19_R = crate::BitReader; +#[doc = "Field `REN19` writer - Rising edge enabled 19"] +pub type REN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN20` reader - Rising edge enabled 20"] +pub type REN20_R = crate::BitReader; +#[doc = "Field `REN20` writer - Rising edge enabled 20"] +pub type REN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN21` reader - Rising edge enabled 21"] +pub type REN21_R = crate::BitReader; +#[doc = "Field `REN21` writer - Rising edge enabled 21"] +pub type REN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN22` reader - Rising edge enabled 22"] +pub type REN22_R = crate::BitReader; +#[doc = "Field `REN22` writer - Rising edge enabled 22"] +pub type REN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN23` reader - Rising edge enabled 23"] +pub type REN23_R = crate::BitReader; +#[doc = "Field `REN23` writer - Rising edge enabled 23"] +pub type REN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN24` reader - Rising edge enabled 24"] +pub type REN24_R = crate::BitReader; +#[doc = "Field `REN24` writer - Rising edge enabled 24"] +pub type REN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN25` reader - Rising edge enabled 25"] +pub type REN25_R = crate::BitReader; +#[doc = "Field `REN25` writer - Rising edge enabled 25"] +pub type REN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN26` reader - Rising edge enabled 26"] +pub type REN26_R = crate::BitReader; +#[doc = "Field `REN26` writer - Rising edge enabled 26"] +pub type REN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN27` reader - Rising edge enabled 27"] +pub type REN27_R = crate::BitReader; +#[doc = "Field `REN27` writer - Rising edge enabled 27"] +pub type REN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN28` reader - Rising edge enabled 28"] +pub type REN28_R = crate::BitReader; +#[doc = "Field `REN28` writer - Rising edge enabled 28"] +pub type REN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN29` reader - Rising edge enabled 29"] +pub type REN29_R = crate::BitReader; +#[doc = "Field `REN29` writer - Rising edge enabled 29"] +pub type REN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN30` reader - Rising edge enabled 30"] +pub type REN30_R = crate::BitReader; +#[doc = "Field `REN30` writer - Rising edge enabled 30"] +pub type REN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN31` reader - Rising edge enabled 31"] +pub type REN31_R = crate::BitReader; +#[doc = "Field `REN31` writer - Rising edge enabled 31"] +pub type REN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Rising edge enabled 0"] + #[inline(always)] + pub fn ren0(&self) -> REN0_R { + REN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rising edge enabled 1"] + #[inline(always)] + pub fn ren1(&self) -> REN1_R { + REN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Rising edge enabled 2"] + #[inline(always)] + pub fn ren2(&self) -> REN2_R { + REN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising edge enabled 3"] + #[inline(always)] + pub fn ren3(&self) -> REN3_R { + REN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Rising edge enabled 4"] + #[inline(always)] + pub fn ren4(&self) -> REN4_R { + REN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Rising edge enabled 5"] + #[inline(always)] + pub fn ren5(&self) -> REN5_R { + REN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising edge enabled 6"] + #[inline(always)] + pub fn ren6(&self) -> REN6_R { + REN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Rising edge enabled 7"] + #[inline(always)] + pub fn ren7(&self) -> REN7_R { + REN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Rising edge enabled 8"] + #[inline(always)] + pub fn ren8(&self) -> REN8_R { + REN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising edge enabled 9"] + #[inline(always)] + pub fn ren9(&self) -> REN9_R { + REN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Rising edge enabled 10"] + #[inline(always)] + pub fn ren10(&self) -> REN10_R { + REN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Rising edge enabled 11"] + #[inline(always)] + pub fn ren11(&self) -> REN11_R { + REN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Rising edge enabled 12"] + #[inline(always)] + pub fn ren12(&self) -> REN12_R { + REN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Rising edge enabled 13"] + #[inline(always)] + pub fn ren13(&self) -> REN13_R { + REN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Rising edge enabled 14"] + #[inline(always)] + pub fn ren14(&self) -> REN14_R { + REN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Rising edge enabled 15"] + #[inline(always)] + pub fn ren15(&self) -> REN15_R { + REN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Rising edge enabled 16"] + #[inline(always)] + pub fn ren16(&self) -> REN16_R { + REN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Rising edge enabled 17"] + #[inline(always)] + pub fn ren17(&self) -> REN17_R { + REN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Rising edge enabled 18"] + #[inline(always)] + pub fn ren18(&self) -> REN18_R { + REN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Rising edge enabled 19"] + #[inline(always)] + pub fn ren19(&self) -> REN19_R { + REN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Rising edge enabled 20"] + #[inline(always)] + pub fn ren20(&self) -> REN20_R { + REN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Rising edge enabled 21"] + #[inline(always)] + pub fn ren21(&self) -> REN21_R { + REN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Rising edge enabled 22"] + #[inline(always)] + pub fn ren22(&self) -> REN22_R { + REN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Rising edge enabled 23"] + #[inline(always)] + pub fn ren23(&self) -> REN23_R { + REN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Rising edge enabled 24"] + #[inline(always)] + pub fn ren24(&self) -> REN24_R { + REN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Rising edge enabled 25"] + #[inline(always)] + pub fn ren25(&self) -> REN25_R { + REN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Rising edge enabled 26"] + #[inline(always)] + pub fn ren26(&self) -> REN26_R { + REN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Rising edge enabled 27"] + #[inline(always)] + pub fn ren27(&self) -> REN27_R { + REN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Rising edge enabled 28"] + #[inline(always)] + pub fn ren28(&self) -> REN28_R { + REN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Rising edge enabled 29"] + #[inline(always)] + pub fn ren29(&self) -> REN29_R { + REN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Rising edge enabled 30"] + #[inline(always)] + pub fn ren30(&self) -> REN30_R { + REN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Rising edge enabled 31"] + #[inline(always)] + pub fn ren31(&self) -> REN31_R { + REN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising edge enabled 0"] + #[inline(always)] + #[must_use] + pub fn ren0(&mut self) -> REN0_W<0> { + REN0_W::new(self) + } + #[doc = "Bit 1 - Rising edge enabled 1"] + #[inline(always)] + #[must_use] + pub fn ren1(&mut self) -> REN1_W<1> { + REN1_W::new(self) + } + #[doc = "Bit 2 - Rising edge enabled 2"] + #[inline(always)] + #[must_use] + pub fn ren2(&mut self) -> REN2_W<2> { + REN2_W::new(self) + } + #[doc = "Bit 3 - Rising edge enabled 3"] + #[inline(always)] + #[must_use] + pub fn ren3(&mut self) -> REN3_W<3> { + REN3_W::new(self) + } + #[doc = "Bit 4 - Rising edge enabled 4"] + #[inline(always)] + #[must_use] + pub fn ren4(&mut self) -> REN4_W<4> { + REN4_W::new(self) + } + #[doc = "Bit 5 - Rising edge enabled 5"] + #[inline(always)] + #[must_use] + pub fn ren5(&mut self) -> REN5_W<5> { + REN5_W::new(self) + } + #[doc = "Bit 6 - Rising edge enabled 6"] + #[inline(always)] + #[must_use] + pub fn ren6(&mut self) -> REN6_W<6> { + REN6_W::new(self) + } + #[doc = "Bit 7 - Rising edge enabled 7"] + #[inline(always)] + #[must_use] + pub fn ren7(&mut self) -> REN7_W<7> { + REN7_W::new(self) + } + #[doc = "Bit 8 - Rising edge enabled 8"] + #[inline(always)] + #[must_use] + pub fn ren8(&mut self) -> REN8_W<8> { + REN8_W::new(self) + } + #[doc = "Bit 9 - Rising edge enabled 9"] + #[inline(always)] + #[must_use] + pub fn ren9(&mut self) -> REN9_W<9> { + REN9_W::new(self) + } + #[doc = "Bit 10 - Rising edge enabled 10"] + #[inline(always)] + #[must_use] + pub fn ren10(&mut self) -> REN10_W<10> { + REN10_W::new(self) + } + #[doc = "Bit 11 - Rising edge enabled 11"] + #[inline(always)] + #[must_use] + pub fn ren11(&mut self) -> REN11_W<11> { + REN11_W::new(self) + } + #[doc = "Bit 12 - Rising edge enabled 12"] + #[inline(always)] + #[must_use] + pub fn ren12(&mut self) -> REN12_W<12> { + REN12_W::new(self) + } + #[doc = "Bit 13 - Rising edge enabled 13"] + #[inline(always)] + #[must_use] + pub fn ren13(&mut self) -> REN13_W<13> { + REN13_W::new(self) + } + #[doc = "Bit 14 - Rising edge enabled 14"] + #[inline(always)] + #[must_use] + pub fn ren14(&mut self) -> REN14_W<14> { + REN14_W::new(self) + } + #[doc = "Bit 15 - Rising edge enabled 15"] + #[inline(always)] + #[must_use] + pub fn ren15(&mut self) -> REN15_W<15> { + REN15_W::new(self) + } + #[doc = "Bit 16 - Rising edge enabled 16"] + #[inline(always)] + #[must_use] + pub fn ren16(&mut self) -> REN16_W<16> { + REN16_W::new(self) + } + #[doc = "Bit 17 - Rising edge enabled 17"] + #[inline(always)] + #[must_use] + pub fn ren17(&mut self) -> REN17_W<17> { + REN17_W::new(self) + } + #[doc = "Bit 18 - Rising edge enabled 18"] + #[inline(always)] + #[must_use] + pub fn ren18(&mut self) -> REN18_W<18> { + REN18_W::new(self) + } + #[doc = "Bit 19 - Rising edge enabled 19"] + #[inline(always)] + #[must_use] + pub fn ren19(&mut self) -> REN19_W<19> { + REN19_W::new(self) + } + #[doc = "Bit 20 - Rising edge enabled 20"] + #[inline(always)] + #[must_use] + pub fn ren20(&mut self) -> REN20_W<20> { + REN20_W::new(self) + } + #[doc = "Bit 21 - Rising edge enabled 21"] + #[inline(always)] + #[must_use] + pub fn ren21(&mut self) -> REN21_W<21> { + REN21_W::new(self) + } + #[doc = "Bit 22 - Rising edge enabled 22"] + #[inline(always)] + #[must_use] + pub fn ren22(&mut self) -> REN22_W<22> { + REN22_W::new(self) + } + #[doc = "Bit 23 - Rising edge enabled 23"] + #[inline(always)] + #[must_use] + pub fn ren23(&mut self) -> REN23_W<23> { + REN23_W::new(self) + } + #[doc = "Bit 24 - Rising edge enabled 24"] + #[inline(always)] + #[must_use] + pub fn ren24(&mut self) -> REN24_W<24> { + REN24_W::new(self) + } + #[doc = "Bit 25 - Rising edge enabled 25"] + #[inline(always)] + #[must_use] + pub fn ren25(&mut self) -> REN25_W<25> { + REN25_W::new(self) + } + #[doc = "Bit 26 - Rising edge enabled 26"] + #[inline(always)] + #[must_use] + pub fn ren26(&mut self) -> REN26_W<26> { + REN26_W::new(self) + } + #[doc = "Bit 27 - Rising edge enabled 27"] + #[inline(always)] + #[must_use] + pub fn ren27(&mut self) -> REN27_W<27> { + REN27_W::new(self) + } + #[doc = "Bit 28 - Rising edge enabled 28"] + #[inline(always)] + #[must_use] + pub fn ren28(&mut self) -> REN28_W<28> { + REN28_W::new(self) + } + #[doc = "Bit 29 - Rising edge enabled 29"] + #[inline(always)] + #[must_use] + pub fn ren29(&mut self) -> REN29_W<29> { + REN29_W::new(self) + } + #[doc = "Bit 30 - Rising edge enabled 30"] + #[inline(always)] + #[must_use] + pub fn ren30(&mut self) -> REN30_W<30> { + REN30_W::new(self) + } + #[doc = "Bit 31 - Rising edge enabled 31"] + #[inline(always)] + #[must_use] + pub fn ren31(&mut self) -> REN31_W<31> { + REN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren0](index.html) module"] +pub struct GPREN0_SPEC; +impl crate::RegisterSpec for GPREN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpren0::R](R) reader structure"] +impl crate::Readable for GPREN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpren0::W](W) writer structure"] +impl crate::Writable for GPREN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpren1.rs b/crates/bcm2835-lpa/src/gpio/gpren1.rs new file mode 100644 index 0000000..3e70995 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpren1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPREN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REN32` reader - Rising edge enabled 32"] +pub type REN32_R = crate::BitReader; +#[doc = "Field `REN32` writer - Rising edge enabled 32"] +pub type REN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN33` reader - Rising edge enabled 33"] +pub type REN33_R = crate::BitReader; +#[doc = "Field `REN33` writer - Rising edge enabled 33"] +pub type REN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN34` reader - Rising edge enabled 34"] +pub type REN34_R = crate::BitReader; +#[doc = "Field `REN34` writer - Rising edge enabled 34"] +pub type REN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN35` reader - Rising edge enabled 35"] +pub type REN35_R = crate::BitReader; +#[doc = "Field `REN35` writer - Rising edge enabled 35"] +pub type REN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN36` reader - Rising edge enabled 36"] +pub type REN36_R = crate::BitReader; +#[doc = "Field `REN36` writer - Rising edge enabled 36"] +pub type REN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN37` reader - Rising edge enabled 37"] +pub type REN37_R = crate::BitReader; +#[doc = "Field `REN37` writer - Rising edge enabled 37"] +pub type REN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN38` reader - Rising edge enabled 38"] +pub type REN38_R = crate::BitReader; +#[doc = "Field `REN38` writer - Rising edge enabled 38"] +pub type REN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN39` reader - Rising edge enabled 39"] +pub type REN39_R = crate::BitReader; +#[doc = "Field `REN39` writer - Rising edge enabled 39"] +pub type REN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN40` reader - Rising edge enabled 40"] +pub type REN40_R = crate::BitReader; +#[doc = "Field `REN40` writer - Rising edge enabled 40"] +pub type REN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN41` reader - Rising edge enabled 41"] +pub type REN41_R = crate::BitReader; +#[doc = "Field `REN41` writer - Rising edge enabled 41"] +pub type REN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN42` reader - Rising edge enabled 42"] +pub type REN42_R = crate::BitReader; +#[doc = "Field `REN42` writer - Rising edge enabled 42"] +pub type REN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN43` reader - Rising edge enabled 43"] +pub type REN43_R = crate::BitReader; +#[doc = "Field `REN43` writer - Rising edge enabled 43"] +pub type REN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN44` reader - Rising edge enabled 44"] +pub type REN44_R = crate::BitReader; +#[doc = "Field `REN44` writer - Rising edge enabled 44"] +pub type REN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN45` reader - Rising edge enabled 45"] +pub type REN45_R = crate::BitReader; +#[doc = "Field `REN45` writer - Rising edge enabled 45"] +pub type REN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN46` reader - Rising edge enabled 46"] +pub type REN46_R = crate::BitReader; +#[doc = "Field `REN46` writer - Rising edge enabled 46"] +pub type REN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN47` reader - Rising edge enabled 47"] +pub type REN47_R = crate::BitReader; +#[doc = "Field `REN47` writer - Rising edge enabled 47"] +pub type REN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN48` reader - Rising edge enabled 48"] +pub type REN48_R = crate::BitReader; +#[doc = "Field `REN48` writer - Rising edge enabled 48"] +pub type REN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN49` reader - Rising edge enabled 49"] +pub type REN49_R = crate::BitReader; +#[doc = "Field `REN49` writer - Rising edge enabled 49"] +pub type REN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN50` reader - Rising edge enabled 50"] +pub type REN50_R = crate::BitReader; +#[doc = "Field `REN50` writer - Rising edge enabled 50"] +pub type REN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN51` reader - Rising edge enabled 51"] +pub type REN51_R = crate::BitReader; +#[doc = "Field `REN51` writer - Rising edge enabled 51"] +pub type REN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN52` reader - Rising edge enabled 52"] +pub type REN52_R = crate::BitReader; +#[doc = "Field `REN52` writer - Rising edge enabled 52"] +pub type REN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN53` reader - Rising edge enabled 53"] +pub type REN53_R = crate::BitReader; +#[doc = "Field `REN53` writer - Rising edge enabled 53"] +pub type REN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Rising edge enabled 32"] + #[inline(always)] + pub fn ren32(&self) -> REN32_R { + REN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rising edge enabled 33"] + #[inline(always)] + pub fn ren33(&self) -> REN33_R { + REN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Rising edge enabled 34"] + #[inline(always)] + pub fn ren34(&self) -> REN34_R { + REN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising edge enabled 35"] + #[inline(always)] + pub fn ren35(&self) -> REN35_R { + REN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Rising edge enabled 36"] + #[inline(always)] + pub fn ren36(&self) -> REN36_R { + REN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Rising edge enabled 37"] + #[inline(always)] + pub fn ren37(&self) -> REN37_R { + REN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising edge enabled 38"] + #[inline(always)] + pub fn ren38(&self) -> REN38_R { + REN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Rising edge enabled 39"] + #[inline(always)] + pub fn ren39(&self) -> REN39_R { + REN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Rising edge enabled 40"] + #[inline(always)] + pub fn ren40(&self) -> REN40_R { + REN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising edge enabled 41"] + #[inline(always)] + pub fn ren41(&self) -> REN41_R { + REN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Rising edge enabled 42"] + #[inline(always)] + pub fn ren42(&self) -> REN42_R { + REN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Rising edge enabled 43"] + #[inline(always)] + pub fn ren43(&self) -> REN43_R { + REN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Rising edge enabled 44"] + #[inline(always)] + pub fn ren44(&self) -> REN44_R { + REN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Rising edge enabled 45"] + #[inline(always)] + pub fn ren45(&self) -> REN45_R { + REN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Rising edge enabled 46"] + #[inline(always)] + pub fn ren46(&self) -> REN46_R { + REN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Rising edge enabled 47"] + #[inline(always)] + pub fn ren47(&self) -> REN47_R { + REN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Rising edge enabled 48"] + #[inline(always)] + pub fn ren48(&self) -> REN48_R { + REN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Rising edge enabled 49"] + #[inline(always)] + pub fn ren49(&self) -> REN49_R { + REN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Rising edge enabled 50"] + #[inline(always)] + pub fn ren50(&self) -> REN50_R { + REN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Rising edge enabled 51"] + #[inline(always)] + pub fn ren51(&self) -> REN51_R { + REN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Rising edge enabled 52"] + #[inline(always)] + pub fn ren52(&self) -> REN52_R { + REN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Rising edge enabled 53"] + #[inline(always)] + pub fn ren53(&self) -> REN53_R { + REN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising edge enabled 32"] + #[inline(always)] + #[must_use] + pub fn ren32(&mut self) -> REN32_W<0> { + REN32_W::new(self) + } + #[doc = "Bit 1 - Rising edge enabled 33"] + #[inline(always)] + #[must_use] + pub fn ren33(&mut self) -> REN33_W<1> { + REN33_W::new(self) + } + #[doc = "Bit 2 - Rising edge enabled 34"] + #[inline(always)] + #[must_use] + pub fn ren34(&mut self) -> REN34_W<2> { + REN34_W::new(self) + } + #[doc = "Bit 3 - Rising edge enabled 35"] + #[inline(always)] + #[must_use] + pub fn ren35(&mut self) -> REN35_W<3> { + REN35_W::new(self) + } + #[doc = "Bit 4 - Rising edge enabled 36"] + #[inline(always)] + #[must_use] + pub fn ren36(&mut self) -> REN36_W<4> { + REN36_W::new(self) + } + #[doc = "Bit 5 - Rising edge enabled 37"] + #[inline(always)] + #[must_use] + pub fn ren37(&mut self) -> REN37_W<5> { + REN37_W::new(self) + } + #[doc = "Bit 6 - Rising edge enabled 38"] + #[inline(always)] + #[must_use] + pub fn ren38(&mut self) -> REN38_W<6> { + REN38_W::new(self) + } + #[doc = "Bit 7 - Rising edge enabled 39"] + #[inline(always)] + #[must_use] + pub fn ren39(&mut self) -> REN39_W<7> { + REN39_W::new(self) + } + #[doc = "Bit 8 - Rising edge enabled 40"] + #[inline(always)] + #[must_use] + pub fn ren40(&mut self) -> REN40_W<8> { + REN40_W::new(self) + } + #[doc = "Bit 9 - Rising edge enabled 41"] + #[inline(always)] + #[must_use] + pub fn ren41(&mut self) -> REN41_W<9> { + REN41_W::new(self) + } + #[doc = "Bit 10 - Rising edge enabled 42"] + #[inline(always)] + #[must_use] + pub fn ren42(&mut self) -> REN42_W<10> { + REN42_W::new(self) + } + #[doc = "Bit 11 - Rising edge enabled 43"] + #[inline(always)] + #[must_use] + pub fn ren43(&mut self) -> REN43_W<11> { + REN43_W::new(self) + } + #[doc = "Bit 12 - Rising edge enabled 44"] + #[inline(always)] + #[must_use] + pub fn ren44(&mut self) -> REN44_W<12> { + REN44_W::new(self) + } + #[doc = "Bit 13 - Rising edge enabled 45"] + #[inline(always)] + #[must_use] + pub fn ren45(&mut self) -> REN45_W<13> { + REN45_W::new(self) + } + #[doc = "Bit 14 - Rising edge enabled 46"] + #[inline(always)] + #[must_use] + pub fn ren46(&mut self) -> REN46_W<14> { + REN46_W::new(self) + } + #[doc = "Bit 15 - Rising edge enabled 47"] + #[inline(always)] + #[must_use] + pub fn ren47(&mut self) -> REN47_W<15> { + REN47_W::new(self) + } + #[doc = "Bit 16 - Rising edge enabled 48"] + #[inline(always)] + #[must_use] + pub fn ren48(&mut self) -> REN48_W<16> { + REN48_W::new(self) + } + #[doc = "Bit 17 - Rising edge enabled 49"] + #[inline(always)] + #[must_use] + pub fn ren49(&mut self) -> REN49_W<17> { + REN49_W::new(self) + } + #[doc = "Bit 18 - Rising edge enabled 50"] + #[inline(always)] + #[must_use] + pub fn ren50(&mut self) -> REN50_W<18> { + REN50_W::new(self) + } + #[doc = "Bit 19 - Rising edge enabled 51"] + #[inline(always)] + #[must_use] + pub fn ren51(&mut self) -> REN51_W<19> { + REN51_W::new(self) + } + #[doc = "Bit 20 - Rising edge enabled 52"] + #[inline(always)] + #[must_use] + pub fn ren52(&mut self) -> REN52_W<20> { + REN52_W::new(self) + } + #[doc = "Bit 21 - Rising edge enabled 53"] + #[inline(always)] + #[must_use] + pub fn ren53(&mut self) -> REN53_W<21> { + REN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren1](index.html) module"] +pub struct GPREN1_SPEC; +impl crate::RegisterSpec for GPREN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpren1::R](R) reader structure"] +impl crate::Readable for GPREN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpren1::W](W) writer structure"] +impl crate::Writable for GPREN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpset0.rs b/crates/bcm2835-lpa/src/gpio/gpset0.rs new file mode 100644 index 0000000..49e2659 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpset0.rs @@ -0,0 +1,296 @@ +#[doc = "Register `GPSET0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SET0` writer - Set 0"] +pub type SET0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET1` writer - Set 1"] +pub type SET1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET2` writer - Set 2"] +pub type SET2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET3` writer - Set 3"] +pub type SET3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET4` writer - Set 4"] +pub type SET4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET5` writer - Set 5"] +pub type SET5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET6` writer - Set 6"] +pub type SET6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET7` writer - Set 7"] +pub type SET7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET8` writer - Set 8"] +pub type SET8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET9` writer - Set 9"] +pub type SET9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET10` writer - Set 10"] +pub type SET10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET11` writer - Set 11"] +pub type SET11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET12` writer - Set 12"] +pub type SET12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET13` writer - Set 13"] +pub type SET13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET14` writer - Set 14"] +pub type SET14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET15` writer - Set 15"] +pub type SET15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET16` writer - Set 16"] +pub type SET16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET17` writer - Set 17"] +pub type SET17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET18` writer - Set 18"] +pub type SET18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET19` writer - Set 19"] +pub type SET19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET20` writer - Set 20"] +pub type SET20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET21` writer - Set 21"] +pub type SET21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET22` writer - Set 22"] +pub type SET22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET23` writer - Set 23"] +pub type SET23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET24` writer - Set 24"] +pub type SET24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET25` writer - Set 25"] +pub type SET25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET26` writer - Set 26"] +pub type SET26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET27` writer - Set 27"] +pub type SET27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET28` writer - Set 28"] +pub type SET28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET29` writer - Set 29"] +pub type SET29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET30` writer - Set 30"] +pub type SET30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET31` writer - Set 31"] +pub type SET31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Set 0"] + #[inline(always)] + #[must_use] + pub fn set0(&mut self) -> SET0_W<0> { + SET0_W::new(self) + } + #[doc = "Bit 1 - Set 1"] + #[inline(always)] + #[must_use] + pub fn set1(&mut self) -> SET1_W<1> { + SET1_W::new(self) + } + #[doc = "Bit 2 - Set 2"] + #[inline(always)] + #[must_use] + pub fn set2(&mut self) -> SET2_W<2> { + SET2_W::new(self) + } + #[doc = "Bit 3 - Set 3"] + #[inline(always)] + #[must_use] + pub fn set3(&mut self) -> SET3_W<3> { + SET3_W::new(self) + } + #[doc = "Bit 4 - Set 4"] + #[inline(always)] + #[must_use] + pub fn set4(&mut self) -> SET4_W<4> { + SET4_W::new(self) + } + #[doc = "Bit 5 - Set 5"] + #[inline(always)] + #[must_use] + pub fn set5(&mut self) -> SET5_W<5> { + SET5_W::new(self) + } + #[doc = "Bit 6 - Set 6"] + #[inline(always)] + #[must_use] + pub fn set6(&mut self) -> SET6_W<6> { + SET6_W::new(self) + } + #[doc = "Bit 7 - Set 7"] + #[inline(always)] + #[must_use] + pub fn set7(&mut self) -> SET7_W<7> { + SET7_W::new(self) + } + #[doc = "Bit 8 - Set 8"] + #[inline(always)] + #[must_use] + pub fn set8(&mut self) -> SET8_W<8> { + SET8_W::new(self) + } + #[doc = "Bit 9 - Set 9"] + #[inline(always)] + #[must_use] + pub fn set9(&mut self) -> SET9_W<9> { + SET9_W::new(self) + } + #[doc = "Bit 10 - Set 10"] + #[inline(always)] + #[must_use] + pub fn set10(&mut self) -> SET10_W<10> { + SET10_W::new(self) + } + #[doc = "Bit 11 - Set 11"] + #[inline(always)] + #[must_use] + pub fn set11(&mut self) -> SET11_W<11> { + SET11_W::new(self) + } + #[doc = "Bit 12 - Set 12"] + #[inline(always)] + #[must_use] + pub fn set12(&mut self) -> SET12_W<12> { + SET12_W::new(self) + } + #[doc = "Bit 13 - Set 13"] + #[inline(always)] + #[must_use] + pub fn set13(&mut self) -> SET13_W<13> { + SET13_W::new(self) + } + #[doc = "Bit 14 - Set 14"] + #[inline(always)] + #[must_use] + pub fn set14(&mut self) -> SET14_W<14> { + SET14_W::new(self) + } + #[doc = "Bit 15 - Set 15"] + #[inline(always)] + #[must_use] + pub fn set15(&mut self) -> SET15_W<15> { + SET15_W::new(self) + } + #[doc = "Bit 16 - Set 16"] + #[inline(always)] + #[must_use] + pub fn set16(&mut self) -> SET16_W<16> { + SET16_W::new(self) + } + #[doc = "Bit 17 - Set 17"] + #[inline(always)] + #[must_use] + pub fn set17(&mut self) -> SET17_W<17> { + SET17_W::new(self) + } + #[doc = "Bit 18 - Set 18"] + #[inline(always)] + #[must_use] + pub fn set18(&mut self) -> SET18_W<18> { + SET18_W::new(self) + } + #[doc = "Bit 19 - Set 19"] + #[inline(always)] + #[must_use] + pub fn set19(&mut self) -> SET19_W<19> { + SET19_W::new(self) + } + #[doc = "Bit 20 - Set 20"] + #[inline(always)] + #[must_use] + pub fn set20(&mut self) -> SET20_W<20> { + SET20_W::new(self) + } + #[doc = "Bit 21 - Set 21"] + #[inline(always)] + #[must_use] + pub fn set21(&mut self) -> SET21_W<21> { + SET21_W::new(self) + } + #[doc = "Bit 22 - Set 22"] + #[inline(always)] + #[must_use] + pub fn set22(&mut self) -> SET22_W<22> { + SET22_W::new(self) + } + #[doc = "Bit 23 - Set 23"] + #[inline(always)] + #[must_use] + pub fn set23(&mut self) -> SET23_W<23> { + SET23_W::new(self) + } + #[doc = "Bit 24 - Set 24"] + #[inline(always)] + #[must_use] + pub fn set24(&mut self) -> SET24_W<24> { + SET24_W::new(self) + } + #[doc = "Bit 25 - Set 25"] + #[inline(always)] + #[must_use] + pub fn set25(&mut self) -> SET25_W<25> { + SET25_W::new(self) + } + #[doc = "Bit 26 - Set 26"] + #[inline(always)] + #[must_use] + pub fn set26(&mut self) -> SET26_W<26> { + SET26_W::new(self) + } + #[doc = "Bit 27 - Set 27"] + #[inline(always)] + #[must_use] + pub fn set27(&mut self) -> SET27_W<27> { + SET27_W::new(self) + } + #[doc = "Bit 28 - Set 28"] + #[inline(always)] + #[must_use] + pub fn set28(&mut self) -> SET28_W<28> { + SET28_W::new(self) + } + #[doc = "Bit 29 - Set 29"] + #[inline(always)] + #[must_use] + pub fn set29(&mut self) -> SET29_W<29> { + SET29_W::new(self) + } + #[doc = "Bit 30 - Set 30"] + #[inline(always)] + #[must_use] + pub fn set30(&mut self) -> SET30_W<30> { + SET30_W::new(self) + } + #[doc = "Bit 31 - Set 31"] + #[inline(always)] + #[must_use] + pub fn set31(&mut self) -> SET31_W<31> { + SET31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Set 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset0](index.html) module"] +pub struct GPSET0_SPEC; +impl crate::RegisterSpec for GPSET0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpset0::W](W) writer structure"] +impl crate::Writable for GPSET0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2835-lpa/src/gpio/gpset1.rs b/crates/bcm2835-lpa/src/gpio/gpset1.rs new file mode 100644 index 0000000..84f73e5 --- /dev/null +++ b/crates/bcm2835-lpa/src/gpio/gpset1.rs @@ -0,0 +1,216 @@ +#[doc = "Register `GPSET1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SET32` writer - Set 32"] +pub type SET32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET33` writer - Set 33"] +pub type SET33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET34` writer - Set 34"] +pub type SET34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET35` writer - Set 35"] +pub type SET35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET36` writer - Set 36"] +pub type SET36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET37` writer - Set 37"] +pub type SET37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET38` writer - Set 38"] +pub type SET38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET39` writer - Set 39"] +pub type SET39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET40` writer - Set 40"] +pub type SET40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET41` writer - Set 41"] +pub type SET41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET42` writer - Set 42"] +pub type SET42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET43` writer - Set 43"] +pub type SET43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET44` writer - Set 44"] +pub type SET44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET45` writer - Set 45"] +pub type SET45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET46` writer - Set 46"] +pub type SET46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET47` writer - Set 47"] +pub type SET47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET48` writer - Set 48"] +pub type SET48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET49` writer - Set 49"] +pub type SET49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET50` writer - Set 50"] +pub type SET50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET51` writer - Set 51"] +pub type SET51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET52` writer - Set 52"] +pub type SET52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET53` writer - Set 53"] +pub type SET53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Set 32"] + #[inline(always)] + #[must_use] + pub fn set32(&mut self) -> SET32_W<0> { + SET32_W::new(self) + } + #[doc = "Bit 1 - Set 33"] + #[inline(always)] + #[must_use] + pub fn set33(&mut self) -> SET33_W<1> { + SET33_W::new(self) + } + #[doc = "Bit 2 - Set 34"] + #[inline(always)] + #[must_use] + pub fn set34(&mut self) -> SET34_W<2> { + SET34_W::new(self) + } + #[doc = "Bit 3 - Set 35"] + #[inline(always)] + #[must_use] + pub fn set35(&mut self) -> SET35_W<3> { + SET35_W::new(self) + } + #[doc = "Bit 4 - Set 36"] + #[inline(always)] + #[must_use] + pub fn set36(&mut self) -> SET36_W<4> { + SET36_W::new(self) + } + #[doc = "Bit 5 - Set 37"] + #[inline(always)] + #[must_use] + pub fn set37(&mut self) -> SET37_W<5> { + SET37_W::new(self) + } + #[doc = "Bit 6 - Set 38"] + #[inline(always)] + #[must_use] + pub fn set38(&mut self) -> SET38_W<6> { + SET38_W::new(self) + } + #[doc = "Bit 7 - Set 39"] + #[inline(always)] + #[must_use] + pub fn set39(&mut self) -> SET39_W<7> { + SET39_W::new(self) + } + #[doc = "Bit 8 - Set 40"] + #[inline(always)] + #[must_use] + pub fn set40(&mut self) -> SET40_W<8> { + SET40_W::new(self) + } + #[doc = "Bit 9 - Set 41"] + #[inline(always)] + #[must_use] + pub fn set41(&mut self) -> SET41_W<9> { + SET41_W::new(self) + } + #[doc = "Bit 10 - Set 42"] + #[inline(always)] + #[must_use] + pub fn set42(&mut self) -> SET42_W<10> { + SET42_W::new(self) + } + #[doc = "Bit 11 - Set 43"] + #[inline(always)] + #[must_use] + pub fn set43(&mut self) -> SET43_W<11> { + SET43_W::new(self) + } + #[doc = "Bit 12 - Set 44"] + #[inline(always)] + #[must_use] + pub fn set44(&mut self) -> SET44_W<12> { + SET44_W::new(self) + } + #[doc = "Bit 13 - Set 45"] + #[inline(always)] + #[must_use] + pub fn set45(&mut self) -> SET45_W<13> { + SET45_W::new(self) + } + #[doc = "Bit 14 - Set 46"] + #[inline(always)] + #[must_use] + pub fn set46(&mut self) -> SET46_W<14> { + SET46_W::new(self) + } + #[doc = "Bit 15 - Set 47"] + #[inline(always)] + #[must_use] + pub fn set47(&mut self) -> SET47_W<15> { + SET47_W::new(self) + } + #[doc = "Bit 16 - Set 48"] + #[inline(always)] + #[must_use] + pub fn set48(&mut self) -> SET48_W<16> { + SET48_W::new(self) + } + #[doc = "Bit 17 - Set 49"] + #[inline(always)] + #[must_use] + pub fn set49(&mut self) -> SET49_W<17> { + SET49_W::new(self) + } + #[doc = "Bit 18 - Set 50"] + #[inline(always)] + #[must_use] + pub fn set50(&mut self) -> SET50_W<18> { + SET50_W::new(self) + } + #[doc = "Bit 19 - Set 51"] + #[inline(always)] + #[must_use] + pub fn set51(&mut self) -> SET51_W<19> { + SET51_W::new(self) + } + #[doc = "Bit 20 - Set 52"] + #[inline(always)] + #[must_use] + pub fn set52(&mut self) -> SET52_W<20> { + SET52_W::new(self) + } + #[doc = "Bit 21 - Set 53"] + #[inline(always)] + #[must_use] + pub fn set53(&mut self) -> SET53_W<21> { + SET53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Set 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset1](index.html) module"] +pub struct GPSET1_SPEC; +impl crate::RegisterSpec for GPSET1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpset1::W](W) writer structure"] +impl crate::Writable for GPSET1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; +} diff --git a/crates/bcm2835-lpa/src/interrupt.rs b/crates/bcm2835-lpa/src/interrupt.rs new file mode 100644 index 0000000..da6cbf5 --- /dev/null +++ b/crates/bcm2835-lpa/src/interrupt.rs @@ -0,0 +1,59 @@ +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - Timer 0 matched"] + TIMER_0 = 0, + #[doc = "1 - Timer 1 matched"] + TIMER_1 = 1, + #[doc = "2 - Timer 2 matched"] + TIMER_2 = 2, + #[doc = "3 - Timer 3 matched"] + TIMER_3 = 3, + #[doc = "9 - USB interrupt"] + USB = 9, + #[doc = "29 - Interrupt from AUX"] + AUX = 29, + #[doc = "49 - Interrupt from bank 0"] + GPIO0 = 49, + #[doc = "50 - Interrupt from bank 1"] + GPIO1 = 50, + #[doc = "51 - Interrupt from bank 2"] + GPIO2 = 51, + #[doc = "52 - OR of all GPIO interrupts"] + GPIO = 52, + #[doc = "53 - OR of all I2C interrupts"] + I2C = 53, + #[doc = "54 - OR of all SPI interrupts except 1 and 2"] + SPI = 54, + #[doc = "57 - OR of all UART interrupts except 1"] + UART = 57, + #[doc = "62 - OR of EMMC and EMMC2"] + EMMC = 62, +} +#[doc = r" TryFromInterruptError"] +#[derive(Debug, Copy, Clone)] +pub struct TryFromInterruptError(()); +impl Interrupt { + #[doc = r" Attempt to convert a given value into an `Interrupt`"] + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 0 => Ok(Interrupt::TIMER_0), + 1 => Ok(Interrupt::TIMER_1), + 2 => Ok(Interrupt::TIMER_2), + 3 => Ok(Interrupt::TIMER_3), + 9 => Ok(Interrupt::USB), + 29 => Ok(Interrupt::AUX), + 49 => Ok(Interrupt::GPIO0), + 50 => Ok(Interrupt::GPIO1), + 51 => Ok(Interrupt::GPIO2), + 52 => Ok(Interrupt::GPIO), + 53 => Ok(Interrupt::I2C), + 54 => Ok(Interrupt::SPI), + 57 => Ok(Interrupt::UART), + 62 => Ok(Interrupt::EMMC), + _ => Err(TryFromInterruptError(())), + } + } +} diff --git a/crates/bcm2835-lpa/src/lib.rs b/crates/bcm2835-lpa/src/lib.rs new file mode 100644 index 0000000..076b9d0 --- /dev/null +++ b/crates/bcm2835-lpa/src/lib.rs @@ -0,0 +1,786 @@ +#![doc = "Peripheral access API for BCM2835_LPA microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[doc(hidden)] +pub mod interrupt; +pub use self::interrupt::Interrupt; +#[doc = "Mailboxes for talking to/from VideoCore"] +pub struct VCMAILBOX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for VCMAILBOX {} +impl VCMAILBOX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const vcmailbox::RegisterBlock = 0x2000_b880 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const vcmailbox::RegisterBlock { + Self::PTR + } +} +impl Deref for VCMAILBOX { + type Target = vcmailbox::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for VCMAILBOX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VCMAILBOX").finish() + } +} +#[doc = "Mailboxes for talking to/from VideoCore"] +pub mod vcmailbox; +#[doc = "Broadcom Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x2010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Broadcom Power Manager"] +pub mod pm; +#[doc = "Broadcom Clock Manager"] +pub struct CM_PCM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CM_PCM {} +impl CM_PCM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cm_pcm::RegisterBlock = 0x2010_1098 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cm_pcm::RegisterBlock { + Self::PTR + } +} +impl Deref for CM_PCM { + type Target = cm_pcm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CM_PCM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CM_PCM").finish() + } +} +#[doc = "Broadcom Clock Manager"] +pub mod cm_pcm; +#[doc = "Broadcom Clock Manager"] +pub struct CM_PWM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CM_PWM {} +impl CM_PWM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cm_pcm::RegisterBlock = 0x2010_10a0 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cm_pcm::RegisterBlock { + Self::PTR + } +} +impl Deref for CM_PWM { + type Target = cm_pcm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CM_PWM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CM_PWM").finish() + } +} +#[doc = "Broadcom Clock Manager"] +pub use self::cm_pcm as cm_pwm; +#[doc = "Pin level and mux control"] +pub struct GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO {} +impl GPIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio::RegisterBlock = 0x2020_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio::RegisterBlock { + Self::PTR + } +} +impl Deref for GPIO { + type Target = gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO").finish() + } +} +#[doc = "Pin level and mux control"] +pub mod gpio; +#[doc = "Broadcom System Timer"] +pub struct SYSTMR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTMR {} +impl SYSTMR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const systmr::RegisterBlock = 0x2000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const systmr::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTMR { + type Target = systmr::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTMR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTMR").finish() + } +} +#[doc = "Broadcom System Timer"] +pub mod systmr; +#[doc = "ARM Prime Cell PL011"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x2020_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub mod uart0; +#[doc = "Broadcom SPI Controller"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x2020_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub mod spi0; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC0 {} +impl BSC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0x2020_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC0 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC0").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub mod bsc0; +#[doc = "Broadcom PWM"] +pub struct PWM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM0 {} +impl PWM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0::RegisterBlock = 0x2020_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM0 { + type Target = pwm0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0").finish() + } +} +#[doc = "Broadcom PWM"] +pub mod pwm0; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC1 {} +impl BSC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0x2080_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC1 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC1").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc1; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC2 {} +impl BSC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0x2080_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC2 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC2").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc2; +#[doc = "Three auxiliary peripherals"] +pub struct AUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AUX {} +impl AUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const aux::RegisterBlock = 0x2021_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aux::RegisterBlock { + Self::PTR + } +} +impl Deref for AUX { + type Target = aux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AUX").finish() + } +} +#[doc = "Three auxiliary peripherals"] +pub mod aux; +#[doc = "Mini UART"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart1::RegisterBlock = 0x2021_5040 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + Self::PTR + } +} +impl Deref for UART1 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "Mini UART"] +pub mod uart1; +#[doc = "Aux SPI"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0x2021_5080 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI1 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "Aux SPI"] +pub mod spi1; +#[doc = "Aux SPI"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0x2021_50c0 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI2 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2").finish() + } +} +#[doc = "Aux SPI"] +pub use self::spi1 as spi2; +#[doc = "Broadcom Legacy Interrupt Controller"] +pub struct LIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LIC {} +impl LIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lic::RegisterBlock = 0x2000_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lic::RegisterBlock { + Self::PTR + } +} +impl Deref for LIC { + type Target = lic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LIC").finish() + } +} +#[doc = "Broadcom Legacy Interrupt Controller"] +pub mod lic; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_GLOBAL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_GLOBAL {} +impl USB_OTG_GLOBAL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_global::RegisterBlock = 0x2098_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_global::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_GLOBAL { + type Target = usb_otg_global::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_GLOBAL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_GLOBAL").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_global; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_HOST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_HOST {} +impl USB_OTG_HOST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_host::RegisterBlock = 0x2098_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_host::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_HOST { + type Target = usb_otg_host::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_HOST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_HOST").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_host; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_DEVICE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_DEVICE {} +impl USB_OTG_DEVICE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_device::RegisterBlock = 0x2098_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_device::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_DEVICE { + type Target = usb_otg_device::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_DEVICE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_DEVICE").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_device; +#[doc = "USB on the go high speed power control"] +pub struct USB_OTG_PWRCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_PWRCLK {} +impl USB_OTG_PWRCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_pwrclk::RegisterBlock = 0x2098_0e00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_pwrclk::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_PWRCLK { + type Target = usb_otg_pwrclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_PWRCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_PWRCLK").finish() + } +} +#[doc = "USB on the go high speed power control"] +pub mod usb_otg_pwrclk; +#[doc = "Arasan SD3.0 Host AHB eMMC 4.4"] +pub struct EMMC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EMMC {} +impl EMMC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const emmc::RegisterBlock = 0x2030_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const emmc::RegisterBlock { + Self::PTR + } +} +impl Deref for EMMC { + type Target = emmc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EMMC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EMMC").finish() + } +} +#[doc = "Arasan SD3.0 Host AHB eMMC 4.4"] +pub mod emmc; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "VCMAILBOX"] + pub VCMAILBOX: VCMAILBOX, + #[doc = "PM"] + pub PM: PM, + #[doc = "CM_PCM"] + pub CM_PCM: CM_PCM, + #[doc = "CM_PWM"] + pub CM_PWM: CM_PWM, + #[doc = "GPIO"] + pub GPIO: GPIO, + #[doc = "SYSTMR"] + pub SYSTMR: SYSTMR, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "BSC0"] + pub BSC0: BSC0, + #[doc = "PWM0"] + pub PWM0: PWM0, + #[doc = "BSC1"] + pub BSC1: BSC1, + #[doc = "BSC2"] + pub BSC2: BSC2, + #[doc = "AUX"] + pub AUX: AUX, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "LIC"] + pub LIC: LIC, + #[doc = "USB_OTG_GLOBAL"] + pub USB_OTG_GLOBAL: USB_OTG_GLOBAL, + #[doc = "USB_OTG_HOST"] + pub USB_OTG_HOST: USB_OTG_HOST, + #[doc = "USB_OTG_DEVICE"] + pub USB_OTG_DEVICE: USB_OTG_DEVICE, + #[doc = "USB_OTG_PWRCLK"] + pub USB_OTG_PWRCLK: USB_OTG_PWRCLK, + #[doc = "EMMC"] + pub EMMC: EMMC, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + VCMAILBOX: VCMAILBOX { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + CM_PCM: CM_PCM { + _marker: PhantomData, + }, + CM_PWM: CM_PWM { + _marker: PhantomData, + }, + GPIO: GPIO { + _marker: PhantomData, + }, + SYSTMR: SYSTMR { + _marker: PhantomData, + }, + UART0: UART0 { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + BSC0: BSC0 { + _marker: PhantomData, + }, + PWM0: PWM0 { + _marker: PhantomData, + }, + BSC1: BSC1 { + _marker: PhantomData, + }, + BSC2: BSC2 { + _marker: PhantomData, + }, + AUX: AUX { + _marker: PhantomData, + }, + UART1: UART1 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + LIC: LIC { + _marker: PhantomData, + }, + USB_OTG_GLOBAL: USB_OTG_GLOBAL { + _marker: PhantomData, + }, + USB_OTG_HOST: USB_OTG_HOST { + _marker: PhantomData, + }, + USB_OTG_DEVICE: USB_OTG_DEVICE { + _marker: PhantomData, + }, + USB_OTG_PWRCLK: USB_OTG_PWRCLK { + _marker: PhantomData, + }, + EMMC: EMMC { + _marker: PhantomData, + }, + } + } +} diff --git a/crates/bcm2835-lpa/src/lic.rs b/crates/bcm2835-lpa/src/lic.rs new file mode 100644 index 0000000..bc15cd4 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic.rs @@ -0,0 +1,65 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0200], + #[doc = "0x200 - Basic pending info"] + pub basic_pending: BASIC_PENDING, + #[doc = "0x204 - Pending state for interrupts 1 - 31"] + pub pending_1: PENDING_1, + #[doc = "0x208 - Pending state for interrupts 32 - 63"] + pub pending_2: PENDING_2, + #[doc = "0x20c - FIQ control"] + pub fiq_control: FIQ_CONTROL, + #[doc = "0x210 - Enable interrupts 1 - 31"] + pub enable_1: ENABLE_1, + #[doc = "0x214 - Enable interrupts 32 - 63"] + pub enable_2: ENABLE_2, + #[doc = "0x218 - Enable basic interrupts"] + pub enable_basic: ENABLE_BASIC, + #[doc = "0x21c - Disable interrupts 1 - 31"] + pub disable_1: DISABLE_1, + #[doc = "0x220 - Disable interrupts 32 - 63"] + pub disable_2: DISABLE_2, + #[doc = "0x224 - Disable basic interrupts"] + pub disable_basic: DISABLE_BASIC, +} +#[doc = "BASIC_PENDING (r) register accessor: an alias for `Reg`"] +pub type BASIC_PENDING = crate::Reg; +#[doc = "Basic pending info"] +pub mod basic_pending; +#[doc = "PENDING_1 (r) register accessor: an alias for `Reg`"] +pub type PENDING_1 = crate::Reg; +#[doc = "Pending state for interrupts 1 - 31"] +pub mod pending_1; +#[doc = "PENDING_2 (r) register accessor: an alias for `Reg`"] +pub type PENDING_2 = crate::Reg; +#[doc = "Pending state for interrupts 32 - 63"] +pub mod pending_2; +#[doc = "FIQ_CONTROL (rw) register accessor: an alias for `Reg`"] +pub type FIQ_CONTROL = crate::Reg; +#[doc = "FIQ control"] +pub mod fiq_control; +#[doc = "ENABLE_1 (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_1 = crate::Reg; +#[doc = "Enable interrupts 1 - 31"] +pub mod enable_1; +#[doc = "ENABLE_2 (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_2 = crate::Reg; +#[doc = "Enable interrupts 32 - 63"] +pub mod enable_2; +#[doc = "ENABLE_BASIC (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_BASIC = crate::Reg; +#[doc = "Enable basic interrupts"] +pub mod enable_basic; +#[doc = "DISABLE_1 (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_1 = crate::Reg; +#[doc = "Disable interrupts 1 - 31"] +pub mod disable_1; +#[doc = "DISABLE_2 (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_2 = crate::Reg; +#[doc = "Disable interrupts 32 - 63"] +pub mod disable_2; +#[doc = "DISABLE_BASIC (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_BASIC = crate::Reg; +#[doc = "Disable basic interrupts"] +pub mod disable_basic; diff --git a/crates/bcm2835-lpa/src/lic/basic_pending.rs b/crates/bcm2835-lpa/src/lic/basic_pending.rs new file mode 100644 index 0000000..c7dcea2 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/basic_pending.rs @@ -0,0 +1,177 @@ +#[doc = "Register `BASIC_PENDING` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `PENDING_1` reader - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] +pub type PENDING_1_R = crate::BitReader; +#[doc = "Field `PENDING_2` reader - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] +pub type PENDING_2_R = crate::BitReader; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] + #[inline(always)] + pub fn pending_1(&self) -> PENDING_1_R { + PENDING_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] + #[inline(always)] + pub fn pending_2(&self) -> PENDING_2_R { + PENDING_2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[doc = "Basic pending info\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [basic_pending](index.html) module"] +pub struct BASIC_PENDING_SPEC; +impl crate::RegisterSpec for BASIC_PENDING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [basic_pending::R](R) reader structure"] +impl crate::Readable for BASIC_PENDING_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASIC_PENDING to value 0"] +impl crate::Resettable for BASIC_PENDING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/disable_1.rs b/crates/bcm2835-lpa/src/lic/disable_1.rs new file mode 100644 index 0000000..5c8027d --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/disable_1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `DISABLE_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_1](index.html) module"] +pub struct DISABLE_1_SPEC; +impl crate::RegisterSpec for DISABLE_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_1::R](R) reader structure"] +impl crate::Readable for DISABLE_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_1::W](W) writer structure"] +impl crate::Writable for DISABLE_1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets DISABLE_1 to value 0"] +impl crate::Resettable for DISABLE_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/disable_2.rs b/crates/bcm2835-lpa/src/lic/disable_2.rs new file mode 100644 index 0000000..9334cf8 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/disable_2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `DISABLE_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_2](index.html) module"] +pub struct DISABLE_2_SPEC; +impl crate::RegisterSpec for DISABLE_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_2::R](R) reader structure"] +impl crate::Readable for DISABLE_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_2::W](W) writer structure"] +impl crate::Writable for DISABLE_2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets DISABLE_2 to value 0"] +impl crate::Resettable for DISABLE_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/disable_basic.rs b/crates/bcm2835-lpa/src/lic/disable_basic.rs new file mode 100644 index 0000000..df73f14 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/disable_basic.rs @@ -0,0 +1,187 @@ +#[doc = "Register `DISABLE_BASIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_BASIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_basic](index.html) module"] +pub struct DISABLE_BASIC_SPEC; +impl crate::RegisterSpec for DISABLE_BASIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_basic::R](R) reader structure"] +impl crate::Readable for DISABLE_BASIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_basic::W](W) writer structure"] +impl crate::Writable for DISABLE_BASIC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; +} +#[doc = "`reset()` method sets DISABLE_BASIC to value 0"] +impl crate::Resettable for DISABLE_BASIC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/enable_1.rs b/crates/bcm2835-lpa/src/lic/enable_1.rs new file mode 100644 index 0000000..e9aa7ce --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/enable_1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `ENABLE_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_1](index.html) module"] +pub struct ENABLE_1_SPEC; +impl crate::RegisterSpec for ENABLE_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_1::R](R) reader structure"] +impl crate::Readable for ENABLE_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_1::W](W) writer structure"] +impl crate::Writable for ENABLE_1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets ENABLE_1 to value 0"] +impl crate::Resettable for ENABLE_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/enable_2.rs b/crates/bcm2835-lpa/src/lic/enable_2.rs new file mode 100644 index 0000000..45e156d --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/enable_2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `ENABLE_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_2](index.html) module"] +pub struct ENABLE_2_SPEC; +impl crate::RegisterSpec for ENABLE_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_2::R](R) reader structure"] +impl crate::Readable for ENABLE_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_2::W](W) writer structure"] +impl crate::Writable for ENABLE_2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets ENABLE_2 to value 0"] +impl crate::Resettable for ENABLE_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/enable_basic.rs b/crates/bcm2835-lpa/src/lic/enable_basic.rs new file mode 100644 index 0000000..b401deb --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/enable_basic.rs @@ -0,0 +1,186 @@ +#[doc = "Register `ENABLE_BASIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_BASIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_basic](index.html) module"] +pub struct ENABLE_BASIC_SPEC; +impl crate::RegisterSpec for ENABLE_BASIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_basic::R](R) reader structure"] +impl crate::Readable for ENABLE_BASIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_basic::W](W) writer structure"] +impl crate::Writable for ENABLE_BASIC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; +} +#[doc = "`reset()` method sets ENABLE_BASIC to value 0"] +impl crate::Resettable for ENABLE_BASIC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/fiq_control.rs b/crates/bcm2835-lpa/src/lic/fiq_control.rs new file mode 100644 index 0000000..d1b5d51 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/fiq_control.rs @@ -0,0 +1,1054 @@ +#[doc = "Register `FIQ_CONTROL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIQ_CONTROL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SOURCE` reader - FIQ Source"] +pub type SOURCE_R = crate::FieldReader; +#[doc = "FIQ Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SOURCE_A { + #[doc = "0: Timer 0"] + TIMER_0 = 0, + #[doc = "1: Timer 1"] + TIMER_1 = 1, + #[doc = "2: Timer 2"] + TIMER_2 = 2, + #[doc = "3: Timer 3"] + TIMER_3 = 3, + #[doc = "4: H264 0"] + H264_0 = 4, + #[doc = "5: H264 1"] + H264_1 = 5, + #[doc = "6: H264 2"] + H264_2 = 6, + #[doc = "7: JPEG"] + JPEG = 7, + #[doc = "8: ISP"] + ISP = 8, + #[doc = "9: USB"] + USB = 9, + #[doc = "10: V3D"] + V3D = 10, + #[doc = "11: Transposer"] + TRANSPOSER = 11, + #[doc = "12: Multicore Sync 0"] + MULTICORE_SYNC_0 = 12, + #[doc = "13: Multicore Sync 1"] + MULTICORE_SYNC_1 = 13, + #[doc = "14: Multicore Sync 2"] + MULTICORE_SYNC_2 = 14, + #[doc = "15: Multicore Sync 3"] + MULTICORE_SYNC_3 = 15, + #[doc = "16: DMA 0"] + DMA_0 = 16, + #[doc = "17: DMA 1"] + DMA_1 = 17, + #[doc = "18: DMA 2"] + DMA_2 = 18, + #[doc = "19: DMA 3"] + DMA_3 = 19, + #[doc = "20: DMA 4"] + DMA_4 = 20, + #[doc = "21: DMA 5"] + DMA_5 = 21, + #[doc = "22: DMA 6"] + DMA_6 = 22, + #[doc = "23: OR of DMA 7 and 8"] + DMA_7_8 = 23, + #[doc = "24: OR of DMA 9 and 10"] + DMA_9_10 = 24, + #[doc = "25: DMA 11"] + DMA_11 = 25, + #[doc = "26: DMA 12"] + DMA_12 = 26, + #[doc = "27: DMA 13"] + DMA_13 = 27, + #[doc = "28: DMA 14"] + DMA_14 = 28, + #[doc = "29: OR of UART1, SPI1 and SPI2"] + AUX = 29, + #[doc = "30: ARM"] + ARM = 30, + #[doc = "31: DMA 15"] + DMA_15 = 31, + #[doc = "32: HDMI CEC"] + HDMI_CEC = 32, + #[doc = "33: HVS"] + HVS = 33, + #[doc = "34: RPIVID"] + RPIVID = 34, + #[doc = "35: SDC"] + SDC = 35, + #[doc = "36: DSI 0"] + DSI_0 = 36, + #[doc = "37: Pixel Valve 2"] + PIXEL_VALVE_2 = 37, + #[doc = "38: Camera 0"] + CAMERA_0 = 38, + #[doc = "39: Camera 1"] + CAMERA_1 = 39, + #[doc = "40: HDMI 0"] + HDMI_0 = 40, + #[doc = "41: HDMI 1"] + HDMI_1 = 41, + #[doc = "42: Pixel Valve 3"] + PIXEL_VALVE_3 = 42, + #[doc = "43: SPI/BSC Slave"] + SPI_BSC_SLAVE = 43, + #[doc = "44: DSI 1"] + DSI_1 = 44, + #[doc = "45: Pixel Valve 0"] + PIXEL_VALVE_0 = 45, + #[doc = "46: OR of Pixel Valve 1 and 2"] + PIXEL_VALVE_1_2 = 46, + #[doc = "47: CPR"] + CPR = 47, + #[doc = "48: SMI"] + SMI = 48, + #[doc = "49: GPIO 0"] + GPIO_0 = 49, + #[doc = "50: GPIO 1"] + GPIO_1 = 50, + #[doc = "51: GPIO 2"] + GPIO_2 = 51, + #[doc = "52: GPIO 3"] + GPIO_3 = 52, + #[doc = "53: OR of all I2C"] + I2C = 53, + #[doc = "54: OR of all SPI"] + SPI = 54, + #[doc = "55: PCM/I2S"] + PCM_I2S = 55, + #[doc = "56: SDHOST"] + SDHOST = 56, + #[doc = "57: OR of all PL011 UARTs"] + UART = 57, + #[doc = "58: OR of all ETH_PCIe L2"] + ETH_PCIE = 58, + #[doc = "59: VEC"] + VEC = 59, + #[doc = "60: CPG"] + CPG = 60, + #[doc = "61: RNG"] + RNG = 61, + #[doc = "62: OR of EMMC and EMMC2"] + EMMC = 62, + #[doc = "63: ETH_PCIe secure"] + ETH_PCIE_SECURE = 63, + #[doc = "64: ARMC Timer"] + TIMER = 64, + #[doc = "65: Mailbox"] + MAILBOX = 65, + #[doc = "66: Doorbell 0"] + DOORBELL0 = 66, + #[doc = "67: Doorbell 1"] + DOORBELL1 = 67, + #[doc = "68: VPU0 halted"] + VPU0_HALTED = 68, + #[doc = "69: VPU1 halted"] + VPU1_HALTED = 69, + #[doc = "70: ARM address error"] + ARM_ADDRESS_ERROR = 70, + #[doc = "71: ARM AXI error"] + ARM_AXI_ERROR = 71, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SOURCE_A) -> Self { + variant as _ + } +} +impl SOURCE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SOURCE_A::TIMER_0), + 1 => Some(SOURCE_A::TIMER_1), + 2 => Some(SOURCE_A::TIMER_2), + 3 => Some(SOURCE_A::TIMER_3), + 4 => Some(SOURCE_A::H264_0), + 5 => Some(SOURCE_A::H264_1), + 6 => Some(SOURCE_A::H264_2), + 7 => Some(SOURCE_A::JPEG), + 8 => Some(SOURCE_A::ISP), + 9 => Some(SOURCE_A::USB), + 10 => Some(SOURCE_A::V3D), + 11 => Some(SOURCE_A::TRANSPOSER), + 12 => Some(SOURCE_A::MULTICORE_SYNC_0), + 13 => Some(SOURCE_A::MULTICORE_SYNC_1), + 14 => Some(SOURCE_A::MULTICORE_SYNC_2), + 15 => Some(SOURCE_A::MULTICORE_SYNC_3), + 16 => Some(SOURCE_A::DMA_0), + 17 => Some(SOURCE_A::DMA_1), + 18 => Some(SOURCE_A::DMA_2), + 19 => Some(SOURCE_A::DMA_3), + 20 => Some(SOURCE_A::DMA_4), + 21 => Some(SOURCE_A::DMA_5), + 22 => Some(SOURCE_A::DMA_6), + 23 => Some(SOURCE_A::DMA_7_8), + 24 => Some(SOURCE_A::DMA_9_10), + 25 => Some(SOURCE_A::DMA_11), + 26 => Some(SOURCE_A::DMA_12), + 27 => Some(SOURCE_A::DMA_13), + 28 => Some(SOURCE_A::DMA_14), + 29 => Some(SOURCE_A::AUX), + 30 => Some(SOURCE_A::ARM), + 31 => Some(SOURCE_A::DMA_15), + 32 => Some(SOURCE_A::HDMI_CEC), + 33 => Some(SOURCE_A::HVS), + 34 => Some(SOURCE_A::RPIVID), + 35 => Some(SOURCE_A::SDC), + 36 => Some(SOURCE_A::DSI_0), + 37 => Some(SOURCE_A::PIXEL_VALVE_2), + 38 => Some(SOURCE_A::CAMERA_0), + 39 => Some(SOURCE_A::CAMERA_1), + 40 => Some(SOURCE_A::HDMI_0), + 41 => Some(SOURCE_A::HDMI_1), + 42 => Some(SOURCE_A::PIXEL_VALVE_3), + 43 => Some(SOURCE_A::SPI_BSC_SLAVE), + 44 => Some(SOURCE_A::DSI_1), + 45 => Some(SOURCE_A::PIXEL_VALVE_0), + 46 => Some(SOURCE_A::PIXEL_VALVE_1_2), + 47 => Some(SOURCE_A::CPR), + 48 => Some(SOURCE_A::SMI), + 49 => Some(SOURCE_A::GPIO_0), + 50 => Some(SOURCE_A::GPIO_1), + 51 => Some(SOURCE_A::GPIO_2), + 52 => Some(SOURCE_A::GPIO_3), + 53 => Some(SOURCE_A::I2C), + 54 => Some(SOURCE_A::SPI), + 55 => Some(SOURCE_A::PCM_I2S), + 56 => Some(SOURCE_A::SDHOST), + 57 => Some(SOURCE_A::UART), + 58 => Some(SOURCE_A::ETH_PCIE), + 59 => Some(SOURCE_A::VEC), + 60 => Some(SOURCE_A::CPG), + 61 => Some(SOURCE_A::RNG), + 62 => Some(SOURCE_A::EMMC), + 63 => Some(SOURCE_A::ETH_PCIE_SECURE), + 64 => Some(SOURCE_A::TIMER), + 65 => Some(SOURCE_A::MAILBOX), + 66 => Some(SOURCE_A::DOORBELL0), + 67 => Some(SOURCE_A::DOORBELL1), + 68 => Some(SOURCE_A::VPU0_HALTED), + 69 => Some(SOURCE_A::VPU1_HALTED), + 70 => Some(SOURCE_A::ARM_ADDRESS_ERROR), + 71 => Some(SOURCE_A::ARM_AXI_ERROR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TIMER_0`"] + #[inline(always)] + pub fn is_timer_0(&self) -> bool { + *self == SOURCE_A::TIMER_0 + } + #[doc = "Checks if the value of the field is `TIMER_1`"] + #[inline(always)] + pub fn is_timer_1(&self) -> bool { + *self == SOURCE_A::TIMER_1 + } + #[doc = "Checks if the value of the field is `TIMER_2`"] + #[inline(always)] + pub fn is_timer_2(&self) -> bool { + *self == SOURCE_A::TIMER_2 + } + #[doc = "Checks if the value of the field is `TIMER_3`"] + #[inline(always)] + pub fn is_timer_3(&self) -> bool { + *self == SOURCE_A::TIMER_3 + } + #[doc = "Checks if the value of the field is `H264_0`"] + #[inline(always)] + pub fn is_h264_0(&self) -> bool { + *self == SOURCE_A::H264_0 + } + #[doc = "Checks if the value of the field is `H264_1`"] + #[inline(always)] + pub fn is_h264_1(&self) -> bool { + *self == SOURCE_A::H264_1 + } + #[doc = "Checks if the value of the field is `H264_2`"] + #[inline(always)] + pub fn is_h264_2(&self) -> bool { + *self == SOURCE_A::H264_2 + } + #[doc = "Checks if the value of the field is `JPEG`"] + #[inline(always)] + pub fn is_jpeg(&self) -> bool { + *self == SOURCE_A::JPEG + } + #[doc = "Checks if the value of the field is `ISP`"] + #[inline(always)] + pub fn is_isp(&self) -> bool { + *self == SOURCE_A::ISP + } + #[doc = "Checks if the value of the field is `USB`"] + #[inline(always)] + pub fn is_usb(&self) -> bool { + *self == SOURCE_A::USB + } + #[doc = "Checks if the value of the field is `V3D`"] + #[inline(always)] + pub fn is_v3d(&self) -> bool { + *self == SOURCE_A::V3D + } + #[doc = "Checks if the value of the field is `TRANSPOSER`"] + #[inline(always)] + pub fn is_transposer(&self) -> bool { + *self == SOURCE_A::TRANSPOSER + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_0`"] + #[inline(always)] + pub fn is_multicore_sync_0(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_0 + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_1`"] + #[inline(always)] + pub fn is_multicore_sync_1(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_1 + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_2`"] + #[inline(always)] + pub fn is_multicore_sync_2(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_2 + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_3`"] + #[inline(always)] + pub fn is_multicore_sync_3(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_3 + } + #[doc = "Checks if the value of the field is `DMA_0`"] + #[inline(always)] + pub fn is_dma_0(&self) -> bool { + *self == SOURCE_A::DMA_0 + } + #[doc = "Checks if the value of the field is `DMA_1`"] + #[inline(always)] + pub fn is_dma_1(&self) -> bool { + *self == SOURCE_A::DMA_1 + } + #[doc = "Checks if the value of the field is `DMA_2`"] + #[inline(always)] + pub fn is_dma_2(&self) -> bool { + *self == SOURCE_A::DMA_2 + } + #[doc = "Checks if the value of the field is `DMA_3`"] + #[inline(always)] + pub fn is_dma_3(&self) -> bool { + *self == SOURCE_A::DMA_3 + } + #[doc = "Checks if the value of the field is `DMA_4`"] + #[inline(always)] + pub fn is_dma_4(&self) -> bool { + *self == SOURCE_A::DMA_4 + } + #[doc = "Checks if the value of the field is `DMA_5`"] + #[inline(always)] + pub fn is_dma_5(&self) -> bool { + *self == SOURCE_A::DMA_5 + } + #[doc = "Checks if the value of the field is `DMA_6`"] + #[inline(always)] + pub fn is_dma_6(&self) -> bool { + *self == SOURCE_A::DMA_6 + } + #[doc = "Checks if the value of the field is `DMA_7_8`"] + #[inline(always)] + pub fn is_dma_7_8(&self) -> bool { + *self == SOURCE_A::DMA_7_8 + } + #[doc = "Checks if the value of the field is `DMA_9_10`"] + #[inline(always)] + pub fn is_dma_9_10(&self) -> bool { + *self == SOURCE_A::DMA_9_10 + } + #[doc = "Checks if the value of the field is `DMA_11`"] + #[inline(always)] + pub fn is_dma_11(&self) -> bool { + *self == SOURCE_A::DMA_11 + } + #[doc = "Checks if the value of the field is `DMA_12`"] + #[inline(always)] + pub fn is_dma_12(&self) -> bool { + *self == SOURCE_A::DMA_12 + } + #[doc = "Checks if the value of the field is `DMA_13`"] + #[inline(always)] + pub fn is_dma_13(&self) -> bool { + *self == SOURCE_A::DMA_13 + } + #[doc = "Checks if the value of the field is `DMA_14`"] + #[inline(always)] + pub fn is_dma_14(&self) -> bool { + *self == SOURCE_A::DMA_14 + } + #[doc = "Checks if the value of the field is `AUX`"] + #[inline(always)] + pub fn is_aux(&self) -> bool { + *self == SOURCE_A::AUX + } + #[doc = "Checks if the value of the field is `ARM`"] + #[inline(always)] + pub fn is_arm(&self) -> bool { + *self == SOURCE_A::ARM + } + #[doc = "Checks if the value of the field is `DMA_15`"] + #[inline(always)] + pub fn is_dma_15(&self) -> bool { + *self == SOURCE_A::DMA_15 + } + #[doc = "Checks if the value of the field is `HDMI_CEC`"] + #[inline(always)] + pub fn is_hdmi_cec(&self) -> bool { + *self == SOURCE_A::HDMI_CEC + } + #[doc = "Checks if the value of the field is `HVS`"] + #[inline(always)] + pub fn is_hvs(&self) -> bool { + *self == SOURCE_A::HVS + } + #[doc = "Checks if the value of the field is `RPIVID`"] + #[inline(always)] + pub fn is_rpivid(&self) -> bool { + *self == SOURCE_A::RPIVID + } + #[doc = "Checks if the value of the field is `SDC`"] + #[inline(always)] + pub fn is_sdc(&self) -> bool { + *self == SOURCE_A::SDC + } + #[doc = "Checks if the value of the field is `DSI_0`"] + #[inline(always)] + pub fn is_dsi_0(&self) -> bool { + *self == SOURCE_A::DSI_0 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_2`"] + #[inline(always)] + pub fn is_pixel_valve_2(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_2 + } + #[doc = "Checks if the value of the field is `CAMERA_0`"] + #[inline(always)] + pub fn is_camera_0(&self) -> bool { + *self == SOURCE_A::CAMERA_0 + } + #[doc = "Checks if the value of the field is `CAMERA_1`"] + #[inline(always)] + pub fn is_camera_1(&self) -> bool { + *self == SOURCE_A::CAMERA_1 + } + #[doc = "Checks if the value of the field is `HDMI_0`"] + #[inline(always)] + pub fn is_hdmi_0(&self) -> bool { + *self == SOURCE_A::HDMI_0 + } + #[doc = "Checks if the value of the field is `HDMI_1`"] + #[inline(always)] + pub fn is_hdmi_1(&self) -> bool { + *self == SOURCE_A::HDMI_1 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_3`"] + #[inline(always)] + pub fn is_pixel_valve_3(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_3 + } + #[doc = "Checks if the value of the field is `SPI_BSC_SLAVE`"] + #[inline(always)] + pub fn is_spi_bsc_slave(&self) -> bool { + *self == SOURCE_A::SPI_BSC_SLAVE + } + #[doc = "Checks if the value of the field is `DSI_1`"] + #[inline(always)] + pub fn is_dsi_1(&self) -> bool { + *self == SOURCE_A::DSI_1 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_0`"] + #[inline(always)] + pub fn is_pixel_valve_0(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_0 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_1_2`"] + #[inline(always)] + pub fn is_pixel_valve_1_2(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_1_2 + } + #[doc = "Checks if the value of the field is `CPR`"] + #[inline(always)] + pub fn is_cpr(&self) -> bool { + *self == SOURCE_A::CPR + } + #[doc = "Checks if the value of the field is `SMI`"] + #[inline(always)] + pub fn is_smi(&self) -> bool { + *self == SOURCE_A::SMI + } + #[doc = "Checks if the value of the field is `GPIO_0`"] + #[inline(always)] + pub fn is_gpio_0(&self) -> bool { + *self == SOURCE_A::GPIO_0 + } + #[doc = "Checks if the value of the field is `GPIO_1`"] + #[inline(always)] + pub fn is_gpio_1(&self) -> bool { + *self == SOURCE_A::GPIO_1 + } + #[doc = "Checks if the value of the field is `GPIO_2`"] + #[inline(always)] + pub fn is_gpio_2(&self) -> bool { + *self == SOURCE_A::GPIO_2 + } + #[doc = "Checks if the value of the field is `GPIO_3`"] + #[inline(always)] + pub fn is_gpio_3(&self) -> bool { + *self == SOURCE_A::GPIO_3 + } + #[doc = "Checks if the value of the field is `I2C`"] + #[inline(always)] + pub fn is_i2c(&self) -> bool { + *self == SOURCE_A::I2C + } + #[doc = "Checks if the value of the field is `SPI`"] + #[inline(always)] + pub fn is_spi(&self) -> bool { + *self == SOURCE_A::SPI + } + #[doc = "Checks if the value of the field is `PCM_I2S`"] + #[inline(always)] + pub fn is_pcm_i2s(&self) -> bool { + *self == SOURCE_A::PCM_I2S + } + #[doc = "Checks if the value of the field is `SDHOST`"] + #[inline(always)] + pub fn is_sdhost(&self) -> bool { + *self == SOURCE_A::SDHOST + } + #[doc = "Checks if the value of the field is `UART`"] + #[inline(always)] + pub fn is_uart(&self) -> bool { + *self == SOURCE_A::UART + } + #[doc = "Checks if the value of the field is `ETH_PCIE`"] + #[inline(always)] + pub fn is_eth_pcie(&self) -> bool { + *self == SOURCE_A::ETH_PCIE + } + #[doc = "Checks if the value of the field is `VEC`"] + #[inline(always)] + pub fn is_vec(&self) -> bool { + *self == SOURCE_A::VEC + } + #[doc = "Checks if the value of the field is `CPG`"] + #[inline(always)] + pub fn is_cpg(&self) -> bool { + *self == SOURCE_A::CPG + } + #[doc = "Checks if the value of the field is `RNG`"] + #[inline(always)] + pub fn is_rng(&self) -> bool { + *self == SOURCE_A::RNG + } + #[doc = "Checks if the value of the field is `EMMC`"] + #[inline(always)] + pub fn is_emmc(&self) -> bool { + *self == SOURCE_A::EMMC + } + #[doc = "Checks if the value of the field is `ETH_PCIE_SECURE`"] + #[inline(always)] + pub fn is_eth_pcie_secure(&self) -> bool { + *self == SOURCE_A::ETH_PCIE_SECURE + } + #[doc = "Checks if the value of the field is `TIMER`"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == SOURCE_A::TIMER + } + #[doc = "Checks if the value of the field is `MAILBOX`"] + #[inline(always)] + pub fn is_mailbox(&self) -> bool { + *self == SOURCE_A::MAILBOX + } + #[doc = "Checks if the value of the field is `DOORBELL0`"] + #[inline(always)] + pub fn is_doorbell0(&self) -> bool { + *self == SOURCE_A::DOORBELL0 + } + #[doc = "Checks if the value of the field is `DOORBELL1`"] + #[inline(always)] + pub fn is_doorbell1(&self) -> bool { + *self == SOURCE_A::DOORBELL1 + } + #[doc = "Checks if the value of the field is `VPU0_HALTED`"] + #[inline(always)] + pub fn is_vpu0_halted(&self) -> bool { + *self == SOURCE_A::VPU0_HALTED + } + #[doc = "Checks if the value of the field is `VPU1_HALTED`"] + #[inline(always)] + pub fn is_vpu1_halted(&self) -> bool { + *self == SOURCE_A::VPU1_HALTED + } + #[doc = "Checks if the value of the field is `ARM_ADDRESS_ERROR`"] + #[inline(always)] + pub fn is_arm_address_error(&self) -> bool { + *self == SOURCE_A::ARM_ADDRESS_ERROR + } + #[doc = "Checks if the value of the field is `ARM_AXI_ERROR`"] + #[inline(always)] + pub fn is_arm_axi_error(&self) -> bool { + *self == SOURCE_A::ARM_AXI_ERROR + } +} +#[doc = "Field `SOURCE` writer - FIQ Source"] +pub type SOURCE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, FIQ_CONTROL_SPEC, u8, SOURCE_A, 7, O>; +impl<'a, const O: u8> SOURCE_W<'a, O> { + #[doc = "Timer 0"] + #[inline(always)] + pub fn timer_0(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_0) + } + #[doc = "Timer 1"] + #[inline(always)] + pub fn timer_1(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_1) + } + #[doc = "Timer 2"] + #[inline(always)] + pub fn timer_2(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_2) + } + #[doc = "Timer 3"] + #[inline(always)] + pub fn timer_3(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_3) + } + #[doc = "H264 0"] + #[inline(always)] + pub fn h264_0(self) -> &'a mut W { + self.variant(SOURCE_A::H264_0) + } + #[doc = "H264 1"] + #[inline(always)] + pub fn h264_1(self) -> &'a mut W { + self.variant(SOURCE_A::H264_1) + } + #[doc = "H264 2"] + #[inline(always)] + pub fn h264_2(self) -> &'a mut W { + self.variant(SOURCE_A::H264_2) + } + #[doc = "JPEG"] + #[inline(always)] + pub fn jpeg(self) -> &'a mut W { + self.variant(SOURCE_A::JPEG) + } + #[doc = "ISP"] + #[inline(always)] + pub fn isp(self) -> &'a mut W { + self.variant(SOURCE_A::ISP) + } + #[doc = "USB"] + #[inline(always)] + pub fn usb(self) -> &'a mut W { + self.variant(SOURCE_A::USB) + } + #[doc = "V3D"] + #[inline(always)] + pub fn v3d(self) -> &'a mut W { + self.variant(SOURCE_A::V3D) + } + #[doc = "Transposer"] + #[inline(always)] + pub fn transposer(self) -> &'a mut W { + self.variant(SOURCE_A::TRANSPOSER) + } + #[doc = "Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_0) + } + #[doc = "Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_1) + } + #[doc = "Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_2) + } + #[doc = "Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_3) + } + #[doc = "DMA 0"] + #[inline(always)] + pub fn dma_0(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_0) + } + #[doc = "DMA 1"] + #[inline(always)] + pub fn dma_1(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_1) + } + #[doc = "DMA 2"] + #[inline(always)] + pub fn dma_2(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_2) + } + #[doc = "DMA 3"] + #[inline(always)] + pub fn dma_3(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_3) + } + #[doc = "DMA 4"] + #[inline(always)] + pub fn dma_4(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_4) + } + #[doc = "DMA 5"] + #[inline(always)] + pub fn dma_5(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_5) + } + #[doc = "DMA 6"] + #[inline(always)] + pub fn dma_6(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_6) + } + #[doc = "OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_7_8) + } + #[doc = "OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_9_10) + } + #[doc = "DMA 11"] + #[inline(always)] + pub fn dma_11(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_11) + } + #[doc = "DMA 12"] + #[inline(always)] + pub fn dma_12(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_12) + } + #[doc = "DMA 13"] + #[inline(always)] + pub fn dma_13(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_13) + } + #[doc = "DMA 14"] + #[inline(always)] + pub fn dma_14(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_14) + } + #[doc = "OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(self) -> &'a mut W { + self.variant(SOURCE_A::AUX) + } + #[doc = "ARM"] + #[inline(always)] + pub fn arm(self) -> &'a mut W { + self.variant(SOURCE_A::ARM) + } + #[doc = "DMA 15"] + #[inline(always)] + pub fn dma_15(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_15) + } + #[doc = "HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(self) -> &'a mut W { + self.variant(SOURCE_A::HDMI_CEC) + } + #[doc = "HVS"] + #[inline(always)] + pub fn hvs(self) -> &'a mut W { + self.variant(SOURCE_A::HVS) + } + #[doc = "RPIVID"] + #[inline(always)] + pub fn rpivid(self) -> &'a mut W { + self.variant(SOURCE_A::RPIVID) + } + #[doc = "SDC"] + #[inline(always)] + pub fn sdc(self) -> &'a mut W { + self.variant(SOURCE_A::SDC) + } + #[doc = "DSI 0"] + #[inline(always)] + pub fn dsi_0(self) -> &'a mut W { + self.variant(SOURCE_A::DSI_0) + } + #[doc = "Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_2) + } + #[doc = "Camera 0"] + #[inline(always)] + pub fn camera_0(self) -> &'a mut W { + self.variant(SOURCE_A::CAMERA_0) + } + #[doc = "Camera 1"] + #[inline(always)] + pub fn camera_1(self) -> &'a mut W { + self.variant(SOURCE_A::CAMERA_1) + } + #[doc = "HDMI 0"] + #[inline(always)] + pub fn hdmi_0(self) -> &'a mut W { + self.variant(SOURCE_A::HDMI_0) + } + #[doc = "HDMI 1"] + #[inline(always)] + pub fn hdmi_1(self) -> &'a mut W { + self.variant(SOURCE_A::HDMI_1) + } + #[doc = "Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_3) + } + #[doc = "SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(self) -> &'a mut W { + self.variant(SOURCE_A::SPI_BSC_SLAVE) + } + #[doc = "DSI 1"] + #[inline(always)] + pub fn dsi_1(self) -> &'a mut W { + self.variant(SOURCE_A::DSI_1) + } + #[doc = "Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_0) + } + #[doc = "OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_1_2) + } + #[doc = "CPR"] + #[inline(always)] + pub fn cpr(self) -> &'a mut W { + self.variant(SOURCE_A::CPR) + } + #[doc = "SMI"] + #[inline(always)] + pub fn smi(self) -> &'a mut W { + self.variant(SOURCE_A::SMI) + } + #[doc = "GPIO 0"] + #[inline(always)] + pub fn gpio_0(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_0) + } + #[doc = "GPIO 1"] + #[inline(always)] + pub fn gpio_1(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_1) + } + #[doc = "GPIO 2"] + #[inline(always)] + pub fn gpio_2(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_2) + } + #[doc = "GPIO 3"] + #[inline(always)] + pub fn gpio_3(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_3) + } + #[doc = "OR of all I2C"] + #[inline(always)] + pub fn i2c(self) -> &'a mut W { + self.variant(SOURCE_A::I2C) + } + #[doc = "OR of all SPI"] + #[inline(always)] + pub fn spi(self) -> &'a mut W { + self.variant(SOURCE_A::SPI) + } + #[doc = "PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(self) -> &'a mut W { + self.variant(SOURCE_A::PCM_I2S) + } + #[doc = "SDHOST"] + #[inline(always)] + pub fn sdhost(self) -> &'a mut W { + self.variant(SOURCE_A::SDHOST) + } + #[doc = "OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(self) -> &'a mut W { + self.variant(SOURCE_A::UART) + } + #[doc = "OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(self) -> &'a mut W { + self.variant(SOURCE_A::ETH_PCIE) + } + #[doc = "VEC"] + #[inline(always)] + pub fn vec(self) -> &'a mut W { + self.variant(SOURCE_A::VEC) + } + #[doc = "CPG"] + #[inline(always)] + pub fn cpg(self) -> &'a mut W { + self.variant(SOURCE_A::CPG) + } + #[doc = "RNG"] + #[inline(always)] + pub fn rng(self) -> &'a mut W { + self.variant(SOURCE_A::RNG) + } + #[doc = "OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(self) -> &'a mut W { + self.variant(SOURCE_A::EMMC) + } + #[doc = "ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(self) -> &'a mut W { + self.variant(SOURCE_A::ETH_PCIE_SECURE) + } + #[doc = "ARMC Timer"] + #[inline(always)] + pub fn timer(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER) + } + #[doc = "Mailbox"] + #[inline(always)] + pub fn mailbox(self) -> &'a mut W { + self.variant(SOURCE_A::MAILBOX) + } + #[doc = "Doorbell 0"] + #[inline(always)] + pub fn doorbell0(self) -> &'a mut W { + self.variant(SOURCE_A::DOORBELL0) + } + #[doc = "Doorbell 1"] + #[inline(always)] + pub fn doorbell1(self) -> &'a mut W { + self.variant(SOURCE_A::DOORBELL1) + } + #[doc = "VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(self) -> &'a mut W { + self.variant(SOURCE_A::VPU0_HALTED) + } + #[doc = "VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(self) -> &'a mut W { + self.variant(SOURCE_A::VPU1_HALTED) + } + #[doc = "ARM address error"] + #[inline(always)] + pub fn arm_address_error(self) -> &'a mut W { + self.variant(SOURCE_A::ARM_ADDRESS_ERROR) + } + #[doc = "ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(self) -> &'a mut W { + self.variant(SOURCE_A::ARM_AXI_ERROR) + } +} +#[doc = "Field `ENABLE` reader - FIQ Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - FIQ Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIQ_CONTROL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - FIQ Source"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - FIQ Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - FIQ Source"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W<0> { + SOURCE_W::new(self) + } + #[doc = "Bit 7 - FIQ Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<7> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIQ control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fiq_control](index.html) module"] +pub struct FIQ_CONTROL_SPEC; +impl crate::RegisterSpec for FIQ_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fiq_control::R](R) reader structure"] +impl crate::Readable for FIQ_CONTROL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fiq_control::W](W) writer structure"] +impl crate::Writable for FIQ_CONTROL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIQ_CONTROL to value 0"] +impl crate::Resettable for FIQ_CONTROL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/pending_1.rs b/crates/bcm2835-lpa/src/lic/pending_1.rs new file mode 100644 index 0000000..e4ae642 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/pending_1.rs @@ -0,0 +1,254 @@ +#[doc = "Register `PENDING_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Pending state for interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_1](index.html) module"] +pub struct PENDING_1_SPEC; +impl crate::RegisterSpec for PENDING_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pending_1::R](R) reader structure"] +impl crate::Readable for PENDING_1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDING_1 to value 0"] +impl crate::Resettable for PENDING_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/lic/pending_2.rs b/crates/bcm2835-lpa/src/lic/pending_2.rs new file mode 100644 index 0000000..f9a32c7 --- /dev/null +++ b/crates/bcm2835-lpa/src/lic/pending_2.rs @@ -0,0 +1,254 @@ +#[doc = "Register `PENDING_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Pending state for interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_2](index.html) module"] +pub struct PENDING_2_SPEC; +impl crate::RegisterSpec for PENDING_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pending_2::R](R) reader structure"] +impl crate::Readable for PENDING_2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDING_2 to value 0"] +impl crate::Resettable for PENDING_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pm.rs b/crates/bcm2835-lpa/src/pm.rs new file mode 100644 index 0000000..00ca6ac --- /dev/null +++ b/crates/bcm2835-lpa/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x1c], + #[doc = "0x1c - Reset Control"] + pub rstc: RSTC, + _reserved1: [u8; 0x04], + #[doc = "0x24 - Watchdog control"] + pub wdog: WDOG, +} +#[doc = "RSTC (rw) register accessor: an alias for `Reg`"] +pub type RSTC = crate::Reg; +#[doc = "Reset Control"] +pub mod rstc; +#[doc = "WDOG (rw) register accessor: an alias for `Reg`"] +pub type WDOG = crate::Reg; +#[doc = "Watchdog control"] +pub mod wdog; diff --git a/crates/bcm2835-lpa/src/pm/rstc.rs b/crates/bcm2835-lpa/src/pm/rstc.rs new file mode 100644 index 0000000..1903b76 --- /dev/null +++ b/crates/bcm2835-lpa/src/pm/rstc.rs @@ -0,0 +1,143 @@ +#[doc = "Register `RSTC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RSTC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRCFG` reader - Watchdog reset config"] +pub type WRCFG_R = crate::FieldReader; +#[doc = "Watchdog reset config\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WRCFG_A { + #[doc = "2: `10`"] + FULL_RESET = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRCFG_A) -> Self { + variant as _ + } +} +impl WRCFG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(WRCFG_A::FULL_RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FULL_RESET`"] + #[inline(always)] + pub fn is_full_reset(&self) -> bool { + *self == WRCFG_A::FULL_RESET + } +} +#[doc = "Field `WRCFG` writer - Watchdog reset config"] +pub type WRCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSTC_SPEC, u8, WRCFG_A, 2, O>; +impl<'a, const O: u8> WRCFG_W<'a, O> { + #[doc = "`10`"] + #[inline(always)] + pub fn full_reset(self) -> &'a mut W { + self.variant(WRCFG_A::FULL_RESET) + } +} +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSTC_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 4:5 - Watchdog reset config"] + #[inline(always)] + pub fn wrcfg(&self) -> WRCFG_R { + WRCFG_R::new(((self.bits >> 4) & 3) as u8) + } +} +impl W { + #[doc = "Bits 4:5 - Watchdog reset config"] + #[inline(always)] + #[must_use] + pub fn wrcfg(&mut self) -> WRCFG_W<4> { + WRCFG_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rstc](index.html) module"] +pub struct RSTC_SPEC; +impl crate::RegisterSpec for RSTC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rstc::R](R) reader structure"] +impl crate::Readable for RSTC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rstc::W](W) writer structure"] +impl crate::Writable for RSTC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RSTC to value 0x0102"] +impl crate::Resettable for RSTC_SPEC { + const RESET_VALUE: Self::Ux = 0x0102; +} diff --git a/crates/bcm2835-lpa/src/pm/wdog.rs b/crates/bcm2835-lpa/src/pm/wdog.rs new file mode 100644 index 0000000..d599781 --- /dev/null +++ b/crates/bcm2835-lpa/src/pm/wdog.rs @@ -0,0 +1,108 @@ +#[doc = "Register `WDOG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIME` reader - Time until watchdog alarm"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Time until watchdog alarm"] +pub type TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WDOG_SPEC, u32, u32, 20, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WDOG_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:19 - Time until watchdog alarm"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new(self.bits & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:19 - Time until watchdog alarm"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W<0> { + TIME_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Watchdog control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdog](index.html) module"] +pub struct WDOG_SPEC; +impl crate::RegisterSpec for WDOG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdog::R](R) reader structure"] +impl crate::Readable for WDOG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdog::W](W) writer structure"] +impl crate::Writable for WDOG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDOG to value 0"] +impl crate::Resettable for WDOG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pwm0.rs b/crates/bcm2835-lpa/src/pwm0.rs new file mode 100644 index 0000000..4270433 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctl: CTL, + #[doc = "0x04 - Status"] + pub sta: STA, + #[doc = "0x08 - DMA control"] + pub dmac: DMAC, + _reserved3: [u8; 0x04], + #[doc = "0x10 - Range for channel 1"] + pub rng1: RNG1, + #[doc = "0x14 - Channel 1 data"] + pub dat1: DAT1, + #[doc = "0x18 - FIFO input"] + pub fif1: FIF1, + _reserved6: [u8; 0x04], + #[doc = "0x20 - Range for channel 2"] + pub rng2: RNG2, + #[doc = "0x24 - Channel 2 data"] + pub dat2: DAT2, +} +#[doc = "CTL (rw) register accessor: an alias for `Reg`"] +pub type CTL = crate::Reg; +#[doc = "Control"] +pub mod ctl; +#[doc = "STA (rw) register accessor: an alias for `Reg`"] +pub type STA = crate::Reg; +#[doc = "Status"] +pub mod sta; +#[doc = "DMAC (rw) register accessor: an alias for `Reg`"] +pub type DMAC = crate::Reg; +#[doc = "DMA control"] +pub mod dmac; +#[doc = "RNG1 (rw) register accessor: an alias for `Reg`"] +pub type RNG1 = crate::Reg; +#[doc = "Range for channel 1"] +pub mod rng1; +#[doc = "DAT1 (rw) register accessor: an alias for `Reg`"] +pub type DAT1 = crate::Reg; +#[doc = "Channel 1 data"] +pub mod dat1; +#[doc = "FIF1 (w) register accessor: an alias for `Reg`"] +pub type FIF1 = crate::Reg; +#[doc = "FIFO input"] +pub mod fif1; +#[doc = "RNG2 (rw) register accessor: an alias for `Reg`"] +pub type RNG2 = crate::Reg; +#[doc = "Range for channel 2"] +pub mod rng2; +#[doc = "DAT2 (rw) register accessor: an alias for `Reg`"] +pub type DAT2 = crate::Reg; +#[doc = "Channel 2 data"] +pub mod dat2; diff --git a/crates/bcm2835-lpa/src/pwm0/ctl.rs b/crates/bcm2835-lpa/src/pwm0/ctl.rs new file mode 100644 index 0000000..b41b326 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/ctl.rs @@ -0,0 +1,382 @@ +#[doc = "Register `CTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWEN1` reader - Enable channel 1"] +pub type PWEN1_R = crate::BitReader; +#[doc = "Field `PWEN1` writer - Enable channel 1"] +pub type PWEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MODE1` reader - Channel 1 mode"] +pub type MODE1_R = crate::BitReader; +#[doc = "Channel 1 mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE1_A { + #[doc = "0: `0`"] + PWM = 0, + #[doc = "1: `1`"] + SERIAL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE1_A) -> Self { + variant as u8 != 0 + } +} +impl MODE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE1_A { + match self.bits { + false => MODE1_A::PWM, + true => MODE1_A::SERIAL, + } + } + #[doc = "Checks if the value of the field is `PWM`"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == MODE1_A::PWM + } + #[doc = "Checks if the value of the field is `SERIAL`"] + #[inline(always)] + pub fn is_serial(&self) -> bool { + *self == MODE1_A::SERIAL + } +} +#[doc = "Field `MODE1` writer - Channel 1 mode"] +pub type MODE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE1_A, O>; +impl<'a, const O: u8> MODE1_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn pwm(self) -> &'a mut W { + self.variant(MODE1_A::PWM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn serial(self) -> &'a mut W { + self.variant(MODE1_A::SERIAL) + } +} +#[doc = "Field `RPTL1` reader - Repeat last value from FIFO for channel 1"] +pub type RPTL1_R = crate::BitReader; +#[doc = "Field `RPTL1` writer - Repeat last value from FIFO for channel 1"] +pub type RPTL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `SBIT1` reader - State when not transmitting on channel 1"] +pub type SBIT1_R = crate::BitReader; +#[doc = "Field `SBIT1` writer - State when not transmitting on channel 1"] +pub type SBIT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `POLA1` reader - Channel 1 polarity inverted"] +pub type POLA1_R = crate::BitReader; +#[doc = "Field `POLA1` writer - Channel 1 polarity inverted"] +pub type POLA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `USEF1` reader - Use FIFO for channel 1"] +pub type USEF1_R = crate::BitReader; +#[doc = "Field `USEF1` writer - Use FIFO for channel 1"] +pub type USEF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `CLRF1` reader - Clear FIFO"] +pub type CLRF1_R = crate::BitReader; +#[doc = "Field `CLRF1` writer - Clear FIFO"] +pub type CLRF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MSEN1` reader - M/S mode for channel 1"] +pub type MSEN1_R = crate::BitReader; +#[doc = "Field `MSEN1` writer - M/S mode for channel 1"] +pub type MSEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `PWEN2` reader - Enable channel 2"] +pub type PWEN2_R = crate::BitReader; +#[doc = "Field `PWEN2` writer - Enable channel 2"] +pub type PWEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MODE2` reader - Channel 2 mode"] +pub type MODE2_R = crate::BitReader; +#[doc = "Channel 2 mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE2_A { + #[doc = "0: `0`"] + PWM = 0, + #[doc = "1: `1`"] + SERIAL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE2_A) -> Self { + variant as u8 != 0 + } +} +impl MODE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE2_A { + match self.bits { + false => MODE2_A::PWM, + true => MODE2_A::SERIAL, + } + } + #[doc = "Checks if the value of the field is `PWM`"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == MODE2_A::PWM + } + #[doc = "Checks if the value of the field is `SERIAL`"] + #[inline(always)] + pub fn is_serial(&self) -> bool { + *self == MODE2_A::SERIAL + } +} +#[doc = "Field `MODE2` writer - Channel 2 mode"] +pub type MODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE2_A, O>; +impl<'a, const O: u8> MODE2_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn pwm(self) -> &'a mut W { + self.variant(MODE2_A::PWM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn serial(self) -> &'a mut W { + self.variant(MODE2_A::SERIAL) + } +} +#[doc = "Field `RPTL2` reader - Repeat last value from FIFO for channel 2"] +pub type RPTL2_R = crate::BitReader; +#[doc = "Field `RPTL2` writer - Repeat last value from FIFO for channel 2"] +pub type RPTL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `SBIT2` reader - State when not transmitting on channel 2"] +pub type SBIT2_R = crate::BitReader; +#[doc = "Field `SBIT2` writer - State when not transmitting on channel 2"] +pub type SBIT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `POLA2` reader - Channel 2 polarity inverted"] +pub type POLA2_R = crate::BitReader; +#[doc = "Field `POLA2` writer - Channel 2 polarity inverted"] +pub type POLA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `USEF2` reader - Use FIFO for channel 2"] +pub type USEF2_R = crate::BitReader; +#[doc = "Field `USEF2` writer - Use FIFO for channel 2"] +pub type USEF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MSEN2` reader - M/S mode for channel 2"] +pub type MSEN2_R = crate::BitReader; +#[doc = "Field `MSEN2` writer - M/S mode for channel 2"] +pub type MSEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn pwen1(&self) -> PWEN1_R { + PWEN1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 mode"] + #[inline(always)] + pub fn mode1(&self) -> MODE1_R { + MODE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] + #[inline(always)] + pub fn rptl1(&self) -> RPTL1_R { + RPTL1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - State when not transmitting on channel 1"] + #[inline(always)] + pub fn sbit1(&self) -> SBIT1_R { + SBIT1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 1 polarity inverted"] + #[inline(always)] + pub fn pola1(&self) -> POLA1_R { + POLA1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Use FIFO for channel 1"] + #[inline(always)] + pub fn usef1(&self) -> USEF1_R { + USEF1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Clear FIFO"] + #[inline(always)] + pub fn clrf1(&self) -> CLRF1_R { + CLRF1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - M/S mode for channel 1"] + #[inline(always)] + pub fn msen1(&self) -> MSEN1_R { + MSEN1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable channel 2"] + #[inline(always)] + pub fn pwen2(&self) -> PWEN2_R { + PWEN2_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 2 mode"] + #[inline(always)] + pub fn mode2(&self) -> MODE2_R { + MODE2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] + #[inline(always)] + pub fn rptl2(&self) -> RPTL2_R { + RPTL2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - State when not transmitting on channel 2"] + #[inline(always)] + pub fn sbit2(&self) -> SBIT2_R { + SBIT2_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 2 polarity inverted"] + #[inline(always)] + pub fn pola2(&self) -> POLA2_R { + POLA2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Use FIFO for channel 2"] + #[inline(always)] + pub fn usef2(&self) -> USEF2_R { + USEF2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - M/S mode for channel 2"] + #[inline(always)] + pub fn msen2(&self) -> MSEN2_R { + MSEN2_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + #[must_use] + pub fn pwen1(&mut self) -> PWEN1_W<0> { + PWEN1_W::new(self) + } + #[doc = "Bit 1 - Channel 1 mode"] + #[inline(always)] + #[must_use] + pub fn mode1(&mut self) -> MODE1_W<1> { + MODE1_W::new(self) + } + #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] + #[inline(always)] + #[must_use] + pub fn rptl1(&mut self) -> RPTL1_W<2> { + RPTL1_W::new(self) + } + #[doc = "Bit 3 - State when not transmitting on channel 1"] + #[inline(always)] + #[must_use] + pub fn sbit1(&mut self) -> SBIT1_W<3> { + SBIT1_W::new(self) + } + #[doc = "Bit 4 - Channel 1 polarity inverted"] + #[inline(always)] + #[must_use] + pub fn pola1(&mut self) -> POLA1_W<4> { + POLA1_W::new(self) + } + #[doc = "Bit 5 - Use FIFO for channel 1"] + #[inline(always)] + #[must_use] + pub fn usef1(&mut self) -> USEF1_W<5> { + USEF1_W::new(self) + } + #[doc = "Bit 6 - Clear FIFO"] + #[inline(always)] + #[must_use] + pub fn clrf1(&mut self) -> CLRF1_W<6> { + CLRF1_W::new(self) + } + #[doc = "Bit 7 - M/S mode for channel 1"] + #[inline(always)] + #[must_use] + pub fn msen1(&mut self) -> MSEN1_W<7> { + MSEN1_W::new(self) + } + #[doc = "Bit 8 - Enable channel 2"] + #[inline(always)] + #[must_use] + pub fn pwen2(&mut self) -> PWEN2_W<8> { + PWEN2_W::new(self) + } + #[doc = "Bit 9 - Channel 2 mode"] + #[inline(always)] + #[must_use] + pub fn mode2(&mut self) -> MODE2_W<9> { + MODE2_W::new(self) + } + #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] + #[inline(always)] + #[must_use] + pub fn rptl2(&mut self) -> RPTL2_W<10> { + RPTL2_W::new(self) + } + #[doc = "Bit 11 - State when not transmitting on channel 2"] + #[inline(always)] + #[must_use] + pub fn sbit2(&mut self) -> SBIT2_W<11> { + SBIT2_W::new(self) + } + #[doc = "Bit 12 - Channel 2 polarity inverted"] + #[inline(always)] + #[must_use] + pub fn pola2(&mut self) -> POLA2_W<12> { + POLA2_W::new(self) + } + #[doc = "Bit 13 - Use FIFO for channel 2"] + #[inline(always)] + #[must_use] + pub fn usef2(&mut self) -> USEF2_W<13> { + USEF2_W::new(self) + } + #[doc = "Bit 15 - M/S mode for channel 2"] + #[inline(always)] + #[must_use] + pub fn msen2(&mut self) -> MSEN2_W<15> { + MSEN2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"] +pub struct CTL_SPEC; +impl crate::RegisterSpec for CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctl::R](R) reader structure"] +impl crate::Readable for CTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"] +impl crate::Writable for CTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTL to value 0"] +impl crate::Resettable for CTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pwm0/dat1.rs b/crates/bcm2835-lpa/src/pwm0/dat1.rs new file mode 100644 index 0000000..c197492 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/dat1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel 1 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat1](index.html) module"] +pub struct DAT1_SPEC; +impl crate::RegisterSpec for DAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dat1::R](R) reader structure"] +impl crate::Readable for DAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dat1::W](W) writer structure"] +impl crate::Writable for DAT1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAT1 to value 0"] +impl crate::Resettable for DAT1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pwm0/dat2.rs b/crates/bcm2835-lpa/src/pwm0/dat2.rs new file mode 100644 index 0000000..b9e07a3 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/dat2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel 2 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat2](index.html) module"] +pub struct DAT2_SPEC; +impl crate::RegisterSpec for DAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dat2::R](R) reader structure"] +impl crate::Readable for DAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dat2::W](W) writer structure"] +impl crate::Writable for DAT2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAT2 to value 0"] +impl crate::Resettable for DAT2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pwm0/dmac.rs b/crates/bcm2835-lpa/src/pwm0/dmac.rs new file mode 100644 index 0000000..b201822 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/dmac.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DMAC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMAC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DREQ` reader - DMA threshold for DREQ signal"] +pub type DREQ_R = crate::FieldReader; +#[doc = "Field `DREQ` writer - DMA threshold for DREQ signal"] +pub type DREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +#[doc = "Field `PANIC` reader - DMA threshold for panic signal"] +pub type PANIC_R = crate::FieldReader; +#[doc = "Field `PANIC` writer - DMA threshold for panic signal"] +pub type PANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +#[doc = "Field `ENAB` reader - DMA enabled"] +pub type ENAB_R = crate::BitReader; +#[doc = "Field `ENAB` writer - DMA enabled"] +pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] + #[inline(always)] + pub fn dreq(&self) -> DREQ_R { + DREQ_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA threshold for panic signal"] + #[inline(always)] + pub fn panic(&self) -> PANIC_R { + PANIC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 31 - DMA enabled"] + #[inline(always)] + pub fn enab(&self) -> ENAB_R { + ENAB_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] + #[inline(always)] + #[must_use] + pub fn dreq(&mut self) -> DREQ_W<0> { + DREQ_W::new(self) + } + #[doc = "Bits 8:15 - DMA threshold for panic signal"] + #[inline(always)] + #[must_use] + pub fn panic(&mut self) -> PANIC_W<8> { + PANIC_W::new(self) + } + #[doc = "Bit 31 - DMA enabled"] + #[inline(always)] + #[must_use] + pub fn enab(&mut self) -> ENAB_W<31> { + ENAB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac](index.html) module"] +pub struct DMAC_SPEC; +impl crate::RegisterSpec for DMAC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmac::R](R) reader structure"] +impl crate::Readable for DMAC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmac::W](W) writer structure"] +impl crate::Writable for DMAC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMAC to value 0"] +impl crate::Resettable for DMAC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pwm0/fif1.rs b/crates/bcm2835-lpa/src/pwm0/fif1.rs new file mode 100644 index 0000000..e786328 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/fif1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FIF1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO input\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fif1](index.html) module"] +pub struct FIF1_SPEC; +impl crate::RegisterSpec for FIF1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fif1::W](W) writer structure"] +impl crate::Writable for FIF1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIF1 to value 0"] +impl crate::Resettable for FIF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/pwm0/rng1.rs b/crates/bcm2835-lpa/src/pwm0/rng1.rs new file mode 100644 index 0000000..b6f5446 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/rng1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RNG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RNG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Range for channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng1](index.html) module"] +pub struct RNG1_SPEC; +impl crate::RegisterSpec for RNG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rng1::R](R) reader structure"] +impl crate::Readable for RNG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rng1::W](W) writer structure"] +impl crate::Writable for RNG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG1 to value 0x20"] +impl crate::Resettable for RNG1_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/crates/bcm2835-lpa/src/pwm0/rng2.rs b/crates/bcm2835-lpa/src/pwm0/rng2.rs new file mode 100644 index 0000000..0cc95d5 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/rng2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RNG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RNG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Range for channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng2](index.html) module"] +pub struct RNG2_SPEC; +impl crate::RegisterSpec for RNG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rng2::R](R) reader structure"] +impl crate::Readable for RNG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rng2::W](W) writer structure"] +impl crate::Writable for RNG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG2 to value 0x20"] +impl crate::Resettable for RNG2_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/crates/bcm2835-lpa/src/pwm0/sta.rs b/crates/bcm2835-lpa/src/pwm0/sta.rs new file mode 100644 index 0000000..f0b99b7 --- /dev/null +++ b/crates/bcm2835-lpa/src/pwm0/sta.rs @@ -0,0 +1,260 @@ +#[doc = "Register `STA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FULL1` reader - FIFO full"] +pub type FULL1_R = crate::BitReader; +#[doc = "Field `FULL1` writer - FIFO full"] +pub type FULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `EMPT1` reader - FIFO empty"] +pub type EMPT1_R = crate::BitReader; +#[doc = "Field `EMPT1` writer - FIFO empty"] +pub type EMPT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `WERR1` reader - FIFO write error"] +pub type WERR1_R = crate::BitReader; +#[doc = "Field `WERR1` writer - FIFO write error"] +pub type WERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `RERR1` reader - FIFO read error"] +pub type RERR1_R = crate::BitReader; +#[doc = "Field `RERR1` writer - FIFO read error"] +pub type RERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO1` reader - Channel 1 gap occurred"] +pub type GAPO1_R = crate::BitReader; +#[doc = "Field `GAPO1` writer - Channel 1 gap occurred"] +pub type GAPO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO2` reader - Channel 2 gap occurred"] +pub type GAPO2_R = crate::BitReader; +#[doc = "Field `GAPO2` writer - Channel 2 gap occurred"] +pub type GAPO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO3` reader - Channel 3 gap occurred"] +pub type GAPO3_R = crate::BitReader; +#[doc = "Field `GAPO3` writer - Channel 3 gap occurred"] +pub type GAPO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO4` reader - Channel 4 gap occurred"] +pub type GAPO4_R = crate::BitReader; +#[doc = "Field `GAPO4` writer - Channel 4 gap occurred"] +pub type GAPO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Bus error"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Bus error"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA1` reader - Channel 1 state"] +pub type STA1_R = crate::BitReader; +#[doc = "Field `STA1` writer - Channel 1 state"] +pub type STA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA2` reader - Channel 2 state"] +pub type STA2_R = crate::BitReader; +#[doc = "Field `STA2` writer - Channel 2 state"] +pub type STA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA3` reader - Channel 3 state"] +pub type STA3_R = crate::BitReader; +#[doc = "Field `STA3` writer - Channel 3 state"] +pub type STA3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA4` reader - Channel 4 state"] +pub type STA4_R = crate::BitReader; +#[doc = "Field `STA4` writer - Channel 4 state"] +pub type STA4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - FIFO full"] + #[inline(always)] + pub fn full1(&self) -> FULL1_R { + FULL1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO empty"] + #[inline(always)] + pub fn empt1(&self) -> EMPT1_R { + EMPT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO write error"] + #[inline(always)] + pub fn werr1(&self) -> WERR1_R { + WERR1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO read error"] + #[inline(always)] + pub fn rerr1(&self) -> RERR1_R { + RERR1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 1 gap occurred"] + #[inline(always)] + pub fn gapo1(&self) -> GAPO1_R { + GAPO1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 2 gap occurred"] + #[inline(always)] + pub fn gapo2(&self) -> GAPO2_R { + GAPO2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 3 gap occurred"] + #[inline(always)] + pub fn gapo3(&self) -> GAPO3_R { + GAPO3_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 4 gap occurred"] + #[inline(always)] + pub fn gapo4(&self) -> GAPO4_R { + GAPO4_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Bus error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 1 state"] + #[inline(always)] + pub fn sta1(&self) -> STA1_R { + STA1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 2 state"] + #[inline(always)] + pub fn sta2(&self) -> STA2_R { + STA2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 3 state"] + #[inline(always)] + pub fn sta3(&self) -> STA3_R { + STA3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 4 state"] + #[inline(always)] + pub fn sta4(&self) -> STA4_R { + STA4_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FIFO full"] + #[inline(always)] + #[must_use] + pub fn full1(&mut self) -> FULL1_W<0> { + FULL1_W::new(self) + } + #[doc = "Bit 1 - FIFO empty"] + #[inline(always)] + #[must_use] + pub fn empt1(&mut self) -> EMPT1_W<1> { + EMPT1_W::new(self) + } + #[doc = "Bit 2 - FIFO write error"] + #[inline(always)] + #[must_use] + pub fn werr1(&mut self) -> WERR1_W<2> { + WERR1_W::new(self) + } + #[doc = "Bit 3 - FIFO read error"] + #[inline(always)] + #[must_use] + pub fn rerr1(&mut self) -> RERR1_W<3> { + RERR1_W::new(self) + } + #[doc = "Bit 4 - Channel 1 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo1(&mut self) -> GAPO1_W<4> { + GAPO1_W::new(self) + } + #[doc = "Bit 5 - Channel 2 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo2(&mut self) -> GAPO2_W<5> { + GAPO2_W::new(self) + } + #[doc = "Bit 6 - Channel 3 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo3(&mut self) -> GAPO3_W<6> { + GAPO3_W::new(self) + } + #[doc = "Bit 7 - Channel 4 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo4(&mut self) -> GAPO4_W<7> { + GAPO4_W::new(self) + } + #[doc = "Bit 8 - Bus error"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<8> { + BERR_W::new(self) + } + #[doc = "Bit 9 - Channel 1 state"] + #[inline(always)] + #[must_use] + pub fn sta1(&mut self) -> STA1_W<9> { + STA1_W::new(self) + } + #[doc = "Bit 10 - Channel 2 state"] + #[inline(always)] + #[must_use] + pub fn sta2(&mut self) -> STA2_W<10> { + STA2_W::new(self) + } + #[doc = "Bit 11 - Channel 3 state"] + #[inline(always)] + #[must_use] + pub fn sta3(&mut self) -> STA3_W<11> { + STA3_W::new(self) + } + #[doc = "Bit 12 - Channel 4 state"] + #[inline(always)] + #[must_use] + pub fn sta4(&mut self) -> STA4_W<12> { + STA4_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"] +pub struct STA_SPEC; +impl crate::RegisterSpec for STA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sta::R](R) reader structure"] +impl crate::Readable for STA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sta::W](W) writer structure"] +impl crate::Writable for STA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STA to value 0"] +impl crate::Resettable for STA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi0.rs b/crates/bcm2835-lpa/src/spi0.rs new file mode 100644 index 0000000..88737df --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control and Status"] + pub cs: CS, + #[doc = "0x04 - FIFO access"] + pub fifo: FIFO, + #[doc = "0x08 - Clock divider"] + pub clk: CLK, + #[doc = "0x0c - Data length"] + pub dlen: DLEN, + #[doc = "0x10 - LoSSI output hold delay"] + pub ltoh: LTOH, + #[doc = "0x14 - "] + pub dc: DC, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control and Status"] +pub mod cs; +#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +pub type FIFO = crate::Reg; +#[doc = "FIFO access"] +pub mod fifo; +#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +pub type CLK = crate::Reg; +#[doc = "Clock divider"] +pub mod clk; +#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +pub type DLEN = crate::Reg; +#[doc = "Data length"] +pub mod dlen; +#[doc = "LTOH (rw) register accessor: an alias for `Reg`"] +pub type LTOH = crate::Reg; +#[doc = "LoSSI output hold delay"] +pub mod ltoh; +#[doc = "DC (rw) register accessor: an alias for `Reg`"] +pub type DC = crate::Reg; +#[doc = ""] +pub mod dc; diff --git a/crates/bcm2835-lpa/src/spi0/clk.rs b/crates/bcm2835-lpa/src/spi0/clk.rs new file mode 100644 index 0000000..ef3272e --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0/clk.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CLK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CDIV` reader - Clock divider"] +pub type CDIV_R = crate::FieldReader; +#[doc = "Field `CDIV` writer - Clock divider"] +pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Clock divider"] + #[inline(always)] + pub fn cdiv(&self) -> CDIV_R { + CDIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Clock divider"] + #[inline(always)] + #[must_use] + pub fn cdiv(&mut self) -> CDIV_W<0> { + CDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clk::R](R) reader structure"] +impl crate::Readable for CLK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +impl crate::Writable for CLK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi0/cs.rs b/crates/bcm2835-lpa/src/spi0/cs.rs new file mode 100644 index 0000000..50227aa --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0/cs.rs @@ -0,0 +1,446 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CS` reader - Chip select"] +pub type CS_R = crate::FieldReader; +#[doc = "Field `CS` writer - Chip select"] +pub type CS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +#[doc = "Field `CPHA` reader - Clock phase"] +pub type CPHA_R = crate::BitReader; +#[doc = "Field `CPHA` writer - Clock phase"] +pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CPOL` reader - Clock polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Field `CPOL` writer - Clock polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CLEAR` reader - Clear the FIFO(s)"] +pub type CLEAR_R = crate::FieldReader; +#[doc = "Clear the FIFO(s)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CLEAR_A { + #[doc = "1: `1`"] + TX = 1, + #[doc = "2: `10`"] + RX = 2, + #[doc = "3: `11`"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_A) -> Self { + variant as _ + } +} +impl CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CLEAR_A::TX), + 2 => Some(CLEAR_A::RX), + 3 => Some(CLEAR_A::BOTH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + *self == CLEAR_A::TX + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + *self == CLEAR_A::RX + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == CLEAR_A::BOTH + } +} +#[doc = "Field `CLEAR` writer - Clear the FIFO(s)"] +pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, CLEAR_A, 2, O>; +impl<'a, const O: u8> CLEAR_W<'a, O> { + #[doc = "`1`"] + #[inline(always)] + pub fn tx(self) -> &'a mut W { + self.variant(CLEAR_A::TX) + } + #[doc = "`10`"] + #[inline(always)] + pub fn rx(self) -> &'a mut W { + self.variant(CLEAR_A::RX) + } + #[doc = "`11`"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(CLEAR_A::BOTH) + } +} +#[doc = "Field `CSPOL` reader - Chip select polarity"] +pub type CSPOL_R = crate::BitReader; +#[doc = "Field `CSPOL` writer - Chip select polarity"] +pub type CSPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `TA` reader - Transfer active"] +pub type TA_R = crate::BitReader; +#[doc = "Field `TA` writer - Transfer active"] +pub type TA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - Enable DMA"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - Enable DMA"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `INTD` reader - Interrupt on done"] +pub type INTD_R = crate::BitReader; +#[doc = "Field `INTD` writer - Interrupt on done"] +pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `INTR` reader - Interrupt on RX"] +pub type INTR_R = crate::BitReader; +#[doc = "Field `INTR` writer - Interrupt on RX"] +pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `ADCS` reader - Automatically deassert chip select"] +pub type ADCS_R = crate::BitReader; +#[doc = "Field `ADCS` writer - Automatically deassert chip select"] +pub type ADCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `REN` reader - Read enable"] +pub type REN_R = crate::BitReader; +#[doc = "Field `REN` writer - Read enable"] +pub type REN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LEN` reader - LoSSI enable"] +pub type LEN_R = crate::BitReader; +#[doc = "Field `LEN` writer - LoSSI enable"] +pub type LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LMONO` reader - "] +pub type LMONO_R = crate::BitReader; +#[doc = "Field `LMONO` writer - "] +pub type LMONO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `TE_EN` reader - "] +pub type TE_EN_R = crate::BitReader; +#[doc = "Field `TE_EN` writer - "] +pub type TE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DONE` reader - Transfer is done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `RXD` reader - RX FIFO contains data"] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXD` reader - TX FIFO can accept data"] +pub type TXD_R = crate::BitReader; +#[doc = "Field `RXR` reader - RX FIFO has data to be read"] +pub type RXR_R = crate::BitReader; +#[doc = "Field `RXF` reader - RX FIFO full"] +pub type RXF_R = crate::BitReader; +#[doc = "Field `CSPOL0` reader - Chip select 0 polarity"] +pub type CSPOL0_R = crate::BitReader; +#[doc = "Field `CSPOL0` writer - Chip select 0 polarity"] +pub type CSPOL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CSPOL1` reader - Chip select 1 polarity"] +pub type CSPOL1_R = crate::BitReader; +#[doc = "Field `CSPOL1` writer - Chip select 1 polarity"] +pub type CSPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CSPOL2` reader - Chip select 2 polarity"] +pub type CSPOL2_R = crate::BitReader; +#[doc = "Field `CSPOL2` writer - Chip select 2 polarity"] +pub type CSPOL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"] +pub type DMA_LEN_R = crate::BitReader; +#[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"] +pub type DMA_LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"] +pub type LEN_LONG_R = crate::BitReader; +#[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"] +pub type LEN_LONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Chip select"] + #[inline(always)] + pub fn cs(&self) -> CS_R { + CS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Clock phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clock polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Clear the FIFO(s)"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Chip select polarity"] + #[inline(always)] + pub fn cspol(&self) -> CSPOL_R { + CSPOL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transfer active"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable DMA"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on done"] + #[inline(always)] + pub fn intd(&self) -> INTD_R { + INTD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Automatically deassert chip select"] + #[inline(always)] + pub fn adcs(&self) -> ADCS_R { + ADCS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Read enable"] + #[inline(always)] + pub fn ren(&self) -> REN_R { + REN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LoSSI enable"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn lmono(&self) -> LMONO_R { + LMONO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn te_en(&self) -> TE_EN_R { + TE_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Transfer is done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - RX FIFO contains data"] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - TX FIFO can accept data"] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RX FIFO has data to be read"] + #[inline(always)] + pub fn rxr(&self) -> RXR_R { + RXR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - RX FIFO full"] + #[inline(always)] + pub fn rxf(&self) -> RXF_R { + RXF_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Chip select 0 polarity"] + #[inline(always)] + pub fn cspol0(&self) -> CSPOL0_R { + CSPOL0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Chip select 1 polarity"] + #[inline(always)] + pub fn cspol1(&self) -> CSPOL1_R { + CSPOL1_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Chip select 2 polarity"] + #[inline(always)] + pub fn cspol2(&self) -> CSPOL2_R { + CSPOL2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable DMA in LoSSI mode"] + #[inline(always)] + pub fn dma_len(&self) -> DMA_LEN_R { + DMA_LEN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Enable long data word in LoSSI mode"] + #[inline(always)] + pub fn len_long(&self) -> LEN_LONG_R { + LEN_LONG_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Chip select"] + #[inline(always)] + #[must_use] + pub fn cs(&mut self) -> CS_W<0> { + CS_W::new(self) + } + #[doc = "Bit 2 - Clock phase"] + #[inline(always)] + #[must_use] + pub fn cpha(&mut self) -> CPHA_W<2> { + CPHA_W::new(self) + } + #[doc = "Bit 3 - Clock polarity"] + #[inline(always)] + #[must_use] + pub fn cpol(&mut self) -> CPOL_W<3> { + CPOL_W::new(self) + } + #[doc = "Bits 4:5 - Clear the FIFO(s)"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<4> { + CLEAR_W::new(self) + } + #[doc = "Bit 6 - Chip select polarity"] + #[inline(always)] + #[must_use] + pub fn cspol(&mut self) -> CSPOL_W<6> { + CSPOL_W::new(self) + } + #[doc = "Bit 7 - Transfer active"] + #[inline(always)] + #[must_use] + pub fn ta(&mut self) -> TA_W<7> { + TA_W::new(self) + } + #[doc = "Bit 8 - Enable DMA"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<8> { + DMAEN_W::new(self) + } + #[doc = "Bit 9 - Interrupt on done"] + #[inline(always)] + #[must_use] + pub fn intd(&mut self) -> INTD_W<9> { + INTD_W::new(self) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W<10> { + INTR_W::new(self) + } + #[doc = "Bit 11 - Automatically deassert chip select"] + #[inline(always)] + #[must_use] + pub fn adcs(&mut self) -> ADCS_W<11> { + ADCS_W::new(self) + } + #[doc = "Bit 12 - Read enable"] + #[inline(always)] + #[must_use] + pub fn ren(&mut self) -> REN_W<12> { + REN_W::new(self) + } + #[doc = "Bit 13 - LoSSI enable"] + #[inline(always)] + #[must_use] + pub fn len(&mut self) -> LEN_W<13> { + LEN_W::new(self) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn lmono(&mut self) -> LMONO_W<14> { + LMONO_W::new(self) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn te_en(&mut self) -> TE_EN_W<15> { + TE_EN_W::new(self) + } + #[doc = "Bit 21 - Chip select 0 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol0(&mut self) -> CSPOL0_W<21> { + CSPOL0_W::new(self) + } + #[doc = "Bit 22 - Chip select 1 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol1(&mut self) -> CSPOL1_W<22> { + CSPOL1_W::new(self) + } + #[doc = "Bit 23 - Chip select 2 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol2(&mut self) -> CSPOL2_W<23> { + CSPOL2_W::new(self) + } + #[doc = "Bit 24 - Enable DMA in LoSSI mode"] + #[inline(always)] + #[must_use] + pub fn dma_len(&mut self) -> DMA_LEN_W<24> { + DMA_LEN_W::new(self) + } + #[doc = "Bit 25 - Enable long data word in LoSSI mode"] + #[inline(always)] + #[must_use] + pub fn len_long(&mut self) -> LEN_LONG_W<25> { + LEN_LONG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0x0004_1000"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_1000; +} diff --git a/crates/bcm2835-lpa/src/spi0/dc.rs b/crates/bcm2835-lpa/src/spi0/dc.rs new file mode 100644 index 0000000..281dd71 --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0/dc.rs @@ -0,0 +1,125 @@ +#[doc = "Register `DC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDREQ` reader - DMA Write request threshold"] +pub type TDREQ_R = crate::FieldReader; +#[doc = "Field `TDREQ` writer - DMA Write request threshold"] +pub type TDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `TPANIC` reader - DMA write panic threshold"] +pub type TPANIC_R = crate::FieldReader; +#[doc = "Field `TPANIC` writer - DMA write panic threshold"] +pub type TPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `RDREQ` reader - DMA read request threshold"] +pub type RDREQ_R = crate::FieldReader; +#[doc = "Field `RDREQ` writer - DMA read request threshold"] +pub type RDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `RPANIC` reader - DMA read panic threshold"] +pub type RPANIC_R = crate::FieldReader; +#[doc = "Field `RPANIC` writer - DMA read panic threshold"] +pub type RPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA Write request threshold"] + #[inline(always)] + pub fn tdreq(&self) -> TDREQ_R { + TDREQ_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA write panic threshold"] + #[inline(always)] + pub fn tpanic(&self) -> TPANIC_R { + TPANIC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA read request threshold"] + #[inline(always)] + pub fn rdreq(&self) -> RDREQ_R { + RDREQ_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA read panic threshold"] + #[inline(always)] + pub fn rpanic(&self) -> RPANIC_R { + RPANIC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA Write request threshold"] + #[inline(always)] + #[must_use] + pub fn tdreq(&mut self) -> TDREQ_W<0> { + TDREQ_W::new(self) + } + #[doc = "Bits 8:15 - DMA write panic threshold"] + #[inline(always)] + #[must_use] + pub fn tpanic(&mut self) -> TPANIC_W<8> { + TPANIC_W::new(self) + } + #[doc = "Bits 16:23 - DMA read request threshold"] + #[inline(always)] + #[must_use] + pub fn rdreq(&mut self) -> RDREQ_W<16> { + RDREQ_W::new(self) + } + #[doc = "Bits 24:31 - DMA read panic threshold"] + #[inline(always)] + #[must_use] + pub fn rpanic(&mut self) -> RPANIC_W<24> { + RPANIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc](index.html) module"] +pub struct DC_SPEC; +impl crate::RegisterSpec for DC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dc::R](R) reader structure"] +impl crate::Readable for DC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dc::W](W) writer structure"] +impl crate::Writable for DC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DC to value 0x3020_1050"] +impl crate::Resettable for DC_SPEC { + const RESET_VALUE: Self::Ux = 0x3020_1050; +} diff --git a/crates/bcm2835-lpa/src/spi0/dlen.rs b/crates/bcm2835-lpa/src/spi0/dlen.rs new file mode 100644 index 0000000..25e2771 --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0/dlen.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLEN` reader - Data length"] +pub type DLEN_R = crate::FieldReader; +#[doc = "Field `DLEN` writer - Data length"] +pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + pub fn dlen(&self) -> DLEN_R { + DLEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + #[must_use] + pub fn dlen(&mut self) -> DLEN_W<0> { + DLEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +pub struct DLEN_SPEC; +impl crate::RegisterSpec for DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dlen::R](R) reader structure"] +impl crate::Readable for DLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +impl crate::Writable for DLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLEN to value 0"] +impl crate::Resettable for DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi0/fifo.rs b/crates/bcm2835-lpa/src/spi0/fifo.rs new file mode 100644 index 0000000..46d2ece --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0/fifo.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FIFO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo::R](R) reader structure"] +impl crate::Readable for FIFO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi0/ltoh.rs b/crates/bcm2835-lpa/src/spi0/ltoh.rs new file mode 100644 index 0000000..5d0ab3f --- /dev/null +++ b/crates/bcm2835-lpa/src/spi0/ltoh.rs @@ -0,0 +1,80 @@ +#[doc = "Register `LTOH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LTOH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOH` reader - Output hold delay"] +pub type TOH_R = crate::FieldReader; +#[doc = "Field `TOH` writer - Output hold delay"] +pub type TOH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LTOH_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Output hold delay"] + #[inline(always)] + pub fn toh(&self) -> TOH_R { + TOH_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Output hold delay"] + #[inline(always)] + #[must_use] + pub fn toh(&mut self) -> TOH_W<0> { + TOH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LoSSI output hold delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ltoh](index.html) module"] +pub struct LTOH_SPEC; +impl crate::RegisterSpec for LTOH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ltoh::R](R) reader structure"] +impl crate::Readable for LTOH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ltoh::W](W) writer structure"] +impl crate::Writable for LTOH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LTOH to value 0x01"] +impl crate::Resettable for LTOH_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/crates/bcm2835-lpa/src/spi1.rs b/crates/bcm2835-lpa/src/spi1.rs new file mode 100644 index 0000000..1547fcc --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control 0"] + pub cntl0: CNTL0, + #[doc = "0x04 - Control 1"] + pub cntl1: CNTL1, + #[doc = "0x08 - Status"] + pub stat: STAT, + #[doc = "0x0c - Read the RXFIFO without removing an entry"] + pub peek: PEEK, + #[doc = "0x10..0x20 - Writing to the FIFO will deassert CS at the end of the access"] + pub io: [IO; 4], + #[doc = "0x20..0x30 - Writing to the FIFO will maintain CS at the end of the access"] + pub txhold: [TXHOLD; 4], +} +#[doc = "CNTL0 (rw) register accessor: an alias for `Reg`"] +pub type CNTL0 = crate::Reg; +#[doc = "Control 0"] +pub mod cntl0; +#[doc = "CNTL1 (rw) register accessor: an alias for `Reg`"] +pub type CNTL1 = crate::Reg; +#[doc = "Control 1"] +pub mod cntl1; +#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "PEEK (r) register accessor: an alias for `Reg`"] +pub type PEEK = crate::Reg; +#[doc = "Read the RXFIFO without removing an entry"] +pub mod peek; +#[doc = "IO (rw) register accessor: an alias for `Reg`"] +pub type IO = crate::Reg; +#[doc = "Writing to the FIFO will deassert CS at the end of the access"] +pub mod io; +#[doc = "TXHOLD (rw) register accessor: an alias for `Reg`"] +pub type TXHOLD = crate::Reg; +#[doc = "Writing to the FIFO will maintain CS at the end of the access"] +pub mod txhold; diff --git a/crates/bcm2835-lpa/src/spi1/cntl0.rs b/crates/bcm2835-lpa/src/spi1/cntl0.rs new file mode 100644 index 0000000..b9354b5 --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1/cntl0.rs @@ -0,0 +1,335 @@ +#[doc = "Register `CNTL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFT_LENGTH` reader - Number of bits to shift"] +pub type SHIFT_LENGTH_R = crate::FieldReader; +#[doc = "Field `SHIFT_LENGTH` writer - Number of bits to shift"] +pub type SHIFT_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 6, O>; +#[doc = "Field `MSB_FIRST` reader - Shift out the most significant bit (MSB) first"] +pub type MSB_FIRST_R = crate::BitReader; +#[doc = "Field `MSB_FIRST` writer - Shift out the most significant bit (MSB) first"] +pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `INVERT_CLK` reader - Idle clock high"] +pub type INVERT_CLK_R = crate::BitReader; +#[doc = "Field `INVERT_CLK` writer - Idle clock high"] +pub type INVERT_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `OUT_RISING` reader - Data is clocked out on rising edge of CLK"] +pub type OUT_RISING_R = crate::BitReader; +#[doc = "Field `OUT_RISING` writer - Data is clocked out on rising edge of CLK"] +pub type OUT_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `CLEAR_FIFOS` reader - Clear FIFOs"] +pub type CLEAR_FIFOS_R = crate::BitReader; +#[doc = "Field `CLEAR_FIFOS` writer - Clear FIFOs"] +pub type CLEAR_FIFOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `IN_RISING` reader - Data is clocked in on rising edge of CLK"] +pub type IN_RISING_R = crate::BitReader; +#[doc = "Field `IN_RISING` writer - Data is clocked in on rising edge of CLK"] +pub type IN_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable the interface"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable the interface"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `DOUT_HOLD_TIME` reader - Controls extra DOUT hold time in system clock cycles"] +pub type DOUT_HOLD_TIME_R = crate::FieldReader; +#[doc = "Controls extra DOUT hold time in system clock cycles\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DOUT_HOLD_TIME_A { + #[doc = "0: `0`"] + _0 = 0, + #[doc = "1: `1`"] + _1 = 1, + #[doc = "2: `10`"] + _4 = 2, + #[doc = "3: `11`"] + _7 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOUT_HOLD_TIME_A) -> Self { + variant as _ + } +} +impl DOUT_HOLD_TIME_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOUT_HOLD_TIME_A { + match self.bits { + 0 => DOUT_HOLD_TIME_A::_0, + 1 => DOUT_HOLD_TIME_A::_1, + 2 => DOUT_HOLD_TIME_A::_4, + 3 => DOUT_HOLD_TIME_A::_7, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_1 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_4 + } + #[doc = "Checks if the value of the field is `_7`"] + #[inline(always)] + pub fn is_7(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_7 + } +} +#[doc = "Field `DOUT_HOLD_TIME` writer - Controls extra DOUT hold time in system clock cycles"] +pub type DOUT_HOLD_TIME_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CNTL0_SPEC, u8, DOUT_HOLD_TIME_A, 2, O>; +impl<'a, const O: u8> DOUT_HOLD_TIME_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_0) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_1) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_4) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _7(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_7) + } +} +#[doc = "Field `VARIABLE_WIDTH` reader - Take shift length and data from FIFO"] +pub type VARIABLE_WIDTH_R = crate::BitReader; +#[doc = "Field `VARIABLE_WIDTH` writer - Take shift length and data from FIFO"] +pub type VARIABLE_WIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `VARIABLE_CS` reader - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] +pub type VARIABLE_CS_R = crate::BitReader; +#[doc = "Field `VARIABLE_CS` writer - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] +pub type VARIABLE_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `POST_INPUT` reader - Post input mode"] +pub type POST_INPUT_R = crate::BitReader; +#[doc = "Field `POST_INPUT` writer - Post input mode"] +pub type POST_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `CHIP_SELECTS` reader - The CS pattern when active"] +pub type CHIP_SELECTS_R = crate::FieldReader; +#[doc = "Field `CHIP_SELECTS` writer - The CS pattern when active"] +pub type CHIP_SELECTS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 3, O>; +#[doc = "Field `SPEED` reader - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Field `SPEED` writer - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] +pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:5 - Number of bits to shift"] + #[inline(always)] + pub fn shift_length(&self) -> SHIFT_LENGTH_R { + SHIFT_LENGTH_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] + #[inline(always)] + pub fn msb_first(&self) -> MSB_FIRST_R { + MSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Idle clock high"] + #[inline(always)] + pub fn invert_clk(&self) -> INVERT_CLK_R { + INVERT_CLK_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] + #[inline(always)] + pub fn out_rising(&self) -> OUT_RISING_R { + OUT_RISING_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Clear FIFOs"] + #[inline(always)] + pub fn clear_fifos(&self) -> CLEAR_FIFOS_R { + CLEAR_FIFOS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] + #[inline(always)] + pub fn in_rising(&self) -> IN_RISING_R { + IN_RISING_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable the interface"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] + #[inline(always)] + pub fn dout_hold_time(&self) -> DOUT_HOLD_TIME_R { + DOUT_HOLD_TIME_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Take shift length and data from FIFO"] + #[inline(always)] + pub fn variable_width(&self) -> VARIABLE_WIDTH_R { + VARIABLE_WIDTH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] + #[inline(always)] + pub fn variable_cs(&self) -> VARIABLE_CS_R { + VARIABLE_CS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Post input mode"] + #[inline(always)] + pub fn post_input(&self) -> POST_INPUT_R { + POST_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - The CS pattern when active"] + #[inline(always)] + pub fn chip_selects(&self) -> CHIP_SELECTS_R { + CHIP_SELECTS_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:5 - Number of bits to shift"] + #[inline(always)] + #[must_use] + pub fn shift_length(&mut self) -> SHIFT_LENGTH_W<0> { + SHIFT_LENGTH_W::new(self) + } + #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] + #[inline(always)] + #[must_use] + pub fn msb_first(&mut self) -> MSB_FIRST_W<6> { + MSB_FIRST_W::new(self) + } + #[doc = "Bit 7 - Idle clock high"] + #[inline(always)] + #[must_use] + pub fn invert_clk(&mut self) -> INVERT_CLK_W<7> { + INVERT_CLK_W::new(self) + } + #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] + #[inline(always)] + #[must_use] + pub fn out_rising(&mut self) -> OUT_RISING_W<8> { + OUT_RISING_W::new(self) + } + #[doc = "Bit 9 - Clear FIFOs"] + #[inline(always)] + #[must_use] + pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W<9> { + CLEAR_FIFOS_W::new(self) + } + #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] + #[inline(always)] + #[must_use] + pub fn in_rising(&mut self) -> IN_RISING_W<10> { + IN_RISING_W::new(self) + } + #[doc = "Bit 11 - Enable the interface"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<11> { + ENABLE_W::new(self) + } + #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] + #[inline(always)] + #[must_use] + pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W<12> { + DOUT_HOLD_TIME_W::new(self) + } + #[doc = "Bit 14 - Take shift length and data from FIFO"] + #[inline(always)] + #[must_use] + pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W<14> { + VARIABLE_WIDTH_W::new(self) + } + #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] + #[inline(always)] + #[must_use] + pub fn variable_cs(&mut self) -> VARIABLE_CS_W<15> { + VARIABLE_CS_W::new(self) + } + #[doc = "Bit 16 - Post input mode"] + #[inline(always)] + #[must_use] + pub fn post_input(&mut self) -> POST_INPUT_W<16> { + POST_INPUT_W::new(self) + } + #[doc = "Bits 17:19 - The CS pattern when active"] + #[inline(always)] + #[must_use] + pub fn chip_selects(&mut self) -> CHIP_SELECTS_W<17> { + CHIP_SELECTS_W::new(self) + } + #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W<20> { + SPEED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl0](index.html) module"] +pub struct CNTL0_SPEC; +impl crate::RegisterSpec for CNTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl0::R](R) reader structure"] +impl crate::Readable for CNTL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl0::W](W) writer structure"] +impl crate::Writable for CNTL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL0 to value 0x000e_0000"] +impl crate::Resettable for CNTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x000e_0000; +} diff --git a/crates/bcm2835-lpa/src/spi1/cntl1.rs b/crates/bcm2835-lpa/src/spi1/cntl1.rs new file mode 100644 index 0000000..c7d627b --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1/cntl1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CNTL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEEP_INPUT` reader - Don't clear the RX shift register before a new transaction"] +pub type KEEP_INPUT_R = crate::BitReader; +#[doc = "Field `KEEP_INPUT` writer - Don't clear the RX shift register before a new transaction"] +pub type KEEP_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `MSB_FIRST` reader - Shift the most significant bit first (MSB)"] +pub type MSB_FIRST_R = crate::BitReader; +#[doc = "Field `MSB_FIRST` writer - Shift the most significant bit first (MSB)"] +pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `DONE_ENABLE` reader - Enable DONE interrupt"] +pub type DONE_ENABLE_R = crate::BitReader; +#[doc = "Field `DONE_ENABLE` writer - Enable DONE interrupt"] +pub type DONE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `TXE_ENABLE` reader - Enable TX empty interrupt"] +pub type TXE_ENABLE_R = crate::BitReader; +#[doc = "Field `TXE_ENABLE` writer - Enable TX empty interrupt"] +pub type TXE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `CS_HIGH_TIME` reader - Additional SPI clock cycles where CS is high"] +pub type CS_HIGH_TIME_R = crate::FieldReader; +#[doc = "Field `CS_HIGH_TIME` writer - Additional SPI clock cycles where CS is high"] +pub type CS_HIGH_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL1_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] + #[inline(always)] + pub fn keep_input(&self) -> KEEP_INPUT_R { + KEEP_INPUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] + #[inline(always)] + pub fn msb_first(&self) -> MSB_FIRST_R { + MSB_FIRST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Enable DONE interrupt"] + #[inline(always)] + pub fn done_enable(&self) -> DONE_ENABLE_R { + DONE_ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable TX empty interrupt"] + #[inline(always)] + pub fn txe_enable(&self) -> TXE_ENABLE_R { + TXE_ENABLE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] + #[inline(always)] + pub fn cs_high_time(&self) -> CS_HIGH_TIME_R { + CS_HIGH_TIME_R::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] + #[inline(always)] + #[must_use] + pub fn keep_input(&mut self) -> KEEP_INPUT_W<0> { + KEEP_INPUT_W::new(self) + } + #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] + #[inline(always)] + #[must_use] + pub fn msb_first(&mut self) -> MSB_FIRST_W<1> { + MSB_FIRST_W::new(self) + } + #[doc = "Bit 6 - Enable DONE interrupt"] + #[inline(always)] + #[must_use] + pub fn done_enable(&mut self) -> DONE_ENABLE_W<6> { + DONE_ENABLE_W::new(self) + } + #[doc = "Bit 7 - Enable TX empty interrupt"] + #[inline(always)] + #[must_use] + pub fn txe_enable(&mut self) -> TXE_ENABLE_W<7> { + TXE_ENABLE_W::new(self) + } + #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] + #[inline(always)] + #[must_use] + pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W<8> { + CS_HIGH_TIME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl1](index.html) module"] +pub struct CNTL1_SPEC; +impl crate::RegisterSpec for CNTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl1::R](R) reader structure"] +impl crate::Readable for CNTL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl1::W](W) writer structure"] +impl crate::Writable for CNTL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL1 to value 0"] +impl crate::Resettable for CNTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi1/io.rs b/crates/bcm2835-lpa/src/spi1/io.rs new file mode 100644 index 0000000..365004d --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1/io.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IO%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IO%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO data access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +pub struct IO_SPEC; +impl crate::RegisterSpec for IO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [io::R](R) reader structure"] +impl crate::Readable for IO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +impl crate::Writable for IO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IO%s to value 0"] +impl crate::Resettable for IO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi1/peek.rs b/crates/bcm2835-lpa/src/spi1/peek.rs new file mode 100644 index 0000000..b4a7333 --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1/peek.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PEEK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Read the RXFIFO without removing an entry\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek](index.html) module"] +pub struct PEEK_SPEC; +impl crate::RegisterSpec for PEEK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek::R](R) reader structure"] +impl crate::Readable for PEEK_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PEEK to value 0"] +impl crate::Resettable for PEEK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi1/stat.rs b/crates/bcm2835-lpa/src/spi1/stat.rs new file mode 100644 index 0000000..0dd56f6 --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1/stat.rs @@ -0,0 +1,185 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIT_COUNT` reader - Number of bits left to be processed."] +pub type BIT_COUNT_R = crate::FieldReader; +#[doc = "Field `BIT_COUNT` writer - Number of bits left to be processed."] +pub type BIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 6, O>; +#[doc = "Field `BUSY` reader - Indicates a transfer is ongoing"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `BUSY` writer - Indicates a transfer is ongoing"] +pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_EMPTY` reader - RX FIFO is empty"] +pub type RX_EMPTY_R = crate::BitReader; +#[doc = "Field `RX_EMPTY` writer - RX FIFO is empty"] +pub type RX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_FULL` reader - RX FIFO is full"] +pub type RX_FULL_R = crate::BitReader; +#[doc = "Field `RX_FULL` writer - RX FIFO is full"] +pub type RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - TX FIFO is empty"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - TX FIFO is empty"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_FULL` reader - TX FIFO is full"] +pub type TX_FULL_R = crate::BitReader; +#[doc = "Field `TX_FULL` writer - TX FIFO is full"] +pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_LEVEL` reader - Number of entries in RX FIFO"] +pub type RX_LEVEL_R = crate::FieldReader; +#[doc = "Field `RX_LEVEL` writer - Number of entries in RX FIFO"] +pub type RX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_LEVEL` reader - Number of entries in TX FIFO"] +pub type TX_LEVEL_R = crate::FieldReader; +#[doc = "Field `TX_LEVEL` writer - Number of entries in TX FIFO"] +pub type TX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:5 - Number of bits left to be processed."] + #[inline(always)] + pub fn bit_count(&self) -> BIT_COUNT_R { + BIT_COUNT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Indicates a transfer is ongoing"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RX FIFO is empty"] + #[inline(always)] + pub fn rx_empty(&self) -> RX_EMPTY_R { + RX_EMPTY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is full"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TX FIFO is empty"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO is full"] + #[inline(always)] + pub fn tx_full(&self) -> TX_FULL_R { + TX_FULL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 16:19 - Number of entries in RX FIFO"] + #[inline(always)] + pub fn rx_level(&self) -> RX_LEVEL_R { + RX_LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Number of entries in TX FIFO"] + #[inline(always)] + pub fn tx_level(&self) -> TX_LEVEL_R { + TX_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Number of bits left to be processed."] + #[inline(always)] + #[must_use] + pub fn bit_count(&mut self) -> BIT_COUNT_W<0> { + BIT_COUNT_W::new(self) + } + #[doc = "Bit 6 - Indicates a transfer is ongoing"] + #[inline(always)] + #[must_use] + pub fn busy(&mut self) -> BUSY_W<6> { + BUSY_W::new(self) + } + #[doc = "Bit 7 - RX FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn rx_empty(&mut self) -> RX_EMPTY_W<7> { + RX_EMPTY_W::new(self) + } + #[doc = "Bit 8 - RX FIFO is full"] + #[inline(always)] + #[must_use] + pub fn rx_full(&mut self) -> RX_FULL_W<8> { + RX_FULL_W::new(self) + } + #[doc = "Bit 9 - TX FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<9> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 10 - TX FIFO is full"] + #[inline(always)] + #[must_use] + pub fn tx_full(&mut self) -> TX_FULL_W<10> { + TX_FULL_W::new(self) + } + #[doc = "Bits 16:19 - Number of entries in RX FIFO"] + #[inline(always)] + #[must_use] + pub fn rx_level(&mut self) -> RX_LEVEL_W<16> { + RX_LEVEL_W::new(self) + } + #[doc = "Bits 24:27 - Number of entries in TX FIFO"] + #[inline(always)] + #[must_use] + pub fn tx_level(&mut self) -> TX_LEVEL_W<24> { + TX_LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/spi1/txhold.rs b/crates/bcm2835-lpa/src/spi1/txhold.rs new file mode 100644 index 0000000..a2ca31b --- /dev/null +++ b/crates/bcm2835-lpa/src/spi1/txhold.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TXHOLD%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXHOLD%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO data access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXHOLD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txhold](index.html) module"] +pub struct TXHOLD_SPEC; +impl crate::RegisterSpec for TXHOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txhold::R](R) reader structure"] +impl crate::Readable for TXHOLD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txhold::W](W) writer structure"] +impl crate::Writable for TXHOLD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TXHOLD%s to value 0"] +impl crate::Resettable for TXHOLD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr.rs b/crates/bcm2835-lpa/src/systmr.rs new file mode 100644 index 0000000..859ea09 --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control / Status"] + pub cs: CS, + #[doc = "0x04 - Lower 32 bits for the free running counter"] + pub clo: CLO, + #[doc = "0x08 - Higher 32 bits for the free running counter"] + pub chi: CHI, + #[doc = "0x0c - Compare channel 0"] + pub c0: C0, + #[doc = "0x10 - Compare channel 1"] + pub c1: C1, + #[doc = "0x14 - Compare channel 2"] + pub c2: C2, + #[doc = "0x18 - Compare channel 3"] + pub c3: C3, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control / Status"] +pub mod cs; +#[doc = "CLO (r) register accessor: an alias for `Reg`"] +pub type CLO = crate::Reg; +#[doc = "Lower 32 bits for the free running counter"] +pub mod clo; +#[doc = "CHI (r) register accessor: an alias for `Reg`"] +pub type CHI = crate::Reg; +#[doc = "Higher 32 bits for the free running counter"] +pub mod chi; +#[doc = "C0 (rw) register accessor: an alias for `Reg`"] +pub type C0 = crate::Reg; +#[doc = "Compare channel 0"] +pub mod c0; +#[doc = "C1 (rw) register accessor: an alias for `Reg`"] +pub type C1 = crate::Reg; +#[doc = "Compare channel 1"] +pub mod c1; +#[doc = "C2 (rw) register accessor: an alias for `Reg`"] +pub type C2 = crate::Reg; +#[doc = "Compare channel 2"] +pub mod c2; +#[doc = "C3 (rw) register accessor: an alias for `Reg`"] +pub type C3 = crate::Reg; +#[doc = "Compare channel 3"] +pub mod c3; diff --git a/crates/bcm2835-lpa/src/systmr/c0.rs b/crates/bcm2835-lpa/src/systmr/c0.rs new file mode 100644 index 0000000..20b09d2 --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/c0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c0](index.html) module"] +pub struct C0_SPEC; +impl crate::RegisterSpec for C0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c0::R](R) reader structure"] +impl crate::Readable for C0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c0::W](W) writer structure"] +impl crate::Writable for C0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C0 to value 0"] +impl crate::Resettable for C0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr/c1.rs b/crates/bcm2835-lpa/src/systmr/c1.rs new file mode 100644 index 0000000..87cf5ed --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/c1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1](index.html) module"] +pub struct C1_SPEC; +impl crate::RegisterSpec for C1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c1::R](R) reader structure"] +impl crate::Readable for C1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c1::W](W) writer structure"] +impl crate::Writable for C1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C1 to value 0"] +impl crate::Resettable for C1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr/c2.rs b/crates/bcm2835-lpa/src/systmr/c2.rs new file mode 100644 index 0000000..8c9c84b --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/c2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c2](index.html) module"] +pub struct C2_SPEC; +impl crate::RegisterSpec for C2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c2::R](R) reader structure"] +impl crate::Readable for C2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c2::W](W) writer structure"] +impl crate::Writable for C2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C2 to value 0"] +impl crate::Resettable for C2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr/c3.rs b/crates/bcm2835-lpa/src/systmr/c3.rs new file mode 100644 index 0000000..0ac0aa2 --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/c3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c3](index.html) module"] +pub struct C3_SPEC; +impl crate::RegisterSpec for C3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c3::R](R) reader structure"] +impl crate::Readable for C3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c3::W](W) writer structure"] +impl crate::Writable for C3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C3 to value 0"] +impl crate::Resettable for C3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr/chi.rs b/crates/bcm2835-lpa/src/systmr/chi.rs new file mode 100644 index 0000000..9f162ef --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/chi.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CHI` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Higher 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chi](index.html) module"] +pub struct CHI_SPEC; +impl crate::RegisterSpec for CHI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chi::R](R) reader structure"] +impl crate::Readable for CHI_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHI to value 0"] +impl crate::Resettable for CHI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr/clo.rs b/crates/bcm2835-lpa/src/systmr/clo.rs new file mode 100644 index 0000000..0a4b01f --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/clo.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CLO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Lower 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clo](index.html) module"] +pub struct CLO_SPEC; +impl crate::RegisterSpec for CLO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clo::R](R) reader structure"] +impl crate::Readable for CLO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CLO to value 0"] +impl crate::Resettable for CLO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/systmr/cs.rs b/crates/bcm2835-lpa/src/systmr/cs.rs new file mode 100644 index 0000000..dcb8ec2 --- /dev/null +++ b/crates/bcm2835-lpa/src/systmr/cs.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0` reader - System timer match 0"] +pub type M0_R = crate::BitReader; +#[doc = "Field `M0` writer - System timer match 0"] +pub type M0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M1` reader - System timer match 1"] +pub type M1_R = crate::BitReader; +#[doc = "Field `M1` writer - System timer match 1"] +pub type M1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M2` reader - System timer match 2"] +pub type M2_R = crate::BitReader; +#[doc = "Field `M2` writer - System timer match 2"] +pub type M2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M3` reader - System timer match 3"] +pub type M3_R = crate::BitReader; +#[doc = "Field `M3` writer - System timer match 3"] +pub type M3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - System timer match 0"] + #[inline(always)] + pub fn m0(&self) -> M0_R { + M0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - System timer match 1"] + #[inline(always)] + pub fn m1(&self) -> M1_R { + M1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - System timer match 2"] + #[inline(always)] + pub fn m2(&self) -> M2_R { + M2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - System timer match 3"] + #[inline(always)] + pub fn m3(&self) -> M3_R { + M3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - System timer match 0"] + #[inline(always)] + #[must_use] + pub fn m0(&mut self) -> M0_W<0> { + M0_W::new(self) + } + #[doc = "Bit 1 - System timer match 1"] + #[inline(always)] + #[must_use] + pub fn m1(&mut self) -> M1_W<1> { + M1_W::new(self) + } + #[doc = "Bit 2 - System timer match 2"] + #[inline(always)] + #[must_use] + pub fn m2(&mut self) -> M2_W<2> { + M2_W::new(self) + } + #[doc = "Bit 3 - System timer match 3"] + #[inline(always)] + #[must_use] + pub fn m3(&mut self) -> M3_W<3> { + M3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0.rs b/crates/bcm2835-lpa/src/uart0.rs new file mode 100644 index 0000000..aade8a9 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Data Register"] + pub dr: DR, + _reserved_1_ecr: [u8; 0x04], + _reserved2: [u8; 0x10], + #[doc = "0x18 - Flag Register"] + pub fr: FR, + _reserved3: [u8; 0x08], + #[doc = "0x24 - Integer Baud Rate Register"] + pub ibrd: IBRD, + #[doc = "0x28 - Fractional Baud Rate Register"] + pub fbrd: FBRD, + #[doc = "0x2c - Line Control Register"] + pub lcr_h: LCR_H, + #[doc = "0x30 - Control Register"] + pub cr: CR, + #[doc = "0x34 - Interrupt FIFO Level Select Register"] + pub ifls: IFLS, + #[doc = "0x38 - Interrupt Mask set_Clear Register"] + pub imsc: IMSC, + #[doc = "0x3c - Raw Interrupt Status Register"] + pub ris: RIS, + #[doc = "0x40 - Masked Interrupt Status Register"] + pub mis: MIS, + #[doc = "0x44 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x48 - DMA Control Register"] + pub dmacr: DMACR, +} +impl RegisterBlock { + #[doc = "0x04 - Error Clear Register"] + #[inline(always)] + pub const fn ecr(&self) -> &ECR { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } + #[doc = "0x04 - Receive Status Register"] + #[inline(always)] + pub const fn rsr(&self) -> &RSR { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } +} +#[doc = "DR (rw) register accessor: an alias for `Reg`"] +pub type DR = crate::Reg; +#[doc = "Data Register"] +pub mod dr; +#[doc = "RSR (r) register accessor: an alias for `Reg`"] +pub type RSR = crate::Reg; +#[doc = "Receive Status Register"] +pub mod rsr; +#[doc = "ECR (w) register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Clear Register"] +pub mod ecr; +#[doc = "FR (rw) register accessor: an alias for `Reg`"] +pub type FR = crate::Reg; +#[doc = "Flag Register"] +pub mod fr; +#[doc = "IBRD (rw) register accessor: an alias for `Reg`"] +pub type IBRD = crate::Reg; +#[doc = "Integer Baud Rate Register"] +pub mod ibrd; +#[doc = "FBRD (rw) register accessor: an alias for `Reg`"] +pub type FBRD = crate::Reg; +#[doc = "Fractional Baud Rate Register"] +pub mod fbrd; +#[doc = "LCR_H (rw) register accessor: an alias for `Reg`"] +pub type LCR_H = crate::Reg; +#[doc = "Line Control Register"] +pub mod lcr_h; +#[doc = "CR (rw) register accessor: an alias for `Reg`"] +pub type CR = crate::Reg; +#[doc = "Control Register"] +pub mod cr; +#[doc = "IFLS (rw) register accessor: an alias for `Reg`"] +pub type IFLS = crate::Reg; +#[doc = "Interrupt FIFO Level Select Register"] +pub mod ifls; +#[doc = "IMSC (rw) register accessor: an alias for `Reg`"] +pub type IMSC = crate::Reg; +#[doc = "Interrupt Mask set_Clear Register"] +pub mod imsc; +#[doc = "RIS (r) register accessor: an alias for `Reg`"] +pub type RIS = crate::Reg; +#[doc = "Raw Interrupt Status Register"] +pub mod ris; +#[doc = "MIS (r) register accessor: an alias for `Reg`"] +pub type MIS = crate::Reg; +#[doc = "Masked Interrupt Status Register"] +pub mod mis; +#[doc = "ICR (w) register accessor: an alias for `Reg`"] +pub type ICR = crate::Reg; +#[doc = "Interrupt Clear Register"] +pub mod icr; +#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +pub type DMACR = crate::Reg; +#[doc = "DMA Control Register"] +pub mod dmacr; diff --git a/crates/bcm2835-lpa/src/uart0/cr.rs b/crates/bcm2835-lpa/src/uart0/cr.rs new file mode 100644 index 0000000..6c47a00 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/cr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `CR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UARTEN` reader - UARTEN"] +pub type UARTEN_R = crate::BitReader; +#[doc = "Field `UARTEN` writer - UARTEN"] +pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `SIREN` reader - SIREN"] +pub type SIREN_R = crate::BitReader; +#[doc = "Field `SIREN` writer - SIREN"] +pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `SIRLP` reader - SIRLP"] +pub type SIRLP_R = crate::BitReader; +#[doc = "Field `SIRLP` writer - SIRLP"] +pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `TXE` reader - TXE"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `TXE` writer - TXE"] +pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RXE` reader - RXE"] +pub type RXE_R = crate::BitReader; +#[doc = "Field `RXE` writer - RXE"] +pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `DTR` reader - DTR"] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - DTR"] +pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RTS` reader - RTS"] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - RTS"] +pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RTSEN` reader - RTSEN"] +pub type RTSEN_R = crate::BitReader; +#[doc = "Field `RTSEN` writer - RTSEN"] +pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `CTSEN` reader - CTSEN"] +pub type CTSEN_R = crate::BitReader; +#[doc = "Field `CTSEN` writer - CTSEN"] +pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UARTEN"] + #[inline(always)] + pub fn uarten(&self) -> UARTEN_R { + UARTEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SIREN"] + #[inline(always)] + pub fn siren(&self) -> SIREN_R { + SIREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SIRLP"] + #[inline(always)] + pub fn sirlp(&self) -> SIRLP_R { + SIRLP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - TXE"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RXE"] + #[inline(always)] + pub fn rxe(&self) -> RXE_R { + RXE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DTR"] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RTS"] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - RTSEN"] + #[inline(always)] + pub fn rtsen(&self) -> RTSEN_R { + RTSEN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CTSEN"] + #[inline(always)] + pub fn ctsen(&self) -> CTSEN_R { + CTSEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UARTEN"] + #[inline(always)] + #[must_use] + pub fn uarten(&mut self) -> UARTEN_W<0> { + UARTEN_W::new(self) + } + #[doc = "Bit 1 - SIREN"] + #[inline(always)] + #[must_use] + pub fn siren(&mut self) -> SIREN_W<1> { + SIREN_W::new(self) + } + #[doc = "Bit 2 - SIRLP"] + #[inline(always)] + #[must_use] + pub fn sirlp(&mut self) -> SIRLP_W<2> { + SIRLP_W::new(self) + } + #[doc = "Bit 8 - TXE"] + #[inline(always)] + #[must_use] + pub fn txe(&mut self) -> TXE_W<8> { + TXE_W::new(self) + } + #[doc = "Bit 9 - RXE"] + #[inline(always)] + #[must_use] + pub fn rxe(&mut self) -> RXE_W<9> { + RXE_W::new(self) + } + #[doc = "Bit 10 - DTR"] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W<10> { + DTR_W::new(self) + } + #[doc = "Bit 11 - RTS"] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W<11> { + RTS_W::new(self) + } + #[doc = "Bit 14 - RTSEN"] + #[inline(always)] + #[must_use] + pub fn rtsen(&mut self) -> RTSEN_W<14> { + RTSEN_W::new(self) + } + #[doc = "Bit 15 - CTSEN"] + #[inline(always)] + #[must_use] + pub fn ctsen(&mut self) -> CTSEN_W<15> { + CTSEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +pub struct CR_SPEC; +impl crate::RegisterSpec for CR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cr::R](R) reader structure"] +impl crate::Readable for CR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +impl crate::Writable for CR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CR to value 0"] +impl crate::Resettable for CR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/dmacr.rs b/crates/bcm2835-lpa/src/uart0/dmacr.rs new file mode 100644 index 0000000..8bd3632 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/dmacr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DMACR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMACR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXDMAE` reader - RXDMAE"] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `RXDMAE` writer - RXDMAE"] +pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +#[doc = "Field `TXDMAE` reader - TXDMAE"] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `TXDMAE` writer - TXDMAE"] +pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +#[doc = "Field `DMAONERR` reader - DMAONERR"] +pub type DMAONERR_R = crate::BitReader; +#[doc = "Field `DMAONERR` writer - DMAONERR"] +pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - RXDMAE"] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - TXDMAE"] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMAONERR"] + #[inline(always)] + pub fn dmaonerr(&self) -> DMAONERR_R { + DMAONERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RXDMAE"] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - TXDMAE"] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W<1> { + TXDMAE_W::new(self) + } + #[doc = "Bit 2 - DMAONERR"] + #[inline(always)] + #[must_use] + pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + DMAONERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"] +pub struct DMACR_SPEC; +impl crate::RegisterSpec for DMACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmacr::R](R) reader structure"] +impl crate::Readable for DMACR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +impl crate::Writable for DMACR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMACR to value 0"] +impl crate::Resettable for DMACR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/dr.rs b/crates/bcm2835-lpa/src/uart0/dr.rs new file mode 100644 index 0000000..236d30b --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/dr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - DATA"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - DATA"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>; +#[doc = "Field `FE` reader - FE"] +pub type FE_R = crate::BitReader; +#[doc = "Field `FE` writer - FE"] +pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `PE` reader - PE"] +pub type PE_R = crate::BitReader; +#[doc = "Field `PE` writer - PE"] +pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `BE` reader - BE"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - BE"] +pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `OE` reader - OE"] +pub type OE_R = crate::BitReader; +#[doc = "Field `OE` writer - OE"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:7 - DATA"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - FE"] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PE"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - BE"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - OE"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DATA"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Bit 8 - FE"] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W<8> { + FE_W::new(self) + } + #[doc = "Bit 9 - PE"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W<9> { + PE_W::new(self) + } + #[doc = "Bit 10 - BE"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W<10> { + BE_W::new(self) + } + #[doc = "Bit 11 - OE"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<11> { + OE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] +pub struct DR_SPEC; +impl crate::RegisterSpec for DR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dr::R](R) reader structure"] +impl crate::Readable for DR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] +impl crate::Writable for DR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DR to value 0"] +impl crate::Resettable for DR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/ecr.rs b/crates/bcm2835-lpa/src/uart0/ecr.rs new file mode 100644 index 0000000..f469e97 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/ecr.rs @@ -0,0 +1,76 @@ +#[doc = "Register `ECR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FE` writer - FE"] +pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `PE` writer - PE"] +pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `BE` writer - BE"] +pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `OE` writer - OE"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - FE"] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W<0> { + FE_W::new(self) + } + #[doc = "Bit 1 - PE"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W<1> { + PE_W::new(self) + } + #[doc = "Bit 2 - BE"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W<2> { + BE_W::new(self) + } + #[doc = "Bit 3 - OE"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<3> { + OE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"] +impl crate::Writable for ECR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/fbrd.rs b/crates/bcm2835-lpa/src/uart0/fbrd.rs new file mode 100644 index 0000000..14ae9a3 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/fbrd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FBRD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FBRD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDDIVFRAC` reader - BAUDDIVFRAC"] +pub type BAUDDIVFRAC_R = crate::FieldReader; +#[doc = "Field `BAUDDIVFRAC` writer - BAUDDIVFRAC"] +pub type BAUDDIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBRD_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - BAUDDIVFRAC"] + #[inline(always)] + pub fn bauddivfrac(&self) -> BAUDDIVFRAC_R { + BAUDDIVFRAC_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - BAUDDIVFRAC"] + #[inline(always)] + #[must_use] + pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W<0> { + BAUDDIVFRAC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbrd](index.html) module"] +pub struct FBRD_SPEC; +impl crate::RegisterSpec for FBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fbrd::R](R) reader structure"] +impl crate::Readable for FBRD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fbrd::W](W) writer structure"] +impl crate::Writable for FBRD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FBRD to value 0"] +impl crate::Resettable for FBRD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/fr.rs b/crates/bcm2835-lpa/src/uart0/fr.rs new file mode 100644 index 0000000..641becc --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/fr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `FR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - CTS"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `CTS` writer - CTS"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `DSR` reader - DSR"] +pub type DSR_R = crate::BitReader; +#[doc = "Field `DSR` writer - DSR"] +pub type DSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `DCD` reader - DCD"] +pub type DCD_R = crate::BitReader; +#[doc = "Field `DCD` writer - DCD"] +pub type DCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `BUSY` reader - BUSY"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `BUSY` writer - BUSY"] +pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RXFE` reader - RXFE"] +pub type RXFE_R = crate::BitReader; +#[doc = "Field `RXFE` writer - RXFE"] +pub type RXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `TXFF` reader - TXFF"] +pub type TXFF_R = crate::BitReader; +#[doc = "Field `TXFF` writer - TXFF"] +pub type TXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RXFF` reader - RXFF"] +pub type RXFF_R = crate::BitReader; +#[doc = "Field `RXFF` writer - RXFF"] +pub type RXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `TXFE` reader - TXFE"] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `TXFE` writer - TXFE"] +pub type TXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RI` reader - RI"] +pub type RI_R = crate::BitReader; +#[doc = "Field `RI` writer - RI"] +pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - CTS"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DSR"] + #[inline(always)] + pub fn dsr(&self) -> DSR_R { + DSR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCD"] + #[inline(always)] + pub fn dcd(&self) -> DCD_R { + DCD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BUSY"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXFE"] + #[inline(always)] + pub fn rxfe(&self) -> RXFE_R { + RXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXFF"] + #[inline(always)] + pub fn txff(&self) -> TXFF_R { + TXFF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RXFF"] + #[inline(always)] + pub fn rxff(&self) -> RXFF_R { + RXFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TXFE"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RI"] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CTS"] + #[inline(always)] + #[must_use] + pub fn cts(&mut self) -> CTS_W<0> { + CTS_W::new(self) + } + #[doc = "Bit 1 - DSR"] + #[inline(always)] + #[must_use] + pub fn dsr(&mut self) -> DSR_W<1> { + DSR_W::new(self) + } + #[doc = "Bit 2 - DCD"] + #[inline(always)] + #[must_use] + pub fn dcd(&mut self) -> DCD_W<2> { + DCD_W::new(self) + } + #[doc = "Bit 3 - BUSY"] + #[inline(always)] + #[must_use] + pub fn busy(&mut self) -> BUSY_W<3> { + BUSY_W::new(self) + } + #[doc = "Bit 4 - RXFE"] + #[inline(always)] + #[must_use] + pub fn rxfe(&mut self) -> RXFE_W<4> { + RXFE_W::new(self) + } + #[doc = "Bit 5 - TXFF"] + #[inline(always)] + #[must_use] + pub fn txff(&mut self) -> TXFF_W<5> { + TXFF_W::new(self) + } + #[doc = "Bit 6 - RXFF"] + #[inline(always)] + #[must_use] + pub fn rxff(&mut self) -> RXFF_W<6> { + RXFF_W::new(self) + } + #[doc = "Bit 7 - TXFE"] + #[inline(always)] + #[must_use] + pub fn txfe(&mut self) -> TXFE_W<7> { + TXFE_W::new(self) + } + #[doc = "Bit 8 - RI"] + #[inline(always)] + #[must_use] + pub fn ri(&mut self) -> RI_W<8> { + RI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +pub struct FR_SPEC; +impl crate::RegisterSpec for FR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fr::R](R) reader structure"] +impl crate::Readable for FR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] +impl crate::Writable for FR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FR to value 0"] +impl crate::Resettable for FR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/ibrd.rs b/crates/bcm2835-lpa/src/uart0/ibrd.rs new file mode 100644 index 0000000..65af80e --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/ibrd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IBRD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IBRD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDDIVINT` reader - BAUDDIVINT"] +pub type BAUDDIVINT_R = crate::FieldReader; +#[doc = "Field `BAUDDIVINT` writer - BAUDDIVINT"] +pub type BAUDDIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IBRD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - BAUDDIVINT"] + #[inline(always)] + pub fn bauddivint(&self) -> BAUDDIVINT_R { + BAUDDIVINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - BAUDDIVINT"] + #[inline(always)] + #[must_use] + pub fn bauddivint(&mut self) -> BAUDDIVINT_W<0> { + BAUDDIVINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Integer Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ibrd](index.html) module"] +pub struct IBRD_SPEC; +impl crate::RegisterSpec for IBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ibrd::R](R) reader structure"] +impl crate::Readable for IBRD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ibrd::W](W) writer structure"] +impl crate::Writable for IBRD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IBRD to value 0"] +impl crate::Resettable for IBRD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/icr.rs b/crates/bcm2835-lpa/src/uart0/icr.rs new file mode 100644 index 0000000..509869e --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/icr.rs @@ -0,0 +1,132 @@ +#[doc = "Register `ICR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIMIC` writer - RIMIC"] +pub type RIMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `CTSMIC` writer - CTSMIC"] +pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `DCDMIC` writer - DCDMIC"] +pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `DSRMIC` writer - DSRMIC"] +pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `RXIC` writer - RXIC"] +pub type RXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `TXIC` writer - TXIC"] +pub type TXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `RTIC` writer - RTIC"] +pub type RTIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `FEIC` writer - FEIC"] +pub type FEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `PEIC` writer - PEIC"] +pub type PEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `BEIC` writer - BEIC"] +pub type BEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `OEIC` writer - OEIC"] +pub type OEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - RIMIC"] + #[inline(always)] + #[must_use] + pub fn rimic(&mut self) -> RIMIC_W<0> { + RIMIC_W::new(self) + } + #[doc = "Bit 1 - CTSMIC"] + #[inline(always)] + #[must_use] + pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + CTSMIC_W::new(self) + } + #[doc = "Bit 2 - DCDMIC"] + #[inline(always)] + #[must_use] + pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + DCDMIC_W::new(self) + } + #[doc = "Bit 3 - DSRMIC"] + #[inline(always)] + #[must_use] + pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + DSRMIC_W::new(self) + } + #[doc = "Bit 4 - RXIC"] + #[inline(always)] + #[must_use] + pub fn rxic(&mut self) -> RXIC_W<4> { + RXIC_W::new(self) + } + #[doc = "Bit 5 - TXIC"] + #[inline(always)] + #[must_use] + pub fn txic(&mut self) -> TXIC_W<5> { + TXIC_W::new(self) + } + #[doc = "Bit 6 - RTIC"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W<6> { + RTIC_W::new(self) + } + #[doc = "Bit 7 - FEIC"] + #[inline(always)] + #[must_use] + pub fn feic(&mut self) -> FEIC_W<7> { + FEIC_W::new(self) + } + #[doc = "Bit 8 - PEIC"] + #[inline(always)] + #[must_use] + pub fn peic(&mut self) -> PEIC_W<8> { + PEIC_W::new(self) + } + #[doc = "Bit 9 - BEIC"] + #[inline(always)] + #[must_use] + pub fn beic(&mut self) -> BEIC_W<9> { + BEIC_W::new(self) + } + #[doc = "Bit 10 - OEIC"] + #[inline(always)] + #[must_use] + pub fn oeic(&mut self) -> OEIC_W<10> { + OEIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +pub struct ICR_SPEC; +impl crate::RegisterSpec for ICR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +impl crate::Writable for ICR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for ICR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/ifls.rs b/crates/bcm2835-lpa/src/uart0/ifls.rs new file mode 100644 index 0000000..0cfe8d5 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/ifls.rs @@ -0,0 +1,95 @@ +#[doc = "Register `IFLS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IFLS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXIFLSEL` reader - TXIFLSEL"] +pub type TXIFLSEL_R = crate::FieldReader; +#[doc = "Field `TXIFLSEL` writer - TXIFLSEL"] +pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +#[doc = "Field `RXIFLSEL` reader - RXIFLSEL"] +pub type RXIFLSEL_R = crate::FieldReader; +#[doc = "Field `RXIFLSEL` writer - RXIFLSEL"] +pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - TXIFLSEL"] + #[inline(always)] + pub fn txiflsel(&self) -> TXIFLSEL_R { + TXIFLSEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - RXIFLSEL"] + #[inline(always)] + pub fn rxiflsel(&self) -> RXIFLSEL_R { + RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - TXIFLSEL"] + #[inline(always)] + #[must_use] + pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + TXIFLSEL_W::new(self) + } + #[doc = "Bits 3:5 - RXIFLSEL"] + #[inline(always)] + #[must_use] + pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + RXIFLSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifls](index.html) module"] +pub struct IFLS_SPEC; +impl crate::RegisterSpec for IFLS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ifls::R](R) reader structure"] +impl crate::Readable for IFLS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ifls::W](W) writer structure"] +impl crate::Writable for IFLS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IFLS to value 0"] +impl crate::Resettable for IFLS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/imsc.rs b/crates/bcm2835-lpa/src/uart0/imsc.rs new file mode 100644 index 0000000..1b0fb46 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/imsc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `IMSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IMSC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIMIM` reader - RIMIM"] +pub type RIMIM_R = crate::BitReader; +#[doc = "Field `RIMIM` writer - RIMIM"] +pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `CTSMIM` reader - CTSMIM"] +pub type CTSMIM_R = crate::BitReader; +#[doc = "Field `CTSMIM` writer - CTSMIM"] +pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `DCDMIM` reader - DCDMIM"] +pub type DCDMIM_R = crate::BitReader; +#[doc = "Field `DCDMIM` writer - DCDMIM"] +pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `DSRMIM` reader - DSRMIM"] +pub type DSRMIM_R = crate::BitReader; +#[doc = "Field `DSRMIM` writer - DSRMIM"] +pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `RXIM` reader - RXIM"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `RXIM` writer - RXIM"] +pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `TXIM` reader - TXIM"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `TXIM` writer - TXIM"] +pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `RTIM` reader - RTIM"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `RTIM` writer - RTIM"] +pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `FEIM` reader - FEIM"] +pub type FEIM_R = crate::BitReader; +#[doc = "Field `FEIM` writer - FEIM"] +pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `PEIM` reader - PEIM"] +pub type PEIM_R = crate::BitReader; +#[doc = "Field `PEIM` writer - PEIM"] +pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `BEIM` reader - BEIM"] +pub type BEIM_R = crate::BitReader; +#[doc = "Field `BEIM` writer - BEIM"] +pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `OEIM` reader - OEIM"] +pub type OEIM_R = crate::BitReader; +#[doc = "Field `OEIM` writer - OEIM"] +pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - RIMIM"] + #[inline(always)] + pub fn rimim(&self) -> RIMIM_R { + RIMIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSMIM"] + #[inline(always)] + pub fn ctsmim(&self) -> CTSMIM_R { + CTSMIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDMIM"] + #[inline(always)] + pub fn dcdmim(&self) -> DCDMIM_R { + DCDMIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRMIM"] + #[inline(always)] + pub fn dsrmim(&self) -> DSRMIM_R { + DSRMIM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXIM"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXIM"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTIM"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FEIM"] + #[inline(always)] + pub fn feim(&self) -> FEIM_R { + FEIM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PEIM"] + #[inline(always)] + pub fn peim(&self) -> PEIM_R { + PEIM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BEIM"] + #[inline(always)] + pub fn beim(&self) -> BEIM_R { + BEIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OEIM"] + #[inline(always)] + pub fn oeim(&self) -> OEIM_R { + OEIM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RIMIM"] + #[inline(always)] + #[must_use] + pub fn rimim(&mut self) -> RIMIM_W<0> { + RIMIM_W::new(self) + } + #[doc = "Bit 1 - CTSMIM"] + #[inline(always)] + #[must_use] + pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + CTSMIM_W::new(self) + } + #[doc = "Bit 2 - DCDMIM"] + #[inline(always)] + #[must_use] + pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + DCDMIM_W::new(self) + } + #[doc = "Bit 3 - DSRMIM"] + #[inline(always)] + #[must_use] + pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + DSRMIM_W::new(self) + } + #[doc = "Bit 4 - RXIM"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W<4> { + RXIM_W::new(self) + } + #[doc = "Bit 5 - TXIM"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W<5> { + TXIM_W::new(self) + } + #[doc = "Bit 6 - RTIM"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W<6> { + RTIM_W::new(self) + } + #[doc = "Bit 7 - FEIM"] + #[inline(always)] + #[must_use] + pub fn feim(&mut self) -> FEIM_W<7> { + FEIM_W::new(self) + } + #[doc = "Bit 8 - PEIM"] + #[inline(always)] + #[must_use] + pub fn peim(&mut self) -> PEIM_W<8> { + PEIM_W::new(self) + } + #[doc = "Bit 9 - BEIM"] + #[inline(always)] + #[must_use] + pub fn beim(&mut self) -> BEIM_W<9> { + BEIM_W::new(self) + } + #[doc = "Bit 10 - OEIM"] + #[inline(always)] + #[must_use] + pub fn oeim(&mut self) -> OEIM_W<10> { + OEIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Mask set_Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"] +pub struct IMSC_SPEC; +impl crate::RegisterSpec for IMSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [imsc::R](R) reader structure"] +impl crate::Readable for IMSC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"] +impl crate::Writable for IMSC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMSC to value 0"] +impl crate::Resettable for IMSC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/lcr_h.rs b/crates/bcm2835-lpa/src/uart0/lcr_h.rs new file mode 100644 index 0000000..6e02317 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/lcr_h.rs @@ -0,0 +1,170 @@ +#[doc = "Register `LCR_H` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LCR_H` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BRK` reader - BRK"] +pub type BRK_R = crate::BitReader; +#[doc = "Field `BRK` writer - BRK"] +pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `PEN` reader - PEN"] +pub type PEN_R = crate::BitReader; +#[doc = "Field `PEN` writer - PEN"] +pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `EPS` reader - EPS"] +pub type EPS_R = crate::BitReader; +#[doc = "Field `EPS` writer - EPS"] +pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `STP2` reader - STP2"] +pub type STP2_R = crate::BitReader; +#[doc = "Field `STP2` writer - STP2"] +pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `FEN` reader - FEN"] +pub type FEN_R = crate::BitReader; +#[doc = "Field `FEN` writer - FEN"] +pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `WLEN` reader - WLEN"] +pub type WLEN_R = crate::FieldReader; +#[doc = "Field `WLEN` writer - WLEN"] +pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_H_SPEC, u8, u8, 2, O>; +#[doc = "Field `SPS` reader - SPS"] +pub type SPS_R = crate::BitReader; +#[doc = "Field `SPS` writer - SPS"] +pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - BRK"] + #[inline(always)] + pub fn brk(&self) -> BRK_R { + BRK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PEN"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - EPS"] + #[inline(always)] + pub fn eps(&self) -> EPS_R { + EPS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STP2"] + #[inline(always)] + pub fn stp2(&self) -> STP2_R { + STP2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - FEN"] + #[inline(always)] + pub fn fen(&self) -> FEN_R { + FEN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - WLEN"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - SPS"] + #[inline(always)] + pub fn sps(&self) -> SPS_R { + SPS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - BRK"] + #[inline(always)] + #[must_use] + pub fn brk(&mut self) -> BRK_W<0> { + BRK_W::new(self) + } + #[doc = "Bit 1 - PEN"] + #[inline(always)] + #[must_use] + pub fn pen(&mut self) -> PEN_W<1> { + PEN_W::new(self) + } + #[doc = "Bit 2 - EPS"] + #[inline(always)] + #[must_use] + pub fn eps(&mut self) -> EPS_W<2> { + EPS_W::new(self) + } + #[doc = "Bit 3 - STP2"] + #[inline(always)] + #[must_use] + pub fn stp2(&mut self) -> STP2_W<3> { + STP2_W::new(self) + } + #[doc = "Bit 4 - FEN"] + #[inline(always)] + #[must_use] + pub fn fen(&mut self) -> FEN_W<4> { + FEN_W::new(self) + } + #[doc = "Bits 5:6 - WLEN"] + #[inline(always)] + #[must_use] + pub fn wlen(&mut self) -> WLEN_W<5> { + WLEN_W::new(self) + } + #[doc = "Bit 7 - SPS"] + #[inline(always)] + #[must_use] + pub fn sps(&mut self) -> SPS_W<7> { + SPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_h](index.html) module"] +pub struct LCR_H_SPEC; +impl crate::RegisterSpec for LCR_H_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lcr_h::R](R) reader structure"] +impl crate::Readable for LCR_H_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lcr_h::W](W) writer structure"] +impl crate::Writable for LCR_H_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCR_H to value 0"] +impl crate::Resettable for LCR_H_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/mis.rs b/crates/bcm2835-lpa/src/uart0/mis.rs new file mode 100644 index 0000000..ce802e5 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/mis.rs @@ -0,0 +1,107 @@ +#[doc = "Register `MIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RIMMIS` reader - RIMMIS"] +pub type RIMMIS_R = crate::BitReader; +#[doc = "Field `CTSMMIS` reader - CTSMMIS"] +pub type CTSMMIS_R = crate::BitReader; +#[doc = "Field `DCDMMIS` reader - DCDMMIS"] +pub type DCDMMIS_R = crate::BitReader; +#[doc = "Field `DSRMMIS` reader - DSRMMIS"] +pub type DSRMMIS_R = crate::BitReader; +#[doc = "Field `RXMIS` reader - RXMIS"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `TXMIS` reader - TXMIS"] +pub type TXMIS_R = crate::BitReader; +#[doc = "Field `RTMIS` reader - RTMIS"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `FEMIS` reader - FEMIS"] +pub type FEMIS_R = crate::BitReader; +#[doc = "Field `PEMIS` reader - PEMIS"] +pub type PEMIS_R = crate::BitReader; +#[doc = "Field `BEMIS` reader - BEMIS"] +pub type BEMIS_R = crate::BitReader; +#[doc = "Field `OEMIS` reader - OEMIS"] +pub type OEMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RIMMIS"] + #[inline(always)] + pub fn rimmis(&self) -> RIMMIS_R { + RIMMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSMMIS"] + #[inline(always)] + pub fn ctsmmis(&self) -> CTSMMIS_R { + CTSMMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDMMIS"] + #[inline(always)] + pub fn dcdmmis(&self) -> DCDMMIS_R { + DCDMMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRMMIS"] + #[inline(always)] + pub fn dsrmmis(&self) -> DSRMMIS_R { + DSRMMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXMIS"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXMIS"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTMIS"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FEMIS"] + #[inline(always)] + pub fn femis(&self) -> FEMIS_R { + FEMIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PEMIS"] + #[inline(always)] + pub fn pemis(&self) -> PEMIS_R { + PEMIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BEMIS"] + #[inline(always)] + pub fn bemis(&self) -> BEMIS_R { + BEMIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OEMIS"] + #[inline(always)] + pub fn oemis(&self) -> OEMIS_R { + OEMIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Masked Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"] +pub struct MIS_SPEC; +impl crate::RegisterSpec for MIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mis::R](R) reader structure"] +impl crate::Readable for MIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MIS to value 0"] +impl crate::Resettable for MIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/ris.rs b/crates/bcm2835-lpa/src/uart0/ris.rs new file mode 100644 index 0000000..0ab6b9d --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/ris.rs @@ -0,0 +1,107 @@ +#[doc = "Register `RIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RIRMIS` reader - RIRMIS"] +pub type RIRMIS_R = crate::BitReader; +#[doc = "Field `CTSRMIS` reader - CTSRMIS"] +pub type CTSRMIS_R = crate::BitReader; +#[doc = "Field `DCDRMIS` reader - DCDRMIS"] +pub type DCDRMIS_R = crate::BitReader; +#[doc = "Field `DSRRMIS` reader - DSRRMIS"] +pub type DSRRMIS_R = crate::BitReader; +#[doc = "Field `RXRIS` reader - RXRIS"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `TXRIS` reader - TXRIS"] +pub type TXRIS_R = crate::BitReader; +#[doc = "Field `RTRIS` reader - RTRIS"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `FERIS` reader - FERIS"] +pub type FERIS_R = crate::BitReader; +#[doc = "Field `PERIS` reader - PERIS"] +pub type PERIS_R = crate::BitReader; +#[doc = "Field `BERIS` reader - BERIS"] +pub type BERIS_R = crate::BitReader; +#[doc = "Field `OERIS` reader - OERIS"] +pub type OERIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RIRMIS"] + #[inline(always)] + pub fn rirmis(&self) -> RIRMIS_R { + RIRMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSRMIS"] + #[inline(always)] + pub fn ctsrmis(&self) -> CTSRMIS_R { + CTSRMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDRMIS"] + #[inline(always)] + pub fn dcdrmis(&self) -> DCDRMIS_R { + DCDRMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRRMIS"] + #[inline(always)] + pub fn dsrrmis(&self) -> DSRRMIS_R { + DSRRMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXRIS"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXRIS"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTRIS"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FERIS"] + #[inline(always)] + pub fn feris(&self) -> FERIS_R { + FERIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PERIS"] + #[inline(always)] + pub fn peris(&self) -> PERIS_R { + PERIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BERIS"] + #[inline(always)] + pub fn beris(&self) -> BERIS_R { + BERIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OERIS"] + #[inline(always)] + pub fn oeris(&self) -> OERIS_R { + OERIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](index.html) module"] +pub struct RIS_SPEC; +impl crate::RegisterSpec for RIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ris::R](R) reader structure"] +impl crate::Readable for RIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RIS to value 0"] +impl crate::Resettable for RIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart0/rsr.rs b/crates/bcm2835-lpa/src/uart0/rsr.rs new file mode 100644 index 0000000..90a9e0d --- /dev/null +++ b/crates/bcm2835-lpa/src/uart0/rsr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `RSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FE` reader - FE"] +pub type FE_R = crate::BitReader; +#[doc = "Field `PE` reader - PE"] +pub type PE_R = crate::BitReader; +#[doc = "Field `BE` reader - BE"] +pub type BE_R = crate::BitReader; +#[doc = "Field `OE` reader - OE"] +pub type OE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - FE"] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PE"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BE"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - OE"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +pub struct RSR_SPEC; +impl crate::RegisterSpec for RSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rsr::R](R) reader structure"] +impl crate::Readable for RSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RSR to value 0"] +impl crate::Resettable for RSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1.rs b/crates/bcm2835-lpa/src/uart1.rs new file mode 100644 index 0000000..a87a1e5 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_io: [u8; 0x04], + _reserved_1_ier: [u8; 0x04], + #[doc = "0x08 - Interrupt Identify"] + pub iir: IIR, + #[doc = "0x0c - Line control"] + pub lcr: LCR, + #[doc = "0x10 - Modem Control"] + pub mcr: MCR, + #[doc = "0x14 - Line Status"] + pub lsr: LSR, + #[doc = "0x18 - Modem Status"] + pub msr: MSR, + #[doc = "0x1c - Scratch"] + pub scratch: SCRATCH, + _reserved8: [u8; 0x03], + #[doc = "0x20 - Control"] + pub cntl: CNTL, + #[doc = "0x24 - Status"] + pub stat: STAT, + #[doc = "0x28 - Baudrate"] + pub baud: BAUD, +} +impl RegisterBlock { + #[doc = "0x00 - Lower bits of baudrate when DLAB is set"] + #[inline(always)] + pub const fn baudl(&self) -> &BAUDL { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00 - I/O Data"] + #[inline(always)] + pub const fn io(&self) -> &IO { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x04 - High bits of baudrate when DLAB is set"] + #[inline(always)] + pub const fn baudh(&self) -> &BAUDH { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } + #[doc = "0x04 - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &IER { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } +} +#[doc = "IO (rw) register accessor: an alias for `Reg`"] +pub type IO = crate::Reg; +#[doc = "I/O Data"] +pub mod io; +#[doc = "BAUDL (rw) register accessor: an alias for `Reg`"] +pub type BAUDL = crate::Reg; +#[doc = "Lower bits of baudrate when DLAB is set"] +pub mod baudl; +#[doc = "IER (rw) register accessor: an alias for `Reg`"] +pub type IER = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "BAUDH (rw) register accessor: an alias for `Reg`"] +pub type BAUDH = crate::Reg; +#[doc = "High bits of baudrate when DLAB is set"] +pub mod baudh; +#[doc = "IIR (rw) register accessor: an alias for `Reg`"] +pub type IIR = crate::Reg; +#[doc = "Interrupt Identify"] +pub mod iir; +#[doc = "LCR (rw) register accessor: an alias for `Reg`"] +pub type LCR = crate::Reg; +#[doc = "Line control"] +pub mod lcr; +#[doc = "MCR (rw) register accessor: an alias for `Reg`"] +pub type MCR = crate::Reg; +#[doc = "Modem Control"] +pub mod mcr; +#[doc = "LSR (rw) register accessor: an alias for `Reg`"] +pub type LSR = crate::Reg; +#[doc = "Line Status"] +pub mod lsr; +#[doc = "MSR (rw) register accessor: an alias for `Reg`"] +pub type MSR = crate::Reg; +#[doc = "Modem Status"] +pub mod msr; +#[doc = "SCRATCH (rw) register accessor: an alias for `Reg`"] +pub type SCRATCH = crate::Reg; +#[doc = "Scratch"] +pub mod scratch; +#[doc = "CNTL (rw) register accessor: an alias for `Reg`"] +pub type CNTL = crate::Reg; +#[doc = "Control"] +pub mod cntl; +#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "Baudrate"] +pub mod baud; diff --git a/crates/bcm2835-lpa/src/uart1/baud.rs b/crates/bcm2835-lpa/src/uart1/baud.rs new file mode 100644 index 0000000..088c774 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/baud.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Baudrate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/baudh.rs b/crates/bcm2835-lpa/src/uart1/baudh.rs new file mode 100644 index 0000000..8c30695 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/baudh.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUDH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "High bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudh](index.html) module"] +pub struct BAUDH_SPEC; +impl crate::RegisterSpec for BAUDH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baudh::R](R) reader structure"] +impl crate::Readable for BAUDH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudh::W](W) writer structure"] +impl crate::Writable for BAUDH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUDH to value 0"] +impl crate::Resettable for BAUDH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/baudl.rs b/crates/bcm2835-lpa/src/uart1/baudl.rs new file mode 100644 index 0000000..ca7c9f0 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/baudl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUDL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lower bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudl](index.html) module"] +pub struct BAUDL_SPEC; +impl crate::RegisterSpec for BAUDL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baudl::R](R) reader structure"] +impl crate::Readable for BAUDL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudl::W](W) writer structure"] +impl crate::Writable for BAUDL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUDL to value 0"] +impl crate::Resettable for BAUDL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/cntl.rs b/crates/bcm2835-lpa/src/uart1/cntl.rs new file mode 100644 index 0000000..4125093 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/cntl.rs @@ -0,0 +1,291 @@ +#[doc = "Register `CNTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RX_ENABLE` reader - Enable receive"] +pub type RX_ENABLE_R = crate::BitReader; +#[doc = "Field `RX_ENABLE` writer - Enable receive"] +pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `TX_ENABLE` reader - Enable transmit"] +pub type TX_ENABLE_R = crate::BitReader; +#[doc = "Field `TX_ENABLE` writer - Enable transmit"] +pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `RTS_ENABLE` reader - Enable auto receive flow control with RTS"] +pub type RTS_ENABLE_R = crate::BitReader; +#[doc = "Field `RTS_ENABLE` writer - Enable auto receive flow control with RTS"] +pub type RTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `CTS_ENABLE` reader - Enable auto transmit flow control with CTS"] +pub type CTS_ENABLE_R = crate::BitReader; +#[doc = "Field `CTS_ENABLE` writer - Enable auto transmit flow control with CTS"] +pub type CTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `RTS_FIFO_LEVEL` reader - FIFO level to de-assert RTS"] +pub type RTS_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "FIFO level to de-assert RTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FIFO_LEVEL_A { + #[doc = "0: 3 empty spaces"] + _3EMPTY = 0, + #[doc = "1: 2 empty spaces"] + _2EMPTY = 1, + #[doc = "2: 1 empty spaces"] + _1EMPTY = 2, + #[doc = "3: 4 empty spaces"] + _4EMPTY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FIFO_LEVEL_A) -> Self { + variant as _ + } +} +impl RTS_FIFO_LEVEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FIFO_LEVEL_A { + match self.bits { + 0 => FIFO_LEVEL_A::_3EMPTY, + 1 => FIFO_LEVEL_A::_2EMPTY, + 2 => FIFO_LEVEL_A::_1EMPTY, + 3 => FIFO_LEVEL_A::_4EMPTY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_3EMPTY`"] + #[inline(always)] + pub fn is_3empty(&self) -> bool { + *self == FIFO_LEVEL_A::_3EMPTY + } + #[doc = "Checks if the value of the field is `_2EMPTY`"] + #[inline(always)] + pub fn is_2empty(&self) -> bool { + *self == FIFO_LEVEL_A::_2EMPTY + } + #[doc = "Checks if the value of the field is `_1EMPTY`"] + #[inline(always)] + pub fn is_1empty(&self) -> bool { + *self == FIFO_LEVEL_A::_1EMPTY + } + #[doc = "Checks if the value of the field is `_4EMPTY`"] + #[inline(always)] + pub fn is_4empty(&self) -> bool { + *self == FIFO_LEVEL_A::_4EMPTY + } +} +#[doc = "Field `RTS_FIFO_LEVEL` writer - FIFO level to de-assert RTS"] +pub type RTS_FIFO_LEVEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CNTL_SPEC, u8, FIFO_LEVEL_A, 2, O>; +impl<'a, const O: u8> RTS_FIFO_LEVEL_W<'a, O> { + #[doc = "3 empty spaces"] + #[inline(always)] + pub fn _3empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_3EMPTY) + } + #[doc = "2 empty spaces"] + #[inline(always)] + pub fn _2empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_2EMPTY) + } + #[doc = "1 empty spaces"] + #[inline(always)] + pub fn _1empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_1EMPTY) + } + #[doc = "4 empty spaces"] + #[inline(always)] + pub fn _4empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_4EMPTY) + } +} +#[doc = "Field `RTS_ASSERT` reader - RTS assert level"] +pub use CTS_ASSERT_R as RTS_ASSERT_R; +#[doc = "Field `RTS_ASSERT` writer - RTS assert level"] +pub use CTS_ASSERT_W as RTS_ASSERT_W; +#[doc = "Field `CTS_ASSERT` reader - CTS assert level"] +pub type CTS_ASSERT_R = crate::BitReader; +#[doc = "CTS assert level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ASSERT_LEVEL_A { + #[doc = "0: Assert high"] + HIGH = 0, + #[doc = "1: Assert low"] + LOW = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ASSERT_LEVEL_A) -> Self { + variant as u8 != 0 + } +} +impl CTS_ASSERT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ASSERT_LEVEL_A { + match self.bits { + false => ASSERT_LEVEL_A::HIGH, + true => ASSERT_LEVEL_A::LOW, + } + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == ASSERT_LEVEL_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == ASSERT_LEVEL_A::LOW + } +} +#[doc = "Field `CTS_ASSERT` writer - CTS assert level"] +pub type CTS_ASSERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, ASSERT_LEVEL_A, O>; +impl<'a, const O: u8> CTS_ASSERT_W<'a, O> { + #[doc = "Assert high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(ASSERT_LEVEL_A::HIGH) + } + #[doc = "Assert low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(ASSERT_LEVEL_A::LOW) + } +} +impl R { + #[doc = "Bit 0 - Enable receive"] + #[inline(always)] + pub fn rx_enable(&self) -> RX_ENABLE_R { + RX_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable transmit"] + #[inline(always)] + pub fn tx_enable(&self) -> TX_ENABLE_R { + TX_ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable auto receive flow control with RTS"] + #[inline(always)] + pub fn rts_enable(&self) -> RTS_ENABLE_R { + RTS_ENABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] + #[inline(always)] + pub fn cts_enable(&self) -> CTS_ENABLE_R { + CTS_ENABLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] + #[inline(always)] + pub fn rts_fifo_level(&self) -> RTS_FIFO_LEVEL_R { + RTS_FIFO_LEVEL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - RTS assert level"] + #[inline(always)] + pub fn rts_assert(&self) -> RTS_ASSERT_R { + RTS_ASSERT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS assert level"] + #[inline(always)] + pub fn cts_assert(&self) -> CTS_ASSERT_R { + CTS_ASSERT_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable receive"] + #[inline(always)] + #[must_use] + pub fn rx_enable(&mut self) -> RX_ENABLE_W<0> { + RX_ENABLE_W::new(self) + } + #[doc = "Bit 1 - Enable transmit"] + #[inline(always)] + #[must_use] + pub fn tx_enable(&mut self) -> TX_ENABLE_W<1> { + TX_ENABLE_W::new(self) + } + #[doc = "Bit 2 - Enable auto receive flow control with RTS"] + #[inline(always)] + #[must_use] + pub fn rts_enable(&mut self) -> RTS_ENABLE_W<2> { + RTS_ENABLE_W::new(self) + } + #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] + #[inline(always)] + #[must_use] + pub fn cts_enable(&mut self) -> CTS_ENABLE_W<3> { + CTS_ENABLE_W::new(self) + } + #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] + #[inline(always)] + #[must_use] + pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W<4> { + RTS_FIFO_LEVEL_W::new(self) + } + #[doc = "Bit 6 - RTS assert level"] + #[inline(always)] + #[must_use] + pub fn rts_assert(&mut self) -> RTS_ASSERT_W<6> { + RTS_ASSERT_W::new(self) + } + #[doc = "Bit 7 - CTS assert level"] + #[inline(always)] + #[must_use] + pub fn cts_assert(&mut self) -> CTS_ASSERT_W<7> { + CTS_ASSERT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] +pub struct CNTL_SPEC; +impl crate::RegisterSpec for CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl::R](R) reader structure"] +impl crate::Readable for CNTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] +impl crate::Writable for CNTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL to value 0"] +impl crate::Resettable for CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/ier.rs b/crates/bcm2835-lpa/src/uart1/ier.rs new file mode 100644 index 0000000..450afd5 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/ier.rs @@ -0,0 +1,95 @@ +#[doc = "Register `IER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO is empty"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Transmit FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<1> { + TX_READY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +pub struct IER_SPEC; +impl crate::RegisterSpec for IER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ier::R](R) reader structure"] +impl crate::Readable for IER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +impl crate::Writable for IER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/iir.rs b/crates/bcm2835-lpa/src/uart1/iir.rs new file mode 100644 index 0000000..6f66eac --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/iir.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `nPENDING` reader - No pending interrupt"] +pub type N_PENDING_R = crate::BitReader; +#[doc = "Field `nPENDING` writer - No pending interrupt"] +pub type N_PENDING_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - No pending interrupt"] + #[inline(always)] + pub fn n_pending(&self) -> N_PENDING_R { + N_PENDING_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO is empty"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - No pending interrupt"] + #[inline(always)] + #[must_use] + pub fn n_pending(&mut self) -> N_PENDING_W<0> { + N_PENDING_W::new(self) + } + #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<1> { + DATA_READY_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<2> { + TX_READY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Identify\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iir](index.html) module"] +pub struct IIR_SPEC; +impl crate::RegisterSpec for IIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [iir::R](R) reader structure"] +impl crate::Readable for IIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [iir::W](W) writer structure"] +impl crate::Writable for IIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IIR to value 0xb001"] +impl crate::Resettable for IIR_SPEC { + const RESET_VALUE: Self::Ux = 0xb001; +} diff --git a/crates/bcm2835-lpa/src/uart1/io.rs b/crates/bcm2835-lpa/src/uart1/io.rs new file mode 100644 index 0000000..84cd075 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/io.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - FIFO access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - FIFO access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I/O Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +pub struct IO_SPEC; +impl crate::RegisterSpec for IO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [io::R](R) reader structure"] +impl crate::Readable for IO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +impl crate::Writable for IO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IO to value 0"] +impl crate::Resettable for IO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/lcr.rs b/crates/bcm2835-lpa/src/uart1/lcr.rs new file mode 100644 index 0000000..16b3c2b --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/lcr.rs @@ -0,0 +1,158 @@ +#[doc = "Register `LCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_SIZE` reader - UART word size"] +pub type DATA_SIZE_R = crate::FieldReader; +#[doc = "UART word size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: 7 bit"] + _7BIT = 0, + #[doc = "3: 8 bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::_7BIT), + 3 => Some(MODE_A::_8BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_7BIT`"] + #[inline(always)] + pub fn is_7bit(&self) -> bool { + *self == MODE_A::_7BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == MODE_A::_8BIT + } +} +#[doc = "Field `DATA_SIZE` writer - UART word size"] +pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_SPEC, u8, MODE_A, 2, O>; +impl<'a, const O: u8> DATA_SIZE_W<'a, O> { + #[doc = "7 bit"] + #[inline(always)] + pub fn _7bit(self) -> &'a mut W { + self.variant(MODE_A::_7BIT) + } + #[doc = "8 bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(MODE_A::_8BIT) + } +} +#[doc = "Field `BREAK` reader - Pull TX low continuously to send break"] +pub type BREAK_R = crate::BitReader; +#[doc = "Field `BREAK` writer - Pull TX low continuously to send break"] +pub type BREAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +#[doc = "Field `DLAB` reader - First two registers are baudrate"] +pub type DLAB_R = crate::BitReader; +#[doc = "Field `DLAB` writer - First two registers are baudrate"] +pub type DLAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - UART word size"] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 6 - Pull TX low continuously to send break"] + #[inline(always)] + pub fn break_(&self) -> BREAK_R { + BREAK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - First two registers are baudrate"] + #[inline(always)] + pub fn dlab(&self) -> DLAB_R { + DLAB_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - UART word size"] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W<0> { + DATA_SIZE_W::new(self) + } + #[doc = "Bit 6 - Pull TX low continuously to send break"] + #[inline(always)] + #[must_use] + pub fn break_(&mut self) -> BREAK_W<6> { + BREAK_W::new(self) + } + #[doc = "Bit 7 - First two registers are baudrate"] + #[inline(always)] + #[must_use] + pub fn dlab(&mut self) -> DLAB_W<7> { + DLAB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](index.html) module"] +pub struct LCR_SPEC; +impl crate::RegisterSpec for LCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lcr::R](R) reader structure"] +impl crate::Readable for LCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lcr::W](W) writer structure"] +impl crate::Writable for LCR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCR to value 0"] +impl crate::Resettable for LCR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/lsr.rs b/crates/bcm2835-lpa/src/uart1/lsr.rs new file mode 100644 index 0000000..ba34ba7 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/lsr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `LSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least one byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least one byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] +pub type RX_OVERRUN_R = crate::BitReader; +#[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] +pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - Transmit FIFO has room for at least one byte"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - Transmit FIFO has room for at least one byte"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `TX_IDLE` reader - Transmit FIFO empty and all bits shifted out"] +pub type TX_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IDLE` writer - Transmit FIFO empty and all bits shifted out"] +pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least one byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive FIFO overrun"] + #[inline(always)] + pub fn rx_overrun(&self) -> RX_OVERRUN_R { + RX_OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least one byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Receive FIFO overrun"] + #[inline(always)] + #[must_use] + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<1> { + RX_OVERRUN_W::new(self) + } + #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<5> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] + #[inline(always)] + #[must_use] + pub fn tx_idle(&mut self) -> TX_IDLE_W<6> { + TX_IDLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +pub struct LSR_SPEC; +impl crate::RegisterSpec for LSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lsr::R](R) reader structure"] +impl crate::Readable for LSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +impl crate::Writable for LSR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LSR to value 0"] +impl crate::Resettable for LSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/mcr.rs b/crates/bcm2835-lpa/src/uart1/mcr.rs new file mode 100644 index 0000000..89de0a8 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/mcr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RTS` reader - RTS is low"] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - RTS is low"] +pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - RTS is low"] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - RTS is low"] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W<1> { + RTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Modem Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"] +pub struct MCR_SPEC; +impl crate::RegisterSpec for MCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcr::R](R) reader structure"] +impl crate::Readable for MCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"] +impl crate::Writable for MCR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for MCR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/msr.rs b/crates/bcm2835-lpa/src/uart1/msr.rs new file mode 100644 index 0000000..3960539 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/msr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - CTS is low"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `CTS` writer - CTS is low"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSR_SPEC, bool, O>; +impl R { + #[doc = "Bit 4 - CTS is low"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - CTS is low"] + #[inline(always)] + #[must_use] + pub fn cts(&mut self) -> CTS_W<4> { + CTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Modem Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](index.html) module"] +pub struct MSR_SPEC; +impl crate::RegisterSpec for MSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [msr::R](R) reader structure"] +impl crate::Readable for MSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [msr::W](W) writer structure"] +impl crate::Writable for MSR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MSR to value 0"] +impl crate::Resettable for MSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/scratch.rs b/crates/bcm2835-lpa/src/uart1/scratch.rs new file mode 100644 index 0000000..c85f068 --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/scratch.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCRATCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCRATCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scratch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch](index.html) module"] +pub struct SCRATCH_SPEC; +impl crate::RegisterSpec for SCRATCH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scratch::R](R) reader structure"] +impl crate::Readable for SCRATCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scratch::W](W) writer structure"] +impl crate::Writable for SCRATCH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCRATCH to value 0"] +impl crate::Resettable for SCRATCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/uart1/stat.rs b/crates/bcm2835-lpa/src/uart1/stat.rs new file mode 100644 index 0000000..114015e --- /dev/null +++ b/crates/bcm2835-lpa/src/uart1/stat.rs @@ -0,0 +1,245 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least one symbol"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least one symbol"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO has space for at least one symbol"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO has space for at least one symbol"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_IDLE` reader - Receiver is idle"] +pub type RX_IDLE_R = crate::BitReader; +#[doc = "Field `RX_IDLE` writer - Receiver is idle"] +pub type RX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_IDLE` reader - Transmitter is idle"] +pub type TX_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IDLE` writer - Transmitter is idle"] +pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] +pub type RX_OVERRUN_R = crate::BitReader; +#[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] +pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_FULL` reader - Transmit FIFO is full"] +pub type TX_FULL_R = crate::BitReader; +#[doc = "Field `TX_FULL` writer - Transmit FIFO is full"] +pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RTS_STATUS` reader - RTS state"] +pub type RTS_STATUS_R = crate::BitReader; +#[doc = "Field `RTS_STATUS` writer - RTS state"] +pub type RTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `CTS_STATUS` reader - CTS state"] +pub type CTS_STATUS_R = crate::BitReader; +#[doc = "Field `CTS_STATUS` writer - CTS state"] +pub type CTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - Transmit FIFO is completely empty"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - Transmit FIFO is completely empty"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_DONE` reader - Transmit FIFO is empty and transmitter is idle"] +pub type TX_DONE_R = crate::BitReader; +#[doc = "Field `TX_DONE` writer - Transmit FIFO is empty and transmitter is idle"] +pub type TX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_FIFO_LEVEL` reader - How many entries are filled in the RX FIFO"] +pub type RX_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "Field `RX_FIFO_LEVEL` writer - How many entries are filled in the RX FIFO"] +pub type RX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_FIFO_LEVEL` reader - How many entries are filled in the TX FIFO"] +pub type TX_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "Field `TX_FIFO_LEVEL` writer - How many entries are filled in the TX FIFO"] +pub type TX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least one symbol"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receiver is idle"] + #[inline(always)] + pub fn rx_idle(&self) -> RX_IDLE_R { + RX_IDLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmitter is idle"] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO overrun"] + #[inline(always)] + pub fn rx_overrun(&self) -> RX_OVERRUN_R { + RX_OVERRUN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO is full"] + #[inline(always)] + pub fn tx_full(&self) -> TX_FULL_R { + TX_FULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTS state"] + #[inline(always)] + pub fn rts_status(&self) -> RTS_STATUS_R { + RTS_STATUS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS state"] + #[inline(always)] + pub fn cts_status(&self) -> CTS_STATUS_R { + CTS_STATUS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit FIFO is completely empty"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] + #[inline(always)] + pub fn tx_done(&self) -> TX_DONE_R { + TX_DONE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] + #[inline(always)] + pub fn rx_fifo_level(&self) -> RX_FIFO_LEVEL_R { + RX_FIFO_LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] + #[inline(always)] + pub fn tx_fifo_level(&self) -> TX_FIFO_LEVEL_R { + TX_FIFO_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least one symbol"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<1> { + TX_READY_W::new(self) + } + #[doc = "Bit 2 - Receiver is idle"] + #[inline(always)] + #[must_use] + pub fn rx_idle(&mut self) -> RX_IDLE_W<2> { + RX_IDLE_W::new(self) + } + #[doc = "Bit 3 - Transmitter is idle"] + #[inline(always)] + #[must_use] + pub fn tx_idle(&mut self) -> TX_IDLE_W<3> { + TX_IDLE_W::new(self) + } + #[doc = "Bit 4 - Receive FIFO overrun"] + #[inline(always)] + #[must_use] + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<4> { + RX_OVERRUN_W::new(self) + } + #[doc = "Bit 5 - Transmit FIFO is full"] + #[inline(always)] + #[must_use] + pub fn tx_full(&mut self) -> TX_FULL_W<5> { + TX_FULL_W::new(self) + } + #[doc = "Bit 6 - RTS state"] + #[inline(always)] + #[must_use] + pub fn rts_status(&mut self) -> RTS_STATUS_W<6> { + RTS_STATUS_W::new(self) + } + #[doc = "Bit 7 - CTS state"] + #[inline(always)] + #[must_use] + pub fn cts_status(&mut self) -> CTS_STATUS_W<7> { + CTS_STATUS_W::new(self) + } + #[doc = "Bit 8 - Transmit FIFO is completely empty"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<8> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] + #[inline(always)] + #[must_use] + pub fn tx_done(&mut self) -> TX_DONE_W<9> { + TX_DONE_W::new(self) + } + #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W<16> { + RX_FIFO_LEVEL_W::new(self) + } + #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W<24> { + TX_FIFO_LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device.rs b/crates/bcm2835-lpa/src/usb_otg_device.rs new file mode 100644 index 0000000..8050e54 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device.rs @@ -0,0 +1,179 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS device configuration register"] + pub dcfg: DCFG, + #[doc = "0x04 - OTG_HS device control register"] + pub dctl: DCTL, + #[doc = "0x08 - OTG_HS device status register"] + pub dsts: DSTS, + _reserved3: [u8; 0x04], + #[doc = "0x10 - OTG_HS device IN endpoint common interrupt mask register"] + pub diepmsk: DIEPMSK, + #[doc = "0x14 - OTG_HS device OUT endpoint common interrupt mask register"] + pub doepmsk: DOEPMSK, + #[doc = "0x18 - OTG_HS device all endpoints interrupt register"] + pub daint: DAINT, + #[doc = "0x1c - OTG_HS all endpoints interrupt mask register"] + pub daintmsk: DAINTMSK, + _reserved7: [u8; 0x08], + #[doc = "0x28 - OTG_HS device VBUS discharge time register"] + pub dvbusdis: DVBUSDIS, + #[doc = "0x2c - OTG_HS device VBUS pulsing time register"] + pub dvbuspulse: DVBUSPULSE, + #[doc = "0x30 - OTG_HS Device threshold control register"] + pub dthrctl: DTHRCTL, + #[doc = "0x34 - OTG_HS device IN endpoint FIFO empty interrupt mask register"] + pub diepempmsk: DIEPEMPMSK, + #[doc = "0x38 - OTG_HS device each endpoint interrupt register"] + pub deachint: DEACHINT, + #[doc = "0x3c - OTG_HS device each endpoint interrupt register mask"] + pub deachintmsk: DEACHINTMSK, + #[doc = "0x40 - OTG_HS device each in endpoint-1 interrupt register"] + pub diepeachmsk1: DIEPEACHMSK1, + _reserved14: [u8; 0x3c], + #[doc = "0x80 - OTG_HS device each OUT endpoint-1 interrupt register"] + pub doepeachmsk1: DOEPEACHMSK1, + _reserved15: [u8; 0x7c], + #[doc = "0x100..0x11c - IN Endpoint %s"] + pub in_endpoint0: IN_ENDPOINT, + _reserved16: [u8; 0x04], + #[doc = "0x120..0x13c - IN Endpoint %s"] + pub in_endpoint1: IN_ENDPOINT, + _reserved17: [u8; 0x04], + #[doc = "0x140..0x15c - IN Endpoint %s"] + pub in_endpoint2: IN_ENDPOINT, + _reserved18: [u8; 0x04], + #[doc = "0x160..0x17c - IN Endpoint %s"] + pub in_endpoint3: IN_ENDPOINT, + _reserved19: [u8; 0x04], + #[doc = "0x180..0x19c - IN Endpoint %s"] + pub in_endpoint4: IN_ENDPOINT, + _reserved20: [u8; 0x04], + #[doc = "0x1a0..0x1bc - IN Endpoint %s"] + pub in_endpoint5: IN_ENDPOINT, + _reserved21: [u8; 0x04], + #[doc = "0x1c0..0x1dc - IN Endpoint %s"] + pub in_endpoint6: IN_ENDPOINT, + _reserved22: [u8; 0x04], + #[doc = "0x1e0..0x1fc - IN Endpoint %s"] + pub in_endpoint7: IN_ENDPOINT, + _reserved23: [u8; 0x04], + #[doc = "0x200..0x21c - IN Endpoint %s"] + pub in_endpoint8: IN_ENDPOINT, + _reserved24: [u8; 0x04], + #[doc = "0x220..0x23c - IN Endpoint %s"] + pub in_endpoint9: IN_ENDPOINT, + _reserved25: [u8; 0x04], + #[doc = "0x240..0x25c - IN Endpoint %s"] + pub in_endpoint10: IN_ENDPOINT, + _reserved26: [u8; 0x04], + #[doc = "0x260..0x27c - IN Endpoint %s"] + pub in_endpoint11: IN_ENDPOINT, + _reserved27: [u8; 0x84], + #[doc = "0x300..0x318 - OUT Endpoint %s"] + pub out_endpoint0: OUT_ENDPOINT, + _reserved28: [u8; 0x08], + #[doc = "0x320..0x338 - OUT Endpoint %s"] + pub out_endpoint1: OUT_ENDPOINT, + _reserved29: [u8; 0x08], + #[doc = "0x340..0x358 - OUT Endpoint %s"] + pub out_endpoint2: OUT_ENDPOINT, + _reserved30: [u8; 0x08], + #[doc = "0x360..0x378 - OUT Endpoint %s"] + pub out_endpoint3: OUT_ENDPOINT, + _reserved31: [u8; 0x08], + #[doc = "0x380..0x398 - OUT Endpoint %s"] + pub out_endpoint4: OUT_ENDPOINT, + _reserved32: [u8; 0x08], + #[doc = "0x3a0..0x3b8 - OUT Endpoint %s"] + pub out_endpoint5: OUT_ENDPOINT, + _reserved33: [u8; 0x08], + #[doc = "0x3c0..0x3d8 - OUT Endpoint %s"] + pub out_endpoint6: OUT_ENDPOINT, + _reserved34: [u8; 0x08], + #[doc = "0x3e0..0x3f8 - OUT Endpoint %s"] + pub out_endpoint7: OUT_ENDPOINT, + _reserved35: [u8; 0x08], + #[doc = "0x400..0x418 - OUT Endpoint %s"] + pub out_endpoint8: OUT_ENDPOINT, + _reserved36: [u8; 0x08], + #[doc = "0x420..0x438 - OUT Endpoint %s"] + pub out_endpoint9: OUT_ENDPOINT, + _reserved37: [u8; 0x08], + #[doc = "0x440..0x458 - OUT Endpoint %s"] + pub out_endpoint10: OUT_ENDPOINT, + _reserved38: [u8; 0x08], + #[doc = "0x460..0x478 - OUT Endpoint %s"] + pub out_endpoint11: OUT_ENDPOINT, +} +#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "OTG_HS device configuration register"] +pub mod dcfg; +#[doc = "DCTL (rw) register accessor: an alias for `Reg`"] +pub type DCTL = crate::Reg; +#[doc = "OTG_HS device control register"] +pub mod dctl; +#[doc = "DSTS (r) register accessor: an alias for `Reg`"] +pub type DSTS = crate::Reg; +#[doc = "OTG_HS device status register"] +pub mod dsts; +#[doc = "DIEPMSK (rw) register accessor: an alias for `Reg`"] +pub type DIEPMSK = crate::Reg; +#[doc = "OTG_HS device IN endpoint common interrupt mask register"] +pub mod diepmsk; +#[doc = "DOEPMSK (rw) register accessor: an alias for `Reg`"] +pub type DOEPMSK = crate::Reg; +#[doc = "OTG_HS device OUT endpoint common interrupt mask register"] +pub mod doepmsk; +#[doc = "DAINT (r) register accessor: an alias for `Reg`"] +pub type DAINT = crate::Reg; +#[doc = "OTG_HS device all endpoints interrupt register"] +pub mod daint; +#[doc = "DAINTMSK (rw) register accessor: an alias for `Reg`"] +pub type DAINTMSK = crate::Reg; +#[doc = "OTG_HS all endpoints interrupt mask register"] +pub mod daintmsk; +#[doc = "DVBUSDIS (rw) register accessor: an alias for `Reg`"] +pub type DVBUSDIS = crate::Reg; +#[doc = "OTG_HS device VBUS discharge time register"] +pub mod dvbusdis; +#[doc = "DVBUSPULSE (rw) register accessor: an alias for `Reg`"] +pub type DVBUSPULSE = crate::Reg; +#[doc = "OTG_HS device VBUS pulsing time register"] +pub mod dvbuspulse; +#[doc = "DTHRCTL (rw) register accessor: an alias for `Reg`"] +pub type DTHRCTL = crate::Reg; +#[doc = "OTG_HS Device threshold control register"] +pub mod dthrctl; +#[doc = "DIEPEMPMSK (rw) register accessor: an alias for `Reg`"] +pub type DIEPEMPMSK = crate::Reg; +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register"] +pub mod diepempmsk; +#[doc = "DEACHINT (rw) register accessor: an alias for `Reg`"] +pub type DEACHINT = crate::Reg; +#[doc = "OTG_HS device each endpoint interrupt register"] +pub mod deachint; +#[doc = "DEACHINTMSK (rw) register accessor: an alias for `Reg`"] +pub type DEACHINTMSK = crate::Reg; +#[doc = "OTG_HS device each endpoint interrupt register mask"] +pub mod deachintmsk; +#[doc = "DIEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +pub type DIEPEACHMSK1 = crate::Reg; +#[doc = "OTG_HS device each in endpoint-1 interrupt register"] +pub mod diepeachmsk1; +#[doc = "DOEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +pub type DOEPEACHMSK1 = crate::Reg; +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register"] +pub mod doepeachmsk1; +#[doc = "IN Endpoint %s"] +pub use self::in_endpoint::IN_ENDPOINT; +#[doc = r"Cluster"] +#[doc = "IN Endpoint %s"] +pub mod in_endpoint; +#[doc = "OUT Endpoint %s"] +pub use self::out_endpoint::OUT_ENDPOINT; +#[doc = r"Cluster"] +#[doc = "OUT Endpoint %s"] +pub mod out_endpoint; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/daint.rs b/crates/bcm2835-lpa/src/usb_otg_device/daint.rs new file mode 100644 index 0000000..14c25b3 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/daint.rs @@ -0,0 +1,44 @@ +#[doc = "Register `DAINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IEPINT` reader - IN endpoint interrupt bits"] +pub type IEPINT_R = crate::FieldReader; +#[doc = "Field `OEPINT` reader - OUT endpoint interrupt bits"] +pub type OEPINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - IN endpoint interrupt bits"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - OUT endpoint interrupt bits"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "OTG_HS device all endpoints interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](index.html) module"] +pub struct DAINT_SPEC; +impl crate::RegisterSpec for DAINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [daint::R](R) reader structure"] +impl crate::Readable for DAINT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DAINT to value 0"] +impl crate::Resettable for DAINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs new file mode 100644 index 0000000..bf7c858 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DAINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEPM` reader - IN EP interrupt mask bits"] +pub type IEPM_R = crate::FieldReader; +#[doc = "Field `IEPM` writer - IN EP interrupt mask bits"] +pub type IEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +#[doc = "Field `OEPM` reader - OUT EP interrupt mask bits"] +pub type OEPM_R = crate::FieldReader; +#[doc = "Field `OEPM` writer - OUT EP interrupt mask bits"] +pub type OEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN EP interrupt mask bits"] + #[inline(always)] + pub fn iepm(&self) -> IEPM_R { + IEPM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] + #[inline(always)] + pub fn oepm(&self) -> OEPM_R { + OEPM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN EP interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn iepm(&mut self) -> IEPM_W<0> { + IEPM_W::new(self) + } + #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn oepm(&mut self) -> OEPM_W<16> { + OEPM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS all endpoints interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](index.html) module"] +pub struct DAINTMSK_SPEC; +impl crate::RegisterSpec for DAINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [daintmsk::R](R) reader structure"] +impl crate::Readable for DAINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [daintmsk::W](W) writer structure"] +impl crate::Writable for DAINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAINTMSK to value 0"] +impl crate::Resettable for DAINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs b/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs new file mode 100644 index 0000000..ad6ef16 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSPD` reader - Device speed"] +pub type DSPD_R = crate::FieldReader; +#[doc = "Field `DSPD` writer - Device speed"] +pub type DSPD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `NZLSOHSK` reader - Nonzero-length status OUT handshake"] +pub type NZLSOHSK_R = crate::BitReader; +#[doc = "Field `NZLSOHSK` writer - Nonzero-length status OUT handshake"] +pub type NZLSOHSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCFG_SPEC, bool, O>; +#[doc = "Field `DAD` reader - Device address"] +pub type DAD_R = crate::FieldReader; +#[doc = "Field `DAD` writer - Device address"] +pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 7, O>; +#[doc = "Field `PFIVL` reader - Periodic (micro)frame interval"] +pub type PFIVL_R = crate::FieldReader; +#[doc = "Field `PFIVL` writer - Periodic (micro)frame interval"] +pub type PFIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `PERSCHIVL` reader - Periodic scheduling interval"] +pub type PERSCHIVL_R = crate::FieldReader; +#[doc = "Field `PERSCHIVL` writer - Periodic scheduling interval"] +pub type PERSCHIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:1 - Device speed"] + #[inline(always)] + pub fn dspd(&self) -> DSPD_R { + DSPD_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Nonzero-length status OUT handshake"] + #[inline(always)] + pub fn nzlsohsk(&self) -> NZLSOHSK_R { + NZLSOHSK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:10 - Device address"] + #[inline(always)] + pub fn dad(&self) -> DAD_R { + DAD_R::new(((self.bits >> 4) & 0x7f) as u8) + } + #[doc = "Bits 11:12 - Periodic (micro)frame interval"] + #[inline(always)] + pub fn pfivl(&self) -> PFIVL_R { + PFIVL_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bits 24:25 - Periodic scheduling interval"] + #[inline(always)] + pub fn perschivl(&self) -> PERSCHIVL_R { + PERSCHIVL_R::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Device speed"] + #[inline(always)] + #[must_use] + pub fn dspd(&mut self) -> DSPD_W<0> { + DSPD_W::new(self) + } + #[doc = "Bit 2 - Nonzero-length status OUT handshake"] + #[inline(always)] + #[must_use] + pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<2> { + NZLSOHSK_W::new(self) + } + #[doc = "Bits 4:10 - Device address"] + #[inline(always)] + #[must_use] + pub fn dad(&mut self) -> DAD_W<4> { + DAD_W::new(self) + } + #[doc = "Bits 11:12 - Periodic (micro)frame interval"] + #[inline(always)] + #[must_use] + pub fn pfivl(&mut self) -> PFIVL_W<11> { + PFIVL_W::new(self) + } + #[doc = "Bits 24:25 - Periodic scheduling interval"] + #[inline(always)] + #[must_use] + pub fn perschivl(&mut self) -> PERSCHIVL_W<24> { + PERSCHIVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCFG to value 0x0220_0000"] +impl crate::Resettable for DCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_0000; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs b/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs new file mode 100644 index 0000000..ed73ebd --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs @@ -0,0 +1,171 @@ +#[doc = "Register `DCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RWUSIG` reader - Remote wakeup signaling"] +pub type RWUSIG_R = crate::BitReader; +#[doc = "Field `RWUSIG` writer - Remote wakeup signaling"] +pub type RWUSIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `SDIS` reader - Soft disconnect"] +pub type SDIS_R = crate::BitReader; +#[doc = "Field `SDIS` writer - Soft disconnect"] +pub type SDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `GINSTS` reader - Global IN NAK status"] +pub type GINSTS_R = crate::BitReader; +#[doc = "Field `GONSTS` reader - Global OUT NAK status"] +pub type GONSTS_R = crate::BitReader; +#[doc = "Field `TCTL` reader - Test control"] +pub type TCTL_R = crate::FieldReader; +#[doc = "Field `TCTL` writer - Test control"] +pub type TCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTL_SPEC, u8, u8, 3, O>; +#[doc = "Field `SGINAK` writer - Set global IN NAK"] +pub type SGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `CGINAK` writer - Clear global IN NAK"] +pub type CGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `SGONAK` writer - Set global OUT NAK"] +pub type SGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `CGONAK` writer - Clear global OUT NAK"] +pub type CGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `POPRGDNE` reader - Power-on programming done"] +pub type POPRGDNE_R = crate::BitReader; +#[doc = "Field `POPRGDNE` writer - Power-on programming done"] +pub type POPRGDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Remote wakeup signaling"] + #[inline(always)] + pub fn rwusig(&self) -> RWUSIG_R { + RWUSIG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Soft disconnect"] + #[inline(always)] + pub fn sdis(&self) -> SDIS_R { + SDIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Global IN NAK status"] + #[inline(always)] + pub fn ginsts(&self) -> GINSTS_R { + GINSTS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Global OUT NAK status"] + #[inline(always)] + pub fn gonsts(&self) -> GONSTS_R { + GONSTS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Test control"] + #[inline(always)] + pub fn tctl(&self) -> TCTL_R { + TCTL_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 11 - Power-on programming done"] + #[inline(always)] + pub fn poprgdne(&self) -> POPRGDNE_R { + POPRGDNE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remote wakeup signaling"] + #[inline(always)] + #[must_use] + pub fn rwusig(&mut self) -> RWUSIG_W<0> { + RWUSIG_W::new(self) + } + #[doc = "Bit 1 - Soft disconnect"] + #[inline(always)] + #[must_use] + pub fn sdis(&mut self) -> SDIS_W<1> { + SDIS_W::new(self) + } + #[doc = "Bits 4:6 - Test control"] + #[inline(always)] + #[must_use] + pub fn tctl(&mut self) -> TCTL_W<4> { + TCTL_W::new(self) + } + #[doc = "Bit 7 - Set global IN NAK"] + #[inline(always)] + #[must_use] + pub fn sginak(&mut self) -> SGINAK_W<7> { + SGINAK_W::new(self) + } + #[doc = "Bit 8 - Clear global IN NAK"] + #[inline(always)] + #[must_use] + pub fn cginak(&mut self) -> CGINAK_W<8> { + CGINAK_W::new(self) + } + #[doc = "Bit 9 - Set global OUT NAK"] + #[inline(always)] + #[must_use] + pub fn sgonak(&mut self) -> SGONAK_W<9> { + SGONAK_W::new(self) + } + #[doc = "Bit 10 - Clear global OUT NAK"] + #[inline(always)] + #[must_use] + pub fn cgonak(&mut self) -> CGONAK_W<10> { + CGONAK_W::new(self) + } + #[doc = "Bit 11 - Power-on programming done"] + #[inline(always)] + #[must_use] + pub fn poprgdne(&mut self) -> POPRGDNE_W<11> { + POPRGDNE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](index.html) module"] +pub struct DCTL_SPEC; +impl crate::RegisterSpec for DCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dctl::R](R) reader structure"] +impl crate::Readable for DCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dctl::W](W) writer structure"] +impl crate::Writable for DCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCTL to value 0"] +impl crate::Resettable for DCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs b/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs new file mode 100644 index 0000000..b2e2a0b --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEACHINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEACHINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEP1INT` reader - IN endpoint 1interrupt bit"] +pub type IEP1INT_R = crate::BitReader; +#[doc = "Field `IEP1INT` writer - IN endpoint 1interrupt bit"] +pub type IEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +#[doc = "Field `OEP1INT` reader - OUT endpoint 1 interrupt bit"] +pub type OEP1INT_R = crate::BitReader; +#[doc = "Field `OEP1INT` writer - OUT endpoint 1 interrupt bit"] +pub type OEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - IN endpoint 1interrupt bit"] + #[inline(always)] + pub fn iep1int(&self) -> IEP1INT_R { + IEP1INT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] + #[inline(always)] + pub fn oep1int(&self) -> OEP1INT_R { + OEP1INT_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - IN endpoint 1interrupt bit"] + #[inline(always)] + #[must_use] + pub fn iep1int(&mut self) -> IEP1INT_W<1> { + IEP1INT_W::new(self) + } + #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] + #[inline(always)] + #[must_use] + pub fn oep1int(&mut self) -> OEP1INT_W<17> { + OEP1INT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each endpoint interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachint](index.html) module"] +pub struct DEACHINT_SPEC; +impl crate::RegisterSpec for DEACHINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deachint::R](R) reader structure"] +impl crate::Readable for DEACHINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [deachint::W](W) writer structure"] +impl crate::Writable for DEACHINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEACHINT to value 0"] +impl crate::Resettable for DEACHINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs new file mode 100644 index 0000000..635cecf --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEACHINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEACHINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEP1INTM` reader - IN Endpoint 1 interrupt mask bit"] +pub type IEP1INTM_R = crate::BitReader; +#[doc = "Field `IEP1INTM` writer - IN Endpoint 1 interrupt mask bit"] +pub type IEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +#[doc = "Field `OEP1INTM` reader - OUT Endpoint 1 interrupt mask bit"] +pub type OEP1INTM_R = crate::BitReader; +#[doc = "Field `OEP1INTM` writer - OUT Endpoint 1 interrupt mask bit"] +pub type OEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] + #[inline(always)] + pub fn iep1intm(&self) -> IEP1INTM_R { + IEP1INTM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] + #[inline(always)] + pub fn oep1intm(&self) -> OEP1INTM_R { + OEP1INTM_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] + #[inline(always)] + #[must_use] + pub fn iep1intm(&mut self) -> IEP1INTM_W<1> { + IEP1INTM_W::new(self) + } + #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] + #[inline(always)] + #[must_use] + pub fn oep1intm(&mut self) -> OEP1INTM_W<17> { + OEP1INTM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each endpoint interrupt register mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachintmsk](index.html) module"] +pub struct DEACHINTMSK_SPEC; +impl crate::RegisterSpec for DEACHINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deachintmsk::R](R) reader structure"] +impl crate::Readable for DEACHINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [deachintmsk::W](W) writer structure"] +impl crate::Writable for DEACHINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEACHINTMSK to value 0"] +impl crate::Resettable for DEACHINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs b/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs new file mode 100644 index 0000000..6e00947 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs @@ -0,0 +1,200 @@ +#[doc = "Register `DIEPEACHMSK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPEACHMSK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - FIFO underrun mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - FIFO underrun mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<13> { + NAKM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepeachmsk1](index.html) module"] +pub struct DIEPEACHMSK1_SPEC; +impl crate::RegisterSpec for DIEPEACHMSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepeachmsk1::R](R) reader structure"] +impl crate::Readable for DIEPEACHMSK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepeachmsk1::W](W) writer structure"] +impl crate::Writable for DIEPEACHMSK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPEACHMSK1 to value 0"] +impl crate::Resettable for DIEPEACHMSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs new file mode 100644 index 0000000..8e5b978 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs @@ -0,0 +1,81 @@ +#[doc = "Register `DIEPEMPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPEMPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXFEM` reader - IN EP Tx FIFO empty interrupt mask bits"] +pub type INEPTXFEM_R = crate::FieldReader; +#[doc = "Field `INEPTXFEM` writer - IN EP Tx FIFO empty interrupt mask bits"] +pub type INEPTXFEM_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, DIEPEMPMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] + #[inline(always)] + pub fn ineptxfem(&self) -> INEPTXFEM_R { + INEPTXFEM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn ineptxfem(&mut self) -> INEPTXFEM_W<0> { + INEPTXFEM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](index.html) module"] +pub struct DIEPEMPMSK_SPEC; +impl crate::RegisterSpec for DIEPEMPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepempmsk::R](R) reader structure"] +impl crate::Readable for DIEPEMPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepempmsk::W](W) writer structure"] +impl crate::Writable for DIEPEMPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPEMPMSK to value 0"] +impl crate::Resettable for DIEPEMPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs new file mode 100644 index 0000000..6411ce9 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs @@ -0,0 +1,185 @@ +#[doc = "Register `DIEPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - FIFO underrun mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - FIFO underrun mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"] +pub struct DIEPMSK_SPEC; +impl crate::RegisterSpec for DIEPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepmsk::R](R) reader structure"] +impl crate::Readable for DIEPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"] +impl crate::Writable for DIEPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPMSK to value 0"] +impl crate::Resettable for DIEPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs b/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs new file mode 100644 index 0000000..31a5ab1 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs @@ -0,0 +1,230 @@ +#[doc = "Register `DOEPEACHMSK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPEACHMSK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - OUT packet error mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - OUT packet error mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BERRM` reader - Bubble error interrupt mask"] +pub type BERRM_R = crate::BitReader; +#[doc = "Field `BERRM` writer - Bubble error interrupt mask"] +pub type BERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NYETM` reader - NYET interrupt mask"] +pub type NYETM_R = crate::BitReader; +#[doc = "Field `NYETM` writer - NYET interrupt mask"] +pub type NYETM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Bubble error interrupt mask"] + #[inline(always)] + pub fn berrm(&self) -> BERRM_R { + BERRM_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NYET interrupt mask"] + #[inline(always)] + pub fn nyetm(&self) -> NYETM_R { + NYETM_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Bit 12 - Bubble error interrupt mask"] + #[inline(always)] + #[must_use] + pub fn berrm(&mut self) -> BERRM_W<12> { + BERRM_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<13> { + NAKM_W::new(self) + } + #[doc = "Bit 14 - NYET interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nyetm(&mut self) -> NYETM_W<14> { + NYETM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepeachmsk1](index.html) module"] +pub struct DOEPEACHMSK1_SPEC; +impl crate::RegisterSpec for DOEPEACHMSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepeachmsk1::R](R) reader structure"] +impl crate::Readable for DOEPEACHMSK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepeachmsk1::W](W) writer structure"] +impl crate::Writable for DOEPEACHMSK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPEACHMSK1 to value 0"] +impl crate::Resettable for DOEPEACHMSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs new file mode 100644 index 0000000..46e5ca8 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs @@ -0,0 +1,170 @@ +#[doc = "Register `DOEPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `STUPM` reader - SETUP phase done mask"] +pub type STUPM_R = crate::BitReader; +#[doc = "Field `STUPM` writer - SETUP phase done mask"] +pub type STUPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `OTEPDM` reader - OUT token received when endpoint disabled mask"] +pub type OTEPDM_R = crate::BitReader; +#[doc = "Field `OTEPDM` writer - OUT token received when endpoint disabled mask"] +pub type OTEPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received mask"] +pub type B2BSTUP_R = crate::BitReader; +#[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received mask"] +pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `OPEM` reader - OUT packet error mask"] +pub type OPEM_R = crate::BitReader; +#[doc = "Field `OPEM` writer - OUT packet error mask"] +pub type OPEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `BOIM` reader - BNA interrupt mask"] +pub type BOIM_R = crate::BitReader; +#[doc = "Field `BOIM` writer - BNA interrupt mask"] +pub type BOIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - SETUP phase done mask"] + #[inline(always)] + pub fn stupm(&self) -> STUPM_R { + STUPM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] + #[inline(always)] + pub fn otepdm(&self) -> OTEPDM_R { + OTEPDM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] + #[inline(always)] + pub fn b2bstup(&self) -> B2BSTUP_R { + B2BSTUP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + pub fn opem(&self) -> OPEM_R { + OPEM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn boim(&self) -> BOIM_R { + BOIM_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - SETUP phase done mask"] + #[inline(always)] + #[must_use] + pub fn stupm(&mut self) -> STUPM_W<3> { + STUPM_W::new(self) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] + #[inline(always)] + #[must_use] + pub fn otepdm(&mut self) -> OTEPDM_W<4> { + OTEPDM_W::new(self) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] + #[inline(always)] + #[must_use] + pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + B2BSTUP_W::new(self) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + #[must_use] + pub fn opem(&mut self) -> OPEM_W<8> { + OPEM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn boim(&mut self) -> BOIM_W<9> { + BOIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](index.html) module"] +pub struct DOEPMSK_SPEC; +impl crate::RegisterSpec for DOEPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepmsk::R](R) reader structure"] +impl crate::Readable for DOEPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepmsk::W](W) writer structure"] +impl crate::Writable for DOEPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPMSK to value 0"] +impl crate::Resettable for DOEPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs b/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs new file mode 100644 index 0000000..ddf0900 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs @@ -0,0 +1,58 @@ +#[doc = "Register `DSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUSPSTS` reader - Suspend status"] +pub type SUSPSTS_R = crate::BitReader; +#[doc = "Field `ENUMSPD` reader - Enumerated speed"] +pub type ENUMSPD_R = crate::FieldReader; +#[doc = "Field `EERR` reader - Erratic error"] +pub type EERR_R = crate::BitReader; +#[doc = "Field `FNSOF` reader - Frame number of the received SOF"] +pub type FNSOF_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Suspend status"] + #[inline(always)] + pub fn suspsts(&self) -> SUSPSTS_R { + SUSPSTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Enumerated speed"] + #[inline(always)] + pub fn enumspd(&self) -> ENUMSPD_R { + ENUMSPD_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Erratic error"] + #[inline(always)] + pub fn eerr(&self) -> EERR_R { + EERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:21 - Frame number of the received SOF"] + #[inline(always)] + pub fn fnsof(&self) -> FNSOF_R { + FNSOF_R::new(((self.bits >> 8) & 0x3fff) as u16) + } +} +#[doc = "OTG_HS device status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](index.html) module"] +pub struct DSTS_SPEC; +impl crate::RegisterSpec for DSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dsts::R](R) reader structure"] +impl crate::Readable for DSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DSTS to value 0x10"] +impl crate::Resettable for DSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs b/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs new file mode 100644 index 0000000..ea85092 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DTHRCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DTHRCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NONISOTHREN` reader - Nonisochronous IN endpoints threshold enable"] +pub type NONISOTHREN_R = crate::BitReader; +#[doc = "Field `NONISOTHREN` writer - Nonisochronous IN endpoints threshold enable"] +pub type NONISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `ISOTHREN` reader - ISO IN endpoint threshold enable"] +pub type ISOTHREN_R = crate::BitReader; +#[doc = "Field `ISOTHREN` writer - ISO IN endpoint threshold enable"] +pub type ISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `TXTHRLEN` reader - Transmit threshold length"] +pub type TXTHRLEN_R = crate::FieldReader; +#[doc = "Field `TXTHRLEN` writer - Transmit threshold length"] +pub type TXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +#[doc = "Field `RXTHREN` reader - Receive threshold enable"] +pub type RXTHREN_R = crate::BitReader; +#[doc = "Field `RXTHREN` writer - Receive threshold enable"] +pub type RXTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `RXTHRLEN` reader - Receive threshold length"] +pub type RXTHRLEN_R = crate::FieldReader; +#[doc = "Field `RXTHRLEN` writer - Receive threshold length"] +pub type RXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +#[doc = "Field `ARPEN` reader - Arbiter parking enable"] +pub type ARPEN_R = crate::BitReader; +#[doc = "Field `ARPEN` writer - Arbiter parking enable"] +pub type ARPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] + #[inline(always)] + pub fn nonisothren(&self) -> NONISOTHREN_R { + NONISOTHREN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ISO IN endpoint threshold enable"] + #[inline(always)] + pub fn isothren(&self) -> ISOTHREN_R { + ISOTHREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:10 - Transmit threshold length"] + #[inline(always)] + pub fn txthrlen(&self) -> TXTHRLEN_R { + TXTHRLEN_R::new(((self.bits >> 2) & 0x01ff) as u16) + } + #[doc = "Bit 16 - Receive threshold enable"] + #[inline(always)] + pub fn rxthren(&self) -> RXTHREN_R { + RXTHREN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:25 - Receive threshold length"] + #[inline(always)] + pub fn rxthrlen(&self) -> RXTHRLEN_R { + RXTHRLEN_R::new(((self.bits >> 17) & 0x01ff) as u16) + } + #[doc = "Bit 27 - Arbiter parking enable"] + #[inline(always)] + pub fn arpen(&self) -> ARPEN_R { + ARPEN_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] + #[inline(always)] + #[must_use] + pub fn nonisothren(&mut self) -> NONISOTHREN_W<0> { + NONISOTHREN_W::new(self) + } + #[doc = "Bit 1 - ISO IN endpoint threshold enable"] + #[inline(always)] + #[must_use] + pub fn isothren(&mut self) -> ISOTHREN_W<1> { + ISOTHREN_W::new(self) + } + #[doc = "Bits 2:10 - Transmit threshold length"] + #[inline(always)] + #[must_use] + pub fn txthrlen(&mut self) -> TXTHRLEN_W<2> { + TXTHRLEN_W::new(self) + } + #[doc = "Bit 16 - Receive threshold enable"] + #[inline(always)] + #[must_use] + pub fn rxthren(&mut self) -> RXTHREN_W<16> { + RXTHREN_W::new(self) + } + #[doc = "Bits 17:25 - Receive threshold length"] + #[inline(always)] + #[must_use] + pub fn rxthrlen(&mut self) -> RXTHRLEN_W<17> { + RXTHRLEN_W::new(self) + } + #[doc = "Bit 27 - Arbiter parking enable"] + #[inline(always)] + #[must_use] + pub fn arpen(&mut self) -> ARPEN_W<27> { + ARPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Device threshold control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](index.html) module"] +pub struct DTHRCTL_SPEC; +impl crate::RegisterSpec for DTHRCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dthrctl::R](R) reader structure"] +impl crate::Readable for DTHRCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dthrctl::W](W) writer structure"] +impl crate::Writable for DTHRCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DTHRCTL to value 0"] +impl crate::Resettable for DTHRCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs b/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs new file mode 100644 index 0000000..403e00a --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DVBUSDIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DVBUSDIS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VBUSDT` reader - Device VBUS discharge time"] +pub type VBUSDT_R = crate::FieldReader; +#[doc = "Field `VBUSDT` writer - Device VBUS discharge time"] +pub type VBUSDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSDIS_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Device VBUS discharge time"] + #[inline(always)] + pub fn vbusdt(&self) -> VBUSDT_R { + VBUSDT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Device VBUS discharge time"] + #[inline(always)] + #[must_use] + pub fn vbusdt(&mut self) -> VBUSDT_W<0> { + VBUSDT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device VBUS discharge time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](index.html) module"] +pub struct DVBUSDIS_SPEC; +impl crate::RegisterSpec for DVBUSDIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dvbusdis::R](R) reader structure"] +impl crate::Readable for DVBUSDIS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dvbusdis::W](W) writer structure"] +impl crate::Writable for DVBUSDIS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DVBUSDIS to value 0x17d7"] +impl crate::Resettable for DVBUSDIS_SPEC { + const RESET_VALUE: Self::Ux = 0x17d7; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs b/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs new file mode 100644 index 0000000..4871f7b --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DVBUSPULSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DVBUSPULSE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DVBUSP` reader - Device VBUS pulsing time"] +pub type DVBUSP_R = crate::FieldReader; +#[doc = "Field `DVBUSP` writer - Device VBUS pulsing time"] +pub type DVBUSP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSPULSE_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Device VBUS pulsing time"] + #[inline(always)] + pub fn dvbusp(&self) -> DVBUSP_R { + DVBUSP_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Device VBUS pulsing time"] + #[inline(always)] + #[must_use] + pub fn dvbusp(&mut self) -> DVBUSP_W<0> { + DVBUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device VBUS pulsing time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](index.html) module"] +pub struct DVBUSPULSE_SPEC; +impl crate::RegisterSpec for DVBUSPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dvbuspulse::R](R) reader structure"] +impl crate::Readable for DVBUSPULSE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](W) writer structure"] +impl crate::Writable for DVBUSPULSE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DVBUSPULSE to value 0x05b8"] +impl crate::Resettable for DVBUSPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x05b8; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs new file mode 100644 index 0000000..5fd5349 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs @@ -0,0 +1,36 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct IN_ENDPOINT { + #[doc = "0x00 - Control"] + pub diepctl0: DIEPCTL0, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Interrupt"] + pub diepint: DIEPINT, + _reserved2: [u8; 0x04], + #[doc = "0x10 - Transfer size"] + pub dieptsiz: DIEPTSIZ, + #[doc = "0x14 - DMA address"] + pub diepdma: DIEPDMA, + #[doc = "0x18 - Transmit FIFO status"] + pub dtxfsts: DTXFSTS, +} +#[doc = "DIEPCTL0 (rw) register accessor: an alias for `Reg`"] +pub type DIEPCTL0 = crate::Reg; +#[doc = "Control"] +pub mod diepctl0; +#[doc = "DIEPINT (rw) register accessor: an alias for `Reg`"] +pub type DIEPINT = crate::Reg; +#[doc = "Interrupt"] +pub mod diepint; +#[doc = "DIEPTSIZ (rw) register accessor: an alias for `Reg`"] +pub type DIEPTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod dieptsiz; +#[doc = "DIEPDMA (rw) register accessor: an alias for `Reg`"] +pub type DIEPDMA = crate::Reg; +#[doc = "DMA address"] +pub mod diepdma; +#[doc = "DTXFSTS (r) register accessor: an alias for `Reg`"] +pub type DTXFSTS = crate::Reg; +#[doc = "Transmit FIFO status"] +pub mod dtxfsts; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs new file mode 100644 index 0000000..b8fa051 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs @@ -0,0 +1,216 @@ +#[doc = "Register `DIEPCTL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPCTL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `MPSIZ` writer - Maximum packet size"] +pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u16, u16, 11, O>; +#[doc = "Field `USBAEP` reader - USB active endpoint"] +pub type USBAEP_R = crate::BitReader; +#[doc = "Field `USBAEP` writer - USB active endpoint"] +pub type USBAEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EONUM_DPID` reader - Even/odd frame"] +pub type EONUM_DPID_R = crate::BitReader; +#[doc = "Field `NAKSTS` reader - NAK status"] +pub type NAKSTS_R = crate::BitReader; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `EPTYP` writer - Endpoint type"] +pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 2, O>; +#[doc = "Field `Stall` reader - STALL handshake"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `Stall` writer - STALL handshake"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `TXFNUM` reader - TxFIFO number"] +pub type TXFNUM_R = crate::FieldReader; +#[doc = "Field `TXFNUM` writer - TxFIFO number"] +pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `CNAK` writer - Clear NAK"] +pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SNAK` writer - Set NAK"] +pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SD0PID_SEVNFRM` writer - Set DATA0 PID"] +pub type SD0PID_SEVNFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SODDFRM` writer - Set odd frame"] +pub type SODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EPDIS` reader - Endpoint disable"] +pub type EPDIS_R = crate::BitReader; +#[doc = "Field `EPDIS` writer - Endpoint disable"] +pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EPENA` reader - Endpoint enable"] +pub type EPENA_R = crate::BitReader; +#[doc = "Field `EPENA` writer - Endpoint enable"] +pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + pub fn usbaep(&self) -> USBAEP_R { + USBAEP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Even/odd frame"] + #[inline(always)] + pub fn eonum_dpid(&self) -> EONUM_DPID_R { + EONUM_DPID_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NAK status"] + #[inline(always)] + pub fn naksts(&self) -> NAKSTS_R { + NAKSTS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:25 - TxFIFO number"] + #[inline(always)] + pub fn txfnum(&self) -> TXFNUM_R { + TXFNUM_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + pub fn epdis(&self) -> EPDIS_R { + EPDIS_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + pub fn epena(&self) -> EPENA_R { + EPENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + #[must_use] + pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + MPSIZ_W::new(self) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + #[must_use] + pub fn usbaep(&mut self) -> USBAEP_W<15> { + USBAEP_W::new(self) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + #[must_use] + pub fn eptyp(&mut self) -> EPTYP_W<18> { + EPTYP_W::new(self) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<21> { + STALL_W::new(self) + } + #[doc = "Bits 22:25 - TxFIFO number"] + #[inline(always)] + #[must_use] + pub fn txfnum(&mut self) -> TXFNUM_W<22> { + TXFNUM_W::new(self) + } + #[doc = "Bit 26 - Clear NAK"] + #[inline(always)] + #[must_use] + pub fn cnak(&mut self) -> CNAK_W<26> { + CNAK_W::new(self) + } + #[doc = "Bit 27 - Set NAK"] + #[inline(always)] + #[must_use] + pub fn snak(&mut self) -> SNAK_W<27> { + SNAK_W::new(self) + } + #[doc = "Bit 28 - Set DATA0 PID"] + #[inline(always)] + #[must_use] + pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<28> { + SD0PID_SEVNFRM_W::new(self) + } + #[doc = "Bit 29 - Set odd frame"] + #[inline(always)] + #[must_use] + pub fn soddfrm(&mut self) -> SODDFRM_W<29> { + SODDFRM_W::new(self) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + #[must_use] + pub fn epdis(&mut self) -> EPDIS_W<30> { + EPDIS_W::new(self) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + #[must_use] + pub fn epena(&mut self) -> EPENA_W<31> { + EPENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepctl0](index.html) module"] +pub struct DIEPCTL0_SPEC; +impl crate::RegisterSpec for DIEPCTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepctl0::R](R) reader structure"] +impl crate::Readable for DIEPCTL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepctl0::W](W) writer structure"] +impl crate::Writable for DIEPCTL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPCTL0 to value 0"] +impl crate::Resettable for DIEPCTL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs new file mode 100644 index 0000000..321905e --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DIEPDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepdma](index.html) module"] +pub struct DIEPDMA_SPEC; +impl crate::RegisterSpec for DIEPDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepdma::R](R) reader structure"] +impl crate::Readable for DIEPDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepdma::W](W) writer structure"] +impl crate::Writable for DIEPDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPDMA to value 0"] +impl crate::Resettable for DIEPDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs new file mode 100644 index 0000000..f85ca85 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs @@ -0,0 +1,222 @@ +#[doc = "Register `DIEPINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed interrupt"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed interrupt"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] +pub type EPDISD_R = crate::BitReader; +#[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] +pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `TOC` reader - Timeout condition"] +pub type TOC_R = crate::BitReader; +#[doc = "Field `TOC` writer - Timeout condition"] +pub type TOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `ITTXFE` reader - IN token received when TxFIFO is empty"] +pub type ITTXFE_R = crate::BitReader; +#[doc = "Field `ITTXFE` writer - IN token received when TxFIFO is empty"] +pub type ITTXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `INEPNE` reader - IN endpoint NAK effective"] +pub type INEPNE_R = crate::BitReader; +#[doc = "Field `INEPNE` writer - IN endpoint NAK effective"] +pub type INEPNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `TXFE` reader - Transmit FIFO empty"] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `TXFIFOUDRN` reader - Transmit Fifo Underrun"] +pub type TXFIFOUDRN_R = crate::BitReader; +#[doc = "Field `TXFIFOUDRN` writer - Transmit Fifo Underrun"] +pub type TXFIFOUDRN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `BNA` reader - Buffer not available interrupt"] +pub type BNA_R = crate::BitReader; +#[doc = "Field `BNA` writer - Buffer not available interrupt"] +pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `PKTDRPSTS` reader - Packet dropped status"] +pub type PKTDRPSTS_R = crate::BitReader; +#[doc = "Field `PKTDRPSTS` writer - Packet dropped status"] +pub type PKTDRPSTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Babble error interrupt"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Babble error interrupt"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `NAK` reader - NAK interrupt"] +pub type NAK_R = crate::BitReader; +#[doc = "Field `NAK` writer - NAK interrupt"] +pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + pub fn epdisd(&self) -> EPDISD_R { + EPDISD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO is empty"] + #[inline(always)] + pub fn ittxfe(&self) -> ITTXFE_R { + ITTXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective"] + #[inline(always)] + pub fn inepne(&self) -> INEPNE_R { + INEPNE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transmit FIFO empty"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit Fifo Underrun"] + #[inline(always)] + pub fn txfifoudrn(&self) -> TXFIFOUDRN_R { + TXFIFOUDRN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Buffer not available interrupt"] + #[inline(always)] + pub fn bna(&self) -> BNA_R { + BNA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Packet dropped status"] + #[inline(always)] + pub fn pktdrpsts(&self) -> PKTDRPSTS_R { + PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Babble error interrupt"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt"] + #[inline(always)] + pub fn nak(&self) -> NAK_R { + NAK_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + #[must_use] + pub fn epdisd(&mut self) -> EPDISD_W<1> { + EPDISD_W::new(self) + } + #[doc = "Bit 3 - Timeout condition"] + #[inline(always)] + #[must_use] + pub fn toc(&mut self) -> TOC_W<3> { + TOC_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO is empty"] + #[inline(always)] + #[must_use] + pub fn ittxfe(&mut self) -> ITTXFE_W<4> { + ITTXFE_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective"] + #[inline(always)] + #[must_use] + pub fn inepne(&mut self) -> INEPNE_W<6> { + INEPNE_W::new(self) + } + #[doc = "Bit 8 - Transmit Fifo Underrun"] + #[inline(always)] + #[must_use] + pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<8> { + TXFIFOUDRN_W::new(self) + } + #[doc = "Bit 9 - Buffer not available interrupt"] + #[inline(always)] + #[must_use] + pub fn bna(&mut self) -> BNA_W<9> { + BNA_W::new(self) + } + #[doc = "Bit 11 - Packet dropped status"] + #[inline(always)] + #[must_use] + pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<11> { + PKTDRPSTS_W::new(self) + } + #[doc = "Bit 12 - Babble error interrupt"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<12> { + BERR_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt"] + #[inline(always)] + #[must_use] + pub fn nak(&mut self) -> NAK_W<13> { + NAK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepint](index.html) module"] +pub struct DIEPINT_SPEC; +impl crate::RegisterSpec for DIEPINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepint::R](R) reader structure"] +impl crate::Readable for DIEPINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepint::W](W) writer structure"] +impl crate::Writable for DIEPINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPINT to value 0x80"] +impl crate::Resettable for DIEPINT_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs new file mode 100644 index 0000000..7f94dcb --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 7, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::FieldReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 19:20 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bits 19:20 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptsiz](index.html) module"] +pub struct DIEPTSIZ_SPEC; +impl crate::RegisterSpec for DIEPTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptsiz::R](R) reader structure"] +impl crate::Readable for DIEPTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptsiz::W](W) writer structure"] +impl crate::Writable for DIEPTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTSIZ to value 0"] +impl crate::Resettable for DIEPTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs new file mode 100644 index 0000000..c962826 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DTXFSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INEPTFSAV` reader - IN endpoint TxFIFO space avail"] +pub type INEPTFSAV_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - IN endpoint TxFIFO space avail"] + #[inline(always)] + pub fn ineptfsav(&self) -> INEPTFSAV_R { + INEPTFSAV_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Transmit FIFO status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtxfsts](index.html) module"] +pub struct DTXFSTS_SPEC; +impl crate::RegisterSpec for DTXFSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dtxfsts::R](R) reader structure"] +impl crate::Readable for DTXFSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DTXFSTS to value 0"] +impl crate::Resettable for DTXFSTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs new file mode 100644 index 0000000..a3a9e56 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs @@ -0,0 +1,30 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct OUT_ENDPOINT { + #[doc = "0x00 - Control"] + pub doepctl: DOEPCTL, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Interrupt"] + pub doepint: DOEPINT, + _reserved2: [u8; 0x04], + #[doc = "0x10 - Transfer size"] + pub doeptsiz: DOEPTSIZ, + #[doc = "0x14 - DMA address"] + pub doepdma: DOEPDMA, +} +#[doc = "DOEPCTL (rw) register accessor: an alias for `Reg`"] +pub type DOEPCTL = crate::Reg; +#[doc = "Control"] +pub mod doepctl; +#[doc = "DOEPINT (rw) register accessor: an alias for `Reg`"] +pub type DOEPINT = crate::Reg; +#[doc = "Interrupt"] +pub mod doepint; +#[doc = "DOEPTSIZ (rw) register accessor: an alias for `Reg`"] +pub type DOEPTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod doeptsiz; +#[doc = "DOEPDMA (rw) register accessor: an alias for `Reg`"] +pub type DOEPDMA = crate::Reg; +#[doc = "DMA address"] +pub mod doepdma; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs new file mode 100644 index 0000000..2f6baf5 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs @@ -0,0 +1,154 @@ +#[doc = "Register `DOEPCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `USBAEP` reader - USB active endpoint"] +pub type USBAEP_R = crate::BitReader; +#[doc = "Field `NAKSTS` reader - NAK status"] +pub type NAKSTS_R = crate::BitReader; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `SNPM` reader - Snoop mode"] +pub type SNPM_R = crate::BitReader; +#[doc = "Field `SNPM` writer - Snoop mode"] +pub type SNPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `Stall` reader - STALL handshake"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `Stall` writer - STALL handshake"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `CNAK` writer - Clear NAK"] +pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `SNAK` writer - Set NAK"] +pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `EPDIS` reader - Endpoint disable"] +pub type EPDIS_R = crate::BitReader; +#[doc = "Field `EPENA` writer - Endpoint enable"] +pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + pub fn usbaep(&self) -> USBAEP_R { + USBAEP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - NAK status"] + #[inline(always)] + pub fn naksts(&self) -> NAKSTS_R { + NAKSTS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Snoop mode"] + #[inline(always)] + pub fn snpm(&self) -> SNPM_R { + SNPM_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + pub fn epdis(&self) -> EPDIS_R { + EPDIS_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 20 - Snoop mode"] + #[inline(always)] + #[must_use] + pub fn snpm(&mut self) -> SNPM_W<20> { + SNPM_W::new(self) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<21> { + STALL_W::new(self) + } + #[doc = "Bit 26 - Clear NAK"] + #[inline(always)] + #[must_use] + pub fn cnak(&mut self) -> CNAK_W<26> { + CNAK_W::new(self) + } + #[doc = "Bit 27 - Set NAK"] + #[inline(always)] + #[must_use] + pub fn snak(&mut self) -> SNAK_W<27> { + SNAK_W::new(self) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + #[must_use] + pub fn epena(&mut self) -> EPENA_W<31> { + EPENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepctl](index.html) module"] +pub struct DOEPCTL_SPEC; +impl crate::RegisterSpec for DOEPCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepctl::R](R) reader structure"] +impl crate::Readable for DOEPCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepctl::W](W) writer structure"] +impl crate::Writable for DOEPCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPCTL to value 0x8000"] +impl crate::Resettable for DOEPCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs new file mode 100644 index 0000000..92089f0 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DOEPDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepdma](index.html) module"] +pub struct DOEPDMA_SPEC; +impl crate::RegisterSpec for DOEPDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepdma::R](R) reader structure"] +impl crate::Readable for DOEPDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepdma::W](W) writer structure"] +impl crate::Writable for DOEPDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPDMA to value 0"] +impl crate::Resettable for DOEPDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs new file mode 100644 index 0000000..365d667 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DOEPINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed interrupt"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed interrupt"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] +pub type EPDISD_R = crate::BitReader; +#[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] +pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `STUP` reader - SETUP phase done"] +pub type STUP_R = crate::BitReader; +#[doc = "Field `STUP` writer - SETUP phase done"] +pub type STUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `OTEPDIS` reader - OUT token received when endpoint disabled"] +pub type OTEPDIS_R = crate::BitReader; +#[doc = "Field `OTEPDIS` writer - OUT token received when endpoint disabled"] +pub type OTEPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received"] +pub type B2BSTUP_R = crate::BitReader; +#[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received"] +pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `NYET` reader - NYET interrupt"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - NYET interrupt"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + pub fn epdisd(&self) -> EPDISD_R { + EPDISD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - SETUP phase done"] + #[inline(always)] + pub fn stup(&self) -> STUP_R { + STUP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled"] + #[inline(always)] + pub fn otepdis(&self) -> OTEPDIS_R { + OTEPDIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received"] + #[inline(always)] + pub fn b2bstup(&self) -> B2BSTUP_R { + B2BSTUP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 14 - NYET interrupt"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + #[must_use] + pub fn epdisd(&mut self) -> EPDISD_W<1> { + EPDISD_W::new(self) + } + #[doc = "Bit 3 - SETUP phase done"] + #[inline(always)] + #[must_use] + pub fn stup(&mut self) -> STUP_W<3> { + STUP_W::new(self) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled"] + #[inline(always)] + #[must_use] + pub fn otepdis(&mut self) -> OTEPDIS_W<4> { + OTEPDIS_W::new(self) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received"] + #[inline(always)] + #[must_use] + pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + B2BSTUP_W::new(self) + } + #[doc = "Bit 14 - NYET interrupt"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<14> { + NYET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepint](index.html) module"] +pub struct DOEPINT_SPEC; +impl crate::RegisterSpec for DOEPINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepint::R](R) reader structure"] +impl crate::Readable for DOEPINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepint::W](W) writer structure"] +impl crate::Writable for DOEPINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPINT to value 0x80"] +impl crate::Resettable for DOEPINT_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs new file mode 100644 index 0000000..0f78e4d --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DOEPTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 7, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::BitReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPTSIZ_SPEC, bool, O>; +#[doc = "Field `STUPCNT` reader - SETUP packet count"] +pub type STUPCNT_R = crate::FieldReader; +#[doc = "Field `STUPCNT` writer - SETUP packet count"] +pub type STUPCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 19 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 29:30 - SETUP packet count"] + #[inline(always)] + pub fn stupcnt(&self) -> STUPCNT_R { + STUPCNT_R::new(((self.bits >> 29) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bit 19 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Bits 29:30 - SETUP packet count"] + #[inline(always)] + #[must_use] + pub fn stupcnt(&mut self) -> STUPCNT_W<29> { + STUPCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doeptsiz](index.html) module"] +pub struct DOEPTSIZ_SPEC; +impl crate::RegisterSpec for DOEPTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doeptsiz::R](R) reader structure"] +impl crate::Readable for DOEPTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doeptsiz::W](W) writer structure"] +impl crate::Writable for DOEPTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPTSIZ to value 0"] +impl crate::Resettable for DOEPTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global.rs b/crates/bcm2835-lpa/src/usb_otg_global.rs new file mode 100644 index 0000000..a6b35cb --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global.rs @@ -0,0 +1,198 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS control and status register"] + pub gotgctl: GOTGCTL, + #[doc = "0x04 - OTG_HS interrupt register"] + pub gotgint: GOTGINT, + #[doc = "0x08 - OTG_HS AHB configuration register"] + pub gahbcfg: GAHBCFG, + #[doc = "0x0c - OTG_HS USB configuration register"] + pub gusbcfg: GUSBCFG, + #[doc = "0x10 - OTG_HS reset register"] + pub grstctl: GRSTCTL, + #[doc = "0x14 - OTG_HS core interrupt register"] + pub gintsts: GINTSTS, + #[doc = "0x18 - OTG_HS interrupt mask register"] + pub gintmsk: GINTMSK, + _reserved_7_grxstsr: [u8; 0x04], + _reserved_8_grxstsp: [u8; 0x04], + #[doc = "0x24 - OTG_HS Receive FIFO size register"] + pub grxfsiz: GRXFSIZ, + _reserved_10_gnptxfsiz_host: [u8; 0x04], + #[doc = "0x2c - OTG_HS nonperiodic transmit FIFO/queue status register"] + pub gnptxsts: GNPTXSTS, + _reserved12: [u8; 0x08], + #[doc = "0x38 - OTG_HS general core configuration register"] + pub gccfg: GCCFG, + #[doc = "0x3c - OTG_HS core ID register"] + pub cid: CID, + #[doc = "0x40 - OTG_HS vendor ID register"] + pub vid: VID, + #[doc = "0x44 - Direction"] + pub hw_direction: HW_DIRECTION, + #[doc = "0x48 - Hardware Config 0"] + pub hw_config0: HW_CONFIG0, + _reserved17: [u8; 0xb4], + #[doc = "0x100 - OTG_HS Host periodic transmit FIFO size register"] + pub hptxfsiz: HPTXFSIZ, + #[doc = "0x104 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf1: DIEPTXF1, + #[doc = "0x108 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf2: DIEPTXF2, + _reserved20: [u8; 0x10], + #[doc = "0x11c - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf3: DIEPTXF3, + #[doc = "0x120 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf4: DIEPTXF4, + #[doc = "0x124 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf5: DIEPTXF5, + #[doc = "0x128 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf6: DIEPTXF6, + #[doc = "0x12c - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf7: DIEPTXF7, +} +impl RegisterBlock { + #[doc = "0x1c - OTG_HS Receive status debug read register (peripheral mode mode)"] + #[inline(always)] + pub const fn grxstsr_peripheral(&self) -> &GRXSTSR_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(28usize).cast() } + } + #[doc = "0x1c - OTG_HS Receive status debug read register (host mode)"] + #[inline(always)] + pub const fn grxstsr_host(&self) -> &GRXSTSR_HOST { + unsafe { &*(self as *const Self).cast::().add(28usize).cast() } + } + #[doc = "0x20 - OTG_HS status read and pop register (peripheral mode)"] + #[inline(always)] + pub const fn grxstsp_peripheral(&self) -> &GRXSTSP_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(32usize).cast() } + } + #[doc = "0x20 - OTG_HS status read and pop register (host mode)"] + #[inline(always)] + pub const fn grxstsp_host(&self) -> &GRXSTSP_HOST { + unsafe { &*(self as *const Self).cast::().add(32usize).cast() } + } + #[doc = "0x28 - Endpoint 0 transmit FIFO size (peripheral mode)"] + #[inline(always)] + pub const fn tx0fsiz_peripheral(&self) -> &TX0FSIZ_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(40usize).cast() } + } + #[doc = "0x28 - OTG_HS nonperiodic transmit FIFO size register (host mode)"] + #[inline(always)] + pub const fn gnptxfsiz_host(&self) -> &GNPTXFSIZ_HOST { + unsafe { &*(self as *const Self).cast::().add(40usize).cast() } + } +} +#[doc = "GOTGCTL (rw) register accessor: an alias for `Reg`"] +pub type GOTGCTL = crate::Reg; +#[doc = "OTG_HS control and status register"] +pub mod gotgctl; +#[doc = "GOTGINT (rw) register accessor: an alias for `Reg`"] +pub type GOTGINT = crate::Reg; +#[doc = "OTG_HS interrupt register"] +pub mod gotgint; +#[doc = "GAHBCFG (rw) register accessor: an alias for `Reg`"] +pub type GAHBCFG = crate::Reg; +#[doc = "OTG_HS AHB configuration register"] +pub mod gahbcfg; +#[doc = "GUSBCFG (rw) register accessor: an alias for `Reg`"] +pub type GUSBCFG = crate::Reg; +#[doc = "OTG_HS USB configuration register"] +pub mod gusbcfg; +#[doc = "GRSTCTL (rw) register accessor: an alias for `Reg`"] +pub type GRSTCTL = crate::Reg; +#[doc = "OTG_HS reset register"] +pub mod grstctl; +#[doc = "GINTSTS (rw) register accessor: an alias for `Reg`"] +pub type GINTSTS = crate::Reg; +#[doc = "OTG_HS core interrupt register"] +pub mod gintsts; +#[doc = "GINTMSK (rw) register accessor: an alias for `Reg`"] +pub type GINTMSK = crate::Reg; +#[doc = "OTG_HS interrupt mask register"] +pub mod gintmsk; +#[doc = "GRXSTSR_Host (r) register accessor: an alias for `Reg`"] +pub type GRXSTSR_HOST = crate::Reg; +#[doc = "OTG_HS Receive status debug read register (host mode)"] +pub mod grxstsr_host; +#[doc = "GRXSTSP_Host (r) register accessor: an alias for `Reg`"] +pub type GRXSTSP_HOST = crate::Reg; +#[doc = "OTG_HS status read and pop register (host mode)"] +pub mod grxstsp_host; +#[doc = "GRXFSIZ (rw) register accessor: an alias for `Reg`"] +pub type GRXFSIZ = crate::Reg; +#[doc = "OTG_HS Receive FIFO size register"] +pub mod grxfsiz; +#[doc = "GNPTXFSIZ_Host (rw) register accessor: an alias for `Reg`"] +pub type GNPTXFSIZ_HOST = crate::Reg; +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)"] +pub mod gnptxfsiz_host; +#[doc = "TX0FSIZ_Peripheral (rw) register accessor: an alias for `Reg`"] +pub type TX0FSIZ_PERIPHERAL = crate::Reg; +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)"] +pub mod tx0fsiz_peripheral; +#[doc = "GNPTXSTS (r) register accessor: an alias for `Reg`"] +pub type GNPTXSTS = crate::Reg; +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register"] +pub mod gnptxsts; +#[doc = "GCCFG (rw) register accessor: an alias for `Reg`"] +pub type GCCFG = crate::Reg; +#[doc = "OTG_HS general core configuration register"] +pub mod gccfg; +#[doc = "CID (rw) register accessor: an alias for `Reg`"] +pub type CID = crate::Reg; +#[doc = "OTG_HS core ID register"] +pub mod cid; +#[doc = "VID (r) register accessor: an alias for `Reg`"] +pub type VID = crate::Reg; +#[doc = "OTG_HS vendor ID register"] +pub mod vid; +#[doc = "HW_DIRECTION (r) register accessor: an alias for `Reg`"] +pub type HW_DIRECTION = crate::Reg; +#[doc = "Direction"] +pub mod hw_direction; +#[doc = "HW_CONFIG0 (r) register accessor: an alias for `Reg`"] +pub type HW_CONFIG0 = crate::Reg; +#[doc = "Hardware Config 0"] +pub mod hw_config0; +#[doc = "HPTXFSIZ (rw) register accessor: an alias for `Reg`"] +pub type HPTXFSIZ = crate::Reg; +#[doc = "OTG_HS Host periodic transmit FIFO size register"] +pub mod hptxfsiz; +#[doc = "DIEPTXF1 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF1 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf1; +#[doc = "DIEPTXF2 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF2 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf2; +#[doc = "DIEPTXF3 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF3 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf3; +#[doc = "DIEPTXF4 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF4 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf4; +#[doc = "DIEPTXF5 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF5 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf5; +#[doc = "DIEPTXF6 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF6 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf6; +#[doc = "DIEPTXF7 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF7 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf7; +#[doc = "GRXSTSR_Peripheral (r) register accessor: an alias for `Reg`"] +pub type GRXSTSR_PERIPHERAL = crate::Reg; +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)"] +pub mod grxstsr_peripheral; +#[doc = "GRXSTSP_Peripheral (r) register accessor: an alias for `Reg`"] +pub type GRXSTSP_PERIPHERAL = crate::Reg; +#[doc = "OTG_HS status read and pop register (peripheral mode)"] +pub mod grxstsp_peripheral; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/cid.rs b/crates/bcm2835-lpa/src/usb_otg_global/cid.rs new file mode 100644 index 0000000..5a8ef55 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/cid.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRODUCT_ID` reader - Product ID field"] +pub type PRODUCT_ID_R = crate::FieldReader; +#[doc = "Field `PRODUCT_ID` writer - Product ID field"] +pub type PRODUCT_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CID_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Product ID field"] + #[inline(always)] + pub fn product_id(&self) -> PRODUCT_ID_R { + PRODUCT_ID_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Product ID field"] + #[inline(always)] + #[must_use] + pub fn product_id(&mut self) -> PRODUCT_ID_W<0> { + PRODUCT_ID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS core ID register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +pub struct CID_SPEC; +impl crate::RegisterSpec for CID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid::R](R) reader structure"] +impl crate::Readable for CID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +impl crate::Writable for CID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CID to value 0x1200"] +impl crate::Resettable for CID_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs new file mode 100644 index 0000000..b79803c --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](index.html) module"] +pub struct DIEPTXF1_SPEC; +impl crate::RegisterSpec for DIEPTXF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf1::R](R) reader structure"] +impl crate::Readable for DIEPTXF1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf1::W](W) writer structure"] +impl crate::Writable for DIEPTXF1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF1 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF1_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs new file mode 100644 index 0000000..cdf9d1b --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](index.html) module"] +pub struct DIEPTXF2_SPEC; +impl crate::RegisterSpec for DIEPTXF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf2::R](R) reader structure"] +impl crate::Readable for DIEPTXF2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf2::W](W) writer structure"] +impl crate::Writable for DIEPTXF2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF2 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF2_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs new file mode 100644 index 0000000..8eaba75 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](index.html) module"] +pub struct DIEPTXF3_SPEC; +impl crate::RegisterSpec for DIEPTXF3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf3::R](R) reader structure"] +impl crate::Readable for DIEPTXF3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf3::W](W) writer structure"] +impl crate::Writable for DIEPTXF3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF3 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF3_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs new file mode 100644 index 0000000..6b30646 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](index.html) module"] +pub struct DIEPTXF4_SPEC; +impl crate::RegisterSpec for DIEPTXF4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf4::R](R) reader structure"] +impl crate::Readable for DIEPTXF4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf4::W](W) writer structure"] +impl crate::Writable for DIEPTXF4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF4 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF4_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs new file mode 100644 index 0000000..e2b7d98 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](index.html) module"] +pub struct DIEPTXF5_SPEC; +impl crate::RegisterSpec for DIEPTXF5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf5::R](R) reader structure"] +impl crate::Readable for DIEPTXF5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf5::W](W) writer structure"] +impl crate::Writable for DIEPTXF5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF5 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF5_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs new file mode 100644 index 0000000..da38751 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](index.html) module"] +pub struct DIEPTXF6_SPEC; +impl crate::RegisterSpec for DIEPTXF6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf6::R](R) reader structure"] +impl crate::Readable for DIEPTXF6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf6::W](W) writer structure"] +impl crate::Writable for DIEPTXF6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF6 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF6_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs new file mode 100644 index 0000000..811d528 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf7](index.html) module"] +pub struct DIEPTXF7_SPEC; +impl crate::RegisterSpec for DIEPTXF7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf7::R](R) reader structure"] +impl crate::Readable for DIEPTXF7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf7::W](W) writer structure"] +impl crate::Writable for DIEPTXF7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF7 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF7_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs b/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs new file mode 100644 index 0000000..987d389 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs @@ -0,0 +1,230 @@ +#[doc = "Register `GAHBCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAHBCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GINT` reader - Global interrupt mask"] +pub type GINT_R = crate::BitReader; +#[doc = "Field `GINT` writer - Global interrupt mask"] +pub type GINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `AXI_BURST` reader - Maximum AXI burst length"] +pub type AXI_BURST_R = crate::FieldReader; +#[doc = "Maximum AXI burst length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BURST_A { + #[doc = "0: `0`"] + _4 = 0, + #[doc = "1: `1`"] + _3 = 1, + #[doc = "2: `10`"] + _2 = 2, + #[doc = "3: `11`"] + _1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BURST_A) -> Self { + variant as _ + } +} +impl AXI_BURST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BURST_A { + match self.bits { + 0 => BURST_A::_4, + 1 => BURST_A::_3, + 2 => BURST_A::_2, + 3 => BURST_A::_1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == BURST_A::_4 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + *self == BURST_A::_3 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == BURST_A::_2 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == BURST_A::_1 + } +} +#[doc = "Field `AXI_BURST` writer - Maximum AXI burst length"] +pub type AXI_BURST_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GAHBCFG_SPEC, u8, BURST_A, 2, O>; +impl<'a, const O: u8> AXI_BURST_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(BURST_A::_4) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(BURST_A::_3) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(BURST_A::_2) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(BURST_A::_1) + } +} +#[doc = "Field `AXI_WAIT` reader - Wait for all AXI writes before signaling DMA"] +pub type AXI_WAIT_R = crate::BitReader; +#[doc = "Field `AXI_WAIT` writer - Wait for all AXI writes before signaling DMA"] +pub type AXI_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - DMA enable"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - DMA enable"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `TXFELVL` reader - TxFIFO empty level"] +pub type TXFELVL_R = crate::BitReader; +#[doc = "Field `TXFELVL` writer - TxFIFO empty level"] +pub type TXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `PTXFELVL` reader - Periodic TxFIFO empty level"] +pub type PTXFELVL_R = crate::BitReader; +#[doc = "Field `PTXFELVL` writer - Periodic TxFIFO empty level"] +pub type PTXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Global interrupt mask"] + #[inline(always)] + pub fn gint(&self) -> GINT_R { + GINT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Maximum AXI burst length"] + #[inline(always)] + pub fn axi_burst(&self) -> AXI_BURST_R { + AXI_BURST_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] + #[inline(always)] + pub fn axi_wait(&self) -> AXI_WAIT_R { + AXI_WAIT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DMA enable"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - TxFIFO empty level"] + #[inline(always)] + pub fn txfelvl(&self) -> TXFELVL_R { + TXFELVL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Periodic TxFIFO empty level"] + #[inline(always)] + pub fn ptxfelvl(&self) -> PTXFELVL_R { + PTXFELVL_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Global interrupt mask"] + #[inline(always)] + #[must_use] + pub fn gint(&mut self) -> GINT_W<0> { + GINT_W::new(self) + } + #[doc = "Bits 1:2 - Maximum AXI burst length"] + #[inline(always)] + #[must_use] + pub fn axi_burst(&mut self) -> AXI_BURST_W<1> { + AXI_BURST_W::new(self) + } + #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] + #[inline(always)] + #[must_use] + pub fn axi_wait(&mut self) -> AXI_WAIT_W<4> { + AXI_WAIT_W::new(self) + } + #[doc = "Bit 5 - DMA enable"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<5> { + DMAEN_W::new(self) + } + #[doc = "Bit 7 - TxFIFO empty level"] + #[inline(always)] + #[must_use] + pub fn txfelvl(&mut self) -> TXFELVL_W<7> { + TXFELVL_W::new(self) + } + #[doc = "Bit 8 - Periodic TxFIFO empty level"] + #[inline(always)] + #[must_use] + pub fn ptxfelvl(&mut self) -> PTXFELVL_W<8> { + PTXFELVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS AHB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](index.html) module"] +pub struct GAHBCFG_SPEC; +impl crate::RegisterSpec for GAHBCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gahbcfg::R](R) reader structure"] +impl crate::Readable for GAHBCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gahbcfg::W](W) writer structure"] +impl crate::Writable for GAHBCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAHBCFG to value 0"] +impl crate::Resettable for GAHBCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs b/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs new file mode 100644 index 0000000..4dbbf5c --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs @@ -0,0 +1,155 @@ +#[doc = "Register `GCCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GCCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWRDWN` reader - Power down"] +pub type PWRDWN_R = crate::BitReader; +#[doc = "Field `PWRDWN` writer - Power down"] +pub type PWRDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `I2CPADEN` reader - Enable I2C bus connection for the external I2C PHY interface"] +pub type I2CPADEN_R = crate::BitReader; +#[doc = "Field `I2CPADEN` writer - Enable I2C bus connection for the external I2C PHY interface"] +pub type I2CPADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `VBUSASEN` reader - Enable the VBUS sensing device"] +pub type VBUSASEN_R = crate::BitReader; +#[doc = "Field `VBUSASEN` writer - Enable the VBUS sensing device"] +pub type VBUSASEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `VBUSBSEN` reader - Enable the VBUS sensing device"] +pub type VBUSBSEN_R = crate::BitReader; +#[doc = "Field `VBUSBSEN` writer - Enable the VBUS sensing device"] +pub type VBUSBSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `SOFOUTEN` reader - SOF output enable"] +pub type SOFOUTEN_R = crate::BitReader; +#[doc = "Field `SOFOUTEN` writer - SOF output enable"] +pub type SOFOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `NOVBUSSENS` reader - VBUS sensing disable option"] +pub type NOVBUSSENS_R = crate::BitReader; +#[doc = "Field `NOVBUSSENS` writer - VBUS sensing disable option"] +pub type NOVBUSSENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +impl R { + #[doc = "Bit 16 - Power down"] + #[inline(always)] + pub fn pwrdwn(&self) -> PWRDWN_R { + PWRDWN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] + #[inline(always)] + pub fn i2cpaden(&self) -> I2CPADEN_R { + I2CPADEN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable the VBUS sensing device"] + #[inline(always)] + pub fn vbusasen(&self) -> VBUSASEN_R { + VBUSASEN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable the VBUS sensing device"] + #[inline(always)] + pub fn vbusbsen(&self) -> VBUSBSEN_R { + VBUSBSEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - SOF output enable"] + #[inline(always)] + pub fn sofouten(&self) -> SOFOUTEN_R { + SOFOUTEN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - VBUS sensing disable option"] + #[inline(always)] + pub fn novbussens(&self) -> NOVBUSSENS_R { + NOVBUSSENS_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Power down"] + #[inline(always)] + #[must_use] + pub fn pwrdwn(&mut self) -> PWRDWN_W<16> { + PWRDWN_W::new(self) + } + #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] + #[inline(always)] + #[must_use] + pub fn i2cpaden(&mut self) -> I2CPADEN_W<17> { + I2CPADEN_W::new(self) + } + #[doc = "Bit 18 - Enable the VBUS sensing device"] + #[inline(always)] + #[must_use] + pub fn vbusasen(&mut self) -> VBUSASEN_W<18> { + VBUSASEN_W::new(self) + } + #[doc = "Bit 19 - Enable the VBUS sensing device"] + #[inline(always)] + #[must_use] + pub fn vbusbsen(&mut self) -> VBUSBSEN_W<19> { + VBUSBSEN_W::new(self) + } + #[doc = "Bit 20 - SOF output enable"] + #[inline(always)] + #[must_use] + pub fn sofouten(&mut self) -> SOFOUTEN_W<20> { + SOFOUTEN_W::new(self) + } + #[doc = "Bit 21 - VBUS sensing disable option"] + #[inline(always)] + #[must_use] + pub fn novbussens(&mut self) -> NOVBUSSENS_W<21> { + NOVBUSSENS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS general core configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gccfg](index.html) module"] +pub struct GCCFG_SPEC; +impl crate::RegisterSpec for GCCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gccfg::R](R) reader structure"] +impl crate::Readable for GCCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gccfg::W](W) writer structure"] +impl crate::Writable for GCCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GCCFG to value 0"] +impl crate::Resettable for GCCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs new file mode 100644 index 0000000..d3fdb2d --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs @@ -0,0 +1,447 @@ +#[doc = "Register `GINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MMISM` reader - Mode mismatch interrupt mask"] +pub type MMISM_R = crate::BitReader; +#[doc = "Field `MMISM` writer - Mode mismatch interrupt mask"] +pub type MMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `OTGINT` reader - OTG interrupt mask"] +pub type OTGINT_R = crate::BitReader; +#[doc = "Field `OTGINT` writer - OTG interrupt mask"] +pub type OTGINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `SOFM` reader - Start of frame mask"] +pub type SOFM_R = crate::BitReader; +#[doc = "Field `SOFM` writer - Start of frame mask"] +pub type SOFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `RXFLVLM` reader - Receive FIFO nonempty mask"] +pub type RXFLVLM_R = crate::BitReader; +#[doc = "Field `RXFLVLM` writer - Receive FIFO nonempty mask"] +pub type RXFLVLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `NPTXFEM` reader - Nonperiodic TxFIFO empty mask"] +pub type NPTXFEM_R = crate::BitReader; +#[doc = "Field `NPTXFEM` writer - Nonperiodic TxFIFO empty mask"] +pub type NPTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `GINAKEFFM` reader - Global nonperiodic IN NAK effective mask"] +pub type GINAKEFFM_R = crate::BitReader; +#[doc = "Field `GINAKEFFM` writer - Global nonperiodic IN NAK effective mask"] +pub type GINAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `GONAKEFFM` reader - Global OUT NAK effective mask"] +pub type GONAKEFFM_R = crate::BitReader; +#[doc = "Field `GONAKEFFM` writer - Global OUT NAK effective mask"] +pub type GONAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ESUSPM` reader - Early suspend mask"] +pub type ESUSPM_R = crate::BitReader; +#[doc = "Field `ESUSPM` writer - Early suspend mask"] +pub type ESUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `USBSUSPM` reader - USB suspend mask"] +pub type USBSUSPM_R = crate::BitReader; +#[doc = "Field `USBSUSPM` writer - USB suspend mask"] +pub type USBSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `USBRST` reader - USB reset mask"] +pub type USBRST_R = crate::BitReader; +#[doc = "Field `USBRST` writer - USB reset mask"] +pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ENUMDNEM` reader - Enumeration done mask"] +pub type ENUMDNEM_R = crate::BitReader; +#[doc = "Field `ENUMDNEM` writer - Enumeration done mask"] +pub type ENUMDNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ISOODRPM` reader - Isochronous OUT packet dropped interrupt mask"] +pub type ISOODRPM_R = crate::BitReader; +#[doc = "Field `ISOODRPM` writer - Isochronous OUT packet dropped interrupt mask"] +pub type ISOODRPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `EOPFM` reader - End of periodic frame interrupt mask"] +pub type EOPFM_R = crate::BitReader; +#[doc = "Field `EOPFM` writer - End of periodic frame interrupt mask"] +pub type EOPFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `EPMISM` reader - Endpoint mismatch interrupt mask"] +pub type EPMISM_R = crate::BitReader; +#[doc = "Field `EPMISM` writer - Endpoint mismatch interrupt mask"] +pub type EPMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `IEPINT` reader - IN endpoints interrupt mask"] +pub type IEPINT_R = crate::BitReader; +#[doc = "Field `IEPINT` writer - IN endpoints interrupt mask"] +pub type IEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `OEPINT` reader - OUT endpoints interrupt mask"] +pub type OEPINT_R = crate::BitReader; +#[doc = "Field `OEPINT` writer - OUT endpoints interrupt mask"] +pub type OEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `IISOIXFRM` reader - Incomplete isochronous IN transfer mask"] +pub type IISOIXFRM_R = crate::BitReader; +#[doc = "Field `IISOIXFRM` writer - Incomplete isochronous IN transfer mask"] +pub type IISOIXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PXFRM_IISOOXFRM` reader - Incomplete periodic transfer mask"] +pub type PXFRM_IISOOXFRM_R = crate::BitReader; +#[doc = "Field `PXFRM_IISOOXFRM` writer - Incomplete periodic transfer mask"] +pub type PXFRM_IISOOXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `FSUSPM` reader - Data fetch suspended mask"] +pub type FSUSPM_R = crate::BitReader; +#[doc = "Field `FSUSPM` writer - Data fetch suspended mask"] +pub type FSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PRTIM` reader - Host port interrupt mask"] +pub type PRTIM_R = crate::BitReader; +#[doc = "Field `HCIM` reader - Host channels interrupt mask"] +pub type HCIM_R = crate::BitReader; +#[doc = "Field `HCIM` writer - Host channels interrupt mask"] +pub type HCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PTXFEM` reader - Periodic TxFIFO empty mask"] +pub type PTXFEM_R = crate::BitReader; +#[doc = "Field `PTXFEM` writer - Periodic TxFIFO empty mask"] +pub type PTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `CIDSCHGM` reader - Connector ID status change mask"] +pub type CIDSCHGM_R = crate::BitReader; +#[doc = "Field `CIDSCHGM` writer - Connector ID status change mask"] +pub type CIDSCHGM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `DISCINT` reader - Disconnect detected interrupt mask"] +pub type DISCINT_R = crate::BitReader; +#[doc = "Field `DISCINT` writer - Disconnect detected interrupt mask"] +pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `SRQIM` reader - Session request/new session detected interrupt mask"] +pub type SRQIM_R = crate::BitReader; +#[doc = "Field `SRQIM` writer - Session request/new session detected interrupt mask"] +pub type SRQIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `WUIM` reader - Resume/remote wakeup detected interrupt mask"] +pub type WUIM_R = crate::BitReader; +#[doc = "Field `WUIM` writer - Resume/remote wakeup detected interrupt mask"] +pub type WUIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Mode mismatch interrupt mask"] + #[inline(always)] + pub fn mmism(&self) -> MMISM_R { + MMISM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OTG interrupt mask"] + #[inline(always)] + pub fn otgint(&self) -> OTGINT_R { + OTGINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start of frame mask"] + #[inline(always)] + pub fn sofm(&self) -> SOFM_R { + SOFM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO nonempty mask"] + #[inline(always)] + pub fn rxflvlm(&self) -> RXFLVLM_R { + RXFLVLM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] + #[inline(always)] + pub fn nptxfem(&self) -> NPTXFEM_R { + NPTXFEM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] + #[inline(always)] + pub fn ginakeffm(&self) -> GINAKEFFM_R { + GINAKEFFM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global OUT NAK effective mask"] + #[inline(always)] + pub fn gonakeffm(&self) -> GONAKEFFM_R { + GONAKEFFM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Early suspend mask"] + #[inline(always)] + pub fn esuspm(&self) -> ESUSPM_R { + ESUSPM_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB suspend mask"] + #[inline(always)] + pub fn usbsuspm(&self) -> USBSUSPM_R { + USBSUSPM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - USB reset mask"] + #[inline(always)] + pub fn usbrst(&self) -> USBRST_R { + USBRST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enumeration done mask"] + #[inline(always)] + pub fn enumdnem(&self) -> ENUMDNEM_R { + ENUMDNEM_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] + #[inline(always)] + pub fn isoodrpm(&self) -> ISOODRPM_R { + ISOODRPM_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - End of periodic frame interrupt mask"] + #[inline(always)] + pub fn eopfm(&self) -> EOPFM_R { + EOPFM_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] + #[inline(always)] + pub fn epmism(&self) -> EPMISM_R { + EPMISM_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - IN endpoints interrupt mask"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OUT endpoints interrupt mask"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] + #[inline(always)] + pub fn iisoixfrm(&self) -> IISOIXFRM_R { + IISOIXFRM_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Incomplete periodic transfer mask"] + #[inline(always)] + pub fn pxfrm_iisooxfrm(&self) -> PXFRM_IISOOXFRM_R { + PXFRM_IISOOXFRM_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data fetch suspended mask"] + #[inline(always)] + pub fn fsuspm(&self) -> FSUSPM_R { + FSUSPM_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Host port interrupt mask"] + #[inline(always)] + pub fn prtim(&self) -> PRTIM_R { + PRTIM_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Host channels interrupt mask"] + #[inline(always)] + pub fn hcim(&self) -> HCIM_R { + HCIM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Periodic TxFIFO empty mask"] + #[inline(always)] + pub fn ptxfem(&self) -> PTXFEM_R { + PTXFEM_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Connector ID status change mask"] + #[inline(always)] + pub fn cidschgm(&self) -> CIDSCHGM_R { + CIDSCHGM_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Disconnect detected interrupt mask"] + #[inline(always)] + pub fn discint(&self) -> DISCINT_R { + DISCINT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Session request/new session detected interrupt mask"] + #[inline(always)] + pub fn srqim(&self) -> SRQIM_R { + SRQIM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] + #[inline(always)] + pub fn wuim(&self) -> WUIM_R { + WUIM_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Mode mismatch interrupt mask"] + #[inline(always)] + #[must_use] + pub fn mmism(&mut self) -> MMISM_W<1> { + MMISM_W::new(self) + } + #[doc = "Bit 2 - OTG interrupt mask"] + #[inline(always)] + #[must_use] + pub fn otgint(&mut self) -> OTGINT_W<2> { + OTGINT_W::new(self) + } + #[doc = "Bit 3 - Start of frame mask"] + #[inline(always)] + #[must_use] + pub fn sofm(&mut self) -> SOFM_W<3> { + SOFM_W::new(self) + } + #[doc = "Bit 4 - Receive FIFO nonempty mask"] + #[inline(always)] + #[must_use] + pub fn rxflvlm(&mut self) -> RXFLVLM_W<4> { + RXFLVLM_W::new(self) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn nptxfem(&mut self) -> NPTXFEM_W<5> { + NPTXFEM_W::new(self) + } + #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn ginakeffm(&mut self) -> GINAKEFFM_W<6> { + GINAKEFFM_W::new(self) + } + #[doc = "Bit 7 - Global OUT NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn gonakeffm(&mut self) -> GONAKEFFM_W<7> { + GONAKEFFM_W::new(self) + } + #[doc = "Bit 10 - Early suspend mask"] + #[inline(always)] + #[must_use] + pub fn esuspm(&mut self) -> ESUSPM_W<10> { + ESUSPM_W::new(self) + } + #[doc = "Bit 11 - USB suspend mask"] + #[inline(always)] + #[must_use] + pub fn usbsuspm(&mut self) -> USBSUSPM_W<11> { + USBSUSPM_W::new(self) + } + #[doc = "Bit 12 - USB reset mask"] + #[inline(always)] + #[must_use] + pub fn usbrst(&mut self) -> USBRST_W<12> { + USBRST_W::new(self) + } + #[doc = "Bit 13 - Enumeration done mask"] + #[inline(always)] + #[must_use] + pub fn enumdnem(&mut self) -> ENUMDNEM_W<13> { + ENUMDNEM_W::new(self) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] + #[inline(always)] + #[must_use] + pub fn isoodrpm(&mut self) -> ISOODRPM_W<14> { + ISOODRPM_W::new(self) + } + #[doc = "Bit 15 - End of periodic frame interrupt mask"] + #[inline(always)] + #[must_use] + pub fn eopfm(&mut self) -> EOPFM_W<15> { + EOPFM_W::new(self) + } + #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epmism(&mut self) -> EPMISM_W<17> { + EPMISM_W::new(self) + } + #[doc = "Bit 18 - IN endpoints interrupt mask"] + #[inline(always)] + #[must_use] + pub fn iepint(&mut self) -> IEPINT_W<18> { + IEPINT_W::new(self) + } + #[doc = "Bit 19 - OUT endpoints interrupt mask"] + #[inline(always)] + #[must_use] + pub fn oepint(&mut self) -> OEPINT_W<19> { + OEPINT_W::new(self) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] + #[inline(always)] + #[must_use] + pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<20> { + IISOIXFRM_W::new(self) + } + #[doc = "Bit 21 - Incomplete periodic transfer mask"] + #[inline(always)] + #[must_use] + pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<21> { + PXFRM_IISOOXFRM_W::new(self) + } + #[doc = "Bit 22 - Data fetch suspended mask"] + #[inline(always)] + #[must_use] + pub fn fsuspm(&mut self) -> FSUSPM_W<22> { + FSUSPM_W::new(self) + } + #[doc = "Bit 25 - Host channels interrupt mask"] + #[inline(always)] + #[must_use] + pub fn hcim(&mut self) -> HCIM_W<25> { + HCIM_W::new(self) + } + #[doc = "Bit 26 - Periodic TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ptxfem(&mut self) -> PTXFEM_W<26> { + PTXFEM_W::new(self) + } + #[doc = "Bit 28 - Connector ID status change mask"] + #[inline(always)] + #[must_use] + pub fn cidschgm(&mut self) -> CIDSCHGM_W<28> { + CIDSCHGM_W::new(self) + } + #[doc = "Bit 29 - Disconnect detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn discint(&mut self) -> DISCINT_W<29> { + DISCINT_W::new(self) + } + #[doc = "Bit 30 - Session request/new session detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn srqim(&mut self) -> SRQIM_W<30> { + SRQIM_W::new(self) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn wuim(&mut self) -> WUIM_W<31> { + WUIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](index.html) module"] +pub struct GINTMSK_SPEC; +impl crate::RegisterSpec for GINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gintmsk::R](R) reader structure"] +impl crate::Readable for GINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gintmsk::W](W) writer structure"] +impl crate::Writable for GINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GINTMSK to value 0"] +impl crate::Resettable for GINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs b/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs new file mode 100644 index 0000000..4dd3aa9 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs @@ -0,0 +1,367 @@ +#[doc = "Register `GINTSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GINTSTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMOD` reader - Current mode of operation"] +pub type CMOD_R = crate::BitReader; +#[doc = "Field `MMIS` reader - Mode mismatch interrupt"] +pub type MMIS_R = crate::BitReader; +#[doc = "Field `MMIS` writer - Mode mismatch interrupt"] +pub type MMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `OTGINT` reader - OTG interrupt"] +pub type OTGINT_R = crate::BitReader; +#[doc = "Field `SOF` reader - Start of frame"] +pub type SOF_R = crate::BitReader; +#[doc = "Field `SOF` writer - Start of frame"] +pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `RXFLVL` reader - RxFIFO nonempty"] +pub type RXFLVL_R = crate::BitReader; +#[doc = "Field `NPTXFE` reader - Nonperiodic TxFIFO empty"] +pub type NPTXFE_R = crate::BitReader; +#[doc = "Field `GINAKEFF` reader - Global IN nonperiodic NAK effective"] +pub type GINAKEFF_R = crate::BitReader; +#[doc = "Field `BOUTNAKEFF` reader - Global OUT NAK effective"] +pub type BOUTNAKEFF_R = crate::BitReader; +#[doc = "Field `ESUSP` reader - Early suspend"] +pub type ESUSP_R = crate::BitReader; +#[doc = "Field `ESUSP` writer - Early suspend"] +pub type ESUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `USBSUSP` reader - USB suspend"] +pub type USBSUSP_R = crate::BitReader; +#[doc = "Field `USBSUSP` writer - USB suspend"] +pub type USBSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `USBRST` reader - USB reset"] +pub type USBRST_R = crate::BitReader; +#[doc = "Field `USBRST` writer - USB reset"] +pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `ENUMDNE` reader - Enumeration done"] +pub type ENUMDNE_R = crate::BitReader; +#[doc = "Field `ENUMDNE` writer - Enumeration done"] +pub type ENUMDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `ISOODRP` reader - Isochronous OUT packet dropped interrupt"] +pub type ISOODRP_R = crate::BitReader; +#[doc = "Field `ISOODRP` writer - Isochronous OUT packet dropped interrupt"] +pub type ISOODRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `EOPF` reader - End of periodic frame interrupt"] +pub type EOPF_R = crate::BitReader; +#[doc = "Field `EOPF` writer - End of periodic frame interrupt"] +pub type EOPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `IEPINT` reader - IN endpoint interrupt"] +pub type IEPINT_R = crate::BitReader; +#[doc = "Field `OEPINT` reader - OUT endpoint interrupt"] +pub type OEPINT_R = crate::BitReader; +#[doc = "Field `IISOIXFR` reader - Incomplete isochronous IN transfer"] +pub type IISOIXFR_R = crate::BitReader; +#[doc = "Field `IISOIXFR` writer - Incomplete isochronous IN transfer"] +pub type IISOIXFR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `PXFR_INCOMPISOOUT` reader - Incomplete periodic transfer"] +pub type PXFR_INCOMPISOOUT_R = crate::BitReader; +#[doc = "Field `PXFR_INCOMPISOOUT` writer - Incomplete periodic transfer"] +pub type PXFR_INCOMPISOOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `DATAFSUSP` reader - Data fetch suspended"] +pub type DATAFSUSP_R = crate::BitReader; +#[doc = "Field `DATAFSUSP` writer - Data fetch suspended"] +pub type DATAFSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `HPRTINT` reader - Host port interrupt"] +pub type HPRTINT_R = crate::BitReader; +#[doc = "Field `HCINT` reader - Host channels interrupt"] +pub type HCINT_R = crate::BitReader; +#[doc = "Field `PTXFE` reader - Periodic TxFIFO empty"] +pub type PTXFE_R = crate::BitReader; +#[doc = "Field `CIDSCHG` reader - Connector ID status change"] +pub type CIDSCHG_R = crate::BitReader; +#[doc = "Field `CIDSCHG` writer - Connector ID status change"] +pub type CIDSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `DISCINT` reader - Disconnect detected interrupt"] +pub type DISCINT_R = crate::BitReader; +#[doc = "Field `DISCINT` writer - Disconnect detected interrupt"] +pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `SRQINT` reader - Session request/new session detected interrupt"] +pub type SRQINT_R = crate::BitReader; +#[doc = "Field `SRQINT` writer - Session request/new session detected interrupt"] +pub type SRQINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `WKUINT` reader - Resume/remote wakeup detected interrupt"] +pub type WKUINT_R = crate::BitReader; +#[doc = "Field `WKUINT` writer - Resume/remote wakeup detected interrupt"] +pub type WKUINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Current mode of operation"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mode mismatch interrupt"] + #[inline(always)] + pub fn mmis(&self) -> MMIS_R { + MMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OTG interrupt"] + #[inline(always)] + pub fn otgint(&self) -> OTGINT_R { + OTGINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start of frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RxFIFO nonempty"] + #[inline(always)] + pub fn rxflvl(&self) -> RXFLVL_R { + RXFLVL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty"] + #[inline(always)] + pub fn nptxfe(&self) -> NPTXFE_R { + NPTXFE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global IN nonperiodic NAK effective"] + #[inline(always)] + pub fn ginakeff(&self) -> GINAKEFF_R { + GINAKEFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global OUT NAK effective"] + #[inline(always)] + pub fn boutnakeff(&self) -> BOUTNAKEFF_R { + BOUTNAKEFF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Early suspend"] + #[inline(always)] + pub fn esusp(&self) -> ESUSP_R { + ESUSP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB suspend"] + #[inline(always)] + pub fn usbsusp(&self) -> USBSUSP_R { + USBSUSP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - USB reset"] + #[inline(always)] + pub fn usbrst(&self) -> USBRST_R { + USBRST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enumeration done"] + #[inline(always)] + pub fn enumdne(&self) -> ENUMDNE_R { + ENUMDNE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] + #[inline(always)] + pub fn isoodrp(&self) -> ISOODRP_R { + ISOODRP_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - End of periodic frame interrupt"] + #[inline(always)] + pub fn eopf(&self) -> EOPF_R { + EOPF_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 18 - IN endpoint interrupt"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OUT endpoint interrupt"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer"] + #[inline(always)] + pub fn iisoixfr(&self) -> IISOIXFR_R { + IISOIXFR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Incomplete periodic transfer"] + #[inline(always)] + pub fn pxfr_incompisoout(&self) -> PXFR_INCOMPISOOUT_R { + PXFR_INCOMPISOOUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data fetch suspended"] + #[inline(always)] + pub fn datafsusp(&self) -> DATAFSUSP_R { + DATAFSUSP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Host port interrupt"] + #[inline(always)] + pub fn hprtint(&self) -> HPRTINT_R { + HPRTINT_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Host channels interrupt"] + #[inline(always)] + pub fn hcint(&self) -> HCINT_R { + HCINT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Periodic TxFIFO empty"] + #[inline(always)] + pub fn ptxfe(&self) -> PTXFE_R { + PTXFE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Connector ID status change"] + #[inline(always)] + pub fn cidschg(&self) -> CIDSCHG_R { + CIDSCHG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Disconnect detected interrupt"] + #[inline(always)] + pub fn discint(&self) -> DISCINT_R { + DISCINT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Session request/new session detected interrupt"] + #[inline(always)] + pub fn srqint(&self) -> SRQINT_R { + SRQINT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] + #[inline(always)] + pub fn wkuint(&self) -> WKUINT_R { + WKUINT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Mode mismatch interrupt"] + #[inline(always)] + #[must_use] + pub fn mmis(&mut self) -> MMIS_W<1> { + MMIS_W::new(self) + } + #[doc = "Bit 3 - Start of frame"] + #[inline(always)] + #[must_use] + pub fn sof(&mut self) -> SOF_W<3> { + SOF_W::new(self) + } + #[doc = "Bit 10 - Early suspend"] + #[inline(always)] + #[must_use] + pub fn esusp(&mut self) -> ESUSP_W<10> { + ESUSP_W::new(self) + } + #[doc = "Bit 11 - USB suspend"] + #[inline(always)] + #[must_use] + pub fn usbsusp(&mut self) -> USBSUSP_W<11> { + USBSUSP_W::new(self) + } + #[doc = "Bit 12 - USB reset"] + #[inline(always)] + #[must_use] + pub fn usbrst(&mut self) -> USBRST_W<12> { + USBRST_W::new(self) + } + #[doc = "Bit 13 - Enumeration done"] + #[inline(always)] + #[must_use] + pub fn enumdne(&mut self) -> ENUMDNE_W<13> { + ENUMDNE_W::new(self) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] + #[inline(always)] + #[must_use] + pub fn isoodrp(&mut self) -> ISOODRP_W<14> { + ISOODRP_W::new(self) + } + #[doc = "Bit 15 - End of periodic frame interrupt"] + #[inline(always)] + #[must_use] + pub fn eopf(&mut self) -> EOPF_W<15> { + EOPF_W::new(self) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer"] + #[inline(always)] + #[must_use] + pub fn iisoixfr(&mut self) -> IISOIXFR_W<20> { + IISOIXFR_W::new(self) + } + #[doc = "Bit 21 - Incomplete periodic transfer"] + #[inline(always)] + #[must_use] + pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<21> { + PXFR_INCOMPISOOUT_W::new(self) + } + #[doc = "Bit 22 - Data fetch suspended"] + #[inline(always)] + #[must_use] + pub fn datafsusp(&mut self) -> DATAFSUSP_W<22> { + DATAFSUSP_W::new(self) + } + #[doc = "Bit 28 - Connector ID status change"] + #[inline(always)] + #[must_use] + pub fn cidschg(&mut self) -> CIDSCHG_W<28> { + CIDSCHG_W::new(self) + } + #[doc = "Bit 29 - Disconnect detected interrupt"] + #[inline(always)] + #[must_use] + pub fn discint(&mut self) -> DISCINT_W<29> { + DISCINT_W::new(self) + } + #[doc = "Bit 30 - Session request/new session detected interrupt"] + #[inline(always)] + #[must_use] + pub fn srqint(&mut self) -> SRQINT_W<30> { + SRQINT_W::new(self) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] + #[inline(always)] + #[must_use] + pub fn wkuint(&mut self) -> WKUINT_W<31> { + WKUINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS core interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](index.html) module"] +pub struct GINTSTS_SPEC; +impl crate::RegisterSpec for GINTSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gintsts::R](R) reader structure"] +impl crate::Readable for GINTSTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gintsts::W](W) writer structure"] +impl crate::Writable for GINTSTS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GINTSTS to value 0x0400_0020"] +impl crate::Resettable for GINTSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0020; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs b/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs new file mode 100644 index 0000000..89a5540 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs @@ -0,0 +1,97 @@ +#[doc = "Register `GNPTXFSIZ_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GNPTXFSIZ_Host` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NPTXFSA` reader - Nonperiodic transmit RAM start address"] +pub type NPTXFSA_R = crate::FieldReader; +#[doc = "Field `NPTXFSA` writer - Nonperiodic transmit RAM start address"] +pub type NPTXFSA_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +#[doc = "Field `NPTXFD` reader - Nonperiodic TxFIFO depth"] +pub type NPTXFD_R = crate::FieldReader; +#[doc = "Field `NPTXFD` writer - Nonperiodic TxFIFO depth"] +pub type NPTXFD_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] + #[inline(always)] + pub fn nptxfsa(&self) -> NPTXFSA_R { + NPTXFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] + #[inline(always)] + pub fn nptxfd(&self) -> NPTXFD_R { + NPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn nptxfsa(&mut self) -> NPTXFSA_W<0> { + NPTXFSA_W::new(self) + } + #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn nptxfd(&mut self) -> NPTXFD_W<16> { + NPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz_host](index.html) module"] +pub struct GNPTXFSIZ_HOST_SPEC; +impl crate::RegisterSpec for GNPTXFSIZ_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gnptxfsiz_host::R](R) reader structure"] +impl crate::Readable for GNPTXFSIZ_HOST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gnptxfsiz_host::W](W) writer structure"] +impl crate::Writable for GNPTXFSIZ_HOST_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GNPTXFSIZ_Host to value 0x0200"] +impl crate::Resettable for GNPTXFSIZ_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs b/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs new file mode 100644 index 0000000..65ffd12 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs @@ -0,0 +1,51 @@ +#[doc = "Register `GNPTXSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `NPTXFSAV` reader - Nonperiodic TxFIFO space available"] +pub type NPTXFSAV_R = crate::FieldReader; +#[doc = "Field `NPTQXSAV` reader - Nonperiodic transmit request queue space available"] +pub type NPTQXSAV_R = crate::FieldReader; +#[doc = "Field `NPTXQTOP` reader - Top of the nonperiodic transmit request queue"] +pub type NPTXQTOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Nonperiodic TxFIFO space available"] + #[inline(always)] + pub fn nptxfsav(&self) -> NPTXFSAV_R { + NPTXFSAV_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Nonperiodic transmit request queue space available"] + #[inline(always)] + pub fn nptqxsav(&self) -> NPTQXSAV_R { + NPTQXSAV_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:30 - Top of the nonperiodic transmit request queue"] + #[inline(always)] + pub fn nptxqtop(&self) -> NPTXQTOP_R { + NPTXQTOP_R::new(((self.bits >> 24) & 0x7f) as u8) + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](index.html) module"] +pub struct GNPTXSTS_SPEC; +impl crate::RegisterSpec for GNPTXSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gnptxsts::R](R) reader structure"] +impl crate::Readable for GNPTXSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GNPTXSTS to value 0x0008_0200"] +impl crate::Resettable for GNPTXSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0200; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs b/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs new file mode 100644 index 0000000..6576636 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs @@ -0,0 +1,167 @@ +#[doc = "Register `GOTGCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GOTGCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRQSCS` reader - Session request success"] +pub type SRQSCS_R = crate::BitReader; +#[doc = "Field `SRQ` reader - Session request"] +pub type SRQ_R = crate::BitReader; +#[doc = "Field `SRQ` writer - Session request"] +pub type SRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `HNGSCS` reader - Host negotiation success"] +pub type HNGSCS_R = crate::BitReader; +#[doc = "Field `HNPRQ` reader - HNP request"] +pub type HNPRQ_R = crate::BitReader; +#[doc = "Field `HNPRQ` writer - HNP request"] +pub type HNPRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `HSHNPEN` reader - Host set HNP enable"] +pub type HSHNPEN_R = crate::BitReader; +#[doc = "Field `HSHNPEN` writer - Host set HNP enable"] +pub type HSHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `DHNPEN` reader - Device HNP enabled"] +pub type DHNPEN_R = crate::BitReader; +#[doc = "Field `DHNPEN` writer - Device HNP enabled"] +pub type DHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `CIDSTS` reader - Connector ID status"] +pub type CIDSTS_R = crate::BitReader; +#[doc = "Field `DBCT` reader - Long/short debounce time"] +pub type DBCT_R = crate::BitReader; +#[doc = "Field `ASVLD` reader - A-session valid"] +pub type ASVLD_R = crate::BitReader; +#[doc = "Field `BSVLD` reader - B-session valid"] +pub type BSVLD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Session request success"] + #[inline(always)] + pub fn srqscs(&self) -> SRQSCS_R { + SRQSCS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Session request"] + #[inline(always)] + pub fn srq(&self) -> SRQ_R { + SRQ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Host negotiation success"] + #[inline(always)] + pub fn hngscs(&self) -> HNGSCS_R { + HNGSCS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HNP request"] + #[inline(always)] + pub fn hnprq(&self) -> HNPRQ_R { + HNPRQ_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Host set HNP enable"] + #[inline(always)] + pub fn hshnpen(&self) -> HSHNPEN_R { + HSHNPEN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Device HNP enabled"] + #[inline(always)] + pub fn dhnpen(&self) -> DHNPEN_R { + DHNPEN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Connector ID status"] + #[inline(always)] + pub fn cidsts(&self) -> CIDSTS_R { + CIDSTS_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Long/short debounce time"] + #[inline(always)] + pub fn dbct(&self) -> DBCT_R { + DBCT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - A-session valid"] + #[inline(always)] + pub fn asvld(&self) -> ASVLD_R { + ASVLD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - B-session valid"] + #[inline(always)] + pub fn bsvld(&self) -> BSVLD_R { + BSVLD_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Session request"] + #[inline(always)] + #[must_use] + pub fn srq(&mut self) -> SRQ_W<1> { + SRQ_W::new(self) + } + #[doc = "Bit 9 - HNP request"] + #[inline(always)] + #[must_use] + pub fn hnprq(&mut self) -> HNPRQ_W<9> { + HNPRQ_W::new(self) + } + #[doc = "Bit 10 - Host set HNP enable"] + #[inline(always)] + #[must_use] + pub fn hshnpen(&mut self) -> HSHNPEN_W<10> { + HSHNPEN_W::new(self) + } + #[doc = "Bit 11 - Device HNP enabled"] + #[inline(always)] + #[must_use] + pub fn dhnpen(&mut self) -> DHNPEN_W<11> { + DHNPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](index.html) module"] +pub struct GOTGCTL_SPEC; +impl crate::RegisterSpec for GOTGCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gotgctl::R](R) reader structure"] +impl crate::Readable for GOTGCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gotgctl::W](W) writer structure"] +impl crate::Writable for GOTGCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOTGCTL to value 0x0800"] +impl crate::Resettable for GOTGCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs b/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs new file mode 100644 index 0000000..b2c3ab9 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs @@ -0,0 +1,155 @@ +#[doc = "Register `GOTGINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GOTGINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEDET` reader - Session end detected"] +pub type SEDET_R = crate::BitReader; +#[doc = "Field `SEDET` writer - Session end detected"] +pub type SEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `SRSSCHG` reader - Session request success status change"] +pub type SRSSCHG_R = crate::BitReader; +#[doc = "Field `SRSSCHG` writer - Session request success status change"] +pub type SRSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `HNSSCHG` reader - Host negotiation success status change"] +pub type HNSSCHG_R = crate::BitReader; +#[doc = "Field `HNSSCHG` writer - Host negotiation success status change"] +pub type HNSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `HNGDET` reader - Host negotiation detected"] +pub type HNGDET_R = crate::BitReader; +#[doc = "Field `HNGDET` writer - Host negotiation detected"] +pub type HNGDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `ADTOCHG` reader - A-device timeout change"] +pub type ADTOCHG_R = crate::BitReader; +#[doc = "Field `ADTOCHG` writer - A-device timeout change"] +pub type ADTOCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `DBCDNE` reader - Debounce done"] +pub type DBCDNE_R = crate::BitReader; +#[doc = "Field `DBCDNE` writer - Debounce done"] +pub type DBCDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 2 - Session end detected"] + #[inline(always)] + pub fn sedet(&self) -> SEDET_R { + SEDET_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Session request success status change"] + #[inline(always)] + pub fn srsschg(&self) -> SRSSCHG_R { + SRSSCHG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Host negotiation success status change"] + #[inline(always)] + pub fn hnsschg(&self) -> HNSSCHG_R { + HNSSCHG_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Host negotiation detected"] + #[inline(always)] + pub fn hngdet(&self) -> HNGDET_R { + HNGDET_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - A-device timeout change"] + #[inline(always)] + pub fn adtochg(&self) -> ADTOCHG_R { + ADTOCHG_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Debounce done"] + #[inline(always)] + pub fn dbcdne(&self) -> DBCDNE_R { + DBCDNE_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Session end detected"] + #[inline(always)] + #[must_use] + pub fn sedet(&mut self) -> SEDET_W<2> { + SEDET_W::new(self) + } + #[doc = "Bit 8 - Session request success status change"] + #[inline(always)] + #[must_use] + pub fn srsschg(&mut self) -> SRSSCHG_W<8> { + SRSSCHG_W::new(self) + } + #[doc = "Bit 9 - Host negotiation success status change"] + #[inline(always)] + #[must_use] + pub fn hnsschg(&mut self) -> HNSSCHG_W<9> { + HNSSCHG_W::new(self) + } + #[doc = "Bit 17 - Host negotiation detected"] + #[inline(always)] + #[must_use] + pub fn hngdet(&mut self) -> HNGDET_W<17> { + HNGDET_W::new(self) + } + #[doc = "Bit 18 - A-device timeout change"] + #[inline(always)] + #[must_use] + pub fn adtochg(&mut self) -> ADTOCHG_W<18> { + ADTOCHG_W::new(self) + } + #[doc = "Bit 19 - Debounce done"] + #[inline(always)] + #[must_use] + pub fn dbcdne(&mut self) -> DBCDNE_W<19> { + DBCDNE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](index.html) module"] +pub struct GOTGINT_SPEC; +impl crate::RegisterSpec for GOTGINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gotgint::R](R) reader structure"] +impl crate::Readable for GOTGINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gotgint::W](W) writer structure"] +impl crate::Writable for GOTGINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOTGINT to value 0"] +impl crate::Resettable for GOTGINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs b/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs new file mode 100644 index 0000000..c3f83dc --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs @@ -0,0 +1,169 @@ +#[doc = "Register `GRSTCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GRSTCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CSRST` reader - Core soft reset"] +pub type CSRST_R = crate::BitReader; +#[doc = "Field `CSRST` writer - Core soft reset"] +pub type CSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `HSRST` reader - HCLK soft reset"] +pub type HSRST_R = crate::BitReader; +#[doc = "Field `HSRST` writer - HCLK soft reset"] +pub type HSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `FCRST` reader - Host frame counter reset"] +pub type FCRST_R = crate::BitReader; +#[doc = "Field `FCRST` writer - Host frame counter reset"] +pub type FCRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `RXFFLSH` reader - RxFIFO flush"] +pub type RXFFLSH_R = crate::BitReader; +#[doc = "Field `RXFFLSH` writer - RxFIFO flush"] +pub type RXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `TXFFLSH` reader - TxFIFO flush"] +pub type TXFFLSH_R = crate::BitReader; +#[doc = "Field `TXFFLSH` writer - TxFIFO flush"] +pub type TXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `TXFNUM` reader - TxFIFO number"] +pub type TXFNUM_R = crate::FieldReader; +#[doc = "Field `TXFNUM` writer - TxFIFO number"] +pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, u8, 5, O>; +#[doc = "Field `DMAREQ` reader - DMA request signal"] +pub type DMAREQ_R = crate::BitReader; +#[doc = "Field `AHBIDL` reader - AHB master idle"] +pub type AHBIDL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Core soft reset"] + #[inline(always)] + pub fn csrst(&self) -> CSRST_R { + CSRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HCLK soft reset"] + #[inline(always)] + pub fn hsrst(&self) -> HSRST_R { + HSRST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host frame counter reset"] + #[inline(always)] + pub fn fcrst(&self) -> FCRST_R { + FCRST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - RxFIFO flush"] + #[inline(always)] + pub fn rxfflsh(&self) -> RXFFLSH_R { + RXFFLSH_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TxFIFO flush"] + #[inline(always)] + pub fn txfflsh(&self) -> TXFFLSH_R { + TXFFLSH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:10 - TxFIFO number"] + #[inline(always)] + pub fn txfnum(&self) -> TXFNUM_R { + TXFNUM_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bit 30 - DMA request signal"] + #[inline(always)] + pub fn dmareq(&self) -> DMAREQ_R { + DMAREQ_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - AHB master idle"] + #[inline(always)] + pub fn ahbidl(&self) -> AHBIDL_R { + AHBIDL_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Core soft reset"] + #[inline(always)] + #[must_use] + pub fn csrst(&mut self) -> CSRST_W<0> { + CSRST_W::new(self) + } + #[doc = "Bit 1 - HCLK soft reset"] + #[inline(always)] + #[must_use] + pub fn hsrst(&mut self) -> HSRST_W<1> { + HSRST_W::new(self) + } + #[doc = "Bit 2 - Host frame counter reset"] + #[inline(always)] + #[must_use] + pub fn fcrst(&mut self) -> FCRST_W<2> { + FCRST_W::new(self) + } + #[doc = "Bit 4 - RxFIFO flush"] + #[inline(always)] + #[must_use] + pub fn rxfflsh(&mut self) -> RXFFLSH_W<4> { + RXFFLSH_W::new(self) + } + #[doc = "Bit 5 - TxFIFO flush"] + #[inline(always)] + #[must_use] + pub fn txfflsh(&mut self) -> TXFFLSH_W<5> { + TXFFLSH_W::new(self) + } + #[doc = "Bits 6:10 - TxFIFO number"] + #[inline(always)] + #[must_use] + pub fn txfnum(&mut self) -> TXFNUM_W<6> { + TXFNUM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"] +pub struct GRSTCTL_SPEC; +impl crate::RegisterSpec for GRSTCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grstctl::R](R) reader structure"] +impl crate::Readable for GRSTCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"] +impl crate::Writable for GRSTCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GRSTCTL to value 0x2000_0000"] +impl crate::Resettable for GRSTCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_0000; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs new file mode 100644 index 0000000..ec6ba8c --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GRXFSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GRXFSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFD` reader - RxFIFO depth"] +pub type RXFD_R = crate::FieldReader; +#[doc = "Field `RXFD` writer - RxFIFO depth"] +pub type RXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRXFSIZ_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - RxFIFO depth"] + #[inline(always)] + pub fn rxfd(&self) -> RXFD_R { + RXFD_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn rxfd(&mut self) -> RXFD_W<0> { + RXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Receive FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](index.html) module"] +pub struct GRXFSIZ_SPEC; +impl crate::RegisterSpec for GRXFSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxfsiz::R](R) reader structure"] +impl crate::Readable for GRXFSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [grxfsiz::W](W) writer structure"] +impl crate::Writable for GRXFSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GRXFSIZ to value 0x0200"] +impl crate::Resettable for GRXFSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs new file mode 100644 index 0000000..a0231ff --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GRXSTSP_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHNUM` reader - Channel number"] +pub type CHNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Channel number"] + #[inline(always)] + pub fn chnum(&self) -> CHNUM_R { + CHNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[doc = "OTG_HS status read and pop register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_host](index.html) module"] +pub struct GRXSTSP_HOST_SPEC; +impl crate::RegisterSpec for GRXSTSP_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsp_host::R](R) reader structure"] +impl crate::Readable for GRXSTSP_HOST_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSP_Host to value 0"] +impl crate::Resettable for GRXSTSP_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs new file mode 100644 index 0000000..5de1533 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GRXSTSP_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +#[doc = "Field `FRMNUM` reader - Frame number"] +pub type FRMNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:24 - Frame number"] + #[inline(always)] + pub fn frmnum(&self) -> FRMNUM_R { + FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } +} +#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_peripheral](index.html) module"] +pub struct GRXSTSP_PERIPHERAL_SPEC; +impl crate::RegisterSpec for GRXSTSP_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsp_peripheral::R](R) reader structure"] +impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSP_Peripheral to value 0"] +impl crate::Resettable for GRXSTSP_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs new file mode 100644 index 0000000..399a9f8 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GRXSTSR_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHNUM` reader - Channel number"] +pub type CHNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Channel number"] + #[inline(always)] + pub fn chnum(&self) -> CHNUM_R { + CHNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[doc = "OTG_HS Receive status debug read register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_host](index.html) module"] +pub struct GRXSTSR_HOST_SPEC; +impl crate::RegisterSpec for GRXSTSR_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsr_host::R](R) reader structure"] +impl crate::Readable for GRXSTSR_HOST_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSR_Host to value 0"] +impl crate::Resettable for GRXSTSR_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs new file mode 100644 index 0000000..89558d9 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GRXSTSR_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +#[doc = "Field `FRMNUM` reader - Frame number"] +pub type FRMNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:24 - Frame number"] + #[inline(always)] + pub fn frmnum(&self) -> FRMNUM_R { + FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } +} +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_peripheral](index.html) module"] +pub struct GRXSTSR_PERIPHERAL_SPEC; +impl crate::RegisterSpec for GRXSTSR_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsr_peripheral::R](R) reader structure"] +impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSR_Peripheral to value 0"] +impl crate::Resettable for GRXSTSR_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs b/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs new file mode 100644 index 0000000..a958441 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs @@ -0,0 +1,625 @@ +#[doc = "Register `GUSBCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GUSBCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOCAL` reader - FS timeout calibration"] +pub type TOCAL_R = crate::FieldReader; +#[doc = "Field `TOCAL` writer - FS timeout calibration"] +pub type TOCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `PHYIF` reader - PHY Interface width"] +pub type PHYIF_R = crate::BitReader; +#[doc = "PHY Interface width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYIF_A { + #[doc = "0: `0`"] + _8BIT = 0, + #[doc = "1: `1`"] + _16BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYIF_A) -> Self { + variant as u8 != 0 + } +} +impl PHYIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYIF_A { + match self.bits { + false => PHYIF_A::_8BIT, + true => PHYIF_A::_16BIT, + } + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == PHYIF_A::_8BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == PHYIF_A::_16BIT + } +} +#[doc = "Field `PHYIF` writer - PHY Interface width"] +pub type PHYIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYIF_A, O>; +impl<'a, const O: u8> PHYIF_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(PHYIF_A::_8BIT) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(PHYIF_A::_16BIT) + } +} +#[doc = "Field `PHYTYPE` reader - PHY Type"] +pub type PHYTYPE_R = crate::BitReader; +#[doc = "PHY Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYTYPE_A { + #[doc = "0: `0`"] + UTMI = 0, + #[doc = "1: `1`"] + ULPI = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYTYPE_A) -> Self { + variant as u8 != 0 + } +} +impl PHYTYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYTYPE_A { + match self.bits { + false => PHYTYPE_A::UTMI, + true => PHYTYPE_A::ULPI, + } + } + #[doc = "Checks if the value of the field is `UTMI`"] + #[inline(always)] + pub fn is_utmi(&self) -> bool { + *self == PHYTYPE_A::UTMI + } + #[doc = "Checks if the value of the field is `ULPI`"] + #[inline(always)] + pub fn is_ulpi(&self) -> bool { + *self == PHYTYPE_A::ULPI + } +} +#[doc = "Field `PHYTYPE` writer - PHY Type"] +pub type PHYTYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYTYPE_A, O>; +impl<'a, const O: u8> PHYTYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn utmi(self) -> &'a mut W { + self.variant(PHYTYPE_A::UTMI) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ulpi(self) -> &'a mut W { + self.variant(PHYTYPE_A::ULPI) + } +} +#[doc = "Field `FSIF` reader - Full speed interface"] +pub type FSIF_R = crate::BitReader; +#[doc = "Full speed interface\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FSIF_A { + #[doc = "0: `0`"] + _6PIN = 0, + #[doc = "1: `1`"] + _3PIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FSIF_A) -> Self { + variant as u8 != 0 + } +} +impl FSIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSIF_A { + match self.bits { + false => FSIF_A::_6PIN, + true => FSIF_A::_3PIN, + } + } + #[doc = "Checks if the value of the field is `_6PIN`"] + #[inline(always)] + pub fn is_6pin(&self) -> bool { + *self == FSIF_A::_6PIN + } + #[doc = "Checks if the value of the field is `_3PIN`"] + #[inline(always)] + pub fn is_3pin(&self) -> bool { + *self == FSIF_A::_3PIN + } +} +#[doc = "Field `FSIF` writer - Full speed interface"] +pub type FSIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, FSIF_A, O>; +impl<'a, const O: u8> FSIF_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _6pin(self) -> &'a mut W { + self.variant(FSIF_A::_6PIN) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _3pin(self) -> &'a mut W { + self.variant(FSIF_A::_3PIN) + } +} +#[doc = "Field `PHYSEL` reader - Transceiver select"] +pub type PHYSEL_R = crate::BitReader; +#[doc = "Transceiver select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYSEL_A { + #[doc = "0: `0`"] + USB20 = 0, + #[doc = "1: `1`"] + USB11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYSEL_A) -> Self { + variant as u8 != 0 + } +} +impl PHYSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYSEL_A { + match self.bits { + false => PHYSEL_A::USB20, + true => PHYSEL_A::USB11, + } + } + #[doc = "Checks if the value of the field is `USB20`"] + #[inline(always)] + pub fn is_usb20(&self) -> bool { + *self == PHYSEL_A::USB20 + } + #[doc = "Checks if the value of the field is `USB11`"] + #[inline(always)] + pub fn is_usb11(&self) -> bool { + *self == PHYSEL_A::USB11 + } +} +#[doc = "Field `PHYSEL` writer - Transceiver select"] +pub type PHYSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYSEL_A, O>; +impl<'a, const O: u8> PHYSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn usb20(self) -> &'a mut W { + self.variant(PHYSEL_A::USB20) + } + #[doc = "`1`"] + #[inline(always)] + pub fn usb11(self) -> &'a mut W { + self.variant(PHYSEL_A::USB11) + } +} +#[doc = "Field `DDRSEL` reader - ULPI data rate"] +pub type DDRSEL_R = crate::BitReader; +#[doc = "ULPI data rate\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DDRSEL_A { + #[doc = "0: `0`"] + SINGLE = 0, + #[doc = "1: `1`"] + DOUBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DDRSEL_A) -> Self { + variant as u8 != 0 + } +} +impl DDRSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DDRSEL_A { + match self.bits { + false => DDRSEL_A::SINGLE, + true => DDRSEL_A::DOUBLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == DDRSEL_A::SINGLE + } + #[doc = "Checks if the value of the field is `DOUBLE`"] + #[inline(always)] + pub fn is_double(&self) -> bool { + *self == DDRSEL_A::DOUBLE + } +} +#[doc = "Field `DDRSEL` writer - ULPI data rate"] +pub type DDRSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, DDRSEL_A, O>; +impl<'a, const O: u8> DDRSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(DDRSEL_A::SINGLE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn double(self) -> &'a mut W { + self.variant(DDRSEL_A::DOUBLE) + } +} +#[doc = "Field `SRPCAP` reader - SRP-capable"] +pub type SRPCAP_R = crate::BitReader; +#[doc = "Field `SRPCAP` writer - SRP-capable"] +pub type SRPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `HNPCAP` reader - HNP-capable"] +pub type HNPCAP_R = crate::BitReader; +#[doc = "Field `HNPCAP` writer - HNP-capable"] +pub type HNPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `TRDT` reader - USB turnaround time"] +pub type TRDT_R = crate::FieldReader; +#[doc = "Field `TRDT` writer - USB turnaround time"] +pub type TRDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 4, O>; +#[doc = "Field `PHYLPCS` reader - PHY Low-power clock select"] +pub type PHYLPCS_R = crate::BitReader; +#[doc = "Field `PHYLPCS` writer - PHY Low-power clock select"] +pub type PHYLPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIFSLS` reader - ULPI FS/LS select"] +pub type ULPIFSLS_R = crate::BitReader; +#[doc = "Field `ULPIFSLS` writer - ULPI FS/LS select"] +pub type ULPIFSLS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIAR` reader - ULPI Auto-resume"] +pub type ULPIAR_R = crate::BitReader; +#[doc = "Field `ULPIAR` writer - ULPI Auto-resume"] +pub type ULPIAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPICSM` reader - ULPI Clock SuspendM"] +pub type ULPICSM_R = crate::BitReader; +#[doc = "Field `ULPICSM` writer - ULPI Clock SuspendM"] +pub type ULPICSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIEVBUSD` reader - ULPI External VBUS Drive"] +pub type ULPIEVBUSD_R = crate::BitReader; +#[doc = "Field `ULPIEVBUSD` writer - ULPI External VBUS Drive"] +pub type ULPIEVBUSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIEVBUSI` reader - ULPI external VBUS indicator"] +pub type ULPIEVBUSI_R = crate::BitReader; +#[doc = "Field `ULPIEVBUSI` writer - ULPI external VBUS indicator"] +pub type ULPIEVBUSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `TSDPS` reader - TermSel DLine pulsing selection"] +pub type TSDPS_R = crate::BitReader; +#[doc = "Field `TSDPS` writer - TermSel DLine pulsing selection"] +pub type TSDPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `PCCI` reader - Indicator complement"] +pub type PCCI_R = crate::BitReader; +#[doc = "Field `PCCI` writer - Indicator complement"] +pub type PCCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `PTCI` reader - Indicator pass through"] +pub type PTCI_R = crate::BitReader; +#[doc = "Field `PTCI` writer - Indicator pass through"] +pub type PTCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIIPD` reader - ULPI interface protect disable"] +pub type ULPIIPD_R = crate::BitReader; +#[doc = "Field `ULPIIPD` writer - ULPI interface protect disable"] +pub type ULPIIPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `FHMOD` reader - Forced host mode"] +pub type FHMOD_R = crate::BitReader; +#[doc = "Field `FHMOD` writer - Forced host mode"] +pub type FHMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `FDMOD` reader - Forced peripheral mode"] +pub type FDMOD_R = crate::BitReader; +#[doc = "Field `FDMOD` writer - Forced peripheral mode"] +pub type FDMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `CTXPKT` reader - Corrupt Tx packet"] +pub type CTXPKT_R = crate::BitReader; +#[doc = "Field `CTXPKT` writer - Corrupt Tx packet"] +pub type CTXPKT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - FS timeout calibration"] + #[inline(always)] + pub fn tocal(&self) -> TOCAL_R { + TOCAL_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - PHY Interface width"] + #[inline(always)] + pub fn phyif(&self) -> PHYIF_R { + PHYIF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PHY Type"] + #[inline(always)] + pub fn phytype(&self) -> PHYTYPE_R { + PHYTYPE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Full speed interface"] + #[inline(always)] + pub fn fsif(&self) -> FSIF_R { + FSIF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transceiver select"] + #[inline(always)] + pub fn physel(&self) -> PHYSEL_R { + PHYSEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ULPI data rate"] + #[inline(always)] + pub fn ddrsel(&self) -> DDRSEL_R { + DDRSEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SRP-capable"] + #[inline(always)] + pub fn srpcap(&self) -> SRPCAP_R { + SRPCAP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HNP-capable"] + #[inline(always)] + pub fn hnpcap(&self) -> HNPCAP_R { + HNPCAP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - USB turnaround time"] + #[inline(always)] + pub fn trdt(&self) -> TRDT_R { + TRDT_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bit 15 - PHY Low-power clock select"] + #[inline(always)] + pub fn phylpcs(&self) -> PHYLPCS_R { + PHYLPCS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - ULPI FS/LS select"] + #[inline(always)] + pub fn ulpifsls(&self) -> ULPIFSLS_R { + ULPIFSLS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - ULPI Auto-resume"] + #[inline(always)] + pub fn ulpiar(&self) -> ULPIAR_R { + ULPIAR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - ULPI Clock SuspendM"] + #[inline(always)] + pub fn ulpicsm(&self) -> ULPICSM_R { + ULPICSM_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - ULPI External VBUS Drive"] + #[inline(always)] + pub fn ulpievbusd(&self) -> ULPIEVBUSD_R { + ULPIEVBUSD_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ULPI external VBUS indicator"] + #[inline(always)] + pub fn ulpievbusi(&self) -> ULPIEVBUSI_R { + ULPIEVBUSI_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - TermSel DLine pulsing selection"] + #[inline(always)] + pub fn tsdps(&self) -> TSDPS_R { + TSDPS_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Indicator complement"] + #[inline(always)] + pub fn pcci(&self) -> PCCI_R { + PCCI_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Indicator pass through"] + #[inline(always)] + pub fn ptci(&self) -> PTCI_R { + PTCI_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - ULPI interface protect disable"] + #[inline(always)] + pub fn ulpiipd(&self) -> ULPIIPD_R { + ULPIIPD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 29 - Forced host mode"] + #[inline(always)] + pub fn fhmod(&self) -> FHMOD_R { + FHMOD_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Forced peripheral mode"] + #[inline(always)] + pub fn fdmod(&self) -> FDMOD_R { + FDMOD_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Corrupt Tx packet"] + #[inline(always)] + pub fn ctxpkt(&self) -> CTXPKT_R { + CTXPKT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - FS timeout calibration"] + #[inline(always)] + #[must_use] + pub fn tocal(&mut self) -> TOCAL_W<0> { + TOCAL_W::new(self) + } + #[doc = "Bit 3 - PHY Interface width"] + #[inline(always)] + #[must_use] + pub fn phyif(&mut self) -> PHYIF_W<3> { + PHYIF_W::new(self) + } + #[doc = "Bit 4 - PHY Type"] + #[inline(always)] + #[must_use] + pub fn phytype(&mut self) -> PHYTYPE_W<4> { + PHYTYPE_W::new(self) + } + #[doc = "Bit 5 - Full speed interface"] + #[inline(always)] + #[must_use] + pub fn fsif(&mut self) -> FSIF_W<5> { + FSIF_W::new(self) + } + #[doc = "Bit 6 - Transceiver select"] + #[inline(always)] + #[must_use] + pub fn physel(&mut self) -> PHYSEL_W<6> { + PHYSEL_W::new(self) + } + #[doc = "Bit 7 - ULPI data rate"] + #[inline(always)] + #[must_use] + pub fn ddrsel(&mut self) -> DDRSEL_W<7> { + DDRSEL_W::new(self) + } + #[doc = "Bit 8 - SRP-capable"] + #[inline(always)] + #[must_use] + pub fn srpcap(&mut self) -> SRPCAP_W<8> { + SRPCAP_W::new(self) + } + #[doc = "Bit 9 - HNP-capable"] + #[inline(always)] + #[must_use] + pub fn hnpcap(&mut self) -> HNPCAP_W<9> { + HNPCAP_W::new(self) + } + #[doc = "Bits 10:13 - USB turnaround time"] + #[inline(always)] + #[must_use] + pub fn trdt(&mut self) -> TRDT_W<10> { + TRDT_W::new(self) + } + #[doc = "Bit 15 - PHY Low-power clock select"] + #[inline(always)] + #[must_use] + pub fn phylpcs(&mut self) -> PHYLPCS_W<15> { + PHYLPCS_W::new(self) + } + #[doc = "Bit 17 - ULPI FS/LS select"] + #[inline(always)] + #[must_use] + pub fn ulpifsls(&mut self) -> ULPIFSLS_W<17> { + ULPIFSLS_W::new(self) + } + #[doc = "Bit 18 - ULPI Auto-resume"] + #[inline(always)] + #[must_use] + pub fn ulpiar(&mut self) -> ULPIAR_W<18> { + ULPIAR_W::new(self) + } + #[doc = "Bit 19 - ULPI Clock SuspendM"] + #[inline(always)] + #[must_use] + pub fn ulpicsm(&mut self) -> ULPICSM_W<19> { + ULPICSM_W::new(self) + } + #[doc = "Bit 20 - ULPI External VBUS Drive"] + #[inline(always)] + #[must_use] + pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<20> { + ULPIEVBUSD_W::new(self) + } + #[doc = "Bit 21 - ULPI external VBUS indicator"] + #[inline(always)] + #[must_use] + pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<21> { + ULPIEVBUSI_W::new(self) + } + #[doc = "Bit 22 - TermSel DLine pulsing selection"] + #[inline(always)] + #[must_use] + pub fn tsdps(&mut self) -> TSDPS_W<22> { + TSDPS_W::new(self) + } + #[doc = "Bit 23 - Indicator complement"] + #[inline(always)] + #[must_use] + pub fn pcci(&mut self) -> PCCI_W<23> { + PCCI_W::new(self) + } + #[doc = "Bit 24 - Indicator pass through"] + #[inline(always)] + #[must_use] + pub fn ptci(&mut self) -> PTCI_W<24> { + PTCI_W::new(self) + } + #[doc = "Bit 25 - ULPI interface protect disable"] + #[inline(always)] + #[must_use] + pub fn ulpiipd(&mut self) -> ULPIIPD_W<25> { + ULPIIPD_W::new(self) + } + #[doc = "Bit 29 - Forced host mode"] + #[inline(always)] + #[must_use] + pub fn fhmod(&mut self) -> FHMOD_W<29> { + FHMOD_W::new(self) + } + #[doc = "Bit 30 - Forced peripheral mode"] + #[inline(always)] + #[must_use] + pub fn fdmod(&mut self) -> FDMOD_W<30> { + FDMOD_W::new(self) + } + #[doc = "Bit 31 - Corrupt Tx packet"] + #[inline(always)] + #[must_use] + pub fn ctxpkt(&mut self) -> CTXPKT_W<31> { + CTXPKT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS USB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](index.html) module"] +pub struct GUSBCFG_SPEC; +impl crate::RegisterSpec for GUSBCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gusbcfg::R](R) reader structure"] +impl crate::Readable for GUSBCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gusbcfg::W](W) writer structure"] +impl crate::Writable for GUSBCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GUSBCFG to value 0x0a00"] +impl crate::Resettable for GUSBCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0a00; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs b/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs new file mode 100644 index 0000000..c50a180 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs @@ -0,0 +1,95 @@ +#[doc = "Register `HPTXFSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPTXFSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTXSA` reader - Host periodic TxFIFO start address"] +pub type PTXSA_R = crate::FieldReader; +#[doc = "Field `PTXSA` writer - Host periodic TxFIFO start address"] +pub type PTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +#[doc = "Field `PTXFD` reader - Host periodic TxFIFO depth"] +pub type PTXFD_R = crate::FieldReader; +#[doc = "Field `PTXFD` writer - Host periodic TxFIFO depth"] +pub type PTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] + #[inline(always)] + pub fn ptxsa(&self) -> PTXSA_R { + PTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] + #[inline(always)] + pub fn ptxfd(&self) -> PTXFD_R { + PTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] + #[inline(always)] + #[must_use] + pub fn ptxsa(&mut self) -> PTXSA_W<0> { + PTXSA_W::new(self) + } + #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ptxfd(&mut self) -> PTXFD_W<16> { + PTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](index.html) module"] +pub struct HPTXFSIZ_SPEC; +impl crate::RegisterSpec for HPTXFSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hptxfsiz::R](R) reader structure"] +impl crate::Readable for HPTXFSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](W) writer structure"] +impl crate::Writable for HPTXFSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPTXFSIZ to value 0x0200_0600"] +impl crate::Resettable for HPTXFSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0600; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs b/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs new file mode 100644 index 0000000..13715b7 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs @@ -0,0 +1,348 @@ +#[doc = "Register `HW_CONFIG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OPERATING_MODE` reader - Operating Mode"] +pub type OPERATING_MODE_R = crate::FieldReader; +#[doc = "Operating Mode"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OPERATING_MODE_A { + #[doc = "0: `0`"] + HNP_SRP_CAPABLE = 0, + #[doc = "1: `1`"] + SRP_ONLY_CAPABLE = 1, + #[doc = "2: `10`"] + NO_HNP_SRP_CAPABLE = 2, + #[doc = "3: `11`"] + SRP_CAPABLE_DEVICE = 3, + #[doc = "4: `100`"] + NO_SRP_CAPABLE_DEVICE = 4, + #[doc = "5: `101`"] + SRP_CAPABLE_HOST = 5, + #[doc = "6: `110`"] + NO_SRP_CAPABLE_HOST = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OPERATING_MODE_A) -> Self { + variant as _ + } +} +impl OPERATING_MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OPERATING_MODE_A::HNP_SRP_CAPABLE), + 1 => Some(OPERATING_MODE_A::SRP_ONLY_CAPABLE), + 2 => Some(OPERATING_MODE_A::NO_HNP_SRP_CAPABLE), + 3 => Some(OPERATING_MODE_A::SRP_CAPABLE_DEVICE), + 4 => Some(OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE), + 5 => Some(OPERATING_MODE_A::SRP_CAPABLE_HOST), + 6 => Some(OPERATING_MODE_A::NO_SRP_CAPABLE_HOST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `HNP_SRP_CAPABLE`"] + #[inline(always)] + pub fn is_hnp_srp_capable(&self) -> bool { + *self == OPERATING_MODE_A::HNP_SRP_CAPABLE + } + #[doc = "Checks if the value of the field is `SRP_ONLY_CAPABLE`"] + #[inline(always)] + pub fn is_srp_only_capable(&self) -> bool { + *self == OPERATING_MODE_A::SRP_ONLY_CAPABLE + } + #[doc = "Checks if the value of the field is `NO_HNP_SRP_CAPABLE`"] + #[inline(always)] + pub fn is_no_hnp_srp_capable(&self) -> bool { + *self == OPERATING_MODE_A::NO_HNP_SRP_CAPABLE + } + #[doc = "Checks if the value of the field is `SRP_CAPABLE_DEVICE`"] + #[inline(always)] + pub fn is_srp_capable_device(&self) -> bool { + *self == OPERATING_MODE_A::SRP_CAPABLE_DEVICE + } + #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_DEVICE`"] + #[inline(always)] + pub fn is_no_srp_capable_device(&self) -> bool { + *self == OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE + } + #[doc = "Checks if the value of the field is `SRP_CAPABLE_HOST`"] + #[inline(always)] + pub fn is_srp_capable_host(&self) -> bool { + *self == OPERATING_MODE_A::SRP_CAPABLE_HOST + } + #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_HOST`"] + #[inline(always)] + pub fn is_no_srp_capable_host(&self) -> bool { + *self == OPERATING_MODE_A::NO_SRP_CAPABLE_HOST + } +} +#[doc = "Field `ARCHITECTURE` reader - Architecture"] +pub type ARCHITECTURE_R = crate::FieldReader; +#[doc = "Architecture"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ARCHITECTURE_A { + #[doc = "0: `0`"] + SLAVE_ONLY = 0, + #[doc = "1: `1`"] + EXTERNAL_DMA = 1, + #[doc = "2: `10`"] + INTERNAL_DMA = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ARCHITECTURE_A) -> Self { + variant as _ + } +} +impl ARCHITECTURE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ARCHITECTURE_A::SLAVE_ONLY), + 1 => Some(ARCHITECTURE_A::EXTERNAL_DMA), + 2 => Some(ARCHITECTURE_A::INTERNAL_DMA), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SLAVE_ONLY`"] + #[inline(always)] + pub fn is_slave_only(&self) -> bool { + *self == ARCHITECTURE_A::SLAVE_ONLY + } + #[doc = "Checks if the value of the field is `EXTERNAL_DMA`"] + #[inline(always)] + pub fn is_external_dma(&self) -> bool { + *self == ARCHITECTURE_A::EXTERNAL_DMA + } + #[doc = "Checks if the value of the field is `INTERNAL_DMA`"] + #[inline(always)] + pub fn is_internal_dma(&self) -> bool { + *self == ARCHITECTURE_A::INTERNAL_DMA + } +} +#[doc = "Field `POINT_TO_POINT` reader - Point to Point"] +pub type POINT_TO_POINT_R = crate::BitReader; +#[doc = "Field `HIGH_SPEED_PHY` reader - High Speed Physical"] +pub type HIGH_SPEED_PHY_R = crate::FieldReader; +#[doc = "High Speed Physical"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HIGH_SPEED_PHY_A { + #[doc = "0: `0`"] + NOT_SUPPORTED = 0, + #[doc = "1: `1`"] + UTMI = 1, + #[doc = "2: `10`"] + ULPI = 2, + #[doc = "3: `11`"] + UTMI_ULPI = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HIGH_SPEED_PHY_A) -> Self { + variant as _ + } +} +impl HIGH_SPEED_PHY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HIGH_SPEED_PHY_A { + match self.bits { + 0 => HIGH_SPEED_PHY_A::NOT_SUPPORTED, + 1 => HIGH_SPEED_PHY_A::UTMI, + 2 => HIGH_SPEED_PHY_A::ULPI, + 3 => HIGH_SPEED_PHY_A::UTMI_ULPI, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NOT_SUPPORTED`"] + #[inline(always)] + pub fn is_not_supported(&self) -> bool { + *self == HIGH_SPEED_PHY_A::NOT_SUPPORTED + } + #[doc = "Checks if the value of the field is `UTMI`"] + #[inline(always)] + pub fn is_utmi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::UTMI + } + #[doc = "Checks if the value of the field is `ULPI`"] + #[inline(always)] + pub fn is_ulpi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::ULPI + } + #[doc = "Checks if the value of the field is `UTMI_ULPI`"] + #[inline(always)] + pub fn is_utmi_ulpi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::UTMI_ULPI + } +} +#[doc = "Field `FULL_SPEED_PHY` reader - Full Speed Physical"] +pub type FULL_SPEED_PHY_R = crate::FieldReader; +#[doc = "Full Speed Physical"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FULL_SPEED_PHY_A { + #[doc = "0: `0`"] + PHY0 = 0, + #[doc = "1: `1`"] + DEDICATED = 1, + #[doc = "2: `10`"] + PHY2 = 2, + #[doc = "3: `11`"] + PHY3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FULL_SPEED_PHY_A) -> Self { + variant as _ + } +} +impl FULL_SPEED_PHY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FULL_SPEED_PHY_A { + match self.bits { + 0 => FULL_SPEED_PHY_A::PHY0, + 1 => FULL_SPEED_PHY_A::DEDICATED, + 2 => FULL_SPEED_PHY_A::PHY2, + 3 => FULL_SPEED_PHY_A::PHY3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PHY0`"] + #[inline(always)] + pub fn is_phy0(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY0 + } + #[doc = "Checks if the value of the field is `DEDICATED`"] + #[inline(always)] + pub fn is_dedicated(&self) -> bool { + *self == FULL_SPEED_PHY_A::DEDICATED + } + #[doc = "Checks if the value of the field is `PHY2`"] + #[inline(always)] + pub fn is_phy2(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY2 + } + #[doc = "Checks if the value of the field is `PHY3`"] + #[inline(always)] + pub fn is_phy3(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY3 + } +} +#[doc = "Field `DEVICE_END_POINT_COUNT` reader - Device end point count"] +pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; +#[doc = "Field `HOST_CHANNEL_COUNT` reader - Host channel count"] +pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; +#[doc = "Field `SUPPORTS_PERIODIC_ENDPOINTS` reader - Supports periodic endpoints"] +pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; +#[doc = "Field `DYNAMIC_FIFO` reader - Dynamic FIFO"] +pub type DYNAMIC_FIFO_R = crate::BitReader; +#[doc = "Field `MULTI_PROC_INT` reader - Multi proc int"] +pub type MULTI_PROC_INT_R = crate::BitReader; +#[doc = "Field `NON_PERIODIC_QUEUE_DEPTH` reader - Non periodic queue depth"] +pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `HOST_PERIODIC_QUEUE_DEPTH` reader - Host periodic queue depth"] +pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `DEVICE_TOKEN_QUEUE_DEPTH` reader - Device token queue depth"] +pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `ENABLE_IC_USB` reader - Enable IC USB"] +pub type ENABLE_IC_USB_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Operating Mode"] + #[inline(always)] + pub fn operating_mode(&self) -> OPERATING_MODE_R { + OPERATING_MODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Architecture"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Point to Point"] + #[inline(always)] + pub fn point_to_point(&self) -> POINT_TO_POINT_R { + POINT_TO_POINT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - High Speed Physical"] + #[inline(always)] + pub fn high_speed_phy(&self) -> HIGH_SPEED_PHY_R { + HIGH_SPEED_PHY_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Full Speed Physical"] + #[inline(always)] + pub fn full_speed_phy(&self) -> FULL_SPEED_PHY_R { + FULL_SPEED_PHY_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:13 - Device end point count"] + #[inline(always)] + pub fn device_end_point_count(&self) -> DEVICE_END_POINT_COUNT_R { + DEVICE_END_POINT_COUNT_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:17 - Host channel count"] + #[inline(always)] + pub fn host_channel_count(&self) -> HOST_CHANNEL_COUNT_R { + HOST_CHANNEL_COUNT_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bit 18 - Supports periodic endpoints"] + #[inline(always)] + pub fn supports_periodic_endpoints(&self) -> SUPPORTS_PERIODIC_ENDPOINTS_R { + SUPPORTS_PERIODIC_ENDPOINTS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Dynamic FIFO"] + #[inline(always)] + pub fn dynamic_fifo(&self) -> DYNAMIC_FIFO_R { + DYNAMIC_FIFO_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Multi proc int"] + #[inline(always)] + pub fn multi_proc_int(&self) -> MULTI_PROC_INT_R { + MULTI_PROC_INT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 22:23 - Non periodic queue depth"] + #[inline(always)] + pub fn non_periodic_queue_depth(&self) -> NON_PERIODIC_QUEUE_DEPTH_R { + NON_PERIODIC_QUEUE_DEPTH_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Host periodic queue depth"] + #[inline(always)] + pub fn host_periodic_queue_depth(&self) -> HOST_PERIODIC_QUEUE_DEPTH_R { + HOST_PERIODIC_QUEUE_DEPTH_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:30 - Device token queue depth"] + #[inline(always)] + pub fn device_token_queue_depth(&self) -> DEVICE_TOKEN_QUEUE_DEPTH_R { + DEVICE_TOKEN_QUEUE_DEPTH_R::new(((self.bits >> 26) & 0x1f) as u8) + } + #[doc = "Bit 31 - Enable IC USB"] + #[inline(always)] + pub fn enable_ic_usb(&self) -> ENABLE_IC_USB_R { + ENABLE_IC_USB_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Hardware Config 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_config0](index.html) module"] +pub struct HW_CONFIG0_SPEC; +impl crate::RegisterSpec for HW_CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hw_config0::R](R) reader structure"] +impl crate::Readable for HW_CONFIG0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs b/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs new file mode 100644 index 0000000..1ca29d0 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs @@ -0,0 +1,157 @@ +#[doc = "Register `HW_DIRECTION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DIRECTION[0-15]` reader - Direction %s"] +pub type DIRECTION_R = crate::FieldReader; +#[doc = "Direction %s"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + BIDIR = 0, + #[doc = "1: `1`"] + IN = 1, + #[doc = "2: `10`"] + OUT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as _ + } +} +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DIRECTION_A::BIDIR), + 1 => Some(DIRECTION_A::IN), + 2 => Some(DIRECTION_A::OUT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BIDIR`"] + #[inline(always)] + pub fn is_bidir(&self) -> bool { + *self == DIRECTION_A::BIDIR + } + #[doc = "Checks if the value of the field is `IN`"] + #[inline(always)] + pub fn is_in(&self) -> bool { + *self == DIRECTION_A::IN + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + *self == DIRECTION_A::OUT + } +} +impl R { + #[doc = "Direction [0-15]"] + #[inline(always)] + pub unsafe fn direction(&self, n: u8) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> (n * 2)) & 3) as u8) + } + #[doc = "Bits 0:1 - Direction 0"] + #[inline(always)] + pub fn direction0(&self) -> DIRECTION_R { + DIRECTION_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Direction 1"] + #[inline(always)] + pub fn direction1(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Direction 2"] + #[inline(always)] + pub fn direction2(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Direction 3"] + #[inline(always)] + pub fn direction3(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Direction 4"] + #[inline(always)] + pub fn direction4(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Direction 5"] + #[inline(always)] + pub fn direction5(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Direction 6"] + #[inline(always)] + pub fn direction6(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Direction 7"] + #[inline(always)] + pub fn direction7(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Direction 8"] + #[inline(always)] + pub fn direction8(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Direction 9"] + #[inline(always)] + pub fn direction9(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Direction 10"] + #[inline(always)] + pub fn direction10(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Direction 11"] + #[inline(always)] + pub fn direction11(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Direction 12"] + #[inline(always)] + pub fn direction12(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Direction 13"] + #[inline(always)] + pub fn direction13(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Direction 14"] + #[inline(always)] + pub fn direction14(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Direction 15"] + #[inline(always)] + pub fn direction15(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[doc = "Direction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_direction](index.html) module"] +pub struct HW_DIRECTION_SPEC; +impl crate::RegisterSpec for HW_DIRECTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hw_direction::R](R) reader structure"] +impl crate::Readable for HW_DIRECTION_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs b/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs new file mode 100644 index 0000000..8734146 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs @@ -0,0 +1,97 @@ +#[doc = "Register `TX0FSIZ_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TX0FSIZ_Peripheral` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TX0FSA` reader - Endpoint 0 transmit RAM start address"] +pub type TX0FSA_R = crate::FieldReader; +#[doc = "Field `TX0FSA` writer - Endpoint 0 transmit RAM start address"] +pub type TX0FSA_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +#[doc = "Field `TX0FD` reader - Endpoint 0 TxFIFO depth"] +pub type TX0FD_R = crate::FieldReader; +#[doc = "Field `TX0FD` writer - Endpoint 0 TxFIFO depth"] +pub type TX0FD_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] + #[inline(always)] + pub fn tx0fsa(&self) -> TX0FSA_R { + TX0FSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] + #[inline(always)] + pub fn tx0fd(&self) -> TX0FD_R { + TX0FD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn tx0fsa(&mut self) -> TX0FSA_W<0> { + TX0FSA_W::new(self) + } + #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn tx0fd(&mut self) -> TX0FD_W<16> { + TX0FD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx0fsiz_peripheral](index.html) module"] +pub struct TX0FSIZ_PERIPHERAL_SPEC; +impl crate::RegisterSpec for TX0FSIZ_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx0fsiz_peripheral::R](R) reader structure"] +impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tx0fsiz_peripheral::W](W) writer structure"] +impl crate::Writable for TX0FSIZ_PERIPHERAL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX0FSIZ_Peripheral to value 0x0200"] +impl crate::Resettable for TX0FSIZ_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/vid.rs b/crates/bcm2835-lpa/src/usb_otg_global/vid.rs new file mode 100644 index 0000000..ae468f7 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_global/vid.rs @@ -0,0 +1,24 @@ +#[doc = "Register `VID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "OTG_HS vendor ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vid](index.html) module"] +pub struct VID_SPEC; +impl crate::RegisterSpec for VID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vid::R](R) reader structure"] +impl crate::Readable for VID_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host.rs b/crates/bcm2835-lpa/src/usb_otg_host.rs new file mode 100644 index 0000000..c2b6fb8 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host.rs @@ -0,0 +1,89 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS host configuration register"] + pub hcfg: HCFG, + #[doc = "0x04 - OTG_HS Host frame interval register"] + pub hfir: HFIR, + #[doc = "0x08 - OTG_HS host frame number/frame time remaining register"] + pub hfnum: HFNUM, + _reserved3: [u8; 0x04], + #[doc = "0x10 - Host periodic transmit FIFO/queue status register"] + pub hptxsts: HPTXSTS, + #[doc = "0x14 - OTG_HS Host all channels interrupt register"] + pub haint: HAINT, + #[doc = "0x18 - OTG_HS host all channels interrupt mask register"] + pub haintmsk: HAINTMSK, + _reserved6: [u8; 0x24], + #[doc = "0x40 - OTG_HS host port control and status register"] + pub hprt: HPRT, + _reserved7: [u8; 0xbc], + #[doc = "0x100..0x118 - Host channel %s"] + pub host_channel0: HOST_CHANNEL, + _reserved8: [u8; 0x08], + #[doc = "0x120..0x138 - Host channel %s"] + pub host_channel1: HOST_CHANNEL, + _reserved9: [u8; 0x08], + #[doc = "0x140..0x158 - Host channel %s"] + pub host_channel2: HOST_CHANNEL, + _reserved10: [u8; 0x08], + #[doc = "0x160..0x178 - Host channel %s"] + pub host_channel3: HOST_CHANNEL, + _reserved11: [u8; 0x08], + #[doc = "0x180..0x198 - Host channel %s"] + pub host_channel4: HOST_CHANNEL, + _reserved12: [u8; 0x08], + #[doc = "0x1a0..0x1b8 - Host channel %s"] + pub host_channel5: HOST_CHANNEL, + _reserved13: [u8; 0x08], + #[doc = "0x1c0..0x1d8 - Host channel %s"] + pub host_channel6: HOST_CHANNEL, + _reserved14: [u8; 0x08], + #[doc = "0x1e0..0x1f8 - Host channel %s"] + pub host_channel7: HOST_CHANNEL, + _reserved15: [u8; 0x08], + #[doc = "0x200..0x218 - Host channel %s"] + pub host_channel8: HOST_CHANNEL, + _reserved16: [u8; 0x08], + #[doc = "0x220..0x238 - Host channel %s"] + pub host_channel9: HOST_CHANNEL, + _reserved17: [u8; 0x08], + #[doc = "0x240..0x258 - Host channel %s"] + pub host_channel10: HOST_CHANNEL, + _reserved18: [u8; 0x08], + #[doc = "0x260..0x278 - Host channel %s"] + pub host_channel11: HOST_CHANNEL, +} +#[doc = "HCFG (rw) register accessor: an alias for `Reg`"] +pub type HCFG = crate::Reg; +#[doc = "OTG_HS host configuration register"] +pub mod hcfg; +#[doc = "HFIR (rw) register accessor: an alias for `Reg`"] +pub type HFIR = crate::Reg; +#[doc = "OTG_HS Host frame interval register"] +pub mod hfir; +#[doc = "HFNUM (r) register accessor: an alias for `Reg`"] +pub type HFNUM = crate::Reg; +#[doc = "OTG_HS host frame number/frame time remaining register"] +pub mod hfnum; +#[doc = "HPTXSTS (rw) register accessor: an alias for `Reg`"] +pub type HPTXSTS = crate::Reg; +#[doc = "Host periodic transmit FIFO/queue status register"] +pub mod hptxsts; +#[doc = "HAINT (r) register accessor: an alias for `Reg`"] +pub type HAINT = crate::Reg; +#[doc = "OTG_HS Host all channels interrupt register"] +pub mod haint; +#[doc = "HAINTMSK (rw) register accessor: an alias for `Reg`"] +pub type HAINTMSK = crate::Reg; +#[doc = "OTG_HS host all channels interrupt mask register"] +pub mod haintmsk; +#[doc = "HPRT (rw) register accessor: an alias for `Reg`"] +pub type HPRT = crate::Reg; +#[doc = "OTG_HS host port control and status register"] +pub mod hprt; +#[doc = "Host channel %s"] +pub use self::host_channel::HOST_CHANNEL; +#[doc = r"Cluster"] +#[doc = "Host channel %s"] +pub mod host_channel; diff --git a/crates/bcm2835-lpa/src/usb_otg_host/haint.rs b/crates/bcm2835-lpa/src/usb_otg_host/haint.rs new file mode 100644 index 0000000..16455f3 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/haint.rs @@ -0,0 +1,37 @@ +#[doc = "Register `HAINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HAINT` reader - Channel interrupts"] +pub type HAINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Channel interrupts"] + #[inline(always)] + pub fn haint(&self) -> HAINT_R { + HAINT_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "OTG_HS Host all channels interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](index.html) module"] +pub struct HAINT_SPEC; +impl crate::RegisterSpec for HAINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [haint::R](R) reader structure"] +impl crate::Readable for HAINT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HAINT to value 0"] +impl crate::Resettable for HAINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs new file mode 100644 index 0000000..69df5e9 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HAINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HAINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HAINTM` reader - Channel interrupt mask"] +pub type HAINTM_R = crate::FieldReader; +#[doc = "Field `HAINTM` writer - Channel interrupt mask"] +pub type HAINTM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HAINTMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Channel interrupt mask"] + #[inline(always)] + pub fn haintm(&self) -> HAINTM_R { + HAINTM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Channel interrupt mask"] + #[inline(always)] + #[must_use] + pub fn haintm(&mut self) -> HAINTM_W<0> { + HAINTM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host all channels interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](index.html) module"] +pub struct HAINTMSK_SPEC; +impl crate::RegisterSpec for HAINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [haintmsk::R](R) reader structure"] +impl crate::Readable for HAINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [haintmsk::W](W) writer structure"] +impl crate::Writable for HAINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HAINTMSK to value 0"] +impl crate::Resettable for HAINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs b/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs new file mode 100644 index 0000000..17f4b01 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs @@ -0,0 +1,87 @@ +#[doc = "Register `HCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSLSPCS` reader - FS/LS PHY clock select"] +pub type FSLSPCS_R = crate::FieldReader; +#[doc = "Field `FSLSPCS` writer - FS/LS PHY clock select"] +pub type FSLSPCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `FSLSS` reader - FS- and LS-only support"] +pub type FSLSS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - FS/LS PHY clock select"] + #[inline(always)] + pub fn fslspcs(&self) -> FSLSPCS_R { + FSLSPCS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - FS- and LS-only support"] + #[inline(always)] + pub fn fslss(&self) -> FSLSS_R { + FSLSS_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - FS/LS PHY clock select"] + #[inline(always)] + #[must_use] + pub fn fslspcs(&mut self) -> FSLSPCS_W<0> { + FSLSPCS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"] +pub struct HCFG_SPEC; +impl crate::RegisterSpec for HCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcfg::R](R) reader structure"] +impl crate::Readable for HCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"] +impl crate::Writable for HCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCFG to value 0"] +impl crate::Resettable for HCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs b/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs new file mode 100644 index 0000000..9182ff2 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HFIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HFIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FRIVL` reader - Frame interval"] +pub type FRIVL_R = crate::FieldReader; +#[doc = "Field `FRIVL` writer - Frame interval"] +pub type FRIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFIR_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Frame interval"] + #[inline(always)] + pub fn frivl(&self) -> FRIVL_R { + FRIVL_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Frame interval"] + #[inline(always)] + #[must_use] + pub fn frivl(&mut self) -> FRIVL_W<0> { + FRIVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Host frame interval register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](index.html) module"] +pub struct HFIR_SPEC; +impl crate::RegisterSpec for HFIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfir::R](R) reader structure"] +impl crate::Readable for HFIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hfir::W](W) writer structure"] +impl crate::Writable for HFIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HFIR to value 0xea60"] +impl crate::Resettable for HFIR_SPEC { + const RESET_VALUE: Self::Ux = 0xea60; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs b/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs new file mode 100644 index 0000000..0df982a --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HFNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FRNUM` reader - Frame number"] +pub type FRNUM_R = crate::FieldReader; +#[doc = "Field `FTREM` reader - Frame time remaining"] +pub type FTREM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Frame number"] + #[inline(always)] + pub fn frnum(&self) -> FRNUM_R { + FRNUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Frame time remaining"] + #[inline(always)] + pub fn ftrem(&self) -> FTREM_R { + FTREM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "OTG_HS host frame number/frame time remaining register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](index.html) module"] +pub struct HFNUM_SPEC; +impl crate::RegisterSpec for HFNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfnum::R](R) reader structure"] +impl crate::Readable for HFNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HFNUM to value 0x3fff"] +impl crate::Resettable for HFNUM_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs new file mode 100644 index 0000000..ee4a815 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST_CHANNEL { + #[doc = "0x00 - Characteristics register"] + pub hcchar: HCCHAR, + #[doc = "0x04 - Split control register"] + pub hcsplt: HCSPLT, + #[doc = "0x08 - Interrupt register"] + pub hcint: HCINT, + #[doc = "0x0c - Interrupt mask"] + pub hcintmsk: HCINTMSK, + #[doc = "0x10 - Transfer size"] + pub hctsiz: HCTSIZ, + #[doc = "0x14 - DMA address"] + pub hcdma: HCDMA, +} +#[doc = "HCCHAR (rw) register accessor: an alias for `Reg`"] +pub type HCCHAR = crate::Reg; +#[doc = "Characteristics register"] +pub mod hcchar; +#[doc = "HCSPLT (rw) register accessor: an alias for `Reg`"] +pub type HCSPLT = crate::Reg; +#[doc = "Split control register"] +pub mod hcsplt; +#[doc = "HCINT (rw) register accessor: an alias for `Reg`"] +pub type HCINT = crate::Reg; +#[doc = "Interrupt register"] +pub mod hcint; +#[doc = "HCINTMSK (rw) register accessor: an alias for `Reg`"] +pub type HCINTMSK = crate::Reg; +#[doc = "Interrupt mask"] +pub mod hcintmsk; +#[doc = "HCTSIZ (rw) register accessor: an alias for `Reg`"] +pub type HCTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod hctsiz; +#[doc = "HCDMA (rw) register accessor: an alias for `Reg`"] +pub type HCDMA = crate::Reg; +#[doc = "DMA address"] +pub mod hcdma; diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs new file mode 100644 index 0000000..d73f560 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs @@ -0,0 +1,215 @@ +#[doc = "Register `HCCHAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCCHAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `MPSIZ` writer - Maximum packet size"] +pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u16, u16, 11, O>; +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `EPNUM` writer - Endpoint number"] +pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 4, O>; +#[doc = "Field `EPDIR` reader - Endpoint direction"] +pub type EPDIR_R = crate::BitReader; +#[doc = "Field `EPDIR` writer - Endpoint direction"] +pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `LSDEV` reader - Low-speed device"] +pub type LSDEV_R = crate::BitReader; +#[doc = "Field `LSDEV` writer - Low-speed device"] +pub type LSDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `EPTYP` writer - Endpoint type"] +pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +#[doc = "Field `MC` reader - Multi Count (MC) / Error Count (EC)"] +pub type MC_R = crate::FieldReader; +#[doc = "Field `MC` writer - Multi Count (MC) / Error Count (EC)"] +pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +#[doc = "Field `DAD` reader - Device address"] +pub type DAD_R = crate::FieldReader; +#[doc = "Field `DAD` writer - Device address"] +pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 7, O>; +#[doc = "Field `ODDFRM` reader - Odd frame"] +pub type ODDFRM_R = crate::BitReader; +#[doc = "Field `ODDFRM` writer - Odd frame"] +pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `CHDIS` reader - Channel disable"] +pub type CHDIS_R = crate::BitReader; +#[doc = "Field `CHDIS` writer - Channel disable"] +pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `CHENA` reader - Channel enable"] +pub type CHENA_R = crate::BitReader; +#[doc = "Field `CHENA` writer - Channel enable"] +pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:14 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8) + } + #[doc = "Bit 15 - Endpoint direction"] + #[inline(always)] + pub fn epdir(&self) -> EPDIR_R { + EPDIR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Low-speed device"] + #[inline(always)] + pub fn lsdev(&self) -> LSDEV_R { + LSDEV_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] + #[inline(always)] + pub fn mc(&self) -> MC_R { + MC_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:28 - Device address"] + #[inline(always)] + pub fn dad(&self) -> DAD_R { + DAD_R::new(((self.bits >> 22) & 0x7f) as u8) + } + #[doc = "Bit 29 - Odd frame"] + #[inline(always)] + pub fn oddfrm(&self) -> ODDFRM_R { + ODDFRM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Channel disable"] + #[inline(always)] + pub fn chdis(&self) -> CHDIS_R { + CHDIS_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Channel enable"] + #[inline(always)] + pub fn chena(&self) -> CHENA_R { + CHENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + #[must_use] + pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + MPSIZ_W::new(self) + } + #[doc = "Bits 11:14 - Endpoint number"] + #[inline(always)] + #[must_use] + pub fn epnum(&mut self) -> EPNUM_W<11> { + EPNUM_W::new(self) + } + #[doc = "Bit 15 - Endpoint direction"] + #[inline(always)] + #[must_use] + pub fn epdir(&mut self) -> EPDIR_W<15> { + EPDIR_W::new(self) + } + #[doc = "Bit 17 - Low-speed device"] + #[inline(always)] + #[must_use] + pub fn lsdev(&mut self) -> LSDEV_W<17> { + LSDEV_W::new(self) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + #[must_use] + pub fn eptyp(&mut self) -> EPTYP_W<18> { + EPTYP_W::new(self) + } + #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] + #[inline(always)] + #[must_use] + pub fn mc(&mut self) -> MC_W<20> { + MC_W::new(self) + } + #[doc = "Bits 22:28 - Device address"] + #[inline(always)] + #[must_use] + pub fn dad(&mut self) -> DAD_W<22> { + DAD_W::new(self) + } + #[doc = "Bit 29 - Odd frame"] + #[inline(always)] + #[must_use] + pub fn oddfrm(&mut self) -> ODDFRM_W<29> { + ODDFRM_W::new(self) + } + #[doc = "Bit 30 - Channel disable"] + #[inline(always)] + #[must_use] + pub fn chdis(&mut self) -> CHDIS_W<30> { + CHDIS_W::new(self) + } + #[doc = "Bit 31 - Channel enable"] + #[inline(always)] + #[must_use] + pub fn chena(&mut self) -> CHENA_W<31> { + CHENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Characteristics register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcchar](index.html) module"] +pub struct HCCHAR_SPEC; +impl crate::RegisterSpec for HCCHAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcchar::R](R) reader structure"] +impl crate::Readable for HCCHAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcchar::W](W) writer structure"] +impl crate::Writable for HCCHAR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCCHAR to value 0"] +impl crate::Resettable for HCCHAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs new file mode 100644 index 0000000..bfcef2a --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HCDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcdma](index.html) module"] +pub struct HCDMA_SPEC; +impl crate::RegisterSpec for HCDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcdma::R](R) reader structure"] +impl crate::Readable for HCDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcdma::W](W) writer structure"] +impl crate::Writable for HCDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCDMA to value 0"] +impl crate::Resettable for HCDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs new file mode 100644 index 0000000..a8ef9ea --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs @@ -0,0 +1,230 @@ +#[doc = "Register `HCINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `CHH` reader - Channel halted"] +pub type CHH_R = crate::BitReader; +#[doc = "Field `CHH` writer - Channel halted"] +pub type CHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `AHBERR` reader - AHB error"] +pub type AHBERR_R = crate::BitReader; +#[doc = "Field `AHBERR` writer - AHB error"] +pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `STALL` reader - STALL response received interrupt"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `STALL` writer - STALL response received interrupt"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `NAK` reader - NAK response received interrupt"] +pub type NAK_R = crate::BitReader; +#[doc = "Field `NAK` writer - NAK response received interrupt"] +pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `ACK` reader - ACK response received/transmitted interrupt"] +pub type ACK_R = crate::BitReader; +#[doc = "Field `ACK` writer - ACK response received/transmitted interrupt"] +pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `NYET` reader - Response received interrupt"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - Response received interrupt"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `TXERR` reader - Transaction error"] +pub type TXERR_R = crate::BitReader; +#[doc = "Field `TXERR` writer - Transaction error"] +pub type TXERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `BBERR` reader - Babble error"] +pub type BBERR_R = crate::BitReader; +#[doc = "Field `BBERR` writer - Babble error"] +pub type BBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `FRMOR` reader - Frame overrun"] +pub type FRMOR_R = crate::BitReader; +#[doc = "Field `FRMOR` writer - Frame overrun"] +pub type FRMOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `DTERR` reader - Data toggle error"] +pub type DTERR_R = crate::BitReader; +#[doc = "Field `DTERR` writer - Data toggle error"] +pub type DTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel halted"] + #[inline(always)] + pub fn chh(&self) -> CHH_R { + CHH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + pub fn ahberr(&self) -> AHBERR_R { + AHBERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STALL response received interrupt"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NAK response received interrupt"] + #[inline(always)] + pub fn nak(&self) -> NAK_R { + NAK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt"] + #[inline(always)] + pub fn ack(&self) -> ACK_R { + ACK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Response received interrupt"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transaction error"] + #[inline(always)] + pub fn txerr(&self) -> TXERR_R { + TXERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Babble error"] + #[inline(always)] + pub fn bberr(&self) -> BBERR_R { + BBERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame overrun"] + #[inline(always)] + pub fn frmor(&self) -> FRMOR_R { + FRMOR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data toggle error"] + #[inline(always)] + pub fn dterr(&self) -> DTERR_R { + DTERR_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Channel halted"] + #[inline(always)] + #[must_use] + pub fn chh(&mut self) -> CHH_W<1> { + CHH_W::new(self) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + #[must_use] + pub fn ahberr(&mut self) -> AHBERR_W<2> { + AHBERR_W::new(self) + } + #[doc = "Bit 3 - STALL response received interrupt"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<3> { + STALL_W::new(self) + } + #[doc = "Bit 4 - NAK response received interrupt"] + #[inline(always)] + #[must_use] + pub fn nak(&mut self) -> NAK_W<4> { + NAK_W::new(self) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt"] + #[inline(always)] + #[must_use] + pub fn ack(&mut self) -> ACK_W<5> { + ACK_W::new(self) + } + #[doc = "Bit 6 - Response received interrupt"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<6> { + NYET_W::new(self) + } + #[doc = "Bit 7 - Transaction error"] + #[inline(always)] + #[must_use] + pub fn txerr(&mut self) -> TXERR_W<7> { + TXERR_W::new(self) + } + #[doc = "Bit 8 - Babble error"] + #[inline(always)] + #[must_use] + pub fn bberr(&mut self) -> BBERR_W<8> { + BBERR_W::new(self) + } + #[doc = "Bit 9 - Frame overrun"] + #[inline(always)] + #[must_use] + pub fn frmor(&mut self) -> FRMOR_W<9> { + FRMOR_W::new(self) + } + #[doc = "Bit 10 - Data toggle error"] + #[inline(always)] + #[must_use] + pub fn dterr(&mut self) -> DTERR_W<10> { + DTERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcint](index.html) module"] +pub struct HCINT_SPEC; +impl crate::RegisterSpec for HCINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcint::R](R) reader structure"] +impl crate::Readable for HCINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcint::W](W) writer structure"] +impl crate::Writable for HCINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCINT to value 0"] +impl crate::Resettable for HCINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs new file mode 100644 index 0000000..e158cb4 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs @@ -0,0 +1,230 @@ +#[doc = "Register `HCINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `CHHM` reader - Channel halted mask"] +pub type CHHM_R = crate::BitReader; +#[doc = "Field `CHHM` writer - Channel halted mask"] +pub type CHHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `AHBERR` reader - AHB error"] +pub type AHBERR_R = crate::BitReader; +#[doc = "Field `AHBERR` writer - AHB error"] +pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `STALLM` reader - STALL response received interrupt mask"] +pub type STALLM_R = crate::BitReader; +#[doc = "Field `STALLM` writer - STALL response received interrupt mask"] +pub type STALLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK response received interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK response received interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `ACKM` reader - ACK response received/transmitted interrupt mask"] +pub type ACKM_R = crate::BitReader; +#[doc = "Field `ACKM` writer - ACK response received/transmitted interrupt mask"] +pub type ACKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `NYET` reader - response received interrupt mask"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - response received interrupt mask"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `TXERRM` reader - Transaction error mask"] +pub type TXERRM_R = crate::BitReader; +#[doc = "Field `TXERRM` writer - Transaction error mask"] +pub type TXERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `BBERRM` reader - Babble error mask"] +pub type BBERRM_R = crate::BitReader; +#[doc = "Field `BBERRM` writer - Babble error mask"] +pub type BBERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `FRMORM` reader - Frame overrun mask"] +pub type FRMORM_R = crate::BitReader; +#[doc = "Field `FRMORM` writer - Frame overrun mask"] +pub type FRMORM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `DTERRM` reader - Data toggle error mask"] +pub type DTERRM_R = crate::BitReader; +#[doc = "Field `DTERRM` writer - Data toggle error mask"] +pub type DTERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel halted mask"] + #[inline(always)] + pub fn chhm(&self) -> CHHM_R { + CHHM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + pub fn ahberr(&self) -> AHBERR_R { + AHBERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STALL response received interrupt mask"] + #[inline(always)] + pub fn stallm(&self) -> STALLM_R { + STALLM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NAK response received interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] + #[inline(always)] + pub fn ackm(&self) -> ACKM_R { + ACKM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - response received interrupt mask"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transaction error mask"] + #[inline(always)] + pub fn txerrm(&self) -> TXERRM_R { + TXERRM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Babble error mask"] + #[inline(always)] + pub fn bberrm(&self) -> BBERRM_R { + BBERRM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame overrun mask"] + #[inline(always)] + pub fn frmorm(&self) -> FRMORM_R { + FRMORM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data toggle error mask"] + #[inline(always)] + pub fn dterrm(&self) -> DTERRM_R { + DTERRM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Channel halted mask"] + #[inline(always)] + #[must_use] + pub fn chhm(&mut self) -> CHHM_W<1> { + CHHM_W::new(self) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + #[must_use] + pub fn ahberr(&mut self) -> AHBERR_W<2> { + AHBERR_W::new(self) + } + #[doc = "Bit 3 - STALL response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn stallm(&mut self) -> STALLM_W<3> { + STALLM_W::new(self) + } + #[doc = "Bit 4 - NAK response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<4> { + NAKM_W::new(self) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] + #[inline(always)] + #[must_use] + pub fn ackm(&mut self) -> ACKM_W<5> { + ACKM_W::new(self) + } + #[doc = "Bit 6 - response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<6> { + NYET_W::new(self) + } + #[doc = "Bit 7 - Transaction error mask"] + #[inline(always)] + #[must_use] + pub fn txerrm(&mut self) -> TXERRM_W<7> { + TXERRM_W::new(self) + } + #[doc = "Bit 8 - Babble error mask"] + #[inline(always)] + #[must_use] + pub fn bberrm(&mut self) -> BBERRM_W<8> { + BBERRM_W::new(self) + } + #[doc = "Bit 9 - Frame overrun mask"] + #[inline(always)] + #[must_use] + pub fn frmorm(&mut self) -> FRMORM_W<9> { + FRMORM_W::new(self) + } + #[doc = "Bit 10 - Data toggle error mask"] + #[inline(always)] + #[must_use] + pub fn dterrm(&mut self) -> DTERRM_W<10> { + DTERRM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcintmsk](index.html) module"] +pub struct HCINTMSK_SPEC; +impl crate::RegisterSpec for HCINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcintmsk::R](R) reader structure"] +impl crate::Readable for HCINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcintmsk::W](W) writer structure"] +impl crate::Writable for HCINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCINTMSK to value 0"] +impl crate::Resettable for HCINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs new file mode 100644 index 0000000..b20ca79 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs @@ -0,0 +1,140 @@ +#[doc = "Register `HCSPLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCSPLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRTADDR` reader - Port address"] +pub type PRTADDR_R = crate::FieldReader; +#[doc = "Field `PRTADDR` writer - Port address"] +pub type PRTADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +#[doc = "Field `HUBADDR` reader - Hub address"] +pub type HUBADDR_R = crate::FieldReader; +#[doc = "Field `HUBADDR` writer - Hub address"] +pub type HUBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +#[doc = "Field `XACTPOS` reader - XACTPOS"] +pub type XACTPOS_R = crate::FieldReader; +#[doc = "Field `XACTPOS` writer - XACTPOS"] +pub type XACTPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 2, O>; +#[doc = "Field `COMPLSPLT` reader - Do complete split"] +pub type COMPLSPLT_R = crate::BitReader; +#[doc = "Field `COMPLSPLT` writer - Do complete split"] +pub type COMPLSPLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +#[doc = "Field `SPLITEN` reader - Split enable"] +pub type SPLITEN_R = crate::BitReader; +#[doc = "Field `SPLITEN` writer - Split enable"] +pub type SPLITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Port address"] + #[inline(always)] + pub fn prtaddr(&self) -> PRTADDR_R { + PRTADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Hub address"] + #[inline(always)] + pub fn hubaddr(&self) -> HUBADDR_R { + HUBADDR_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:15 - XACTPOS"] + #[inline(always)] + pub fn xactpos(&self) -> XACTPOS_R { + XACTPOS_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - Do complete split"] + #[inline(always)] + pub fn complsplt(&self) -> COMPLSPLT_R { + COMPLSPLT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 31 - Split enable"] + #[inline(always)] + pub fn spliten(&self) -> SPLITEN_R { + SPLITEN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Port address"] + #[inline(always)] + #[must_use] + pub fn prtaddr(&mut self) -> PRTADDR_W<0> { + PRTADDR_W::new(self) + } + #[doc = "Bits 7:13 - Hub address"] + #[inline(always)] + #[must_use] + pub fn hubaddr(&mut self) -> HUBADDR_W<7> { + HUBADDR_W::new(self) + } + #[doc = "Bits 14:15 - XACTPOS"] + #[inline(always)] + #[must_use] + pub fn xactpos(&mut self) -> XACTPOS_W<14> { + XACTPOS_W::new(self) + } + #[doc = "Bit 16 - Do complete split"] + #[inline(always)] + #[must_use] + pub fn complsplt(&mut self) -> COMPLSPLT_W<16> { + COMPLSPLT_W::new(self) + } + #[doc = "Bit 31 - Split enable"] + #[inline(always)] + #[must_use] + pub fn spliten(&mut self) -> SPLITEN_W<31> { + SPLITEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Split control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcsplt](index.html) module"] +pub struct HCSPLT_SPEC; +impl crate::RegisterSpec for HCSPLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcsplt::R](R) reader structure"] +impl crate::Readable for HCSPLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcsplt::W](W) writer structure"] +impl crate::Writable for HCSPLT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCSPLT to value 0"] +impl crate::Resettable for HCSPLT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs new file mode 100644 index 0000000..a7361fd --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs @@ -0,0 +1,110 @@ +#[doc = "Register `HCTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u32, u32, 19, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::FieldReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u16, u16, 10, O>; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `DPID` writer - Data PID"] +pub type DPID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:18 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new(self.bits & 0x0007_ffff) + } + #[doc = "Bits 19:28 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 0x03ff) as u16) + } + #[doc = "Bits 29:30 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 29) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:18 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bits 19:28 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Bits 29:30 - Data PID"] + #[inline(always)] + #[must_use] + pub fn dpid(&mut self) -> DPID_W<29> { + DPID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctsiz](index.html) module"] +pub struct HCTSIZ_SPEC; +impl crate::RegisterSpec for HCTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hctsiz::R](R) reader structure"] +impl crate::Readable for HCTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hctsiz::W](W) writer structure"] +impl crate::Writable for HCTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCTSIZ to value 0"] +impl crate::Resettable for HCTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs b/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs new file mode 100644 index 0000000..cb893f3 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs @@ -0,0 +1,228 @@ +#[doc = "Register `HPRT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPRT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PCSTS` reader - Port connect status"] +pub type PCSTS_R = crate::BitReader; +#[doc = "Field `PCDET` reader - Port connect detected"] +pub type PCDET_R = crate::BitReader; +#[doc = "Field `PCDET` writer - Port connect detected"] +pub type PCDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PENA` reader - Port enable"] +pub type PENA_R = crate::BitReader; +#[doc = "Field `PENA` writer - Port enable"] +pub type PENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PENCHNG` reader - Port enable/disable change"] +pub type PENCHNG_R = crate::BitReader; +#[doc = "Field `PENCHNG` writer - Port enable/disable change"] +pub type PENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `POCA` reader - Port overcurrent active"] +pub type POCA_R = crate::BitReader; +#[doc = "Field `POCCHNG` reader - Port overcurrent change"] +pub type POCCHNG_R = crate::BitReader; +#[doc = "Field `POCCHNG` writer - Port overcurrent change"] +pub type POCCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PRES` reader - Port resume"] +pub type PRES_R = crate::BitReader; +#[doc = "Field `PRES` writer - Port resume"] +pub type PRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PSUSP` reader - Port suspend"] +pub type PSUSP_R = crate::BitReader; +#[doc = "Field `PSUSP` writer - Port suspend"] +pub type PSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PRST` reader - Port reset"] +pub type PRST_R = crate::BitReader; +#[doc = "Field `PRST` writer - Port reset"] +pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PLSTS` reader - Port line status"] +pub type PLSTS_R = crate::FieldReader; +#[doc = "Field `PPWR` reader - Port power"] +pub type PPWR_R = crate::BitReader; +#[doc = "Field `PPWR` writer - Port power"] +pub type PPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PTCTL` reader - Port test control"] +pub type PTCTL_R = crate::FieldReader; +#[doc = "Field `PTCTL` writer - Port test control"] +pub type PTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, u8, 4, O>; +#[doc = "Field `PSPD` reader - Port speed"] +pub type PSPD_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Port connect status"] + #[inline(always)] + pub fn pcsts(&self) -> PCSTS_R { + PCSTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port connect detected"] + #[inline(always)] + pub fn pcdet(&self) -> PCDET_R { + PCDET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port enable"] + #[inline(always)] + pub fn pena(&self) -> PENA_R { + PENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port enable/disable change"] + #[inline(always)] + pub fn penchng(&self) -> PENCHNG_R { + PENCHNG_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port overcurrent active"] + #[inline(always)] + pub fn poca(&self) -> POCA_R { + POCA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port overcurrent change"] + #[inline(always)] + pub fn pocchng(&self) -> POCCHNG_R { + POCCHNG_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port resume"] + #[inline(always)] + pub fn pres(&self) -> PRES_R { + PRES_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port suspend"] + #[inline(always)] + pub fn psusp(&self) -> PSUSP_R { + PSUSP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port reset"] + #[inline(always)] + pub fn prst(&self) -> PRST_R { + PRST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 10:11 - Port line status"] + #[inline(always)] + pub fn plsts(&self) -> PLSTS_R { + PLSTS_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Port power"] + #[inline(always)] + pub fn ppwr(&self) -> PPWR_R { + PPWR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - Port test control"] + #[inline(always)] + pub fn ptctl(&self) -> PTCTL_R { + PTCTL_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:18 - Port speed"] + #[inline(always)] + pub fn pspd(&self) -> PSPD_R { + PSPD_R::new(((self.bits >> 17) & 3) as u8) + } +} +impl W { + #[doc = "Bit 1 - Port connect detected"] + #[inline(always)] + #[must_use] + pub fn pcdet(&mut self) -> PCDET_W<1> { + PCDET_W::new(self) + } + #[doc = "Bit 2 - Port enable"] + #[inline(always)] + #[must_use] + pub fn pena(&mut self) -> PENA_W<2> { + PENA_W::new(self) + } + #[doc = "Bit 3 - Port enable/disable change"] + #[inline(always)] + #[must_use] + pub fn penchng(&mut self) -> PENCHNG_W<3> { + PENCHNG_W::new(self) + } + #[doc = "Bit 5 - Port overcurrent change"] + #[inline(always)] + #[must_use] + pub fn pocchng(&mut self) -> POCCHNG_W<5> { + POCCHNG_W::new(self) + } + #[doc = "Bit 6 - Port resume"] + #[inline(always)] + #[must_use] + pub fn pres(&mut self) -> PRES_W<6> { + PRES_W::new(self) + } + #[doc = "Bit 7 - Port suspend"] + #[inline(always)] + #[must_use] + pub fn psusp(&mut self) -> PSUSP_W<7> { + PSUSP_W::new(self) + } + #[doc = "Bit 8 - Port reset"] + #[inline(always)] + #[must_use] + pub fn prst(&mut self) -> PRST_W<8> { + PRST_W::new(self) + } + #[doc = "Bit 12 - Port power"] + #[inline(always)] + #[must_use] + pub fn ppwr(&mut self) -> PPWR_W<12> { + PPWR_W::new(self) + } + #[doc = "Bits 13:16 - Port test control"] + #[inline(always)] + #[must_use] + pub fn ptctl(&mut self) -> PTCTL_W<13> { + PTCTL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host port control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"] +pub struct HPRT_SPEC; +impl crate::RegisterSpec for HPRT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hprt::R](R) reader structure"] +impl crate::Readable for HPRT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"] +impl crate::Writable for HPRT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPRT to value 0"] +impl crate::Resettable for HPRT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs b/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs new file mode 100644 index 0000000..3cb5895 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs @@ -0,0 +1,94 @@ +#[doc = "Register `HPTXSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPTXSTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTXFSAVL` reader - Periodic transmit data FIFO space available"] +pub type PTXFSAVL_R = crate::FieldReader; +#[doc = "Field `PTXFSAVL` writer - Periodic transmit data FIFO space available"] +pub type PTXFSAVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXSTS_SPEC, u16, u16, 16, O>; +#[doc = "Field `PTXQSAV` reader - Periodic transmit request queue space available"] +pub type PTXQSAV_R = crate::FieldReader; +#[doc = "Field `PTXQTOP` reader - Top of the periodic transmit request queue"] +pub type PTXQTOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] + #[inline(always)] + pub fn ptxfsavl(&self) -> PTXFSAVL_R { + PTXFSAVL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Periodic transmit request queue space available"] + #[inline(always)] + pub fn ptxqsav(&self) -> PTXQSAV_R { + PTXQSAV_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Top of the periodic transmit request queue"] + #[inline(always)] + pub fn ptxqtop(&self) -> PTXQTOP_R { + PTXQTOP_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] + #[inline(always)] + #[must_use] + pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<0> { + PTXFSAVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Host periodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](index.html) module"] +pub struct HPTXSTS_SPEC; +impl crate::RegisterSpec for HPTXSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hptxsts::R](R) reader structure"] +impl crate::Readable for HPTXSTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hptxsts::W](W) writer structure"] +impl crate::Writable for HPTXSTS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPTXSTS to value 0x0008_0100"] +impl crate::Resettable for HPTXSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0100; +} diff --git a/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs b/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs new file mode 100644 index 0000000..67a9eb5 --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - power and clock gating control"] + pub pcgcctl: PCGCCTL, +} +#[doc = "PCGCCTL (rw) register accessor: an alias for `Reg`"] +pub type PCGCCTL = crate::Reg; +#[doc = "power and clock gating control"] +pub mod pcgcctl; diff --git a/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs b/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs new file mode 100644 index 0000000..061312d --- /dev/null +++ b/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs @@ -0,0 +1,293 @@ +#[doc = "Register `PCGCCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCGCCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STPPCLK` reader - Stop PHY clock"] +pub type STPPCLK_R = crate::BitReader; +#[doc = "Field `STPPCLK` writer - Stop PHY clock"] +pub type STPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `GATEHCLK` reader - Gate HCLK"] +pub type GATEHCLK_R = crate::BitReader; +#[doc = "Field `GATEHCLK` writer - Gate HCLK"] +pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PWRCLMP` reader - Power clamp"] +pub type PWRCLMP_R = crate::BitReader; +#[doc = "Field `PWRCLMP` writer - Power clamp"] +pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RSTPDWNMODULE` reader - Power down modules"] +pub type RSTPDWNMODULE_R = crate::BitReader; +#[doc = "Field `RSTPDWNMODULE` writer - Power down modules"] +pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PHYSUSP` reader - PHY Suspended"] +pub type PHYSUSP_R = crate::BitReader; +#[doc = "Field `PHYSUSP` writer - PHY Suspended"] +pub type PHYSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ENABLE_L1GATING` reader - Enable sleep clock gating"] +pub type ENABLE_L1GATING_R = crate::BitReader; +#[doc = "Field `ENABLE_L1GATING` writer - Enable sleep clock gating"] +pub type ENABLE_L1GATING_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PHYSLEEP` reader - PHY is in sleep mode"] +pub type PHYSLEEP_R = crate::BitReader; +#[doc = "Field `PHYSLEEP` writer - PHY is in sleep mode"] +pub type PHYSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `DEEPSLEEP` reader - PHY is in deep sleep"] +pub type DEEPSLEEP_R = crate::BitReader; +#[doc = "Field `DEEPSLEEP` writer - PHY is in deep sleep"] +pub type DEEPSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"] +pub type RESETAFTERSUSP_R = crate::BitReader; +#[doc = "Field `RESETAFTERSUSP` writer - Reset after suspend"] +pub type RESETAFTERSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESTOREMODE` reader - Restore mode"] +pub type RESTOREMODE_R = crate::BitReader; +#[doc = "Field `RESTOREMODE` writer - Restore mode"] +pub type RESTOREMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ENEXTNDEDHIBER` reader - Enable extended hibernation"] +pub type ENEXTNDEDHIBER_R = crate::BitReader; +#[doc = "Field `ENEXTNDEDHIBER` writer - Enable extended hibernation"] +pub type ENEXTNDEDHIBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `EXTNDEDHIBERNATIONCLAMP` reader - Extended hibernation clamp"] +pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; +#[doc = "Field `EXTNDEDHIBERNATIONCLAMP` writer - Extended hibernation clamp"] +pub type EXTNDEDHIBERNATIONCLAMP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `EXTNDEDHIBERNATIONSWITCH` reader - Extended hibernation switch"] +pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; +#[doc = "Field `EXTNDEDHIBERNATIONSWITCH` writer - Extended hibernation switch"] +pub type EXTNDEDHIBERNATIONSWITCH_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ESSREGRESTORED` reader - Essential register values restored"] +pub type ESSREGRESTORED_R = crate::BitReader; +#[doc = "Field `ESSREGRESTORED` writer - Essential register values restored"] +pub type ESSREGRESTORED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESTORE_VALUE` reader - Restore value"] +pub type RESTORE_VALUE_R = crate::FieldReader; +#[doc = "Field `RESTORE_VALUE` writer - Restore value"] +pub type RESTORE_VALUE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PCGCCTL_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bit 0 - Stop PHY clock"] + #[inline(always)] + pub fn stppclk(&self) -> STPPCLK_R { + STPPCLK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gate HCLK"] + #[inline(always)] + pub fn gatehclk(&self) -> GATEHCLK_R { + GATEHCLK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Power clamp"] + #[inline(always)] + pub fn pwrclmp(&self) -> PWRCLMP_R { + PWRCLMP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Power down modules"] + #[inline(always)] + pub fn rstpdwnmodule(&self) -> RSTPDWNMODULE_R { + RSTPDWNMODULE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PHY Suspended"] + #[inline(always)] + pub fn physusp(&self) -> PHYSUSP_R { + PHYSUSP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable sleep clock gating"] + #[inline(always)] + pub fn enable_l1gating(&self) -> ENABLE_L1GATING_R { + ENABLE_L1GATING_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - PHY is in sleep mode"] + #[inline(always)] + pub fn physleep(&self) -> PHYSLEEP_R { + PHYSLEEP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - PHY is in deep sleep"] + #[inline(always)] + pub fn deepsleep(&self) -> DEEPSLEEP_R { + DEEPSLEEP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reset after suspend"] + #[inline(always)] + pub fn resetaftersusp(&self) -> RESETAFTERSUSP_R { + RESETAFTERSUSP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Restore mode"] + #[inline(always)] + pub fn restoremode(&self) -> RESTOREMODE_R { + RESTOREMODE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable extended hibernation"] + #[inline(always)] + pub fn enextndedhiber(&self) -> ENEXTNDEDHIBER_R { + ENEXTNDEDHIBER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Extended hibernation clamp"] + #[inline(always)] + pub fn extndedhibernationclamp(&self) -> EXTNDEDHIBERNATIONCLAMP_R { + EXTNDEDHIBERNATIONCLAMP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Extended hibernation switch"] + #[inline(always)] + pub fn extndedhibernationswitch(&self) -> EXTNDEDHIBERNATIONSWITCH_R { + EXTNDEDHIBERNATIONSWITCH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Essential register values restored"] + #[inline(always)] + pub fn essregrestored(&self) -> ESSREGRESTORED_R { + ESSREGRESTORED_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:31 - Restore value"] + #[inline(always)] + pub fn restore_value(&self) -> RESTORE_VALUE_R { + RESTORE_VALUE_R::new((self.bits >> 14) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bit 0 - Stop PHY clock"] + #[inline(always)] + #[must_use] + pub fn stppclk(&mut self) -> STPPCLK_W<0> { + STPPCLK_W::new(self) + } + #[doc = "Bit 1 - Gate HCLK"] + #[inline(always)] + #[must_use] + pub fn gatehclk(&mut self) -> GATEHCLK_W<1> { + GATEHCLK_W::new(self) + } + #[doc = "Bit 2 - Power clamp"] + #[inline(always)] + #[must_use] + pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> { + PWRCLMP_W::new(self) + } + #[doc = "Bit 3 - Power down modules"] + #[inline(always)] + #[must_use] + pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> { + RSTPDWNMODULE_W::new(self) + } + #[doc = "Bit 4 - PHY Suspended"] + #[inline(always)] + #[must_use] + pub fn physusp(&mut self) -> PHYSUSP_W<4> { + PHYSUSP_W::new(self) + } + #[doc = "Bit 5 - Enable sleep clock gating"] + #[inline(always)] + #[must_use] + pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W<5> { + ENABLE_L1GATING_W::new(self) + } + #[doc = "Bit 6 - PHY is in sleep mode"] + #[inline(always)] + #[must_use] + pub fn physleep(&mut self) -> PHYSLEEP_W<6> { + PHYSLEEP_W::new(self) + } + #[doc = "Bit 7 - PHY is in deep sleep"] + #[inline(always)] + #[must_use] + pub fn deepsleep(&mut self) -> DEEPSLEEP_W<7> { + DEEPSLEEP_W::new(self) + } + #[doc = "Bit 8 - Reset after suspend"] + #[inline(always)] + #[must_use] + pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<8> { + RESETAFTERSUSP_W::new(self) + } + #[doc = "Bit 9 - Restore mode"] + #[inline(always)] + #[must_use] + pub fn restoremode(&mut self) -> RESTOREMODE_W<9> { + RESTOREMODE_W::new(self) + } + #[doc = "Bit 10 - Enable extended hibernation"] + #[inline(always)] + #[must_use] + pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W<10> { + ENEXTNDEDHIBER_W::new(self) + } + #[doc = "Bit 11 - Extended hibernation clamp"] + #[inline(always)] + #[must_use] + pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W<11> { + EXTNDEDHIBERNATIONCLAMP_W::new(self) + } + #[doc = "Bit 12 - Extended hibernation switch"] + #[inline(always)] + #[must_use] + pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W<12> { + EXTNDEDHIBERNATIONSWITCH_W::new(self) + } + #[doc = "Bit 13 - Essential register values restored"] + #[inline(always)] + #[must_use] + pub fn essregrestored(&mut self) -> ESSREGRESTORED_W<13> { + ESSREGRESTORED_W::new(self) + } + #[doc = "Bits 14:31 - Restore value"] + #[inline(always)] + #[must_use] + pub fn restore_value(&mut self) -> RESTORE_VALUE_W<14> { + RESTORE_VALUE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "power and clock gating control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"] +pub struct PCGCCTL_SPEC; +impl crate::RegisterSpec for PCGCCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"] +impl crate::Readable for PCGCCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"] +impl crate::Writable for PCGCCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCGCCTL to value 0x200b_8000"] +impl crate::Resettable for PCGCCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x200b_8000; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox.rs b/crates/bcm2835-lpa/src/vcmailbox.rs new file mode 100644 index 0000000..7490467 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox.rs @@ -0,0 +1,66 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Read messages from the VideoCore"] + pub read: READ, + _reserved1: [u8; 0x0c], + #[doc = "0x10 - "] + pub peek0: PEEK0, + #[doc = "0x14 - "] + pub sender0: SENDER0, + #[doc = "0x18 - "] + pub status0: STATUS0, + #[doc = "0x1c - "] + pub config0: CONFIG0, + #[doc = "0x20 - Write messages to the VideoCore"] + pub write: WRITE, + _reserved6: [u8; 0x0c], + #[doc = "0x30 - "] + pub peek1: PEEK1, + #[doc = "0x34 - "] + pub sender1: SENDER1, + #[doc = "0x38 - "] + pub status1: STATUS1, + #[doc = "0x3c - "] + pub config1: CONFIG1, +} +#[doc = "READ (r) register accessor: an alias for `Reg`"] +pub type READ = crate::Reg; +#[doc = "Read messages from the VideoCore"] +pub mod read; +#[doc = "PEEK0 (rw) register accessor: an alias for `Reg`"] +pub type PEEK0 = crate::Reg; +#[doc = ""] +pub mod peek0; +#[doc = "SENDER0 (rw) register accessor: an alias for `Reg`"] +pub type SENDER0 = crate::Reg; +#[doc = ""] +pub mod sender0; +#[doc = "STATUS0 (r) register accessor: an alias for `Reg`"] +pub type STATUS0 = crate::Reg; +#[doc = ""] +pub mod status0; +#[doc = "CONFIG0 (rw) register accessor: an alias for `Reg`"] +pub type CONFIG0 = crate::Reg; +#[doc = ""] +pub mod config0; +#[doc = "WRITE (w) register accessor: an alias for `Reg`"] +pub type WRITE = crate::Reg; +#[doc = "Write messages to the VideoCore"] +pub mod write; +#[doc = "PEEK1 (rw) register accessor: an alias for `Reg`"] +pub type PEEK1 = crate::Reg; +#[doc = ""] +pub mod peek1; +#[doc = "SENDER1 (rw) register accessor: an alias for `Reg`"] +pub type SENDER1 = crate::Reg; +#[doc = ""] +pub mod sender1; +#[doc = "STATUS1 (rw) register accessor: an alias for `Reg`"] +pub type STATUS1 = crate::Reg; +#[doc = ""] +pub mod status1; +#[doc = "CONFIG1 (rw) register accessor: an alias for `Reg`"] +pub type CONFIG1 = crate::Reg; +#[doc = ""] +pub mod config1; diff --git a/crates/bcm2835-lpa/src/vcmailbox/config0.rs b/crates/bcm2835-lpa/src/vcmailbox/config0.rs new file mode 100644 index 0000000..dce060f --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/config0.rs @@ -0,0 +1,76 @@ +#[doc = "Register `CONFIG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IRQEN` reader - Enable the interrupt when data is available"] +pub type IRQEN_R = crate::BitReader; +#[doc = "Field `IRQEN` writer - Enable the interrupt when data is available"] +pub type IRQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable the interrupt when data is available"] + #[inline(always)] + pub fn irqen(&self) -> IRQEN_R { + IRQEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the interrupt when data is available"] + #[inline(always)] + #[must_use] + pub fn irqen(&mut self) -> IRQEN_W<0> { + IRQEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config0](index.html) module"] +pub struct CONFIG0_SPEC; +impl crate::RegisterSpec for CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config0::R](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config0::W](W) writer structure"] +impl crate::Writable for CONFIG0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/config1.rs b/crates/bcm2835-lpa/src/vcmailbox/config1.rs new file mode 100644 index 0000000..3c238a6 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/config1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `CONFIG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config1](index.html) module"] +pub struct CONFIG1_SPEC; +impl crate::RegisterSpec for CONFIG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config1::R](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config1::W](W) writer structure"] +impl crate::Writable for CONFIG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/peek0.rs b/crates/bcm2835-lpa/src/vcmailbox/peek0.rs new file mode 100644 index 0000000..3b63843 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/peek0.rs @@ -0,0 +1,59 @@ +#[doc = "Register `PEEK0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PEEK0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek0](index.html) module"] +pub struct PEEK0_SPEC; +impl crate::RegisterSpec for PEEK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek0::R](R) reader structure"] +impl crate::Readable for PEEK0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peek0::W](W) writer structure"] +impl crate::Writable for PEEK0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/peek1.rs b/crates/bcm2835-lpa/src/vcmailbox/peek1.rs new file mode 100644 index 0000000..2431cc4 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/peek1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `PEEK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PEEK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek1](index.html) module"] +pub struct PEEK1_SPEC; +impl crate::RegisterSpec for PEEK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek1::R](R) reader structure"] +impl crate::Readable for PEEK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peek1::W](W) writer structure"] +impl crate::Writable for PEEK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/read.rs b/crates/bcm2835-lpa/src/vcmailbox/read.rs new file mode 100644 index 0000000..60b2d04 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/read.rs @@ -0,0 +1,24 @@ +#[doc = "Register `READ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Read messages from the VideoCore\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [read](index.html) module"] +pub struct READ_SPEC; +impl crate::RegisterSpec for READ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [read::R](R) reader structure"] +impl crate::Readable for READ_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/sender0.rs b/crates/bcm2835-lpa/src/vcmailbox/sender0.rs new file mode 100644 index 0000000..cbeb2f1 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/sender0.rs @@ -0,0 +1,59 @@ +#[doc = "Register `SENDER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SENDER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender0](index.html) module"] +pub struct SENDER0_SPEC; +impl crate::RegisterSpec for SENDER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sender0::R](R) reader structure"] +impl crate::Readable for SENDER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sender0::W](W) writer structure"] +impl crate::Writable for SENDER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/sender1.rs b/crates/bcm2835-lpa/src/vcmailbox/sender1.rs new file mode 100644 index 0000000..1537c2d --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/sender1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `SENDER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SENDER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender1](index.html) module"] +pub struct SENDER1_SPEC; +impl crate::RegisterSpec for SENDER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sender1::R](R) reader structure"] +impl crate::Readable for SENDER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sender1::W](W) writer structure"] +impl crate::Writable for SENDER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/status0.rs b/crates/bcm2835-lpa/src/vcmailbox/status0.rs new file mode 100644 index 0000000..035e2a4 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/status0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `STATUS0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EMPTY` reader - "] +pub type EMPTY_R = crate::BitReader; +#[doc = "Field `FULL` reader - "] +pub type FULL_R = crate::BitReader; +impl R { + #[doc = "Bit 30"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status0](index.html) module"] +pub struct STATUS0_SPEC; +impl crate::RegisterSpec for STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status0::R](R) reader structure"] +impl crate::Readable for STATUS0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/status1.rs b/crates/bcm2835-lpa/src/vcmailbox/status1.rs new file mode 100644 index 0000000..1a7b501 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/status1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `STATUS1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status1](index.html) module"] +pub struct STATUS1_SPEC; +impl crate::RegisterSpec for STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status1::R](R) reader structure"] +impl crate::Readable for STATUS1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status1::W](W) writer structure"] +impl crate::Writable for STATUS1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2835-lpa/src/vcmailbox/write.rs b/crates/bcm2835-lpa/src/vcmailbox/write.rs new file mode 100644 index 0000000..4e09735 --- /dev/null +++ b/crates/bcm2835-lpa/src/vcmailbox/write.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WRITE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write messages to the VideoCore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [write](index.html) module"] +pub struct WRITE_SPEC; +impl crate::RegisterSpec for WRITE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [write::W](W) writer structure"] +impl crate::Writable for WRITE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/.gitignore b/crates/bcm2837-lpa/.gitignore new file mode 100644 index 0000000..4fffb2f --- /dev/null +++ b/crates/bcm2837-lpa/.gitignore @@ -0,0 +1,2 @@ +/target +/Cargo.lock diff --git a/crates/bcm2837-lpa/Cargo.toml b/crates/bcm2837-lpa/Cargo.toml new file mode 100644 index 0000000..ba2bbb0 --- /dev/null +++ b/crates/bcm2837-lpa/Cargo.toml @@ -0,0 +1,19 @@ +[package] +name = "bcm2837-lpa" +version = "0.1.0" +authors = ["Po-Yi Tsai "] +edition = "2021" +rust-version = "1.61.0" +description = "Peripheral access crate for BCM2837 found in the Raspberry Pi 3 and Zero 2W." +repository = "https://github.com/abt8601/raspi-pacs" +license = "Unlicense" +keywords = ["raspberrypi", "bcm2837", "pac"] +categories = ["embedded", "hardware-support", "no-std", "no-std::no-alloc"] + +[dependencies] +critical-section = { version = "1.0", optional = true } +vcell = "0.1.0" +portable-atomic = { version = "0.3.16", default-features = false } + +[features] +rt = [] diff --git a/crates/bcm2837-lpa/README.md b/crates/bcm2837-lpa/README.md new file mode 100644 index 0000000..dee6828 --- /dev/null +++ b/crates/bcm2837-lpa/README.md @@ -0,0 +1,16 @@ +# bcm2837-lpa + +[![crates.io](https://img.shields.io/crates/v/bcm2837-lpa.svg)](https://crates.io/crates/bcm2837-lpa) +[![docs.rs](https://img.shields.io/docsrs/bcm2837-lpa)](https://docs.rs/bcm2837-lpa) + +Peripheral access crate for BCM2837 found in the Raspberry Pi 3 and Zero 2W. + +This crate is generated by [`svd2rust`](https://crates.io/crates/svd2rust) +from the +[SVD file](https://github.com/abt8601/broadcom-peripherals/blob/6bc44a4fd5c956249b9d8815f66a9df41b5791b1/svd/gen/bcm2837_lpa.svd) +in +[`abt8601/broadcom-peripherals@6bc44a4`](https://github.com/abt8601/broadcom-peripherals/tree/6bc44a4fd5c956249b9d8815f66a9df41b5791b1), +which is based on that in +[`adafruit/broadcom-peripherals@d3a6b50`](https://github.com/adafruit/broadcom-peripherals/tree/d3a6b50a21e7dd49ba4bfa0374da3407594caa50). +(The SVD files in these two repositories are identical, +save that that in the former has the missing tags required by `svd2rust`.) diff --git a/crates/bcm2837-lpa/src/aux.rs b/crates/bcm2837-lpa/src/aux.rs new file mode 100644 index 0000000..5380cb2 --- /dev/null +++ b/crates/bcm2837-lpa/src/aux.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt status"] + pub irq: IRQ, + #[doc = "0x04 - Enable sub-peripherals"] + pub enables: ENABLES, +} +#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +pub type IRQ = crate::Reg; +#[doc = "Interrupt status"] +pub mod irq; +#[doc = "ENABLES (rw) register accessor: an alias for `Reg`"] +pub type ENABLES = crate::Reg; +#[doc = "Enable sub-peripherals"] +pub mod enables; diff --git a/crates/bcm2837-lpa/src/aux/enables.rs b/crates/bcm2837-lpa/src/aux/enables.rs new file mode 100644 index 0000000..eb9fc6d --- /dev/null +++ b/crates/bcm2837-lpa/src/aux/enables.rs @@ -0,0 +1,110 @@ +#[doc = "Register `ENABLES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLES` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UART_1` reader - UART1 enabled"] +pub type UART_1_R = crate::BitReader; +#[doc = "Field `UART_1` writer - UART1 enabled"] +pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 enabled"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 enabled"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 enabled"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 enabled"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UART1 enabled"] + #[inline(always)] + pub fn uart_1(&self) -> UART_1_R { + UART_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 enabled"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 enabled"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART1 enabled"] + #[inline(always)] + #[must_use] + pub fn uart_1(&mut self) -> UART_1_W<0> { + UART_1_W::new(self) + } + #[doc = "Bit 1 - SPI1 enabled"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 enabled"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"] +pub struct ENABLES_SPEC; +impl crate::RegisterSpec for ENABLES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enables::R](R) reader structure"] +impl crate::Readable for ENABLES_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"] +impl crate::Writable for ENABLES_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLES to value 0"] +impl crate::Resettable for ENABLES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/aux/irq.rs b/crates/bcm2837-lpa/src/aux/irq.rs new file mode 100644 index 0000000..a59c319 --- /dev/null +++ b/crates/bcm2837-lpa/src/aux/irq.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IRQ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UART_1` reader - UART1 interrupt active"] +pub type UART_1_R = crate::BitReader; +#[doc = "Field `UART_1` writer - UART1 interrupt active"] +pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +#[doc = "Field `SPI_1` reader - SPI1 interrupt active"] +pub type SPI_1_R = crate::BitReader; +#[doc = "Field `SPI_1` writer - SPI1 interrupt active"] +pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +#[doc = "Field `SPI_2` reader - SPI2 interrupt active"] +pub type SPI_2_R = crate::BitReader; +#[doc = "Field `SPI_2` writer - SPI2 interrupt active"] +pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UART1 interrupt active"] + #[inline(always)] + pub fn uart_1(&self) -> UART_1_R { + UART_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + pub fn spi_1(&self) -> SPI_1_R { + SPI_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + pub fn spi_2(&self) -> SPI_2_R { + SPI_2_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn uart_1(&mut self) -> UART_1_W<0> { + UART_1_W::new(self) + } + #[doc = "Bit 1 - SPI1 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_1(&mut self) -> SPI_1_W<1> { + SPI_1_W::new(self) + } + #[doc = "Bit 2 - SPI2 interrupt active"] + #[inline(always)] + #[must_use] + pub fn spi_2(&mut self) -> SPI_2_W<2> { + SPI_2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"] +pub struct IRQ_SPEC; +impl crate::RegisterSpec for IRQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq::R](R) reader structure"] +impl crate::Readable for IRQ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +impl crate::Writable for IRQ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRQ to value 0"] +impl crate::Resettable for IRQ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/bsc0.rs b/crates/bcm2837-lpa/src/bsc0.rs new file mode 100644 index 0000000..8ccfb52 --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub c: C, + #[doc = "0x04 - Status"] + pub s: S, + #[doc = "0x08 - Data length"] + pub dlen: DLEN, + #[doc = "0x0c - Slave address"] + pub a: A, + #[doc = "0x10 - Data FIFO"] + pub fifo: FIFO, + #[doc = "0x14 - Clock divider"] + pub div: DIV, + #[doc = "0x18 - Data delay (Values must be under CDIV / 2)"] + pub del: DEL, + #[doc = "0x1c - Clock stretch timeout (broken on 283x)"] + pub clkt: CLKT, +} +#[doc = "C (rw) register accessor: an alias for `Reg`"] +pub type C = crate::Reg; +#[doc = "Control"] +pub mod c; +#[doc = "S (rw) register accessor: an alias for `Reg`"] +pub type S = crate::Reg; +#[doc = "Status"] +pub mod s; +#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +pub type DLEN = crate::Reg; +#[doc = "Data length"] +pub mod dlen; +#[doc = "A (rw) register accessor: an alias for `Reg`"] +pub type A = crate::Reg; +#[doc = "Slave address"] +pub mod a; +#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +pub type FIFO = crate::Reg; +#[doc = "Data FIFO"] +pub mod fifo; +#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +pub type DIV = crate::Reg; +#[doc = "Clock divider"] +pub mod div; +#[doc = "DEL (rw) register accessor: an alias for `Reg`"] +pub type DEL = crate::Reg; +#[doc = "Data delay (Values must be under CDIV / 2)"] +pub mod del; +#[doc = "CLKT (rw) register accessor: an alias for `Reg`"] +pub type CLKT = crate::Reg; +#[doc = "Clock stretch timeout (broken on 283x)"] +pub mod clkt; diff --git a/crates/bcm2837-lpa/src/bsc0/a.rs b/crates/bcm2837-lpa/src/bsc0/a.rs new file mode 100644 index 0000000..d98d147 --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/a.rs @@ -0,0 +1,80 @@ +#[doc = "Register `A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Slave address"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Slave address"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, A_SPEC, u8, u8, 7, O>; +impl R { + #[doc = "Bits 0:6 - Slave address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Slave address"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<0> { + ADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [a](index.html) module"] +pub struct A_SPEC; +impl crate::RegisterSpec for A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [a::R](R) reader structure"] +impl crate::Readable for A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [a::W](W) writer structure"] +impl crate::Writable for A_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A to value 0"] +impl crate::Resettable for A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/bsc0/c.rs b/crates/bcm2837-lpa/src/bsc0/c.rs new file mode 100644 index 0000000..f62d48d --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/c.rs @@ -0,0 +1,170 @@ +#[doc = "Register `C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READ` reader - Transfer is read"] +pub type READ_R = crate::BitReader; +#[doc = "Field `READ` writer - Transfer is read"] +pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `CLEAR` reader - Clear the FIFO"] +pub type CLEAR_R = crate::FieldReader; +#[doc = "Field `CLEAR` writer - Clear the FIFO"] +pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, C_SPEC, u8, u8, 2, O>; +#[doc = "Field `ST` reader - Start transfer"] +pub type ST_R = crate::BitReader; +#[doc = "Field `ST` writer - Start transfer"] +pub type ST_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTD` reader - Interrupt on done"] +pub type INTD_R = crate::BitReader; +#[doc = "Field `INTD` writer - Interrupt on done"] +pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTT` reader - Interrupt on TX"] +pub type INTT_R = crate::BitReader; +#[doc = "Field `INTT` writer - Interrupt on TX"] +pub type INTT_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `INTR` reader - Interrupt on RX"] +pub type INTR_R = crate::BitReader; +#[doc = "Field `INTR` writer - Interrupt on RX"] +pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +#[doc = "Field `I2CEN` reader - I2C Enable"] +pub type I2CEN_R = crate::BitReader; +#[doc = "Field `I2CEN` writer - I2C Enable"] +pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer is read"] + #[inline(always)] + pub fn read(&self) -> READ_R { + READ_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:5 - Clear the FIFO"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Start transfer"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Interrupt on done"] + #[inline(always)] + pub fn intd(&self) -> INTD_R { + INTD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on TX"] + #[inline(always)] + pub fn intt(&self) -> INTT_R { + INTT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 15 - I2C Enable"] + #[inline(always)] + pub fn i2cen(&self) -> I2CEN_R { + I2CEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer is read"] + #[inline(always)] + #[must_use] + pub fn read(&mut self) -> READ_W<0> { + READ_W::new(self) + } + #[doc = "Bits 4:5 - Clear the FIFO"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<4> { + CLEAR_W::new(self) + } + #[doc = "Bit 7 - Start transfer"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> ST_W<7> { + ST_W::new(self) + } + #[doc = "Bit 8 - Interrupt on done"] + #[inline(always)] + #[must_use] + pub fn intd(&mut self) -> INTD_W<8> { + INTD_W::new(self) + } + #[doc = "Bit 9 - Interrupt on TX"] + #[inline(always)] + #[must_use] + pub fn intt(&mut self) -> INTT_W<9> { + INTT_W::new(self) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W<10> { + INTR_W::new(self) + } + #[doc = "Bit 15 - I2C Enable"] + #[inline(always)] + #[must_use] + pub fn i2cen(&mut self) -> I2CEN_W<15> { + I2CEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c](index.html) module"] +pub struct C_SPEC; +impl crate::RegisterSpec for C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c::R](R) reader structure"] +impl crate::Readable for C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c::W](W) writer structure"] +impl crate::Writable for C_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C to value 0"] +impl crate::Resettable for C_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/bsc0/clkt.rs b/crates/bcm2837-lpa/src/bsc0/clkt.rs new file mode 100644 index 0000000..15bc5c4 --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/clkt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CLKT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"] +pub type TOUT_R = crate::FieldReader; +#[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"] +pub type TOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] + #[inline(always)] + pub fn tout(&self) -> TOUT_R { + TOUT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] + #[inline(always)] + #[must_use] + pub fn tout(&mut self) -> TOUT_W<0> { + TOUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock stretch timeout (broken on 283x)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkt](index.html) module"] +pub struct CLKT_SPEC; +impl crate::RegisterSpec for CLKT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkt::R](R) reader structure"] +impl crate::Readable for CLKT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkt::W](W) writer structure"] +impl crate::Writable for CLKT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKT to value 0"] +impl crate::Resettable for CLKT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/bsc0/del.rs b/crates/bcm2837-lpa/src/bsc0/del.rs new file mode 100644 index 0000000..c39336b --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/del.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REDL` reader - Delay before reading after a rising edge"] +pub type REDL_R = crate::FieldReader; +#[doc = "Field `REDL` writer - Delay before reading after a rising edge"] +pub type REDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +#[doc = "Field `FEDL` reader - Delay before reading after a falling edge"] +pub type FEDL_R = crate::FieldReader; +#[doc = "Field `FEDL` writer - Delay before reading after a falling edge"] +pub type FEDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Delay before reading after a rising edge"] + #[inline(always)] + pub fn redl(&self) -> REDL_R { + REDL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Delay before reading after a falling edge"] + #[inline(always)] + pub fn fedl(&self) -> FEDL_R { + FEDL_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Delay before reading after a rising edge"] + #[inline(always)] + #[must_use] + pub fn redl(&mut self) -> REDL_W<0> { + REDL_W::new(self) + } + #[doc = "Bits 16:31 - Delay before reading after a falling edge"] + #[inline(always)] + #[must_use] + pub fn fedl(&mut self) -> FEDL_W<16> { + FEDL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data delay (Values must be under CDIV / 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [del](index.html) module"] +pub struct DEL_SPEC; +impl crate::RegisterSpec for DEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [del::R](R) reader structure"] +impl crate::Readable for DEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [del::W](W) writer structure"] +impl crate::Writable for DEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEL to value 0x0030_0030"] +impl crate::Resettable for DEL_SPEC { + const RESET_VALUE: Self::Ux = 0x0030_0030; +} diff --git a/crates/bcm2837-lpa/src/bsc0/div.rs b/crates/bcm2837-lpa/src/bsc0/div.rs new file mode 100644 index 0000000..ce0aa5a --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/div.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CDIV` reader - Divide the source clock"] +pub type CDIV_R = crate::FieldReader; +#[doc = "Field `CDIV` writer - Divide the source clock"] +pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Divide the source clock"] + #[inline(always)] + pub fn cdiv(&self) -> CDIV_R { + CDIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Divide the source clock"] + #[inline(always)] + #[must_use] + pub fn cdiv(&mut self) -> CDIV_W<0> { + CDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [div::R](R) reader structure"] +impl crate::Readable for DIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIV to value 0x05dc"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: Self::Ux = 0x05dc; +} diff --git a/crates/bcm2837-lpa/src/bsc0/dlen.rs b/crates/bcm2837-lpa/src/bsc0/dlen.rs new file mode 100644 index 0000000..25e2771 --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/dlen.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLEN` reader - Data length"] +pub type DLEN_R = crate::FieldReader; +#[doc = "Field `DLEN` writer - Data length"] +pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + pub fn dlen(&self) -> DLEN_R { + DLEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + #[must_use] + pub fn dlen(&mut self) -> DLEN_W<0> { + DLEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +pub struct DLEN_SPEC; +impl crate::RegisterSpec for DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dlen::R](R) reader structure"] +impl crate::Readable for DLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +impl crate::Writable for DLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLEN to value 0"] +impl crate::Resettable for DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/bsc0/fifo.rs b/crates/bcm2837-lpa/src/bsc0/fifo.rs new file mode 100644 index 0000000..f85912b --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/fifo.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FIFO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Access the FIFO"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Access the FIFO"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Access the FIFO"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Access the FIFO"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo::R](R) reader structure"] +impl crate::Readable for FIFO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/bsc0/s.rs b/crates/bcm2837-lpa/src/bsc0/s.rs new file mode 100644 index 0000000..45f365b --- /dev/null +++ b/crates/bcm2837-lpa/src/bsc0/s.rs @@ -0,0 +1,159 @@ +#[doc = "Register `S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TA` reader - Transfer active"] +pub type TA_R = crate::BitReader; +#[doc = "Field `DONE` reader - Transfer done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Transfer done"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +#[doc = "Field `TXW` reader - FIFO needs to be written"] +pub type TXW_R = crate::BitReader; +#[doc = "Field `RXR` reader - FIFO needs to be read"] +pub type RXR_R = crate::BitReader; +#[doc = "Field `TXD` reader - FIFO has space for at least one byte"] +pub type TXD_R = crate::BitReader; +#[doc = "Field `RXD` reader - FIFO contains at least one byte"] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXE` reader - FIFO is empty. Nothing to transmit"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `RXF` reader - FIFO is full. Can't receive anything else"] +pub type RXF_R = crate::BitReader; +#[doc = "Field `ERR` reader - Error: No ack"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Error: No ack"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +#[doc = "Field `CLKT` reader - Clock stretch timeout"] +pub type CLKT_R = crate::BitReader; +#[doc = "Field `CLKT` writer - Clock stretch timeout"] +pub type CLKT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer active"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO needs to be written"] + #[inline(always)] + pub fn txw(&self) -> TXW_R { + TXW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO needs to be read"] + #[inline(always)] + pub fn rxr(&self) -> RXR_R { + RXR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - FIFO has space for at least one byte"] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - FIFO contains at least one byte"] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - FIFO is empty. Nothing to transmit"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FIFO is full. Can't receive anything else"] + #[inline(always)] + pub fn rxf(&self) -> RXF_R { + RXF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Error: No ack"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Clock stretch timeout"] + #[inline(always)] + pub fn clkt(&self) -> CLKT_R { + CLKT_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Transfer done"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<1> { + DONE_W::new(self) + } + #[doc = "Bit 8 - Error: No ack"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<8> { + ERR_W::new(self) + } + #[doc = "Bit 9 - Clock stretch timeout"] + #[inline(always)] + #[must_use] + pub fn clkt(&mut self) -> CLKT_W<9> { + CLKT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s](index.html) module"] +pub struct S_SPEC; +impl crate::RegisterSpec for S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s::R](R) reader structure"] +impl crate::Readable for S_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s::W](W) writer structure"] +impl crate::Writable for S_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0302; +} +#[doc = "`reset()` method sets S to value 0x50"] +impl crate::Resettable for S_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/crates/bcm2837-lpa/src/cm_pcm.rs b/crates/bcm2837-lpa/src/cm_pcm.rs new file mode 100644 index 0000000..0c60fcd --- /dev/null +++ b/crates/bcm2837-lpa/src/cm_pcm.rs @@ -0,0 +1,16 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control / Status"] + pub cs: CS, + #[doc = "0x04 - Clock divisor"] + pub div: DIV, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control / Status"] +pub mod cs; +#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +pub type DIV = crate::Reg; +#[doc = "Clock divisor"] +pub mod div; diff --git a/crates/bcm2837-lpa/src/cm_pcm/cs.rs b/crates/bcm2837-lpa/src/cm_pcm/cs.rs new file mode 100644 index 0000000..67ddd60 --- /dev/null +++ b/crates/bcm2837-lpa/src/cm_pcm/cs.rs @@ -0,0 +1,288 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Clock source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "1: `1`"] + XOSC = 1, + #[doc = "2: `10`"] + TEST0 = 2, + #[doc = "3: `11`"] + TEST1 = 3, + #[doc = "4: `100`"] + PLLA = 4, + #[doc = "5: `101`"] + PLLB = 5, + #[doc = "6: `110`"] + PLLC = 6, + #[doc = "7: `111`"] + HDMI = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(SRC_A::XOSC), + 2 => Some(SRC_A::TEST0), + 3 => Some(SRC_A::TEST1), + 4 => Some(SRC_A::PLLA), + 5 => Some(SRC_A::PLLB), + 6 => Some(SRC_A::PLLC), + 7 => Some(SRC_A::HDMI), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + *self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `TEST0`"] + #[inline(always)] + pub fn is_test0(&self) -> bool { + *self == SRC_A::TEST0 + } + #[doc = "Checks if the value of the field is `TEST1`"] + #[inline(always)] + pub fn is_test1(&self) -> bool { + *self == SRC_A::TEST1 + } + #[doc = "Checks if the value of the field is `PLLA`"] + #[inline(always)] + pub fn is_plla(&self) -> bool { + *self == SRC_A::PLLA + } + #[doc = "Checks if the value of the field is `PLLB`"] + #[inline(always)] + pub fn is_pllb(&self) -> bool { + *self == SRC_A::PLLB + } + #[doc = "Checks if the value of the field is `PLLC`"] + #[inline(always)] + pub fn is_pllc(&self) -> bool { + *self == SRC_A::PLLC + } + #[doc = "Checks if the value of the field is `HDMI`"] + #[inline(always)] + pub fn is_hdmi(&self) -> bool { + *self == SRC_A::HDMI + } +} +#[doc = "Field `SRC` writer - Clock source"] +pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, SRC_A, 4, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "`1`"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "`10`"] + #[inline(always)] + pub fn test0(self) -> &'a mut W { + self.variant(SRC_A::TEST0) + } + #[doc = "`11`"] + #[inline(always)] + pub fn test1(self) -> &'a mut W { + self.variant(SRC_A::TEST1) + } + #[doc = "`100`"] + #[inline(always)] + pub fn plla(self) -> &'a mut W { + self.variant(SRC_A::PLLA) + } + #[doc = "`101`"] + #[inline(always)] + pub fn pllb(self) -> &'a mut W { + self.variant(SRC_A::PLLB) + } + #[doc = "`110`"] + #[inline(always)] + pub fn pllc(self) -> &'a mut W { + self.variant(SRC_A::PLLC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn hdmi(self) -> &'a mut W { + self.variant(SRC_A::HDMI) + } +} +#[doc = "Field `ENAB` reader - Enable the clock generator. (Switch SRC first.)"] +pub type ENAB_R = crate::BitReader; +#[doc = "Field `ENAB` writer - Enable the clock generator. (Switch SRC first.)"] +pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `KILL` reader - Stop and reset the generator"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Stop and reset the generator"] +pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `BUSY` reader - Indicates the clock generator is running"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `FLIP` reader - Generate an edge on output. (For testing)"] +pub type FLIP_R = crate::BitReader; +#[doc = "Field `FLIP` writer - Generate an edge on output. (For testing)"] +pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `MASH` reader - MASH control, stage count"] +pub type MASH_R = crate::FieldReader; +#[doc = "Field `MASH` writer - MASH control, stage count"] +pub type MASH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:3 - Clock source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] + #[inline(always)] + pub fn enab(&self) -> ENAB_R { + ENAB_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stop and reset the generator"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Indicates the clock generator is running"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Generate an edge on output. (For testing)"] + #[inline(always)] + pub fn flip(&self) -> FLIP_R { + FLIP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:10 - MASH control, stage count"] + #[inline(always)] + pub fn mash(&self) -> MASH_R { + MASH_R::new(((self.bits >> 9) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Clock source"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] + #[inline(always)] + #[must_use] + pub fn enab(&mut self) -> ENAB_W<4> { + ENAB_W::new(self) + } + #[doc = "Bit 5 - Stop and reset the generator"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W<5> { + KILL_W::new(self) + } + #[doc = "Bit 8 - Generate an edge on output. (For testing)"] + #[inline(always)] + #[must_use] + pub fn flip(&mut self) -> FLIP_W<8> { + FLIP_W::new(self) + } + #[doc = "Bits 9:10 - MASH control, stage count"] + #[inline(always)] + #[must_use] + pub fn mash(&mut self) -> MASH_W<9> { + MASH_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/cm_pcm/div.rs b/crates/bcm2837-lpa/src/cm_pcm/div.rs new file mode 100644 index 0000000..a0c99f8 --- /dev/null +++ b/crates/bcm2837-lpa/src/cm_pcm/div.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVF` reader - Fractional part of divisor"] +pub type DIVF_R = crate::FieldReader; +#[doc = "Field `DIVF` writer - Fractional part of divisor"] +pub type DIVF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +#[doc = "Field `DIVI` reader - Integer part of divisor"] +pub type DIVI_R = crate::FieldReader; +#[doc = "Field `DIVI` writer - Integer part of divisor"] +pub type DIVI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +#[doc = "Password. Always 0x5a\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PASSWD_AW { + #[doc = "90: `1011010`"] + PASSWD = 90, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PASSWD_AW) -> Self { + variant as _ + } +} +#[doc = "Field `PASSWD` writer - Password. Always 0x5a"] +pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u8, PASSWD_AW, 8, O>; +impl<'a, const O: u8> PASSWD_W<'a, O> { + #[doc = "`1011010`"] + #[inline(always)] + pub fn passwd(self) -> &'a mut W { + self.variant(PASSWD_AW::PASSWD) + } +} +impl R { + #[doc = "Bits 0:11 - Fractional part of divisor"] + #[inline(always)] + pub fn divf(&self) -> DIVF_R { + DIVF_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - Integer part of divisor"] + #[inline(always)] + pub fn divi(&self) -> DIVI_R { + DIVI_R::new(((self.bits >> 12) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Fractional part of divisor"] + #[inline(always)] + #[must_use] + pub fn divf(&mut self) -> DIVF_W<0> { + DIVF_W::new(self) + } + #[doc = "Bits 12:23 - Integer part of divisor"] + #[inline(always)] + #[must_use] + pub fn divi(&mut self) -> DIVI_W<12> { + DIVI_W::new(self) + } + #[doc = "Bits 24:31 - Password. Always 0x5a"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W<24> { + PASSWD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [div::R](R) reader structure"] +impl crate::Readable for DIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIV to value 0"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc.rs b/crates/bcm2837-lpa/src/emmc.rs new file mode 100644 index 0000000..e4be2cf --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc.rs @@ -0,0 +1,165 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Argument for ACMD23 command"] + pub arg2: ARG2, + #[doc = "0x04 - Numer and size in bytes for data block to be transferred"] + pub blksizecnt: BLKSIZECNT, + #[doc = "0x08 - Argument for everything but ACMD23"] + pub arg1: ARG1, + #[doc = "0x0c - Issue commands to the card"] + pub cmdtm: CMDTM, + #[doc = "0x10 - Status bits of the response"] + pub resp0: RESP0, + #[doc = "0x14 - Bits 63:32 of CMD2 and CMD10 responses"] + pub resp1: RESP1, + #[doc = "0x18 - Bits 95:64 of CMD2 and CMD10 responses"] + pub resp2: RESP2, + #[doc = "0x1c - Bits 127:96 of CMD2 and CMD10 responses"] + pub resp3: RESP3, + #[doc = "0x20 - Data to/from the card"] + pub data: DATA, + #[doc = "0x24 - Status info for debugging"] + pub status: STATUS, + #[doc = "0x28 - Control"] + pub control0: CONTROL0, + #[doc = "0x2c - Configure"] + pub control1: CONTROL1, + #[doc = "0x30 - Interrupt flags"] + pub interrupt: INTERRUPT, + #[doc = "0x34 - Mask interrupts that change in INTERRUPT"] + pub irpt_mask: IRPT_MASK, + #[doc = "0x38 - Enable interrupt to core"] + pub irpt_en: IRPT_EN, + #[doc = "0x3c - Control 2"] + pub control2: CONTROL2, + _reserved16: [u8; 0x10], + #[doc = "0x50 - Force an interrupt"] + pub force_irpt: FORCE_IRPT, + _reserved17: [u8; 0x1c], + #[doc = "0x70 - Number of SD clock cycles to wait for boot"] + pub boot_timeout: BOOT_TIMEOUT, + #[doc = "0x74 - What submodules are accessed by the debug bus"] + pub dbg_sel: DBG_SEL, + _reserved19: [u8; 0x08], + #[doc = "0x80 - Fine tune DMA request generation"] + pub exrdfifo_cfg: EXRDFIFO_CFG, + #[doc = "0x84 - Enable the extension data register"] + pub exrdfifo_en: EXRDFIFO_EN, + #[doc = "0x88 - Sample clock delay step duration"] + pub tune_step: TUNE_STEP, + #[doc = "0x8c - Sample clock delay step count for SDR"] + pub tune_steps_std: TUNE_STEPS_STD, + #[doc = "0x90 - Sample clock delay step count for DDR"] + pub tune_steps_ddr: TUNE_STEPS_DDR, + _reserved24: [u8; 0x5c], + #[doc = "0xf0 - Interrupts in SPI mode depend on CS"] + pub spi_int_spt: SPI_INT_SPT, + _reserved25: [u8; 0x08], + #[doc = "0xfc - Version information and slot interrupt status"] + pub slotisr_ver: SLOTISR_VER, +} +#[doc = "ARG2 (rw) register accessor: an alias for `Reg`"] +pub type ARG2 = crate::Reg; +#[doc = "Argument for ACMD23 command"] +pub mod arg2; +#[doc = "BLKSIZECNT (rw) register accessor: an alias for `Reg`"] +pub type BLKSIZECNT = crate::Reg; +#[doc = "Numer and size in bytes for data block to be transferred"] +pub mod blksizecnt; +#[doc = "ARG1 (rw) register accessor: an alias for `Reg`"] +pub type ARG1 = crate::Reg; +#[doc = "Argument for everything but ACMD23"] +pub mod arg1; +#[doc = "CMDTM (rw) register accessor: an alias for `Reg`"] +pub type CMDTM = crate::Reg; +#[doc = "Issue commands to the card"] +pub mod cmdtm; +#[doc = "RESP0 (rw) register accessor: an alias for `Reg`"] +pub type RESP0 = crate::Reg; +#[doc = "Status bits of the response"] +pub mod resp0; +#[doc = "RESP1 (rw) register accessor: an alias for `Reg`"] +pub type RESP1 = crate::Reg; +#[doc = "Bits 63:32 of CMD2 and CMD10 responses"] +pub mod resp1; +#[doc = "RESP2 (rw) register accessor: an alias for `Reg`"] +pub type RESP2 = crate::Reg; +#[doc = "Bits 95:64 of CMD2 and CMD10 responses"] +pub mod resp2; +#[doc = "RESP3 (rw) register accessor: an alias for `Reg`"] +pub type RESP3 = crate::Reg; +#[doc = "Bits 127:96 of CMD2 and CMD10 responses"] +pub mod resp3; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data to/from the card"] +pub mod data; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status info for debugging"] +pub mod status; +#[doc = "CONTROL0 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL0 = crate::Reg; +#[doc = "Control"] +pub mod control0; +#[doc = "CONTROL1 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL1 = crate::Reg; +#[doc = "Configure"] +pub mod control1; +#[doc = "INTERRUPT (rw) register accessor: an alias for `Reg`"] +pub type INTERRUPT = crate::Reg; +#[doc = "Interrupt flags"] +pub mod interrupt; +#[doc = "IRPT_MASK (rw) register accessor: an alias for `Reg`"] +pub type IRPT_MASK = crate::Reg; +#[doc = "Mask interrupts that change in INTERRUPT"] +pub mod irpt_mask; +#[doc = "IRPT_EN (rw) register accessor: an alias for `Reg`"] +pub type IRPT_EN = crate::Reg; +#[doc = "Enable interrupt to core"] +pub mod irpt_en; +#[doc = "CONTROL2 (rw) register accessor: an alias for `Reg`"] +pub type CONTROL2 = crate::Reg; +#[doc = "Control 2"] +pub mod control2; +#[doc = "FORCE_IRPT (rw) register accessor: an alias for `Reg`"] +pub type FORCE_IRPT = crate::Reg; +#[doc = "Force an interrupt"] +pub mod force_irpt; +#[doc = "BOOT_TIMEOUT (rw) register accessor: an alias for `Reg`"] +pub type BOOT_TIMEOUT = crate::Reg; +#[doc = "Number of SD clock cycles to wait for boot"] +pub mod boot_timeout; +#[doc = "DBG_SEL (rw) register accessor: an alias for `Reg`"] +pub type DBG_SEL = crate::Reg; +#[doc = "What submodules are accessed by the debug bus"] +pub mod dbg_sel; +#[doc = "EXRDFIFO_CFG (rw) register accessor: an alias for `Reg`"] +pub type EXRDFIFO_CFG = crate::Reg; +#[doc = "Fine tune DMA request generation"] +pub mod exrdfifo_cfg; +#[doc = "EXRDFIFO_EN (rw) register accessor: an alias for `Reg`"] +pub type EXRDFIFO_EN = crate::Reg; +#[doc = "Enable the extension data register"] +pub mod exrdfifo_en; +#[doc = "TUNE_STEP (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEP = crate::Reg; +#[doc = "Sample clock delay step duration"] +pub mod tune_step; +#[doc = "TUNE_STEPS_STD (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEPS_STD = crate::Reg; +#[doc = "Sample clock delay step count for SDR"] +pub mod tune_steps_std; +#[doc = "TUNE_STEPS_DDR (rw) register accessor: an alias for `Reg`"] +pub type TUNE_STEPS_DDR = crate::Reg; +#[doc = "Sample clock delay step count for DDR"] +pub mod tune_steps_ddr; +#[doc = "SPI_INT_SPT (rw) register accessor: an alias for `Reg`"] +pub type SPI_INT_SPT = crate::Reg; +#[doc = "Interrupts in SPI mode depend on CS"] +pub mod spi_int_spt; +#[doc = "SLOTISR_VER (rw) register accessor: an alias for `Reg`"] +pub type SLOTISR_VER = crate::Reg; +#[doc = "Version information and slot interrupt status"] +pub mod slotisr_ver; diff --git a/crates/bcm2837-lpa/src/emmc/arg1.rs b/crates/bcm2837-lpa/src/emmc/arg1.rs new file mode 100644 index 0000000..4a25300 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/arg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ARG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ARG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Argument for everything but ACMD23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg1](index.html) module"] +pub struct ARG1_SPEC; +impl crate::RegisterSpec for ARG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [arg1::R](R) reader structure"] +impl crate::Readable for ARG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [arg1::W](W) writer structure"] +impl crate::Writable for ARG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARG1 to value 0"] +impl crate::Resettable for ARG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/arg2.rs b/crates/bcm2837-lpa/src/emmc/arg2.rs new file mode 100644 index 0000000..b295b35 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/arg2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ARG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ARG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Argument for ACMD23 command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg2](index.html) module"] +pub struct ARG2_SPEC; +impl crate::RegisterSpec for ARG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [arg2::R](R) reader structure"] +impl crate::Readable for ARG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [arg2::W](W) writer structure"] +impl crate::Writable for ARG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARG2 to value 0"] +impl crate::Resettable for ARG2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/blksizecnt.rs b/crates/bcm2837-lpa/src/emmc/blksizecnt.rs new file mode 100644 index 0000000..f3dabd8 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/blksizecnt.rs @@ -0,0 +1,95 @@ +#[doc = "Register `BLKSIZECNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BLKSIZECNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BLKSIZE` reader - Block size in bytes"] +pub type BLKSIZE_R = crate::FieldReader; +#[doc = "Field `BLKSIZE` writer - Block size in bytes"] +pub type BLKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 10, O>; +#[doc = "Field `BLKCNT` reader - Number of blocks to be transferred"] +pub type BLKCNT_R = crate::FieldReader; +#[doc = "Field `BLKCNT` writer - Number of blocks to be transferred"] +pub type BLKCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:9 - Block size in bytes"] + #[inline(always)] + pub fn blksize(&self) -> BLKSIZE_R { + BLKSIZE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:31 - Number of blocks to be transferred"] + #[inline(always)] + pub fn blkcnt(&self) -> BLKCNT_R { + BLKCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Block size in bytes"] + #[inline(always)] + #[must_use] + pub fn blksize(&mut self) -> BLKSIZE_W<0> { + BLKSIZE_W::new(self) + } + #[doc = "Bits 16:31 - Number of blocks to be transferred"] + #[inline(always)] + #[must_use] + pub fn blkcnt(&mut self) -> BLKCNT_W<16> { + BLKCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Numer and size in bytes for data block to be transferred\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blksizecnt](index.html) module"] +pub struct BLKSIZECNT_SPEC; +impl crate::RegisterSpec for BLKSIZECNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [blksizecnt::R](R) reader structure"] +impl crate::Readable for BLKSIZECNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [blksizecnt::W](W) writer structure"] +impl crate::Writable for BLKSIZECNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLKSIZECNT to value 0"] +impl crate::Resettable for BLKSIZECNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/boot_timeout.rs b/crates/bcm2837-lpa/src/emmc/boot_timeout.rs new file mode 100644 index 0000000..5a9943a --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/boot_timeout.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BOOT_TIMEOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOOT_TIMEOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Number of SD clock cycles to wait for boot\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_timeout](index.html) module"] +pub struct BOOT_TIMEOUT_SPEC; +impl crate::RegisterSpec for BOOT_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [boot_timeout::R](R) reader structure"] +impl crate::Readable for BOOT_TIMEOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [boot_timeout::W](W) writer structure"] +impl crate::Writable for BOOT_TIMEOUT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOOT_TIMEOUT to value 0"] +impl crate::Resettable for BOOT_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/cmdtm.rs b/crates/bcm2837-lpa/src/emmc/cmdtm.rs new file mode 100644 index 0000000..e30a873 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/cmdtm.rs @@ -0,0 +1,520 @@ +#[doc = "Register `CMDTM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMDTM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TM_BLKCNT_EN` reader - Enable block counter"] +pub type TM_BLKCNT_EN_R = crate::BitReader; +#[doc = "Field `TM_BLKCNT_EN` writer - Enable block counter"] +pub type TM_BLKCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `TM_AUTO_CMD_EN` reader - Command after completion"] +pub type TM_AUTO_CMD_EN_R = crate::FieldReader; +#[doc = "Command after completion\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TM_AUTO_CMD_EN_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + CMD12 = 1, + #[doc = "2: `10`"] + CMD23 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TM_AUTO_CMD_EN_A) -> Self { + variant as _ + } +} +impl TM_AUTO_CMD_EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TM_AUTO_CMD_EN_A::NONE), + 1 => Some(TM_AUTO_CMD_EN_A::CMD12), + 2 => Some(TM_AUTO_CMD_EN_A::CMD23), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::NONE + } + #[doc = "Checks if the value of the field is `CMD12`"] + #[inline(always)] + pub fn is_cmd12(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::CMD12 + } + #[doc = "Checks if the value of the field is `CMD23`"] + #[inline(always)] + pub fn is_cmd23(&self) -> bool { + *self == TM_AUTO_CMD_EN_A::CMD23 + } +} +#[doc = "Field `TM_AUTO_CMD_EN` writer - Command after completion"] +pub type TM_AUTO_CMD_EN_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, TM_AUTO_CMD_EN_A, 2, O>; +impl<'a, const O: u8> TM_AUTO_CMD_EN_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::NONE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn cmd12(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::CMD12) + } + #[doc = "`10`"] + #[inline(always)] + pub fn cmd23(self) -> &'a mut W { + self.variant(TM_AUTO_CMD_EN_A::CMD23) + } +} +#[doc = "Field `TM_DAT_DIR` reader - Direction of data transfer"] +pub type TM_DAT_DIR_R = crate::BitReader; +#[doc = "Direction of data transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TM_DAT_DIR_A { + #[doc = "0: `0`"] + HOST_TO_CARD = 0, + #[doc = "1: `1`"] + CARD_TO_HOST = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TM_DAT_DIR_A) -> Self { + variant as u8 != 0 + } +} +impl TM_DAT_DIR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TM_DAT_DIR_A { + match self.bits { + false => TM_DAT_DIR_A::HOST_TO_CARD, + true => TM_DAT_DIR_A::CARD_TO_HOST, + } + } + #[doc = "Checks if the value of the field is `HOST_TO_CARD`"] + #[inline(always)] + pub fn is_host_to_card(&self) -> bool { + *self == TM_DAT_DIR_A::HOST_TO_CARD + } + #[doc = "Checks if the value of the field is `CARD_TO_HOST`"] + #[inline(always)] + pub fn is_card_to_host(&self) -> bool { + *self == TM_DAT_DIR_A::CARD_TO_HOST + } +} +#[doc = "Field `TM_DAT_DIR` writer - Direction of data transfer"] +pub type TM_DAT_DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, TM_DAT_DIR_A, O>; +impl<'a, const O: u8> TM_DAT_DIR_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn host_to_card(self) -> &'a mut W { + self.variant(TM_DAT_DIR_A::HOST_TO_CARD) + } + #[doc = "`1`"] + #[inline(always)] + pub fn card_to_host(self) -> &'a mut W { + self.variant(TM_DAT_DIR_A::CARD_TO_HOST) + } +} +#[doc = "Field `TM_MULTI_BLOCK` reader - Type of data transfer"] +pub type TM_MULTI_BLOCK_R = crate::BitReader; +#[doc = "Type of data transfer\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TM_MULTI_BLOCK_A { + #[doc = "0: `0`"] + SINGLE = 0, + #[doc = "1: `1`"] + MULTIPLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TM_MULTI_BLOCK_A) -> Self { + variant as u8 != 0 + } +} +impl TM_MULTI_BLOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TM_MULTI_BLOCK_A { + match self.bits { + false => TM_MULTI_BLOCK_A::SINGLE, + true => TM_MULTI_BLOCK_A::MULTIPLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == TM_MULTI_BLOCK_A::SINGLE + } + #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[inline(always)] + pub fn is_multiple(&self) -> bool { + *self == TM_MULTI_BLOCK_A::MULTIPLE + } +} +#[doc = "Field `TM_MULTI_BLOCK` writer - Type of data transfer"] +pub type TM_MULTI_BLOCK_W<'a, const O: u8> = + crate::BitWriter<'a, u32, CMDTM_SPEC, TM_MULTI_BLOCK_A, O>; +impl<'a, const O: u8> TM_MULTI_BLOCK_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(TM_MULTI_BLOCK_A::SINGLE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn multiple(self) -> &'a mut W { + self.variant(TM_MULTI_BLOCK_A::MULTIPLE) + } +} +#[doc = "Field `CMD_RSPNS_TYPE` reader - Type of expected response"] +pub type CMD_RSPNS_TYPE_R = crate::FieldReader; +#[doc = "Type of expected response\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RESPONSE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _136BITS = 1, + #[doc = "2: `10`"] + _48BITS = 2, + #[doc = "3: `11`"] + _48BITS_USING_BUSY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESPONSE_A) -> Self { + variant as _ + } +} +impl CMD_RSPNS_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESPONSE_A { + match self.bits { + 0 => RESPONSE_A::NONE, + 1 => RESPONSE_A::_136BITS, + 2 => RESPONSE_A::_48BITS, + 3 => RESPONSE_A::_48BITS_USING_BUSY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == RESPONSE_A::NONE + } + #[doc = "Checks if the value of the field is `_136BITS`"] + #[inline(always)] + pub fn is_136bits(&self) -> bool { + *self == RESPONSE_A::_136BITS + } + #[doc = "Checks if the value of the field is `_48BITS`"] + #[inline(always)] + pub fn is_48bits(&self) -> bool { + *self == RESPONSE_A::_48BITS + } + #[doc = "Checks if the value of the field is `_48BITS_USING_BUSY`"] + #[inline(always)] + pub fn is_48bits_using_busy(&self) -> bool { + *self == RESPONSE_A::_48BITS_USING_BUSY + } +} +#[doc = "Field `CMD_RSPNS_TYPE` writer - Type of expected response"] +pub type CMD_RSPNS_TYPE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, RESPONSE_A, 2, O>; +impl<'a, const O: u8> CMD_RSPNS_TYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESPONSE_A::NONE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _136bits(self) -> &'a mut W { + self.variant(RESPONSE_A::_136BITS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _48bits(self) -> &'a mut W { + self.variant(RESPONSE_A::_48BITS) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _48bits_using_busy(self) -> &'a mut W { + self.variant(RESPONSE_A::_48BITS_USING_BUSY) + } +} +#[doc = "Field `CMD_CRCCHK_EN` reader - Check the responses CRC"] +pub type CMD_CRCCHK_EN_R = crate::BitReader; +#[doc = "Field `CMD_CRCCHK_EN` writer - Check the responses CRC"] +pub type CMD_CRCCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_IXCHK_EN` reader - Check that the response has the same command index"] +pub type CMD_IXCHK_EN_R = crate::BitReader; +#[doc = "Field `CMD_IXCHK_EN` writer - Check that the response has the same command index"] +pub type CMD_IXCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_ISDATA` reader - Command involves data"] +pub type CMD_ISDATA_R = crate::BitReader; +#[doc = "Field `CMD_ISDATA` writer - Command involves data"] +pub type CMD_ISDATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +#[doc = "Field `CMD_TYPE` reader - Type of command to be issued"] +pub type CMD_TYPE_R = crate::FieldReader; +#[doc = "Type of command to be issued\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMD_TYPE_A { + #[doc = "0: `0`"] + NORMAL = 0, + #[doc = "1: `1`"] + SUSPEND = 1, + #[doc = "2: `10`"] + RESUME = 2, + #[doc = "3: `11`"] + ABORT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_TYPE_A) -> Self { + variant as _ + } +} +impl CMD_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMD_TYPE_A { + match self.bits { + 0 => CMD_TYPE_A::NORMAL, + 1 => CMD_TYPE_A::SUSPEND, + 2 => CMD_TYPE_A::RESUME, + 3 => CMD_TYPE_A::ABORT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NORMAL`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == CMD_TYPE_A::NORMAL + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == CMD_TYPE_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + *self == CMD_TYPE_A::RESUME + } + #[doc = "Checks if the value of the field is `ABORT`"] + #[inline(always)] + pub fn is_abort(&self) -> bool { + *self == CMD_TYPE_A::ABORT + } +} +#[doc = "Field `CMD_TYPE` writer - Type of command to be issued"] +pub type CMD_TYPE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, CMD_TYPE_A, 2, O>; +impl<'a, const O: u8> CMD_TYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn normal(self) -> &'a mut W { + self.variant(CMD_TYPE_A::NORMAL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_TYPE_A::SUSPEND) + } + #[doc = "`10`"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_TYPE_A::RESUME) + } + #[doc = "`11`"] + #[inline(always)] + pub fn abort(self) -> &'a mut W { + self.variant(CMD_TYPE_A::ABORT) + } +} +#[doc = "Field `CMD_INDEX` reader - Command index to be issued"] +pub type CMD_INDEX_R = crate::FieldReader; +#[doc = "Field `CMD_INDEX` writer - Command index to be issued"] +pub type CMD_INDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bit 1 - Enable block counter"] + #[inline(always)] + pub fn tm_blkcnt_en(&self) -> TM_BLKCNT_EN_R { + TM_BLKCNT_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Command after completion"] + #[inline(always)] + pub fn tm_auto_cmd_en(&self) -> TM_AUTO_CMD_EN_R { + TM_AUTO_CMD_EN_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Direction of data transfer"] + #[inline(always)] + pub fn tm_dat_dir(&self) -> TM_DAT_DIR_R { + TM_DAT_DIR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Type of data transfer"] + #[inline(always)] + pub fn tm_multi_block(&self) -> TM_MULTI_BLOCK_R { + TM_MULTI_BLOCK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 16:17 - Type of expected response"] + #[inline(always)] + pub fn cmd_rspns_type(&self) -> CMD_RSPNS_TYPE_R { + CMD_RSPNS_TYPE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 19 - Check the responses CRC"] + #[inline(always)] + pub fn cmd_crcchk_en(&self) -> CMD_CRCCHK_EN_R { + CMD_CRCCHK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Check that the response has the same command index"] + #[inline(always)] + pub fn cmd_ixchk_en(&self) -> CMD_IXCHK_EN_R { + CMD_IXCHK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Command involves data"] + #[inline(always)] + pub fn cmd_isdata(&self) -> CMD_ISDATA_R { + CMD_ISDATA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:23 - Type of command to be issued"] + #[inline(always)] + pub fn cmd_type(&self) -> CMD_TYPE_R { + CMD_TYPE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:29 - Command index to be issued"] + #[inline(always)] + pub fn cmd_index(&self) -> CMD_INDEX_R { + CMD_INDEX_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable block counter"] + #[inline(always)] + #[must_use] + pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W<1> { + TM_BLKCNT_EN_W::new(self) + } + #[doc = "Bits 2:3 - Command after completion"] + #[inline(always)] + #[must_use] + pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W<2> { + TM_AUTO_CMD_EN_W::new(self) + } + #[doc = "Bit 4 - Direction of data transfer"] + #[inline(always)] + #[must_use] + pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W<4> { + TM_DAT_DIR_W::new(self) + } + #[doc = "Bit 5 - Type of data transfer"] + #[inline(always)] + #[must_use] + pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W<5> { + TM_MULTI_BLOCK_W::new(self) + } + #[doc = "Bits 16:17 - Type of expected response"] + #[inline(always)] + #[must_use] + pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W<16> { + CMD_RSPNS_TYPE_W::new(self) + } + #[doc = "Bit 19 - Check the responses CRC"] + #[inline(always)] + #[must_use] + pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W<19> { + CMD_CRCCHK_EN_W::new(self) + } + #[doc = "Bit 20 - Check that the response has the same command index"] + #[inline(always)] + #[must_use] + pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W<20> { + CMD_IXCHK_EN_W::new(self) + } + #[doc = "Bit 21 - Command involves data"] + #[inline(always)] + #[must_use] + pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W<21> { + CMD_ISDATA_W::new(self) + } + #[doc = "Bits 22:23 - Type of command to be issued"] + #[inline(always)] + #[must_use] + pub fn cmd_type(&mut self) -> CMD_TYPE_W<22> { + CMD_TYPE_W::new(self) + } + #[doc = "Bits 24:29 - Command index to be issued"] + #[inline(always)] + #[must_use] + pub fn cmd_index(&mut self) -> CMD_INDEX_W<24> { + CMD_INDEX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Issue commands to the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdtm](index.html) module"] +pub struct CMDTM_SPEC; +impl crate::RegisterSpec for CMDTM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cmdtm::R](R) reader structure"] +impl crate::Readable for CMDTM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmdtm::W](W) writer structure"] +impl crate::Writable for CMDTM_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMDTM to value 0"] +impl crate::Resettable for CMDTM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/control0.rs b/crates/bcm2837-lpa/src/emmc/control0.rs new file mode 100644 index 0000000..948b94b --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/control0.rs @@ -0,0 +1,215 @@ +#[doc = "Register `CONTROL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HCTL_DWIDTH` reader - Use 4 data lines"] +pub type HCTL_DWIDTH_R = crate::BitReader; +#[doc = "Field `HCTL_DWIDTH` writer - Use 4 data lines"] +pub type HCTL_DWIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `HCTL_HS_EN` reader - Enable high speed mode"] +pub type HCTL_HS_EN_R = crate::BitReader; +#[doc = "Field `HCTL_HS_EN` writer - Enable high speed mode"] +pub type HCTL_HS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `HCTL_8BIT` reader - Use 8 data lines"] +pub type HCTL_8BIT_R = crate::BitReader; +#[doc = "Field `HCTL_8BIT` writer - Use 8 data lines"] +pub type HCTL_8BIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_STOP` reader - Stop the current transaction at the next block gap"] +pub type GAP_STOP_R = crate::BitReader; +#[doc = "Field `GAP_STOP` writer - Stop the current transaction at the next block gap"] +pub type GAP_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_RESTART` reader - Restart a transaction stopped by GAP_STOP"] +pub type GAP_RESTART_R = crate::BitReader; +#[doc = "Field `GAP_RESTART` writer - Restart a transaction stopped by GAP_STOP"] +pub type GAP_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `READWAIT_EN` reader - Use DAT2 read/wait protocol"] +pub type READWAIT_EN_R = crate::BitReader; +#[doc = "Field `READWAIT_EN` writer - Use DAT2 read/wait protocol"] +pub type READWAIT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `GAP_IEN` reader - Enable interrupt on block gap"] +pub type GAP_IEN_R = crate::BitReader; +#[doc = "Field `GAP_IEN` writer - Enable interrupt on block gap"] +pub type GAP_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `SPI_MODE` reader - Enable SPI mode"] +pub type SPI_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MODE` writer - Enable SPI mode"] +pub type SPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `BOOT_EN` reader - Boot mode enabled"] +pub type BOOT_EN_R = crate::BitReader; +#[doc = "Field `BOOT_EN` writer - Boot mode enabled"] +pub type BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +#[doc = "Field `ALT_BOOT_EN` reader - Enable alternate boot mode"] +pub type ALT_BOOT_EN_R = crate::BitReader; +#[doc = "Field `ALT_BOOT_EN` writer - Enable alternate boot mode"] +pub type ALT_BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Use 4 data lines"] + #[inline(always)] + pub fn hctl_dwidth(&self) -> HCTL_DWIDTH_R { + HCTL_DWIDTH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable high speed mode"] + #[inline(always)] + pub fn hctl_hs_en(&self) -> HCTL_HS_EN_R { + HCTL_HS_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Use 8 data lines"] + #[inline(always)] + pub fn hctl_8bit(&self) -> HCTL_8BIT_R { + HCTL_8BIT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - Stop the current transaction at the next block gap"] + #[inline(always)] + pub fn gap_stop(&self) -> GAP_STOP_R { + GAP_STOP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] + #[inline(always)] + pub fn gap_restart(&self) -> GAP_RESTART_R { + GAP_RESTART_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Use DAT2 read/wait protocol"] + #[inline(always)] + pub fn readwait_en(&self) -> READWAIT_EN_R { + READWAIT_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable interrupt on block gap"] + #[inline(always)] + pub fn gap_ien(&self) -> GAP_IEN_R { + GAP_IEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable SPI mode"] + #[inline(always)] + pub fn spi_mode(&self) -> SPI_MODE_R { + SPI_MODE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Boot mode enabled"] + #[inline(always)] + pub fn boot_en(&self) -> BOOT_EN_R { + BOOT_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enable alternate boot mode"] + #[inline(always)] + pub fn alt_boot_en(&self) -> ALT_BOOT_EN_R { + ALT_BOOT_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Use 4 data lines"] + #[inline(always)] + #[must_use] + pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W<1> { + HCTL_DWIDTH_W::new(self) + } + #[doc = "Bit 2 - Enable high speed mode"] + #[inline(always)] + #[must_use] + pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W<2> { + HCTL_HS_EN_W::new(self) + } + #[doc = "Bit 5 - Use 8 data lines"] + #[inline(always)] + #[must_use] + pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W<5> { + HCTL_8BIT_W::new(self) + } + #[doc = "Bit 16 - Stop the current transaction at the next block gap"] + #[inline(always)] + #[must_use] + pub fn gap_stop(&mut self) -> GAP_STOP_W<16> { + GAP_STOP_W::new(self) + } + #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] + #[inline(always)] + #[must_use] + pub fn gap_restart(&mut self) -> GAP_RESTART_W<17> { + GAP_RESTART_W::new(self) + } + #[doc = "Bit 18 - Use DAT2 read/wait protocol"] + #[inline(always)] + #[must_use] + pub fn readwait_en(&mut self) -> READWAIT_EN_W<18> { + READWAIT_EN_W::new(self) + } + #[doc = "Bit 19 - Enable interrupt on block gap"] + #[inline(always)] + #[must_use] + pub fn gap_ien(&mut self) -> GAP_IEN_W<19> { + GAP_IEN_W::new(self) + } + #[doc = "Bit 20 - Enable SPI mode"] + #[inline(always)] + #[must_use] + pub fn spi_mode(&mut self) -> SPI_MODE_W<20> { + SPI_MODE_W::new(self) + } + #[doc = "Bit 21 - Boot mode enabled"] + #[inline(always)] + #[must_use] + pub fn boot_en(&mut self) -> BOOT_EN_W<21> { + BOOT_EN_W::new(self) + } + #[doc = "Bit 22 - Enable alternate boot mode"] + #[inline(always)] + #[must_use] + pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W<22> { + ALT_BOOT_EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control0](index.html) module"] +pub struct CONTROL0_SPEC; +impl crate::RegisterSpec for CONTROL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control0::R](R) reader structure"] +impl crate::Readable for CONTROL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control0::W](W) writer structure"] +impl crate::Writable for CONTROL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL0 to value 0"] +impl crate::Resettable for CONTROL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/control1.rs b/crates/bcm2837-lpa/src/emmc/control1.rs new file mode 100644 index 0000000..1dc7cb3 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/control1.rs @@ -0,0 +1,253 @@ +#[doc = "Register `CONTROL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLK_INTLEN` reader - Enable internal clock"] +pub type CLK_INTLEN_R = crate::BitReader; +#[doc = "Field `CLK_INTLEN` writer - Enable internal clock"] +pub type CLK_INTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `CLK_STABLE` reader - SD Clock stable"] +pub type CLK_STABLE_R = crate::BitReader; +#[doc = "Field `CLK_EN` reader - SD Clock enable"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - SD Clock enable"] +pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `CLK_GENSEL` reader - Mode of clock generation"] +pub type CLK_GENSEL_R = crate::BitReader; +#[doc = "Mode of clock generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CLK_GENSEL_A { + #[doc = "0: `0`"] + DIVIDED = 0, + #[doc = "1: `1`"] + PROGRAMMABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLK_GENSEL_A) -> Self { + variant as u8 != 0 + } +} +impl CLK_GENSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLK_GENSEL_A { + match self.bits { + false => CLK_GENSEL_A::DIVIDED, + true => CLK_GENSEL_A::PROGRAMMABLE, + } + } + #[doc = "Checks if the value of the field is `DIVIDED`"] + #[inline(always)] + pub fn is_divided(&self) -> bool { + *self == CLK_GENSEL_A::DIVIDED + } + #[doc = "Checks if the value of the field is `PROGRAMMABLE`"] + #[inline(always)] + pub fn is_programmable(&self) -> bool { + *self == CLK_GENSEL_A::PROGRAMMABLE + } +} +#[doc = "Field `CLK_GENSEL` writer - Mode of clock generation"] +pub type CLK_GENSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, CLK_GENSEL_A, O>; +impl<'a, const O: u8> CLK_GENSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn divided(self) -> &'a mut W { + self.variant(CLK_GENSEL_A::DIVIDED) + } + #[doc = "`1`"] + #[inline(always)] + pub fn programmable(self) -> &'a mut W { + self.variant(CLK_GENSEL_A::PROGRAMMABLE) + } +} +#[doc = "Field `CLK_FREQ_MS2` reader - Clock base divider MSBs"] +pub type CLK_FREQ_MS2_R = crate::FieldReader; +#[doc = "Field `CLK_FREQ_MS2` writer - Clock base divider MSBs"] +pub type CLK_FREQ_MS2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 2, O>; +#[doc = "Field `CLK_FREQ8` reader - Clock base divider LSB"] +pub type CLK_FREQ8_R = crate::FieldReader; +#[doc = "Field `CLK_FREQ8` writer - Clock base divider LSB"] +pub type CLK_FREQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 8, O>; +#[doc = "Field `DATA_TOUNIT` reader - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] +pub type DATA_TOUNIT_R = crate::FieldReader; +#[doc = "Field `DATA_TOUNIT` writer - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] +pub type DATA_TOUNIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 4, O>; +#[doc = "Field `SRST_HC` reader - Reset the complete host circuit"] +pub type SRST_HC_R = crate::BitReader; +#[doc = "Field `SRST_HC` writer - Reset the complete host circuit"] +pub type SRST_HC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `SRST_CMD` reader - Reset the command handling circuit"] +pub type SRST_CMD_R = crate::BitReader; +#[doc = "Field `SRST_CMD` writer - Reset the command handling circuit"] +pub type SRST_CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +#[doc = "Field `SRST_DATA` reader - Reset the data handling circuit"] +pub type SRST_DATA_R = crate::BitReader; +#[doc = "Field `SRST_DATA` writer - Reset the data handling circuit"] +pub type SRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable internal clock"] + #[inline(always)] + pub fn clk_intlen(&self) -> CLK_INTLEN_R { + CLK_INTLEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SD Clock stable"] + #[inline(always)] + pub fn clk_stable(&self) -> CLK_STABLE_R { + CLK_STABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SD Clock enable"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 5 - Mode of clock generation"] + #[inline(always)] + pub fn clk_gensel(&self) -> CLK_GENSEL_R { + CLK_GENSEL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Clock base divider MSBs"] + #[inline(always)] + pub fn clk_freq_ms2(&self) -> CLK_FREQ_MS2_R { + CLK_FREQ_MS2_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:15 - Clock base divider LSB"] + #[inline(always)] + pub fn clk_freq8(&self) -> CLK_FREQ8_R { + CLK_FREQ8_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] + #[inline(always)] + pub fn data_tounit(&self) -> DATA_TOUNIT_R { + DATA_TOUNIT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 24 - Reset the complete host circuit"] + #[inline(always)] + pub fn srst_hc(&self) -> SRST_HC_R { + SRST_HC_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reset the command handling circuit"] + #[inline(always)] + pub fn srst_cmd(&self) -> SRST_CMD_R { + SRST_CMD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reset the data handling circuit"] + #[inline(always)] + pub fn srst_data(&self) -> SRST_DATA_R { + SRST_DATA_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable internal clock"] + #[inline(always)] + #[must_use] + pub fn clk_intlen(&mut self) -> CLK_INTLEN_W<0> { + CLK_INTLEN_W::new(self) + } + #[doc = "Bit 2 - SD Clock enable"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W<2> { + CLK_EN_W::new(self) + } + #[doc = "Bit 5 - Mode of clock generation"] + #[inline(always)] + #[must_use] + pub fn clk_gensel(&mut self) -> CLK_GENSEL_W<5> { + CLK_GENSEL_W::new(self) + } + #[doc = "Bits 6:7 - Clock base divider MSBs"] + #[inline(always)] + #[must_use] + pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W<6> { + CLK_FREQ_MS2_W::new(self) + } + #[doc = "Bits 8:15 - Clock base divider LSB"] + #[inline(always)] + #[must_use] + pub fn clk_freq8(&mut self) -> CLK_FREQ8_W<8> { + CLK_FREQ8_W::new(self) + } + #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] + #[inline(always)] + #[must_use] + pub fn data_tounit(&mut self) -> DATA_TOUNIT_W<16> { + DATA_TOUNIT_W::new(self) + } + #[doc = "Bit 24 - Reset the complete host circuit"] + #[inline(always)] + #[must_use] + pub fn srst_hc(&mut self) -> SRST_HC_W<24> { + SRST_HC_W::new(self) + } + #[doc = "Bit 25 - Reset the command handling circuit"] + #[inline(always)] + #[must_use] + pub fn srst_cmd(&mut self) -> SRST_CMD_W<25> { + SRST_CMD_W::new(self) + } + #[doc = "Bit 26 - Reset the data handling circuit"] + #[inline(always)] + #[must_use] + pub fn srst_data(&mut self) -> SRST_DATA_W<26> { + SRST_DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configure\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control1](index.html) module"] +pub struct CONTROL1_SPEC; +impl crate::RegisterSpec for CONTROL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control1::R](R) reader structure"] +impl crate::Readable for CONTROL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control1::W](W) writer structure"] +impl crate::Writable for CONTROL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL1 to value 0"] +impl crate::Resettable for CONTROL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/control2.rs b/crates/bcm2837-lpa/src/emmc/control2.rs new file mode 100644 index 0000000..1bc9076 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/control2.rs @@ -0,0 +1,240 @@ +#[doc = "Register `CONTROL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONTROL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ACNOX_ERR` reader - Auto command not executed due to an error"] +pub type ACNOX_ERR_R = crate::BitReader; +#[doc = "Field `ACTO_ERR` reader - Auto command timeout"] +pub type ACTO_ERR_R = crate::BitReader; +#[doc = "Field `ACCRC_ERR` reader - Command CRC error during auto command"] +pub type ACCRC_ERR_R = crate::BitReader; +#[doc = "Field `ACEND_ERR` reader - End bit is not 1 during auto command"] +pub type ACEND_ERR_R = crate::BitReader; +#[doc = "Field `ACBAD_ERR` reader - Command index error during auto command"] +pub type ACBAD_ERR_R = crate::BitReader; +#[doc = "Field `NOTC12_ERR` reader - Error during auto CMD12"] +pub type NOTC12_ERR_R = crate::BitReader; +#[doc = "Field `UHSMODE` reader - Select the speed of the SD card"] +pub type UHSMODE_R = crate::FieldReader; +#[doc = "Select the speed of the SD card\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum UHSMODE_A { + #[doc = "0: `0`"] + SDR12 = 0, + #[doc = "1: `1`"] + SDR25 = 1, + #[doc = "2: `10`"] + SDR50 = 2, + #[doc = "3: `11`"] + SDR104 = 3, + #[doc = "4: `100`"] + DDR50 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: UHSMODE_A) -> Self { + variant as _ + } +} +impl UHSMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(UHSMODE_A::SDR12), + 1 => Some(UHSMODE_A::SDR25), + 2 => Some(UHSMODE_A::SDR50), + 3 => Some(UHSMODE_A::SDR104), + 4 => Some(UHSMODE_A::DDR50), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SDR12`"] + #[inline(always)] + pub fn is_sdr12(&self) -> bool { + *self == UHSMODE_A::SDR12 + } + #[doc = "Checks if the value of the field is `SDR25`"] + #[inline(always)] + pub fn is_sdr25(&self) -> bool { + *self == UHSMODE_A::SDR25 + } + #[doc = "Checks if the value of the field is `SDR50`"] + #[inline(always)] + pub fn is_sdr50(&self) -> bool { + *self == UHSMODE_A::SDR50 + } + #[doc = "Checks if the value of the field is `SDR104`"] + #[inline(always)] + pub fn is_sdr104(&self) -> bool { + *self == UHSMODE_A::SDR104 + } + #[doc = "Checks if the value of the field is `DDR50`"] + #[inline(always)] + pub fn is_ddr50(&self) -> bool { + *self == UHSMODE_A::DDR50 + } +} +#[doc = "Field `UHSMODE` writer - Select the speed of the SD card"] +pub type UHSMODE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONTROL2_SPEC, u8, UHSMODE_A, 3, O>; +impl<'a, const O: u8> UHSMODE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn sdr12(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR12) + } + #[doc = "`1`"] + #[inline(always)] + pub fn sdr25(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR25) + } + #[doc = "`10`"] + #[inline(always)] + pub fn sdr50(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR50) + } + #[doc = "`11`"] + #[inline(always)] + pub fn sdr104(self) -> &'a mut W { + self.variant(UHSMODE_A::SDR104) + } + #[doc = "`100`"] + #[inline(always)] + pub fn ddr50(self) -> &'a mut W { + self.variant(UHSMODE_A::DDR50) + } +} +#[doc = "Field `TUNEON` reader - SD Clock tune in progress"] +pub type TUNEON_R = crate::BitReader; +#[doc = "Field `TUNEON` writer - SD Clock tune in progress"] +pub type TUNEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +#[doc = "Field `TUNED` reader - Tuned clock is used for sampling data"] +pub type TUNED_R = crate::BitReader; +#[doc = "Field `TUNED` writer - Tuned clock is used for sampling data"] +pub type TUNED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Auto command not executed due to an error"] + #[inline(always)] + pub fn acnox_err(&self) -> ACNOX_ERR_R { + ACNOX_ERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Auto command timeout"] + #[inline(always)] + pub fn acto_err(&self) -> ACTO_ERR_R { + ACTO_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Command CRC error during auto command"] + #[inline(always)] + pub fn accrc_err(&self) -> ACCRC_ERR_R { + ACCRC_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End bit is not 1 during auto command"] + #[inline(always)] + pub fn acend_err(&self) -> ACEND_ERR_R { + ACEND_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Command index error during auto command"] + #[inline(always)] + pub fn acbad_err(&self) -> ACBAD_ERR_R { + ACBAD_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - Error during auto CMD12"] + #[inline(always)] + pub fn notc12_err(&self) -> NOTC12_ERR_R { + NOTC12_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 16:18 - Select the speed of the SD card"] + #[inline(always)] + pub fn uhsmode(&self) -> UHSMODE_R { + UHSMODE_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 22 - SD Clock tune in progress"] + #[inline(always)] + pub fn tuneon(&self) -> TUNEON_R { + TUNEON_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Tuned clock is used for sampling data"] + #[inline(always)] + pub fn tuned(&self) -> TUNED_R { + TUNED_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bits 16:18 - Select the speed of the SD card"] + #[inline(always)] + #[must_use] + pub fn uhsmode(&mut self) -> UHSMODE_W<16> { + UHSMODE_W::new(self) + } + #[doc = "Bit 22 - SD Clock tune in progress"] + #[inline(always)] + #[must_use] + pub fn tuneon(&mut self) -> TUNEON_W<22> { + TUNEON_W::new(self) + } + #[doc = "Bit 23 - Tuned clock is used for sampling data"] + #[inline(always)] + #[must_use] + pub fn tuned(&mut self) -> TUNED_W<23> { + TUNED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control2](index.html) module"] +pub struct CONTROL2_SPEC; +impl crate::RegisterSpec for CONTROL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [control2::R](R) reader structure"] +impl crate::Readable for CONTROL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [control2::W](W) writer structure"] +impl crate::Writable for CONTROL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTROL2 to value 0"] +impl crate::Resettable for CONTROL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/data.rs b/crates/bcm2837-lpa/src/emmc/data.rs new file mode 100644 index 0000000..8c082b8 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/data.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data to/from the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/dbg_sel.rs b/crates/bcm2837-lpa/src/emmc/dbg_sel.rs new file mode 100644 index 0000000..c489a27 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/dbg_sel.rs @@ -0,0 +1,126 @@ +#[doc = "Register `DBG_SEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBG_SEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SELECT` reader - "] +pub type SELECT_R = crate::BitReader; +#[doc = "\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SELECT_A { + #[doc = "0: `0`"] + RECEIVER_FIFO = 0, + #[doc = "1: `1`"] + OTHERS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl SELECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SELECT_A { + match self.bits { + false => SELECT_A::RECEIVER_FIFO, + true => SELECT_A::OTHERS, + } + } + #[doc = "Checks if the value of the field is `RECEIVER_FIFO`"] + #[inline(always)] + pub fn is_receiver_fifo(&self) -> bool { + *self == SELECT_A::RECEIVER_FIFO + } + #[doc = "Checks if the value of the field is `OTHERS`"] + #[inline(always)] + pub fn is_others(&self) -> bool { + *self == SELECT_A::OTHERS + } +} +#[doc = "Field `SELECT` writer - "] +pub type SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DBG_SEL_SPEC, SELECT_A, O>; +impl<'a, const O: u8> SELECT_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn receiver_fifo(self) -> &'a mut W { + self.variant(SELECT_A::RECEIVER_FIFO) + } + #[doc = "`1`"] + #[inline(always)] + pub fn others(self) -> &'a mut W { + self.variant(SELECT_A::OTHERS) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W<0> { + SELECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "What submodules are accessed by the debug bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbg_sel](index.html) module"] +pub struct DBG_SEL_SPEC; +impl crate::RegisterSpec for DBG_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbg_sel::R](R) reader structure"] +impl crate::Readable for DBG_SEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbg_sel::W](W) writer structure"] +impl crate::Writable for DBG_SEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBG_SEL to value 0"] +impl crate::Resettable for DBG_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs b/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs new file mode 100644 index 0000000..1c7e3be --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EXRDFIFO_CFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXRDFIFO_CFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RD_THRSH` reader - Read threshold in 32 bit words"] +pub type RD_THRSH_R = crate::FieldReader; +#[doc = "Field `RD_THRSH` writer - Read threshold in 32 bit words"] +pub type RD_THRSH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXRDFIFO_CFG_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Read threshold in 32 bit words"] + #[inline(always)] + pub fn rd_thrsh(&self) -> RD_THRSH_R { + RD_THRSH_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Read threshold in 32 bit words"] + #[inline(always)] + #[must_use] + pub fn rd_thrsh(&mut self) -> RD_THRSH_W<0> { + RD_THRSH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fine tune DMA request generation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_cfg](index.html) module"] +pub struct EXRDFIFO_CFG_SPEC; +impl crate::RegisterSpec for EXRDFIFO_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [exrdfifo_cfg::R](R) reader structure"] +impl crate::Readable for EXRDFIFO_CFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [exrdfifo_cfg::W](W) writer structure"] +impl crate::Writable for EXRDFIFO_CFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXRDFIFO_CFG to value 0"] +impl crate::Resettable for EXRDFIFO_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs b/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs new file mode 100644 index 0000000..26c7adc --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EXRDFIFO_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXRDFIFO_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable the extension FIFO"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable the extension FIFO"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXRDFIFO_EN_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable the extension FIFO"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the extension FIFO"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<0> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable the extension data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_en](index.html) module"] +pub struct EXRDFIFO_EN_SPEC; +impl crate::RegisterSpec for EXRDFIFO_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [exrdfifo_en::R](R) reader structure"] +impl crate::Readable for EXRDFIFO_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [exrdfifo_en::W](W) writer structure"] +impl crate::Writable for EXRDFIFO_EN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXRDFIFO_EN to value 0"] +impl crate::Resettable for EXRDFIFO_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/force_irpt.rs b/crates/bcm2837-lpa/src/emmc/force_irpt.rs new file mode 100644 index 0000000..eca9ec6 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/force_irpt.rs @@ -0,0 +1,320 @@ +#[doc = "Register `FORCE_IRPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FORCE_IRPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Force an interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [force_irpt](index.html) module"] +pub struct FORCE_IRPT_SPEC; +impl crate::RegisterSpec for FORCE_IRPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [force_irpt::R](R) reader structure"] +impl crate::Readable for FORCE_IRPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [force_irpt::W](W) writer structure"] +impl crate::Writable for FORCE_IRPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FORCE_IRPT to value 0"] +impl crate::Resettable for FORCE_IRPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/interrupt.rs b/crates/bcm2837-lpa/src/emmc/interrupt.rs new file mode 100644 index 0000000..c687814 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/interrupt.rs @@ -0,0 +1,327 @@ +#[doc = "Register `INTERRUPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTERRUPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ERR` reader - An error has occured"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - An error has occured"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt flags\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"] +pub struct INTERRUPT_SPEC; +impl crate::RegisterSpec for INTERRUPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [interrupt::R](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"] +impl crate::Writable for INTERRUPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTERRUPT to value 0"] +impl crate::Resettable for INTERRUPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/irpt_en.rs b/crates/bcm2837-lpa/src/emmc/irpt_en.rs new file mode 100644 index 0000000..0e71317 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/irpt_en.rs @@ -0,0 +1,320 @@ +#[doc = "Register `IRPT_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRPT_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupt to core\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_en](index.html) module"] +pub struct IRPT_EN_SPEC; +impl crate::RegisterSpec for IRPT_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irpt_en::R](R) reader structure"] +impl crate::Readable for IRPT_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irpt_en::W](W) writer structure"] +impl crate::Writable for IRPT_EN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRPT_EN to value 0"] +impl crate::Resettable for IRPT_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/irpt_mask.rs b/crates/bcm2837-lpa/src/emmc/irpt_mask.rs new file mode 100644 index 0000000..87a9fdd --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/irpt_mask.rs @@ -0,0 +1,320 @@ +#[doc = "Register `IRPT_MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRPT_MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_DONE` reader - Command has finished"] +pub type CMD_DONE_R = crate::BitReader; +#[doc = "Field `CMD_DONE` writer - Command has finished"] +pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DATA_DONE` reader - Data transfer has finished"] +pub type DATA_DONE_R = crate::BitReader; +#[doc = "Field `DATA_DONE` writer - Data transfer has finished"] +pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_R = crate::BitReader; +#[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] +pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `WRITE_RDY` reader - DATA can be written to"] +pub type WRITE_RDY_R = crate::BitReader; +#[doc = "Field `WRITE_RDY` writer - DATA can be written to"] +pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `READ_RDY` reader - DATA contains data to be read"] +pub type READ_RDY_R = crate::BitReader; +#[doc = "Field `READ_RDY` writer - DATA contains data to be read"] +pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CARD` reader - Card made interrupt request"] +pub type CARD_R = crate::BitReader; +#[doc = "Field `CARD` writer - Card made interrupt request"] +pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `RETUNE` reader - Clock retune request"] +pub type RETUNE_R = crate::BitReader; +#[doc = "Field `RETUNE` writer - Clock retune request"] +pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] +pub type BOOTACK_R = crate::BitReader; +#[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] +pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] +pub type ENDBOOT_R = crate::BitReader; +#[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] +pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CTO_ERR` reader - Command timeout"] +pub type CTO_ERR_R = crate::BitReader; +#[doc = "Field `CTO_ERR` writer - Command timeout"] +pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CCRC_ERR` reader - Command CRC error"] +pub type CCRC_ERR_R = crate::BitReader; +#[doc = "Field `CCRC_ERR` writer - Command CRC error"] +pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] +pub type CEND_ERR_R = crate::BitReader; +#[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] +pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] +pub type CBAD_ERR_R = crate::BitReader; +#[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] +pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DTO_ERR` reader - Data timeout"] +pub type DTO_ERR_R = crate::BitReader; +#[doc = "Field `DTO_ERR` writer - Data timeout"] +pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DCRC_ERR` reader - Data CRC error"] +pub type DCRC_ERR_R = crate::BitReader; +#[doc = "Field `DCRC_ERR` writer - Data CRC error"] +pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] +pub type DEND_ERR_R = crate::BitReader; +#[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] +pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +#[doc = "Field `ACMD_ERR` reader - Auto command error"] +pub type ACMD_ERR_R = crate::BitReader; +#[doc = "Field `ACMD_ERR` writer - Auto command error"] +pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + pub fn cmd_done(&self) -> CMD_DONE_R { + CMD_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + pub fn data_done(&self) -> DATA_DONE_R { + DATA_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + pub fn block_gap(&self) -> BLOCK_GAP_R { + BLOCK_GAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + pub fn write_rdy(&self) -> WRITE_RDY_R { + WRITE_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + pub fn read_rdy(&self) -> READ_RDY_R { + READ_RDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + pub fn card(&self) -> CARD_R { + CARD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + pub fn retune(&self) -> RETUNE_R { + RETUNE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + pub fn bootack(&self) -> BOOTACK_R { + BOOTACK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + pub fn endboot(&self) -> ENDBOOT_R { + ENDBOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + pub fn cto_err(&self) -> CTO_ERR_R { + CTO_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + pub fn ccrc_err(&self) -> CCRC_ERR_R { + CCRC_ERR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + pub fn cend_err(&self) -> CEND_ERR_R { + CEND_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + pub fn cbad_err(&self) -> CBAD_ERR_R { + CBAD_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + pub fn dto_err(&self) -> DTO_ERR_R { + DTO_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + pub fn dcrc_err(&self) -> DCRC_ERR_R { + DCRC_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + pub fn dend_err(&self) -> DEND_ERR_R { + DEND_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + pub fn acmd_err(&self) -> ACMD_ERR_R { + ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Command has finished"] + #[inline(always)] + #[must_use] + pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + CMD_DONE_W::new(self) + } + #[doc = "Bit 1 - Data transfer has finished"] + #[inline(always)] + #[must_use] + pub fn data_done(&mut self) -> DATA_DONE_W<1> { + DATA_DONE_W::new(self) + } + #[doc = "Bit 2 - Data transfer has stopped at block gap"] + #[inline(always)] + #[must_use] + pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + BLOCK_GAP_W::new(self) + } + #[doc = "Bit 4 - DATA can be written to"] + #[inline(always)] + #[must_use] + pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + WRITE_RDY_W::new(self) + } + #[doc = "Bit 5 - DATA contains data to be read"] + #[inline(always)] + #[must_use] + pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + READ_RDY_W::new(self) + } + #[doc = "Bit 8 - Card made interrupt request"] + #[inline(always)] + #[must_use] + pub fn card(&mut self) -> CARD_W<8> { + CARD_W::new(self) + } + #[doc = "Bit 12 - Clock retune request"] + #[inline(always)] + #[must_use] + pub fn retune(&mut self) -> RETUNE_W<12> { + RETUNE_W::new(self) + } + #[doc = "Bit 13 - Boot has been acknowledged"] + #[inline(always)] + #[must_use] + pub fn bootack(&mut self) -> BOOTACK_W<13> { + BOOTACK_W::new(self) + } + #[doc = "Bit 14 - Boot operation has terminated"] + #[inline(always)] + #[must_use] + pub fn endboot(&mut self) -> ENDBOOT_W<14> { + ENDBOOT_W::new(self) + } + #[doc = "Bit 16 - Command timeout"] + #[inline(always)] + #[must_use] + pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + CTO_ERR_W::new(self) + } + #[doc = "Bit 17 - Command CRC error"] + #[inline(always)] + #[must_use] + pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + CCRC_ERR_W::new(self) + } + #[doc = "Bit 18 - Command end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + CEND_ERR_W::new(self) + } + #[doc = "Bit 19 - Incorrect response command index"] + #[inline(always)] + #[must_use] + pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + CBAD_ERR_W::new(self) + } + #[doc = "Bit 20 - Data timeout"] + #[inline(always)] + #[must_use] + pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + DTO_ERR_W::new(self) + } + #[doc = "Bit 21 - Data CRC error"] + #[inline(always)] + #[must_use] + pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + DCRC_ERR_W::new(self) + } + #[doc = "Bit 22 - Data end bit error (not 1)"] + #[inline(always)] + #[must_use] + pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + DEND_ERR_W::new(self) + } + #[doc = "Bit 24 - Auto command error"] + #[inline(always)] + #[must_use] + pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + ACMD_ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Mask interrupts that change in INTERRUPT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_mask](index.html) module"] +pub struct IRPT_MASK_SPEC; +impl crate::RegisterSpec for IRPT_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irpt_mask::R](R) reader structure"] +impl crate::Readable for IRPT_MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irpt_mask::W](W) writer structure"] +impl crate::Writable for IRPT_MASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRPT_MASK to value 0"] +impl crate::Resettable for IRPT_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/resp0.rs b/crates/bcm2837-lpa/src/emmc/resp0.rs new file mode 100644 index 0000000..1022d1a --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/resp0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status bits of the response\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp0](index.html) module"] +pub struct RESP0_SPEC; +impl crate::RegisterSpec for RESP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp0::R](R) reader structure"] +impl crate::Readable for RESP0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp0::W](W) writer structure"] +impl crate::Writable for RESP0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP0 to value 0"] +impl crate::Resettable for RESP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/resp1.rs b/crates/bcm2837-lpa/src/emmc/resp1.rs new file mode 100644 index 0000000..d1e9b42 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/resp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp1](index.html) module"] +pub struct RESP1_SPEC; +impl crate::RegisterSpec for RESP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp1::R](R) reader structure"] +impl crate::Readable for RESP1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp1::W](W) writer structure"] +impl crate::Writable for RESP1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP1 to value 0"] +impl crate::Resettable for RESP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/resp2.rs b/crates/bcm2837-lpa/src/emmc/resp2.rs new file mode 100644 index 0000000..418942a --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/resp2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp2](index.html) module"] +pub struct RESP2_SPEC; +impl crate::RegisterSpec for RESP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp2::R](R) reader structure"] +impl crate::Readable for RESP2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp2::W](W) writer structure"] +impl crate::Writable for RESP2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP2 to value 0"] +impl crate::Resettable for RESP2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/resp3.rs b/crates/bcm2837-lpa/src/emmc/resp3.rs new file mode 100644 index 0000000..36b2c80 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/resp3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESP3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RESP3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp3](index.html) module"] +pub struct RESP3_SPEC; +impl crate::RegisterSpec for RESP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [resp3::R](R) reader structure"] +impl crate::Readable for RESP3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [resp3::W](W) writer structure"] +impl crate::Writable for RESP3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESP3 to value 0"] +impl crate::Resettable for RESP3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs b/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs new file mode 100644 index 0000000..6016436 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SLOTISR_VER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLOTISR_VER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_STATUS` reader - OR of interrupt and wakeup signals for each slot"] +pub type SLOT_STATUS_R = crate::FieldReader; +#[doc = "Field `SLOT_STATUS` writer - OR of interrupt and wakeup signals for each slot"] +pub type SLOT_STATUS_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +#[doc = "Field `SDVERSION` reader - Host controller specification version"] +pub type SDVERSION_R = crate::FieldReader; +#[doc = "Field `SDVERSION` writer - Host controller specification version"] +pub type SDVERSION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +#[doc = "Field `VENDOR` reader - Vendor version number"] +pub type VENDOR_R = crate::FieldReader; +#[doc = "Field `VENDOR` writer - Vendor version number"] +pub type VENDOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] + #[inline(always)] + pub fn slot_status(&self) -> SLOT_STATUS_R { + SLOT_STATUS_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Host controller specification version"] + #[inline(always)] + pub fn sdversion(&self) -> SDVERSION_R { + SDVERSION_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Vendor version number"] + #[inline(always)] + pub fn vendor(&self) -> VENDOR_R { + VENDOR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] + #[inline(always)] + #[must_use] + pub fn slot_status(&mut self) -> SLOT_STATUS_W<0> { + SLOT_STATUS_W::new(self) + } + #[doc = "Bits 16:23 - Host controller specification version"] + #[inline(always)] + #[must_use] + pub fn sdversion(&mut self) -> SDVERSION_W<16> { + SDVERSION_W::new(self) + } + #[doc = "Bits 24:31 - Vendor version number"] + #[inline(always)] + #[must_use] + pub fn vendor(&mut self) -> VENDOR_W<24> { + VENDOR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Version information and slot interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slotisr_ver](index.html) module"] +pub struct SLOTISR_VER_SPEC; +impl crate::RegisterSpec for SLOTISR_VER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [slotisr_ver::R](R) reader structure"] +impl crate::Readable for SLOTISR_VER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [slotisr_ver::W](W) writer structure"] +impl crate::Writable for SLOTISR_VER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLOTISR_VER to value 0"] +impl crate::Resettable for SLOTISR_VER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs b/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs new file mode 100644 index 0000000..bce7edc --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SPI_INT_SPT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SPI_INT_SPT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SELECT` reader - "] +pub type SELECT_R = crate::FieldReader; +#[doc = "Field `SELECT` writer - "] +pub type SELECT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_INT_SPT_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W<0> { + SELECT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupts in SPI mode depend on CS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_int_spt](index.html) module"] +pub struct SPI_INT_SPT_SPEC; +impl crate::RegisterSpec for SPI_INT_SPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [spi_int_spt::R](R) reader structure"] +impl crate::Readable for SPI_INT_SPT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [spi_int_spt::W](W) writer structure"] +impl crate::Writable for SPI_INT_SPT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_INT_SPT to value 0"] +impl crate::Resettable for SPI_INT_SPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/status.rs b/crates/bcm2837-lpa/src/emmc/status.rs new file mode 100644 index 0000000..0b86ab0 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/status.rs @@ -0,0 +1,215 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD_INHIBIT` reader - Command line still in use"] +pub type CMD_INHIBIT_R = crate::BitReader; +#[doc = "Field `CMD_INHIBIT` writer - Command line still in use"] +pub type CMD_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_INHIBIT` reader - Data lines still in use"] +pub type DAT_INHIBIT_R = crate::BitReader; +#[doc = "Field `DAT_INHIBIT` writer - Data lines still in use"] +pub type DAT_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_ACTIVE` reader - At least one data line is active"] +pub type DAT_ACTIVE_R = crate::BitReader; +#[doc = "Field `DAT_ACTIVE` writer - At least one data line is active"] +pub type DAT_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `WRITE_TRANSFER` reader - Write transfer is active"] +pub type WRITE_TRANSFER_R = crate::BitReader; +#[doc = "Field `WRITE_TRANSFER` writer - Write transfer is active"] +pub type WRITE_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `READ_TRANSFER` reader - Read transfer is active"] +pub type READ_TRANSFER_R = crate::BitReader; +#[doc = "Field `READ_TRANSFER` writer - Read transfer is active"] +pub type READ_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFFER_WRITE_ENABLE` reader - The buffer has space for new data"] +pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; +#[doc = "Field `BUFFER_WRITE_ENABLE` writer - The buffer has space for new data"] +pub type BUFFER_WRITE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFFER_READ_ENABLE` reader - New data is available to read"] +pub type BUFFER_READ_ENABLE_R = crate::BitReader; +#[doc = "Field `BUFFER_READ_ENABLE` writer - New data is available to read"] +pub type BUFFER_READ_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_LEVEL0` reader - Value of DAT\\[3:0\\]"] +pub type DAT_LEVEL0_R = crate::FieldReader; +#[doc = "Field `DAT_LEVEL0` writer - Value of DAT\\[3:0\\]"] +pub type DAT_LEVEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +#[doc = "Field `CMD_LEVEL` reader - Value of CMD"] +pub type CMD_LEVEL_R = crate::BitReader; +#[doc = "Field `CMD_LEVEL` writer - Value of CMD"] +pub type CMD_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DAT_LEVEL1` reader - Value of DAT\\[7:4\\]"] +pub type DAT_LEVEL1_R = crate::FieldReader; +#[doc = "Field `DAT_LEVEL1` writer - Value of DAT\\[7:4\\]"] +pub type DAT_LEVEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Command line still in use"] + #[inline(always)] + pub fn cmd_inhibit(&self) -> CMD_INHIBIT_R { + CMD_INHIBIT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data lines still in use"] + #[inline(always)] + pub fn dat_inhibit(&self) -> DAT_INHIBIT_R { + DAT_INHIBIT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - At least one data line is active"] + #[inline(always)] + pub fn dat_active(&self) -> DAT_ACTIVE_R { + DAT_ACTIVE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Write transfer is active"] + #[inline(always)] + pub fn write_transfer(&self) -> WRITE_TRANSFER_R { + WRITE_TRANSFER_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Read transfer is active"] + #[inline(always)] + pub fn read_transfer(&self) -> READ_TRANSFER_R { + READ_TRANSFER_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The buffer has space for new data"] + #[inline(always)] + pub fn buffer_write_enable(&self) -> BUFFER_WRITE_ENABLE_R { + BUFFER_WRITE_ENABLE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - New data is available to read"] + #[inline(always)] + pub fn buffer_read_enable(&self) -> BUFFER_READ_ENABLE_R { + BUFFER_READ_ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] + #[inline(always)] + pub fn dat_level0(&self) -> DAT_LEVEL0_R { + DAT_LEVEL0_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - Value of CMD"] + #[inline(always)] + pub fn cmd_level(&self) -> CMD_LEVEL_R { + CMD_LEVEL_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] + #[inline(always)] + pub fn dat_level1(&self) -> DAT_LEVEL1_R { + DAT_LEVEL1_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Command line still in use"] + #[inline(always)] + #[must_use] + pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W<0> { + CMD_INHIBIT_W::new(self) + } + #[doc = "Bit 1 - Data lines still in use"] + #[inline(always)] + #[must_use] + pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W<1> { + DAT_INHIBIT_W::new(self) + } + #[doc = "Bit 2 - At least one data line is active"] + #[inline(always)] + #[must_use] + pub fn dat_active(&mut self) -> DAT_ACTIVE_W<2> { + DAT_ACTIVE_W::new(self) + } + #[doc = "Bit 8 - Write transfer is active"] + #[inline(always)] + #[must_use] + pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W<8> { + WRITE_TRANSFER_W::new(self) + } + #[doc = "Bit 9 - Read transfer is active"] + #[inline(always)] + #[must_use] + pub fn read_transfer(&mut self) -> READ_TRANSFER_W<9> { + READ_TRANSFER_W::new(self) + } + #[doc = "Bit 10 - The buffer has space for new data"] + #[inline(always)] + #[must_use] + pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W<10> { + BUFFER_WRITE_ENABLE_W::new(self) + } + #[doc = "Bit 11 - New data is available to read"] + #[inline(always)] + #[must_use] + pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W<11> { + BUFFER_READ_ENABLE_W::new(self) + } + #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn dat_level0(&mut self) -> DAT_LEVEL0_W<20> { + DAT_LEVEL0_W::new(self) + } + #[doc = "Bit 24 - Value of CMD"] + #[inline(always)] + #[must_use] + pub fn cmd_level(&mut self) -> CMD_LEVEL_W<24> { + CMD_LEVEL_W::new(self) + } + #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] + #[inline(always)] + #[must_use] + pub fn dat_level1(&mut self) -> DAT_LEVEL1_W<25> { + DAT_LEVEL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status info for debugging\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/tune_step.rs b/crates/bcm2837-lpa/src/emmc/tune_step.rs new file mode 100644 index 0000000..2f0169b --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/tune_step.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DELAY` reader - "] +pub type DELAY_R = crate::FieldReader; +#[doc = "Field `DELAY` writer - "] +pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEP_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn delay(&self) -> DELAY_R { + DELAY_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2"] + #[inline(always)] + #[must_use] + pub fn delay(&mut self) -> DELAY_W<0> { + DELAY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step duration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_step](index.html) module"] +pub struct TUNE_STEP_SPEC; +impl crate::RegisterSpec for TUNE_STEP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_step::R](R) reader structure"] +impl crate::Readable for TUNE_STEP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_step::W](W) writer structure"] +impl crate::Writable for TUNE_STEP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEP to value 0"] +impl crate::Resettable for TUNE_STEP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs b/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs new file mode 100644 index 0000000..a8fea76 --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEPS_DDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEPS_DDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STEPS` reader - "] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - "] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_DDR_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<0> { + STEPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step count for DDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_ddr](index.html) module"] +pub struct TUNE_STEPS_DDR_SPEC; +impl crate::RegisterSpec for TUNE_STEPS_DDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_steps_ddr::R](R) reader structure"] +impl crate::Readable for TUNE_STEPS_DDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_steps_ddr::W](W) writer structure"] +impl crate::Writable for TUNE_STEPS_DDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEPS_DDR to value 0"] +impl crate::Resettable for TUNE_STEPS_DDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs b/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs new file mode 100644 index 0000000..c04740c --- /dev/null +++ b/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TUNE_STEPS_STD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TUNE_STEPS_STD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STEPS` reader - "] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - "] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_STD_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<0> { + STEPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample clock delay step count for SDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_std](index.html) module"] +pub struct TUNE_STEPS_STD_SPEC; +impl crate::RegisterSpec for TUNE_STEPS_STD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tune_steps_std::R](R) reader structure"] +impl crate::Readable for TUNE_STEPS_STD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tune_steps_std::W](W) writer structure"] +impl crate::Writable for TUNE_STEPS_STD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TUNE_STEPS_STD to value 0"] +impl crate::Resettable for TUNE_STEPS_STD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/generic.rs b/crates/bcm2837-lpa/src/generic.rs new file mode 100644 index 0000000..f10ca73 --- /dev/null +++ b/crates/bcm2837-lpa/src/generic.rs @@ -0,0 +1,695 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc(hidden)] +pub struct FieldReaderRaw { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReaderRaw +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitReaderRaw { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReaderRaw { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = FieldReaderRaw; +#[doc = " Bit-wise field reader"] +pub type BitReader = BitReaderRaw; +impl FieldReader +where + U: Copy, +{ + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy, + U: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&U::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc(hidden)] +pub struct Safe; +#[doc(hidden)] +pub struct Unsafe; +#[doc(hidden)] +pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> +where + REG: Writable + RegisterSpec, + N: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(N, FI, Safety)>, +} +impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> + FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + } + }; +} +macro_rules! impl_bit_proxy { + ($ writer : ident) => { + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, + { + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w.bits |= (U::from(value) & U::one()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + unsafe { self.bits(N::from(variant)) } + } +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bits(N::from(variant)) + } +} +impl_bit_proxy!(BitWriter); +impl_bit_proxy!(BitWriter1S); +impl_bit_proxy!(BitWriter0C); +impl_bit_proxy!(BitWriter1C); +impl_bit_proxy!(BitWriter0S); +impl_bit_proxy!(BitWriter1T); +impl_bit_proxy!(BitWriter0T); +impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +mod atomic; +use atomic::AtomicOperations; +impl Reg +where + REG::Ux: AtomicOperations + Default + core::ops::Not, +{ + #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn set_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: Default::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_or(self.register.as_ptr(), bits); + } + #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn clear_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: !REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_and(self.register.as_ptr(), bits); + } + #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn toggle_bits(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + let bits = f(&mut REG::Writer::from(W { + bits: Default::default(), + _reg: marker::PhantomData, + })) + .bits; + REG::Ux::atomic_xor(self.register.as_ptr(), bits); + } +} diff --git a/crates/bcm2837-lpa/src/generic/atomic.rs b/crates/bcm2837-lpa/src/generic/atomic.rs new file mode 100644 index 0000000..acee997 --- /dev/null +++ b/crates/bcm2837-lpa/src/generic/atomic.rs @@ -0,0 +1,27 @@ +use portable_atomic::Ordering; +pub trait AtomicOperations { + unsafe fn atomic_or(ptr: *mut Self, val: Self); + unsafe fn atomic_and(ptr: *mut Self, val: Self); + unsafe fn atomic_xor(ptr: *mut Self, val: Self); +} +macro_rules! impl_atomics { + ($ U : ty , $ Atomic : ty) => { + impl AtomicOperations for $U { + unsafe fn atomic_or(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).or(val, Ordering::SeqCst); + } + unsafe fn atomic_and(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).and(val, Ordering::SeqCst); + } + unsafe fn atomic_xor(ptr: *mut Self, val: Self) { + (*(ptr as *const $Atomic)).xor(val, Ordering::SeqCst); + } + } + }; +} +impl_atomics!(u8, portable_atomic::AtomicU8); +impl_atomics!(u16, portable_atomic::AtomicU16); +#[cfg(not(target_pointer_width = "16"))] +impl_atomics!(u32, portable_atomic::AtomicU32); +#[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))] +impl_atomics!(u64, portable_atomic::AtomicU64); diff --git a/crates/bcm2837-lpa/src/gpio.rs b/crates/bcm2837-lpa/src/gpio.rs new file mode 100644 index 0000000..e643036 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio.rs @@ -0,0 +1,206 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - GPIO Function Select 0"] + pub gpfsel0: GPFSEL0, + #[doc = "0x04 - GPIO Function Select 1"] + pub gpfsel1: GPFSEL1, + #[doc = "0x08 - GPIO Function Select 2"] + pub gpfsel2: GPFSEL2, + #[doc = "0x0c - GPIO Function Select 3"] + pub gpfsel3: GPFSEL3, + #[doc = "0x10 - GPIO Function Select 4"] + pub gpfsel4: GPFSEL4, + #[doc = "0x14 - GPIO Function Select 5"] + pub gpfsel5: GPFSEL5, + _reserved6: [u8; 0x04], + #[doc = "0x1c - GPIO Pin Output Set 0"] + pub gpset0: GPSET0, + #[doc = "0x20 - GPIO Pin Output Set 1"] + pub gpset1: GPSET1, + _reserved8: [u8; 0x04], + #[doc = "0x28 - GPIO Pin Output Clear 0"] + pub gpclr0: GPCLR0, + #[doc = "0x2c - GPIO Pin Output Clear 1"] + pub gpclr1: GPCLR1, + _reserved10: [u8; 0x04], + #[doc = "0x34 - GPIO Pin Level 0"] + pub gplev0: GPLEV0, + #[doc = "0x38 - GPIO Pin Level 1"] + pub gplev1: GPLEV1, + _reserved12: [u8; 0x04], + #[doc = "0x40 - GPIO Pin Event Detect Status 0"] + pub gpeds0: GPEDS0, + #[doc = "0x44 - GPIO Pin Event Detect Status 1"] + pub gpeds1: GPEDS1, + _reserved14: [u8; 0x04], + #[doc = "0x4c - GPIO Pin Rising Edge Detect Enable 0"] + pub gpren0: GPREN0, + #[doc = "0x50 - GPIO Pin Rising Edge Detect Enable 1"] + pub gpren1: GPREN1, + _reserved16: [u8; 0x04], + #[doc = "0x58 - GPIO Pin Falling Edge Detect Enable 0"] + pub gpfen0: GPFEN0, + #[doc = "0x5c - GPIO Pin Falling Edge Detect Enable 1"] + pub gpfen1: GPFEN1, + _reserved18: [u8; 0x04], + #[doc = "0x64 - GPIO Pin High Detect Enable 0"] + pub gphen0: GPHEN0, + #[doc = "0x68 - GPIO Pin High Detect Enable 1"] + pub gphen1: GPHEN1, + _reserved20: [u8; 0x04], + #[doc = "0x70 - GPIO Pin Low Detect Enable 0"] + pub gplen0: GPLEN0, + #[doc = "0x74 - GPIO Pin Low Detect Enable 1"] + pub gplen1: GPLEN1, + _reserved22: [u8; 0x04], + #[doc = "0x7c - GPIO Pin Async. Rising Edge Detect 0"] + pub gparen0: GPAREN0, + #[doc = "0x80 - GPIO Pin Async. Rising Edge Detect 1"] + pub gparen1: GPAREN1, + _reserved24: [u8; 0x04], + #[doc = "0x88 - GPIO Pin Async. Falling Edge Detect 0"] + pub gpafen0: GPAFEN0, + #[doc = "0x8c - GPIO Pin Async. Falling Edge Detect 1"] + pub gpafen1: GPAFEN1, + _reserved26: [u8; 0x40], + #[doc = "0xd0 - Undocumented multiplexing bits"] + pub extra_mux: EXTRA_MUX, + _reserved27: [u8; 0x10], + #[doc = "0xe4 - GPIO Pull-up / Pull-down Register 0"] + pub gpio_pup_pdn_cntrl_reg0: GPIO_PUP_PDN_CNTRL_REG0, + #[doc = "0xe8 - GPIO Pull-up / Pull-down Register 1"] + pub gpio_pup_pdn_cntrl_reg1: GPIO_PUP_PDN_CNTRL_REG1, + #[doc = "0xec - GPIO Pull-up / Pull-down Register 2"] + pub gpio_pup_pdn_cntrl_reg2: GPIO_PUP_PDN_CNTRL_REG2, + #[doc = "0xf0 - GPIO Pull-up / Pull-down Register 3"] + pub gpio_pup_pdn_cntrl_reg3: GPIO_PUP_PDN_CNTRL_REG3, +} +#[doc = "GPFSEL0 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL0 = crate::Reg; +#[doc = "GPIO Function Select 0"] +pub mod gpfsel0; +#[doc = "GPFSEL1 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL1 = crate::Reg; +#[doc = "GPIO Function Select 1"] +pub mod gpfsel1; +#[doc = "GPFSEL2 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL2 = crate::Reg; +#[doc = "GPIO Function Select 2"] +pub mod gpfsel2; +#[doc = "GPFSEL3 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL3 = crate::Reg; +#[doc = "GPIO Function Select 3"] +pub mod gpfsel3; +#[doc = "GPFSEL4 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL4 = crate::Reg; +#[doc = "GPIO Function Select 4"] +pub mod gpfsel4; +#[doc = "GPFSEL5 (rw) register accessor: an alias for `Reg`"] +pub type GPFSEL5 = crate::Reg; +#[doc = "GPIO Function Select 5"] +pub mod gpfsel5; +#[doc = "GPSET0 (w) register accessor: an alias for `Reg`"] +pub type GPSET0 = crate::Reg; +#[doc = "GPIO Pin Output Set 0"] +pub mod gpset0; +#[doc = "GPSET1 (w) register accessor: an alias for `Reg`"] +pub type GPSET1 = crate::Reg; +#[doc = "GPIO Pin Output Set 1"] +pub mod gpset1; +#[doc = "GPCLR0 (w) register accessor: an alias for `Reg`"] +pub type GPCLR0 = crate::Reg; +#[doc = "GPIO Pin Output Clear 0"] +pub mod gpclr0; +#[doc = "GPCLR1 (w) register accessor: an alias for `Reg`"] +pub type GPCLR1 = crate::Reg; +#[doc = "GPIO Pin Output Clear 1"] +pub mod gpclr1; +#[doc = "GPLEV0 (r) register accessor: an alias for `Reg`"] +pub type GPLEV0 = crate::Reg; +#[doc = "GPIO Pin Level 0"] +pub mod gplev0; +#[doc = "GPLEV1 (r) register accessor: an alias for `Reg`"] +pub type GPLEV1 = crate::Reg; +#[doc = "GPIO Pin Level 1"] +pub mod gplev1; +#[doc = "GPEDS0 (rw) register accessor: an alias for `Reg`"] +pub type GPEDS0 = crate::Reg; +#[doc = "GPIO Pin Event Detect Status 0"] +pub mod gpeds0; +#[doc = "GPEDS1 (rw) register accessor: an alias for `Reg`"] +pub type GPEDS1 = crate::Reg; +#[doc = "GPIO Pin Event Detect Status 1"] +pub mod gpeds1; +#[doc = "GPREN0 (rw) register accessor: an alias for `Reg`"] +pub type GPREN0 = crate::Reg; +#[doc = "GPIO Pin Rising Edge Detect Enable 0"] +pub mod gpren0; +#[doc = "GPREN1 (rw) register accessor: an alias for `Reg`"] +pub type GPREN1 = crate::Reg; +#[doc = "GPIO Pin Rising Edge Detect Enable 1"] +pub mod gpren1; +#[doc = "GPFEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPFEN0 = crate::Reg; +#[doc = "GPIO Pin Falling Edge Detect Enable 0"] +pub mod gpfen0; +#[doc = "GPFEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPFEN1 = crate::Reg; +#[doc = "GPIO Pin Falling Edge Detect Enable 1"] +pub mod gpfen1; +#[doc = "GPHEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPHEN0 = crate::Reg; +#[doc = "GPIO Pin High Detect Enable 0"] +pub mod gphen0; +#[doc = "GPHEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPHEN1 = crate::Reg; +#[doc = "GPIO Pin High Detect Enable 1"] +pub mod gphen1; +#[doc = "GPLEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPLEN0 = crate::Reg; +#[doc = "GPIO Pin Low Detect Enable 0"] +pub mod gplen0; +#[doc = "GPLEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPLEN1 = crate::Reg; +#[doc = "GPIO Pin Low Detect Enable 1"] +pub mod gplen1; +#[doc = "GPAREN0 (rw) register accessor: an alias for `Reg`"] +pub type GPAREN0 = crate::Reg; +#[doc = "GPIO Pin Async. Rising Edge Detect 0"] +pub mod gparen0; +#[doc = "GPAREN1 (rw) register accessor: an alias for `Reg`"] +pub type GPAREN1 = crate::Reg; +#[doc = "GPIO Pin Async. Rising Edge Detect 1"] +pub mod gparen1; +#[doc = "GPAFEN0 (rw) register accessor: an alias for `Reg`"] +pub type GPAFEN0 = crate::Reg; +#[doc = "GPIO Pin Async. Falling Edge Detect 0"] +pub mod gpafen0; +#[doc = "GPAFEN1 (rw) register accessor: an alias for `Reg`"] +pub type GPAFEN1 = crate::Reg; +#[doc = "GPIO Pin Async. Falling Edge Detect 1"] +pub mod gpafen1; +#[doc = "EXTRA_MUX (rw) register accessor: an alias for `Reg`"] +pub type EXTRA_MUX = crate::Reg; +#[doc = "Undocumented multiplexing bits"] +pub mod extra_mux; +#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG0 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 0"] +pub mod gpio_pup_pdn_cntrl_reg0; +#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG1 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 1"] +pub mod gpio_pup_pdn_cntrl_reg1; +#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG2 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 2"] +pub mod gpio_pup_pdn_cntrl_reg2; +#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: an alias for `Reg`"] +pub type GPIO_PUP_PDN_CNTRL_REG3 = + crate::Reg; +#[doc = "GPIO Pull-up / Pull-down Register 3"] +pub mod gpio_pup_pdn_cntrl_reg3; diff --git a/crates/bcm2837-lpa/src/gpio/extra_mux.rs b/crates/bcm2837-lpa/src/gpio/extra_mux.rs new file mode 100644 index 0000000..a35ba4f --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/extra_mux.rs @@ -0,0 +1,122 @@ +#[doc = "Register `EXTRA_MUX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EXTRA_MUX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDIO` reader - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +pub type SDIO_R = crate::BitReader; +#[doc = "Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SDIO_A { + #[doc = "0: Connect the newer SD host"] + SDHOST = 0, + #[doc = "1: Connect Arasan SD/EMMC host"] + ARASAN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SDIO_A) -> Self { + variant as u8 != 0 + } +} +impl SDIO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDIO_A { + match self.bits { + false => SDIO_A::SDHOST, + true => SDIO_A::ARASAN, + } + } + #[doc = "Checks if the value of the field is `SDHOST`"] + #[inline(always)] + pub fn is_sdhost(&self) -> bool { + *self == SDIO_A::SDHOST + } + #[doc = "Checks if the value of the field is `ARASAN`"] + #[inline(always)] + pub fn is_arasan(&self) -> bool { + *self == SDIO_A::ARASAN + } +} +#[doc = "Field `SDIO` writer - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] +pub type SDIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTRA_MUX_SPEC, SDIO_A, O>; +impl<'a, const O: u8> SDIO_W<'a, O> { + #[doc = "Connect the newer SD host"] + #[inline(always)] + pub fn sdhost(self) -> &'a mut W { + self.variant(SDIO_A::SDHOST) + } + #[doc = "Connect Arasan SD/EMMC host"] + #[inline(always)] + pub fn arasan(self) -> &'a mut W { + self.variant(SDIO_A::ARASAN) + } +} +impl R { + #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] + #[inline(always)] + pub fn sdio(&self) -> SDIO_R { + SDIO_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] + #[inline(always)] + #[must_use] + pub fn sdio(&mut self) -> SDIO_W<1> { + SDIO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Undocumented multiplexing bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extra_mux](index.html) module"] +pub struct EXTRA_MUX_SPEC; +impl crate::RegisterSpec for EXTRA_MUX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [extra_mux::R](R) reader structure"] +impl crate::Readable for EXTRA_MUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [extra_mux::W](W) writer structure"] +impl crate::Writable for EXTRA_MUX_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpafen0.rs b/crates/bcm2837-lpa/src/gpio/gpafen0.rs new file mode 100644 index 0000000..5c84fd8 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpafen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPAFEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAFEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AFEN0` reader - Async falling enabled 0"] +pub type AFEN0_R = crate::BitReader; +#[doc = "Field `AFEN0` writer - Async falling enabled 0"] +pub type AFEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN1` reader - Async falling enabled 1"] +pub type AFEN1_R = crate::BitReader; +#[doc = "Field `AFEN1` writer - Async falling enabled 1"] +pub type AFEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN2` reader - Async falling enabled 2"] +pub type AFEN2_R = crate::BitReader; +#[doc = "Field `AFEN2` writer - Async falling enabled 2"] +pub type AFEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN3` reader - Async falling enabled 3"] +pub type AFEN3_R = crate::BitReader; +#[doc = "Field `AFEN3` writer - Async falling enabled 3"] +pub type AFEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN4` reader - Async falling enabled 4"] +pub type AFEN4_R = crate::BitReader; +#[doc = "Field `AFEN4` writer - Async falling enabled 4"] +pub type AFEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN5` reader - Async falling enabled 5"] +pub type AFEN5_R = crate::BitReader; +#[doc = "Field `AFEN5` writer - Async falling enabled 5"] +pub type AFEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN6` reader - Async falling enabled 6"] +pub type AFEN6_R = crate::BitReader; +#[doc = "Field `AFEN6` writer - Async falling enabled 6"] +pub type AFEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN7` reader - Async falling enabled 7"] +pub type AFEN7_R = crate::BitReader; +#[doc = "Field `AFEN7` writer - Async falling enabled 7"] +pub type AFEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN8` reader - Async falling enabled 8"] +pub type AFEN8_R = crate::BitReader; +#[doc = "Field `AFEN8` writer - Async falling enabled 8"] +pub type AFEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN9` reader - Async falling enabled 9"] +pub type AFEN9_R = crate::BitReader; +#[doc = "Field `AFEN9` writer - Async falling enabled 9"] +pub type AFEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN10` reader - Async falling enabled 10"] +pub type AFEN10_R = crate::BitReader; +#[doc = "Field `AFEN10` writer - Async falling enabled 10"] +pub type AFEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN11` reader - Async falling enabled 11"] +pub type AFEN11_R = crate::BitReader; +#[doc = "Field `AFEN11` writer - Async falling enabled 11"] +pub type AFEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN12` reader - Async falling enabled 12"] +pub type AFEN12_R = crate::BitReader; +#[doc = "Field `AFEN12` writer - Async falling enabled 12"] +pub type AFEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN13` reader - Async falling enabled 13"] +pub type AFEN13_R = crate::BitReader; +#[doc = "Field `AFEN13` writer - Async falling enabled 13"] +pub type AFEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN14` reader - Async falling enabled 14"] +pub type AFEN14_R = crate::BitReader; +#[doc = "Field `AFEN14` writer - Async falling enabled 14"] +pub type AFEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN15` reader - Async falling enabled 15"] +pub type AFEN15_R = crate::BitReader; +#[doc = "Field `AFEN15` writer - Async falling enabled 15"] +pub type AFEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN16` reader - Async falling enabled 16"] +pub type AFEN16_R = crate::BitReader; +#[doc = "Field `AFEN16` writer - Async falling enabled 16"] +pub type AFEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN17` reader - Async falling enabled 17"] +pub type AFEN17_R = crate::BitReader; +#[doc = "Field `AFEN17` writer - Async falling enabled 17"] +pub type AFEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN18` reader - Async falling enabled 18"] +pub type AFEN18_R = crate::BitReader; +#[doc = "Field `AFEN18` writer - Async falling enabled 18"] +pub type AFEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN19` reader - Async falling enabled 19"] +pub type AFEN19_R = crate::BitReader; +#[doc = "Field `AFEN19` writer - Async falling enabled 19"] +pub type AFEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN20` reader - Async falling enabled 20"] +pub type AFEN20_R = crate::BitReader; +#[doc = "Field `AFEN20` writer - Async falling enabled 20"] +pub type AFEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN21` reader - Async falling enabled 21"] +pub type AFEN21_R = crate::BitReader; +#[doc = "Field `AFEN21` writer - Async falling enabled 21"] +pub type AFEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN22` reader - Async falling enabled 22"] +pub type AFEN22_R = crate::BitReader; +#[doc = "Field `AFEN22` writer - Async falling enabled 22"] +pub type AFEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN23` reader - Async falling enabled 23"] +pub type AFEN23_R = crate::BitReader; +#[doc = "Field `AFEN23` writer - Async falling enabled 23"] +pub type AFEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN24` reader - Async falling enabled 24"] +pub type AFEN24_R = crate::BitReader; +#[doc = "Field `AFEN24` writer - Async falling enabled 24"] +pub type AFEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN25` reader - Async falling enabled 25"] +pub type AFEN25_R = crate::BitReader; +#[doc = "Field `AFEN25` writer - Async falling enabled 25"] +pub type AFEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN26` reader - Async falling enabled 26"] +pub type AFEN26_R = crate::BitReader; +#[doc = "Field `AFEN26` writer - Async falling enabled 26"] +pub type AFEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN27` reader - Async falling enabled 27"] +pub type AFEN27_R = crate::BitReader; +#[doc = "Field `AFEN27` writer - Async falling enabled 27"] +pub type AFEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN28` reader - Async falling enabled 28"] +pub type AFEN28_R = crate::BitReader; +#[doc = "Field `AFEN28` writer - Async falling enabled 28"] +pub type AFEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN29` reader - Async falling enabled 29"] +pub type AFEN29_R = crate::BitReader; +#[doc = "Field `AFEN29` writer - Async falling enabled 29"] +pub type AFEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN30` reader - Async falling enabled 30"] +pub type AFEN30_R = crate::BitReader; +#[doc = "Field `AFEN30` writer - Async falling enabled 30"] +pub type AFEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +#[doc = "Field `AFEN31` reader - Async falling enabled 31"] +pub type AFEN31_R = crate::BitReader; +#[doc = "Field `AFEN31` writer - Async falling enabled 31"] +pub type AFEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async falling enabled 0"] + #[inline(always)] + pub fn afen0(&self) -> AFEN0_R { + AFEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async falling enabled 1"] + #[inline(always)] + pub fn afen1(&self) -> AFEN1_R { + AFEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async falling enabled 2"] + #[inline(always)] + pub fn afen2(&self) -> AFEN2_R { + AFEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async falling enabled 3"] + #[inline(always)] + pub fn afen3(&self) -> AFEN3_R { + AFEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async falling enabled 4"] + #[inline(always)] + pub fn afen4(&self) -> AFEN4_R { + AFEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async falling enabled 5"] + #[inline(always)] + pub fn afen5(&self) -> AFEN5_R { + AFEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async falling enabled 6"] + #[inline(always)] + pub fn afen6(&self) -> AFEN6_R { + AFEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async falling enabled 7"] + #[inline(always)] + pub fn afen7(&self) -> AFEN7_R { + AFEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async falling enabled 8"] + #[inline(always)] + pub fn afen8(&self) -> AFEN8_R { + AFEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async falling enabled 9"] + #[inline(always)] + pub fn afen9(&self) -> AFEN9_R { + AFEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async falling enabled 10"] + #[inline(always)] + pub fn afen10(&self) -> AFEN10_R { + AFEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async falling enabled 11"] + #[inline(always)] + pub fn afen11(&self) -> AFEN11_R { + AFEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async falling enabled 12"] + #[inline(always)] + pub fn afen12(&self) -> AFEN12_R { + AFEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async falling enabled 13"] + #[inline(always)] + pub fn afen13(&self) -> AFEN13_R { + AFEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async falling enabled 14"] + #[inline(always)] + pub fn afen14(&self) -> AFEN14_R { + AFEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async falling enabled 15"] + #[inline(always)] + pub fn afen15(&self) -> AFEN15_R { + AFEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async falling enabled 16"] + #[inline(always)] + pub fn afen16(&self) -> AFEN16_R { + AFEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async falling enabled 17"] + #[inline(always)] + pub fn afen17(&self) -> AFEN17_R { + AFEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async falling enabled 18"] + #[inline(always)] + pub fn afen18(&self) -> AFEN18_R { + AFEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async falling enabled 19"] + #[inline(always)] + pub fn afen19(&self) -> AFEN19_R { + AFEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async falling enabled 20"] + #[inline(always)] + pub fn afen20(&self) -> AFEN20_R { + AFEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async falling enabled 21"] + #[inline(always)] + pub fn afen21(&self) -> AFEN21_R { + AFEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async falling enabled 22"] + #[inline(always)] + pub fn afen22(&self) -> AFEN22_R { + AFEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async falling enabled 23"] + #[inline(always)] + pub fn afen23(&self) -> AFEN23_R { + AFEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async falling enabled 24"] + #[inline(always)] + pub fn afen24(&self) -> AFEN24_R { + AFEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async falling enabled 25"] + #[inline(always)] + pub fn afen25(&self) -> AFEN25_R { + AFEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Async falling enabled 26"] + #[inline(always)] + pub fn afen26(&self) -> AFEN26_R { + AFEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Async falling enabled 27"] + #[inline(always)] + pub fn afen27(&self) -> AFEN27_R { + AFEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Async falling enabled 28"] + #[inline(always)] + pub fn afen28(&self) -> AFEN28_R { + AFEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Async falling enabled 29"] + #[inline(always)] + pub fn afen29(&self) -> AFEN29_R { + AFEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Async falling enabled 30"] + #[inline(always)] + pub fn afen30(&self) -> AFEN30_R { + AFEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Async falling enabled 31"] + #[inline(always)] + pub fn afen31(&self) -> AFEN31_R { + AFEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async falling enabled 0"] + #[inline(always)] + #[must_use] + pub fn afen0(&mut self) -> AFEN0_W<0> { + AFEN0_W::new(self) + } + #[doc = "Bit 1 - Async falling enabled 1"] + #[inline(always)] + #[must_use] + pub fn afen1(&mut self) -> AFEN1_W<1> { + AFEN1_W::new(self) + } + #[doc = "Bit 2 - Async falling enabled 2"] + #[inline(always)] + #[must_use] + pub fn afen2(&mut self) -> AFEN2_W<2> { + AFEN2_W::new(self) + } + #[doc = "Bit 3 - Async falling enabled 3"] + #[inline(always)] + #[must_use] + pub fn afen3(&mut self) -> AFEN3_W<3> { + AFEN3_W::new(self) + } + #[doc = "Bit 4 - Async falling enabled 4"] + #[inline(always)] + #[must_use] + pub fn afen4(&mut self) -> AFEN4_W<4> { + AFEN4_W::new(self) + } + #[doc = "Bit 5 - Async falling enabled 5"] + #[inline(always)] + #[must_use] + pub fn afen5(&mut self) -> AFEN5_W<5> { + AFEN5_W::new(self) + } + #[doc = "Bit 6 - Async falling enabled 6"] + #[inline(always)] + #[must_use] + pub fn afen6(&mut self) -> AFEN6_W<6> { + AFEN6_W::new(self) + } + #[doc = "Bit 7 - Async falling enabled 7"] + #[inline(always)] + #[must_use] + pub fn afen7(&mut self) -> AFEN7_W<7> { + AFEN7_W::new(self) + } + #[doc = "Bit 8 - Async falling enabled 8"] + #[inline(always)] + #[must_use] + pub fn afen8(&mut self) -> AFEN8_W<8> { + AFEN8_W::new(self) + } + #[doc = "Bit 9 - Async falling enabled 9"] + #[inline(always)] + #[must_use] + pub fn afen9(&mut self) -> AFEN9_W<9> { + AFEN9_W::new(self) + } + #[doc = "Bit 10 - Async falling enabled 10"] + #[inline(always)] + #[must_use] + pub fn afen10(&mut self) -> AFEN10_W<10> { + AFEN10_W::new(self) + } + #[doc = "Bit 11 - Async falling enabled 11"] + #[inline(always)] + #[must_use] + pub fn afen11(&mut self) -> AFEN11_W<11> { + AFEN11_W::new(self) + } + #[doc = "Bit 12 - Async falling enabled 12"] + #[inline(always)] + #[must_use] + pub fn afen12(&mut self) -> AFEN12_W<12> { + AFEN12_W::new(self) + } + #[doc = "Bit 13 - Async falling enabled 13"] + #[inline(always)] + #[must_use] + pub fn afen13(&mut self) -> AFEN13_W<13> { + AFEN13_W::new(self) + } + #[doc = "Bit 14 - Async falling enabled 14"] + #[inline(always)] + #[must_use] + pub fn afen14(&mut self) -> AFEN14_W<14> { + AFEN14_W::new(self) + } + #[doc = "Bit 15 - Async falling enabled 15"] + #[inline(always)] + #[must_use] + pub fn afen15(&mut self) -> AFEN15_W<15> { + AFEN15_W::new(self) + } + #[doc = "Bit 16 - Async falling enabled 16"] + #[inline(always)] + #[must_use] + pub fn afen16(&mut self) -> AFEN16_W<16> { + AFEN16_W::new(self) + } + #[doc = "Bit 17 - Async falling enabled 17"] + #[inline(always)] + #[must_use] + pub fn afen17(&mut self) -> AFEN17_W<17> { + AFEN17_W::new(self) + } + #[doc = "Bit 18 - Async falling enabled 18"] + #[inline(always)] + #[must_use] + pub fn afen18(&mut self) -> AFEN18_W<18> { + AFEN18_W::new(self) + } + #[doc = "Bit 19 - Async falling enabled 19"] + #[inline(always)] + #[must_use] + pub fn afen19(&mut self) -> AFEN19_W<19> { + AFEN19_W::new(self) + } + #[doc = "Bit 20 - Async falling enabled 20"] + #[inline(always)] + #[must_use] + pub fn afen20(&mut self) -> AFEN20_W<20> { + AFEN20_W::new(self) + } + #[doc = "Bit 21 - Async falling enabled 21"] + #[inline(always)] + #[must_use] + pub fn afen21(&mut self) -> AFEN21_W<21> { + AFEN21_W::new(self) + } + #[doc = "Bit 22 - Async falling enabled 22"] + #[inline(always)] + #[must_use] + pub fn afen22(&mut self) -> AFEN22_W<22> { + AFEN22_W::new(self) + } + #[doc = "Bit 23 - Async falling enabled 23"] + #[inline(always)] + #[must_use] + pub fn afen23(&mut self) -> AFEN23_W<23> { + AFEN23_W::new(self) + } + #[doc = "Bit 24 - Async falling enabled 24"] + #[inline(always)] + #[must_use] + pub fn afen24(&mut self) -> AFEN24_W<24> { + AFEN24_W::new(self) + } + #[doc = "Bit 25 - Async falling enabled 25"] + #[inline(always)] + #[must_use] + pub fn afen25(&mut self) -> AFEN25_W<25> { + AFEN25_W::new(self) + } + #[doc = "Bit 26 - Async falling enabled 26"] + #[inline(always)] + #[must_use] + pub fn afen26(&mut self) -> AFEN26_W<26> { + AFEN26_W::new(self) + } + #[doc = "Bit 27 - Async falling enabled 27"] + #[inline(always)] + #[must_use] + pub fn afen27(&mut self) -> AFEN27_W<27> { + AFEN27_W::new(self) + } + #[doc = "Bit 28 - Async falling enabled 28"] + #[inline(always)] + #[must_use] + pub fn afen28(&mut self) -> AFEN28_W<28> { + AFEN28_W::new(self) + } + #[doc = "Bit 29 - Async falling enabled 29"] + #[inline(always)] + #[must_use] + pub fn afen29(&mut self) -> AFEN29_W<29> { + AFEN29_W::new(self) + } + #[doc = "Bit 30 - Async falling enabled 30"] + #[inline(always)] + #[must_use] + pub fn afen30(&mut self) -> AFEN30_W<30> { + AFEN30_W::new(self) + } + #[doc = "Bit 31 - Async falling enabled 31"] + #[inline(always)] + #[must_use] + pub fn afen31(&mut self) -> AFEN31_W<31> { + AFEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen0](index.html) module"] +pub struct GPAFEN0_SPEC; +impl crate::RegisterSpec for GPAFEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpafen0::R](R) reader structure"] +impl crate::Readable for GPAFEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpafen0::W](W) writer structure"] +impl crate::Writable for GPAFEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpafen1.rs b/crates/bcm2837-lpa/src/gpio/gpafen1.rs new file mode 100644 index 0000000..a87edeb --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpafen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPAFEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAFEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AFEN32` reader - Async falling enabled 32"] +pub type AFEN32_R = crate::BitReader; +#[doc = "Field `AFEN32` writer - Async falling enabled 32"] +pub type AFEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN33` reader - Async falling enabled 33"] +pub type AFEN33_R = crate::BitReader; +#[doc = "Field `AFEN33` writer - Async falling enabled 33"] +pub type AFEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN34` reader - Async falling enabled 34"] +pub type AFEN34_R = crate::BitReader; +#[doc = "Field `AFEN34` writer - Async falling enabled 34"] +pub type AFEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN35` reader - Async falling enabled 35"] +pub type AFEN35_R = crate::BitReader; +#[doc = "Field `AFEN35` writer - Async falling enabled 35"] +pub type AFEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN36` reader - Async falling enabled 36"] +pub type AFEN36_R = crate::BitReader; +#[doc = "Field `AFEN36` writer - Async falling enabled 36"] +pub type AFEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN37` reader - Async falling enabled 37"] +pub type AFEN37_R = crate::BitReader; +#[doc = "Field `AFEN37` writer - Async falling enabled 37"] +pub type AFEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN38` reader - Async falling enabled 38"] +pub type AFEN38_R = crate::BitReader; +#[doc = "Field `AFEN38` writer - Async falling enabled 38"] +pub type AFEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN39` reader - Async falling enabled 39"] +pub type AFEN39_R = crate::BitReader; +#[doc = "Field `AFEN39` writer - Async falling enabled 39"] +pub type AFEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN40` reader - Async falling enabled 40"] +pub type AFEN40_R = crate::BitReader; +#[doc = "Field `AFEN40` writer - Async falling enabled 40"] +pub type AFEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN41` reader - Async falling enabled 41"] +pub type AFEN41_R = crate::BitReader; +#[doc = "Field `AFEN41` writer - Async falling enabled 41"] +pub type AFEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN42` reader - Async falling enabled 42"] +pub type AFEN42_R = crate::BitReader; +#[doc = "Field `AFEN42` writer - Async falling enabled 42"] +pub type AFEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN43` reader - Async falling enabled 43"] +pub type AFEN43_R = crate::BitReader; +#[doc = "Field `AFEN43` writer - Async falling enabled 43"] +pub type AFEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN44` reader - Async falling enabled 44"] +pub type AFEN44_R = crate::BitReader; +#[doc = "Field `AFEN44` writer - Async falling enabled 44"] +pub type AFEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN45` reader - Async falling enabled 45"] +pub type AFEN45_R = crate::BitReader; +#[doc = "Field `AFEN45` writer - Async falling enabled 45"] +pub type AFEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN46` reader - Async falling enabled 46"] +pub type AFEN46_R = crate::BitReader; +#[doc = "Field `AFEN46` writer - Async falling enabled 46"] +pub type AFEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN47` reader - Async falling enabled 47"] +pub type AFEN47_R = crate::BitReader; +#[doc = "Field `AFEN47` writer - Async falling enabled 47"] +pub type AFEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN48` reader - Async falling enabled 48"] +pub type AFEN48_R = crate::BitReader; +#[doc = "Field `AFEN48` writer - Async falling enabled 48"] +pub type AFEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN49` reader - Async falling enabled 49"] +pub type AFEN49_R = crate::BitReader; +#[doc = "Field `AFEN49` writer - Async falling enabled 49"] +pub type AFEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN50` reader - Async falling enabled 50"] +pub type AFEN50_R = crate::BitReader; +#[doc = "Field `AFEN50` writer - Async falling enabled 50"] +pub type AFEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN51` reader - Async falling enabled 51"] +pub type AFEN51_R = crate::BitReader; +#[doc = "Field `AFEN51` writer - Async falling enabled 51"] +pub type AFEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN52` reader - Async falling enabled 52"] +pub type AFEN52_R = crate::BitReader; +#[doc = "Field `AFEN52` writer - Async falling enabled 52"] +pub type AFEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +#[doc = "Field `AFEN53` reader - Async falling enabled 53"] +pub type AFEN53_R = crate::BitReader; +#[doc = "Field `AFEN53` writer - Async falling enabled 53"] +pub type AFEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async falling enabled 32"] + #[inline(always)] + pub fn afen32(&self) -> AFEN32_R { + AFEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async falling enabled 33"] + #[inline(always)] + pub fn afen33(&self) -> AFEN33_R { + AFEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async falling enabled 34"] + #[inline(always)] + pub fn afen34(&self) -> AFEN34_R { + AFEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async falling enabled 35"] + #[inline(always)] + pub fn afen35(&self) -> AFEN35_R { + AFEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async falling enabled 36"] + #[inline(always)] + pub fn afen36(&self) -> AFEN36_R { + AFEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async falling enabled 37"] + #[inline(always)] + pub fn afen37(&self) -> AFEN37_R { + AFEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async falling enabled 38"] + #[inline(always)] + pub fn afen38(&self) -> AFEN38_R { + AFEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async falling enabled 39"] + #[inline(always)] + pub fn afen39(&self) -> AFEN39_R { + AFEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async falling enabled 40"] + #[inline(always)] + pub fn afen40(&self) -> AFEN40_R { + AFEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async falling enabled 41"] + #[inline(always)] + pub fn afen41(&self) -> AFEN41_R { + AFEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async falling enabled 42"] + #[inline(always)] + pub fn afen42(&self) -> AFEN42_R { + AFEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async falling enabled 43"] + #[inline(always)] + pub fn afen43(&self) -> AFEN43_R { + AFEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async falling enabled 44"] + #[inline(always)] + pub fn afen44(&self) -> AFEN44_R { + AFEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async falling enabled 45"] + #[inline(always)] + pub fn afen45(&self) -> AFEN45_R { + AFEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async falling enabled 46"] + #[inline(always)] + pub fn afen46(&self) -> AFEN46_R { + AFEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async falling enabled 47"] + #[inline(always)] + pub fn afen47(&self) -> AFEN47_R { + AFEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async falling enabled 48"] + #[inline(always)] + pub fn afen48(&self) -> AFEN48_R { + AFEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async falling enabled 49"] + #[inline(always)] + pub fn afen49(&self) -> AFEN49_R { + AFEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async falling enabled 50"] + #[inline(always)] + pub fn afen50(&self) -> AFEN50_R { + AFEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async falling enabled 51"] + #[inline(always)] + pub fn afen51(&self) -> AFEN51_R { + AFEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async falling enabled 52"] + #[inline(always)] + pub fn afen52(&self) -> AFEN52_R { + AFEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async falling enabled 53"] + #[inline(always)] + pub fn afen53(&self) -> AFEN53_R { + AFEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async falling enabled 32"] + #[inline(always)] + #[must_use] + pub fn afen32(&mut self) -> AFEN32_W<0> { + AFEN32_W::new(self) + } + #[doc = "Bit 1 - Async falling enabled 33"] + #[inline(always)] + #[must_use] + pub fn afen33(&mut self) -> AFEN33_W<1> { + AFEN33_W::new(self) + } + #[doc = "Bit 2 - Async falling enabled 34"] + #[inline(always)] + #[must_use] + pub fn afen34(&mut self) -> AFEN34_W<2> { + AFEN34_W::new(self) + } + #[doc = "Bit 3 - Async falling enabled 35"] + #[inline(always)] + #[must_use] + pub fn afen35(&mut self) -> AFEN35_W<3> { + AFEN35_W::new(self) + } + #[doc = "Bit 4 - Async falling enabled 36"] + #[inline(always)] + #[must_use] + pub fn afen36(&mut self) -> AFEN36_W<4> { + AFEN36_W::new(self) + } + #[doc = "Bit 5 - Async falling enabled 37"] + #[inline(always)] + #[must_use] + pub fn afen37(&mut self) -> AFEN37_W<5> { + AFEN37_W::new(self) + } + #[doc = "Bit 6 - Async falling enabled 38"] + #[inline(always)] + #[must_use] + pub fn afen38(&mut self) -> AFEN38_W<6> { + AFEN38_W::new(self) + } + #[doc = "Bit 7 - Async falling enabled 39"] + #[inline(always)] + #[must_use] + pub fn afen39(&mut self) -> AFEN39_W<7> { + AFEN39_W::new(self) + } + #[doc = "Bit 8 - Async falling enabled 40"] + #[inline(always)] + #[must_use] + pub fn afen40(&mut self) -> AFEN40_W<8> { + AFEN40_W::new(self) + } + #[doc = "Bit 9 - Async falling enabled 41"] + #[inline(always)] + #[must_use] + pub fn afen41(&mut self) -> AFEN41_W<9> { + AFEN41_W::new(self) + } + #[doc = "Bit 10 - Async falling enabled 42"] + #[inline(always)] + #[must_use] + pub fn afen42(&mut self) -> AFEN42_W<10> { + AFEN42_W::new(self) + } + #[doc = "Bit 11 - Async falling enabled 43"] + #[inline(always)] + #[must_use] + pub fn afen43(&mut self) -> AFEN43_W<11> { + AFEN43_W::new(self) + } + #[doc = "Bit 12 - Async falling enabled 44"] + #[inline(always)] + #[must_use] + pub fn afen44(&mut self) -> AFEN44_W<12> { + AFEN44_W::new(self) + } + #[doc = "Bit 13 - Async falling enabled 45"] + #[inline(always)] + #[must_use] + pub fn afen45(&mut self) -> AFEN45_W<13> { + AFEN45_W::new(self) + } + #[doc = "Bit 14 - Async falling enabled 46"] + #[inline(always)] + #[must_use] + pub fn afen46(&mut self) -> AFEN46_W<14> { + AFEN46_W::new(self) + } + #[doc = "Bit 15 - Async falling enabled 47"] + #[inline(always)] + #[must_use] + pub fn afen47(&mut self) -> AFEN47_W<15> { + AFEN47_W::new(self) + } + #[doc = "Bit 16 - Async falling enabled 48"] + #[inline(always)] + #[must_use] + pub fn afen48(&mut self) -> AFEN48_W<16> { + AFEN48_W::new(self) + } + #[doc = "Bit 17 - Async falling enabled 49"] + #[inline(always)] + #[must_use] + pub fn afen49(&mut self) -> AFEN49_W<17> { + AFEN49_W::new(self) + } + #[doc = "Bit 18 - Async falling enabled 50"] + #[inline(always)] + #[must_use] + pub fn afen50(&mut self) -> AFEN50_W<18> { + AFEN50_W::new(self) + } + #[doc = "Bit 19 - Async falling enabled 51"] + #[inline(always)] + #[must_use] + pub fn afen51(&mut self) -> AFEN51_W<19> { + AFEN51_W::new(self) + } + #[doc = "Bit 20 - Async falling enabled 52"] + #[inline(always)] + #[must_use] + pub fn afen52(&mut self) -> AFEN52_W<20> { + AFEN52_W::new(self) + } + #[doc = "Bit 21 - Async falling enabled 53"] + #[inline(always)] + #[must_use] + pub fn afen53(&mut self) -> AFEN53_W<21> { + AFEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen1](index.html) module"] +pub struct GPAFEN1_SPEC; +impl crate::RegisterSpec for GPAFEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpafen1::R](R) reader structure"] +impl crate::Readable for GPAFEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpafen1::W](W) writer structure"] +impl crate::Writable for GPAFEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gparen0.rs b/crates/bcm2837-lpa/src/gpio/gparen0.rs new file mode 100644 index 0000000..f4ef746 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gparen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPAREN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAREN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AREN0` reader - Async rising enabled 0"] +pub type AREN0_R = crate::BitReader; +#[doc = "Field `AREN0` writer - Async rising enabled 0"] +pub type AREN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN1` reader - Async rising enabled 1"] +pub type AREN1_R = crate::BitReader; +#[doc = "Field `AREN1` writer - Async rising enabled 1"] +pub type AREN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN2` reader - Async rising enabled 2"] +pub type AREN2_R = crate::BitReader; +#[doc = "Field `AREN2` writer - Async rising enabled 2"] +pub type AREN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN3` reader - Async rising enabled 3"] +pub type AREN3_R = crate::BitReader; +#[doc = "Field `AREN3` writer - Async rising enabled 3"] +pub type AREN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN4` reader - Async rising enabled 4"] +pub type AREN4_R = crate::BitReader; +#[doc = "Field `AREN4` writer - Async rising enabled 4"] +pub type AREN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN5` reader - Async rising enabled 5"] +pub type AREN5_R = crate::BitReader; +#[doc = "Field `AREN5` writer - Async rising enabled 5"] +pub type AREN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN6` reader - Async rising enabled 6"] +pub type AREN6_R = crate::BitReader; +#[doc = "Field `AREN6` writer - Async rising enabled 6"] +pub type AREN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN7` reader - Async rising enabled 7"] +pub type AREN7_R = crate::BitReader; +#[doc = "Field `AREN7` writer - Async rising enabled 7"] +pub type AREN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN8` reader - Async rising enabled 8"] +pub type AREN8_R = crate::BitReader; +#[doc = "Field `AREN8` writer - Async rising enabled 8"] +pub type AREN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN9` reader - Async rising enabled 9"] +pub type AREN9_R = crate::BitReader; +#[doc = "Field `AREN9` writer - Async rising enabled 9"] +pub type AREN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN10` reader - Async rising enabled 10"] +pub type AREN10_R = crate::BitReader; +#[doc = "Field `AREN10` writer - Async rising enabled 10"] +pub type AREN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN11` reader - Async rising enabled 11"] +pub type AREN11_R = crate::BitReader; +#[doc = "Field `AREN11` writer - Async rising enabled 11"] +pub type AREN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN12` reader - Async rising enabled 12"] +pub type AREN12_R = crate::BitReader; +#[doc = "Field `AREN12` writer - Async rising enabled 12"] +pub type AREN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN13` reader - Async rising enabled 13"] +pub type AREN13_R = crate::BitReader; +#[doc = "Field `AREN13` writer - Async rising enabled 13"] +pub type AREN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN14` reader - Async rising enabled 14"] +pub type AREN14_R = crate::BitReader; +#[doc = "Field `AREN14` writer - Async rising enabled 14"] +pub type AREN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN15` reader - Async rising enabled 15"] +pub type AREN15_R = crate::BitReader; +#[doc = "Field `AREN15` writer - Async rising enabled 15"] +pub type AREN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN16` reader - Async rising enabled 16"] +pub type AREN16_R = crate::BitReader; +#[doc = "Field `AREN16` writer - Async rising enabled 16"] +pub type AREN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN17` reader - Async rising enabled 17"] +pub type AREN17_R = crate::BitReader; +#[doc = "Field `AREN17` writer - Async rising enabled 17"] +pub type AREN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN18` reader - Async rising enabled 18"] +pub type AREN18_R = crate::BitReader; +#[doc = "Field `AREN18` writer - Async rising enabled 18"] +pub type AREN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN19` reader - Async rising enabled 19"] +pub type AREN19_R = crate::BitReader; +#[doc = "Field `AREN19` writer - Async rising enabled 19"] +pub type AREN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN20` reader - Async rising enabled 20"] +pub type AREN20_R = crate::BitReader; +#[doc = "Field `AREN20` writer - Async rising enabled 20"] +pub type AREN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN21` reader - Async rising enabled 21"] +pub type AREN21_R = crate::BitReader; +#[doc = "Field `AREN21` writer - Async rising enabled 21"] +pub type AREN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN22` reader - Async rising enabled 22"] +pub type AREN22_R = crate::BitReader; +#[doc = "Field `AREN22` writer - Async rising enabled 22"] +pub type AREN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN23` reader - Async rising enabled 23"] +pub type AREN23_R = crate::BitReader; +#[doc = "Field `AREN23` writer - Async rising enabled 23"] +pub type AREN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN24` reader - Async rising enabled 24"] +pub type AREN24_R = crate::BitReader; +#[doc = "Field `AREN24` writer - Async rising enabled 24"] +pub type AREN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN25` reader - Async rising enabled 25"] +pub type AREN25_R = crate::BitReader; +#[doc = "Field `AREN25` writer - Async rising enabled 25"] +pub type AREN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN26` reader - Async rising enabled 26"] +pub type AREN26_R = crate::BitReader; +#[doc = "Field `AREN26` writer - Async rising enabled 26"] +pub type AREN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN27` reader - Async rising enabled 27"] +pub type AREN27_R = crate::BitReader; +#[doc = "Field `AREN27` writer - Async rising enabled 27"] +pub type AREN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN28` reader - Async rising enabled 28"] +pub type AREN28_R = crate::BitReader; +#[doc = "Field `AREN28` writer - Async rising enabled 28"] +pub type AREN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN29` reader - Async rising enabled 29"] +pub type AREN29_R = crate::BitReader; +#[doc = "Field `AREN29` writer - Async rising enabled 29"] +pub type AREN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN30` reader - Async rising enabled 30"] +pub type AREN30_R = crate::BitReader; +#[doc = "Field `AREN30` writer - Async rising enabled 30"] +pub type AREN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +#[doc = "Field `AREN31` reader - Async rising enabled 31"] +pub type AREN31_R = crate::BitReader; +#[doc = "Field `AREN31` writer - Async rising enabled 31"] +pub type AREN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async rising enabled 0"] + #[inline(always)] + pub fn aren0(&self) -> AREN0_R { + AREN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async rising enabled 1"] + #[inline(always)] + pub fn aren1(&self) -> AREN1_R { + AREN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async rising enabled 2"] + #[inline(always)] + pub fn aren2(&self) -> AREN2_R { + AREN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async rising enabled 3"] + #[inline(always)] + pub fn aren3(&self) -> AREN3_R { + AREN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async rising enabled 4"] + #[inline(always)] + pub fn aren4(&self) -> AREN4_R { + AREN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async rising enabled 5"] + #[inline(always)] + pub fn aren5(&self) -> AREN5_R { + AREN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async rising enabled 6"] + #[inline(always)] + pub fn aren6(&self) -> AREN6_R { + AREN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async rising enabled 7"] + #[inline(always)] + pub fn aren7(&self) -> AREN7_R { + AREN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async rising enabled 8"] + #[inline(always)] + pub fn aren8(&self) -> AREN8_R { + AREN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async rising enabled 9"] + #[inline(always)] + pub fn aren9(&self) -> AREN9_R { + AREN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async rising enabled 10"] + #[inline(always)] + pub fn aren10(&self) -> AREN10_R { + AREN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async rising enabled 11"] + #[inline(always)] + pub fn aren11(&self) -> AREN11_R { + AREN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async rising enabled 12"] + #[inline(always)] + pub fn aren12(&self) -> AREN12_R { + AREN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async rising enabled 13"] + #[inline(always)] + pub fn aren13(&self) -> AREN13_R { + AREN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async rising enabled 14"] + #[inline(always)] + pub fn aren14(&self) -> AREN14_R { + AREN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async rising enabled 15"] + #[inline(always)] + pub fn aren15(&self) -> AREN15_R { + AREN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async rising enabled 16"] + #[inline(always)] + pub fn aren16(&self) -> AREN16_R { + AREN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async rising enabled 17"] + #[inline(always)] + pub fn aren17(&self) -> AREN17_R { + AREN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async rising enabled 18"] + #[inline(always)] + pub fn aren18(&self) -> AREN18_R { + AREN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async rising enabled 19"] + #[inline(always)] + pub fn aren19(&self) -> AREN19_R { + AREN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async rising enabled 20"] + #[inline(always)] + pub fn aren20(&self) -> AREN20_R { + AREN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async rising enabled 21"] + #[inline(always)] + pub fn aren21(&self) -> AREN21_R { + AREN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Async rising enabled 22"] + #[inline(always)] + pub fn aren22(&self) -> AREN22_R { + AREN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Async rising enabled 23"] + #[inline(always)] + pub fn aren23(&self) -> AREN23_R { + AREN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Async rising enabled 24"] + #[inline(always)] + pub fn aren24(&self) -> AREN24_R { + AREN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Async rising enabled 25"] + #[inline(always)] + pub fn aren25(&self) -> AREN25_R { + AREN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Async rising enabled 26"] + #[inline(always)] + pub fn aren26(&self) -> AREN26_R { + AREN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Async rising enabled 27"] + #[inline(always)] + pub fn aren27(&self) -> AREN27_R { + AREN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Async rising enabled 28"] + #[inline(always)] + pub fn aren28(&self) -> AREN28_R { + AREN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Async rising enabled 29"] + #[inline(always)] + pub fn aren29(&self) -> AREN29_R { + AREN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Async rising enabled 30"] + #[inline(always)] + pub fn aren30(&self) -> AREN30_R { + AREN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Async rising enabled 31"] + #[inline(always)] + pub fn aren31(&self) -> AREN31_R { + AREN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async rising enabled 0"] + #[inline(always)] + #[must_use] + pub fn aren0(&mut self) -> AREN0_W<0> { + AREN0_W::new(self) + } + #[doc = "Bit 1 - Async rising enabled 1"] + #[inline(always)] + #[must_use] + pub fn aren1(&mut self) -> AREN1_W<1> { + AREN1_W::new(self) + } + #[doc = "Bit 2 - Async rising enabled 2"] + #[inline(always)] + #[must_use] + pub fn aren2(&mut self) -> AREN2_W<2> { + AREN2_W::new(self) + } + #[doc = "Bit 3 - Async rising enabled 3"] + #[inline(always)] + #[must_use] + pub fn aren3(&mut self) -> AREN3_W<3> { + AREN3_W::new(self) + } + #[doc = "Bit 4 - Async rising enabled 4"] + #[inline(always)] + #[must_use] + pub fn aren4(&mut self) -> AREN4_W<4> { + AREN4_W::new(self) + } + #[doc = "Bit 5 - Async rising enabled 5"] + #[inline(always)] + #[must_use] + pub fn aren5(&mut self) -> AREN5_W<5> { + AREN5_W::new(self) + } + #[doc = "Bit 6 - Async rising enabled 6"] + #[inline(always)] + #[must_use] + pub fn aren6(&mut self) -> AREN6_W<6> { + AREN6_W::new(self) + } + #[doc = "Bit 7 - Async rising enabled 7"] + #[inline(always)] + #[must_use] + pub fn aren7(&mut self) -> AREN7_W<7> { + AREN7_W::new(self) + } + #[doc = "Bit 8 - Async rising enabled 8"] + #[inline(always)] + #[must_use] + pub fn aren8(&mut self) -> AREN8_W<8> { + AREN8_W::new(self) + } + #[doc = "Bit 9 - Async rising enabled 9"] + #[inline(always)] + #[must_use] + pub fn aren9(&mut self) -> AREN9_W<9> { + AREN9_W::new(self) + } + #[doc = "Bit 10 - Async rising enabled 10"] + #[inline(always)] + #[must_use] + pub fn aren10(&mut self) -> AREN10_W<10> { + AREN10_W::new(self) + } + #[doc = "Bit 11 - Async rising enabled 11"] + #[inline(always)] + #[must_use] + pub fn aren11(&mut self) -> AREN11_W<11> { + AREN11_W::new(self) + } + #[doc = "Bit 12 - Async rising enabled 12"] + #[inline(always)] + #[must_use] + pub fn aren12(&mut self) -> AREN12_W<12> { + AREN12_W::new(self) + } + #[doc = "Bit 13 - Async rising enabled 13"] + #[inline(always)] + #[must_use] + pub fn aren13(&mut self) -> AREN13_W<13> { + AREN13_W::new(self) + } + #[doc = "Bit 14 - Async rising enabled 14"] + #[inline(always)] + #[must_use] + pub fn aren14(&mut self) -> AREN14_W<14> { + AREN14_W::new(self) + } + #[doc = "Bit 15 - Async rising enabled 15"] + #[inline(always)] + #[must_use] + pub fn aren15(&mut self) -> AREN15_W<15> { + AREN15_W::new(self) + } + #[doc = "Bit 16 - Async rising enabled 16"] + #[inline(always)] + #[must_use] + pub fn aren16(&mut self) -> AREN16_W<16> { + AREN16_W::new(self) + } + #[doc = "Bit 17 - Async rising enabled 17"] + #[inline(always)] + #[must_use] + pub fn aren17(&mut self) -> AREN17_W<17> { + AREN17_W::new(self) + } + #[doc = "Bit 18 - Async rising enabled 18"] + #[inline(always)] + #[must_use] + pub fn aren18(&mut self) -> AREN18_W<18> { + AREN18_W::new(self) + } + #[doc = "Bit 19 - Async rising enabled 19"] + #[inline(always)] + #[must_use] + pub fn aren19(&mut self) -> AREN19_W<19> { + AREN19_W::new(self) + } + #[doc = "Bit 20 - Async rising enabled 20"] + #[inline(always)] + #[must_use] + pub fn aren20(&mut self) -> AREN20_W<20> { + AREN20_W::new(self) + } + #[doc = "Bit 21 - Async rising enabled 21"] + #[inline(always)] + #[must_use] + pub fn aren21(&mut self) -> AREN21_W<21> { + AREN21_W::new(self) + } + #[doc = "Bit 22 - Async rising enabled 22"] + #[inline(always)] + #[must_use] + pub fn aren22(&mut self) -> AREN22_W<22> { + AREN22_W::new(self) + } + #[doc = "Bit 23 - Async rising enabled 23"] + #[inline(always)] + #[must_use] + pub fn aren23(&mut self) -> AREN23_W<23> { + AREN23_W::new(self) + } + #[doc = "Bit 24 - Async rising enabled 24"] + #[inline(always)] + #[must_use] + pub fn aren24(&mut self) -> AREN24_W<24> { + AREN24_W::new(self) + } + #[doc = "Bit 25 - Async rising enabled 25"] + #[inline(always)] + #[must_use] + pub fn aren25(&mut self) -> AREN25_W<25> { + AREN25_W::new(self) + } + #[doc = "Bit 26 - Async rising enabled 26"] + #[inline(always)] + #[must_use] + pub fn aren26(&mut self) -> AREN26_W<26> { + AREN26_W::new(self) + } + #[doc = "Bit 27 - Async rising enabled 27"] + #[inline(always)] + #[must_use] + pub fn aren27(&mut self) -> AREN27_W<27> { + AREN27_W::new(self) + } + #[doc = "Bit 28 - Async rising enabled 28"] + #[inline(always)] + #[must_use] + pub fn aren28(&mut self) -> AREN28_W<28> { + AREN28_W::new(self) + } + #[doc = "Bit 29 - Async rising enabled 29"] + #[inline(always)] + #[must_use] + pub fn aren29(&mut self) -> AREN29_W<29> { + AREN29_W::new(self) + } + #[doc = "Bit 30 - Async rising enabled 30"] + #[inline(always)] + #[must_use] + pub fn aren30(&mut self) -> AREN30_W<30> { + AREN30_W::new(self) + } + #[doc = "Bit 31 - Async rising enabled 31"] + #[inline(always)] + #[must_use] + pub fn aren31(&mut self) -> AREN31_W<31> { + AREN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen0](index.html) module"] +pub struct GPAREN0_SPEC; +impl crate::RegisterSpec for GPAREN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gparen0::R](R) reader structure"] +impl crate::Readable for GPAREN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gparen0::W](W) writer structure"] +impl crate::Writable for GPAREN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gparen1.rs b/crates/bcm2837-lpa/src/gpio/gparen1.rs new file mode 100644 index 0000000..158f1ef --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gparen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPAREN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPAREN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AREN32` reader - Async rising enabled 32"] +pub type AREN32_R = crate::BitReader; +#[doc = "Field `AREN32` writer - Async rising enabled 32"] +pub type AREN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN33` reader - Async rising enabled 33"] +pub type AREN33_R = crate::BitReader; +#[doc = "Field `AREN33` writer - Async rising enabled 33"] +pub type AREN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN34` reader - Async rising enabled 34"] +pub type AREN34_R = crate::BitReader; +#[doc = "Field `AREN34` writer - Async rising enabled 34"] +pub type AREN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN35` reader - Async rising enabled 35"] +pub type AREN35_R = crate::BitReader; +#[doc = "Field `AREN35` writer - Async rising enabled 35"] +pub type AREN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN36` reader - Async rising enabled 36"] +pub type AREN36_R = crate::BitReader; +#[doc = "Field `AREN36` writer - Async rising enabled 36"] +pub type AREN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN37` reader - Async rising enabled 37"] +pub type AREN37_R = crate::BitReader; +#[doc = "Field `AREN37` writer - Async rising enabled 37"] +pub type AREN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN38` reader - Async rising enabled 38"] +pub type AREN38_R = crate::BitReader; +#[doc = "Field `AREN38` writer - Async rising enabled 38"] +pub type AREN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN39` reader - Async rising enabled 39"] +pub type AREN39_R = crate::BitReader; +#[doc = "Field `AREN39` writer - Async rising enabled 39"] +pub type AREN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN40` reader - Async rising enabled 40"] +pub type AREN40_R = crate::BitReader; +#[doc = "Field `AREN40` writer - Async rising enabled 40"] +pub type AREN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN41` reader - Async rising enabled 41"] +pub type AREN41_R = crate::BitReader; +#[doc = "Field `AREN41` writer - Async rising enabled 41"] +pub type AREN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN42` reader - Async rising enabled 42"] +pub type AREN42_R = crate::BitReader; +#[doc = "Field `AREN42` writer - Async rising enabled 42"] +pub type AREN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN43` reader - Async rising enabled 43"] +pub type AREN43_R = crate::BitReader; +#[doc = "Field `AREN43` writer - Async rising enabled 43"] +pub type AREN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN44` reader - Async rising enabled 44"] +pub type AREN44_R = crate::BitReader; +#[doc = "Field `AREN44` writer - Async rising enabled 44"] +pub type AREN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN45` reader - Async rising enabled 45"] +pub type AREN45_R = crate::BitReader; +#[doc = "Field `AREN45` writer - Async rising enabled 45"] +pub type AREN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN46` reader - Async rising enabled 46"] +pub type AREN46_R = crate::BitReader; +#[doc = "Field `AREN46` writer - Async rising enabled 46"] +pub type AREN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN47` reader - Async rising enabled 47"] +pub type AREN47_R = crate::BitReader; +#[doc = "Field `AREN47` writer - Async rising enabled 47"] +pub type AREN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN48` reader - Async rising enabled 48"] +pub type AREN48_R = crate::BitReader; +#[doc = "Field `AREN48` writer - Async rising enabled 48"] +pub type AREN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN49` reader - Async rising enabled 49"] +pub type AREN49_R = crate::BitReader; +#[doc = "Field `AREN49` writer - Async rising enabled 49"] +pub type AREN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN50` reader - Async rising enabled 50"] +pub type AREN50_R = crate::BitReader; +#[doc = "Field `AREN50` writer - Async rising enabled 50"] +pub type AREN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN51` reader - Async rising enabled 51"] +pub type AREN51_R = crate::BitReader; +#[doc = "Field `AREN51` writer - Async rising enabled 51"] +pub type AREN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN52` reader - Async rising enabled 52"] +pub type AREN52_R = crate::BitReader; +#[doc = "Field `AREN52` writer - Async rising enabled 52"] +pub type AREN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +#[doc = "Field `AREN53` reader - Async rising enabled 53"] +pub type AREN53_R = crate::BitReader; +#[doc = "Field `AREN53` writer - Async rising enabled 53"] +pub type AREN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Async rising enabled 32"] + #[inline(always)] + pub fn aren32(&self) -> AREN32_R { + AREN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Async rising enabled 33"] + #[inline(always)] + pub fn aren33(&self) -> AREN33_R { + AREN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Async rising enabled 34"] + #[inline(always)] + pub fn aren34(&self) -> AREN34_R { + AREN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Async rising enabled 35"] + #[inline(always)] + pub fn aren35(&self) -> AREN35_R { + AREN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Async rising enabled 36"] + #[inline(always)] + pub fn aren36(&self) -> AREN36_R { + AREN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Async rising enabled 37"] + #[inline(always)] + pub fn aren37(&self) -> AREN37_R { + AREN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Async rising enabled 38"] + #[inline(always)] + pub fn aren38(&self) -> AREN38_R { + AREN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Async rising enabled 39"] + #[inline(always)] + pub fn aren39(&self) -> AREN39_R { + AREN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Async rising enabled 40"] + #[inline(always)] + pub fn aren40(&self) -> AREN40_R { + AREN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Async rising enabled 41"] + #[inline(always)] + pub fn aren41(&self) -> AREN41_R { + AREN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Async rising enabled 42"] + #[inline(always)] + pub fn aren42(&self) -> AREN42_R { + AREN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Async rising enabled 43"] + #[inline(always)] + pub fn aren43(&self) -> AREN43_R { + AREN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Async rising enabled 44"] + #[inline(always)] + pub fn aren44(&self) -> AREN44_R { + AREN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Async rising enabled 45"] + #[inline(always)] + pub fn aren45(&self) -> AREN45_R { + AREN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Async rising enabled 46"] + #[inline(always)] + pub fn aren46(&self) -> AREN46_R { + AREN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Async rising enabled 47"] + #[inline(always)] + pub fn aren47(&self) -> AREN47_R { + AREN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Async rising enabled 48"] + #[inline(always)] + pub fn aren48(&self) -> AREN48_R { + AREN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Async rising enabled 49"] + #[inline(always)] + pub fn aren49(&self) -> AREN49_R { + AREN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Async rising enabled 50"] + #[inline(always)] + pub fn aren50(&self) -> AREN50_R { + AREN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Async rising enabled 51"] + #[inline(always)] + pub fn aren51(&self) -> AREN51_R { + AREN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Async rising enabled 52"] + #[inline(always)] + pub fn aren52(&self) -> AREN52_R { + AREN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Async rising enabled 53"] + #[inline(always)] + pub fn aren53(&self) -> AREN53_R { + AREN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Async rising enabled 32"] + #[inline(always)] + #[must_use] + pub fn aren32(&mut self) -> AREN32_W<0> { + AREN32_W::new(self) + } + #[doc = "Bit 1 - Async rising enabled 33"] + #[inline(always)] + #[must_use] + pub fn aren33(&mut self) -> AREN33_W<1> { + AREN33_W::new(self) + } + #[doc = "Bit 2 - Async rising enabled 34"] + #[inline(always)] + #[must_use] + pub fn aren34(&mut self) -> AREN34_W<2> { + AREN34_W::new(self) + } + #[doc = "Bit 3 - Async rising enabled 35"] + #[inline(always)] + #[must_use] + pub fn aren35(&mut self) -> AREN35_W<3> { + AREN35_W::new(self) + } + #[doc = "Bit 4 - Async rising enabled 36"] + #[inline(always)] + #[must_use] + pub fn aren36(&mut self) -> AREN36_W<4> { + AREN36_W::new(self) + } + #[doc = "Bit 5 - Async rising enabled 37"] + #[inline(always)] + #[must_use] + pub fn aren37(&mut self) -> AREN37_W<5> { + AREN37_W::new(self) + } + #[doc = "Bit 6 - Async rising enabled 38"] + #[inline(always)] + #[must_use] + pub fn aren38(&mut self) -> AREN38_W<6> { + AREN38_W::new(self) + } + #[doc = "Bit 7 - Async rising enabled 39"] + #[inline(always)] + #[must_use] + pub fn aren39(&mut self) -> AREN39_W<7> { + AREN39_W::new(self) + } + #[doc = "Bit 8 - Async rising enabled 40"] + #[inline(always)] + #[must_use] + pub fn aren40(&mut self) -> AREN40_W<8> { + AREN40_W::new(self) + } + #[doc = "Bit 9 - Async rising enabled 41"] + #[inline(always)] + #[must_use] + pub fn aren41(&mut self) -> AREN41_W<9> { + AREN41_W::new(self) + } + #[doc = "Bit 10 - Async rising enabled 42"] + #[inline(always)] + #[must_use] + pub fn aren42(&mut self) -> AREN42_W<10> { + AREN42_W::new(self) + } + #[doc = "Bit 11 - Async rising enabled 43"] + #[inline(always)] + #[must_use] + pub fn aren43(&mut self) -> AREN43_W<11> { + AREN43_W::new(self) + } + #[doc = "Bit 12 - Async rising enabled 44"] + #[inline(always)] + #[must_use] + pub fn aren44(&mut self) -> AREN44_W<12> { + AREN44_W::new(self) + } + #[doc = "Bit 13 - Async rising enabled 45"] + #[inline(always)] + #[must_use] + pub fn aren45(&mut self) -> AREN45_W<13> { + AREN45_W::new(self) + } + #[doc = "Bit 14 - Async rising enabled 46"] + #[inline(always)] + #[must_use] + pub fn aren46(&mut self) -> AREN46_W<14> { + AREN46_W::new(self) + } + #[doc = "Bit 15 - Async rising enabled 47"] + #[inline(always)] + #[must_use] + pub fn aren47(&mut self) -> AREN47_W<15> { + AREN47_W::new(self) + } + #[doc = "Bit 16 - Async rising enabled 48"] + #[inline(always)] + #[must_use] + pub fn aren48(&mut self) -> AREN48_W<16> { + AREN48_W::new(self) + } + #[doc = "Bit 17 - Async rising enabled 49"] + #[inline(always)] + #[must_use] + pub fn aren49(&mut self) -> AREN49_W<17> { + AREN49_W::new(self) + } + #[doc = "Bit 18 - Async rising enabled 50"] + #[inline(always)] + #[must_use] + pub fn aren50(&mut self) -> AREN50_W<18> { + AREN50_W::new(self) + } + #[doc = "Bit 19 - Async rising enabled 51"] + #[inline(always)] + #[must_use] + pub fn aren51(&mut self) -> AREN51_W<19> { + AREN51_W::new(self) + } + #[doc = "Bit 20 - Async rising enabled 52"] + #[inline(always)] + #[must_use] + pub fn aren52(&mut self) -> AREN52_W<20> { + AREN52_W::new(self) + } + #[doc = "Bit 21 - Async rising enabled 53"] + #[inline(always)] + #[must_use] + pub fn aren53(&mut self) -> AREN53_W<21> { + AREN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen1](index.html) module"] +pub struct GPAREN1_SPEC; +impl crate::RegisterSpec for GPAREN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gparen1::R](R) reader structure"] +impl crate::Readable for GPAREN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gparen1::W](W) writer structure"] +impl crate::Writable for GPAREN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpclr0.rs b/crates/bcm2837-lpa/src/gpio/gpclr0.rs new file mode 100644 index 0000000..1a6b2cd --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpclr0.rs @@ -0,0 +1,296 @@ +#[doc = "Register `GPCLR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLR0` writer - Clear 0"] +pub type CLR0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR1` writer - Clear 1"] +pub type CLR1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR2` writer - Clear 2"] +pub type CLR2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR3` writer - Clear 3"] +pub type CLR3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR4` writer - Clear 4"] +pub type CLR4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR5` writer - Clear 5"] +pub type CLR5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR6` writer - Clear 6"] +pub type CLR6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR7` writer - Clear 7"] +pub type CLR7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR8` writer - Clear 8"] +pub type CLR8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR9` writer - Clear 9"] +pub type CLR9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR10` writer - Clear 10"] +pub type CLR10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR11` writer - Clear 11"] +pub type CLR11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR12` writer - Clear 12"] +pub type CLR12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR13` writer - Clear 13"] +pub type CLR13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR14` writer - Clear 14"] +pub type CLR14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR15` writer - Clear 15"] +pub type CLR15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR16` writer - Clear 16"] +pub type CLR16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR17` writer - Clear 17"] +pub type CLR17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR18` writer - Clear 18"] +pub type CLR18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR19` writer - Clear 19"] +pub type CLR19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR20` writer - Clear 20"] +pub type CLR20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR21` writer - Clear 21"] +pub type CLR21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR22` writer - Clear 22"] +pub type CLR22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR23` writer - Clear 23"] +pub type CLR23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR24` writer - Clear 24"] +pub type CLR24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR25` writer - Clear 25"] +pub type CLR25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR26` writer - Clear 26"] +pub type CLR26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR27` writer - Clear 27"] +pub type CLR27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR28` writer - Clear 28"] +pub type CLR28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR29` writer - Clear 29"] +pub type CLR29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR30` writer - Clear 30"] +pub type CLR30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +#[doc = "Field `CLR31` writer - Clear 31"] +pub type CLR31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Clear 0"] + #[inline(always)] + #[must_use] + pub fn clr0(&mut self) -> CLR0_W<0> { + CLR0_W::new(self) + } + #[doc = "Bit 1 - Clear 1"] + #[inline(always)] + #[must_use] + pub fn clr1(&mut self) -> CLR1_W<1> { + CLR1_W::new(self) + } + #[doc = "Bit 2 - Clear 2"] + #[inline(always)] + #[must_use] + pub fn clr2(&mut self) -> CLR2_W<2> { + CLR2_W::new(self) + } + #[doc = "Bit 3 - Clear 3"] + #[inline(always)] + #[must_use] + pub fn clr3(&mut self) -> CLR3_W<3> { + CLR3_W::new(self) + } + #[doc = "Bit 4 - Clear 4"] + #[inline(always)] + #[must_use] + pub fn clr4(&mut self) -> CLR4_W<4> { + CLR4_W::new(self) + } + #[doc = "Bit 5 - Clear 5"] + #[inline(always)] + #[must_use] + pub fn clr5(&mut self) -> CLR5_W<5> { + CLR5_W::new(self) + } + #[doc = "Bit 6 - Clear 6"] + #[inline(always)] + #[must_use] + pub fn clr6(&mut self) -> CLR6_W<6> { + CLR6_W::new(self) + } + #[doc = "Bit 7 - Clear 7"] + #[inline(always)] + #[must_use] + pub fn clr7(&mut self) -> CLR7_W<7> { + CLR7_W::new(self) + } + #[doc = "Bit 8 - Clear 8"] + #[inline(always)] + #[must_use] + pub fn clr8(&mut self) -> CLR8_W<8> { + CLR8_W::new(self) + } + #[doc = "Bit 9 - Clear 9"] + #[inline(always)] + #[must_use] + pub fn clr9(&mut self) -> CLR9_W<9> { + CLR9_W::new(self) + } + #[doc = "Bit 10 - Clear 10"] + #[inline(always)] + #[must_use] + pub fn clr10(&mut self) -> CLR10_W<10> { + CLR10_W::new(self) + } + #[doc = "Bit 11 - Clear 11"] + #[inline(always)] + #[must_use] + pub fn clr11(&mut self) -> CLR11_W<11> { + CLR11_W::new(self) + } + #[doc = "Bit 12 - Clear 12"] + #[inline(always)] + #[must_use] + pub fn clr12(&mut self) -> CLR12_W<12> { + CLR12_W::new(self) + } + #[doc = "Bit 13 - Clear 13"] + #[inline(always)] + #[must_use] + pub fn clr13(&mut self) -> CLR13_W<13> { + CLR13_W::new(self) + } + #[doc = "Bit 14 - Clear 14"] + #[inline(always)] + #[must_use] + pub fn clr14(&mut self) -> CLR14_W<14> { + CLR14_W::new(self) + } + #[doc = "Bit 15 - Clear 15"] + #[inline(always)] + #[must_use] + pub fn clr15(&mut self) -> CLR15_W<15> { + CLR15_W::new(self) + } + #[doc = "Bit 16 - Clear 16"] + #[inline(always)] + #[must_use] + pub fn clr16(&mut self) -> CLR16_W<16> { + CLR16_W::new(self) + } + #[doc = "Bit 17 - Clear 17"] + #[inline(always)] + #[must_use] + pub fn clr17(&mut self) -> CLR17_W<17> { + CLR17_W::new(self) + } + #[doc = "Bit 18 - Clear 18"] + #[inline(always)] + #[must_use] + pub fn clr18(&mut self) -> CLR18_W<18> { + CLR18_W::new(self) + } + #[doc = "Bit 19 - Clear 19"] + #[inline(always)] + #[must_use] + pub fn clr19(&mut self) -> CLR19_W<19> { + CLR19_W::new(self) + } + #[doc = "Bit 20 - Clear 20"] + #[inline(always)] + #[must_use] + pub fn clr20(&mut self) -> CLR20_W<20> { + CLR20_W::new(self) + } + #[doc = "Bit 21 - Clear 21"] + #[inline(always)] + #[must_use] + pub fn clr21(&mut self) -> CLR21_W<21> { + CLR21_W::new(self) + } + #[doc = "Bit 22 - Clear 22"] + #[inline(always)] + #[must_use] + pub fn clr22(&mut self) -> CLR22_W<22> { + CLR22_W::new(self) + } + #[doc = "Bit 23 - Clear 23"] + #[inline(always)] + #[must_use] + pub fn clr23(&mut self) -> CLR23_W<23> { + CLR23_W::new(self) + } + #[doc = "Bit 24 - Clear 24"] + #[inline(always)] + #[must_use] + pub fn clr24(&mut self) -> CLR24_W<24> { + CLR24_W::new(self) + } + #[doc = "Bit 25 - Clear 25"] + #[inline(always)] + #[must_use] + pub fn clr25(&mut self) -> CLR25_W<25> { + CLR25_W::new(self) + } + #[doc = "Bit 26 - Clear 26"] + #[inline(always)] + #[must_use] + pub fn clr26(&mut self) -> CLR26_W<26> { + CLR26_W::new(self) + } + #[doc = "Bit 27 - Clear 27"] + #[inline(always)] + #[must_use] + pub fn clr27(&mut self) -> CLR27_W<27> { + CLR27_W::new(self) + } + #[doc = "Bit 28 - Clear 28"] + #[inline(always)] + #[must_use] + pub fn clr28(&mut self) -> CLR28_W<28> { + CLR28_W::new(self) + } + #[doc = "Bit 29 - Clear 29"] + #[inline(always)] + #[must_use] + pub fn clr29(&mut self) -> CLR29_W<29> { + CLR29_W::new(self) + } + #[doc = "Bit 30 - Clear 30"] + #[inline(always)] + #[must_use] + pub fn clr30(&mut self) -> CLR30_W<30> { + CLR30_W::new(self) + } + #[doc = "Bit 31 - Clear 31"] + #[inline(always)] + #[must_use] + pub fn clr31(&mut self) -> CLR31_W<31> { + CLR31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Clear 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr0](index.html) module"] +pub struct GPCLR0_SPEC; +impl crate::RegisterSpec for GPCLR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpclr0::W](W) writer structure"] +impl crate::Writable for GPCLR0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpclr1.rs b/crates/bcm2837-lpa/src/gpio/gpclr1.rs new file mode 100644 index 0000000..84ce196 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpclr1.rs @@ -0,0 +1,216 @@ +#[doc = "Register `GPCLR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLR32` writer - Clear 32"] +pub type CLR32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR33` writer - Clear 33"] +pub type CLR33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR34` writer - Clear 34"] +pub type CLR34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR35` writer - Clear 35"] +pub type CLR35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR36` writer - Clear 36"] +pub type CLR36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR37` writer - Clear 37"] +pub type CLR37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR38` writer - Clear 38"] +pub type CLR38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR39` writer - Clear 39"] +pub type CLR39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR40` writer - Clear 40"] +pub type CLR40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR41` writer - Clear 41"] +pub type CLR41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR42` writer - Clear 42"] +pub type CLR42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR43` writer - Clear 43"] +pub type CLR43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR44` writer - Clear 44"] +pub type CLR44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR45` writer - Clear 45"] +pub type CLR45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR46` writer - Clear 46"] +pub type CLR46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR47` writer - Clear 47"] +pub type CLR47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR48` writer - Clear 48"] +pub type CLR48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR49` writer - Clear 49"] +pub type CLR49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR50` writer - Clear 50"] +pub type CLR50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR51` writer - Clear 51"] +pub type CLR51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR52` writer - Clear 52"] +pub type CLR52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +#[doc = "Field `CLR53` writer - Clear 53"] +pub type CLR53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Clear 32"] + #[inline(always)] + #[must_use] + pub fn clr32(&mut self) -> CLR32_W<0> { + CLR32_W::new(self) + } + #[doc = "Bit 1 - Clear 33"] + #[inline(always)] + #[must_use] + pub fn clr33(&mut self) -> CLR33_W<1> { + CLR33_W::new(self) + } + #[doc = "Bit 2 - Clear 34"] + #[inline(always)] + #[must_use] + pub fn clr34(&mut self) -> CLR34_W<2> { + CLR34_W::new(self) + } + #[doc = "Bit 3 - Clear 35"] + #[inline(always)] + #[must_use] + pub fn clr35(&mut self) -> CLR35_W<3> { + CLR35_W::new(self) + } + #[doc = "Bit 4 - Clear 36"] + #[inline(always)] + #[must_use] + pub fn clr36(&mut self) -> CLR36_W<4> { + CLR36_W::new(self) + } + #[doc = "Bit 5 - Clear 37"] + #[inline(always)] + #[must_use] + pub fn clr37(&mut self) -> CLR37_W<5> { + CLR37_W::new(self) + } + #[doc = "Bit 6 - Clear 38"] + #[inline(always)] + #[must_use] + pub fn clr38(&mut self) -> CLR38_W<6> { + CLR38_W::new(self) + } + #[doc = "Bit 7 - Clear 39"] + #[inline(always)] + #[must_use] + pub fn clr39(&mut self) -> CLR39_W<7> { + CLR39_W::new(self) + } + #[doc = "Bit 8 - Clear 40"] + #[inline(always)] + #[must_use] + pub fn clr40(&mut self) -> CLR40_W<8> { + CLR40_W::new(self) + } + #[doc = "Bit 9 - Clear 41"] + #[inline(always)] + #[must_use] + pub fn clr41(&mut self) -> CLR41_W<9> { + CLR41_W::new(self) + } + #[doc = "Bit 10 - Clear 42"] + #[inline(always)] + #[must_use] + pub fn clr42(&mut self) -> CLR42_W<10> { + CLR42_W::new(self) + } + #[doc = "Bit 11 - Clear 43"] + #[inline(always)] + #[must_use] + pub fn clr43(&mut self) -> CLR43_W<11> { + CLR43_W::new(self) + } + #[doc = "Bit 12 - Clear 44"] + #[inline(always)] + #[must_use] + pub fn clr44(&mut self) -> CLR44_W<12> { + CLR44_W::new(self) + } + #[doc = "Bit 13 - Clear 45"] + #[inline(always)] + #[must_use] + pub fn clr45(&mut self) -> CLR45_W<13> { + CLR45_W::new(self) + } + #[doc = "Bit 14 - Clear 46"] + #[inline(always)] + #[must_use] + pub fn clr46(&mut self) -> CLR46_W<14> { + CLR46_W::new(self) + } + #[doc = "Bit 15 - Clear 47"] + #[inline(always)] + #[must_use] + pub fn clr47(&mut self) -> CLR47_W<15> { + CLR47_W::new(self) + } + #[doc = "Bit 16 - Clear 48"] + #[inline(always)] + #[must_use] + pub fn clr48(&mut self) -> CLR48_W<16> { + CLR48_W::new(self) + } + #[doc = "Bit 17 - Clear 49"] + #[inline(always)] + #[must_use] + pub fn clr49(&mut self) -> CLR49_W<17> { + CLR49_W::new(self) + } + #[doc = "Bit 18 - Clear 50"] + #[inline(always)] + #[must_use] + pub fn clr50(&mut self) -> CLR50_W<18> { + CLR50_W::new(self) + } + #[doc = "Bit 19 - Clear 51"] + #[inline(always)] + #[must_use] + pub fn clr51(&mut self) -> CLR51_W<19> { + CLR51_W::new(self) + } + #[doc = "Bit 20 - Clear 52"] + #[inline(always)] + #[must_use] + pub fn clr52(&mut self) -> CLR52_W<20> { + CLR52_W::new(self) + } + #[doc = "Bit 21 - Clear 53"] + #[inline(always)] + #[must_use] + pub fn clr53(&mut self) -> CLR53_W<21> { + CLR53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Clear 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr1](index.html) module"] +pub struct GPCLR1_SPEC; +impl crate::RegisterSpec for GPCLR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpclr1::W](W) writer structure"] +impl crate::Writable for GPCLR1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpeds0.rs b/crates/bcm2837-lpa/src/gpio/gpeds0.rs new file mode 100644 index 0000000..7aadf5b --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpeds0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPEDS0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPEDS0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EDS0` reader - Event detected 0"] +pub type EDS0_R = crate::BitReader; +#[doc = "Field `EDS0` writer - Event detected 0"] +pub type EDS0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS1` reader - Event detected 1"] +pub type EDS1_R = crate::BitReader; +#[doc = "Field `EDS1` writer - Event detected 1"] +pub type EDS1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS2` reader - Event detected 2"] +pub type EDS2_R = crate::BitReader; +#[doc = "Field `EDS2` writer - Event detected 2"] +pub type EDS2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS3` reader - Event detected 3"] +pub type EDS3_R = crate::BitReader; +#[doc = "Field `EDS3` writer - Event detected 3"] +pub type EDS3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS4` reader - Event detected 4"] +pub type EDS4_R = crate::BitReader; +#[doc = "Field `EDS4` writer - Event detected 4"] +pub type EDS4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS5` reader - Event detected 5"] +pub type EDS5_R = crate::BitReader; +#[doc = "Field `EDS5` writer - Event detected 5"] +pub type EDS5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS6` reader - Event detected 6"] +pub type EDS6_R = crate::BitReader; +#[doc = "Field `EDS6` writer - Event detected 6"] +pub type EDS6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS7` reader - Event detected 7"] +pub type EDS7_R = crate::BitReader; +#[doc = "Field `EDS7` writer - Event detected 7"] +pub type EDS7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS8` reader - Event detected 8"] +pub type EDS8_R = crate::BitReader; +#[doc = "Field `EDS8` writer - Event detected 8"] +pub type EDS8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS9` reader - Event detected 9"] +pub type EDS9_R = crate::BitReader; +#[doc = "Field `EDS9` writer - Event detected 9"] +pub type EDS9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS10` reader - Event detected 10"] +pub type EDS10_R = crate::BitReader; +#[doc = "Field `EDS10` writer - Event detected 10"] +pub type EDS10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS11` reader - Event detected 11"] +pub type EDS11_R = crate::BitReader; +#[doc = "Field `EDS11` writer - Event detected 11"] +pub type EDS11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS12` reader - Event detected 12"] +pub type EDS12_R = crate::BitReader; +#[doc = "Field `EDS12` writer - Event detected 12"] +pub type EDS12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS13` reader - Event detected 13"] +pub type EDS13_R = crate::BitReader; +#[doc = "Field `EDS13` writer - Event detected 13"] +pub type EDS13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS14` reader - Event detected 14"] +pub type EDS14_R = crate::BitReader; +#[doc = "Field `EDS14` writer - Event detected 14"] +pub type EDS14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS15` reader - Event detected 15"] +pub type EDS15_R = crate::BitReader; +#[doc = "Field `EDS15` writer - Event detected 15"] +pub type EDS15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS16` reader - Event detected 16"] +pub type EDS16_R = crate::BitReader; +#[doc = "Field `EDS16` writer - Event detected 16"] +pub type EDS16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS17` reader - Event detected 17"] +pub type EDS17_R = crate::BitReader; +#[doc = "Field `EDS17` writer - Event detected 17"] +pub type EDS17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS18` reader - Event detected 18"] +pub type EDS18_R = crate::BitReader; +#[doc = "Field `EDS18` writer - Event detected 18"] +pub type EDS18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS19` reader - Event detected 19"] +pub type EDS19_R = crate::BitReader; +#[doc = "Field `EDS19` writer - Event detected 19"] +pub type EDS19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS20` reader - Event detected 20"] +pub type EDS20_R = crate::BitReader; +#[doc = "Field `EDS20` writer - Event detected 20"] +pub type EDS20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS21` reader - Event detected 21"] +pub type EDS21_R = crate::BitReader; +#[doc = "Field `EDS21` writer - Event detected 21"] +pub type EDS21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS22` reader - Event detected 22"] +pub type EDS22_R = crate::BitReader; +#[doc = "Field `EDS22` writer - Event detected 22"] +pub type EDS22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS23` reader - Event detected 23"] +pub type EDS23_R = crate::BitReader; +#[doc = "Field `EDS23` writer - Event detected 23"] +pub type EDS23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS24` reader - Event detected 24"] +pub type EDS24_R = crate::BitReader; +#[doc = "Field `EDS24` writer - Event detected 24"] +pub type EDS24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS25` reader - Event detected 25"] +pub type EDS25_R = crate::BitReader; +#[doc = "Field `EDS25` writer - Event detected 25"] +pub type EDS25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS26` reader - Event detected 26"] +pub type EDS26_R = crate::BitReader; +#[doc = "Field `EDS26` writer - Event detected 26"] +pub type EDS26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS27` reader - Event detected 27"] +pub type EDS27_R = crate::BitReader; +#[doc = "Field `EDS27` writer - Event detected 27"] +pub type EDS27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS28` reader - Event detected 28"] +pub type EDS28_R = crate::BitReader; +#[doc = "Field `EDS28` writer - Event detected 28"] +pub type EDS28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS29` reader - Event detected 29"] +pub type EDS29_R = crate::BitReader; +#[doc = "Field `EDS29` writer - Event detected 29"] +pub type EDS29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS30` reader - Event detected 30"] +pub type EDS30_R = crate::BitReader; +#[doc = "Field `EDS30` writer - Event detected 30"] +pub type EDS30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +#[doc = "Field `EDS31` reader - Event detected 31"] +pub type EDS31_R = crate::BitReader; +#[doc = "Field `EDS31` writer - Event detected 31"] +pub type EDS31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Event detected 0"] + #[inline(always)] + pub fn eds0(&self) -> EDS0_R { + EDS0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Event detected 1"] + #[inline(always)] + pub fn eds1(&self) -> EDS1_R { + EDS1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Event detected 2"] + #[inline(always)] + pub fn eds2(&self) -> EDS2_R { + EDS2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Event detected 3"] + #[inline(always)] + pub fn eds3(&self) -> EDS3_R { + EDS3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Event detected 4"] + #[inline(always)] + pub fn eds4(&self) -> EDS4_R { + EDS4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Event detected 5"] + #[inline(always)] + pub fn eds5(&self) -> EDS5_R { + EDS5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Event detected 6"] + #[inline(always)] + pub fn eds6(&self) -> EDS6_R { + EDS6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Event detected 7"] + #[inline(always)] + pub fn eds7(&self) -> EDS7_R { + EDS7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Event detected 8"] + #[inline(always)] + pub fn eds8(&self) -> EDS8_R { + EDS8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Event detected 9"] + #[inline(always)] + pub fn eds9(&self) -> EDS9_R { + EDS9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Event detected 10"] + #[inline(always)] + pub fn eds10(&self) -> EDS10_R { + EDS10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Event detected 11"] + #[inline(always)] + pub fn eds11(&self) -> EDS11_R { + EDS11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Event detected 12"] + #[inline(always)] + pub fn eds12(&self) -> EDS12_R { + EDS12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Event detected 13"] + #[inline(always)] + pub fn eds13(&self) -> EDS13_R { + EDS13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Event detected 14"] + #[inline(always)] + pub fn eds14(&self) -> EDS14_R { + EDS14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Event detected 15"] + #[inline(always)] + pub fn eds15(&self) -> EDS15_R { + EDS15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Event detected 16"] + #[inline(always)] + pub fn eds16(&self) -> EDS16_R { + EDS16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Event detected 17"] + #[inline(always)] + pub fn eds17(&self) -> EDS17_R { + EDS17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event detected 18"] + #[inline(always)] + pub fn eds18(&self) -> EDS18_R { + EDS18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Event detected 19"] + #[inline(always)] + pub fn eds19(&self) -> EDS19_R { + EDS19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Event detected 20"] + #[inline(always)] + pub fn eds20(&self) -> EDS20_R { + EDS20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event detected 21"] + #[inline(always)] + pub fn eds21(&self) -> EDS21_R { + EDS21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Event detected 22"] + #[inline(always)] + pub fn eds22(&self) -> EDS22_R { + EDS22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Event detected 23"] + #[inline(always)] + pub fn eds23(&self) -> EDS23_R { + EDS23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Event detected 24"] + #[inline(always)] + pub fn eds24(&self) -> EDS24_R { + EDS24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Event detected 25"] + #[inline(always)] + pub fn eds25(&self) -> EDS25_R { + EDS25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Event detected 26"] + #[inline(always)] + pub fn eds26(&self) -> EDS26_R { + EDS26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Event detected 27"] + #[inline(always)] + pub fn eds27(&self) -> EDS27_R { + EDS27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Event detected 28"] + #[inline(always)] + pub fn eds28(&self) -> EDS28_R { + EDS28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Event detected 29"] + #[inline(always)] + pub fn eds29(&self) -> EDS29_R { + EDS29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Event detected 30"] + #[inline(always)] + pub fn eds30(&self) -> EDS30_R { + EDS30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Event detected 31"] + #[inline(always)] + pub fn eds31(&self) -> EDS31_R { + EDS31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event detected 0"] + #[inline(always)] + #[must_use] + pub fn eds0(&mut self) -> EDS0_W<0> { + EDS0_W::new(self) + } + #[doc = "Bit 1 - Event detected 1"] + #[inline(always)] + #[must_use] + pub fn eds1(&mut self) -> EDS1_W<1> { + EDS1_W::new(self) + } + #[doc = "Bit 2 - Event detected 2"] + #[inline(always)] + #[must_use] + pub fn eds2(&mut self) -> EDS2_W<2> { + EDS2_W::new(self) + } + #[doc = "Bit 3 - Event detected 3"] + #[inline(always)] + #[must_use] + pub fn eds3(&mut self) -> EDS3_W<3> { + EDS3_W::new(self) + } + #[doc = "Bit 4 - Event detected 4"] + #[inline(always)] + #[must_use] + pub fn eds4(&mut self) -> EDS4_W<4> { + EDS4_W::new(self) + } + #[doc = "Bit 5 - Event detected 5"] + #[inline(always)] + #[must_use] + pub fn eds5(&mut self) -> EDS5_W<5> { + EDS5_W::new(self) + } + #[doc = "Bit 6 - Event detected 6"] + #[inline(always)] + #[must_use] + pub fn eds6(&mut self) -> EDS6_W<6> { + EDS6_W::new(self) + } + #[doc = "Bit 7 - Event detected 7"] + #[inline(always)] + #[must_use] + pub fn eds7(&mut self) -> EDS7_W<7> { + EDS7_W::new(self) + } + #[doc = "Bit 8 - Event detected 8"] + #[inline(always)] + #[must_use] + pub fn eds8(&mut self) -> EDS8_W<8> { + EDS8_W::new(self) + } + #[doc = "Bit 9 - Event detected 9"] + #[inline(always)] + #[must_use] + pub fn eds9(&mut self) -> EDS9_W<9> { + EDS9_W::new(self) + } + #[doc = "Bit 10 - Event detected 10"] + #[inline(always)] + #[must_use] + pub fn eds10(&mut self) -> EDS10_W<10> { + EDS10_W::new(self) + } + #[doc = "Bit 11 - Event detected 11"] + #[inline(always)] + #[must_use] + pub fn eds11(&mut self) -> EDS11_W<11> { + EDS11_W::new(self) + } + #[doc = "Bit 12 - Event detected 12"] + #[inline(always)] + #[must_use] + pub fn eds12(&mut self) -> EDS12_W<12> { + EDS12_W::new(self) + } + #[doc = "Bit 13 - Event detected 13"] + #[inline(always)] + #[must_use] + pub fn eds13(&mut self) -> EDS13_W<13> { + EDS13_W::new(self) + } + #[doc = "Bit 14 - Event detected 14"] + #[inline(always)] + #[must_use] + pub fn eds14(&mut self) -> EDS14_W<14> { + EDS14_W::new(self) + } + #[doc = "Bit 15 - Event detected 15"] + #[inline(always)] + #[must_use] + pub fn eds15(&mut self) -> EDS15_W<15> { + EDS15_W::new(self) + } + #[doc = "Bit 16 - Event detected 16"] + #[inline(always)] + #[must_use] + pub fn eds16(&mut self) -> EDS16_W<16> { + EDS16_W::new(self) + } + #[doc = "Bit 17 - Event detected 17"] + #[inline(always)] + #[must_use] + pub fn eds17(&mut self) -> EDS17_W<17> { + EDS17_W::new(self) + } + #[doc = "Bit 18 - Event detected 18"] + #[inline(always)] + #[must_use] + pub fn eds18(&mut self) -> EDS18_W<18> { + EDS18_W::new(self) + } + #[doc = "Bit 19 - Event detected 19"] + #[inline(always)] + #[must_use] + pub fn eds19(&mut self) -> EDS19_W<19> { + EDS19_W::new(self) + } + #[doc = "Bit 20 - Event detected 20"] + #[inline(always)] + #[must_use] + pub fn eds20(&mut self) -> EDS20_W<20> { + EDS20_W::new(self) + } + #[doc = "Bit 21 - Event detected 21"] + #[inline(always)] + #[must_use] + pub fn eds21(&mut self) -> EDS21_W<21> { + EDS21_W::new(self) + } + #[doc = "Bit 22 - Event detected 22"] + #[inline(always)] + #[must_use] + pub fn eds22(&mut self) -> EDS22_W<22> { + EDS22_W::new(self) + } + #[doc = "Bit 23 - Event detected 23"] + #[inline(always)] + #[must_use] + pub fn eds23(&mut self) -> EDS23_W<23> { + EDS23_W::new(self) + } + #[doc = "Bit 24 - Event detected 24"] + #[inline(always)] + #[must_use] + pub fn eds24(&mut self) -> EDS24_W<24> { + EDS24_W::new(self) + } + #[doc = "Bit 25 - Event detected 25"] + #[inline(always)] + #[must_use] + pub fn eds25(&mut self) -> EDS25_W<25> { + EDS25_W::new(self) + } + #[doc = "Bit 26 - Event detected 26"] + #[inline(always)] + #[must_use] + pub fn eds26(&mut self) -> EDS26_W<26> { + EDS26_W::new(self) + } + #[doc = "Bit 27 - Event detected 27"] + #[inline(always)] + #[must_use] + pub fn eds27(&mut self) -> EDS27_W<27> { + EDS27_W::new(self) + } + #[doc = "Bit 28 - Event detected 28"] + #[inline(always)] + #[must_use] + pub fn eds28(&mut self) -> EDS28_W<28> { + EDS28_W::new(self) + } + #[doc = "Bit 29 - Event detected 29"] + #[inline(always)] + #[must_use] + pub fn eds29(&mut self) -> EDS29_W<29> { + EDS29_W::new(self) + } + #[doc = "Bit 30 - Event detected 30"] + #[inline(always)] + #[must_use] + pub fn eds30(&mut self) -> EDS30_W<30> { + EDS30_W::new(self) + } + #[doc = "Bit 31 - Event detected 31"] + #[inline(always)] + #[must_use] + pub fn eds31(&mut self) -> EDS31_W<31> { + EDS31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Event Detect Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds0](index.html) module"] +pub struct GPEDS0_SPEC; +impl crate::RegisterSpec for GPEDS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpeds0::R](R) reader structure"] +impl crate::Readable for GPEDS0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpeds0::W](W) writer structure"] +impl crate::Writable for GPEDS0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpeds1.rs b/crates/bcm2837-lpa/src/gpio/gpeds1.rs new file mode 100644 index 0000000..bcef23a --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpeds1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPEDS1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPEDS1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EDS32` reader - Event detected 32"] +pub type EDS32_R = crate::BitReader; +#[doc = "Field `EDS32` writer - Event detected 32"] +pub type EDS32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS33` reader - Event detected 33"] +pub type EDS33_R = crate::BitReader; +#[doc = "Field `EDS33` writer - Event detected 33"] +pub type EDS33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS34` reader - Event detected 34"] +pub type EDS34_R = crate::BitReader; +#[doc = "Field `EDS34` writer - Event detected 34"] +pub type EDS34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS35` reader - Event detected 35"] +pub type EDS35_R = crate::BitReader; +#[doc = "Field `EDS35` writer - Event detected 35"] +pub type EDS35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS36` reader - Event detected 36"] +pub type EDS36_R = crate::BitReader; +#[doc = "Field `EDS36` writer - Event detected 36"] +pub type EDS36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS37` reader - Event detected 37"] +pub type EDS37_R = crate::BitReader; +#[doc = "Field `EDS37` writer - Event detected 37"] +pub type EDS37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS38` reader - Event detected 38"] +pub type EDS38_R = crate::BitReader; +#[doc = "Field `EDS38` writer - Event detected 38"] +pub type EDS38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS39` reader - Event detected 39"] +pub type EDS39_R = crate::BitReader; +#[doc = "Field `EDS39` writer - Event detected 39"] +pub type EDS39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS40` reader - Event detected 40"] +pub type EDS40_R = crate::BitReader; +#[doc = "Field `EDS40` writer - Event detected 40"] +pub type EDS40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS41` reader - Event detected 41"] +pub type EDS41_R = crate::BitReader; +#[doc = "Field `EDS41` writer - Event detected 41"] +pub type EDS41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS42` reader - Event detected 42"] +pub type EDS42_R = crate::BitReader; +#[doc = "Field `EDS42` writer - Event detected 42"] +pub type EDS42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS43` reader - Event detected 43"] +pub type EDS43_R = crate::BitReader; +#[doc = "Field `EDS43` writer - Event detected 43"] +pub type EDS43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS44` reader - Event detected 44"] +pub type EDS44_R = crate::BitReader; +#[doc = "Field `EDS44` writer - Event detected 44"] +pub type EDS44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS45` reader - Event detected 45"] +pub type EDS45_R = crate::BitReader; +#[doc = "Field `EDS45` writer - Event detected 45"] +pub type EDS45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS46` reader - Event detected 46"] +pub type EDS46_R = crate::BitReader; +#[doc = "Field `EDS46` writer - Event detected 46"] +pub type EDS46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS47` reader - Event detected 47"] +pub type EDS47_R = crate::BitReader; +#[doc = "Field `EDS47` writer - Event detected 47"] +pub type EDS47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS48` reader - Event detected 48"] +pub type EDS48_R = crate::BitReader; +#[doc = "Field `EDS48` writer - Event detected 48"] +pub type EDS48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS49` reader - Event detected 49"] +pub type EDS49_R = crate::BitReader; +#[doc = "Field `EDS49` writer - Event detected 49"] +pub type EDS49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS50` reader - Event detected 50"] +pub type EDS50_R = crate::BitReader; +#[doc = "Field `EDS50` writer - Event detected 50"] +pub type EDS50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS51` reader - Event detected 51"] +pub type EDS51_R = crate::BitReader; +#[doc = "Field `EDS51` writer - Event detected 51"] +pub type EDS51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS52` reader - Event detected 52"] +pub type EDS52_R = crate::BitReader; +#[doc = "Field `EDS52` writer - Event detected 52"] +pub type EDS52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +#[doc = "Field `EDS53` reader - Event detected 53"] +pub type EDS53_R = crate::BitReader; +#[doc = "Field `EDS53` writer - Event detected 53"] +pub type EDS53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Event detected 32"] + #[inline(always)] + pub fn eds32(&self) -> EDS32_R { + EDS32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Event detected 33"] + #[inline(always)] + pub fn eds33(&self) -> EDS33_R { + EDS33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Event detected 34"] + #[inline(always)] + pub fn eds34(&self) -> EDS34_R { + EDS34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Event detected 35"] + #[inline(always)] + pub fn eds35(&self) -> EDS35_R { + EDS35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Event detected 36"] + #[inline(always)] + pub fn eds36(&self) -> EDS36_R { + EDS36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Event detected 37"] + #[inline(always)] + pub fn eds37(&self) -> EDS37_R { + EDS37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Event detected 38"] + #[inline(always)] + pub fn eds38(&self) -> EDS38_R { + EDS38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Event detected 39"] + #[inline(always)] + pub fn eds39(&self) -> EDS39_R { + EDS39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Event detected 40"] + #[inline(always)] + pub fn eds40(&self) -> EDS40_R { + EDS40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Event detected 41"] + #[inline(always)] + pub fn eds41(&self) -> EDS41_R { + EDS41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Event detected 42"] + #[inline(always)] + pub fn eds42(&self) -> EDS42_R { + EDS42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Event detected 43"] + #[inline(always)] + pub fn eds43(&self) -> EDS43_R { + EDS43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Event detected 44"] + #[inline(always)] + pub fn eds44(&self) -> EDS44_R { + EDS44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Event detected 45"] + #[inline(always)] + pub fn eds45(&self) -> EDS45_R { + EDS45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Event detected 46"] + #[inline(always)] + pub fn eds46(&self) -> EDS46_R { + EDS46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Event detected 47"] + #[inline(always)] + pub fn eds47(&self) -> EDS47_R { + EDS47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Event detected 48"] + #[inline(always)] + pub fn eds48(&self) -> EDS48_R { + EDS48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Event detected 49"] + #[inline(always)] + pub fn eds49(&self) -> EDS49_R { + EDS49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Event detected 50"] + #[inline(always)] + pub fn eds50(&self) -> EDS50_R { + EDS50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Event detected 51"] + #[inline(always)] + pub fn eds51(&self) -> EDS51_R { + EDS51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Event detected 52"] + #[inline(always)] + pub fn eds52(&self) -> EDS52_R { + EDS52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event detected 53"] + #[inline(always)] + pub fn eds53(&self) -> EDS53_R { + EDS53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Event detected 32"] + #[inline(always)] + #[must_use] + pub fn eds32(&mut self) -> EDS32_W<0> { + EDS32_W::new(self) + } + #[doc = "Bit 1 - Event detected 33"] + #[inline(always)] + #[must_use] + pub fn eds33(&mut self) -> EDS33_W<1> { + EDS33_W::new(self) + } + #[doc = "Bit 2 - Event detected 34"] + #[inline(always)] + #[must_use] + pub fn eds34(&mut self) -> EDS34_W<2> { + EDS34_W::new(self) + } + #[doc = "Bit 3 - Event detected 35"] + #[inline(always)] + #[must_use] + pub fn eds35(&mut self) -> EDS35_W<3> { + EDS35_W::new(self) + } + #[doc = "Bit 4 - Event detected 36"] + #[inline(always)] + #[must_use] + pub fn eds36(&mut self) -> EDS36_W<4> { + EDS36_W::new(self) + } + #[doc = "Bit 5 - Event detected 37"] + #[inline(always)] + #[must_use] + pub fn eds37(&mut self) -> EDS37_W<5> { + EDS37_W::new(self) + } + #[doc = "Bit 6 - Event detected 38"] + #[inline(always)] + #[must_use] + pub fn eds38(&mut self) -> EDS38_W<6> { + EDS38_W::new(self) + } + #[doc = "Bit 7 - Event detected 39"] + #[inline(always)] + #[must_use] + pub fn eds39(&mut self) -> EDS39_W<7> { + EDS39_W::new(self) + } + #[doc = "Bit 8 - Event detected 40"] + #[inline(always)] + #[must_use] + pub fn eds40(&mut self) -> EDS40_W<8> { + EDS40_W::new(self) + } + #[doc = "Bit 9 - Event detected 41"] + #[inline(always)] + #[must_use] + pub fn eds41(&mut self) -> EDS41_W<9> { + EDS41_W::new(self) + } + #[doc = "Bit 10 - Event detected 42"] + #[inline(always)] + #[must_use] + pub fn eds42(&mut self) -> EDS42_W<10> { + EDS42_W::new(self) + } + #[doc = "Bit 11 - Event detected 43"] + #[inline(always)] + #[must_use] + pub fn eds43(&mut self) -> EDS43_W<11> { + EDS43_W::new(self) + } + #[doc = "Bit 12 - Event detected 44"] + #[inline(always)] + #[must_use] + pub fn eds44(&mut self) -> EDS44_W<12> { + EDS44_W::new(self) + } + #[doc = "Bit 13 - Event detected 45"] + #[inline(always)] + #[must_use] + pub fn eds45(&mut self) -> EDS45_W<13> { + EDS45_W::new(self) + } + #[doc = "Bit 14 - Event detected 46"] + #[inline(always)] + #[must_use] + pub fn eds46(&mut self) -> EDS46_W<14> { + EDS46_W::new(self) + } + #[doc = "Bit 15 - Event detected 47"] + #[inline(always)] + #[must_use] + pub fn eds47(&mut self) -> EDS47_W<15> { + EDS47_W::new(self) + } + #[doc = "Bit 16 - Event detected 48"] + #[inline(always)] + #[must_use] + pub fn eds48(&mut self) -> EDS48_W<16> { + EDS48_W::new(self) + } + #[doc = "Bit 17 - Event detected 49"] + #[inline(always)] + #[must_use] + pub fn eds49(&mut self) -> EDS49_W<17> { + EDS49_W::new(self) + } + #[doc = "Bit 18 - Event detected 50"] + #[inline(always)] + #[must_use] + pub fn eds50(&mut self) -> EDS50_W<18> { + EDS50_W::new(self) + } + #[doc = "Bit 19 - Event detected 51"] + #[inline(always)] + #[must_use] + pub fn eds51(&mut self) -> EDS51_W<19> { + EDS51_W::new(self) + } + #[doc = "Bit 20 - Event detected 52"] + #[inline(always)] + #[must_use] + pub fn eds52(&mut self) -> EDS52_W<20> { + EDS52_W::new(self) + } + #[doc = "Bit 21 - Event detected 53"] + #[inline(always)] + #[must_use] + pub fn eds53(&mut self) -> EDS53_W<21> { + EDS53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Event Detect Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds1](index.html) module"] +pub struct GPEDS1_SPEC; +impl crate::RegisterSpec for GPEDS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpeds1::R](R) reader structure"] +impl crate::Readable for GPEDS1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpeds1::W](W) writer structure"] +impl crate::Writable for GPEDS1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfen0.rs b/crates/bcm2837-lpa/src/gpio/gpfen0.rs new file mode 100644 index 0000000..58ded22 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPFEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FEN0` reader - Falling edge enabled 0"] +pub type FEN0_R = crate::BitReader; +#[doc = "Field `FEN0` writer - Falling edge enabled 0"] +pub type FEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN1` reader - Falling edge enabled 1"] +pub type FEN1_R = crate::BitReader; +#[doc = "Field `FEN1` writer - Falling edge enabled 1"] +pub type FEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN2` reader - Falling edge enabled 2"] +pub type FEN2_R = crate::BitReader; +#[doc = "Field `FEN2` writer - Falling edge enabled 2"] +pub type FEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN3` reader - Falling edge enabled 3"] +pub type FEN3_R = crate::BitReader; +#[doc = "Field `FEN3` writer - Falling edge enabled 3"] +pub type FEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN4` reader - Falling edge enabled 4"] +pub type FEN4_R = crate::BitReader; +#[doc = "Field `FEN4` writer - Falling edge enabled 4"] +pub type FEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN5` reader - Falling edge enabled 5"] +pub type FEN5_R = crate::BitReader; +#[doc = "Field `FEN5` writer - Falling edge enabled 5"] +pub type FEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN6` reader - Falling edge enabled 6"] +pub type FEN6_R = crate::BitReader; +#[doc = "Field `FEN6` writer - Falling edge enabled 6"] +pub type FEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN7` reader - Falling edge enabled 7"] +pub type FEN7_R = crate::BitReader; +#[doc = "Field `FEN7` writer - Falling edge enabled 7"] +pub type FEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN8` reader - Falling edge enabled 8"] +pub type FEN8_R = crate::BitReader; +#[doc = "Field `FEN8` writer - Falling edge enabled 8"] +pub type FEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN9` reader - Falling edge enabled 9"] +pub type FEN9_R = crate::BitReader; +#[doc = "Field `FEN9` writer - Falling edge enabled 9"] +pub type FEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN10` reader - Falling edge enabled 10"] +pub type FEN10_R = crate::BitReader; +#[doc = "Field `FEN10` writer - Falling edge enabled 10"] +pub type FEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN11` reader - Falling edge enabled 11"] +pub type FEN11_R = crate::BitReader; +#[doc = "Field `FEN11` writer - Falling edge enabled 11"] +pub type FEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN12` reader - Falling edge enabled 12"] +pub type FEN12_R = crate::BitReader; +#[doc = "Field `FEN12` writer - Falling edge enabled 12"] +pub type FEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN13` reader - Falling edge enabled 13"] +pub type FEN13_R = crate::BitReader; +#[doc = "Field `FEN13` writer - Falling edge enabled 13"] +pub type FEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN14` reader - Falling edge enabled 14"] +pub type FEN14_R = crate::BitReader; +#[doc = "Field `FEN14` writer - Falling edge enabled 14"] +pub type FEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN15` reader - Falling edge enabled 15"] +pub type FEN15_R = crate::BitReader; +#[doc = "Field `FEN15` writer - Falling edge enabled 15"] +pub type FEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN16` reader - Falling edge enabled 16"] +pub type FEN16_R = crate::BitReader; +#[doc = "Field `FEN16` writer - Falling edge enabled 16"] +pub type FEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN17` reader - Falling edge enabled 17"] +pub type FEN17_R = crate::BitReader; +#[doc = "Field `FEN17` writer - Falling edge enabled 17"] +pub type FEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN18` reader - Falling edge enabled 18"] +pub type FEN18_R = crate::BitReader; +#[doc = "Field `FEN18` writer - Falling edge enabled 18"] +pub type FEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN19` reader - Falling edge enabled 19"] +pub type FEN19_R = crate::BitReader; +#[doc = "Field `FEN19` writer - Falling edge enabled 19"] +pub type FEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN20` reader - Falling edge enabled 20"] +pub type FEN20_R = crate::BitReader; +#[doc = "Field `FEN20` writer - Falling edge enabled 20"] +pub type FEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN21` reader - Falling edge enabled 21"] +pub type FEN21_R = crate::BitReader; +#[doc = "Field `FEN21` writer - Falling edge enabled 21"] +pub type FEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN22` reader - Falling edge enabled 22"] +pub type FEN22_R = crate::BitReader; +#[doc = "Field `FEN22` writer - Falling edge enabled 22"] +pub type FEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN23` reader - Falling edge enabled 23"] +pub type FEN23_R = crate::BitReader; +#[doc = "Field `FEN23` writer - Falling edge enabled 23"] +pub type FEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN24` reader - Falling edge enabled 24"] +pub type FEN24_R = crate::BitReader; +#[doc = "Field `FEN24` writer - Falling edge enabled 24"] +pub type FEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN25` reader - Falling edge enabled 25"] +pub type FEN25_R = crate::BitReader; +#[doc = "Field `FEN25` writer - Falling edge enabled 25"] +pub type FEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN26` reader - Falling edge enabled 26"] +pub type FEN26_R = crate::BitReader; +#[doc = "Field `FEN26` writer - Falling edge enabled 26"] +pub type FEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN27` reader - Falling edge enabled 27"] +pub type FEN27_R = crate::BitReader; +#[doc = "Field `FEN27` writer - Falling edge enabled 27"] +pub type FEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN28` reader - Falling edge enabled 28"] +pub type FEN28_R = crate::BitReader; +#[doc = "Field `FEN28` writer - Falling edge enabled 28"] +pub type FEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN29` reader - Falling edge enabled 29"] +pub type FEN29_R = crate::BitReader; +#[doc = "Field `FEN29` writer - Falling edge enabled 29"] +pub type FEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN30` reader - Falling edge enabled 30"] +pub type FEN30_R = crate::BitReader; +#[doc = "Field `FEN30` writer - Falling edge enabled 30"] +pub type FEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +#[doc = "Field `FEN31` reader - Falling edge enabled 31"] +pub type FEN31_R = crate::BitReader; +#[doc = "Field `FEN31` writer - Falling edge enabled 31"] +pub type FEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Falling edge enabled 0"] + #[inline(always)] + pub fn fen0(&self) -> FEN0_R { + FEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling edge enabled 1"] + #[inline(always)] + pub fn fen1(&self) -> FEN1_R { + FEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Falling edge enabled 2"] + #[inline(always)] + pub fn fen2(&self) -> FEN2_R { + FEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Falling edge enabled 3"] + #[inline(always)] + pub fn fen3(&self) -> FEN3_R { + FEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling edge enabled 4"] + #[inline(always)] + pub fn fen4(&self) -> FEN4_R { + FEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Falling edge enabled 5"] + #[inline(always)] + pub fn fen5(&self) -> FEN5_R { + FEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Falling edge enabled 6"] + #[inline(always)] + pub fn fen6(&self) -> FEN6_R { + FEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling edge enabled 7"] + #[inline(always)] + pub fn fen7(&self) -> FEN7_R { + FEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Falling edge enabled 8"] + #[inline(always)] + pub fn fen8(&self) -> FEN8_R { + FEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Falling edge enabled 9"] + #[inline(always)] + pub fn fen9(&self) -> FEN9_R { + FEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling edge enabled 10"] + #[inline(always)] + pub fn fen10(&self) -> FEN10_R { + FEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Falling edge enabled 11"] + #[inline(always)] + pub fn fen11(&self) -> FEN11_R { + FEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Falling edge enabled 12"] + #[inline(always)] + pub fn fen12(&self) -> FEN12_R { + FEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Falling edge enabled 13"] + #[inline(always)] + pub fn fen13(&self) -> FEN13_R { + FEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Falling edge enabled 14"] + #[inline(always)] + pub fn fen14(&self) -> FEN14_R { + FEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Falling edge enabled 15"] + #[inline(always)] + pub fn fen15(&self) -> FEN15_R { + FEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Falling edge enabled 16"] + #[inline(always)] + pub fn fen16(&self) -> FEN16_R { + FEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Falling edge enabled 17"] + #[inline(always)] + pub fn fen17(&self) -> FEN17_R { + FEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Falling edge enabled 18"] + #[inline(always)] + pub fn fen18(&self) -> FEN18_R { + FEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Falling edge enabled 19"] + #[inline(always)] + pub fn fen19(&self) -> FEN19_R { + FEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Falling edge enabled 20"] + #[inline(always)] + pub fn fen20(&self) -> FEN20_R { + FEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Falling edge enabled 21"] + #[inline(always)] + pub fn fen21(&self) -> FEN21_R { + FEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Falling edge enabled 22"] + #[inline(always)] + pub fn fen22(&self) -> FEN22_R { + FEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Falling edge enabled 23"] + #[inline(always)] + pub fn fen23(&self) -> FEN23_R { + FEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Falling edge enabled 24"] + #[inline(always)] + pub fn fen24(&self) -> FEN24_R { + FEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Falling edge enabled 25"] + #[inline(always)] + pub fn fen25(&self) -> FEN25_R { + FEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Falling edge enabled 26"] + #[inline(always)] + pub fn fen26(&self) -> FEN26_R { + FEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Falling edge enabled 27"] + #[inline(always)] + pub fn fen27(&self) -> FEN27_R { + FEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Falling edge enabled 28"] + #[inline(always)] + pub fn fen28(&self) -> FEN28_R { + FEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Falling edge enabled 29"] + #[inline(always)] + pub fn fen29(&self) -> FEN29_R { + FEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Falling edge enabled 30"] + #[inline(always)] + pub fn fen30(&self) -> FEN30_R { + FEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Falling edge enabled 31"] + #[inline(always)] + pub fn fen31(&self) -> FEN31_R { + FEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Falling edge enabled 0"] + #[inline(always)] + #[must_use] + pub fn fen0(&mut self) -> FEN0_W<0> { + FEN0_W::new(self) + } + #[doc = "Bit 1 - Falling edge enabled 1"] + #[inline(always)] + #[must_use] + pub fn fen1(&mut self) -> FEN1_W<1> { + FEN1_W::new(self) + } + #[doc = "Bit 2 - Falling edge enabled 2"] + #[inline(always)] + #[must_use] + pub fn fen2(&mut self) -> FEN2_W<2> { + FEN2_W::new(self) + } + #[doc = "Bit 3 - Falling edge enabled 3"] + #[inline(always)] + #[must_use] + pub fn fen3(&mut self) -> FEN3_W<3> { + FEN3_W::new(self) + } + #[doc = "Bit 4 - Falling edge enabled 4"] + #[inline(always)] + #[must_use] + pub fn fen4(&mut self) -> FEN4_W<4> { + FEN4_W::new(self) + } + #[doc = "Bit 5 - Falling edge enabled 5"] + #[inline(always)] + #[must_use] + pub fn fen5(&mut self) -> FEN5_W<5> { + FEN5_W::new(self) + } + #[doc = "Bit 6 - Falling edge enabled 6"] + #[inline(always)] + #[must_use] + pub fn fen6(&mut self) -> FEN6_W<6> { + FEN6_W::new(self) + } + #[doc = "Bit 7 - Falling edge enabled 7"] + #[inline(always)] + #[must_use] + pub fn fen7(&mut self) -> FEN7_W<7> { + FEN7_W::new(self) + } + #[doc = "Bit 8 - Falling edge enabled 8"] + #[inline(always)] + #[must_use] + pub fn fen8(&mut self) -> FEN8_W<8> { + FEN8_W::new(self) + } + #[doc = "Bit 9 - Falling edge enabled 9"] + #[inline(always)] + #[must_use] + pub fn fen9(&mut self) -> FEN9_W<9> { + FEN9_W::new(self) + } + #[doc = "Bit 10 - Falling edge enabled 10"] + #[inline(always)] + #[must_use] + pub fn fen10(&mut self) -> FEN10_W<10> { + FEN10_W::new(self) + } + #[doc = "Bit 11 - Falling edge enabled 11"] + #[inline(always)] + #[must_use] + pub fn fen11(&mut self) -> FEN11_W<11> { + FEN11_W::new(self) + } + #[doc = "Bit 12 - Falling edge enabled 12"] + #[inline(always)] + #[must_use] + pub fn fen12(&mut self) -> FEN12_W<12> { + FEN12_W::new(self) + } + #[doc = "Bit 13 - Falling edge enabled 13"] + #[inline(always)] + #[must_use] + pub fn fen13(&mut self) -> FEN13_W<13> { + FEN13_W::new(self) + } + #[doc = "Bit 14 - Falling edge enabled 14"] + #[inline(always)] + #[must_use] + pub fn fen14(&mut self) -> FEN14_W<14> { + FEN14_W::new(self) + } + #[doc = "Bit 15 - Falling edge enabled 15"] + #[inline(always)] + #[must_use] + pub fn fen15(&mut self) -> FEN15_W<15> { + FEN15_W::new(self) + } + #[doc = "Bit 16 - Falling edge enabled 16"] + #[inline(always)] + #[must_use] + pub fn fen16(&mut self) -> FEN16_W<16> { + FEN16_W::new(self) + } + #[doc = "Bit 17 - Falling edge enabled 17"] + #[inline(always)] + #[must_use] + pub fn fen17(&mut self) -> FEN17_W<17> { + FEN17_W::new(self) + } + #[doc = "Bit 18 - Falling edge enabled 18"] + #[inline(always)] + #[must_use] + pub fn fen18(&mut self) -> FEN18_W<18> { + FEN18_W::new(self) + } + #[doc = "Bit 19 - Falling edge enabled 19"] + #[inline(always)] + #[must_use] + pub fn fen19(&mut self) -> FEN19_W<19> { + FEN19_W::new(self) + } + #[doc = "Bit 20 - Falling edge enabled 20"] + #[inline(always)] + #[must_use] + pub fn fen20(&mut self) -> FEN20_W<20> { + FEN20_W::new(self) + } + #[doc = "Bit 21 - Falling edge enabled 21"] + #[inline(always)] + #[must_use] + pub fn fen21(&mut self) -> FEN21_W<21> { + FEN21_W::new(self) + } + #[doc = "Bit 22 - Falling edge enabled 22"] + #[inline(always)] + #[must_use] + pub fn fen22(&mut self) -> FEN22_W<22> { + FEN22_W::new(self) + } + #[doc = "Bit 23 - Falling edge enabled 23"] + #[inline(always)] + #[must_use] + pub fn fen23(&mut self) -> FEN23_W<23> { + FEN23_W::new(self) + } + #[doc = "Bit 24 - Falling edge enabled 24"] + #[inline(always)] + #[must_use] + pub fn fen24(&mut self) -> FEN24_W<24> { + FEN24_W::new(self) + } + #[doc = "Bit 25 - Falling edge enabled 25"] + #[inline(always)] + #[must_use] + pub fn fen25(&mut self) -> FEN25_W<25> { + FEN25_W::new(self) + } + #[doc = "Bit 26 - Falling edge enabled 26"] + #[inline(always)] + #[must_use] + pub fn fen26(&mut self) -> FEN26_W<26> { + FEN26_W::new(self) + } + #[doc = "Bit 27 - Falling edge enabled 27"] + #[inline(always)] + #[must_use] + pub fn fen27(&mut self) -> FEN27_W<27> { + FEN27_W::new(self) + } + #[doc = "Bit 28 - Falling edge enabled 28"] + #[inline(always)] + #[must_use] + pub fn fen28(&mut self) -> FEN28_W<28> { + FEN28_W::new(self) + } + #[doc = "Bit 29 - Falling edge enabled 29"] + #[inline(always)] + #[must_use] + pub fn fen29(&mut self) -> FEN29_W<29> { + FEN29_W::new(self) + } + #[doc = "Bit 30 - Falling edge enabled 30"] + #[inline(always)] + #[must_use] + pub fn fen30(&mut self) -> FEN30_W<30> { + FEN30_W::new(self) + } + #[doc = "Bit 31 - Falling edge enabled 31"] + #[inline(always)] + #[must_use] + pub fn fen31(&mut self) -> FEN31_W<31> { + FEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen0](index.html) module"] +pub struct GPFEN0_SPEC; +impl crate::RegisterSpec for GPFEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfen0::R](R) reader structure"] +impl crate::Readable for GPFEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfen0::W](W) writer structure"] +impl crate::Writable for GPFEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfen1.rs b/crates/bcm2837-lpa/src/gpio/gpfen1.rs new file mode 100644 index 0000000..4e4498a --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPFEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FEN32` reader - Falling edge enabled 32"] +pub type FEN32_R = crate::BitReader; +#[doc = "Field `FEN32` writer - Falling edge enabled 32"] +pub type FEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN33` reader - Falling edge enabled 33"] +pub type FEN33_R = crate::BitReader; +#[doc = "Field `FEN33` writer - Falling edge enabled 33"] +pub type FEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN34` reader - Falling edge enabled 34"] +pub type FEN34_R = crate::BitReader; +#[doc = "Field `FEN34` writer - Falling edge enabled 34"] +pub type FEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN35` reader - Falling edge enabled 35"] +pub type FEN35_R = crate::BitReader; +#[doc = "Field `FEN35` writer - Falling edge enabled 35"] +pub type FEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN36` reader - Falling edge enabled 36"] +pub type FEN36_R = crate::BitReader; +#[doc = "Field `FEN36` writer - Falling edge enabled 36"] +pub type FEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN37` reader - Falling edge enabled 37"] +pub type FEN37_R = crate::BitReader; +#[doc = "Field `FEN37` writer - Falling edge enabled 37"] +pub type FEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN38` reader - Falling edge enabled 38"] +pub type FEN38_R = crate::BitReader; +#[doc = "Field `FEN38` writer - Falling edge enabled 38"] +pub type FEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN39` reader - Falling edge enabled 39"] +pub type FEN39_R = crate::BitReader; +#[doc = "Field `FEN39` writer - Falling edge enabled 39"] +pub type FEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN40` reader - Falling edge enabled 40"] +pub type FEN40_R = crate::BitReader; +#[doc = "Field `FEN40` writer - Falling edge enabled 40"] +pub type FEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN41` reader - Falling edge enabled 41"] +pub type FEN41_R = crate::BitReader; +#[doc = "Field `FEN41` writer - Falling edge enabled 41"] +pub type FEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN42` reader - Falling edge enabled 42"] +pub type FEN42_R = crate::BitReader; +#[doc = "Field `FEN42` writer - Falling edge enabled 42"] +pub type FEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN43` reader - Falling edge enabled 43"] +pub type FEN43_R = crate::BitReader; +#[doc = "Field `FEN43` writer - Falling edge enabled 43"] +pub type FEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN44` reader - Falling edge enabled 44"] +pub type FEN44_R = crate::BitReader; +#[doc = "Field `FEN44` writer - Falling edge enabled 44"] +pub type FEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN45` reader - Falling edge enabled 45"] +pub type FEN45_R = crate::BitReader; +#[doc = "Field `FEN45` writer - Falling edge enabled 45"] +pub type FEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN46` reader - Falling edge enabled 46"] +pub type FEN46_R = crate::BitReader; +#[doc = "Field `FEN46` writer - Falling edge enabled 46"] +pub type FEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN47` reader - Falling edge enabled 47"] +pub type FEN47_R = crate::BitReader; +#[doc = "Field `FEN47` writer - Falling edge enabled 47"] +pub type FEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN48` reader - Falling edge enabled 48"] +pub type FEN48_R = crate::BitReader; +#[doc = "Field `FEN48` writer - Falling edge enabled 48"] +pub type FEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN49` reader - Falling edge enabled 49"] +pub type FEN49_R = crate::BitReader; +#[doc = "Field `FEN49` writer - Falling edge enabled 49"] +pub type FEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN50` reader - Falling edge enabled 50"] +pub type FEN50_R = crate::BitReader; +#[doc = "Field `FEN50` writer - Falling edge enabled 50"] +pub type FEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN51` reader - Falling edge enabled 51"] +pub type FEN51_R = crate::BitReader; +#[doc = "Field `FEN51` writer - Falling edge enabled 51"] +pub type FEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN52` reader - Falling edge enabled 52"] +pub type FEN52_R = crate::BitReader; +#[doc = "Field `FEN52` writer - Falling edge enabled 52"] +pub type FEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +#[doc = "Field `FEN53` reader - Falling edge enabled 53"] +pub type FEN53_R = crate::BitReader; +#[doc = "Field `FEN53` writer - Falling edge enabled 53"] +pub type FEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Falling edge enabled 32"] + #[inline(always)] + pub fn fen32(&self) -> FEN32_R { + FEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Falling edge enabled 33"] + #[inline(always)] + pub fn fen33(&self) -> FEN33_R { + FEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Falling edge enabled 34"] + #[inline(always)] + pub fn fen34(&self) -> FEN34_R { + FEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Falling edge enabled 35"] + #[inline(always)] + pub fn fen35(&self) -> FEN35_R { + FEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Falling edge enabled 36"] + #[inline(always)] + pub fn fen36(&self) -> FEN36_R { + FEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Falling edge enabled 37"] + #[inline(always)] + pub fn fen37(&self) -> FEN37_R { + FEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Falling edge enabled 38"] + #[inline(always)] + pub fn fen38(&self) -> FEN38_R { + FEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Falling edge enabled 39"] + #[inline(always)] + pub fn fen39(&self) -> FEN39_R { + FEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Falling edge enabled 40"] + #[inline(always)] + pub fn fen40(&self) -> FEN40_R { + FEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Falling edge enabled 41"] + #[inline(always)] + pub fn fen41(&self) -> FEN41_R { + FEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Falling edge enabled 42"] + #[inline(always)] + pub fn fen42(&self) -> FEN42_R { + FEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Falling edge enabled 43"] + #[inline(always)] + pub fn fen43(&self) -> FEN43_R { + FEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Falling edge enabled 44"] + #[inline(always)] + pub fn fen44(&self) -> FEN44_R { + FEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Falling edge enabled 45"] + #[inline(always)] + pub fn fen45(&self) -> FEN45_R { + FEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Falling edge enabled 46"] + #[inline(always)] + pub fn fen46(&self) -> FEN46_R { + FEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Falling edge enabled 47"] + #[inline(always)] + pub fn fen47(&self) -> FEN47_R { + FEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Falling edge enabled 48"] + #[inline(always)] + pub fn fen48(&self) -> FEN48_R { + FEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Falling edge enabled 49"] + #[inline(always)] + pub fn fen49(&self) -> FEN49_R { + FEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Falling edge enabled 50"] + #[inline(always)] + pub fn fen50(&self) -> FEN50_R { + FEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Falling edge enabled 51"] + #[inline(always)] + pub fn fen51(&self) -> FEN51_R { + FEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Falling edge enabled 52"] + #[inline(always)] + pub fn fen52(&self) -> FEN52_R { + FEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Falling edge enabled 53"] + #[inline(always)] + pub fn fen53(&self) -> FEN53_R { + FEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Falling edge enabled 32"] + #[inline(always)] + #[must_use] + pub fn fen32(&mut self) -> FEN32_W<0> { + FEN32_W::new(self) + } + #[doc = "Bit 1 - Falling edge enabled 33"] + #[inline(always)] + #[must_use] + pub fn fen33(&mut self) -> FEN33_W<1> { + FEN33_W::new(self) + } + #[doc = "Bit 2 - Falling edge enabled 34"] + #[inline(always)] + #[must_use] + pub fn fen34(&mut self) -> FEN34_W<2> { + FEN34_W::new(self) + } + #[doc = "Bit 3 - Falling edge enabled 35"] + #[inline(always)] + #[must_use] + pub fn fen35(&mut self) -> FEN35_W<3> { + FEN35_W::new(self) + } + #[doc = "Bit 4 - Falling edge enabled 36"] + #[inline(always)] + #[must_use] + pub fn fen36(&mut self) -> FEN36_W<4> { + FEN36_W::new(self) + } + #[doc = "Bit 5 - Falling edge enabled 37"] + #[inline(always)] + #[must_use] + pub fn fen37(&mut self) -> FEN37_W<5> { + FEN37_W::new(self) + } + #[doc = "Bit 6 - Falling edge enabled 38"] + #[inline(always)] + #[must_use] + pub fn fen38(&mut self) -> FEN38_W<6> { + FEN38_W::new(self) + } + #[doc = "Bit 7 - Falling edge enabled 39"] + #[inline(always)] + #[must_use] + pub fn fen39(&mut self) -> FEN39_W<7> { + FEN39_W::new(self) + } + #[doc = "Bit 8 - Falling edge enabled 40"] + #[inline(always)] + #[must_use] + pub fn fen40(&mut self) -> FEN40_W<8> { + FEN40_W::new(self) + } + #[doc = "Bit 9 - Falling edge enabled 41"] + #[inline(always)] + #[must_use] + pub fn fen41(&mut self) -> FEN41_W<9> { + FEN41_W::new(self) + } + #[doc = "Bit 10 - Falling edge enabled 42"] + #[inline(always)] + #[must_use] + pub fn fen42(&mut self) -> FEN42_W<10> { + FEN42_W::new(self) + } + #[doc = "Bit 11 - Falling edge enabled 43"] + #[inline(always)] + #[must_use] + pub fn fen43(&mut self) -> FEN43_W<11> { + FEN43_W::new(self) + } + #[doc = "Bit 12 - Falling edge enabled 44"] + #[inline(always)] + #[must_use] + pub fn fen44(&mut self) -> FEN44_W<12> { + FEN44_W::new(self) + } + #[doc = "Bit 13 - Falling edge enabled 45"] + #[inline(always)] + #[must_use] + pub fn fen45(&mut self) -> FEN45_W<13> { + FEN45_W::new(self) + } + #[doc = "Bit 14 - Falling edge enabled 46"] + #[inline(always)] + #[must_use] + pub fn fen46(&mut self) -> FEN46_W<14> { + FEN46_W::new(self) + } + #[doc = "Bit 15 - Falling edge enabled 47"] + #[inline(always)] + #[must_use] + pub fn fen47(&mut self) -> FEN47_W<15> { + FEN47_W::new(self) + } + #[doc = "Bit 16 - Falling edge enabled 48"] + #[inline(always)] + #[must_use] + pub fn fen48(&mut self) -> FEN48_W<16> { + FEN48_W::new(self) + } + #[doc = "Bit 17 - Falling edge enabled 49"] + #[inline(always)] + #[must_use] + pub fn fen49(&mut self) -> FEN49_W<17> { + FEN49_W::new(self) + } + #[doc = "Bit 18 - Falling edge enabled 50"] + #[inline(always)] + #[must_use] + pub fn fen50(&mut self) -> FEN50_W<18> { + FEN50_W::new(self) + } + #[doc = "Bit 19 - Falling edge enabled 51"] + #[inline(always)] + #[must_use] + pub fn fen51(&mut self) -> FEN51_W<19> { + FEN51_W::new(self) + } + #[doc = "Bit 20 - Falling edge enabled 52"] + #[inline(always)] + #[must_use] + pub fn fen52(&mut self) -> FEN52_W<20> { + FEN52_W::new(self) + } + #[doc = "Bit 21 - Falling edge enabled 53"] + #[inline(always)] + #[must_use] + pub fn fen53(&mut self) -> FEN53_W<21> { + FEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen1](index.html) module"] +pub struct GPFEN1_SPEC; +impl crate::RegisterSpec for GPFEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfen1::R](R) reader structure"] +impl crate::Readable for GPFEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfen1::W](W) writer structure"] +impl crate::Writable for GPFEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel0.rs b/crates/bcm2837-lpa/src/gpio/gpfsel0.rs new file mode 100644 index 0000000..4109144 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfsel0.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL0` reader - Function Select 0"] +pub type FSEL0_R = crate::FieldReader; +#[doc = "Function Select 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL0_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA0"] + SDA0 = 4, + #[doc = "5: Pin is connected to SA5"] + SA5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL0_A) -> Self { + variant as _ + } +} +impl FSEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL0_A { + match self.bits { + 0 => FSEL0_A::INPUT, + 1 => FSEL0_A::OUTPUT, + 4 => FSEL0_A::SDA0, + 5 => FSEL0_A::SA5, + 6 => FSEL0_A::RESERVED2, + 7 => FSEL0_A::RESERVED3, + 3 => FSEL0_A::RESERVED4, + 2 => FSEL0_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL0_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL0_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL0_A::SDA0 + } + #[doc = "Checks if the value of the field is `SA5`"] + #[inline(always)] + pub fn is_sa5(&self) -> bool { + *self == FSEL0_A::SA5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL0_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL0_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL0_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL0_A::RESERVED5 + } +} +#[doc = "Field `FSEL0` writer - Function Select 0"] +pub type FSEL0_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL0_A, 3, O>; +impl<'a, const O: u8> FSEL0_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL0_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL0_A::OUTPUT) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL0_A::SDA0) + } + #[doc = "Pin is connected to SA5"] + #[inline(always)] + pub fn sa5(self) -> &'a mut W { + self.variant(FSEL0_A::SA5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL0_A::RESERVED5) + } +} +#[doc = "Field `FSEL1` reader - Function Select 1"] +pub type FSEL1_R = crate::FieldReader; +#[doc = "Function Select 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL1_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL0"] + SCL0 = 4, + #[doc = "5: Pin is connected to SA4"] + SA4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL1_A) -> Self { + variant as _ + } +} +impl FSEL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL1_A { + match self.bits { + 0 => FSEL1_A::INPUT, + 1 => FSEL1_A::OUTPUT, + 4 => FSEL1_A::SCL0, + 5 => FSEL1_A::SA4, + 6 => FSEL1_A::RESERVED2, + 7 => FSEL1_A::RESERVED3, + 3 => FSEL1_A::RESERVED4, + 2 => FSEL1_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL1_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL1_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL1_A::SCL0 + } + #[doc = "Checks if the value of the field is `SA4`"] + #[inline(always)] + pub fn is_sa4(&self) -> bool { + *self == FSEL1_A::SA4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL1_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL1_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL1_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL1_A::RESERVED5 + } +} +#[doc = "Field `FSEL1` writer - Function Select 1"] +pub type FSEL1_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL1_A, 3, O>; +impl<'a, const O: u8> FSEL1_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL1_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL1_A::OUTPUT) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL1_A::SCL0) + } + #[doc = "Pin is connected to SA4"] + #[inline(always)] + pub fn sa4(self) -> &'a mut W { + self.variant(FSEL1_A::SA4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL1_A::RESERVED5) + } +} +#[doc = "Field `FSEL2` reader - Function Select 2"] +pub type FSEL2_R = crate::FieldReader; +#[doc = "Function Select 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL2_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA1"] + SDA1 = 4, + #[doc = "5: Pin is connected to SA3"] + SA3 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL2_A) -> Self { + variant as _ + } +} +impl FSEL2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL2_A { + match self.bits { + 0 => FSEL2_A::INPUT, + 1 => FSEL2_A::OUTPUT, + 4 => FSEL2_A::SDA1, + 5 => FSEL2_A::SA3, + 6 => FSEL2_A::RESERVED2, + 7 => FSEL2_A::RESERVED3, + 3 => FSEL2_A::RESERVED4, + 2 => FSEL2_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL2_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL2_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA1`"] + #[inline(always)] + pub fn is_sda1(&self) -> bool { + *self == FSEL2_A::SDA1 + } + #[doc = "Checks if the value of the field is `SA3`"] + #[inline(always)] + pub fn is_sa3(&self) -> bool { + *self == FSEL2_A::SA3 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL2_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL2_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL2_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL2_A::RESERVED5 + } +} +#[doc = "Field `FSEL2` writer - Function Select 2"] +pub type FSEL2_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL2_A, 3, O>; +impl<'a, const O: u8> FSEL2_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL2_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL2_A::OUTPUT) + } + #[doc = "Pin is connected to SDA1"] + #[inline(always)] + pub fn sda1(self) -> &'a mut W { + self.variant(FSEL2_A::SDA1) + } + #[doc = "Pin is connected to SA3"] + #[inline(always)] + pub fn sa3(self) -> &'a mut W { + self.variant(FSEL2_A::SA3) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL2_A::RESERVED5) + } +} +#[doc = "Field `FSEL3` reader - Function Select 3"] +pub type FSEL3_R = crate::FieldReader; +#[doc = "Function Select 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL3_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL1"] + SCL1 = 4, + #[doc = "5: Pin is connected to SA2"] + SA2 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL3_A) -> Self { + variant as _ + } +} +impl FSEL3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL3_A { + match self.bits { + 0 => FSEL3_A::INPUT, + 1 => FSEL3_A::OUTPUT, + 4 => FSEL3_A::SCL1, + 5 => FSEL3_A::SA2, + 6 => FSEL3_A::RESERVED2, + 7 => FSEL3_A::RESERVED3, + 3 => FSEL3_A::RESERVED4, + 2 => FSEL3_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL3_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL3_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL1`"] + #[inline(always)] + pub fn is_scl1(&self) -> bool { + *self == FSEL3_A::SCL1 + } + #[doc = "Checks if the value of the field is `SA2`"] + #[inline(always)] + pub fn is_sa2(&self) -> bool { + *self == FSEL3_A::SA2 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL3_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL3_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL3_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL3_A::RESERVED5 + } +} +#[doc = "Field `FSEL3` writer - Function Select 3"] +pub type FSEL3_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL3_A, 3, O>; +impl<'a, const O: u8> FSEL3_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL3_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL3_A::OUTPUT) + } + #[doc = "Pin is connected to SCL1"] + #[inline(always)] + pub fn scl1(self) -> &'a mut W { + self.variant(FSEL3_A::SCL1) + } + #[doc = "Pin is connected to SA2"] + #[inline(always)] + pub fn sa2(self) -> &'a mut W { + self.variant(FSEL3_A::SA2) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL3_A::RESERVED5) + } +} +#[doc = "Field `FSEL4` reader - Function Select 4"] +pub type FSEL4_R = crate::FieldReader; +#[doc = "Function Select 4"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL4_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SA1"] + SA1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TDI"] + ARM_TDI = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL4_A) -> Self { + variant as _ + } +} +impl FSEL4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL4_A { + match self.bits { + 0 => FSEL4_A::INPUT, + 1 => FSEL4_A::OUTPUT, + 4 => FSEL4_A::GPCLK0, + 5 => FSEL4_A::SA1, + 6 => FSEL4_A::RESERVED2, + 7 => FSEL4_A::RESERVED3, + 3 => FSEL4_A::RESERVED4, + 2 => FSEL4_A::ARM_TDI, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL4_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL4_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL4_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SA1`"] + #[inline(always)] + pub fn is_sa1(&self) -> bool { + *self == FSEL4_A::SA1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL4_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL4_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL4_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[inline(always)] + pub fn is_arm_tdi(&self) -> bool { + *self == FSEL4_A::ARM_TDI + } +} +#[doc = "Field `FSEL4` writer - Function Select 4"] +pub type FSEL4_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL4_A, 3, O>; +impl<'a, const O: u8> FSEL4_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL4_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL4_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL4_A::GPCLK0) + } + #[doc = "Pin is connected to SA1"] + #[inline(always)] + pub fn sa1(self) -> &'a mut W { + self.variant(FSEL4_A::SA1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL4_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL4_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL4_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TDI"] + #[inline(always)] + pub fn arm_tdi(self) -> &'a mut W { + self.variant(FSEL4_A::ARM_TDI) + } +} +#[doc = "Field `FSEL5` reader - Function Select 5"] +pub type FSEL5_R = crate::FieldReader; +#[doc = "Function Select 5"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL5_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SA0"] + SA0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TDO"] + ARM_TDO = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL5_A) -> Self { + variant as _ + } +} +impl FSEL5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL5_A { + match self.bits { + 0 => FSEL5_A::INPUT, + 1 => FSEL5_A::OUTPUT, + 4 => FSEL5_A::GPCLK1, + 5 => FSEL5_A::SA0, + 6 => FSEL5_A::RESERVED2, + 7 => FSEL5_A::RESERVED3, + 3 => FSEL5_A::RESERVED4, + 2 => FSEL5_A::ARM_TDO, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL5_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL5_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL5_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SA0`"] + #[inline(always)] + pub fn is_sa0(&self) -> bool { + *self == FSEL5_A::SA0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL5_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL5_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL5_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[inline(always)] + pub fn is_arm_tdo(&self) -> bool { + *self == FSEL5_A::ARM_TDO + } +} +#[doc = "Field `FSEL5` writer - Function Select 5"] +pub type FSEL5_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL5_A, 3, O>; +impl<'a, const O: u8> FSEL5_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL5_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL5_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL5_A::GPCLK1) + } + #[doc = "Pin is connected to SA0"] + #[inline(always)] + pub fn sa0(self) -> &'a mut W { + self.variant(FSEL5_A::SA0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL5_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL5_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL5_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TDO"] + #[inline(always)] + pub fn arm_tdo(self) -> &'a mut W { + self.variant(FSEL5_A::ARM_TDO) + } +} +#[doc = "Field `FSEL6` reader - Function Select 6"] +pub type FSEL6_R = crate::FieldReader; +#[doc = "Function Select 6"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL6_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK2"] + GPCLK2 = 4, + #[doc = "5: Pin is connected to SOE_N"] + SOE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_RTCK"] + ARM_RTCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL6_A) -> Self { + variant as _ + } +} +impl FSEL6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL6_A { + match self.bits { + 0 => FSEL6_A::INPUT, + 1 => FSEL6_A::OUTPUT, + 4 => FSEL6_A::GPCLK2, + 5 => FSEL6_A::SOE_N, + 6 => FSEL6_A::RESERVED2, + 7 => FSEL6_A::RESERVED3, + 3 => FSEL6_A::RESERVED4, + 2 => FSEL6_A::ARM_RTCK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL6_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL6_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK2`"] + #[inline(always)] + pub fn is_gpclk2(&self) -> bool { + *self == FSEL6_A::GPCLK2 + } + #[doc = "Checks if the value of the field is `SOE_N`"] + #[inline(always)] + pub fn is_soe_n(&self) -> bool { + *self == FSEL6_A::SOE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL6_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL6_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL6_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[inline(always)] + pub fn is_arm_rtck(&self) -> bool { + *self == FSEL6_A::ARM_RTCK + } +} +#[doc = "Field `FSEL6` writer - Function Select 6"] +pub type FSEL6_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL6_A, 3, O>; +impl<'a, const O: u8> FSEL6_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL6_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL6_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK2"] + #[inline(always)] + pub fn gpclk2(self) -> &'a mut W { + self.variant(FSEL6_A::GPCLK2) + } + #[doc = "Pin is connected to SOE_N"] + #[inline(always)] + pub fn soe_n(self) -> &'a mut W { + self.variant(FSEL6_A::SOE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL6_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL6_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL6_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_RTCK"] + #[inline(always)] + pub fn arm_rtck(self) -> &'a mut W { + self.variant(FSEL6_A::ARM_RTCK) + } +} +#[doc = "Field `FSEL7` reader - Function Select 7"] +pub type FSEL7_R = crate::FieldReader; +#[doc = "Function Select 7"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL7_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE1_N"] + SPI0_CE1_N = 4, + #[doc = "5: Pin is connected to SWE_N"] + SWE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL7_A) -> Self { + variant as _ + } +} +impl FSEL7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL7_A { + match self.bits { + 0 => FSEL7_A::INPUT, + 1 => FSEL7_A::OUTPUT, + 4 => FSEL7_A::SPI0_CE1_N, + 5 => FSEL7_A::SWE_N, + 6 => FSEL7_A::RESERVED2, + 7 => FSEL7_A::RESERVED3, + 3 => FSEL7_A::RESERVED4, + 2 => FSEL7_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL7_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL7_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[inline(always)] + pub fn is_spi0_ce1_n(&self) -> bool { + *self == FSEL7_A::SPI0_CE1_N + } + #[doc = "Checks if the value of the field is `SWE_N`"] + #[inline(always)] + pub fn is_swe_n(&self) -> bool { + *self == FSEL7_A::SWE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL7_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL7_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL7_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL7_A::RESERVED5 + } +} +#[doc = "Field `FSEL7` writer - Function Select 7"] +pub type FSEL7_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL7_A, 3, O>; +impl<'a, const O: u8> FSEL7_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL7_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL7_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE1_N"] + #[inline(always)] + pub fn spi0_ce1_n(self) -> &'a mut W { + self.variant(FSEL7_A::SPI0_CE1_N) + } + #[doc = "Pin is connected to SWE_N"] + #[inline(always)] + pub fn swe_n(self) -> &'a mut W { + self.variant(FSEL7_A::SWE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL7_A::RESERVED5) + } +} +#[doc = "Field `FSEL8` reader - Function Select 8"] +pub type FSEL8_R = crate::FieldReader; +#[doc = "Function Select 8"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL8_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE0_N"] + SPI0_CE0_N = 4, + #[doc = "5: Pin is connected to SD0"] + SD0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL8_A) -> Self { + variant as _ + } +} +impl FSEL8_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL8_A { + match self.bits { + 0 => FSEL8_A::INPUT, + 1 => FSEL8_A::OUTPUT, + 4 => FSEL8_A::SPI0_CE0_N, + 5 => FSEL8_A::SD0, + 6 => FSEL8_A::RESERVED2, + 7 => FSEL8_A::RESERVED3, + 3 => FSEL8_A::RESERVED4, + 2 => FSEL8_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL8_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL8_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[inline(always)] + pub fn is_spi0_ce0_n(&self) -> bool { + *self == FSEL8_A::SPI0_CE0_N + } + #[doc = "Checks if the value of the field is `SD0`"] + #[inline(always)] + pub fn is_sd0(&self) -> bool { + *self == FSEL8_A::SD0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL8_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL8_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL8_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL8_A::RESERVED5 + } +} +#[doc = "Field `FSEL8` writer - Function Select 8"] +pub type FSEL8_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL8_A, 3, O>; +impl<'a, const O: u8> FSEL8_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL8_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL8_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE0_N"] + #[inline(always)] + pub fn spi0_ce0_n(self) -> &'a mut W { + self.variant(FSEL8_A::SPI0_CE0_N) + } + #[doc = "Pin is connected to SD0"] + #[inline(always)] + pub fn sd0(self) -> &'a mut W { + self.variant(FSEL8_A::SD0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL8_A::RESERVED5) + } +} +#[doc = "Field `FSEL9` reader - Function Select 9"] +pub type FSEL9_R = crate::FieldReader; +#[doc = "Function Select 9"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL9_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MISO"] + SPI0_MISO = 4, + #[doc = "5: Pin is connected to SD1"] + SD1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL9_A) -> Self { + variant as _ + } +} +impl FSEL9_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL9_A { + match self.bits { + 0 => FSEL9_A::INPUT, + 1 => FSEL9_A::OUTPUT, + 4 => FSEL9_A::SPI0_MISO, + 5 => FSEL9_A::SD1, + 6 => FSEL9_A::RESERVED2, + 7 => FSEL9_A::RESERVED3, + 3 => FSEL9_A::RESERVED4, + 2 => FSEL9_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL9_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL9_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[inline(always)] + pub fn is_spi0_miso(&self) -> bool { + *self == FSEL9_A::SPI0_MISO + } + #[doc = "Checks if the value of the field is `SD1`"] + #[inline(always)] + pub fn is_sd1(&self) -> bool { + *self == FSEL9_A::SD1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL9_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL9_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL9_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL9_A::RESERVED5 + } +} +#[doc = "Field `FSEL9` writer - Function Select 9"] +pub type FSEL9_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL9_A, 3, O>; +impl<'a, const O: u8> FSEL9_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL9_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL9_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MISO"] + #[inline(always)] + pub fn spi0_miso(self) -> &'a mut W { + self.variant(FSEL9_A::SPI0_MISO) + } + #[doc = "Pin is connected to SD1"] + #[inline(always)] + pub fn sd1(self) -> &'a mut W { + self.variant(FSEL9_A::SD1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL9_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 0"] + #[inline(always)] + pub fn fsel0(&self) -> FSEL0_R { + FSEL0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 1"] + #[inline(always)] + pub fn fsel1(&self) -> FSEL1_R { + FSEL1_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 2"] + #[inline(always)] + pub fn fsel2(&self) -> FSEL2_R { + FSEL2_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 3"] + #[inline(always)] + pub fn fsel3(&self) -> FSEL3_R { + FSEL3_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 4"] + #[inline(always)] + pub fn fsel4(&self) -> FSEL4_R { + FSEL4_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 5"] + #[inline(always)] + pub fn fsel5(&self) -> FSEL5_R { + FSEL5_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 6"] + #[inline(always)] + pub fn fsel6(&self) -> FSEL6_R { + FSEL6_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 7"] + #[inline(always)] + pub fn fsel7(&self) -> FSEL7_R { + FSEL7_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 8"] + #[inline(always)] + pub fn fsel8(&self) -> FSEL8_R { + FSEL8_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 9"] + #[inline(always)] + pub fn fsel9(&self) -> FSEL9_R { + FSEL9_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 0"] + #[inline(always)] + #[must_use] + pub fn fsel0(&mut self) -> FSEL0_W<0> { + FSEL0_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 1"] + #[inline(always)] + #[must_use] + pub fn fsel1(&mut self) -> FSEL1_W<3> { + FSEL1_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 2"] + #[inline(always)] + #[must_use] + pub fn fsel2(&mut self) -> FSEL2_W<6> { + FSEL2_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 3"] + #[inline(always)] + #[must_use] + pub fn fsel3(&mut self) -> FSEL3_W<9> { + FSEL3_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 4"] + #[inline(always)] + #[must_use] + pub fn fsel4(&mut self) -> FSEL4_W<12> { + FSEL4_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 5"] + #[inline(always)] + #[must_use] + pub fn fsel5(&mut self) -> FSEL5_W<15> { + FSEL5_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 6"] + #[inline(always)] + #[must_use] + pub fn fsel6(&mut self) -> FSEL6_W<18> { + FSEL6_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 7"] + #[inline(always)] + #[must_use] + pub fn fsel7(&mut self) -> FSEL7_W<21> { + FSEL7_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 8"] + #[inline(always)] + #[must_use] + pub fn fsel8(&mut self) -> FSEL8_W<24> { + FSEL8_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 9"] + #[inline(always)] + #[must_use] + pub fn fsel9(&mut self) -> FSEL9_W<27> { + FSEL9_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel0](index.html) module"] +pub struct GPFSEL0_SPEC; +impl crate::RegisterSpec for GPFSEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel0::R](R) reader structure"] +impl crate::Readable for GPFSEL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel0::W](W) writer structure"] +impl crate::Writable for GPFSEL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel1.rs b/crates/bcm2837-lpa/src/gpio/gpfsel1.rs new file mode 100644 index 0000000..170dd75 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfsel1.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL10` reader - Function Select 10"] +pub type FSEL10_R = crate::FieldReader; +#[doc = "Function Select 10"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL10_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MOSI"] + SPI0_MOSI = 4, + #[doc = "5: Pin is connected to SD2"] + SD2 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL10_A) -> Self { + variant as _ + } +} +impl FSEL10_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL10_A { + match self.bits { + 0 => FSEL10_A::INPUT, + 1 => FSEL10_A::OUTPUT, + 4 => FSEL10_A::SPI0_MOSI, + 5 => FSEL10_A::SD2, + 6 => FSEL10_A::RESERVED2, + 7 => FSEL10_A::RESERVED3, + 3 => FSEL10_A::RESERVED4, + 2 => FSEL10_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL10_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL10_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[inline(always)] + pub fn is_spi0_mosi(&self) -> bool { + *self == FSEL10_A::SPI0_MOSI + } + #[doc = "Checks if the value of the field is `SD2`"] + #[inline(always)] + pub fn is_sd2(&self) -> bool { + *self == FSEL10_A::SD2 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL10_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL10_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL10_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL10_A::RESERVED5 + } +} +#[doc = "Field `FSEL10` writer - Function Select 10"] +pub type FSEL10_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL10_A, 3, O>; +impl<'a, const O: u8> FSEL10_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL10_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL10_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MOSI"] + #[inline(always)] + pub fn spi0_mosi(self) -> &'a mut W { + self.variant(FSEL10_A::SPI0_MOSI) + } + #[doc = "Pin is connected to SD2"] + #[inline(always)] + pub fn sd2(self) -> &'a mut W { + self.variant(FSEL10_A::SD2) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL10_A::RESERVED5) + } +} +#[doc = "Field `FSEL11` reader - Function Select 11"] +pub type FSEL11_R = crate::FieldReader; +#[doc = "Function Select 11"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL11_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_SCLK"] + SPI0_SCLK = 4, + #[doc = "5: Pin is connected to SD3"] + SD3 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL11_A) -> Self { + variant as _ + } +} +impl FSEL11_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL11_A { + match self.bits { + 0 => FSEL11_A::INPUT, + 1 => FSEL11_A::OUTPUT, + 4 => FSEL11_A::SPI0_SCLK, + 5 => FSEL11_A::SD3, + 6 => FSEL11_A::RESERVED2, + 7 => FSEL11_A::RESERVED3, + 3 => FSEL11_A::RESERVED4, + 2 => FSEL11_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL11_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL11_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[inline(always)] + pub fn is_spi0_sclk(&self) -> bool { + *self == FSEL11_A::SPI0_SCLK + } + #[doc = "Checks if the value of the field is `SD3`"] + #[inline(always)] + pub fn is_sd3(&self) -> bool { + *self == FSEL11_A::SD3 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL11_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL11_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL11_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL11_A::RESERVED5 + } +} +#[doc = "Field `FSEL11` writer - Function Select 11"] +pub type FSEL11_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL11_A, 3, O>; +impl<'a, const O: u8> FSEL11_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL11_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL11_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_SCLK"] + #[inline(always)] + pub fn spi0_sclk(self) -> &'a mut W { + self.variant(FSEL11_A::SPI0_SCLK) + } + #[doc = "Pin is connected to SD3"] + #[inline(always)] + pub fn sd3(self) -> &'a mut W { + self.variant(FSEL11_A::SD3) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL11_A::RESERVED5) + } +} +#[doc = "Field `FSEL12` reader - Function Select 12"] +pub type FSEL12_R = crate::FieldReader; +#[doc = "Function Select 12"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL12_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_0"] + PWM0_0 = 4, + #[doc = "5: Pin is connected to SD4"] + SD4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TMS"] + ARM_TMS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL12_A) -> Self { + variant as _ + } +} +impl FSEL12_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL12_A { + match self.bits { + 0 => FSEL12_A::INPUT, + 1 => FSEL12_A::OUTPUT, + 4 => FSEL12_A::PWM0_0, + 5 => FSEL12_A::SD4, + 6 => FSEL12_A::RESERVED2, + 7 => FSEL12_A::RESERVED3, + 3 => FSEL12_A::RESERVED4, + 2 => FSEL12_A::ARM_TMS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL12_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL12_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL12_A::PWM0_0 + } + #[doc = "Checks if the value of the field is `SD4`"] + #[inline(always)] + pub fn is_sd4(&self) -> bool { + *self == FSEL12_A::SD4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL12_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL12_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL12_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[inline(always)] + pub fn is_arm_tms(&self) -> bool { + *self == FSEL12_A::ARM_TMS + } +} +#[doc = "Field `FSEL12` writer - Function Select 12"] +pub type FSEL12_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL12_A, 3, O>; +impl<'a, const O: u8> FSEL12_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL12_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL12_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL12_A::PWM0_0) + } + #[doc = "Pin is connected to SD4"] + #[inline(always)] + pub fn sd4(self) -> &'a mut W { + self.variant(FSEL12_A::SD4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL12_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL12_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL12_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TMS"] + #[inline(always)] + pub fn arm_tms(self) -> &'a mut W { + self.variant(FSEL12_A::ARM_TMS) + } +} +#[doc = "Field `FSEL13` reader - Function Select 13"] +pub type FSEL13_R = crate::FieldReader; +#[doc = "Function Select 13"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL13_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SD5"] + SD5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to ARM_TCK"] + ARM_TCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL13_A) -> Self { + variant as _ + } +} +impl FSEL13_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL13_A { + match self.bits { + 0 => FSEL13_A::INPUT, + 1 => FSEL13_A::OUTPUT, + 4 => FSEL13_A::PWM0_1, + 5 => FSEL13_A::SD5, + 6 => FSEL13_A::RESERVED2, + 7 => FSEL13_A::RESERVED3, + 3 => FSEL13_A::RESERVED4, + 2 => FSEL13_A::ARM_TCK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL13_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL13_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL13_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SD5`"] + #[inline(always)] + pub fn is_sd5(&self) -> bool { + *self == FSEL13_A::SD5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL13_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL13_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL13_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[inline(always)] + pub fn is_arm_tck(&self) -> bool { + *self == FSEL13_A::ARM_TCK + } +} +#[doc = "Field `FSEL13` writer - Function Select 13"] +pub type FSEL13_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL13_A, 3, O>; +impl<'a, const O: u8> FSEL13_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL13_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL13_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL13_A::PWM0_1) + } + #[doc = "Pin is connected to SD5"] + #[inline(always)] + pub fn sd5(self) -> &'a mut W { + self.variant(FSEL13_A::SD5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL13_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL13_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL13_A::RESERVED4) + } + #[doc = "Pin is connected to ARM_TCK"] + #[inline(always)] + pub fn arm_tck(self) -> &'a mut W { + self.variant(FSEL13_A::ARM_TCK) + } +} +#[doc = "Field `FSEL14` reader - Function Select 14"] +pub type FSEL14_R = crate::FieldReader; +#[doc = "Function Select 14"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL14_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to TXD0"] + TXD0 = 4, + #[doc = "5: Pin is connected to SD6"] + SD6 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL14_A) -> Self { + variant as _ + } +} +impl FSEL14_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL14_A { + match self.bits { + 0 => FSEL14_A::INPUT, + 1 => FSEL14_A::OUTPUT, + 4 => FSEL14_A::TXD0, + 5 => FSEL14_A::SD6, + 6 => FSEL14_A::RESERVED2, + 7 => FSEL14_A::RESERVED3, + 3 => FSEL14_A::RESERVED4, + 2 => FSEL14_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL14_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL14_A::OUTPUT + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL14_A::TXD0 + } + #[doc = "Checks if the value of the field is `SD6`"] + #[inline(always)] + pub fn is_sd6(&self) -> bool { + *self == FSEL14_A::SD6 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL14_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL14_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL14_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL14_A::TXD1 + } +} +#[doc = "Field `FSEL14` writer - Function Select 14"] +pub type FSEL14_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL14_A, 3, O>; +impl<'a, const O: u8> FSEL14_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL14_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL14_A::OUTPUT) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL14_A::TXD0) + } + #[doc = "Pin is connected to SD6"] + #[inline(always)] + pub fn sd6(self) -> &'a mut W { + self.variant(FSEL14_A::SD6) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL14_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL14_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL14_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL14_A::TXD1) + } +} +#[doc = "Field `FSEL15` reader - Function Select 15"] +pub type FSEL15_R = crate::FieldReader; +#[doc = "Function Select 15"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL15_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to RXD0"] + RXD0 = 4, + #[doc = "5: Pin is connected to SD7"] + SD7 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL15_A) -> Self { + variant as _ + } +} +impl FSEL15_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL15_A { + match self.bits { + 0 => FSEL15_A::INPUT, + 1 => FSEL15_A::OUTPUT, + 4 => FSEL15_A::RXD0, + 5 => FSEL15_A::SD7, + 6 => FSEL15_A::RESERVED2, + 7 => FSEL15_A::RESERVED3, + 3 => FSEL15_A::RESERVED4, + 2 => FSEL15_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL15_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL15_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL15_A::RXD0 + } + #[doc = "Checks if the value of the field is `SD7`"] + #[inline(always)] + pub fn is_sd7(&self) -> bool { + *self == FSEL15_A::SD7 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL15_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL15_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL15_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL15_A::RXD1 + } +} +#[doc = "Field `FSEL15` writer - Function Select 15"] +pub type FSEL15_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL15_A, 3, O>; +impl<'a, const O: u8> FSEL15_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL15_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL15_A::OUTPUT) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL15_A::RXD0) + } + #[doc = "Pin is connected to SD7"] + #[inline(always)] + pub fn sd7(self) -> &'a mut W { + self.variant(FSEL15_A::SD7) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL15_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL15_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL15_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL15_A::RXD1) + } +} +#[doc = "Field `FSEL16` reader - Function Select 16"] +pub type FSEL16_R = crate::FieldReader; +#[doc = "Function Select 16"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL16_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD8"] + SD8 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to CTS0"] + CTS0 = 7, + #[doc = "3: Pin is connected to SPI1_CE2_N"] + SPI1_CE2_N = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL16_A) -> Self { + variant as _ + } +} +impl FSEL16_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL16_A { + match self.bits { + 0 => FSEL16_A::INPUT, + 1 => FSEL16_A::OUTPUT, + 4 => FSEL16_A::RESERVED0, + 5 => FSEL16_A::SD8, + 6 => FSEL16_A::RESERVED2, + 7 => FSEL16_A::CTS0, + 3 => FSEL16_A::SPI1_CE2_N, + 2 => FSEL16_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL16_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL16_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL16_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD8`"] + #[inline(always)] + pub fn is_sd8(&self) -> bool { + *self == FSEL16_A::SD8 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL16_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL16_A::CTS0 + } + #[doc = "Checks if the value of the field is `SPI1_CE2_N`"] + #[inline(always)] + pub fn is_spi1_ce2_n(&self) -> bool { + *self == FSEL16_A::SPI1_CE2_N + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL16_A::CTS1 + } +} +#[doc = "Field `FSEL16` writer - Function Select 16"] +pub type FSEL16_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL16_A, 3, O>; +impl<'a, const O: u8> FSEL16_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL16_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL16_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL16_A::RESERVED0) + } + #[doc = "Pin is connected to SD8"] + #[inline(always)] + pub fn sd8(self) -> &'a mut W { + self.variant(FSEL16_A::SD8) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL16_A::RESERVED2) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL16_A::CTS0) + } + #[doc = "Pin is connected to SPI1_CE2_N"] + #[inline(always)] + pub fn spi1_ce2_n(self) -> &'a mut W { + self.variant(FSEL16_A::SPI1_CE2_N) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL16_A::CTS1) + } +} +#[doc = "Field `FSEL17` reader - Function Select 17"] +pub type FSEL17_R = crate::FieldReader; +#[doc = "Function Select 17"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL17_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD9"] + SD9 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to RTS0"] + RTS0 = 7, + #[doc = "3: Pin is connected to SPI1_CE1_N"] + SPI1_CE1_N = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL17_A) -> Self { + variant as _ + } +} +impl FSEL17_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL17_A { + match self.bits { + 0 => FSEL17_A::INPUT, + 1 => FSEL17_A::OUTPUT, + 4 => FSEL17_A::RESERVED0, + 5 => FSEL17_A::SD9, + 6 => FSEL17_A::RESERVED2, + 7 => FSEL17_A::RTS0, + 3 => FSEL17_A::SPI1_CE1_N, + 2 => FSEL17_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL17_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL17_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL17_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD9`"] + #[inline(always)] + pub fn is_sd9(&self) -> bool { + *self == FSEL17_A::SD9 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL17_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL17_A::RTS0 + } + #[doc = "Checks if the value of the field is `SPI1_CE1_N`"] + #[inline(always)] + pub fn is_spi1_ce1_n(&self) -> bool { + *self == FSEL17_A::SPI1_CE1_N + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL17_A::RTS1 + } +} +#[doc = "Field `FSEL17` writer - Function Select 17"] +pub type FSEL17_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL17_A, 3, O>; +impl<'a, const O: u8> FSEL17_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL17_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL17_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL17_A::RESERVED0) + } + #[doc = "Pin is connected to SD9"] + #[inline(always)] + pub fn sd9(self) -> &'a mut W { + self.variant(FSEL17_A::SD9) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL17_A::RESERVED2) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL17_A::RTS0) + } + #[doc = "Pin is connected to SPI1_CE1_N"] + #[inline(always)] + pub fn spi1_ce1_n(self) -> &'a mut W { + self.variant(FSEL17_A::SPI1_CE1_N) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL17_A::RTS1) + } +} +#[doc = "Field `FSEL18` reader - Function Select 18"] +pub type FSEL18_R = crate::FieldReader; +#[doc = "Function Select 18"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL18_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_CLK"] + PCM_CLK = 4, + #[doc = "5: Pin is connected to SD10"] + SD10 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_CE0_N"] + SPI1_CE0_N = 3, + #[doc = "2: Pin is connected to PWM0_0"] + PWM0_0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL18_A) -> Self { + variant as _ + } +} +impl FSEL18_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL18_A { + match self.bits { + 0 => FSEL18_A::INPUT, + 1 => FSEL18_A::OUTPUT, + 4 => FSEL18_A::PCM_CLK, + 5 => FSEL18_A::SD10, + 6 => FSEL18_A::RESERVED2, + 7 => FSEL18_A::RESERVED3, + 3 => FSEL18_A::SPI1_CE0_N, + 2 => FSEL18_A::PWM0_0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL18_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL18_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[inline(always)] + pub fn is_pcm_clk(&self) -> bool { + *self == FSEL18_A::PCM_CLK + } + #[doc = "Checks if the value of the field is `SD10`"] + #[inline(always)] + pub fn is_sd10(&self) -> bool { + *self == FSEL18_A::SD10 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL18_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL18_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_CE0_N`"] + #[inline(always)] + pub fn is_spi1_ce0_n(&self) -> bool { + *self == FSEL18_A::SPI1_CE0_N + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL18_A::PWM0_0 + } +} +#[doc = "Field `FSEL18` writer - Function Select 18"] +pub type FSEL18_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL18_A, 3, O>; +impl<'a, const O: u8> FSEL18_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL18_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL18_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_CLK"] + #[inline(always)] + pub fn pcm_clk(self) -> &'a mut W { + self.variant(FSEL18_A::PCM_CLK) + } + #[doc = "Pin is connected to SD10"] + #[inline(always)] + pub fn sd10(self) -> &'a mut W { + self.variant(FSEL18_A::SD10) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL18_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL18_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_CE0_N"] + #[inline(always)] + pub fn spi1_ce0_n(self) -> &'a mut W { + self.variant(FSEL18_A::SPI1_CE0_N) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL18_A::PWM0_0) + } +} +#[doc = "Field `FSEL19` reader - Function Select 19"] +pub type FSEL19_R = crate::FieldReader; +#[doc = "Function Select 19"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL19_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_FS"] + PCM_FS = 4, + #[doc = "5: Pin is connected to SD11"] + SD11 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_MISO"] + SPI1_MISO = 3, + #[doc = "2: Pin is connected to PWM0_1"] + PWM0_1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL19_A) -> Self { + variant as _ + } +} +impl FSEL19_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL19_A { + match self.bits { + 0 => FSEL19_A::INPUT, + 1 => FSEL19_A::OUTPUT, + 4 => FSEL19_A::PCM_FS, + 5 => FSEL19_A::SD11, + 6 => FSEL19_A::RESERVED2, + 7 => FSEL19_A::RESERVED3, + 3 => FSEL19_A::SPI1_MISO, + 2 => FSEL19_A::PWM0_1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL19_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL19_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_FS`"] + #[inline(always)] + pub fn is_pcm_fs(&self) -> bool { + *self == FSEL19_A::PCM_FS + } + #[doc = "Checks if the value of the field is `SD11`"] + #[inline(always)] + pub fn is_sd11(&self) -> bool { + *self == FSEL19_A::SD11 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL19_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL19_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_MISO`"] + #[inline(always)] + pub fn is_spi1_miso(&self) -> bool { + *self == FSEL19_A::SPI1_MISO + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL19_A::PWM0_1 + } +} +#[doc = "Field `FSEL19` writer - Function Select 19"] +pub type FSEL19_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL19_A, 3, O>; +impl<'a, const O: u8> FSEL19_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL19_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL19_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_FS"] + #[inline(always)] + pub fn pcm_fs(self) -> &'a mut W { + self.variant(FSEL19_A::PCM_FS) + } + #[doc = "Pin is connected to SD11"] + #[inline(always)] + pub fn sd11(self) -> &'a mut W { + self.variant(FSEL19_A::SD11) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL19_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL19_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_MISO"] + #[inline(always)] + pub fn spi1_miso(self) -> &'a mut W { + self.variant(FSEL19_A::SPI1_MISO) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL19_A::PWM0_1) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 10"] + #[inline(always)] + pub fn fsel10(&self) -> FSEL10_R { + FSEL10_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 11"] + #[inline(always)] + pub fn fsel11(&self) -> FSEL11_R { + FSEL11_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 12"] + #[inline(always)] + pub fn fsel12(&self) -> FSEL12_R { + FSEL12_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 13"] + #[inline(always)] + pub fn fsel13(&self) -> FSEL13_R { + FSEL13_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 14"] + #[inline(always)] + pub fn fsel14(&self) -> FSEL14_R { + FSEL14_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 15"] + #[inline(always)] + pub fn fsel15(&self) -> FSEL15_R { + FSEL15_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 16"] + #[inline(always)] + pub fn fsel16(&self) -> FSEL16_R { + FSEL16_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 17"] + #[inline(always)] + pub fn fsel17(&self) -> FSEL17_R { + FSEL17_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 18"] + #[inline(always)] + pub fn fsel18(&self) -> FSEL18_R { + FSEL18_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 19"] + #[inline(always)] + pub fn fsel19(&self) -> FSEL19_R { + FSEL19_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 10"] + #[inline(always)] + #[must_use] + pub fn fsel10(&mut self) -> FSEL10_W<0> { + FSEL10_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 11"] + #[inline(always)] + #[must_use] + pub fn fsel11(&mut self) -> FSEL11_W<3> { + FSEL11_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 12"] + #[inline(always)] + #[must_use] + pub fn fsel12(&mut self) -> FSEL12_W<6> { + FSEL12_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 13"] + #[inline(always)] + #[must_use] + pub fn fsel13(&mut self) -> FSEL13_W<9> { + FSEL13_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 14"] + #[inline(always)] + #[must_use] + pub fn fsel14(&mut self) -> FSEL14_W<12> { + FSEL14_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 15"] + #[inline(always)] + #[must_use] + pub fn fsel15(&mut self) -> FSEL15_W<15> { + FSEL15_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 16"] + #[inline(always)] + #[must_use] + pub fn fsel16(&mut self) -> FSEL16_W<18> { + FSEL16_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 17"] + #[inline(always)] + #[must_use] + pub fn fsel17(&mut self) -> FSEL17_W<21> { + FSEL17_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 18"] + #[inline(always)] + #[must_use] + pub fn fsel18(&mut self) -> FSEL18_W<24> { + FSEL18_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 19"] + #[inline(always)] + #[must_use] + pub fn fsel19(&mut self) -> FSEL19_W<27> { + FSEL19_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel1](index.html) module"] +pub struct GPFSEL1_SPEC; +impl crate::RegisterSpec for GPFSEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel1::R](R) reader structure"] +impl crate::Readable for GPFSEL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel1::W](W) writer structure"] +impl crate::Writable for GPFSEL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel2.rs b/crates/bcm2837-lpa/src/gpio/gpfsel2.rs new file mode 100644 index 0000000..8bc92dc --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfsel2.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL20` reader - Function Select 20"] +pub type FSEL20_R = crate::FieldReader; +#[doc = "Function Select 20"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL20_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_DIN"] + PCM_DIN = 4, + #[doc = "5: Pin is connected to SD12"] + SD12 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_MOSI"] + SPI1_MOSI = 3, + #[doc = "2: Pin is connected to GPCLK0"] + GPCLK0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL20_A) -> Self { + variant as _ + } +} +impl FSEL20_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL20_A { + match self.bits { + 0 => FSEL20_A::INPUT, + 1 => FSEL20_A::OUTPUT, + 4 => FSEL20_A::PCM_DIN, + 5 => FSEL20_A::SD12, + 6 => FSEL20_A::RESERVED2, + 7 => FSEL20_A::RESERVED3, + 3 => FSEL20_A::SPI1_MOSI, + 2 => FSEL20_A::GPCLK0, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL20_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL20_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[inline(always)] + pub fn is_pcm_din(&self) -> bool { + *self == FSEL20_A::PCM_DIN + } + #[doc = "Checks if the value of the field is `SD12`"] + #[inline(always)] + pub fn is_sd12(&self) -> bool { + *self == FSEL20_A::SD12 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL20_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL20_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_MOSI`"] + #[inline(always)] + pub fn is_spi1_mosi(&self) -> bool { + *self == FSEL20_A::SPI1_MOSI + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL20_A::GPCLK0 + } +} +#[doc = "Field `FSEL20` writer - Function Select 20"] +pub type FSEL20_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL20_A, 3, O>; +impl<'a, const O: u8> FSEL20_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL20_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL20_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_DIN"] + #[inline(always)] + pub fn pcm_din(self) -> &'a mut W { + self.variant(FSEL20_A::PCM_DIN) + } + #[doc = "Pin is connected to SD12"] + #[inline(always)] + pub fn sd12(self) -> &'a mut W { + self.variant(FSEL20_A::SD12) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL20_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL20_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_MOSI"] + #[inline(always)] + pub fn spi1_mosi(self) -> &'a mut W { + self.variant(FSEL20_A::SPI1_MOSI) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL20_A::GPCLK0) + } +} +#[doc = "Field `FSEL21` reader - Function Select 21"] +pub type FSEL21_R = crate::FieldReader; +#[doc = "Function Select 21"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL21_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PCM_DOUT"] + PCM_DOUT = 4, + #[doc = "5: Pin is connected to SD13"] + SD13 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Pin is connected to SPI1_SCLK"] + SPI1_SCLK = 3, + #[doc = "2: Pin is connected to GPCLK1"] + GPCLK1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL21_A) -> Self { + variant as _ + } +} +impl FSEL21_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL21_A { + match self.bits { + 0 => FSEL21_A::INPUT, + 1 => FSEL21_A::OUTPUT, + 4 => FSEL21_A::PCM_DOUT, + 5 => FSEL21_A::SD13, + 6 => FSEL21_A::RESERVED2, + 7 => FSEL21_A::RESERVED3, + 3 => FSEL21_A::SPI1_SCLK, + 2 => FSEL21_A::GPCLK1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL21_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL21_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[inline(always)] + pub fn is_pcm_dout(&self) -> bool { + *self == FSEL21_A::PCM_DOUT + } + #[doc = "Checks if the value of the field is `SD13`"] + #[inline(always)] + pub fn is_sd13(&self) -> bool { + *self == FSEL21_A::SD13 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL21_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL21_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `SPI1_SCLK`"] + #[inline(always)] + pub fn is_spi1_sclk(&self) -> bool { + *self == FSEL21_A::SPI1_SCLK + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL21_A::GPCLK1 + } +} +#[doc = "Field `FSEL21` writer - Function Select 21"] +pub type FSEL21_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL21_A, 3, O>; +impl<'a, const O: u8> FSEL21_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL21_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL21_A::OUTPUT) + } + #[doc = "Pin is connected to PCM_DOUT"] + #[inline(always)] + pub fn pcm_dout(self) -> &'a mut W { + self.variant(FSEL21_A::PCM_DOUT) + } + #[doc = "Pin is connected to SD13"] + #[inline(always)] + pub fn sd13(self) -> &'a mut W { + self.variant(FSEL21_A::SD13) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL21_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL21_A::RESERVED3) + } + #[doc = "Pin is connected to SPI1_SCLK"] + #[inline(always)] + pub fn spi1_sclk(self) -> &'a mut W { + self.variant(FSEL21_A::SPI1_SCLK) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL21_A::GPCLK1) + } +} +#[doc = "Field `FSEL22` reader - Function Select 22"] +pub type FSEL22_R = crate::FieldReader; +#[doc = "Function Select 22"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL22_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD14"] + SD14 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Pin is connected to ARM_TRST"] + ARM_TRST = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL22_A) -> Self { + variant as _ + } +} +impl FSEL22_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL22_A { + match self.bits { + 0 => FSEL22_A::INPUT, + 1 => FSEL22_A::OUTPUT, + 4 => FSEL22_A::RESERVED0, + 5 => FSEL22_A::SD14, + 6 => FSEL22_A::RESERVED2, + 7 => FSEL22_A::SD1_CLK, + 3 => FSEL22_A::ARM_TRST, + 2 => FSEL22_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL22_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL22_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL22_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD14`"] + #[inline(always)] + pub fn is_sd14(&self) -> bool { + *self == FSEL22_A::SD14 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL22_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL22_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `ARM_TRST`"] + #[inline(always)] + pub fn is_arm_trst(&self) -> bool { + *self == FSEL22_A::ARM_TRST + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL22_A::RESERVED5 + } +} +#[doc = "Field `FSEL22` writer - Function Select 22"] +pub type FSEL22_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL22_A, 3, O>; +impl<'a, const O: u8> FSEL22_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL22_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL22_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL22_A::RESERVED0) + } + #[doc = "Pin is connected to SD14"] + #[inline(always)] + pub fn sd14(self) -> &'a mut W { + self.variant(FSEL22_A::SD14) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL22_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL22_A::SD1_CLK) + } + #[doc = "Pin is connected to ARM_TRST"] + #[inline(always)] + pub fn arm_trst(self) -> &'a mut W { + self.variant(FSEL22_A::ARM_TRST) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL22_A::RESERVED5) + } +} +#[doc = "Field `FSEL23` reader - Function Select 23"] +pub type FSEL23_R = crate::FieldReader; +#[doc = "Function Select 23"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL23_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD15"] + SD15 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Pin is connected to ARM_RTCK"] + ARM_RTCK = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL23_A) -> Self { + variant as _ + } +} +impl FSEL23_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL23_A { + match self.bits { + 0 => FSEL23_A::INPUT, + 1 => FSEL23_A::OUTPUT, + 4 => FSEL23_A::RESERVED0, + 5 => FSEL23_A::SD15, + 6 => FSEL23_A::RESERVED2, + 7 => FSEL23_A::SD1_CMD, + 3 => FSEL23_A::ARM_RTCK, + 2 => FSEL23_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL23_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL23_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL23_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD15`"] + #[inline(always)] + pub fn is_sd15(&self) -> bool { + *self == FSEL23_A::SD15 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL23_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL23_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[inline(always)] + pub fn is_arm_rtck(&self) -> bool { + *self == FSEL23_A::ARM_RTCK + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL23_A::RESERVED5 + } +} +#[doc = "Field `FSEL23` writer - Function Select 23"] +pub type FSEL23_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL23_A, 3, O>; +impl<'a, const O: u8> FSEL23_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL23_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL23_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL23_A::RESERVED0) + } + #[doc = "Pin is connected to SD15"] + #[inline(always)] + pub fn sd15(self) -> &'a mut W { + self.variant(FSEL23_A::SD15) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL23_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL23_A::SD1_CMD) + } + #[doc = "Pin is connected to ARM_RTCK"] + #[inline(always)] + pub fn arm_rtck(self) -> &'a mut W { + self.variant(FSEL23_A::ARM_RTCK) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL23_A::RESERVED5) + } +} +#[doc = "Field `FSEL24` reader - Function Select 24"] +pub type FSEL24_R = crate::FieldReader; +#[doc = "Function Select 24"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL24_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD16"] + SD16 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Pin is connected to ARM_TDO"] + ARM_TDO = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL24_A) -> Self { + variant as _ + } +} +impl FSEL24_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL24_A { + match self.bits { + 0 => FSEL24_A::INPUT, + 1 => FSEL24_A::OUTPUT, + 4 => FSEL24_A::RESERVED0, + 5 => FSEL24_A::SD16, + 6 => FSEL24_A::RESERVED2, + 7 => FSEL24_A::SD1_DAT0, + 3 => FSEL24_A::ARM_TDO, + 2 => FSEL24_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL24_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL24_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL24_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD16`"] + #[inline(always)] + pub fn is_sd16(&self) -> bool { + *self == FSEL24_A::SD16 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL24_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL24_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[inline(always)] + pub fn is_arm_tdo(&self) -> bool { + *self == FSEL24_A::ARM_TDO + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL24_A::RESERVED5 + } +} +#[doc = "Field `FSEL24` writer - Function Select 24"] +pub type FSEL24_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL24_A, 3, O>; +impl<'a, const O: u8> FSEL24_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL24_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL24_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL24_A::RESERVED0) + } + #[doc = "Pin is connected to SD16"] + #[inline(always)] + pub fn sd16(self) -> &'a mut W { + self.variant(FSEL24_A::SD16) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL24_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL24_A::SD1_DAT0) + } + #[doc = "Pin is connected to ARM_TDO"] + #[inline(always)] + pub fn arm_tdo(self) -> &'a mut W { + self.variant(FSEL24_A::ARM_TDO) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL24_A::RESERVED5) + } +} +#[doc = "Field `FSEL25` reader - Function Select 25"] +pub type FSEL25_R = crate::FieldReader; +#[doc = "Function Select 25"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL25_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SD17"] + SD17 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Pin is connected to ARM_TCK"] + ARM_TCK = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL25_A) -> Self { + variant as _ + } +} +impl FSEL25_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL25_A { + match self.bits { + 0 => FSEL25_A::INPUT, + 1 => FSEL25_A::OUTPUT, + 4 => FSEL25_A::RESERVED0, + 5 => FSEL25_A::SD17, + 6 => FSEL25_A::RESERVED2, + 7 => FSEL25_A::SD1_DAT1, + 3 => FSEL25_A::ARM_TCK, + 2 => FSEL25_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL25_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL25_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL25_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SD17`"] + #[inline(always)] + pub fn is_sd17(&self) -> bool { + *self == FSEL25_A::SD17 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL25_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL25_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[inline(always)] + pub fn is_arm_tck(&self) -> bool { + *self == FSEL25_A::ARM_TCK + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL25_A::RESERVED5 + } +} +#[doc = "Field `FSEL25` writer - Function Select 25"] +pub type FSEL25_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL25_A, 3, O>; +impl<'a, const O: u8> FSEL25_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL25_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL25_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL25_A::RESERVED0) + } + #[doc = "Pin is connected to SD17"] + #[inline(always)] + pub fn sd17(self) -> &'a mut W { + self.variant(FSEL25_A::SD17) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL25_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL25_A::SD1_DAT1) + } + #[doc = "Pin is connected to ARM_TCK"] + #[inline(always)] + pub fn arm_tck(self) -> &'a mut W { + self.variant(FSEL25_A::ARM_TCK) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL25_A::RESERVED5) + } +} +#[doc = "Field `FSEL26` reader - Function Select 26"] +pub type FSEL26_R = crate::FieldReader; +#[doc = "Function Select 26"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL26_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Pin is connected to ARM_TDI"] + ARM_TDI = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL26_A) -> Self { + variant as _ + } +} +impl FSEL26_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL26_A { + match self.bits { + 0 => FSEL26_A::INPUT, + 1 => FSEL26_A::OUTPUT, + 4 => FSEL26_A::RESERVED0, + 5 => FSEL26_A::RESERVED1, + 6 => FSEL26_A::RESERVED2, + 7 => FSEL26_A::SD1_DAT2, + 3 => FSEL26_A::ARM_TDI, + 2 => FSEL26_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL26_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL26_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL26_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL26_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL26_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL26_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[inline(always)] + pub fn is_arm_tdi(&self) -> bool { + *self == FSEL26_A::ARM_TDI + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL26_A::RESERVED5 + } +} +#[doc = "Field `FSEL26` writer - Function Select 26"] +pub type FSEL26_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL26_A, 3, O>; +impl<'a, const O: u8> FSEL26_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL26_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL26_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL26_A::SD1_DAT2) + } + #[doc = "Pin is connected to ARM_TDI"] + #[inline(always)] + pub fn arm_tdi(self) -> &'a mut W { + self.variant(FSEL26_A::ARM_TDI) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL26_A::RESERVED5) + } +} +#[doc = "Field `FSEL27` reader - Function Select 27"] +pub type FSEL27_R = crate::FieldReader; +#[doc = "Function Select 27"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL27_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Pin is connected to ARM_TMS"] + ARM_TMS = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL27_A) -> Self { + variant as _ + } +} +impl FSEL27_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL27_A { + match self.bits { + 0 => FSEL27_A::INPUT, + 1 => FSEL27_A::OUTPUT, + 4 => FSEL27_A::RESERVED0, + 5 => FSEL27_A::RESERVED1, + 6 => FSEL27_A::RESERVED2, + 7 => FSEL27_A::SD1_DAT3, + 3 => FSEL27_A::ARM_TMS, + 2 => FSEL27_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL27_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL27_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL27_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL27_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL27_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL27_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[inline(always)] + pub fn is_arm_tms(&self) -> bool { + *self == FSEL27_A::ARM_TMS + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL27_A::RESERVED5 + } +} +#[doc = "Field `FSEL27` writer - Function Select 27"] +pub type FSEL27_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL27_A, 3, O>; +impl<'a, const O: u8> FSEL27_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL27_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL27_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL27_A::SD1_DAT3) + } + #[doc = "Pin is connected to ARM_TMS"] + #[inline(always)] + pub fn arm_tms(self) -> &'a mut W { + self.variant(FSEL27_A::ARM_TMS) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL27_A::RESERVED5) + } +} +#[doc = "Field `FSEL28` reader - Function Select 28"] +pub type FSEL28_R = crate::FieldReader; +#[doc = "Function Select 28"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL28_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SDA0"] + SDA0 = 4, + #[doc = "5: Pin is connected to SA5"] + SA5 = 5, + #[doc = "6: Pin is connected to PCM_CLK"] + PCM_CLK = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL28_A) -> Self { + variant as _ + } +} +impl FSEL28_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL28_A { + match self.bits { + 0 => FSEL28_A::INPUT, + 1 => FSEL28_A::OUTPUT, + 4 => FSEL28_A::SDA0, + 5 => FSEL28_A::SA5, + 6 => FSEL28_A::PCM_CLK, + 7 => FSEL28_A::RESERVED3, + 3 => FSEL28_A::RESERVED4, + 2 => FSEL28_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL28_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL28_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL28_A::SDA0 + } + #[doc = "Checks if the value of the field is `SA5`"] + #[inline(always)] + pub fn is_sa5(&self) -> bool { + *self == FSEL28_A::SA5 + } + #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[inline(always)] + pub fn is_pcm_clk(&self) -> bool { + *self == FSEL28_A::PCM_CLK + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL28_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL28_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL28_A::RESERVED5 + } +} +#[doc = "Field `FSEL28` writer - Function Select 28"] +pub type FSEL28_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL28_A, 3, O>; +impl<'a, const O: u8> FSEL28_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL28_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL28_A::OUTPUT) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL28_A::SDA0) + } + #[doc = "Pin is connected to SA5"] + #[inline(always)] + pub fn sa5(self) -> &'a mut W { + self.variant(FSEL28_A::SA5) + } + #[doc = "Pin is connected to PCM_CLK"] + #[inline(always)] + pub fn pcm_clk(self) -> &'a mut W { + self.variant(FSEL28_A::PCM_CLK) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL28_A::RESERVED5) + } +} +#[doc = "Field `FSEL29` reader - Function Select 29"] +pub type FSEL29_R = crate::FieldReader; +#[doc = "Function Select 29"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL29_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SCL0"] + SCL0 = 4, + #[doc = "5: Pin is connected to SA4"] + SA4 = 5, + #[doc = "6: Pin is connected to PCM_FS"] + PCM_FS = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL29_A) -> Self { + variant as _ + } +} +impl FSEL29_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL29_A { + match self.bits { + 0 => FSEL29_A::INPUT, + 1 => FSEL29_A::OUTPUT, + 4 => FSEL29_A::SCL0, + 5 => FSEL29_A::SA4, + 6 => FSEL29_A::PCM_FS, + 7 => FSEL29_A::RESERVED3, + 3 => FSEL29_A::RESERVED4, + 2 => FSEL29_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL29_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL29_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL29_A::SCL0 + } + #[doc = "Checks if the value of the field is `SA4`"] + #[inline(always)] + pub fn is_sa4(&self) -> bool { + *self == FSEL29_A::SA4 + } + #[doc = "Checks if the value of the field is `PCM_FS`"] + #[inline(always)] + pub fn is_pcm_fs(&self) -> bool { + *self == FSEL29_A::PCM_FS + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL29_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL29_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL29_A::RESERVED5 + } +} +#[doc = "Field `FSEL29` writer - Function Select 29"] +pub type FSEL29_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL29_A, 3, O>; +impl<'a, const O: u8> FSEL29_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL29_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL29_A::OUTPUT) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL29_A::SCL0) + } + #[doc = "Pin is connected to SA4"] + #[inline(always)] + pub fn sa4(self) -> &'a mut W { + self.variant(FSEL29_A::SA4) + } + #[doc = "Pin is connected to PCM_FS"] + #[inline(always)] + pub fn pcm_fs(self) -> &'a mut W { + self.variant(FSEL29_A::PCM_FS) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL29_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 20"] + #[inline(always)] + pub fn fsel20(&self) -> FSEL20_R { + FSEL20_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 21"] + #[inline(always)] + pub fn fsel21(&self) -> FSEL21_R { + FSEL21_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 22"] + #[inline(always)] + pub fn fsel22(&self) -> FSEL22_R { + FSEL22_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 23"] + #[inline(always)] + pub fn fsel23(&self) -> FSEL23_R { + FSEL23_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 24"] + #[inline(always)] + pub fn fsel24(&self) -> FSEL24_R { + FSEL24_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 25"] + #[inline(always)] + pub fn fsel25(&self) -> FSEL25_R { + FSEL25_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 26"] + #[inline(always)] + pub fn fsel26(&self) -> FSEL26_R { + FSEL26_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 27"] + #[inline(always)] + pub fn fsel27(&self) -> FSEL27_R { + FSEL27_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 28"] + #[inline(always)] + pub fn fsel28(&self) -> FSEL28_R { + FSEL28_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 29"] + #[inline(always)] + pub fn fsel29(&self) -> FSEL29_R { + FSEL29_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 20"] + #[inline(always)] + #[must_use] + pub fn fsel20(&mut self) -> FSEL20_W<0> { + FSEL20_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 21"] + #[inline(always)] + #[must_use] + pub fn fsel21(&mut self) -> FSEL21_W<3> { + FSEL21_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 22"] + #[inline(always)] + #[must_use] + pub fn fsel22(&mut self) -> FSEL22_W<6> { + FSEL22_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 23"] + #[inline(always)] + #[must_use] + pub fn fsel23(&mut self) -> FSEL23_W<9> { + FSEL23_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 24"] + #[inline(always)] + #[must_use] + pub fn fsel24(&mut self) -> FSEL24_W<12> { + FSEL24_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 25"] + #[inline(always)] + #[must_use] + pub fn fsel25(&mut self) -> FSEL25_W<15> { + FSEL25_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 26"] + #[inline(always)] + #[must_use] + pub fn fsel26(&mut self) -> FSEL26_W<18> { + FSEL26_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 27"] + #[inline(always)] + #[must_use] + pub fn fsel27(&mut self) -> FSEL27_W<21> { + FSEL27_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 28"] + #[inline(always)] + #[must_use] + pub fn fsel28(&mut self) -> FSEL28_W<24> { + FSEL28_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 29"] + #[inline(always)] + #[must_use] + pub fn fsel29(&mut self) -> FSEL29_W<27> { + FSEL29_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel2](index.html) module"] +pub struct GPFSEL2_SPEC; +impl crate::RegisterSpec for GPFSEL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel2::R](R) reader structure"] +impl crate::Readable for GPFSEL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel2::W](W) writer structure"] +impl crate::Writable for GPFSEL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel3.rs b/crates/bcm2837-lpa/src/gpio/gpfsel3.rs new file mode 100644 index 0000000..d3f9c4f --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfsel3.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL30` reader - Function Select 30"] +pub type FSEL30_R = crate::FieldReader; +#[doc = "Function Select 30"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL30_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA3"] + SA3 = 5, + #[doc = "6: Pin is connected to PCM_DIN"] + PCM_DIN = 6, + #[doc = "7: Pin is connected to CTS0"] + CTS0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL30_A) -> Self { + variant as _ + } +} +impl FSEL30_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL30_A { + match self.bits { + 0 => FSEL30_A::INPUT, + 1 => FSEL30_A::OUTPUT, + 4 => FSEL30_A::RESERVED0, + 5 => FSEL30_A::SA3, + 6 => FSEL30_A::PCM_DIN, + 7 => FSEL30_A::CTS0, + 3 => FSEL30_A::RESERVED4, + 2 => FSEL30_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL30_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL30_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL30_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA3`"] + #[inline(always)] + pub fn is_sa3(&self) -> bool { + *self == FSEL30_A::SA3 + } + #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[inline(always)] + pub fn is_pcm_din(&self) -> bool { + *self == FSEL30_A::PCM_DIN + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL30_A::CTS0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL30_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL30_A::CTS1 + } +} +#[doc = "Field `FSEL30` writer - Function Select 30"] +pub type FSEL30_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL30_A, 3, O>; +impl<'a, const O: u8> FSEL30_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL30_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL30_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL30_A::RESERVED0) + } + #[doc = "Pin is connected to SA3"] + #[inline(always)] + pub fn sa3(self) -> &'a mut W { + self.variant(FSEL30_A::SA3) + } + #[doc = "Pin is connected to PCM_DIN"] + #[inline(always)] + pub fn pcm_din(self) -> &'a mut W { + self.variant(FSEL30_A::PCM_DIN) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL30_A::CTS0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL30_A::RESERVED4) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL30_A::CTS1) + } +} +#[doc = "Field `FSEL31` reader - Function Select 31"] +pub type FSEL31_R = crate::FieldReader; +#[doc = "Function Select 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL31_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA2"] + SA2 = 5, + #[doc = "6: Pin is connected to PCM_DOUT"] + PCM_DOUT = 6, + #[doc = "7: Pin is connected to RTS0"] + RTS0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL31_A) -> Self { + variant as _ + } +} +impl FSEL31_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL31_A { + match self.bits { + 0 => FSEL31_A::INPUT, + 1 => FSEL31_A::OUTPUT, + 4 => FSEL31_A::RESERVED0, + 5 => FSEL31_A::SA2, + 6 => FSEL31_A::PCM_DOUT, + 7 => FSEL31_A::RTS0, + 3 => FSEL31_A::RESERVED4, + 2 => FSEL31_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL31_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL31_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL31_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA2`"] + #[inline(always)] + pub fn is_sa2(&self) -> bool { + *self == FSEL31_A::SA2 + } + #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[inline(always)] + pub fn is_pcm_dout(&self) -> bool { + *self == FSEL31_A::PCM_DOUT + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL31_A::RTS0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL31_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL31_A::RTS1 + } +} +#[doc = "Field `FSEL31` writer - Function Select 31"] +pub type FSEL31_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL31_A, 3, O>; +impl<'a, const O: u8> FSEL31_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL31_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL31_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL31_A::RESERVED0) + } + #[doc = "Pin is connected to SA2"] + #[inline(always)] + pub fn sa2(self) -> &'a mut W { + self.variant(FSEL31_A::SA2) + } + #[doc = "Pin is connected to PCM_DOUT"] + #[inline(always)] + pub fn pcm_dout(self) -> &'a mut W { + self.variant(FSEL31_A::PCM_DOUT) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL31_A::RTS0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL31_A::RESERVED4) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL31_A::RTS1) + } +} +#[doc = "Field `FSEL32` reader - Function Select 32"] +pub type FSEL32_R = crate::FieldReader; +#[doc = "Function Select 32"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL32_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SA1"] + SA1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to TXD0"] + TXD0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL32_A) -> Self { + variant as _ + } +} +impl FSEL32_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL32_A { + match self.bits { + 0 => FSEL32_A::INPUT, + 1 => FSEL32_A::OUTPUT, + 4 => FSEL32_A::GPCLK0, + 5 => FSEL32_A::SA1, + 6 => FSEL32_A::RESERVED2, + 7 => FSEL32_A::TXD0, + 3 => FSEL32_A::RESERVED4, + 2 => FSEL32_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL32_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL32_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL32_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SA1`"] + #[inline(always)] + pub fn is_sa1(&self) -> bool { + *self == FSEL32_A::SA1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL32_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL32_A::TXD0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL32_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL32_A::TXD1 + } +} +#[doc = "Field `FSEL32` writer - Function Select 32"] +pub type FSEL32_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL32_A, 3, O>; +impl<'a, const O: u8> FSEL32_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL32_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL32_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL32_A::GPCLK0) + } + #[doc = "Pin is connected to SA1"] + #[inline(always)] + pub fn sa1(self) -> &'a mut W { + self.variant(FSEL32_A::SA1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL32_A::RESERVED2) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL32_A::TXD0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL32_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL32_A::TXD1) + } +} +#[doc = "Field `FSEL33` reader - Function Select 33"] +pub type FSEL33_R = crate::FieldReader; +#[doc = "Function Select 33"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL33_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Pin is connected to SA0"] + SA0 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to RXD0"] + RXD0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL33_A) -> Self { + variant as _ + } +} +impl FSEL33_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL33_A { + match self.bits { + 0 => FSEL33_A::INPUT, + 1 => FSEL33_A::OUTPUT, + 4 => FSEL33_A::RESERVED0, + 5 => FSEL33_A::SA0, + 6 => FSEL33_A::RESERVED2, + 7 => FSEL33_A::RXD0, + 3 => FSEL33_A::RESERVED4, + 2 => FSEL33_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL33_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL33_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL33_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `SA0`"] + #[inline(always)] + pub fn is_sa0(&self) -> bool { + *self == FSEL33_A::SA0 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL33_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL33_A::RXD0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL33_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL33_A::RXD1 + } +} +#[doc = "Field `FSEL33` writer - Function Select 33"] +pub type FSEL33_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL33_A, 3, O>; +impl<'a, const O: u8> FSEL33_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL33_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL33_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED0) + } + #[doc = "Pin is connected to SA0"] + #[inline(always)] + pub fn sa0(self) -> &'a mut W { + self.variant(FSEL33_A::SA0) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED2) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL33_A::RXD0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL33_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL33_A::RXD1) + } +} +#[doc = "Field `FSEL34` reader - Function Select 34"] +pub type FSEL34_R = crate::FieldReader; +#[doc = "Function Select 34"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL34_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK0"] + GPCLK0 = 4, + #[doc = "5: Pin is connected to SOE_N"] + SOE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL34_A) -> Self { + variant as _ + } +} +impl FSEL34_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL34_A { + match self.bits { + 0 => FSEL34_A::INPUT, + 1 => FSEL34_A::OUTPUT, + 4 => FSEL34_A::GPCLK0, + 5 => FSEL34_A::SOE_N, + 6 => FSEL34_A::RESERVED2, + 7 => FSEL34_A::RESERVED3, + 3 => FSEL34_A::RESERVED4, + 2 => FSEL34_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL34_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL34_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK0`"] + #[inline(always)] + pub fn is_gpclk0(&self) -> bool { + *self == FSEL34_A::GPCLK0 + } + #[doc = "Checks if the value of the field is `SOE_N`"] + #[inline(always)] + pub fn is_soe_n(&self) -> bool { + *self == FSEL34_A::SOE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL34_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL34_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL34_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL34_A::RESERVED5 + } +} +#[doc = "Field `FSEL34` writer - Function Select 34"] +pub type FSEL34_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL34_A, 3, O>; +impl<'a, const O: u8> FSEL34_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL34_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL34_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK0"] + #[inline(always)] + pub fn gpclk0(self) -> &'a mut W { + self.variant(FSEL34_A::GPCLK0) + } + #[doc = "Pin is connected to SOE_N"] + #[inline(always)] + pub fn soe_n(self) -> &'a mut W { + self.variant(FSEL34_A::SOE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL34_A::RESERVED5) + } +} +#[doc = "Field `FSEL35` reader - Function Select 35"] +pub type FSEL35_R = crate::FieldReader; +#[doc = "Function Select 35"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL35_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE1_N"] + SPI0_CE1_N = 4, + #[doc = "5: Pin is connected to SWE_N"] + SWE_N = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL35_A) -> Self { + variant as _ + } +} +impl FSEL35_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL35_A { + match self.bits { + 0 => FSEL35_A::INPUT, + 1 => FSEL35_A::OUTPUT, + 4 => FSEL35_A::SPI0_CE1_N, + 5 => FSEL35_A::SWE_N, + 6 => FSEL35_A::RESERVED2, + 7 => FSEL35_A::RESERVED3, + 3 => FSEL35_A::RESERVED4, + 2 => FSEL35_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL35_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL35_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[inline(always)] + pub fn is_spi0_ce1_n(&self) -> bool { + *self == FSEL35_A::SPI0_CE1_N + } + #[doc = "Checks if the value of the field is `SWE_N`"] + #[inline(always)] + pub fn is_swe_n(&self) -> bool { + *self == FSEL35_A::SWE_N + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL35_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL35_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL35_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL35_A::RESERVED5 + } +} +#[doc = "Field `FSEL35` writer - Function Select 35"] +pub type FSEL35_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL35_A, 3, O>; +impl<'a, const O: u8> FSEL35_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL35_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL35_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE1_N"] + #[inline(always)] + pub fn spi0_ce1_n(self) -> &'a mut W { + self.variant(FSEL35_A::SPI0_CE1_N) + } + #[doc = "Pin is connected to SWE_N"] + #[inline(always)] + pub fn swe_n(self) -> &'a mut W { + self.variant(FSEL35_A::SWE_N) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL35_A::RESERVED5) + } +} +#[doc = "Field `FSEL36` reader - Function Select 36"] +pub type FSEL36_R = crate::FieldReader; +#[doc = "Function Select 36"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL36_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_CE0_N"] + SPI0_CE0_N = 4, + #[doc = "5: Pin is connected to SD0"] + SD0 = 5, + #[doc = "6: Pin is connected to TXD0"] + TXD0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL36_A) -> Self { + variant as _ + } +} +impl FSEL36_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL36_A { + match self.bits { + 0 => FSEL36_A::INPUT, + 1 => FSEL36_A::OUTPUT, + 4 => FSEL36_A::SPI0_CE0_N, + 5 => FSEL36_A::SD0, + 6 => FSEL36_A::TXD0, + 7 => FSEL36_A::RESERVED3, + 3 => FSEL36_A::RESERVED4, + 2 => FSEL36_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL36_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL36_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[inline(always)] + pub fn is_spi0_ce0_n(&self) -> bool { + *self == FSEL36_A::SPI0_CE0_N + } + #[doc = "Checks if the value of the field is `SD0`"] + #[inline(always)] + pub fn is_sd0(&self) -> bool { + *self == FSEL36_A::SD0 + } + #[doc = "Checks if the value of the field is `TXD0`"] + #[inline(always)] + pub fn is_txd0(&self) -> bool { + *self == FSEL36_A::TXD0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL36_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL36_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL36_A::RESERVED5 + } +} +#[doc = "Field `FSEL36` writer - Function Select 36"] +pub type FSEL36_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL36_A, 3, O>; +impl<'a, const O: u8> FSEL36_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL36_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL36_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_CE0_N"] + #[inline(always)] + pub fn spi0_ce0_n(self) -> &'a mut W { + self.variant(FSEL36_A::SPI0_CE0_N) + } + #[doc = "Pin is connected to SD0"] + #[inline(always)] + pub fn sd0(self) -> &'a mut W { + self.variant(FSEL36_A::SD0) + } + #[doc = "Pin is connected to TXD0"] + #[inline(always)] + pub fn txd0(self) -> &'a mut W { + self.variant(FSEL36_A::TXD0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL36_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL36_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL36_A::RESERVED5) + } +} +#[doc = "Field `FSEL37` reader - Function Select 37"] +pub type FSEL37_R = crate::FieldReader; +#[doc = "Function Select 37"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL37_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MISO"] + SPI0_MISO = 4, + #[doc = "5: Pin is connected to SD1"] + SD1 = 5, + #[doc = "6: Pin is connected to RXD0"] + RXD0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL37_A) -> Self { + variant as _ + } +} +impl FSEL37_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL37_A { + match self.bits { + 0 => FSEL37_A::INPUT, + 1 => FSEL37_A::OUTPUT, + 4 => FSEL37_A::SPI0_MISO, + 5 => FSEL37_A::SD1, + 6 => FSEL37_A::RXD0, + 7 => FSEL37_A::RESERVED3, + 3 => FSEL37_A::RESERVED4, + 2 => FSEL37_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL37_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL37_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[inline(always)] + pub fn is_spi0_miso(&self) -> bool { + *self == FSEL37_A::SPI0_MISO + } + #[doc = "Checks if the value of the field is `SD1`"] + #[inline(always)] + pub fn is_sd1(&self) -> bool { + *self == FSEL37_A::SD1 + } + #[doc = "Checks if the value of the field is `RXD0`"] + #[inline(always)] + pub fn is_rxd0(&self) -> bool { + *self == FSEL37_A::RXD0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL37_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL37_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL37_A::RESERVED5 + } +} +#[doc = "Field `FSEL37` writer - Function Select 37"] +pub type FSEL37_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL37_A, 3, O>; +impl<'a, const O: u8> FSEL37_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL37_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL37_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MISO"] + #[inline(always)] + pub fn spi0_miso(self) -> &'a mut W { + self.variant(FSEL37_A::SPI0_MISO) + } + #[doc = "Pin is connected to SD1"] + #[inline(always)] + pub fn sd1(self) -> &'a mut W { + self.variant(FSEL37_A::SD1) + } + #[doc = "Pin is connected to RXD0"] + #[inline(always)] + pub fn rxd0(self) -> &'a mut W { + self.variant(FSEL37_A::RXD0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL37_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL37_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL37_A::RESERVED5) + } +} +#[doc = "Field `FSEL38` reader - Function Select 38"] +pub type FSEL38_R = crate::FieldReader; +#[doc = "Function Select 38"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL38_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_MOSI"] + SPI0_MOSI = 4, + #[doc = "5: Pin is connected to SD2"] + SD2 = 5, + #[doc = "6: Pin is connected to CTS0"] + CTS0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL38_A) -> Self { + variant as _ + } +} +impl FSEL38_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL38_A { + match self.bits { + 0 => FSEL38_A::INPUT, + 1 => FSEL38_A::OUTPUT, + 4 => FSEL38_A::SPI0_MOSI, + 5 => FSEL38_A::SD2, + 6 => FSEL38_A::CTS0, + 7 => FSEL38_A::RESERVED3, + 3 => FSEL38_A::RESERVED4, + 2 => FSEL38_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL38_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL38_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[inline(always)] + pub fn is_spi0_mosi(&self) -> bool { + *self == FSEL38_A::SPI0_MOSI + } + #[doc = "Checks if the value of the field is `SD2`"] + #[inline(always)] + pub fn is_sd2(&self) -> bool { + *self == FSEL38_A::SD2 + } + #[doc = "Checks if the value of the field is `CTS0`"] + #[inline(always)] + pub fn is_cts0(&self) -> bool { + *self == FSEL38_A::CTS0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL38_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL38_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL38_A::RESERVED5 + } +} +#[doc = "Field `FSEL38` writer - Function Select 38"] +pub type FSEL38_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL38_A, 3, O>; +impl<'a, const O: u8> FSEL38_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL38_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL38_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_MOSI"] + #[inline(always)] + pub fn spi0_mosi(self) -> &'a mut W { + self.variant(FSEL38_A::SPI0_MOSI) + } + #[doc = "Pin is connected to SD2"] + #[inline(always)] + pub fn sd2(self) -> &'a mut W { + self.variant(FSEL38_A::SD2) + } + #[doc = "Pin is connected to CTS0"] + #[inline(always)] + pub fn cts0(self) -> &'a mut W { + self.variant(FSEL38_A::CTS0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL38_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL38_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL38_A::RESERVED5) + } +} +#[doc = "Field `FSEL39` reader - Function Select 39"] +pub type FSEL39_R = crate::FieldReader; +#[doc = "Function Select 39"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL39_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to SPI0_SCLK"] + SPI0_SCLK = 4, + #[doc = "5: Pin is connected to SD3"] + SD3 = 5, + #[doc = "6: Pin is connected to RTS0"] + RTS0 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL39_A) -> Self { + variant as _ + } +} +impl FSEL39_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL39_A { + match self.bits { + 0 => FSEL39_A::INPUT, + 1 => FSEL39_A::OUTPUT, + 4 => FSEL39_A::SPI0_SCLK, + 5 => FSEL39_A::SD3, + 6 => FSEL39_A::RTS0, + 7 => FSEL39_A::RESERVED3, + 3 => FSEL39_A::RESERVED4, + 2 => FSEL39_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL39_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL39_A::OUTPUT + } + #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[inline(always)] + pub fn is_spi0_sclk(&self) -> bool { + *self == FSEL39_A::SPI0_SCLK + } + #[doc = "Checks if the value of the field is `SD3`"] + #[inline(always)] + pub fn is_sd3(&self) -> bool { + *self == FSEL39_A::SD3 + } + #[doc = "Checks if the value of the field is `RTS0`"] + #[inline(always)] + pub fn is_rts0(&self) -> bool { + *self == FSEL39_A::RTS0 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL39_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL39_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL39_A::RESERVED5 + } +} +#[doc = "Field `FSEL39` writer - Function Select 39"] +pub type FSEL39_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL39_A, 3, O>; +impl<'a, const O: u8> FSEL39_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL39_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL39_A::OUTPUT) + } + #[doc = "Pin is connected to SPI0_SCLK"] + #[inline(always)] + pub fn spi0_sclk(self) -> &'a mut W { + self.variant(FSEL39_A::SPI0_SCLK) + } + #[doc = "Pin is connected to SD3"] + #[inline(always)] + pub fn sd3(self) -> &'a mut W { + self.variant(FSEL39_A::SD3) + } + #[doc = "Pin is connected to RTS0"] + #[inline(always)] + pub fn rts0(self) -> &'a mut W { + self.variant(FSEL39_A::RTS0) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL39_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL39_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL39_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 30"] + #[inline(always)] + pub fn fsel30(&self) -> FSEL30_R { + FSEL30_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 31"] + #[inline(always)] + pub fn fsel31(&self) -> FSEL31_R { + FSEL31_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 32"] + #[inline(always)] + pub fn fsel32(&self) -> FSEL32_R { + FSEL32_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 33"] + #[inline(always)] + pub fn fsel33(&self) -> FSEL33_R { + FSEL33_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 34"] + #[inline(always)] + pub fn fsel34(&self) -> FSEL34_R { + FSEL34_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 35"] + #[inline(always)] + pub fn fsel35(&self) -> FSEL35_R { + FSEL35_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 36"] + #[inline(always)] + pub fn fsel36(&self) -> FSEL36_R { + FSEL36_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 37"] + #[inline(always)] + pub fn fsel37(&self) -> FSEL37_R { + FSEL37_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 38"] + #[inline(always)] + pub fn fsel38(&self) -> FSEL38_R { + FSEL38_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 39"] + #[inline(always)] + pub fn fsel39(&self) -> FSEL39_R { + FSEL39_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 30"] + #[inline(always)] + #[must_use] + pub fn fsel30(&mut self) -> FSEL30_W<0> { + FSEL30_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 31"] + #[inline(always)] + #[must_use] + pub fn fsel31(&mut self) -> FSEL31_W<3> { + FSEL31_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 32"] + #[inline(always)] + #[must_use] + pub fn fsel32(&mut self) -> FSEL32_W<6> { + FSEL32_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 33"] + #[inline(always)] + #[must_use] + pub fn fsel33(&mut self) -> FSEL33_W<9> { + FSEL33_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 34"] + #[inline(always)] + #[must_use] + pub fn fsel34(&mut self) -> FSEL34_W<12> { + FSEL34_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 35"] + #[inline(always)] + #[must_use] + pub fn fsel35(&mut self) -> FSEL35_W<15> { + FSEL35_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 36"] + #[inline(always)] + #[must_use] + pub fn fsel36(&mut self) -> FSEL36_W<18> { + FSEL36_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 37"] + #[inline(always)] + #[must_use] + pub fn fsel37(&mut self) -> FSEL37_W<21> { + FSEL37_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 38"] + #[inline(always)] + #[must_use] + pub fn fsel38(&mut self) -> FSEL38_W<24> { + FSEL38_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 39"] + #[inline(always)] + #[must_use] + pub fn fsel39(&mut self) -> FSEL39_W<27> { + FSEL39_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel3](index.html) module"] +pub struct GPFSEL3_SPEC; +impl crate::RegisterSpec for GPFSEL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel3::R](R) reader structure"] +impl crate::Readable for GPFSEL3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel3::W](W) writer structure"] +impl crate::Writable for GPFSEL3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel4.rs b/crates/bcm2837-lpa/src/gpio/gpfsel4.rs new file mode 100644 index 0000000..16bf84a --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfsel4.rs @@ -0,0 +1,1481 @@ +#[doc = "Register `GPFSEL4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL40` reader - Function Select 40"] +pub type FSEL40_R = crate::FieldReader; +#[doc = "Function Select 40"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL40_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_0"] + PWM0_0 = 4, + #[doc = "5: Pin is connected to SD4"] + SD4 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to TXD1"] + TXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL40_A) -> Self { + variant as _ + } +} +impl FSEL40_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL40_A { + match self.bits { + 0 => FSEL40_A::INPUT, + 1 => FSEL40_A::OUTPUT, + 4 => FSEL40_A::PWM0_0, + 5 => FSEL40_A::SD4, + 6 => FSEL40_A::RESERVED2, + 7 => FSEL40_A::RESERVED3, + 3 => FSEL40_A::RESERVED4, + 2 => FSEL40_A::TXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL40_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL40_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_0`"] + #[inline(always)] + pub fn is_pwm0_0(&self) -> bool { + *self == FSEL40_A::PWM0_0 + } + #[doc = "Checks if the value of the field is `SD4`"] + #[inline(always)] + pub fn is_sd4(&self) -> bool { + *self == FSEL40_A::SD4 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL40_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL40_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL40_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `TXD1`"] + #[inline(always)] + pub fn is_txd1(&self) -> bool { + *self == FSEL40_A::TXD1 + } +} +#[doc = "Field `FSEL40` writer - Function Select 40"] +pub type FSEL40_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL40_A, 3, O>; +impl<'a, const O: u8> FSEL40_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL40_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL40_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_0"] + #[inline(always)] + pub fn pwm0_0(self) -> &'a mut W { + self.variant(FSEL40_A::PWM0_0) + } + #[doc = "Pin is connected to SD4"] + #[inline(always)] + pub fn sd4(self) -> &'a mut W { + self.variant(FSEL40_A::SD4) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL40_A::RESERVED4) + } + #[doc = "Pin is connected to TXD1"] + #[inline(always)] + pub fn txd1(self) -> &'a mut W { + self.variant(FSEL40_A::TXD1) + } +} +#[doc = "Field `FSEL41` reader - Function Select 41"] +pub type FSEL41_R = crate::FieldReader; +#[doc = "Function Select 41"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL41_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SD5"] + SD5 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RXD1"] + RXD1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL41_A) -> Self { + variant as _ + } +} +impl FSEL41_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL41_A { + match self.bits { + 0 => FSEL41_A::INPUT, + 1 => FSEL41_A::OUTPUT, + 4 => FSEL41_A::PWM0_1, + 5 => FSEL41_A::SD5, + 6 => FSEL41_A::RESERVED2, + 7 => FSEL41_A::RESERVED3, + 3 => FSEL41_A::RESERVED4, + 2 => FSEL41_A::RXD1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL41_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL41_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL41_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SD5`"] + #[inline(always)] + pub fn is_sd5(&self) -> bool { + *self == FSEL41_A::SD5 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL41_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL41_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL41_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RXD1`"] + #[inline(always)] + pub fn is_rxd1(&self) -> bool { + *self == FSEL41_A::RXD1 + } +} +#[doc = "Field `FSEL41` writer - Function Select 41"] +pub type FSEL41_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL41_A, 3, O>; +impl<'a, const O: u8> FSEL41_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL41_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL41_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL41_A::PWM0_1) + } + #[doc = "Pin is connected to SD5"] + #[inline(always)] + pub fn sd5(self) -> &'a mut W { + self.variant(FSEL41_A::SD5) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL41_A::RESERVED4) + } + #[doc = "Pin is connected to RXD1"] + #[inline(always)] + pub fn rxd1(self) -> &'a mut W { + self.variant(FSEL41_A::RXD1) + } +} +#[doc = "Field `FSEL42` reader - Function Select 42"] +pub type FSEL42_R = crate::FieldReader; +#[doc = "Function Select 42"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL42_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SD6"] + SD6 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to CTS1"] + CTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL42_A) -> Self { + variant as _ + } +} +impl FSEL42_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL42_A { + match self.bits { + 0 => FSEL42_A::INPUT, + 1 => FSEL42_A::OUTPUT, + 4 => FSEL42_A::GPCLK1, + 5 => FSEL42_A::SD6, + 6 => FSEL42_A::RESERVED2, + 7 => FSEL42_A::RESERVED3, + 3 => FSEL42_A::RESERVED4, + 2 => FSEL42_A::CTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL42_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL42_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL42_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SD6`"] + #[inline(always)] + pub fn is_sd6(&self) -> bool { + *self == FSEL42_A::SD6 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL42_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL42_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL42_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `CTS1`"] + #[inline(always)] + pub fn is_cts1(&self) -> bool { + *self == FSEL42_A::CTS1 + } +} +#[doc = "Field `FSEL42` writer - Function Select 42"] +pub type FSEL42_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL42_A, 3, O>; +impl<'a, const O: u8> FSEL42_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL42_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL42_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL42_A::GPCLK1) + } + #[doc = "Pin is connected to SD6"] + #[inline(always)] + pub fn sd6(self) -> &'a mut W { + self.variant(FSEL42_A::SD6) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL42_A::RESERVED4) + } + #[doc = "Pin is connected to CTS1"] + #[inline(always)] + pub fn cts1(self) -> &'a mut W { + self.variant(FSEL42_A::CTS1) + } +} +#[doc = "Field `FSEL43` reader - Function Select 43"] +pub type FSEL43_R = crate::FieldReader; +#[doc = "Function Select 43"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL43_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK2"] + GPCLK2 = 4, + #[doc = "5: Pin is connected to SD7"] + SD7 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Pin is connected to RTS1"] + RTS1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL43_A) -> Self { + variant as _ + } +} +impl FSEL43_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL43_A { + match self.bits { + 0 => FSEL43_A::INPUT, + 1 => FSEL43_A::OUTPUT, + 4 => FSEL43_A::GPCLK2, + 5 => FSEL43_A::SD7, + 6 => FSEL43_A::RESERVED2, + 7 => FSEL43_A::RESERVED3, + 3 => FSEL43_A::RESERVED4, + 2 => FSEL43_A::RTS1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL43_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL43_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK2`"] + #[inline(always)] + pub fn is_gpclk2(&self) -> bool { + *self == FSEL43_A::GPCLK2 + } + #[doc = "Checks if the value of the field is `SD7`"] + #[inline(always)] + pub fn is_sd7(&self) -> bool { + *self == FSEL43_A::SD7 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL43_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL43_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL43_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RTS1`"] + #[inline(always)] + pub fn is_rts1(&self) -> bool { + *self == FSEL43_A::RTS1 + } +} +#[doc = "Field `FSEL43` writer - Function Select 43"] +pub type FSEL43_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL43_A, 3, O>; +impl<'a, const O: u8> FSEL43_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL43_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL43_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK2"] + #[inline(always)] + pub fn gpclk2(self) -> &'a mut W { + self.variant(FSEL43_A::GPCLK2) + } + #[doc = "Pin is connected to SD7"] + #[inline(always)] + pub fn sd7(self) -> &'a mut W { + self.variant(FSEL43_A::SD7) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL43_A::RESERVED4) + } + #[doc = "Pin is connected to RTS1"] + #[inline(always)] + pub fn rts1(self) -> &'a mut W { + self.variant(FSEL43_A::RTS1) + } +} +#[doc = "Field `FSEL44` reader - Function Select 44"] +pub type FSEL44_R = crate::FieldReader; +#[doc = "Function Select 44"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL44_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to GPCLK1"] + GPCLK1 = 4, + #[doc = "5: Pin is connected to SDA0"] + SDA0 = 5, + #[doc = "6: Pin is connected to SDA1"] + SDA1 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL44_A) -> Self { + variant as _ + } +} +impl FSEL44_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL44_A { + match self.bits { + 0 => FSEL44_A::INPUT, + 1 => FSEL44_A::OUTPUT, + 4 => FSEL44_A::GPCLK1, + 5 => FSEL44_A::SDA0, + 6 => FSEL44_A::SDA1, + 7 => FSEL44_A::RESERVED3, + 3 => FSEL44_A::RESERVED4, + 2 => FSEL44_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL44_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL44_A::OUTPUT + } + #[doc = "Checks if the value of the field is `GPCLK1`"] + #[inline(always)] + pub fn is_gpclk1(&self) -> bool { + *self == FSEL44_A::GPCLK1 + } + #[doc = "Checks if the value of the field is `SDA0`"] + #[inline(always)] + pub fn is_sda0(&self) -> bool { + *self == FSEL44_A::SDA0 + } + #[doc = "Checks if the value of the field is `SDA1`"] + #[inline(always)] + pub fn is_sda1(&self) -> bool { + *self == FSEL44_A::SDA1 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL44_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL44_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL44_A::RESERVED5 + } +} +#[doc = "Field `FSEL44` writer - Function Select 44"] +pub type FSEL44_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL44_A, 3, O>; +impl<'a, const O: u8> FSEL44_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL44_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL44_A::OUTPUT) + } + #[doc = "Pin is connected to GPCLK1"] + #[inline(always)] + pub fn gpclk1(self) -> &'a mut W { + self.variant(FSEL44_A::GPCLK1) + } + #[doc = "Pin is connected to SDA0"] + #[inline(always)] + pub fn sda0(self) -> &'a mut W { + self.variant(FSEL44_A::SDA0) + } + #[doc = "Pin is connected to SDA1"] + #[inline(always)] + pub fn sda1(self) -> &'a mut W { + self.variant(FSEL44_A::SDA1) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL44_A::RESERVED5) + } +} +#[doc = "Field `FSEL45` reader - Function Select 45"] +pub type FSEL45_R = crate::FieldReader; +#[doc = "Function Select 45"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL45_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Pin is connected to PWM0_1"] + PWM0_1 = 4, + #[doc = "5: Pin is connected to SCL0"] + SCL0 = 5, + #[doc = "6: Pin is connected to SCL1"] + SCL1 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL45_A) -> Self { + variant as _ + } +} +impl FSEL45_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL45_A { + match self.bits { + 0 => FSEL45_A::INPUT, + 1 => FSEL45_A::OUTPUT, + 4 => FSEL45_A::PWM0_1, + 5 => FSEL45_A::SCL0, + 6 => FSEL45_A::SCL1, + 7 => FSEL45_A::RESERVED3, + 3 => FSEL45_A::RESERVED4, + 2 => FSEL45_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL45_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL45_A::OUTPUT + } + #[doc = "Checks if the value of the field is `PWM0_1`"] + #[inline(always)] + pub fn is_pwm0_1(&self) -> bool { + *self == FSEL45_A::PWM0_1 + } + #[doc = "Checks if the value of the field is `SCL0`"] + #[inline(always)] + pub fn is_scl0(&self) -> bool { + *self == FSEL45_A::SCL0 + } + #[doc = "Checks if the value of the field is `SCL1`"] + #[inline(always)] + pub fn is_scl1(&self) -> bool { + *self == FSEL45_A::SCL1 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL45_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL45_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL45_A::RESERVED5 + } +} +#[doc = "Field `FSEL45` writer - Function Select 45"] +pub type FSEL45_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL45_A, 3, O>; +impl<'a, const O: u8> FSEL45_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL45_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL45_A::OUTPUT) + } + #[doc = "Pin is connected to PWM0_1"] + #[inline(always)] + pub fn pwm0_1(self) -> &'a mut W { + self.variant(FSEL45_A::PWM0_1) + } + #[doc = "Pin is connected to SCL0"] + #[inline(always)] + pub fn scl0(self) -> &'a mut W { + self.variant(FSEL45_A::SCL0) + } + #[doc = "Pin is connected to SCL1"] + #[inline(always)] + pub fn scl1(self) -> &'a mut W { + self.variant(FSEL45_A::SCL1) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL45_A::RESERVED5) + } +} +#[doc = "Field `FSEL46` reader - Function Select 46"] +pub type FSEL46_R = crate::FieldReader; +#[doc = "Function Select 46"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL46_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL46_A) -> Self { + variant as _ + } +} +impl FSEL46_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL46_A { + match self.bits { + 0 => FSEL46_A::INPUT, + 1 => FSEL46_A::OUTPUT, + 4 => FSEL46_A::RESERVED0, + 5 => FSEL46_A::RESERVED1, + 6 => FSEL46_A::RESERVED2, + 7 => FSEL46_A::RESERVED3, + 3 => FSEL46_A::RESERVED4, + 2 => FSEL46_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL46_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL46_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL46_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL46_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL46_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL46_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL46_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL46_A::RESERVED5 + } +} +#[doc = "Field `FSEL46` writer - Function Select 46"] +pub type FSEL46_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL46_A, 3, O>; +impl<'a, const O: u8> FSEL46_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL46_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL46_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL46_A::RESERVED5) + } +} +#[doc = "Field `FSEL47` reader - Function Select 47"] +pub type FSEL47_R = crate::FieldReader; +#[doc = "Function Select 47"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL47_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Alt function 3 reserved"] + RESERVED3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL47_A) -> Self { + variant as _ + } +} +impl FSEL47_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL47_A { + match self.bits { + 0 => FSEL47_A::INPUT, + 1 => FSEL47_A::OUTPUT, + 4 => FSEL47_A::RESERVED0, + 5 => FSEL47_A::RESERVED1, + 6 => FSEL47_A::RESERVED2, + 7 => FSEL47_A::RESERVED3, + 3 => FSEL47_A::RESERVED4, + 2 => FSEL47_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL47_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL47_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL47_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL47_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL47_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `RESERVED3`"] + #[inline(always)] + pub fn is_reserved3(&self) -> bool { + *self == FSEL47_A::RESERVED3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL47_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL47_A::RESERVED5 + } +} +#[doc = "Field `FSEL47` writer - Function Select 47"] +pub type FSEL47_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL47_A, 3, O>; +impl<'a, const O: u8> FSEL47_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL47_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL47_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED2) + } + #[doc = "Alt function 3 reserved"] + #[inline(always)] + pub fn reserved3(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL47_A::RESERVED5) + } +} +#[doc = "Field `FSEL48` reader - Function Select 48"] +pub type FSEL48_R = crate::FieldReader; +#[doc = "Function Select 48"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL48_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CLK"] + SD1_CLK = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL48_A) -> Self { + variant as _ + } +} +impl FSEL48_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL48_A { + match self.bits { + 0 => FSEL48_A::INPUT, + 1 => FSEL48_A::OUTPUT, + 4 => FSEL48_A::RESERVED0, + 5 => FSEL48_A::RESERVED1, + 6 => FSEL48_A::RESERVED2, + 7 => FSEL48_A::SD1_CLK, + 3 => FSEL48_A::RESERVED4, + 2 => FSEL48_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL48_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL48_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL48_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL48_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL48_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[inline(always)] + pub fn is_sd1_clk(&self) -> bool { + *self == FSEL48_A::SD1_CLK + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL48_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL48_A::RESERVED5 + } +} +#[doc = "Field `FSEL48` writer - Function Select 48"] +pub type FSEL48_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL48_A, 3, O>; +impl<'a, const O: u8> FSEL48_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL48_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL48_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CLK"] + #[inline(always)] + pub fn sd1_clk(self) -> &'a mut W { + self.variant(FSEL48_A::SD1_CLK) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL48_A::RESERVED5) + } +} +#[doc = "Field `FSEL49` reader - Function Select 49"] +pub type FSEL49_R = crate::FieldReader; +#[doc = "Function Select 49"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL49_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_CMD"] + SD1_CMD = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL49_A) -> Self { + variant as _ + } +} +impl FSEL49_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL49_A { + match self.bits { + 0 => FSEL49_A::INPUT, + 1 => FSEL49_A::OUTPUT, + 4 => FSEL49_A::RESERVED0, + 5 => FSEL49_A::RESERVED1, + 6 => FSEL49_A::RESERVED2, + 7 => FSEL49_A::SD1_CMD, + 3 => FSEL49_A::RESERVED4, + 2 => FSEL49_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL49_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL49_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL49_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL49_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL49_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[inline(always)] + pub fn is_sd1_cmd(&self) -> bool { + *self == FSEL49_A::SD1_CMD + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL49_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL49_A::RESERVED5 + } +} +#[doc = "Field `FSEL49` writer - Function Select 49"] +pub type FSEL49_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL49_A, 3, O>; +impl<'a, const O: u8> FSEL49_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL49_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL49_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_CMD"] + #[inline(always)] + pub fn sd1_cmd(self) -> &'a mut W { + self.variant(FSEL49_A::SD1_CMD) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL49_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 40"] + #[inline(always)] + pub fn fsel40(&self) -> FSEL40_R { + FSEL40_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 41"] + #[inline(always)] + pub fn fsel41(&self) -> FSEL41_R { + FSEL41_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 42"] + #[inline(always)] + pub fn fsel42(&self) -> FSEL42_R { + FSEL42_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 43"] + #[inline(always)] + pub fn fsel43(&self) -> FSEL43_R { + FSEL43_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - Function Select 44"] + #[inline(always)] + pub fn fsel44(&self) -> FSEL44_R { + FSEL44_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Function Select 45"] + #[inline(always)] + pub fn fsel45(&self) -> FSEL45_R { + FSEL45_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Function Select 46"] + #[inline(always)] + pub fn fsel46(&self) -> FSEL46_R { + FSEL46_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - Function Select 47"] + #[inline(always)] + pub fn fsel47(&self) -> FSEL47_R { + FSEL47_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - Function Select 48"] + #[inline(always)] + pub fn fsel48(&self) -> FSEL48_R { + FSEL48_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 27:29 - Function Select 49"] + #[inline(always)] + pub fn fsel49(&self) -> FSEL49_R { + FSEL49_R::new(((self.bits >> 27) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 40"] + #[inline(always)] + #[must_use] + pub fn fsel40(&mut self) -> FSEL40_W<0> { + FSEL40_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 41"] + #[inline(always)] + #[must_use] + pub fn fsel41(&mut self) -> FSEL41_W<3> { + FSEL41_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 42"] + #[inline(always)] + #[must_use] + pub fn fsel42(&mut self) -> FSEL42_W<6> { + FSEL42_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 43"] + #[inline(always)] + #[must_use] + pub fn fsel43(&mut self) -> FSEL43_W<9> { + FSEL43_W::new(self) + } + #[doc = "Bits 12:14 - Function Select 44"] + #[inline(always)] + #[must_use] + pub fn fsel44(&mut self) -> FSEL44_W<12> { + FSEL44_W::new(self) + } + #[doc = "Bits 15:17 - Function Select 45"] + #[inline(always)] + #[must_use] + pub fn fsel45(&mut self) -> FSEL45_W<15> { + FSEL45_W::new(self) + } + #[doc = "Bits 18:20 - Function Select 46"] + #[inline(always)] + #[must_use] + pub fn fsel46(&mut self) -> FSEL46_W<18> { + FSEL46_W::new(self) + } + #[doc = "Bits 21:23 - Function Select 47"] + #[inline(always)] + #[must_use] + pub fn fsel47(&mut self) -> FSEL47_W<21> { + FSEL47_W::new(self) + } + #[doc = "Bits 24:26 - Function Select 48"] + #[inline(always)] + #[must_use] + pub fn fsel48(&mut self) -> FSEL48_W<24> { + FSEL48_W::new(self) + } + #[doc = "Bits 27:29 - Function Select 49"] + #[inline(always)] + #[must_use] + pub fn fsel49(&mut self) -> FSEL49_W<27> { + FSEL49_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel4](index.html) module"] +pub struct GPFSEL4_SPEC; +impl crate::RegisterSpec for GPFSEL4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel4::R](R) reader structure"] +impl crate::Readable for GPFSEL4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel4::W](W) writer structure"] +impl crate::Writable for GPFSEL4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel5.rs b/crates/bcm2837-lpa/src/gpio/gpfsel5.rs new file mode 100644 index 0000000..7195017 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpfsel5.rs @@ -0,0 +1,629 @@ +#[doc = "Register `GPFSEL5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPFSEL5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSEL50` reader - Function Select 50"] +pub type FSEL50_R = crate::FieldReader; +#[doc = "Function Select 50"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL50_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT0"] + SD1_DAT0 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL50_A) -> Self { + variant as _ + } +} +impl FSEL50_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL50_A { + match self.bits { + 0 => FSEL50_A::INPUT, + 1 => FSEL50_A::OUTPUT, + 4 => FSEL50_A::RESERVED0, + 5 => FSEL50_A::RESERVED1, + 6 => FSEL50_A::RESERVED2, + 7 => FSEL50_A::SD1_DAT0, + 3 => FSEL50_A::RESERVED4, + 2 => FSEL50_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL50_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL50_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL50_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL50_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL50_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[inline(always)] + pub fn is_sd1_dat0(&self) -> bool { + *self == FSEL50_A::SD1_DAT0 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL50_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL50_A::RESERVED5 + } +} +#[doc = "Field `FSEL50` writer - Function Select 50"] +pub type FSEL50_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL50_A, 3, O>; +impl<'a, const O: u8> FSEL50_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL50_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL50_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT0"] + #[inline(always)] + pub fn sd1_dat0(self) -> &'a mut W { + self.variant(FSEL50_A::SD1_DAT0) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL50_A::RESERVED5) + } +} +#[doc = "Field `FSEL51` reader - Function Select 51"] +pub type FSEL51_R = crate::FieldReader; +#[doc = "Function Select 51"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL51_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT1"] + SD1_DAT1 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL51_A) -> Self { + variant as _ + } +} +impl FSEL51_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL51_A { + match self.bits { + 0 => FSEL51_A::INPUT, + 1 => FSEL51_A::OUTPUT, + 4 => FSEL51_A::RESERVED0, + 5 => FSEL51_A::RESERVED1, + 6 => FSEL51_A::RESERVED2, + 7 => FSEL51_A::SD1_DAT1, + 3 => FSEL51_A::RESERVED4, + 2 => FSEL51_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL51_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL51_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL51_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL51_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL51_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[inline(always)] + pub fn is_sd1_dat1(&self) -> bool { + *self == FSEL51_A::SD1_DAT1 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL51_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL51_A::RESERVED5 + } +} +#[doc = "Field `FSEL51` writer - Function Select 51"] +pub type FSEL51_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL51_A, 3, O>; +impl<'a, const O: u8> FSEL51_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL51_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL51_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT1"] + #[inline(always)] + pub fn sd1_dat1(self) -> &'a mut W { + self.variant(FSEL51_A::SD1_DAT1) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL51_A::RESERVED5) + } +} +#[doc = "Field `FSEL52` reader - Function Select 52"] +pub type FSEL52_R = crate::FieldReader; +#[doc = "Function Select 52"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL52_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT2"] + SD1_DAT2 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL52_A) -> Self { + variant as _ + } +} +impl FSEL52_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL52_A { + match self.bits { + 0 => FSEL52_A::INPUT, + 1 => FSEL52_A::OUTPUT, + 4 => FSEL52_A::RESERVED0, + 5 => FSEL52_A::RESERVED1, + 6 => FSEL52_A::RESERVED2, + 7 => FSEL52_A::SD1_DAT2, + 3 => FSEL52_A::RESERVED4, + 2 => FSEL52_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL52_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL52_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL52_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL52_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL52_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[inline(always)] + pub fn is_sd1_dat2(&self) -> bool { + *self == FSEL52_A::SD1_DAT2 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL52_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL52_A::RESERVED5 + } +} +#[doc = "Field `FSEL52` writer - Function Select 52"] +pub type FSEL52_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL52_A, 3, O>; +impl<'a, const O: u8> FSEL52_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL52_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL52_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT2"] + #[inline(always)] + pub fn sd1_dat2(self) -> &'a mut W { + self.variant(FSEL52_A::SD1_DAT2) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL52_A::RESERVED5) + } +} +#[doc = "Field `FSEL53` reader - Function Select 53"] +pub type FSEL53_R = crate::FieldReader; +#[doc = "Function Select 53"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSEL53_A { + #[doc = "0: Pin is an input"] + INPUT = 0, + #[doc = "1: Pin is an output"] + OUTPUT = 1, + #[doc = "4: Alt function 0 reserved"] + RESERVED0 = 4, + #[doc = "5: Alt function 1 reserved"] + RESERVED1 = 5, + #[doc = "6: Alt function 2 reserved"] + RESERVED2 = 6, + #[doc = "7: Pin is connected to SD1_DAT3"] + SD1_DAT3 = 7, + #[doc = "3: Alt function 4 reserved"] + RESERVED4 = 3, + #[doc = "2: Alt function 5 reserved"] + RESERVED5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSEL53_A) -> Self { + variant as _ + } +} +impl FSEL53_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSEL53_A { + match self.bits { + 0 => FSEL53_A::INPUT, + 1 => FSEL53_A::OUTPUT, + 4 => FSEL53_A::RESERVED0, + 5 => FSEL53_A::RESERVED1, + 6 => FSEL53_A::RESERVED2, + 7 => FSEL53_A::SD1_DAT3, + 3 => FSEL53_A::RESERVED4, + 2 => FSEL53_A::RESERVED5, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INPUT`"] + #[inline(always)] + pub fn is_input(&self) -> bool { + *self == FSEL53_A::INPUT + } + #[doc = "Checks if the value of the field is `OUTPUT`"] + #[inline(always)] + pub fn is_output(&self) -> bool { + *self == FSEL53_A::OUTPUT + } + #[doc = "Checks if the value of the field is `RESERVED0`"] + #[inline(always)] + pub fn is_reserved0(&self) -> bool { + *self == FSEL53_A::RESERVED0 + } + #[doc = "Checks if the value of the field is `RESERVED1`"] + #[inline(always)] + pub fn is_reserved1(&self) -> bool { + *self == FSEL53_A::RESERVED1 + } + #[doc = "Checks if the value of the field is `RESERVED2`"] + #[inline(always)] + pub fn is_reserved2(&self) -> bool { + *self == FSEL53_A::RESERVED2 + } + #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[inline(always)] + pub fn is_sd1_dat3(&self) -> bool { + *self == FSEL53_A::SD1_DAT3 + } + #[doc = "Checks if the value of the field is `RESERVED4`"] + #[inline(always)] + pub fn is_reserved4(&self) -> bool { + *self == FSEL53_A::RESERVED4 + } + #[doc = "Checks if the value of the field is `RESERVED5`"] + #[inline(always)] + pub fn is_reserved5(&self) -> bool { + *self == FSEL53_A::RESERVED5 + } +} +#[doc = "Field `FSEL53` writer - Function Select 53"] +pub type FSEL53_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL53_A, 3, O>; +impl<'a, const O: u8> FSEL53_W<'a, O> { + #[doc = "Pin is an input"] + #[inline(always)] + pub fn input(self) -> &'a mut W { + self.variant(FSEL53_A::INPUT) + } + #[doc = "Pin is an output"] + #[inline(always)] + pub fn output(self) -> &'a mut W { + self.variant(FSEL53_A::OUTPUT) + } + #[doc = "Alt function 0 reserved"] + #[inline(always)] + pub fn reserved0(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED0) + } + #[doc = "Alt function 1 reserved"] + #[inline(always)] + pub fn reserved1(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED1) + } + #[doc = "Alt function 2 reserved"] + #[inline(always)] + pub fn reserved2(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED2) + } + #[doc = "Pin is connected to SD1_DAT3"] + #[inline(always)] + pub fn sd1_dat3(self) -> &'a mut W { + self.variant(FSEL53_A::SD1_DAT3) + } + #[doc = "Alt function 4 reserved"] + #[inline(always)] + pub fn reserved4(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED4) + } + #[doc = "Alt function 5 reserved"] + #[inline(always)] + pub fn reserved5(self) -> &'a mut W { + self.variant(FSEL53_A::RESERVED5) + } +} +impl R { + #[doc = "Bits 0:2 - Function Select 50"] + #[inline(always)] + pub fn fsel50(&self) -> FSEL50_R { + FSEL50_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Function Select 51"] + #[inline(always)] + pub fn fsel51(&self) -> FSEL51_R { + FSEL51_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Function Select 52"] + #[inline(always)] + pub fn fsel52(&self) -> FSEL52_R { + FSEL52_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - Function Select 53"] + #[inline(always)] + pub fn fsel53(&self) -> FSEL53_R { + FSEL53_R::new(((self.bits >> 9) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Function Select 50"] + #[inline(always)] + #[must_use] + pub fn fsel50(&mut self) -> FSEL50_W<0> { + FSEL50_W::new(self) + } + #[doc = "Bits 3:5 - Function Select 51"] + #[inline(always)] + #[must_use] + pub fn fsel51(&mut self) -> FSEL51_W<3> { + FSEL51_W::new(self) + } + #[doc = "Bits 6:8 - Function Select 52"] + #[inline(always)] + #[must_use] + pub fn fsel52(&mut self) -> FSEL52_W<6> { + FSEL52_W::new(self) + } + #[doc = "Bits 9:11 - Function Select 53"] + #[inline(always)] + #[must_use] + pub fn fsel53(&mut self) -> FSEL53_W<9> { + FSEL53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Function Select 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel5](index.html) module"] +pub struct GPFSEL5_SPEC; +impl crate::RegisterSpec for GPFSEL5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpfsel5::R](R) reader structure"] +impl crate::Readable for GPFSEL5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpfsel5::W](W) writer structure"] +impl crate::Writable for GPFSEL5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gphen0.rs b/crates/bcm2837-lpa/src/gpio/gphen0.rs new file mode 100644 index 0000000..b45a414 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gphen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPHEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPHEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HEN0` reader - High detect enabled 0"] +pub type HEN0_R = crate::BitReader; +#[doc = "Field `HEN0` writer - High detect enabled 0"] +pub type HEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN1` reader - High detect enabled 1"] +pub type HEN1_R = crate::BitReader; +#[doc = "Field `HEN1` writer - High detect enabled 1"] +pub type HEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN2` reader - High detect enabled 2"] +pub type HEN2_R = crate::BitReader; +#[doc = "Field `HEN2` writer - High detect enabled 2"] +pub type HEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN3` reader - High detect enabled 3"] +pub type HEN3_R = crate::BitReader; +#[doc = "Field `HEN3` writer - High detect enabled 3"] +pub type HEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN4` reader - High detect enabled 4"] +pub type HEN4_R = crate::BitReader; +#[doc = "Field `HEN4` writer - High detect enabled 4"] +pub type HEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN5` reader - High detect enabled 5"] +pub type HEN5_R = crate::BitReader; +#[doc = "Field `HEN5` writer - High detect enabled 5"] +pub type HEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN6` reader - High detect enabled 6"] +pub type HEN6_R = crate::BitReader; +#[doc = "Field `HEN6` writer - High detect enabled 6"] +pub type HEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN7` reader - High detect enabled 7"] +pub type HEN7_R = crate::BitReader; +#[doc = "Field `HEN7` writer - High detect enabled 7"] +pub type HEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN8` reader - High detect enabled 8"] +pub type HEN8_R = crate::BitReader; +#[doc = "Field `HEN8` writer - High detect enabled 8"] +pub type HEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN9` reader - High detect enabled 9"] +pub type HEN9_R = crate::BitReader; +#[doc = "Field `HEN9` writer - High detect enabled 9"] +pub type HEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN10` reader - High detect enabled 10"] +pub type HEN10_R = crate::BitReader; +#[doc = "Field `HEN10` writer - High detect enabled 10"] +pub type HEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN11` reader - High detect enabled 11"] +pub type HEN11_R = crate::BitReader; +#[doc = "Field `HEN11` writer - High detect enabled 11"] +pub type HEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN12` reader - High detect enabled 12"] +pub type HEN12_R = crate::BitReader; +#[doc = "Field `HEN12` writer - High detect enabled 12"] +pub type HEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN13` reader - High detect enabled 13"] +pub type HEN13_R = crate::BitReader; +#[doc = "Field `HEN13` writer - High detect enabled 13"] +pub type HEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN14` reader - High detect enabled 14"] +pub type HEN14_R = crate::BitReader; +#[doc = "Field `HEN14` writer - High detect enabled 14"] +pub type HEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN15` reader - High detect enabled 15"] +pub type HEN15_R = crate::BitReader; +#[doc = "Field `HEN15` writer - High detect enabled 15"] +pub type HEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN16` reader - High detect enabled 16"] +pub type HEN16_R = crate::BitReader; +#[doc = "Field `HEN16` writer - High detect enabled 16"] +pub type HEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN17` reader - High detect enabled 17"] +pub type HEN17_R = crate::BitReader; +#[doc = "Field `HEN17` writer - High detect enabled 17"] +pub type HEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN18` reader - High detect enabled 18"] +pub type HEN18_R = crate::BitReader; +#[doc = "Field `HEN18` writer - High detect enabled 18"] +pub type HEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN19` reader - High detect enabled 19"] +pub type HEN19_R = crate::BitReader; +#[doc = "Field `HEN19` writer - High detect enabled 19"] +pub type HEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN20` reader - High detect enabled 20"] +pub type HEN20_R = crate::BitReader; +#[doc = "Field `HEN20` writer - High detect enabled 20"] +pub type HEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN21` reader - High detect enabled 21"] +pub type HEN21_R = crate::BitReader; +#[doc = "Field `HEN21` writer - High detect enabled 21"] +pub type HEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN22` reader - High detect enabled 22"] +pub type HEN22_R = crate::BitReader; +#[doc = "Field `HEN22` writer - High detect enabled 22"] +pub type HEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN23` reader - High detect enabled 23"] +pub type HEN23_R = crate::BitReader; +#[doc = "Field `HEN23` writer - High detect enabled 23"] +pub type HEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN24` reader - High detect enabled 24"] +pub type HEN24_R = crate::BitReader; +#[doc = "Field `HEN24` writer - High detect enabled 24"] +pub type HEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN25` reader - High detect enabled 25"] +pub type HEN25_R = crate::BitReader; +#[doc = "Field `HEN25` writer - High detect enabled 25"] +pub type HEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN26` reader - High detect enabled 26"] +pub type HEN26_R = crate::BitReader; +#[doc = "Field `HEN26` writer - High detect enabled 26"] +pub type HEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN27` reader - High detect enabled 27"] +pub type HEN27_R = crate::BitReader; +#[doc = "Field `HEN27` writer - High detect enabled 27"] +pub type HEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN28` reader - High detect enabled 28"] +pub type HEN28_R = crate::BitReader; +#[doc = "Field `HEN28` writer - High detect enabled 28"] +pub type HEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN29` reader - High detect enabled 29"] +pub type HEN29_R = crate::BitReader; +#[doc = "Field `HEN29` writer - High detect enabled 29"] +pub type HEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN30` reader - High detect enabled 30"] +pub type HEN30_R = crate::BitReader; +#[doc = "Field `HEN30` writer - High detect enabled 30"] +pub type HEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +#[doc = "Field `HEN31` reader - High detect enabled 31"] +pub type HEN31_R = crate::BitReader; +#[doc = "Field `HEN31` writer - High detect enabled 31"] +pub type HEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - High detect enabled 0"] + #[inline(always)] + pub fn hen0(&self) -> HEN0_R { + HEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - High detect enabled 1"] + #[inline(always)] + pub fn hen1(&self) -> HEN1_R { + HEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - High detect enabled 2"] + #[inline(always)] + pub fn hen2(&self) -> HEN2_R { + HEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - High detect enabled 3"] + #[inline(always)] + pub fn hen3(&self) -> HEN3_R { + HEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - High detect enabled 4"] + #[inline(always)] + pub fn hen4(&self) -> HEN4_R { + HEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - High detect enabled 5"] + #[inline(always)] + pub fn hen5(&self) -> HEN5_R { + HEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - High detect enabled 6"] + #[inline(always)] + pub fn hen6(&self) -> HEN6_R { + HEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - High detect enabled 7"] + #[inline(always)] + pub fn hen7(&self) -> HEN7_R { + HEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - High detect enabled 8"] + #[inline(always)] + pub fn hen8(&self) -> HEN8_R { + HEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High detect enabled 9"] + #[inline(always)] + pub fn hen9(&self) -> HEN9_R { + HEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High detect enabled 10"] + #[inline(always)] + pub fn hen10(&self) -> HEN10_R { + HEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - High detect enabled 11"] + #[inline(always)] + pub fn hen11(&self) -> HEN11_R { + HEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - High detect enabled 12"] + #[inline(always)] + pub fn hen12(&self) -> HEN12_R { + HEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - High detect enabled 13"] + #[inline(always)] + pub fn hen13(&self) -> HEN13_R { + HEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High detect enabled 14"] + #[inline(always)] + pub fn hen14(&self) -> HEN14_R { + HEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - High detect enabled 15"] + #[inline(always)] + pub fn hen15(&self) -> HEN15_R { + HEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High detect enabled 16"] + #[inline(always)] + pub fn hen16(&self) -> HEN16_R { + HEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - High detect enabled 17"] + #[inline(always)] + pub fn hen17(&self) -> HEN17_R { + HEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - High detect enabled 18"] + #[inline(always)] + pub fn hen18(&self) -> HEN18_R { + HEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - High detect enabled 19"] + #[inline(always)] + pub fn hen19(&self) -> HEN19_R { + HEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - High detect enabled 20"] + #[inline(always)] + pub fn hen20(&self) -> HEN20_R { + HEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - High detect enabled 21"] + #[inline(always)] + pub fn hen21(&self) -> HEN21_R { + HEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - High detect enabled 22"] + #[inline(always)] + pub fn hen22(&self) -> HEN22_R { + HEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - High detect enabled 23"] + #[inline(always)] + pub fn hen23(&self) -> HEN23_R { + HEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - High detect enabled 24"] + #[inline(always)] + pub fn hen24(&self) -> HEN24_R { + HEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - High detect enabled 25"] + #[inline(always)] + pub fn hen25(&self) -> HEN25_R { + HEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - High detect enabled 26"] + #[inline(always)] + pub fn hen26(&self) -> HEN26_R { + HEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - High detect enabled 27"] + #[inline(always)] + pub fn hen27(&self) -> HEN27_R { + HEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - High detect enabled 28"] + #[inline(always)] + pub fn hen28(&self) -> HEN28_R { + HEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - High detect enabled 29"] + #[inline(always)] + pub fn hen29(&self) -> HEN29_R { + HEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - High detect enabled 30"] + #[inline(always)] + pub fn hen30(&self) -> HEN30_R { + HEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - High detect enabled 31"] + #[inline(always)] + pub fn hen31(&self) -> HEN31_R { + HEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - High detect enabled 0"] + #[inline(always)] + #[must_use] + pub fn hen0(&mut self) -> HEN0_W<0> { + HEN0_W::new(self) + } + #[doc = "Bit 1 - High detect enabled 1"] + #[inline(always)] + #[must_use] + pub fn hen1(&mut self) -> HEN1_W<1> { + HEN1_W::new(self) + } + #[doc = "Bit 2 - High detect enabled 2"] + #[inline(always)] + #[must_use] + pub fn hen2(&mut self) -> HEN2_W<2> { + HEN2_W::new(self) + } + #[doc = "Bit 3 - High detect enabled 3"] + #[inline(always)] + #[must_use] + pub fn hen3(&mut self) -> HEN3_W<3> { + HEN3_W::new(self) + } + #[doc = "Bit 4 - High detect enabled 4"] + #[inline(always)] + #[must_use] + pub fn hen4(&mut self) -> HEN4_W<4> { + HEN4_W::new(self) + } + #[doc = "Bit 5 - High detect enabled 5"] + #[inline(always)] + #[must_use] + pub fn hen5(&mut self) -> HEN5_W<5> { + HEN5_W::new(self) + } + #[doc = "Bit 6 - High detect enabled 6"] + #[inline(always)] + #[must_use] + pub fn hen6(&mut self) -> HEN6_W<6> { + HEN6_W::new(self) + } + #[doc = "Bit 7 - High detect enabled 7"] + #[inline(always)] + #[must_use] + pub fn hen7(&mut self) -> HEN7_W<7> { + HEN7_W::new(self) + } + #[doc = "Bit 8 - High detect enabled 8"] + #[inline(always)] + #[must_use] + pub fn hen8(&mut self) -> HEN8_W<8> { + HEN8_W::new(self) + } + #[doc = "Bit 9 - High detect enabled 9"] + #[inline(always)] + #[must_use] + pub fn hen9(&mut self) -> HEN9_W<9> { + HEN9_W::new(self) + } + #[doc = "Bit 10 - High detect enabled 10"] + #[inline(always)] + #[must_use] + pub fn hen10(&mut self) -> HEN10_W<10> { + HEN10_W::new(self) + } + #[doc = "Bit 11 - High detect enabled 11"] + #[inline(always)] + #[must_use] + pub fn hen11(&mut self) -> HEN11_W<11> { + HEN11_W::new(self) + } + #[doc = "Bit 12 - High detect enabled 12"] + #[inline(always)] + #[must_use] + pub fn hen12(&mut self) -> HEN12_W<12> { + HEN12_W::new(self) + } + #[doc = "Bit 13 - High detect enabled 13"] + #[inline(always)] + #[must_use] + pub fn hen13(&mut self) -> HEN13_W<13> { + HEN13_W::new(self) + } + #[doc = "Bit 14 - High detect enabled 14"] + #[inline(always)] + #[must_use] + pub fn hen14(&mut self) -> HEN14_W<14> { + HEN14_W::new(self) + } + #[doc = "Bit 15 - High detect enabled 15"] + #[inline(always)] + #[must_use] + pub fn hen15(&mut self) -> HEN15_W<15> { + HEN15_W::new(self) + } + #[doc = "Bit 16 - High detect enabled 16"] + #[inline(always)] + #[must_use] + pub fn hen16(&mut self) -> HEN16_W<16> { + HEN16_W::new(self) + } + #[doc = "Bit 17 - High detect enabled 17"] + #[inline(always)] + #[must_use] + pub fn hen17(&mut self) -> HEN17_W<17> { + HEN17_W::new(self) + } + #[doc = "Bit 18 - High detect enabled 18"] + #[inline(always)] + #[must_use] + pub fn hen18(&mut self) -> HEN18_W<18> { + HEN18_W::new(self) + } + #[doc = "Bit 19 - High detect enabled 19"] + #[inline(always)] + #[must_use] + pub fn hen19(&mut self) -> HEN19_W<19> { + HEN19_W::new(self) + } + #[doc = "Bit 20 - High detect enabled 20"] + #[inline(always)] + #[must_use] + pub fn hen20(&mut self) -> HEN20_W<20> { + HEN20_W::new(self) + } + #[doc = "Bit 21 - High detect enabled 21"] + #[inline(always)] + #[must_use] + pub fn hen21(&mut self) -> HEN21_W<21> { + HEN21_W::new(self) + } + #[doc = "Bit 22 - High detect enabled 22"] + #[inline(always)] + #[must_use] + pub fn hen22(&mut self) -> HEN22_W<22> { + HEN22_W::new(self) + } + #[doc = "Bit 23 - High detect enabled 23"] + #[inline(always)] + #[must_use] + pub fn hen23(&mut self) -> HEN23_W<23> { + HEN23_W::new(self) + } + #[doc = "Bit 24 - High detect enabled 24"] + #[inline(always)] + #[must_use] + pub fn hen24(&mut self) -> HEN24_W<24> { + HEN24_W::new(self) + } + #[doc = "Bit 25 - High detect enabled 25"] + #[inline(always)] + #[must_use] + pub fn hen25(&mut self) -> HEN25_W<25> { + HEN25_W::new(self) + } + #[doc = "Bit 26 - High detect enabled 26"] + #[inline(always)] + #[must_use] + pub fn hen26(&mut self) -> HEN26_W<26> { + HEN26_W::new(self) + } + #[doc = "Bit 27 - High detect enabled 27"] + #[inline(always)] + #[must_use] + pub fn hen27(&mut self) -> HEN27_W<27> { + HEN27_W::new(self) + } + #[doc = "Bit 28 - High detect enabled 28"] + #[inline(always)] + #[must_use] + pub fn hen28(&mut self) -> HEN28_W<28> { + HEN28_W::new(self) + } + #[doc = "Bit 29 - High detect enabled 29"] + #[inline(always)] + #[must_use] + pub fn hen29(&mut self) -> HEN29_W<29> { + HEN29_W::new(self) + } + #[doc = "Bit 30 - High detect enabled 30"] + #[inline(always)] + #[must_use] + pub fn hen30(&mut self) -> HEN30_W<30> { + HEN30_W::new(self) + } + #[doc = "Bit 31 - High detect enabled 31"] + #[inline(always)] + #[must_use] + pub fn hen31(&mut self) -> HEN31_W<31> { + HEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin High Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen0](index.html) module"] +pub struct GPHEN0_SPEC; +impl crate::RegisterSpec for GPHEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gphen0::R](R) reader structure"] +impl crate::Readable for GPHEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gphen0::W](W) writer structure"] +impl crate::Writable for GPHEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gphen1.rs b/crates/bcm2837-lpa/src/gpio/gphen1.rs new file mode 100644 index 0000000..23c512c --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gphen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPHEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPHEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HEN32` reader - High detect enabled 32"] +pub type HEN32_R = crate::BitReader; +#[doc = "Field `HEN32` writer - High detect enabled 32"] +pub type HEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN33` reader - High detect enabled 33"] +pub type HEN33_R = crate::BitReader; +#[doc = "Field `HEN33` writer - High detect enabled 33"] +pub type HEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN34` reader - High detect enabled 34"] +pub type HEN34_R = crate::BitReader; +#[doc = "Field `HEN34` writer - High detect enabled 34"] +pub type HEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN35` reader - High detect enabled 35"] +pub type HEN35_R = crate::BitReader; +#[doc = "Field `HEN35` writer - High detect enabled 35"] +pub type HEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN36` reader - High detect enabled 36"] +pub type HEN36_R = crate::BitReader; +#[doc = "Field `HEN36` writer - High detect enabled 36"] +pub type HEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN37` reader - High detect enabled 37"] +pub type HEN37_R = crate::BitReader; +#[doc = "Field `HEN37` writer - High detect enabled 37"] +pub type HEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN38` reader - High detect enabled 38"] +pub type HEN38_R = crate::BitReader; +#[doc = "Field `HEN38` writer - High detect enabled 38"] +pub type HEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN39` reader - High detect enabled 39"] +pub type HEN39_R = crate::BitReader; +#[doc = "Field `HEN39` writer - High detect enabled 39"] +pub type HEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN40` reader - High detect enabled 40"] +pub type HEN40_R = crate::BitReader; +#[doc = "Field `HEN40` writer - High detect enabled 40"] +pub type HEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN41` reader - High detect enabled 41"] +pub type HEN41_R = crate::BitReader; +#[doc = "Field `HEN41` writer - High detect enabled 41"] +pub type HEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN42` reader - High detect enabled 42"] +pub type HEN42_R = crate::BitReader; +#[doc = "Field `HEN42` writer - High detect enabled 42"] +pub type HEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN43` reader - High detect enabled 43"] +pub type HEN43_R = crate::BitReader; +#[doc = "Field `HEN43` writer - High detect enabled 43"] +pub type HEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN44` reader - High detect enabled 44"] +pub type HEN44_R = crate::BitReader; +#[doc = "Field `HEN44` writer - High detect enabled 44"] +pub type HEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN45` reader - High detect enabled 45"] +pub type HEN45_R = crate::BitReader; +#[doc = "Field `HEN45` writer - High detect enabled 45"] +pub type HEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN46` reader - High detect enabled 46"] +pub type HEN46_R = crate::BitReader; +#[doc = "Field `HEN46` writer - High detect enabled 46"] +pub type HEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN47` reader - High detect enabled 47"] +pub type HEN47_R = crate::BitReader; +#[doc = "Field `HEN47` writer - High detect enabled 47"] +pub type HEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN48` reader - High detect enabled 48"] +pub type HEN48_R = crate::BitReader; +#[doc = "Field `HEN48` writer - High detect enabled 48"] +pub type HEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN49` reader - High detect enabled 49"] +pub type HEN49_R = crate::BitReader; +#[doc = "Field `HEN49` writer - High detect enabled 49"] +pub type HEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN50` reader - High detect enabled 50"] +pub type HEN50_R = crate::BitReader; +#[doc = "Field `HEN50` writer - High detect enabled 50"] +pub type HEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN51` reader - High detect enabled 51"] +pub type HEN51_R = crate::BitReader; +#[doc = "Field `HEN51` writer - High detect enabled 51"] +pub type HEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN52` reader - High detect enabled 52"] +pub type HEN52_R = crate::BitReader; +#[doc = "Field `HEN52` writer - High detect enabled 52"] +pub type HEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +#[doc = "Field `HEN53` reader - High detect enabled 53"] +pub type HEN53_R = crate::BitReader; +#[doc = "Field `HEN53` writer - High detect enabled 53"] +pub type HEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - High detect enabled 32"] + #[inline(always)] + pub fn hen32(&self) -> HEN32_R { + HEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - High detect enabled 33"] + #[inline(always)] + pub fn hen33(&self) -> HEN33_R { + HEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - High detect enabled 34"] + #[inline(always)] + pub fn hen34(&self) -> HEN34_R { + HEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - High detect enabled 35"] + #[inline(always)] + pub fn hen35(&self) -> HEN35_R { + HEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - High detect enabled 36"] + #[inline(always)] + pub fn hen36(&self) -> HEN36_R { + HEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - High detect enabled 37"] + #[inline(always)] + pub fn hen37(&self) -> HEN37_R { + HEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - High detect enabled 38"] + #[inline(always)] + pub fn hen38(&self) -> HEN38_R { + HEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - High detect enabled 39"] + #[inline(always)] + pub fn hen39(&self) -> HEN39_R { + HEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - High detect enabled 40"] + #[inline(always)] + pub fn hen40(&self) -> HEN40_R { + HEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - High detect enabled 41"] + #[inline(always)] + pub fn hen41(&self) -> HEN41_R { + HEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High detect enabled 42"] + #[inline(always)] + pub fn hen42(&self) -> HEN42_R { + HEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - High detect enabled 43"] + #[inline(always)] + pub fn hen43(&self) -> HEN43_R { + HEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - High detect enabled 44"] + #[inline(always)] + pub fn hen44(&self) -> HEN44_R { + HEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - High detect enabled 45"] + #[inline(always)] + pub fn hen45(&self) -> HEN45_R { + HEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High detect enabled 46"] + #[inline(always)] + pub fn hen46(&self) -> HEN46_R { + HEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - High detect enabled 47"] + #[inline(always)] + pub fn hen47(&self) -> HEN47_R { + HEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - High detect enabled 48"] + #[inline(always)] + pub fn hen48(&self) -> HEN48_R { + HEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - High detect enabled 49"] + #[inline(always)] + pub fn hen49(&self) -> HEN49_R { + HEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - High detect enabled 50"] + #[inline(always)] + pub fn hen50(&self) -> HEN50_R { + HEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - High detect enabled 51"] + #[inline(always)] + pub fn hen51(&self) -> HEN51_R { + HEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - High detect enabled 52"] + #[inline(always)] + pub fn hen52(&self) -> HEN52_R { + HEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - High detect enabled 53"] + #[inline(always)] + pub fn hen53(&self) -> HEN53_R { + HEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - High detect enabled 32"] + #[inline(always)] + #[must_use] + pub fn hen32(&mut self) -> HEN32_W<0> { + HEN32_W::new(self) + } + #[doc = "Bit 1 - High detect enabled 33"] + #[inline(always)] + #[must_use] + pub fn hen33(&mut self) -> HEN33_W<1> { + HEN33_W::new(self) + } + #[doc = "Bit 2 - High detect enabled 34"] + #[inline(always)] + #[must_use] + pub fn hen34(&mut self) -> HEN34_W<2> { + HEN34_W::new(self) + } + #[doc = "Bit 3 - High detect enabled 35"] + #[inline(always)] + #[must_use] + pub fn hen35(&mut self) -> HEN35_W<3> { + HEN35_W::new(self) + } + #[doc = "Bit 4 - High detect enabled 36"] + #[inline(always)] + #[must_use] + pub fn hen36(&mut self) -> HEN36_W<4> { + HEN36_W::new(self) + } + #[doc = "Bit 5 - High detect enabled 37"] + #[inline(always)] + #[must_use] + pub fn hen37(&mut self) -> HEN37_W<5> { + HEN37_W::new(self) + } + #[doc = "Bit 6 - High detect enabled 38"] + #[inline(always)] + #[must_use] + pub fn hen38(&mut self) -> HEN38_W<6> { + HEN38_W::new(self) + } + #[doc = "Bit 7 - High detect enabled 39"] + #[inline(always)] + #[must_use] + pub fn hen39(&mut self) -> HEN39_W<7> { + HEN39_W::new(self) + } + #[doc = "Bit 8 - High detect enabled 40"] + #[inline(always)] + #[must_use] + pub fn hen40(&mut self) -> HEN40_W<8> { + HEN40_W::new(self) + } + #[doc = "Bit 9 - High detect enabled 41"] + #[inline(always)] + #[must_use] + pub fn hen41(&mut self) -> HEN41_W<9> { + HEN41_W::new(self) + } + #[doc = "Bit 10 - High detect enabled 42"] + #[inline(always)] + #[must_use] + pub fn hen42(&mut self) -> HEN42_W<10> { + HEN42_W::new(self) + } + #[doc = "Bit 11 - High detect enabled 43"] + #[inline(always)] + #[must_use] + pub fn hen43(&mut self) -> HEN43_W<11> { + HEN43_W::new(self) + } + #[doc = "Bit 12 - High detect enabled 44"] + #[inline(always)] + #[must_use] + pub fn hen44(&mut self) -> HEN44_W<12> { + HEN44_W::new(self) + } + #[doc = "Bit 13 - High detect enabled 45"] + #[inline(always)] + #[must_use] + pub fn hen45(&mut self) -> HEN45_W<13> { + HEN45_W::new(self) + } + #[doc = "Bit 14 - High detect enabled 46"] + #[inline(always)] + #[must_use] + pub fn hen46(&mut self) -> HEN46_W<14> { + HEN46_W::new(self) + } + #[doc = "Bit 15 - High detect enabled 47"] + #[inline(always)] + #[must_use] + pub fn hen47(&mut self) -> HEN47_W<15> { + HEN47_W::new(self) + } + #[doc = "Bit 16 - High detect enabled 48"] + #[inline(always)] + #[must_use] + pub fn hen48(&mut self) -> HEN48_W<16> { + HEN48_W::new(self) + } + #[doc = "Bit 17 - High detect enabled 49"] + #[inline(always)] + #[must_use] + pub fn hen49(&mut self) -> HEN49_W<17> { + HEN49_W::new(self) + } + #[doc = "Bit 18 - High detect enabled 50"] + #[inline(always)] + #[must_use] + pub fn hen50(&mut self) -> HEN50_W<18> { + HEN50_W::new(self) + } + #[doc = "Bit 19 - High detect enabled 51"] + #[inline(always)] + #[must_use] + pub fn hen51(&mut self) -> HEN51_W<19> { + HEN51_W::new(self) + } + #[doc = "Bit 20 - High detect enabled 52"] + #[inline(always)] + #[must_use] + pub fn hen52(&mut self) -> HEN52_W<20> { + HEN52_W::new(self) + } + #[doc = "Bit 21 - High detect enabled 53"] + #[inline(always)] + #[must_use] + pub fn hen53(&mut self) -> HEN53_W<21> { + HEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin High Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen1](index.html) module"] +pub struct GPHEN1_SPEC; +impl crate::RegisterSpec for GPHEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gphen1::R](R) reader structure"] +impl crate::Readable for GPHEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gphen1::W](W) writer structure"] +impl crate::Writable for GPHEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs new file mode 100644 index 0000000..12b55c2 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs @@ -0,0 +1,363 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL0` reader - Resistor select for 0"] +pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; +#[doc = "Resistor select for 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BP_PULL_A { + #[doc = "0: No pull"] + NONE = 0, + #[doc = "1: Pull up"] + UP = 1, + #[doc = "2: Pull down"] + DOWN = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BP_PULL_A) -> Self { + variant as _ + } +} +impl GPIO_PUP_PDN_CNTRL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(BP_PULL_A::NONE), + 1 => Some(BP_PULL_A::UP), + 2 => Some(BP_PULL_A::DOWN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == BP_PULL_A::NONE + } + #[doc = "Checks if the value of the field is `UP`"] + #[inline(always)] + pub fn is_up(&self) -> bool { + *self == BP_PULL_A::UP + } + #[doc = "Checks if the value of the field is `DOWN`"] + #[inline(always)] + pub fn is_down(&self) -> bool { + *self == BP_PULL_A::DOWN + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL0` writer - Resistor select for 0"] +pub type GPIO_PUP_PDN_CNTRL0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG0_SPEC, u8, BP_PULL_A, 2, O>; +impl<'a, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, O> { + #[doc = "No pull"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(BP_PULL_A::NONE) + } + #[doc = "Pull up"] + #[inline(always)] + pub fn up(self) -> &'a mut W { + self.variant(BP_PULL_A::UP) + } + #[doc = "Pull down"] + #[inline(always)] + pub fn down(self) -> &'a mut W { + self.variant(BP_PULL_A::DOWN) + } +} +#[doc = "Field `GPIO_PUP_PDN_CNTRL1` reader - Resistor select for 1"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL1_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL2` reader - Resistor select for 2"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL2_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL3` reader - Resistor select for 3"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL3_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL4` reader - Resistor select for 4"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL4_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL5` reader - Resistor select for 5"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL5_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL6` reader - Resistor select for 6"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL6_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL7` reader - Resistor select for 7"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL7_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL8` reader - Resistor select for 8"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL8_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL9` reader - Resistor select for 9"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL9_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL10` reader - Resistor select for 10"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL10_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL11` reader - Resistor select for 11"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL11_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL12` reader - Resistor select for 12"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL12_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL13` reader - Resistor select for 13"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL13_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL14` reader - Resistor select for 14"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL14_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL15` reader - Resistor select for 15"] +pub use GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL15_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL1` writer - Resistor select for 1"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL1_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL2` writer - Resistor select for 2"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL2_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL3` writer - Resistor select for 3"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL3_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL4` writer - Resistor select for 4"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL4_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL5` writer - Resistor select for 5"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL5_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL6` writer - Resistor select for 6"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL6_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL7` writer - Resistor select for 7"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL7_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL8` writer - Resistor select for 8"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL8_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL9` writer - Resistor select for 9"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL9_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL10` writer - Resistor select for 10"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL10_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL11` writer - Resistor select for 11"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL11_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL12` writer - Resistor select for 12"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL12_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL13` writer - Resistor select for 13"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL13_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL14` writer - Resistor select for 14"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL14_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL15` writer - Resistor select for 15"] +pub use GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL15_W; +impl R { + #[doc = "Bits 0:1 - Resistor select for 0"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl0(&self) -> GPIO_PUP_PDN_CNTRL0_R { + GPIO_PUP_PDN_CNTRL0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 1"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl1(&self) -> GPIO_PUP_PDN_CNTRL1_R { + GPIO_PUP_PDN_CNTRL1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 2"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl2(&self) -> GPIO_PUP_PDN_CNTRL2_R { + GPIO_PUP_PDN_CNTRL2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 3"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl3(&self) -> GPIO_PUP_PDN_CNTRL3_R { + GPIO_PUP_PDN_CNTRL3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 4"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl4(&self) -> GPIO_PUP_PDN_CNTRL4_R { + GPIO_PUP_PDN_CNTRL4_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 5"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl5(&self) -> GPIO_PUP_PDN_CNTRL5_R { + GPIO_PUP_PDN_CNTRL5_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 6"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl6(&self) -> GPIO_PUP_PDN_CNTRL6_R { + GPIO_PUP_PDN_CNTRL6_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 7"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl7(&self) -> GPIO_PUP_PDN_CNTRL7_R { + GPIO_PUP_PDN_CNTRL7_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 8"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl8(&self) -> GPIO_PUP_PDN_CNTRL8_R { + GPIO_PUP_PDN_CNTRL8_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 9"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl9(&self) -> GPIO_PUP_PDN_CNTRL9_R { + GPIO_PUP_PDN_CNTRL9_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 10"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl10(&self) -> GPIO_PUP_PDN_CNTRL10_R { + GPIO_PUP_PDN_CNTRL10_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 11"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl11(&self) -> GPIO_PUP_PDN_CNTRL11_R { + GPIO_PUP_PDN_CNTRL11_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 12"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl12(&self) -> GPIO_PUP_PDN_CNTRL12_R { + GPIO_PUP_PDN_CNTRL12_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 13"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl13(&self) -> GPIO_PUP_PDN_CNTRL13_R { + GPIO_PUP_PDN_CNTRL13_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 14"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl14(&self) -> GPIO_PUP_PDN_CNTRL14_R { + GPIO_PUP_PDN_CNTRL14_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 15"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl15(&self) -> GPIO_PUP_PDN_CNTRL15_R { + GPIO_PUP_PDN_CNTRL15_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 0"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl0(&mut self) -> GPIO_PUP_PDN_CNTRL0_W<0> { + GPIO_PUP_PDN_CNTRL0_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 1"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl1(&mut self) -> GPIO_PUP_PDN_CNTRL1_W<2> { + GPIO_PUP_PDN_CNTRL1_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 2"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl2(&mut self) -> GPIO_PUP_PDN_CNTRL2_W<4> { + GPIO_PUP_PDN_CNTRL2_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 3"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl3(&mut self) -> GPIO_PUP_PDN_CNTRL3_W<6> { + GPIO_PUP_PDN_CNTRL3_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 4"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl4(&mut self) -> GPIO_PUP_PDN_CNTRL4_W<8> { + GPIO_PUP_PDN_CNTRL4_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 5"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl5(&mut self) -> GPIO_PUP_PDN_CNTRL5_W<10> { + GPIO_PUP_PDN_CNTRL5_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 6"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl6(&mut self) -> GPIO_PUP_PDN_CNTRL6_W<12> { + GPIO_PUP_PDN_CNTRL6_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 7"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl7(&mut self) -> GPIO_PUP_PDN_CNTRL7_W<14> { + GPIO_PUP_PDN_CNTRL7_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 8"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl8(&mut self) -> GPIO_PUP_PDN_CNTRL8_W<16> { + GPIO_PUP_PDN_CNTRL8_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 9"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl9(&mut self) -> GPIO_PUP_PDN_CNTRL9_W<18> { + GPIO_PUP_PDN_CNTRL9_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 10"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl10(&mut self) -> GPIO_PUP_PDN_CNTRL10_W<20> { + GPIO_PUP_PDN_CNTRL10_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 11"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl11(&mut self) -> GPIO_PUP_PDN_CNTRL11_W<22> { + GPIO_PUP_PDN_CNTRL11_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 12"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl12(&mut self) -> GPIO_PUP_PDN_CNTRL12_W<24> { + GPIO_PUP_PDN_CNTRL12_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 13"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl13(&mut self) -> GPIO_PUP_PDN_CNTRL13_W<26> { + GPIO_PUP_PDN_CNTRL13_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 14"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl14(&mut self) -> GPIO_PUP_PDN_CNTRL14_W<28> { + GPIO_PUP_PDN_CNTRL14_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 15"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl15(&mut self) -> GPIO_PUP_PDN_CNTRL15_W<30> { + GPIO_PUP_PDN_CNTRL15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg0](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG0_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg0::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg0::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs new file mode 100644 index 0000000..49faec3 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs @@ -0,0 +1,319 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` reader - Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL16_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] +pub type GPIO_PUP_PDN_CNTRL16_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` reader - Resistor select for 17"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL17_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] +pub type GPIO_PUP_PDN_CNTRL17_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` reader - Resistor select for 18"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL18_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] +pub type GPIO_PUP_PDN_CNTRL18_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` reader - Resistor select for 19"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL19_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] +pub type GPIO_PUP_PDN_CNTRL19_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` reader - Resistor select for 20"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL20_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] +pub type GPIO_PUP_PDN_CNTRL20_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` reader - Resistor select for 21"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL21_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] +pub type GPIO_PUP_PDN_CNTRL21_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` reader - Resistor select for 22"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL22_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] +pub type GPIO_PUP_PDN_CNTRL22_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` reader - Resistor select for 23"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL23_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] +pub type GPIO_PUP_PDN_CNTRL23_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` reader - Resistor select for 24"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL24_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] +pub type GPIO_PUP_PDN_CNTRL24_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` reader - Resistor select for 25"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL25_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] +pub type GPIO_PUP_PDN_CNTRL25_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` reader - Resistor select for 26"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL26_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] +pub type GPIO_PUP_PDN_CNTRL26_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` reader - Resistor select for 27"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL27_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] +pub type GPIO_PUP_PDN_CNTRL27_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` reader - Resistor select for 28"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL28_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] +pub type GPIO_PUP_PDN_CNTRL28_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` reader - Resistor select for 29"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL29_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] +pub type GPIO_PUP_PDN_CNTRL29_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` reader - Resistor select for 30"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL30_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] +pub type GPIO_PUP_PDN_CNTRL30_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL31` reader - Resistor select for 31"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL31_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL31` writer - Resistor select for 31"] +pub type GPIO_PUP_PDN_CNTRL31_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 16"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl16(&self) -> GPIO_PUP_PDN_CNTRL16_R { + GPIO_PUP_PDN_CNTRL16_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 17"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl17(&self) -> GPIO_PUP_PDN_CNTRL17_R { + GPIO_PUP_PDN_CNTRL17_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 18"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl18(&self) -> GPIO_PUP_PDN_CNTRL18_R { + GPIO_PUP_PDN_CNTRL18_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 19"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl19(&self) -> GPIO_PUP_PDN_CNTRL19_R { + GPIO_PUP_PDN_CNTRL19_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 20"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl20(&self) -> GPIO_PUP_PDN_CNTRL20_R { + GPIO_PUP_PDN_CNTRL20_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 21"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl21(&self) -> GPIO_PUP_PDN_CNTRL21_R { + GPIO_PUP_PDN_CNTRL21_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 22"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl22(&self) -> GPIO_PUP_PDN_CNTRL22_R { + GPIO_PUP_PDN_CNTRL22_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 23"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl23(&self) -> GPIO_PUP_PDN_CNTRL23_R { + GPIO_PUP_PDN_CNTRL23_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 24"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl24(&self) -> GPIO_PUP_PDN_CNTRL24_R { + GPIO_PUP_PDN_CNTRL24_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 25"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl25(&self) -> GPIO_PUP_PDN_CNTRL25_R { + GPIO_PUP_PDN_CNTRL25_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 26"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl26(&self) -> GPIO_PUP_PDN_CNTRL26_R { + GPIO_PUP_PDN_CNTRL26_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 27"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl27(&self) -> GPIO_PUP_PDN_CNTRL27_R { + GPIO_PUP_PDN_CNTRL27_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 28"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl28(&self) -> GPIO_PUP_PDN_CNTRL28_R { + GPIO_PUP_PDN_CNTRL28_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 29"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl29(&self) -> GPIO_PUP_PDN_CNTRL29_R { + GPIO_PUP_PDN_CNTRL29_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 30"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl30(&self) -> GPIO_PUP_PDN_CNTRL30_R { + GPIO_PUP_PDN_CNTRL30_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 31"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl31(&self) -> GPIO_PUP_PDN_CNTRL31_R { + GPIO_PUP_PDN_CNTRL31_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 16"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl16(&mut self) -> GPIO_PUP_PDN_CNTRL16_W<0> { + GPIO_PUP_PDN_CNTRL16_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 17"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl17(&mut self) -> GPIO_PUP_PDN_CNTRL17_W<2> { + GPIO_PUP_PDN_CNTRL17_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 18"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl18(&mut self) -> GPIO_PUP_PDN_CNTRL18_W<4> { + GPIO_PUP_PDN_CNTRL18_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 19"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl19(&mut self) -> GPIO_PUP_PDN_CNTRL19_W<6> { + GPIO_PUP_PDN_CNTRL19_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 20"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl20(&mut self) -> GPIO_PUP_PDN_CNTRL20_W<8> { + GPIO_PUP_PDN_CNTRL20_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 21"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl21(&mut self) -> GPIO_PUP_PDN_CNTRL21_W<10> { + GPIO_PUP_PDN_CNTRL21_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 22"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl22(&mut self) -> GPIO_PUP_PDN_CNTRL22_W<12> { + GPIO_PUP_PDN_CNTRL22_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 23"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl23(&mut self) -> GPIO_PUP_PDN_CNTRL23_W<14> { + GPIO_PUP_PDN_CNTRL23_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 24"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl24(&mut self) -> GPIO_PUP_PDN_CNTRL24_W<16> { + GPIO_PUP_PDN_CNTRL24_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 25"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl25(&mut self) -> GPIO_PUP_PDN_CNTRL25_W<18> { + GPIO_PUP_PDN_CNTRL25_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 26"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl26(&mut self) -> GPIO_PUP_PDN_CNTRL26_W<20> { + GPIO_PUP_PDN_CNTRL26_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 27"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl27(&mut self) -> GPIO_PUP_PDN_CNTRL27_W<22> { + GPIO_PUP_PDN_CNTRL27_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 28"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl28(&mut self) -> GPIO_PUP_PDN_CNTRL28_W<24> { + GPIO_PUP_PDN_CNTRL28_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 29"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl29(&mut self) -> GPIO_PUP_PDN_CNTRL29_W<26> { + GPIO_PUP_PDN_CNTRL29_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 30"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl30(&mut self) -> GPIO_PUP_PDN_CNTRL30_W<28> { + GPIO_PUP_PDN_CNTRL30_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 31"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl31(&mut self) -> GPIO_PUP_PDN_CNTRL31_W<30> { + GPIO_PUP_PDN_CNTRL31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg1](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG1_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg1::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg1::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs new file mode 100644 index 0000000..67047c9 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs @@ -0,0 +1,319 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` reader - Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL32_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] +pub type GPIO_PUP_PDN_CNTRL32_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` reader - Resistor select for 33"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL33_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] +pub type GPIO_PUP_PDN_CNTRL33_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` reader - Resistor select for 34"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL34_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] +pub type GPIO_PUP_PDN_CNTRL34_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` reader - Resistor select for 35"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL35_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] +pub type GPIO_PUP_PDN_CNTRL35_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` reader - Resistor select for 36"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL36_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] +pub type GPIO_PUP_PDN_CNTRL36_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` reader - Resistor select for 37"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL37_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] +pub type GPIO_PUP_PDN_CNTRL37_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` reader - Resistor select for 38"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL38_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] +pub type GPIO_PUP_PDN_CNTRL38_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` reader - Resistor select for 39"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL39_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] +pub type GPIO_PUP_PDN_CNTRL39_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` reader - Resistor select for 40"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL40_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] +pub type GPIO_PUP_PDN_CNTRL40_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` reader - Resistor select for 41"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL41_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] +pub type GPIO_PUP_PDN_CNTRL41_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` reader - Resistor select for 42"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL42_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] +pub type GPIO_PUP_PDN_CNTRL42_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` reader - Resistor select for 43"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL43_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] +pub type GPIO_PUP_PDN_CNTRL43_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` reader - Resistor select for 44"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL44_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] +pub type GPIO_PUP_PDN_CNTRL44_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` reader - Resistor select for 45"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL45_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] +pub type GPIO_PUP_PDN_CNTRL45_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` reader - Resistor select for 46"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL46_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] +pub type GPIO_PUP_PDN_CNTRL46_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL47` reader - Resistor select for 47"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL47_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL47` writer - Resistor select for 47"] +pub type GPIO_PUP_PDN_CNTRL47_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 32"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl32(&self) -> GPIO_PUP_PDN_CNTRL32_R { + GPIO_PUP_PDN_CNTRL32_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 33"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl33(&self) -> GPIO_PUP_PDN_CNTRL33_R { + GPIO_PUP_PDN_CNTRL33_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 34"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl34(&self) -> GPIO_PUP_PDN_CNTRL34_R { + GPIO_PUP_PDN_CNTRL34_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 35"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl35(&self) -> GPIO_PUP_PDN_CNTRL35_R { + GPIO_PUP_PDN_CNTRL35_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 36"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl36(&self) -> GPIO_PUP_PDN_CNTRL36_R { + GPIO_PUP_PDN_CNTRL36_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 37"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl37(&self) -> GPIO_PUP_PDN_CNTRL37_R { + GPIO_PUP_PDN_CNTRL37_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Resistor select for 38"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl38(&self) -> GPIO_PUP_PDN_CNTRL38_R { + GPIO_PUP_PDN_CNTRL38_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Resistor select for 39"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl39(&self) -> GPIO_PUP_PDN_CNTRL39_R { + GPIO_PUP_PDN_CNTRL39_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Resistor select for 40"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl40(&self) -> GPIO_PUP_PDN_CNTRL40_R { + GPIO_PUP_PDN_CNTRL40_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Resistor select for 41"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl41(&self) -> GPIO_PUP_PDN_CNTRL41_R { + GPIO_PUP_PDN_CNTRL41_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Resistor select for 42"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl42(&self) -> GPIO_PUP_PDN_CNTRL42_R { + GPIO_PUP_PDN_CNTRL42_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Resistor select for 43"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl43(&self) -> GPIO_PUP_PDN_CNTRL43_R { + GPIO_PUP_PDN_CNTRL43_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Resistor select for 44"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl44(&self) -> GPIO_PUP_PDN_CNTRL44_R { + GPIO_PUP_PDN_CNTRL44_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Resistor select for 45"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl45(&self) -> GPIO_PUP_PDN_CNTRL45_R { + GPIO_PUP_PDN_CNTRL45_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Resistor select for 46"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl46(&self) -> GPIO_PUP_PDN_CNTRL46_R { + GPIO_PUP_PDN_CNTRL46_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Resistor select for 47"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl47(&self) -> GPIO_PUP_PDN_CNTRL47_R { + GPIO_PUP_PDN_CNTRL47_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 32"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl32(&mut self) -> GPIO_PUP_PDN_CNTRL32_W<0> { + GPIO_PUP_PDN_CNTRL32_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 33"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl33(&mut self) -> GPIO_PUP_PDN_CNTRL33_W<2> { + GPIO_PUP_PDN_CNTRL33_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 34"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl34(&mut self) -> GPIO_PUP_PDN_CNTRL34_W<4> { + GPIO_PUP_PDN_CNTRL34_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 35"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl35(&mut self) -> GPIO_PUP_PDN_CNTRL35_W<6> { + GPIO_PUP_PDN_CNTRL35_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 36"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl36(&mut self) -> GPIO_PUP_PDN_CNTRL36_W<8> { + GPIO_PUP_PDN_CNTRL36_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 37"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl37(&mut self) -> GPIO_PUP_PDN_CNTRL37_W<10> { + GPIO_PUP_PDN_CNTRL37_W::new(self) + } + #[doc = "Bits 12:13 - Resistor select for 38"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl38(&mut self) -> GPIO_PUP_PDN_CNTRL38_W<12> { + GPIO_PUP_PDN_CNTRL38_W::new(self) + } + #[doc = "Bits 14:15 - Resistor select for 39"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl39(&mut self) -> GPIO_PUP_PDN_CNTRL39_W<14> { + GPIO_PUP_PDN_CNTRL39_W::new(self) + } + #[doc = "Bits 16:17 - Resistor select for 40"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl40(&mut self) -> GPIO_PUP_PDN_CNTRL40_W<16> { + GPIO_PUP_PDN_CNTRL40_W::new(self) + } + #[doc = "Bits 18:19 - Resistor select for 41"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl41(&mut self) -> GPIO_PUP_PDN_CNTRL41_W<18> { + GPIO_PUP_PDN_CNTRL41_W::new(self) + } + #[doc = "Bits 20:21 - Resistor select for 42"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl42(&mut self) -> GPIO_PUP_PDN_CNTRL42_W<20> { + GPIO_PUP_PDN_CNTRL42_W::new(self) + } + #[doc = "Bits 22:23 - Resistor select for 43"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl43(&mut self) -> GPIO_PUP_PDN_CNTRL43_W<22> { + GPIO_PUP_PDN_CNTRL43_W::new(self) + } + #[doc = "Bits 24:25 - Resistor select for 44"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl44(&mut self) -> GPIO_PUP_PDN_CNTRL44_W<24> { + GPIO_PUP_PDN_CNTRL44_W::new(self) + } + #[doc = "Bits 26:27 - Resistor select for 45"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl45(&mut self) -> GPIO_PUP_PDN_CNTRL45_W<26> { + GPIO_PUP_PDN_CNTRL45_W::new(self) + } + #[doc = "Bits 28:29 - Resistor select for 46"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl46(&mut self) -> GPIO_PUP_PDN_CNTRL46_W<28> { + GPIO_PUP_PDN_CNTRL46_W::new(self) + } + #[doc = "Bits 30:31 - Resistor select for 47"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl47(&mut self) -> GPIO_PUP_PDN_CNTRL47_W<30> { + GPIO_PUP_PDN_CNTRL47_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg2](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG2_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg2::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg2::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs new file mode 100644 index 0000000..61b9329 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs @@ -0,0 +1,159 @@ +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` reader - Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL48_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] +pub type GPIO_PUP_PDN_CNTRL48_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` reader - Resistor select for 49"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL49_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] +pub type GPIO_PUP_PDN_CNTRL49_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` reader - Resistor select for 50"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL50_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] +pub type GPIO_PUP_PDN_CNTRL50_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` reader - Resistor select for 51"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL51_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] +pub type GPIO_PUP_PDN_CNTRL51_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` reader - Resistor select for 52"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL52_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] +pub type GPIO_PUP_PDN_CNTRL52_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` reader - Resistor select for 53"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL53_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] +pub type GPIO_PUP_PDN_CNTRL53_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +impl R { + #[doc = "Bits 0:1 - Resistor select for 48"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl48(&self) -> GPIO_PUP_PDN_CNTRL48_R { + GPIO_PUP_PDN_CNTRL48_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Resistor select for 49"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl49(&self) -> GPIO_PUP_PDN_CNTRL49_R { + GPIO_PUP_PDN_CNTRL49_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Resistor select for 50"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl50(&self) -> GPIO_PUP_PDN_CNTRL50_R { + GPIO_PUP_PDN_CNTRL50_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Resistor select for 51"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl51(&self) -> GPIO_PUP_PDN_CNTRL51_R { + GPIO_PUP_PDN_CNTRL51_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Resistor select for 52"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl52(&self) -> GPIO_PUP_PDN_CNTRL52_R { + GPIO_PUP_PDN_CNTRL52_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Resistor select for 53"] + #[inline(always)] + pub fn gpio_pup_pdn_cntrl53(&self) -> GPIO_PUP_PDN_CNTRL53_R { + GPIO_PUP_PDN_CNTRL53_R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Resistor select for 48"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl48(&mut self) -> GPIO_PUP_PDN_CNTRL48_W<0> { + GPIO_PUP_PDN_CNTRL48_W::new(self) + } + #[doc = "Bits 2:3 - Resistor select for 49"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl49(&mut self) -> GPIO_PUP_PDN_CNTRL49_W<2> { + GPIO_PUP_PDN_CNTRL49_W::new(self) + } + #[doc = "Bits 4:5 - Resistor select for 50"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl50(&mut self) -> GPIO_PUP_PDN_CNTRL50_W<4> { + GPIO_PUP_PDN_CNTRL50_W::new(self) + } + #[doc = "Bits 6:7 - Resistor select for 51"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl51(&mut self) -> GPIO_PUP_PDN_CNTRL51_W<6> { + GPIO_PUP_PDN_CNTRL51_W::new(self) + } + #[doc = "Bits 8:9 - Resistor select for 52"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl52(&mut self) -> GPIO_PUP_PDN_CNTRL52_W<8> { + GPIO_PUP_PDN_CNTRL52_W::new(self) + } + #[doc = "Bits 10:11 - Resistor select for 53"] + #[inline(always)] + #[must_use] + pub fn gpio_pup_pdn_cntrl53(&mut self) -> GPIO_PUP_PDN_CNTRL53_W<10> { + GPIO_PUP_PDN_CNTRL53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pull-up / Pull-down Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg3](index.html) module"] +pub struct GPIO_PUP_PDN_CNTRL_REG3_SPEC; +impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg3::R](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg3::W](W) writer structure"] +impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gplen0.rs b/crates/bcm2837-lpa/src/gpio/gplen0.rs new file mode 100644 index 0000000..54f51bd --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gplen0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPLEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPLEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEN0` reader - Low detect enabled 0"] +pub type LEN0_R = crate::BitReader; +#[doc = "Field `LEN0` writer - Low detect enabled 0"] +pub type LEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN1` reader - Low detect enabled 1"] +pub type LEN1_R = crate::BitReader; +#[doc = "Field `LEN1` writer - Low detect enabled 1"] +pub type LEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN2` reader - Low detect enabled 2"] +pub type LEN2_R = crate::BitReader; +#[doc = "Field `LEN2` writer - Low detect enabled 2"] +pub type LEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN3` reader - Low detect enabled 3"] +pub type LEN3_R = crate::BitReader; +#[doc = "Field `LEN3` writer - Low detect enabled 3"] +pub type LEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN4` reader - Low detect enabled 4"] +pub type LEN4_R = crate::BitReader; +#[doc = "Field `LEN4` writer - Low detect enabled 4"] +pub type LEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN5` reader - Low detect enabled 5"] +pub type LEN5_R = crate::BitReader; +#[doc = "Field `LEN5` writer - Low detect enabled 5"] +pub type LEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN6` reader - Low detect enabled 6"] +pub type LEN6_R = crate::BitReader; +#[doc = "Field `LEN6` writer - Low detect enabled 6"] +pub type LEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN7` reader - Low detect enabled 7"] +pub type LEN7_R = crate::BitReader; +#[doc = "Field `LEN7` writer - Low detect enabled 7"] +pub type LEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN8` reader - Low detect enabled 8"] +pub type LEN8_R = crate::BitReader; +#[doc = "Field `LEN8` writer - Low detect enabled 8"] +pub type LEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN9` reader - Low detect enabled 9"] +pub type LEN9_R = crate::BitReader; +#[doc = "Field `LEN9` writer - Low detect enabled 9"] +pub type LEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN10` reader - Low detect enabled 10"] +pub type LEN10_R = crate::BitReader; +#[doc = "Field `LEN10` writer - Low detect enabled 10"] +pub type LEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN11` reader - Low detect enabled 11"] +pub type LEN11_R = crate::BitReader; +#[doc = "Field `LEN11` writer - Low detect enabled 11"] +pub type LEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN12` reader - Low detect enabled 12"] +pub type LEN12_R = crate::BitReader; +#[doc = "Field `LEN12` writer - Low detect enabled 12"] +pub type LEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN13` reader - Low detect enabled 13"] +pub type LEN13_R = crate::BitReader; +#[doc = "Field `LEN13` writer - Low detect enabled 13"] +pub type LEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN14` reader - Low detect enabled 14"] +pub type LEN14_R = crate::BitReader; +#[doc = "Field `LEN14` writer - Low detect enabled 14"] +pub type LEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN15` reader - Low detect enabled 15"] +pub type LEN15_R = crate::BitReader; +#[doc = "Field `LEN15` writer - Low detect enabled 15"] +pub type LEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN16` reader - Low detect enabled 16"] +pub type LEN16_R = crate::BitReader; +#[doc = "Field `LEN16` writer - Low detect enabled 16"] +pub type LEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN17` reader - Low detect enabled 17"] +pub type LEN17_R = crate::BitReader; +#[doc = "Field `LEN17` writer - Low detect enabled 17"] +pub type LEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN18` reader - Low detect enabled 18"] +pub type LEN18_R = crate::BitReader; +#[doc = "Field `LEN18` writer - Low detect enabled 18"] +pub type LEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN19` reader - Low detect enabled 19"] +pub type LEN19_R = crate::BitReader; +#[doc = "Field `LEN19` writer - Low detect enabled 19"] +pub type LEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN20` reader - Low detect enabled 20"] +pub type LEN20_R = crate::BitReader; +#[doc = "Field `LEN20` writer - Low detect enabled 20"] +pub type LEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN21` reader - Low detect enabled 21"] +pub type LEN21_R = crate::BitReader; +#[doc = "Field `LEN21` writer - Low detect enabled 21"] +pub type LEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN22` reader - Low detect enabled 22"] +pub type LEN22_R = crate::BitReader; +#[doc = "Field `LEN22` writer - Low detect enabled 22"] +pub type LEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN23` reader - Low detect enabled 23"] +pub type LEN23_R = crate::BitReader; +#[doc = "Field `LEN23` writer - Low detect enabled 23"] +pub type LEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN24` reader - Low detect enabled 24"] +pub type LEN24_R = crate::BitReader; +#[doc = "Field `LEN24` writer - Low detect enabled 24"] +pub type LEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN25` reader - Low detect enabled 25"] +pub type LEN25_R = crate::BitReader; +#[doc = "Field `LEN25` writer - Low detect enabled 25"] +pub type LEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN26` reader - Low detect enabled 26"] +pub type LEN26_R = crate::BitReader; +#[doc = "Field `LEN26` writer - Low detect enabled 26"] +pub type LEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN27` reader - Low detect enabled 27"] +pub type LEN27_R = crate::BitReader; +#[doc = "Field `LEN27` writer - Low detect enabled 27"] +pub type LEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN28` reader - Low detect enabled 28"] +pub type LEN28_R = crate::BitReader; +#[doc = "Field `LEN28` writer - Low detect enabled 28"] +pub type LEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN29` reader - Low detect enabled 29"] +pub type LEN29_R = crate::BitReader; +#[doc = "Field `LEN29` writer - Low detect enabled 29"] +pub type LEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN30` reader - Low detect enabled 30"] +pub type LEN30_R = crate::BitReader; +#[doc = "Field `LEN30` writer - Low detect enabled 30"] +pub type LEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +#[doc = "Field `LEN31` reader - Low detect enabled 31"] +pub type LEN31_R = crate::BitReader; +#[doc = "Field `LEN31` writer - Low detect enabled 31"] +pub type LEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Low detect enabled 0"] + #[inline(always)] + pub fn len0(&self) -> LEN0_R { + LEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low detect enabled 1"] + #[inline(always)] + pub fn len1(&self) -> LEN1_R { + LEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Low detect enabled 2"] + #[inline(always)] + pub fn len2(&self) -> LEN2_R { + LEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Low detect enabled 3"] + #[inline(always)] + pub fn len3(&self) -> LEN3_R { + LEN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Low detect enabled 4"] + #[inline(always)] + pub fn len4(&self) -> LEN4_R { + LEN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Low detect enabled 5"] + #[inline(always)] + pub fn len5(&self) -> LEN5_R { + LEN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Low detect enabled 6"] + #[inline(always)] + pub fn len6(&self) -> LEN6_R { + LEN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Low detect enabled 7"] + #[inline(always)] + pub fn len7(&self) -> LEN7_R { + LEN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Low detect enabled 8"] + #[inline(always)] + pub fn len8(&self) -> LEN8_R { + LEN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low detect enabled 9"] + #[inline(always)] + pub fn len9(&self) -> LEN9_R { + LEN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Low detect enabled 10"] + #[inline(always)] + pub fn len10(&self) -> LEN10_R { + LEN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low detect enabled 11"] + #[inline(always)] + pub fn len11(&self) -> LEN11_R { + LEN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low detect enabled 12"] + #[inline(always)] + pub fn len12(&self) -> LEN12_R { + LEN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Low detect enabled 13"] + #[inline(always)] + pub fn len13(&self) -> LEN13_R { + LEN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Low detect enabled 14"] + #[inline(always)] + pub fn len14(&self) -> LEN14_R { + LEN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Low detect enabled 15"] + #[inline(always)] + pub fn len15(&self) -> LEN15_R { + LEN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Low detect enabled 16"] + #[inline(always)] + pub fn len16(&self) -> LEN16_R { + LEN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Low detect enabled 17"] + #[inline(always)] + pub fn len17(&self) -> LEN17_R { + LEN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Low detect enabled 18"] + #[inline(always)] + pub fn len18(&self) -> LEN18_R { + LEN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Low detect enabled 19"] + #[inline(always)] + pub fn len19(&self) -> LEN19_R { + LEN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low detect enabled 20"] + #[inline(always)] + pub fn len20(&self) -> LEN20_R { + LEN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Low detect enabled 21"] + #[inline(always)] + pub fn len21(&self) -> LEN21_R { + LEN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Low detect enabled 22"] + #[inline(always)] + pub fn len22(&self) -> LEN22_R { + LEN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Low detect enabled 23"] + #[inline(always)] + pub fn len23(&self) -> LEN23_R { + LEN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Low detect enabled 24"] + #[inline(always)] + pub fn len24(&self) -> LEN24_R { + LEN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Low detect enabled 25"] + #[inline(always)] + pub fn len25(&self) -> LEN25_R { + LEN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Low detect enabled 26"] + #[inline(always)] + pub fn len26(&self) -> LEN26_R { + LEN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Low detect enabled 27"] + #[inline(always)] + pub fn len27(&self) -> LEN27_R { + LEN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Low detect enabled 28"] + #[inline(always)] + pub fn len28(&self) -> LEN28_R { + LEN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Low detect enabled 29"] + #[inline(always)] + pub fn len29(&self) -> LEN29_R { + LEN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Low detect enabled 30"] + #[inline(always)] + pub fn len30(&self) -> LEN30_R { + LEN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Low detect enabled 31"] + #[inline(always)] + pub fn len31(&self) -> LEN31_R { + LEN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Low detect enabled 0"] + #[inline(always)] + #[must_use] + pub fn len0(&mut self) -> LEN0_W<0> { + LEN0_W::new(self) + } + #[doc = "Bit 1 - Low detect enabled 1"] + #[inline(always)] + #[must_use] + pub fn len1(&mut self) -> LEN1_W<1> { + LEN1_W::new(self) + } + #[doc = "Bit 2 - Low detect enabled 2"] + #[inline(always)] + #[must_use] + pub fn len2(&mut self) -> LEN2_W<2> { + LEN2_W::new(self) + } + #[doc = "Bit 3 - Low detect enabled 3"] + #[inline(always)] + #[must_use] + pub fn len3(&mut self) -> LEN3_W<3> { + LEN3_W::new(self) + } + #[doc = "Bit 4 - Low detect enabled 4"] + #[inline(always)] + #[must_use] + pub fn len4(&mut self) -> LEN4_W<4> { + LEN4_W::new(self) + } + #[doc = "Bit 5 - Low detect enabled 5"] + #[inline(always)] + #[must_use] + pub fn len5(&mut self) -> LEN5_W<5> { + LEN5_W::new(self) + } + #[doc = "Bit 6 - Low detect enabled 6"] + #[inline(always)] + #[must_use] + pub fn len6(&mut self) -> LEN6_W<6> { + LEN6_W::new(self) + } + #[doc = "Bit 7 - Low detect enabled 7"] + #[inline(always)] + #[must_use] + pub fn len7(&mut self) -> LEN7_W<7> { + LEN7_W::new(self) + } + #[doc = "Bit 8 - Low detect enabled 8"] + #[inline(always)] + #[must_use] + pub fn len8(&mut self) -> LEN8_W<8> { + LEN8_W::new(self) + } + #[doc = "Bit 9 - Low detect enabled 9"] + #[inline(always)] + #[must_use] + pub fn len9(&mut self) -> LEN9_W<9> { + LEN9_W::new(self) + } + #[doc = "Bit 10 - Low detect enabled 10"] + #[inline(always)] + #[must_use] + pub fn len10(&mut self) -> LEN10_W<10> { + LEN10_W::new(self) + } + #[doc = "Bit 11 - Low detect enabled 11"] + #[inline(always)] + #[must_use] + pub fn len11(&mut self) -> LEN11_W<11> { + LEN11_W::new(self) + } + #[doc = "Bit 12 - Low detect enabled 12"] + #[inline(always)] + #[must_use] + pub fn len12(&mut self) -> LEN12_W<12> { + LEN12_W::new(self) + } + #[doc = "Bit 13 - Low detect enabled 13"] + #[inline(always)] + #[must_use] + pub fn len13(&mut self) -> LEN13_W<13> { + LEN13_W::new(self) + } + #[doc = "Bit 14 - Low detect enabled 14"] + #[inline(always)] + #[must_use] + pub fn len14(&mut self) -> LEN14_W<14> { + LEN14_W::new(self) + } + #[doc = "Bit 15 - Low detect enabled 15"] + #[inline(always)] + #[must_use] + pub fn len15(&mut self) -> LEN15_W<15> { + LEN15_W::new(self) + } + #[doc = "Bit 16 - Low detect enabled 16"] + #[inline(always)] + #[must_use] + pub fn len16(&mut self) -> LEN16_W<16> { + LEN16_W::new(self) + } + #[doc = "Bit 17 - Low detect enabled 17"] + #[inline(always)] + #[must_use] + pub fn len17(&mut self) -> LEN17_W<17> { + LEN17_W::new(self) + } + #[doc = "Bit 18 - Low detect enabled 18"] + #[inline(always)] + #[must_use] + pub fn len18(&mut self) -> LEN18_W<18> { + LEN18_W::new(self) + } + #[doc = "Bit 19 - Low detect enabled 19"] + #[inline(always)] + #[must_use] + pub fn len19(&mut self) -> LEN19_W<19> { + LEN19_W::new(self) + } + #[doc = "Bit 20 - Low detect enabled 20"] + #[inline(always)] + #[must_use] + pub fn len20(&mut self) -> LEN20_W<20> { + LEN20_W::new(self) + } + #[doc = "Bit 21 - Low detect enabled 21"] + #[inline(always)] + #[must_use] + pub fn len21(&mut self) -> LEN21_W<21> { + LEN21_W::new(self) + } + #[doc = "Bit 22 - Low detect enabled 22"] + #[inline(always)] + #[must_use] + pub fn len22(&mut self) -> LEN22_W<22> { + LEN22_W::new(self) + } + #[doc = "Bit 23 - Low detect enabled 23"] + #[inline(always)] + #[must_use] + pub fn len23(&mut self) -> LEN23_W<23> { + LEN23_W::new(self) + } + #[doc = "Bit 24 - Low detect enabled 24"] + #[inline(always)] + #[must_use] + pub fn len24(&mut self) -> LEN24_W<24> { + LEN24_W::new(self) + } + #[doc = "Bit 25 - Low detect enabled 25"] + #[inline(always)] + #[must_use] + pub fn len25(&mut self) -> LEN25_W<25> { + LEN25_W::new(self) + } + #[doc = "Bit 26 - Low detect enabled 26"] + #[inline(always)] + #[must_use] + pub fn len26(&mut self) -> LEN26_W<26> { + LEN26_W::new(self) + } + #[doc = "Bit 27 - Low detect enabled 27"] + #[inline(always)] + #[must_use] + pub fn len27(&mut self) -> LEN27_W<27> { + LEN27_W::new(self) + } + #[doc = "Bit 28 - Low detect enabled 28"] + #[inline(always)] + #[must_use] + pub fn len28(&mut self) -> LEN28_W<28> { + LEN28_W::new(self) + } + #[doc = "Bit 29 - Low detect enabled 29"] + #[inline(always)] + #[must_use] + pub fn len29(&mut self) -> LEN29_W<29> { + LEN29_W::new(self) + } + #[doc = "Bit 30 - Low detect enabled 30"] + #[inline(always)] + #[must_use] + pub fn len30(&mut self) -> LEN30_W<30> { + LEN30_W::new(self) + } + #[doc = "Bit 31 - Low detect enabled 31"] + #[inline(always)] + #[must_use] + pub fn len31(&mut self) -> LEN31_W<31> { + LEN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Low Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen0](index.html) module"] +pub struct GPLEN0_SPEC; +impl crate::RegisterSpec for GPLEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplen0::R](R) reader structure"] +impl crate::Readable for GPLEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gplen0::W](W) writer structure"] +impl crate::Writable for GPLEN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gplen1.rs b/crates/bcm2837-lpa/src/gpio/gplen1.rs new file mode 100644 index 0000000..070e4d4 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gplen1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPLEN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPLEN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEN32` reader - Low detect enabled 32"] +pub type LEN32_R = crate::BitReader; +#[doc = "Field `LEN32` writer - Low detect enabled 32"] +pub type LEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN33` reader - Low detect enabled 33"] +pub type LEN33_R = crate::BitReader; +#[doc = "Field `LEN33` writer - Low detect enabled 33"] +pub type LEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN34` reader - Low detect enabled 34"] +pub type LEN34_R = crate::BitReader; +#[doc = "Field `LEN34` writer - Low detect enabled 34"] +pub type LEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN35` reader - Low detect enabled 35"] +pub type LEN35_R = crate::BitReader; +#[doc = "Field `LEN35` writer - Low detect enabled 35"] +pub type LEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN36` reader - Low detect enabled 36"] +pub type LEN36_R = crate::BitReader; +#[doc = "Field `LEN36` writer - Low detect enabled 36"] +pub type LEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN37` reader - Low detect enabled 37"] +pub type LEN37_R = crate::BitReader; +#[doc = "Field `LEN37` writer - Low detect enabled 37"] +pub type LEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN38` reader - Low detect enabled 38"] +pub type LEN38_R = crate::BitReader; +#[doc = "Field `LEN38` writer - Low detect enabled 38"] +pub type LEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN39` reader - Low detect enabled 39"] +pub type LEN39_R = crate::BitReader; +#[doc = "Field `LEN39` writer - Low detect enabled 39"] +pub type LEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN40` reader - Low detect enabled 40"] +pub type LEN40_R = crate::BitReader; +#[doc = "Field `LEN40` writer - Low detect enabled 40"] +pub type LEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN41` reader - Low detect enabled 41"] +pub type LEN41_R = crate::BitReader; +#[doc = "Field `LEN41` writer - Low detect enabled 41"] +pub type LEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN42` reader - Low detect enabled 42"] +pub type LEN42_R = crate::BitReader; +#[doc = "Field `LEN42` writer - Low detect enabled 42"] +pub type LEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN43` reader - Low detect enabled 43"] +pub type LEN43_R = crate::BitReader; +#[doc = "Field `LEN43` writer - Low detect enabled 43"] +pub type LEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN44` reader - Low detect enabled 44"] +pub type LEN44_R = crate::BitReader; +#[doc = "Field `LEN44` writer - Low detect enabled 44"] +pub type LEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN45` reader - Low detect enabled 45"] +pub type LEN45_R = crate::BitReader; +#[doc = "Field `LEN45` writer - Low detect enabled 45"] +pub type LEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN46` reader - Low detect enabled 46"] +pub type LEN46_R = crate::BitReader; +#[doc = "Field `LEN46` writer - Low detect enabled 46"] +pub type LEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN47` reader - Low detect enabled 47"] +pub type LEN47_R = crate::BitReader; +#[doc = "Field `LEN47` writer - Low detect enabled 47"] +pub type LEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN48` reader - Low detect enabled 48"] +pub type LEN48_R = crate::BitReader; +#[doc = "Field `LEN48` writer - Low detect enabled 48"] +pub type LEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN49` reader - Low detect enabled 49"] +pub type LEN49_R = crate::BitReader; +#[doc = "Field `LEN49` writer - Low detect enabled 49"] +pub type LEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN50` reader - Low detect enabled 50"] +pub type LEN50_R = crate::BitReader; +#[doc = "Field `LEN50` writer - Low detect enabled 50"] +pub type LEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN51` reader - Low detect enabled 51"] +pub type LEN51_R = crate::BitReader; +#[doc = "Field `LEN51` writer - Low detect enabled 51"] +pub type LEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN52` reader - Low detect enabled 52"] +pub type LEN52_R = crate::BitReader; +#[doc = "Field `LEN52` writer - Low detect enabled 52"] +pub type LEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +#[doc = "Field `LEN53` reader - Low detect enabled 53"] +pub type LEN53_R = crate::BitReader; +#[doc = "Field `LEN53` writer - Low detect enabled 53"] +pub type LEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Low detect enabled 32"] + #[inline(always)] + pub fn len32(&self) -> LEN32_R { + LEN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Low detect enabled 33"] + #[inline(always)] + pub fn len33(&self) -> LEN33_R { + LEN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Low detect enabled 34"] + #[inline(always)] + pub fn len34(&self) -> LEN34_R { + LEN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Low detect enabled 35"] + #[inline(always)] + pub fn len35(&self) -> LEN35_R { + LEN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Low detect enabled 36"] + #[inline(always)] + pub fn len36(&self) -> LEN36_R { + LEN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Low detect enabled 37"] + #[inline(always)] + pub fn len37(&self) -> LEN37_R { + LEN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Low detect enabled 38"] + #[inline(always)] + pub fn len38(&self) -> LEN38_R { + LEN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Low detect enabled 39"] + #[inline(always)] + pub fn len39(&self) -> LEN39_R { + LEN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Low detect enabled 40"] + #[inline(always)] + pub fn len40(&self) -> LEN40_R { + LEN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Low detect enabled 41"] + #[inline(always)] + pub fn len41(&self) -> LEN41_R { + LEN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Low detect enabled 42"] + #[inline(always)] + pub fn len42(&self) -> LEN42_R { + LEN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Low detect enabled 43"] + #[inline(always)] + pub fn len43(&self) -> LEN43_R { + LEN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low detect enabled 44"] + #[inline(always)] + pub fn len44(&self) -> LEN44_R { + LEN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Low detect enabled 45"] + #[inline(always)] + pub fn len45(&self) -> LEN45_R { + LEN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Low detect enabled 46"] + #[inline(always)] + pub fn len46(&self) -> LEN46_R { + LEN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Low detect enabled 47"] + #[inline(always)] + pub fn len47(&self) -> LEN47_R { + LEN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Low detect enabled 48"] + #[inline(always)] + pub fn len48(&self) -> LEN48_R { + LEN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Low detect enabled 49"] + #[inline(always)] + pub fn len49(&self) -> LEN49_R { + LEN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Low detect enabled 50"] + #[inline(always)] + pub fn len50(&self) -> LEN50_R { + LEN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Low detect enabled 51"] + #[inline(always)] + pub fn len51(&self) -> LEN51_R { + LEN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Low detect enabled 52"] + #[inline(always)] + pub fn len52(&self) -> LEN52_R { + LEN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Low detect enabled 53"] + #[inline(always)] + pub fn len53(&self) -> LEN53_R { + LEN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Low detect enabled 32"] + #[inline(always)] + #[must_use] + pub fn len32(&mut self) -> LEN32_W<0> { + LEN32_W::new(self) + } + #[doc = "Bit 1 - Low detect enabled 33"] + #[inline(always)] + #[must_use] + pub fn len33(&mut self) -> LEN33_W<1> { + LEN33_W::new(self) + } + #[doc = "Bit 2 - Low detect enabled 34"] + #[inline(always)] + #[must_use] + pub fn len34(&mut self) -> LEN34_W<2> { + LEN34_W::new(self) + } + #[doc = "Bit 3 - Low detect enabled 35"] + #[inline(always)] + #[must_use] + pub fn len35(&mut self) -> LEN35_W<3> { + LEN35_W::new(self) + } + #[doc = "Bit 4 - Low detect enabled 36"] + #[inline(always)] + #[must_use] + pub fn len36(&mut self) -> LEN36_W<4> { + LEN36_W::new(self) + } + #[doc = "Bit 5 - Low detect enabled 37"] + #[inline(always)] + #[must_use] + pub fn len37(&mut self) -> LEN37_W<5> { + LEN37_W::new(self) + } + #[doc = "Bit 6 - Low detect enabled 38"] + #[inline(always)] + #[must_use] + pub fn len38(&mut self) -> LEN38_W<6> { + LEN38_W::new(self) + } + #[doc = "Bit 7 - Low detect enabled 39"] + #[inline(always)] + #[must_use] + pub fn len39(&mut self) -> LEN39_W<7> { + LEN39_W::new(self) + } + #[doc = "Bit 8 - Low detect enabled 40"] + #[inline(always)] + #[must_use] + pub fn len40(&mut self) -> LEN40_W<8> { + LEN40_W::new(self) + } + #[doc = "Bit 9 - Low detect enabled 41"] + #[inline(always)] + #[must_use] + pub fn len41(&mut self) -> LEN41_W<9> { + LEN41_W::new(self) + } + #[doc = "Bit 10 - Low detect enabled 42"] + #[inline(always)] + #[must_use] + pub fn len42(&mut self) -> LEN42_W<10> { + LEN42_W::new(self) + } + #[doc = "Bit 11 - Low detect enabled 43"] + #[inline(always)] + #[must_use] + pub fn len43(&mut self) -> LEN43_W<11> { + LEN43_W::new(self) + } + #[doc = "Bit 12 - Low detect enabled 44"] + #[inline(always)] + #[must_use] + pub fn len44(&mut self) -> LEN44_W<12> { + LEN44_W::new(self) + } + #[doc = "Bit 13 - Low detect enabled 45"] + #[inline(always)] + #[must_use] + pub fn len45(&mut self) -> LEN45_W<13> { + LEN45_W::new(self) + } + #[doc = "Bit 14 - Low detect enabled 46"] + #[inline(always)] + #[must_use] + pub fn len46(&mut self) -> LEN46_W<14> { + LEN46_W::new(self) + } + #[doc = "Bit 15 - Low detect enabled 47"] + #[inline(always)] + #[must_use] + pub fn len47(&mut self) -> LEN47_W<15> { + LEN47_W::new(self) + } + #[doc = "Bit 16 - Low detect enabled 48"] + #[inline(always)] + #[must_use] + pub fn len48(&mut self) -> LEN48_W<16> { + LEN48_W::new(self) + } + #[doc = "Bit 17 - Low detect enabled 49"] + #[inline(always)] + #[must_use] + pub fn len49(&mut self) -> LEN49_W<17> { + LEN49_W::new(self) + } + #[doc = "Bit 18 - Low detect enabled 50"] + #[inline(always)] + #[must_use] + pub fn len50(&mut self) -> LEN50_W<18> { + LEN50_W::new(self) + } + #[doc = "Bit 19 - Low detect enabled 51"] + #[inline(always)] + #[must_use] + pub fn len51(&mut self) -> LEN51_W<19> { + LEN51_W::new(self) + } + #[doc = "Bit 20 - Low detect enabled 52"] + #[inline(always)] + #[must_use] + pub fn len52(&mut self) -> LEN52_W<20> { + LEN52_W::new(self) + } + #[doc = "Bit 21 - Low detect enabled 53"] + #[inline(always)] + #[must_use] + pub fn len53(&mut self) -> LEN53_W<21> { + LEN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Low Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen1](index.html) module"] +pub struct GPLEN1_SPEC; +impl crate::RegisterSpec for GPLEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplen1::R](R) reader structure"] +impl crate::Readable for GPLEN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gplen1::W](W) writer structure"] +impl crate::Writable for GPLEN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gplev0.rs b/crates/bcm2837-lpa/src/gpio/gplev0.rs new file mode 100644 index 0000000..e6f9b94 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gplev0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `GPLEV0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LEV0` reader - Level 0"] +pub type LEV0_R = crate::BitReader; +#[doc = "Field `LEV1` reader - Level 1"] +pub type LEV1_R = crate::BitReader; +#[doc = "Field `LEV2` reader - Level 2"] +pub type LEV2_R = crate::BitReader; +#[doc = "Field `LEV3` reader - Level 3"] +pub type LEV3_R = crate::BitReader; +#[doc = "Field `LEV4` reader - Level 4"] +pub type LEV4_R = crate::BitReader; +#[doc = "Field `LEV5` reader - Level 5"] +pub type LEV5_R = crate::BitReader; +#[doc = "Field `LEV6` reader - Level 6"] +pub type LEV6_R = crate::BitReader; +#[doc = "Field `LEV7` reader - Level 7"] +pub type LEV7_R = crate::BitReader; +#[doc = "Field `LEV8` reader - Level 8"] +pub type LEV8_R = crate::BitReader; +#[doc = "Field `LEV9` reader - Level 9"] +pub type LEV9_R = crate::BitReader; +#[doc = "Field `LEV10` reader - Level 10"] +pub type LEV10_R = crate::BitReader; +#[doc = "Field `LEV11` reader - Level 11"] +pub type LEV11_R = crate::BitReader; +#[doc = "Field `LEV12` reader - Level 12"] +pub type LEV12_R = crate::BitReader; +#[doc = "Field `LEV13` reader - Level 13"] +pub type LEV13_R = crate::BitReader; +#[doc = "Field `LEV14` reader - Level 14"] +pub type LEV14_R = crate::BitReader; +#[doc = "Field `LEV15` reader - Level 15"] +pub type LEV15_R = crate::BitReader; +#[doc = "Field `LEV16` reader - Level 16"] +pub type LEV16_R = crate::BitReader; +#[doc = "Field `LEV17` reader - Level 17"] +pub type LEV17_R = crate::BitReader; +#[doc = "Field `LEV18` reader - Level 18"] +pub type LEV18_R = crate::BitReader; +#[doc = "Field `LEV19` reader - Level 19"] +pub type LEV19_R = crate::BitReader; +#[doc = "Field `LEV20` reader - Level 20"] +pub type LEV20_R = crate::BitReader; +#[doc = "Field `LEV21` reader - Level 21"] +pub type LEV21_R = crate::BitReader; +#[doc = "Field `LEV22` reader - Level 22"] +pub type LEV22_R = crate::BitReader; +#[doc = "Field `LEV23` reader - Level 23"] +pub type LEV23_R = crate::BitReader; +#[doc = "Field `LEV24` reader - Level 24"] +pub type LEV24_R = crate::BitReader; +#[doc = "Field `LEV25` reader - Level 25"] +pub type LEV25_R = crate::BitReader; +#[doc = "Field `LEV26` reader - Level 26"] +pub type LEV26_R = crate::BitReader; +#[doc = "Field `LEV27` reader - Level 27"] +pub type LEV27_R = crate::BitReader; +#[doc = "Field `LEV28` reader - Level 28"] +pub type LEV28_R = crate::BitReader; +#[doc = "Field `LEV29` reader - Level 29"] +pub type LEV29_R = crate::BitReader; +#[doc = "Field `LEV30` reader - Level 30"] +pub type LEV30_R = crate::BitReader; +#[doc = "Field `LEV31` reader - Level 31"] +pub type LEV31_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Level 0"] + #[inline(always)] + pub fn lev0(&self) -> LEV0_R { + LEV0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 1"] + #[inline(always)] + pub fn lev1(&self) -> LEV1_R { + LEV1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 2"] + #[inline(always)] + pub fn lev2(&self) -> LEV2_R { + LEV2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 3"] + #[inline(always)] + pub fn lev3(&self) -> LEV3_R { + LEV3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Level 4"] + #[inline(always)] + pub fn lev4(&self) -> LEV4_R { + LEV4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Level 5"] + #[inline(always)] + pub fn lev5(&self) -> LEV5_R { + LEV5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Level 6"] + #[inline(always)] + pub fn lev6(&self) -> LEV6_R { + LEV6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Level 7"] + #[inline(always)] + pub fn lev7(&self) -> LEV7_R { + LEV7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Level 8"] + #[inline(always)] + pub fn lev8(&self) -> LEV8_R { + LEV8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Level 9"] + #[inline(always)] + pub fn lev9(&self) -> LEV9_R { + LEV9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Level 10"] + #[inline(always)] + pub fn lev10(&self) -> LEV10_R { + LEV10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Level 11"] + #[inline(always)] + pub fn lev11(&self) -> LEV11_R { + LEV11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Level 12"] + #[inline(always)] + pub fn lev12(&self) -> LEV12_R { + LEV12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Level 13"] + #[inline(always)] + pub fn lev13(&self) -> LEV13_R { + LEV13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Level 14"] + #[inline(always)] + pub fn lev14(&self) -> LEV14_R { + LEV14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Level 15"] + #[inline(always)] + pub fn lev15(&self) -> LEV15_R { + LEV15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Level 16"] + #[inline(always)] + pub fn lev16(&self) -> LEV16_R { + LEV16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Level 17"] + #[inline(always)] + pub fn lev17(&self) -> LEV17_R { + LEV17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Level 18"] + #[inline(always)] + pub fn lev18(&self) -> LEV18_R { + LEV18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Level 19"] + #[inline(always)] + pub fn lev19(&self) -> LEV19_R { + LEV19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Level 20"] + #[inline(always)] + pub fn lev20(&self) -> LEV20_R { + LEV20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Level 21"] + #[inline(always)] + pub fn lev21(&self) -> LEV21_R { + LEV21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Level 22"] + #[inline(always)] + pub fn lev22(&self) -> LEV22_R { + LEV22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Level 23"] + #[inline(always)] + pub fn lev23(&self) -> LEV23_R { + LEV23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Level 24"] + #[inline(always)] + pub fn lev24(&self) -> LEV24_R { + LEV24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Level 25"] + #[inline(always)] + pub fn lev25(&self) -> LEV25_R { + LEV25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Level 26"] + #[inline(always)] + pub fn lev26(&self) -> LEV26_R { + LEV26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Level 27"] + #[inline(always)] + pub fn lev27(&self) -> LEV27_R { + LEV27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Level 28"] + #[inline(always)] + pub fn lev28(&self) -> LEV28_R { + LEV28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Level 29"] + #[inline(always)] + pub fn lev29(&self) -> LEV29_R { + LEV29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Level 30"] + #[inline(always)] + pub fn lev30(&self) -> LEV30_R { + LEV30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Level 31"] + #[inline(always)] + pub fn lev31(&self) -> LEV31_R { + LEV31_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "GPIO Pin Level 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev0](index.html) module"] +pub struct GPLEV0_SPEC; +impl crate::RegisterSpec for GPLEV0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplev0::R](R) reader structure"] +impl crate::Readable for GPLEV0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/gpio/gplev1.rs b/crates/bcm2837-lpa/src/gpio/gplev1.rs new file mode 100644 index 0000000..5323ce3 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gplev1.rs @@ -0,0 +1,180 @@ +#[doc = "Register `GPLEV1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LEV32` reader - Level 32"] +pub type LEV32_R = crate::BitReader; +#[doc = "Field `LEV33` reader - Level 33"] +pub type LEV33_R = crate::BitReader; +#[doc = "Field `LEV34` reader - Level 34"] +pub type LEV34_R = crate::BitReader; +#[doc = "Field `LEV35` reader - Level 35"] +pub type LEV35_R = crate::BitReader; +#[doc = "Field `LEV36` reader - Level 36"] +pub type LEV36_R = crate::BitReader; +#[doc = "Field `LEV37` reader - Level 37"] +pub type LEV37_R = crate::BitReader; +#[doc = "Field `LEV38` reader - Level 38"] +pub type LEV38_R = crate::BitReader; +#[doc = "Field `LEV39` reader - Level 39"] +pub type LEV39_R = crate::BitReader; +#[doc = "Field `LEV40` reader - Level 40"] +pub type LEV40_R = crate::BitReader; +#[doc = "Field `LEV41` reader - Level 41"] +pub type LEV41_R = crate::BitReader; +#[doc = "Field `LEV42` reader - Level 42"] +pub type LEV42_R = crate::BitReader; +#[doc = "Field `LEV43` reader - Level 43"] +pub type LEV43_R = crate::BitReader; +#[doc = "Field `LEV44` reader - Level 44"] +pub type LEV44_R = crate::BitReader; +#[doc = "Field `LEV45` reader - Level 45"] +pub type LEV45_R = crate::BitReader; +#[doc = "Field `LEV46` reader - Level 46"] +pub type LEV46_R = crate::BitReader; +#[doc = "Field `LEV47` reader - Level 47"] +pub type LEV47_R = crate::BitReader; +#[doc = "Field `LEV48` reader - Level 48"] +pub type LEV48_R = crate::BitReader; +#[doc = "Field `LEV49` reader - Level 49"] +pub type LEV49_R = crate::BitReader; +#[doc = "Field `LEV50` reader - Level 50"] +pub type LEV50_R = crate::BitReader; +#[doc = "Field `LEV51` reader - Level 51"] +pub type LEV51_R = crate::BitReader; +#[doc = "Field `LEV52` reader - Level 52"] +pub type LEV52_R = crate::BitReader; +#[doc = "Field `LEV53` reader - Level 53"] +pub type LEV53_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Level 32"] + #[inline(always)] + pub fn lev32(&self) -> LEV32_R { + LEV32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 33"] + #[inline(always)] + pub fn lev33(&self) -> LEV33_R { + LEV33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 34"] + #[inline(always)] + pub fn lev34(&self) -> LEV34_R { + LEV34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 35"] + #[inline(always)] + pub fn lev35(&self) -> LEV35_R { + LEV35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Level 36"] + #[inline(always)] + pub fn lev36(&self) -> LEV36_R { + LEV36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Level 37"] + #[inline(always)] + pub fn lev37(&self) -> LEV37_R { + LEV37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Level 38"] + #[inline(always)] + pub fn lev38(&self) -> LEV38_R { + LEV38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Level 39"] + #[inline(always)] + pub fn lev39(&self) -> LEV39_R { + LEV39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Level 40"] + #[inline(always)] + pub fn lev40(&self) -> LEV40_R { + LEV40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Level 41"] + #[inline(always)] + pub fn lev41(&self) -> LEV41_R { + LEV41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Level 42"] + #[inline(always)] + pub fn lev42(&self) -> LEV42_R { + LEV42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Level 43"] + #[inline(always)] + pub fn lev43(&self) -> LEV43_R { + LEV43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Level 44"] + #[inline(always)] + pub fn lev44(&self) -> LEV44_R { + LEV44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Level 45"] + #[inline(always)] + pub fn lev45(&self) -> LEV45_R { + LEV45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Level 46"] + #[inline(always)] + pub fn lev46(&self) -> LEV46_R { + LEV46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Level 47"] + #[inline(always)] + pub fn lev47(&self) -> LEV47_R { + LEV47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Level 48"] + #[inline(always)] + pub fn lev48(&self) -> LEV48_R { + LEV48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Level 49"] + #[inline(always)] + pub fn lev49(&self) -> LEV49_R { + LEV49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Level 50"] + #[inline(always)] + pub fn lev50(&self) -> LEV50_R { + LEV50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Level 51"] + #[inline(always)] + pub fn lev51(&self) -> LEV51_R { + LEV51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Level 52"] + #[inline(always)] + pub fn lev52(&self) -> LEV52_R { + LEV52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Level 53"] + #[inline(always)] + pub fn lev53(&self) -> LEV53_R { + LEV53_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[doc = "GPIO Pin Level 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev1](index.html) module"] +pub struct GPLEV1_SPEC; +impl crate::RegisterSpec for GPLEV1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gplev1::R](R) reader structure"] +impl crate::Readable for GPLEV1_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpren0.rs b/crates/bcm2837-lpa/src/gpio/gpren0.rs new file mode 100644 index 0000000..af4f16c --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpren0.rs @@ -0,0 +1,541 @@ +#[doc = "Register `GPREN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REN0` reader - Rising edge enabled 0"] +pub type REN0_R = crate::BitReader; +#[doc = "Field `REN0` writer - Rising edge enabled 0"] +pub type REN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN1` reader - Rising edge enabled 1"] +pub type REN1_R = crate::BitReader; +#[doc = "Field `REN1` writer - Rising edge enabled 1"] +pub type REN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN2` reader - Rising edge enabled 2"] +pub type REN2_R = crate::BitReader; +#[doc = "Field `REN2` writer - Rising edge enabled 2"] +pub type REN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN3` reader - Rising edge enabled 3"] +pub type REN3_R = crate::BitReader; +#[doc = "Field `REN3` writer - Rising edge enabled 3"] +pub type REN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN4` reader - Rising edge enabled 4"] +pub type REN4_R = crate::BitReader; +#[doc = "Field `REN4` writer - Rising edge enabled 4"] +pub type REN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN5` reader - Rising edge enabled 5"] +pub type REN5_R = crate::BitReader; +#[doc = "Field `REN5` writer - Rising edge enabled 5"] +pub type REN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN6` reader - Rising edge enabled 6"] +pub type REN6_R = crate::BitReader; +#[doc = "Field `REN6` writer - Rising edge enabled 6"] +pub type REN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN7` reader - Rising edge enabled 7"] +pub type REN7_R = crate::BitReader; +#[doc = "Field `REN7` writer - Rising edge enabled 7"] +pub type REN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN8` reader - Rising edge enabled 8"] +pub type REN8_R = crate::BitReader; +#[doc = "Field `REN8` writer - Rising edge enabled 8"] +pub type REN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN9` reader - Rising edge enabled 9"] +pub type REN9_R = crate::BitReader; +#[doc = "Field `REN9` writer - Rising edge enabled 9"] +pub type REN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN10` reader - Rising edge enabled 10"] +pub type REN10_R = crate::BitReader; +#[doc = "Field `REN10` writer - Rising edge enabled 10"] +pub type REN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN11` reader - Rising edge enabled 11"] +pub type REN11_R = crate::BitReader; +#[doc = "Field `REN11` writer - Rising edge enabled 11"] +pub type REN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN12` reader - Rising edge enabled 12"] +pub type REN12_R = crate::BitReader; +#[doc = "Field `REN12` writer - Rising edge enabled 12"] +pub type REN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN13` reader - Rising edge enabled 13"] +pub type REN13_R = crate::BitReader; +#[doc = "Field `REN13` writer - Rising edge enabled 13"] +pub type REN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN14` reader - Rising edge enabled 14"] +pub type REN14_R = crate::BitReader; +#[doc = "Field `REN14` writer - Rising edge enabled 14"] +pub type REN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN15` reader - Rising edge enabled 15"] +pub type REN15_R = crate::BitReader; +#[doc = "Field `REN15` writer - Rising edge enabled 15"] +pub type REN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN16` reader - Rising edge enabled 16"] +pub type REN16_R = crate::BitReader; +#[doc = "Field `REN16` writer - Rising edge enabled 16"] +pub type REN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN17` reader - Rising edge enabled 17"] +pub type REN17_R = crate::BitReader; +#[doc = "Field `REN17` writer - Rising edge enabled 17"] +pub type REN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN18` reader - Rising edge enabled 18"] +pub type REN18_R = crate::BitReader; +#[doc = "Field `REN18` writer - Rising edge enabled 18"] +pub type REN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN19` reader - Rising edge enabled 19"] +pub type REN19_R = crate::BitReader; +#[doc = "Field `REN19` writer - Rising edge enabled 19"] +pub type REN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN20` reader - Rising edge enabled 20"] +pub type REN20_R = crate::BitReader; +#[doc = "Field `REN20` writer - Rising edge enabled 20"] +pub type REN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN21` reader - Rising edge enabled 21"] +pub type REN21_R = crate::BitReader; +#[doc = "Field `REN21` writer - Rising edge enabled 21"] +pub type REN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN22` reader - Rising edge enabled 22"] +pub type REN22_R = crate::BitReader; +#[doc = "Field `REN22` writer - Rising edge enabled 22"] +pub type REN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN23` reader - Rising edge enabled 23"] +pub type REN23_R = crate::BitReader; +#[doc = "Field `REN23` writer - Rising edge enabled 23"] +pub type REN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN24` reader - Rising edge enabled 24"] +pub type REN24_R = crate::BitReader; +#[doc = "Field `REN24` writer - Rising edge enabled 24"] +pub type REN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN25` reader - Rising edge enabled 25"] +pub type REN25_R = crate::BitReader; +#[doc = "Field `REN25` writer - Rising edge enabled 25"] +pub type REN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN26` reader - Rising edge enabled 26"] +pub type REN26_R = crate::BitReader; +#[doc = "Field `REN26` writer - Rising edge enabled 26"] +pub type REN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN27` reader - Rising edge enabled 27"] +pub type REN27_R = crate::BitReader; +#[doc = "Field `REN27` writer - Rising edge enabled 27"] +pub type REN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN28` reader - Rising edge enabled 28"] +pub type REN28_R = crate::BitReader; +#[doc = "Field `REN28` writer - Rising edge enabled 28"] +pub type REN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN29` reader - Rising edge enabled 29"] +pub type REN29_R = crate::BitReader; +#[doc = "Field `REN29` writer - Rising edge enabled 29"] +pub type REN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN30` reader - Rising edge enabled 30"] +pub type REN30_R = crate::BitReader; +#[doc = "Field `REN30` writer - Rising edge enabled 30"] +pub type REN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +#[doc = "Field `REN31` reader - Rising edge enabled 31"] +pub type REN31_R = crate::BitReader; +#[doc = "Field `REN31` writer - Rising edge enabled 31"] +pub type REN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Rising edge enabled 0"] + #[inline(always)] + pub fn ren0(&self) -> REN0_R { + REN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rising edge enabled 1"] + #[inline(always)] + pub fn ren1(&self) -> REN1_R { + REN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Rising edge enabled 2"] + #[inline(always)] + pub fn ren2(&self) -> REN2_R { + REN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising edge enabled 3"] + #[inline(always)] + pub fn ren3(&self) -> REN3_R { + REN3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Rising edge enabled 4"] + #[inline(always)] + pub fn ren4(&self) -> REN4_R { + REN4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Rising edge enabled 5"] + #[inline(always)] + pub fn ren5(&self) -> REN5_R { + REN5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising edge enabled 6"] + #[inline(always)] + pub fn ren6(&self) -> REN6_R { + REN6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Rising edge enabled 7"] + #[inline(always)] + pub fn ren7(&self) -> REN7_R { + REN7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Rising edge enabled 8"] + #[inline(always)] + pub fn ren8(&self) -> REN8_R { + REN8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising edge enabled 9"] + #[inline(always)] + pub fn ren9(&self) -> REN9_R { + REN9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Rising edge enabled 10"] + #[inline(always)] + pub fn ren10(&self) -> REN10_R { + REN10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Rising edge enabled 11"] + #[inline(always)] + pub fn ren11(&self) -> REN11_R { + REN11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Rising edge enabled 12"] + #[inline(always)] + pub fn ren12(&self) -> REN12_R { + REN12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Rising edge enabled 13"] + #[inline(always)] + pub fn ren13(&self) -> REN13_R { + REN13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Rising edge enabled 14"] + #[inline(always)] + pub fn ren14(&self) -> REN14_R { + REN14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Rising edge enabled 15"] + #[inline(always)] + pub fn ren15(&self) -> REN15_R { + REN15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Rising edge enabled 16"] + #[inline(always)] + pub fn ren16(&self) -> REN16_R { + REN16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Rising edge enabled 17"] + #[inline(always)] + pub fn ren17(&self) -> REN17_R { + REN17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Rising edge enabled 18"] + #[inline(always)] + pub fn ren18(&self) -> REN18_R { + REN18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Rising edge enabled 19"] + #[inline(always)] + pub fn ren19(&self) -> REN19_R { + REN19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Rising edge enabled 20"] + #[inline(always)] + pub fn ren20(&self) -> REN20_R { + REN20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Rising edge enabled 21"] + #[inline(always)] + pub fn ren21(&self) -> REN21_R { + REN21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Rising edge enabled 22"] + #[inline(always)] + pub fn ren22(&self) -> REN22_R { + REN22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Rising edge enabled 23"] + #[inline(always)] + pub fn ren23(&self) -> REN23_R { + REN23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Rising edge enabled 24"] + #[inline(always)] + pub fn ren24(&self) -> REN24_R { + REN24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Rising edge enabled 25"] + #[inline(always)] + pub fn ren25(&self) -> REN25_R { + REN25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Rising edge enabled 26"] + #[inline(always)] + pub fn ren26(&self) -> REN26_R { + REN26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Rising edge enabled 27"] + #[inline(always)] + pub fn ren27(&self) -> REN27_R { + REN27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Rising edge enabled 28"] + #[inline(always)] + pub fn ren28(&self) -> REN28_R { + REN28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Rising edge enabled 29"] + #[inline(always)] + pub fn ren29(&self) -> REN29_R { + REN29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Rising edge enabled 30"] + #[inline(always)] + pub fn ren30(&self) -> REN30_R { + REN30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Rising edge enabled 31"] + #[inline(always)] + pub fn ren31(&self) -> REN31_R { + REN31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising edge enabled 0"] + #[inline(always)] + #[must_use] + pub fn ren0(&mut self) -> REN0_W<0> { + REN0_W::new(self) + } + #[doc = "Bit 1 - Rising edge enabled 1"] + #[inline(always)] + #[must_use] + pub fn ren1(&mut self) -> REN1_W<1> { + REN1_W::new(self) + } + #[doc = "Bit 2 - Rising edge enabled 2"] + #[inline(always)] + #[must_use] + pub fn ren2(&mut self) -> REN2_W<2> { + REN2_W::new(self) + } + #[doc = "Bit 3 - Rising edge enabled 3"] + #[inline(always)] + #[must_use] + pub fn ren3(&mut self) -> REN3_W<3> { + REN3_W::new(self) + } + #[doc = "Bit 4 - Rising edge enabled 4"] + #[inline(always)] + #[must_use] + pub fn ren4(&mut self) -> REN4_W<4> { + REN4_W::new(self) + } + #[doc = "Bit 5 - Rising edge enabled 5"] + #[inline(always)] + #[must_use] + pub fn ren5(&mut self) -> REN5_W<5> { + REN5_W::new(self) + } + #[doc = "Bit 6 - Rising edge enabled 6"] + #[inline(always)] + #[must_use] + pub fn ren6(&mut self) -> REN6_W<6> { + REN6_W::new(self) + } + #[doc = "Bit 7 - Rising edge enabled 7"] + #[inline(always)] + #[must_use] + pub fn ren7(&mut self) -> REN7_W<7> { + REN7_W::new(self) + } + #[doc = "Bit 8 - Rising edge enabled 8"] + #[inline(always)] + #[must_use] + pub fn ren8(&mut self) -> REN8_W<8> { + REN8_W::new(self) + } + #[doc = "Bit 9 - Rising edge enabled 9"] + #[inline(always)] + #[must_use] + pub fn ren9(&mut self) -> REN9_W<9> { + REN9_W::new(self) + } + #[doc = "Bit 10 - Rising edge enabled 10"] + #[inline(always)] + #[must_use] + pub fn ren10(&mut self) -> REN10_W<10> { + REN10_W::new(self) + } + #[doc = "Bit 11 - Rising edge enabled 11"] + #[inline(always)] + #[must_use] + pub fn ren11(&mut self) -> REN11_W<11> { + REN11_W::new(self) + } + #[doc = "Bit 12 - Rising edge enabled 12"] + #[inline(always)] + #[must_use] + pub fn ren12(&mut self) -> REN12_W<12> { + REN12_W::new(self) + } + #[doc = "Bit 13 - Rising edge enabled 13"] + #[inline(always)] + #[must_use] + pub fn ren13(&mut self) -> REN13_W<13> { + REN13_W::new(self) + } + #[doc = "Bit 14 - Rising edge enabled 14"] + #[inline(always)] + #[must_use] + pub fn ren14(&mut self) -> REN14_W<14> { + REN14_W::new(self) + } + #[doc = "Bit 15 - Rising edge enabled 15"] + #[inline(always)] + #[must_use] + pub fn ren15(&mut self) -> REN15_W<15> { + REN15_W::new(self) + } + #[doc = "Bit 16 - Rising edge enabled 16"] + #[inline(always)] + #[must_use] + pub fn ren16(&mut self) -> REN16_W<16> { + REN16_W::new(self) + } + #[doc = "Bit 17 - Rising edge enabled 17"] + #[inline(always)] + #[must_use] + pub fn ren17(&mut self) -> REN17_W<17> { + REN17_W::new(self) + } + #[doc = "Bit 18 - Rising edge enabled 18"] + #[inline(always)] + #[must_use] + pub fn ren18(&mut self) -> REN18_W<18> { + REN18_W::new(self) + } + #[doc = "Bit 19 - Rising edge enabled 19"] + #[inline(always)] + #[must_use] + pub fn ren19(&mut self) -> REN19_W<19> { + REN19_W::new(self) + } + #[doc = "Bit 20 - Rising edge enabled 20"] + #[inline(always)] + #[must_use] + pub fn ren20(&mut self) -> REN20_W<20> { + REN20_W::new(self) + } + #[doc = "Bit 21 - Rising edge enabled 21"] + #[inline(always)] + #[must_use] + pub fn ren21(&mut self) -> REN21_W<21> { + REN21_W::new(self) + } + #[doc = "Bit 22 - Rising edge enabled 22"] + #[inline(always)] + #[must_use] + pub fn ren22(&mut self) -> REN22_W<22> { + REN22_W::new(self) + } + #[doc = "Bit 23 - Rising edge enabled 23"] + #[inline(always)] + #[must_use] + pub fn ren23(&mut self) -> REN23_W<23> { + REN23_W::new(self) + } + #[doc = "Bit 24 - Rising edge enabled 24"] + #[inline(always)] + #[must_use] + pub fn ren24(&mut self) -> REN24_W<24> { + REN24_W::new(self) + } + #[doc = "Bit 25 - Rising edge enabled 25"] + #[inline(always)] + #[must_use] + pub fn ren25(&mut self) -> REN25_W<25> { + REN25_W::new(self) + } + #[doc = "Bit 26 - Rising edge enabled 26"] + #[inline(always)] + #[must_use] + pub fn ren26(&mut self) -> REN26_W<26> { + REN26_W::new(self) + } + #[doc = "Bit 27 - Rising edge enabled 27"] + #[inline(always)] + #[must_use] + pub fn ren27(&mut self) -> REN27_W<27> { + REN27_W::new(self) + } + #[doc = "Bit 28 - Rising edge enabled 28"] + #[inline(always)] + #[must_use] + pub fn ren28(&mut self) -> REN28_W<28> { + REN28_W::new(self) + } + #[doc = "Bit 29 - Rising edge enabled 29"] + #[inline(always)] + #[must_use] + pub fn ren29(&mut self) -> REN29_W<29> { + REN29_W::new(self) + } + #[doc = "Bit 30 - Rising edge enabled 30"] + #[inline(always)] + #[must_use] + pub fn ren30(&mut self) -> REN30_W<30> { + REN30_W::new(self) + } + #[doc = "Bit 31 - Rising edge enabled 31"] + #[inline(always)] + #[must_use] + pub fn ren31(&mut self) -> REN31_W<31> { + REN31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren0](index.html) module"] +pub struct GPREN0_SPEC; +impl crate::RegisterSpec for GPREN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpren0::R](R) reader structure"] +impl crate::Readable for GPREN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpren0::W](W) writer structure"] +impl crate::Writable for GPREN0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpren1.rs b/crates/bcm2837-lpa/src/gpio/gpren1.rs new file mode 100644 index 0000000..3e70995 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpren1.rs @@ -0,0 +1,391 @@ +#[doc = "Register `GPREN1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GPREN1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REN32` reader - Rising edge enabled 32"] +pub type REN32_R = crate::BitReader; +#[doc = "Field `REN32` writer - Rising edge enabled 32"] +pub type REN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN33` reader - Rising edge enabled 33"] +pub type REN33_R = crate::BitReader; +#[doc = "Field `REN33` writer - Rising edge enabled 33"] +pub type REN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN34` reader - Rising edge enabled 34"] +pub type REN34_R = crate::BitReader; +#[doc = "Field `REN34` writer - Rising edge enabled 34"] +pub type REN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN35` reader - Rising edge enabled 35"] +pub type REN35_R = crate::BitReader; +#[doc = "Field `REN35` writer - Rising edge enabled 35"] +pub type REN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN36` reader - Rising edge enabled 36"] +pub type REN36_R = crate::BitReader; +#[doc = "Field `REN36` writer - Rising edge enabled 36"] +pub type REN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN37` reader - Rising edge enabled 37"] +pub type REN37_R = crate::BitReader; +#[doc = "Field `REN37` writer - Rising edge enabled 37"] +pub type REN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN38` reader - Rising edge enabled 38"] +pub type REN38_R = crate::BitReader; +#[doc = "Field `REN38` writer - Rising edge enabled 38"] +pub type REN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN39` reader - Rising edge enabled 39"] +pub type REN39_R = crate::BitReader; +#[doc = "Field `REN39` writer - Rising edge enabled 39"] +pub type REN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN40` reader - Rising edge enabled 40"] +pub type REN40_R = crate::BitReader; +#[doc = "Field `REN40` writer - Rising edge enabled 40"] +pub type REN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN41` reader - Rising edge enabled 41"] +pub type REN41_R = crate::BitReader; +#[doc = "Field `REN41` writer - Rising edge enabled 41"] +pub type REN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN42` reader - Rising edge enabled 42"] +pub type REN42_R = crate::BitReader; +#[doc = "Field `REN42` writer - Rising edge enabled 42"] +pub type REN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN43` reader - Rising edge enabled 43"] +pub type REN43_R = crate::BitReader; +#[doc = "Field `REN43` writer - Rising edge enabled 43"] +pub type REN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN44` reader - Rising edge enabled 44"] +pub type REN44_R = crate::BitReader; +#[doc = "Field `REN44` writer - Rising edge enabled 44"] +pub type REN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN45` reader - Rising edge enabled 45"] +pub type REN45_R = crate::BitReader; +#[doc = "Field `REN45` writer - Rising edge enabled 45"] +pub type REN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN46` reader - Rising edge enabled 46"] +pub type REN46_R = crate::BitReader; +#[doc = "Field `REN46` writer - Rising edge enabled 46"] +pub type REN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN47` reader - Rising edge enabled 47"] +pub type REN47_R = crate::BitReader; +#[doc = "Field `REN47` writer - Rising edge enabled 47"] +pub type REN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN48` reader - Rising edge enabled 48"] +pub type REN48_R = crate::BitReader; +#[doc = "Field `REN48` writer - Rising edge enabled 48"] +pub type REN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN49` reader - Rising edge enabled 49"] +pub type REN49_R = crate::BitReader; +#[doc = "Field `REN49` writer - Rising edge enabled 49"] +pub type REN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN50` reader - Rising edge enabled 50"] +pub type REN50_R = crate::BitReader; +#[doc = "Field `REN50` writer - Rising edge enabled 50"] +pub type REN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN51` reader - Rising edge enabled 51"] +pub type REN51_R = crate::BitReader; +#[doc = "Field `REN51` writer - Rising edge enabled 51"] +pub type REN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN52` reader - Rising edge enabled 52"] +pub type REN52_R = crate::BitReader; +#[doc = "Field `REN52` writer - Rising edge enabled 52"] +pub type REN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +#[doc = "Field `REN53` reader - Rising edge enabled 53"] +pub type REN53_R = crate::BitReader; +#[doc = "Field `REN53` writer - Rising edge enabled 53"] +pub type REN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Rising edge enabled 32"] + #[inline(always)] + pub fn ren32(&self) -> REN32_R { + REN32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rising edge enabled 33"] + #[inline(always)] + pub fn ren33(&self) -> REN33_R { + REN33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Rising edge enabled 34"] + #[inline(always)] + pub fn ren34(&self) -> REN34_R { + REN34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Rising edge enabled 35"] + #[inline(always)] + pub fn ren35(&self) -> REN35_R { + REN35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Rising edge enabled 36"] + #[inline(always)] + pub fn ren36(&self) -> REN36_R { + REN36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Rising edge enabled 37"] + #[inline(always)] + pub fn ren37(&self) -> REN37_R { + REN37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Rising edge enabled 38"] + #[inline(always)] + pub fn ren38(&self) -> REN38_R { + REN38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Rising edge enabled 39"] + #[inline(always)] + pub fn ren39(&self) -> REN39_R { + REN39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Rising edge enabled 40"] + #[inline(always)] + pub fn ren40(&self) -> REN40_R { + REN40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Rising edge enabled 41"] + #[inline(always)] + pub fn ren41(&self) -> REN41_R { + REN41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Rising edge enabled 42"] + #[inline(always)] + pub fn ren42(&self) -> REN42_R { + REN42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Rising edge enabled 43"] + #[inline(always)] + pub fn ren43(&self) -> REN43_R { + REN43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Rising edge enabled 44"] + #[inline(always)] + pub fn ren44(&self) -> REN44_R { + REN44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Rising edge enabled 45"] + #[inline(always)] + pub fn ren45(&self) -> REN45_R { + REN45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Rising edge enabled 46"] + #[inline(always)] + pub fn ren46(&self) -> REN46_R { + REN46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Rising edge enabled 47"] + #[inline(always)] + pub fn ren47(&self) -> REN47_R { + REN47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Rising edge enabled 48"] + #[inline(always)] + pub fn ren48(&self) -> REN48_R { + REN48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Rising edge enabled 49"] + #[inline(always)] + pub fn ren49(&self) -> REN49_R { + REN49_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Rising edge enabled 50"] + #[inline(always)] + pub fn ren50(&self) -> REN50_R { + REN50_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Rising edge enabled 51"] + #[inline(always)] + pub fn ren51(&self) -> REN51_R { + REN51_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Rising edge enabled 52"] + #[inline(always)] + pub fn ren52(&self) -> REN52_R { + REN52_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Rising edge enabled 53"] + #[inline(always)] + pub fn ren53(&self) -> REN53_R { + REN53_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rising edge enabled 32"] + #[inline(always)] + #[must_use] + pub fn ren32(&mut self) -> REN32_W<0> { + REN32_W::new(self) + } + #[doc = "Bit 1 - Rising edge enabled 33"] + #[inline(always)] + #[must_use] + pub fn ren33(&mut self) -> REN33_W<1> { + REN33_W::new(self) + } + #[doc = "Bit 2 - Rising edge enabled 34"] + #[inline(always)] + #[must_use] + pub fn ren34(&mut self) -> REN34_W<2> { + REN34_W::new(self) + } + #[doc = "Bit 3 - Rising edge enabled 35"] + #[inline(always)] + #[must_use] + pub fn ren35(&mut self) -> REN35_W<3> { + REN35_W::new(self) + } + #[doc = "Bit 4 - Rising edge enabled 36"] + #[inline(always)] + #[must_use] + pub fn ren36(&mut self) -> REN36_W<4> { + REN36_W::new(self) + } + #[doc = "Bit 5 - Rising edge enabled 37"] + #[inline(always)] + #[must_use] + pub fn ren37(&mut self) -> REN37_W<5> { + REN37_W::new(self) + } + #[doc = "Bit 6 - Rising edge enabled 38"] + #[inline(always)] + #[must_use] + pub fn ren38(&mut self) -> REN38_W<6> { + REN38_W::new(self) + } + #[doc = "Bit 7 - Rising edge enabled 39"] + #[inline(always)] + #[must_use] + pub fn ren39(&mut self) -> REN39_W<7> { + REN39_W::new(self) + } + #[doc = "Bit 8 - Rising edge enabled 40"] + #[inline(always)] + #[must_use] + pub fn ren40(&mut self) -> REN40_W<8> { + REN40_W::new(self) + } + #[doc = "Bit 9 - Rising edge enabled 41"] + #[inline(always)] + #[must_use] + pub fn ren41(&mut self) -> REN41_W<9> { + REN41_W::new(self) + } + #[doc = "Bit 10 - Rising edge enabled 42"] + #[inline(always)] + #[must_use] + pub fn ren42(&mut self) -> REN42_W<10> { + REN42_W::new(self) + } + #[doc = "Bit 11 - Rising edge enabled 43"] + #[inline(always)] + #[must_use] + pub fn ren43(&mut self) -> REN43_W<11> { + REN43_W::new(self) + } + #[doc = "Bit 12 - Rising edge enabled 44"] + #[inline(always)] + #[must_use] + pub fn ren44(&mut self) -> REN44_W<12> { + REN44_W::new(self) + } + #[doc = "Bit 13 - Rising edge enabled 45"] + #[inline(always)] + #[must_use] + pub fn ren45(&mut self) -> REN45_W<13> { + REN45_W::new(self) + } + #[doc = "Bit 14 - Rising edge enabled 46"] + #[inline(always)] + #[must_use] + pub fn ren46(&mut self) -> REN46_W<14> { + REN46_W::new(self) + } + #[doc = "Bit 15 - Rising edge enabled 47"] + #[inline(always)] + #[must_use] + pub fn ren47(&mut self) -> REN47_W<15> { + REN47_W::new(self) + } + #[doc = "Bit 16 - Rising edge enabled 48"] + #[inline(always)] + #[must_use] + pub fn ren48(&mut self) -> REN48_W<16> { + REN48_W::new(self) + } + #[doc = "Bit 17 - Rising edge enabled 49"] + #[inline(always)] + #[must_use] + pub fn ren49(&mut self) -> REN49_W<17> { + REN49_W::new(self) + } + #[doc = "Bit 18 - Rising edge enabled 50"] + #[inline(always)] + #[must_use] + pub fn ren50(&mut self) -> REN50_W<18> { + REN50_W::new(self) + } + #[doc = "Bit 19 - Rising edge enabled 51"] + #[inline(always)] + #[must_use] + pub fn ren51(&mut self) -> REN51_W<19> { + REN51_W::new(self) + } + #[doc = "Bit 20 - Rising edge enabled 52"] + #[inline(always)] + #[must_use] + pub fn ren52(&mut self) -> REN52_W<20> { + REN52_W::new(self) + } + #[doc = "Bit 21 - Rising edge enabled 53"] + #[inline(always)] + #[must_use] + pub fn ren53(&mut self) -> REN53_W<21> { + REN53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren1](index.html) module"] +pub struct GPREN1_SPEC; +impl crate::RegisterSpec for GPREN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gpren1::R](R) reader structure"] +impl crate::Readable for GPREN1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gpren1::W](W) writer structure"] +impl crate::Writable for GPREN1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpset0.rs b/crates/bcm2837-lpa/src/gpio/gpset0.rs new file mode 100644 index 0000000..49e2659 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpset0.rs @@ -0,0 +1,296 @@ +#[doc = "Register `GPSET0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SET0` writer - Set 0"] +pub type SET0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET1` writer - Set 1"] +pub type SET1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET2` writer - Set 2"] +pub type SET2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET3` writer - Set 3"] +pub type SET3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET4` writer - Set 4"] +pub type SET4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET5` writer - Set 5"] +pub type SET5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET6` writer - Set 6"] +pub type SET6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET7` writer - Set 7"] +pub type SET7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET8` writer - Set 8"] +pub type SET8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET9` writer - Set 9"] +pub type SET9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET10` writer - Set 10"] +pub type SET10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET11` writer - Set 11"] +pub type SET11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET12` writer - Set 12"] +pub type SET12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET13` writer - Set 13"] +pub type SET13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET14` writer - Set 14"] +pub type SET14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET15` writer - Set 15"] +pub type SET15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET16` writer - Set 16"] +pub type SET16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET17` writer - Set 17"] +pub type SET17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET18` writer - Set 18"] +pub type SET18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET19` writer - Set 19"] +pub type SET19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET20` writer - Set 20"] +pub type SET20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET21` writer - Set 21"] +pub type SET21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET22` writer - Set 22"] +pub type SET22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET23` writer - Set 23"] +pub type SET23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET24` writer - Set 24"] +pub type SET24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET25` writer - Set 25"] +pub type SET25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET26` writer - Set 26"] +pub type SET26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET27` writer - Set 27"] +pub type SET27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET28` writer - Set 28"] +pub type SET28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET29` writer - Set 29"] +pub type SET29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET30` writer - Set 30"] +pub type SET30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +#[doc = "Field `SET31` writer - Set 31"] +pub type SET31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Set 0"] + #[inline(always)] + #[must_use] + pub fn set0(&mut self) -> SET0_W<0> { + SET0_W::new(self) + } + #[doc = "Bit 1 - Set 1"] + #[inline(always)] + #[must_use] + pub fn set1(&mut self) -> SET1_W<1> { + SET1_W::new(self) + } + #[doc = "Bit 2 - Set 2"] + #[inline(always)] + #[must_use] + pub fn set2(&mut self) -> SET2_W<2> { + SET2_W::new(self) + } + #[doc = "Bit 3 - Set 3"] + #[inline(always)] + #[must_use] + pub fn set3(&mut self) -> SET3_W<3> { + SET3_W::new(self) + } + #[doc = "Bit 4 - Set 4"] + #[inline(always)] + #[must_use] + pub fn set4(&mut self) -> SET4_W<4> { + SET4_W::new(self) + } + #[doc = "Bit 5 - Set 5"] + #[inline(always)] + #[must_use] + pub fn set5(&mut self) -> SET5_W<5> { + SET5_W::new(self) + } + #[doc = "Bit 6 - Set 6"] + #[inline(always)] + #[must_use] + pub fn set6(&mut self) -> SET6_W<6> { + SET6_W::new(self) + } + #[doc = "Bit 7 - Set 7"] + #[inline(always)] + #[must_use] + pub fn set7(&mut self) -> SET7_W<7> { + SET7_W::new(self) + } + #[doc = "Bit 8 - Set 8"] + #[inline(always)] + #[must_use] + pub fn set8(&mut self) -> SET8_W<8> { + SET8_W::new(self) + } + #[doc = "Bit 9 - Set 9"] + #[inline(always)] + #[must_use] + pub fn set9(&mut self) -> SET9_W<9> { + SET9_W::new(self) + } + #[doc = "Bit 10 - Set 10"] + #[inline(always)] + #[must_use] + pub fn set10(&mut self) -> SET10_W<10> { + SET10_W::new(self) + } + #[doc = "Bit 11 - Set 11"] + #[inline(always)] + #[must_use] + pub fn set11(&mut self) -> SET11_W<11> { + SET11_W::new(self) + } + #[doc = "Bit 12 - Set 12"] + #[inline(always)] + #[must_use] + pub fn set12(&mut self) -> SET12_W<12> { + SET12_W::new(self) + } + #[doc = "Bit 13 - Set 13"] + #[inline(always)] + #[must_use] + pub fn set13(&mut self) -> SET13_W<13> { + SET13_W::new(self) + } + #[doc = "Bit 14 - Set 14"] + #[inline(always)] + #[must_use] + pub fn set14(&mut self) -> SET14_W<14> { + SET14_W::new(self) + } + #[doc = "Bit 15 - Set 15"] + #[inline(always)] + #[must_use] + pub fn set15(&mut self) -> SET15_W<15> { + SET15_W::new(self) + } + #[doc = "Bit 16 - Set 16"] + #[inline(always)] + #[must_use] + pub fn set16(&mut self) -> SET16_W<16> { + SET16_W::new(self) + } + #[doc = "Bit 17 - Set 17"] + #[inline(always)] + #[must_use] + pub fn set17(&mut self) -> SET17_W<17> { + SET17_W::new(self) + } + #[doc = "Bit 18 - Set 18"] + #[inline(always)] + #[must_use] + pub fn set18(&mut self) -> SET18_W<18> { + SET18_W::new(self) + } + #[doc = "Bit 19 - Set 19"] + #[inline(always)] + #[must_use] + pub fn set19(&mut self) -> SET19_W<19> { + SET19_W::new(self) + } + #[doc = "Bit 20 - Set 20"] + #[inline(always)] + #[must_use] + pub fn set20(&mut self) -> SET20_W<20> { + SET20_W::new(self) + } + #[doc = "Bit 21 - Set 21"] + #[inline(always)] + #[must_use] + pub fn set21(&mut self) -> SET21_W<21> { + SET21_W::new(self) + } + #[doc = "Bit 22 - Set 22"] + #[inline(always)] + #[must_use] + pub fn set22(&mut self) -> SET22_W<22> { + SET22_W::new(self) + } + #[doc = "Bit 23 - Set 23"] + #[inline(always)] + #[must_use] + pub fn set23(&mut self) -> SET23_W<23> { + SET23_W::new(self) + } + #[doc = "Bit 24 - Set 24"] + #[inline(always)] + #[must_use] + pub fn set24(&mut self) -> SET24_W<24> { + SET24_W::new(self) + } + #[doc = "Bit 25 - Set 25"] + #[inline(always)] + #[must_use] + pub fn set25(&mut self) -> SET25_W<25> { + SET25_W::new(self) + } + #[doc = "Bit 26 - Set 26"] + #[inline(always)] + #[must_use] + pub fn set26(&mut self) -> SET26_W<26> { + SET26_W::new(self) + } + #[doc = "Bit 27 - Set 27"] + #[inline(always)] + #[must_use] + pub fn set27(&mut self) -> SET27_W<27> { + SET27_W::new(self) + } + #[doc = "Bit 28 - Set 28"] + #[inline(always)] + #[must_use] + pub fn set28(&mut self) -> SET28_W<28> { + SET28_W::new(self) + } + #[doc = "Bit 29 - Set 29"] + #[inline(always)] + #[must_use] + pub fn set29(&mut self) -> SET29_W<29> { + SET29_W::new(self) + } + #[doc = "Bit 30 - Set 30"] + #[inline(always)] + #[must_use] + pub fn set30(&mut self) -> SET30_W<30> { + SET30_W::new(self) + } + #[doc = "Bit 31 - Set 31"] + #[inline(always)] + #[must_use] + pub fn set31(&mut self) -> SET31_W<31> { + SET31_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Set 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset0](index.html) module"] +pub struct GPSET0_SPEC; +impl crate::RegisterSpec for GPSET0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpset0::W](W) writer structure"] +impl crate::Writable for GPSET0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} diff --git a/crates/bcm2837-lpa/src/gpio/gpset1.rs b/crates/bcm2837-lpa/src/gpio/gpset1.rs new file mode 100644 index 0000000..84f73e5 --- /dev/null +++ b/crates/bcm2837-lpa/src/gpio/gpset1.rs @@ -0,0 +1,216 @@ +#[doc = "Register `GPSET1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SET32` writer - Set 32"] +pub type SET32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET33` writer - Set 33"] +pub type SET33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET34` writer - Set 34"] +pub type SET34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET35` writer - Set 35"] +pub type SET35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET36` writer - Set 36"] +pub type SET36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET37` writer - Set 37"] +pub type SET37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET38` writer - Set 38"] +pub type SET38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET39` writer - Set 39"] +pub type SET39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET40` writer - Set 40"] +pub type SET40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET41` writer - Set 41"] +pub type SET41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET42` writer - Set 42"] +pub type SET42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET43` writer - Set 43"] +pub type SET43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET44` writer - Set 44"] +pub type SET44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET45` writer - Set 45"] +pub type SET45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET46` writer - Set 46"] +pub type SET46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET47` writer - Set 47"] +pub type SET47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET48` writer - Set 48"] +pub type SET48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET49` writer - Set 49"] +pub type SET49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET50` writer - Set 50"] +pub type SET50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET51` writer - Set 51"] +pub type SET51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET52` writer - Set 52"] +pub type SET52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +#[doc = "Field `SET53` writer - Set 53"] +pub type SET53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Set 32"] + #[inline(always)] + #[must_use] + pub fn set32(&mut self) -> SET32_W<0> { + SET32_W::new(self) + } + #[doc = "Bit 1 - Set 33"] + #[inline(always)] + #[must_use] + pub fn set33(&mut self) -> SET33_W<1> { + SET33_W::new(self) + } + #[doc = "Bit 2 - Set 34"] + #[inline(always)] + #[must_use] + pub fn set34(&mut self) -> SET34_W<2> { + SET34_W::new(self) + } + #[doc = "Bit 3 - Set 35"] + #[inline(always)] + #[must_use] + pub fn set35(&mut self) -> SET35_W<3> { + SET35_W::new(self) + } + #[doc = "Bit 4 - Set 36"] + #[inline(always)] + #[must_use] + pub fn set36(&mut self) -> SET36_W<4> { + SET36_W::new(self) + } + #[doc = "Bit 5 - Set 37"] + #[inline(always)] + #[must_use] + pub fn set37(&mut self) -> SET37_W<5> { + SET37_W::new(self) + } + #[doc = "Bit 6 - Set 38"] + #[inline(always)] + #[must_use] + pub fn set38(&mut self) -> SET38_W<6> { + SET38_W::new(self) + } + #[doc = "Bit 7 - Set 39"] + #[inline(always)] + #[must_use] + pub fn set39(&mut self) -> SET39_W<7> { + SET39_W::new(self) + } + #[doc = "Bit 8 - Set 40"] + #[inline(always)] + #[must_use] + pub fn set40(&mut self) -> SET40_W<8> { + SET40_W::new(self) + } + #[doc = "Bit 9 - Set 41"] + #[inline(always)] + #[must_use] + pub fn set41(&mut self) -> SET41_W<9> { + SET41_W::new(self) + } + #[doc = "Bit 10 - Set 42"] + #[inline(always)] + #[must_use] + pub fn set42(&mut self) -> SET42_W<10> { + SET42_W::new(self) + } + #[doc = "Bit 11 - Set 43"] + #[inline(always)] + #[must_use] + pub fn set43(&mut self) -> SET43_W<11> { + SET43_W::new(self) + } + #[doc = "Bit 12 - Set 44"] + #[inline(always)] + #[must_use] + pub fn set44(&mut self) -> SET44_W<12> { + SET44_W::new(self) + } + #[doc = "Bit 13 - Set 45"] + #[inline(always)] + #[must_use] + pub fn set45(&mut self) -> SET45_W<13> { + SET45_W::new(self) + } + #[doc = "Bit 14 - Set 46"] + #[inline(always)] + #[must_use] + pub fn set46(&mut self) -> SET46_W<14> { + SET46_W::new(self) + } + #[doc = "Bit 15 - Set 47"] + #[inline(always)] + #[must_use] + pub fn set47(&mut self) -> SET47_W<15> { + SET47_W::new(self) + } + #[doc = "Bit 16 - Set 48"] + #[inline(always)] + #[must_use] + pub fn set48(&mut self) -> SET48_W<16> { + SET48_W::new(self) + } + #[doc = "Bit 17 - Set 49"] + #[inline(always)] + #[must_use] + pub fn set49(&mut self) -> SET49_W<17> { + SET49_W::new(self) + } + #[doc = "Bit 18 - Set 50"] + #[inline(always)] + #[must_use] + pub fn set50(&mut self) -> SET50_W<18> { + SET50_W::new(self) + } + #[doc = "Bit 19 - Set 51"] + #[inline(always)] + #[must_use] + pub fn set51(&mut self) -> SET51_W<19> { + SET51_W::new(self) + } + #[doc = "Bit 20 - Set 52"] + #[inline(always)] + #[must_use] + pub fn set52(&mut self) -> SET52_W<20> { + SET52_W::new(self) + } + #[doc = "Bit 21 - Set 53"] + #[inline(always)] + #[must_use] + pub fn set53(&mut self) -> SET53_W<21> { + SET53_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "GPIO Pin Output Set 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset1](index.html) module"] +pub struct GPSET1_SPEC; +impl crate::RegisterSpec for GPSET1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [gpset1::W](W) writer structure"] +impl crate::Writable for GPSET1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; +} diff --git a/crates/bcm2837-lpa/src/interrupt.rs b/crates/bcm2837-lpa/src/interrupt.rs new file mode 100644 index 0000000..da6cbf5 --- /dev/null +++ b/crates/bcm2837-lpa/src/interrupt.rs @@ -0,0 +1,59 @@ +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - Timer 0 matched"] + TIMER_0 = 0, + #[doc = "1 - Timer 1 matched"] + TIMER_1 = 1, + #[doc = "2 - Timer 2 matched"] + TIMER_2 = 2, + #[doc = "3 - Timer 3 matched"] + TIMER_3 = 3, + #[doc = "9 - USB interrupt"] + USB = 9, + #[doc = "29 - Interrupt from AUX"] + AUX = 29, + #[doc = "49 - Interrupt from bank 0"] + GPIO0 = 49, + #[doc = "50 - Interrupt from bank 1"] + GPIO1 = 50, + #[doc = "51 - Interrupt from bank 2"] + GPIO2 = 51, + #[doc = "52 - OR of all GPIO interrupts"] + GPIO = 52, + #[doc = "53 - OR of all I2C interrupts"] + I2C = 53, + #[doc = "54 - OR of all SPI interrupts except 1 and 2"] + SPI = 54, + #[doc = "57 - OR of all UART interrupts except 1"] + UART = 57, + #[doc = "62 - OR of EMMC and EMMC2"] + EMMC = 62, +} +#[doc = r" TryFromInterruptError"] +#[derive(Debug, Copy, Clone)] +pub struct TryFromInterruptError(()); +impl Interrupt { + #[doc = r" Attempt to convert a given value into an `Interrupt`"] + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 0 => Ok(Interrupt::TIMER_0), + 1 => Ok(Interrupt::TIMER_1), + 2 => Ok(Interrupt::TIMER_2), + 3 => Ok(Interrupt::TIMER_3), + 9 => Ok(Interrupt::USB), + 29 => Ok(Interrupt::AUX), + 49 => Ok(Interrupt::GPIO0), + 50 => Ok(Interrupt::GPIO1), + 51 => Ok(Interrupt::GPIO2), + 52 => Ok(Interrupt::GPIO), + 53 => Ok(Interrupt::I2C), + 54 => Ok(Interrupt::SPI), + 57 => Ok(Interrupt::UART), + 62 => Ok(Interrupt::EMMC), + _ => Err(TryFromInterruptError(())), + } + } +} diff --git a/crates/bcm2837-lpa/src/lib.rs b/crates/bcm2837-lpa/src/lib.rs new file mode 100644 index 0000000..2647c5a --- /dev/null +++ b/crates/bcm2837-lpa/src/lib.rs @@ -0,0 +1,753 @@ +#![doc = "Peripheral access API for BCM2837_LPA microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[doc(hidden)] +pub mod interrupt; +pub use self::interrupt::Interrupt; +#[doc = "Mailboxes for talking to/from VideoCore"] +pub struct VCMAILBOX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for VCMAILBOX {} +impl VCMAILBOX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const vcmailbox::RegisterBlock = 0x3f00_b880 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const vcmailbox::RegisterBlock { + Self::PTR + } +} +impl Deref for VCMAILBOX { + type Target = vcmailbox::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for VCMAILBOX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VCMAILBOX").finish() + } +} +#[doc = "Mailboxes for talking to/from VideoCore"] +pub mod vcmailbox; +#[doc = "Broadcom Clock Manager"] +pub struct CM_PCM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CM_PCM {} +impl CM_PCM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cm_pcm::RegisterBlock = 0x3f10_1098 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cm_pcm::RegisterBlock { + Self::PTR + } +} +impl Deref for CM_PCM { + type Target = cm_pcm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CM_PCM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CM_PCM").finish() + } +} +#[doc = "Broadcom Clock Manager"] +pub mod cm_pcm; +#[doc = "Broadcom Clock Manager"] +pub struct CM_PWM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CM_PWM {} +impl CM_PWM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cm_pcm::RegisterBlock = 0x3f10_10a0 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cm_pcm::RegisterBlock { + Self::PTR + } +} +impl Deref for CM_PWM { + type Target = cm_pcm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CM_PWM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CM_PWM").finish() + } +} +#[doc = "Broadcom Clock Manager"] +pub use self::cm_pcm as cm_pwm; +#[doc = "Pin level and mux control"] +pub struct GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO {} +impl GPIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio::RegisterBlock = 0x3f20_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio::RegisterBlock { + Self::PTR + } +} +impl Deref for GPIO { + type Target = gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO").finish() + } +} +#[doc = "Pin level and mux control"] +pub mod gpio; +#[doc = "Broadcom System Timer"] +pub struct SYSTMR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTMR {} +impl SYSTMR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const systmr::RegisterBlock = 0x3f00_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const systmr::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTMR { + type Target = systmr::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTMR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTMR").finish() + } +} +#[doc = "Broadcom System Timer"] +pub mod systmr; +#[doc = "ARM Prime Cell PL011"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x3f20_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "ARM Prime Cell PL011"] +pub mod uart0; +#[doc = "Broadcom SPI Controller"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x3f20_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "Broadcom SPI Controller"] +pub mod spi0; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC0 {} +impl BSC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0x3f20_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC0 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC0").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub mod bsc0; +#[doc = "Broadcom PWM"] +pub struct PWM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM0 {} +impl PWM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm0::RegisterBlock = 0x3f20_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm0::RegisterBlock { + Self::PTR + } +} +impl Deref for PWM0 { + type Target = pwm0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0").finish() + } +} +#[doc = "Broadcom PWM"] +pub mod pwm0; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC1 {} +impl BSC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0x3f80_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC1 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC1").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc1; +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub struct BSC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BSC2 {} +impl BSC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bsc0::RegisterBlock = 0x3f80_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bsc0::RegisterBlock { + Self::PTR + } +} +impl Deref for BSC2 { + type Target = bsc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BSC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BSC2").finish() + } +} +#[doc = "Broadcom Serial Controller (I2C compatible)"] +pub use self::bsc0 as bsc2; +#[doc = "Three auxiliary peripherals"] +pub struct AUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AUX {} +impl AUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const aux::RegisterBlock = 0x3f21_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aux::RegisterBlock { + Self::PTR + } +} +impl Deref for AUX { + type Target = aux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AUX").finish() + } +} +#[doc = "Three auxiliary peripherals"] +pub mod aux; +#[doc = "Mini UART"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart1::RegisterBlock = 0x3f21_5040 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart1::RegisterBlock { + Self::PTR + } +} +impl Deref for UART1 { + type Target = uart1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "Mini UART"] +pub mod uart1; +#[doc = "Aux SPI"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0x3f21_5080 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI1 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "Aux SPI"] +pub mod spi1; +#[doc = "Aux SPI"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0x3f21_50c0 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI2 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2").finish() + } +} +#[doc = "Aux SPI"] +pub use self::spi1 as spi2; +#[doc = "Broadcom Legacy Interrupt Controller"] +pub struct LIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LIC {} +impl LIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lic::RegisterBlock = 0x3f00_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lic::RegisterBlock { + Self::PTR + } +} +impl Deref for LIC { + type Target = lic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LIC").finish() + } +} +#[doc = "Broadcom Legacy Interrupt Controller"] +pub mod lic; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_GLOBAL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_GLOBAL {} +impl USB_OTG_GLOBAL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_global::RegisterBlock = 0x3f98_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_global::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_GLOBAL { + type Target = usb_otg_global::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_GLOBAL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_GLOBAL").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_global; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_HOST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_HOST {} +impl USB_OTG_HOST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_host::RegisterBlock = 0x3f98_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_host::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_HOST { + type Target = usb_otg_host::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_HOST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_HOST").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_host; +#[doc = "USB on the go high speed"] +pub struct USB_OTG_DEVICE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_DEVICE {} +impl USB_OTG_DEVICE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_device::RegisterBlock = 0x3f98_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_device::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_DEVICE { + type Target = usb_otg_device::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_DEVICE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_DEVICE").finish() + } +} +#[doc = "USB on the go high speed"] +pub mod usb_otg_device; +#[doc = "USB on the go high speed power control"] +pub struct USB_OTG_PWRCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_OTG_PWRCLK {} +impl USB_OTG_PWRCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_otg_pwrclk::RegisterBlock = 0x3f98_0e00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_otg_pwrclk::RegisterBlock { + Self::PTR + } +} +impl Deref for USB_OTG_PWRCLK { + type Target = usb_otg_pwrclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_OTG_PWRCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_PWRCLK").finish() + } +} +#[doc = "USB on the go high speed power control"] +pub mod usb_otg_pwrclk; +#[doc = "Arasan SD3.0 Host AHB eMMC 4.4"] +pub struct EMMC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EMMC {} +impl EMMC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const emmc::RegisterBlock = 0x3f30_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const emmc::RegisterBlock { + Self::PTR + } +} +impl Deref for EMMC { + type Target = emmc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EMMC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EMMC").finish() + } +} +#[doc = "Arasan SD3.0 Host AHB eMMC 4.4"] +pub mod emmc; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "VCMAILBOX"] + pub VCMAILBOX: VCMAILBOX, + #[doc = "CM_PCM"] + pub CM_PCM: CM_PCM, + #[doc = "CM_PWM"] + pub CM_PWM: CM_PWM, + #[doc = "GPIO"] + pub GPIO: GPIO, + #[doc = "SYSTMR"] + pub SYSTMR: SYSTMR, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "BSC0"] + pub BSC0: BSC0, + #[doc = "PWM0"] + pub PWM0: PWM0, + #[doc = "BSC1"] + pub BSC1: BSC1, + #[doc = "BSC2"] + pub BSC2: BSC2, + #[doc = "AUX"] + pub AUX: AUX, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "LIC"] + pub LIC: LIC, + #[doc = "USB_OTG_GLOBAL"] + pub USB_OTG_GLOBAL: USB_OTG_GLOBAL, + #[doc = "USB_OTG_HOST"] + pub USB_OTG_HOST: USB_OTG_HOST, + #[doc = "USB_OTG_DEVICE"] + pub USB_OTG_DEVICE: USB_OTG_DEVICE, + #[doc = "USB_OTG_PWRCLK"] + pub USB_OTG_PWRCLK: USB_OTG_PWRCLK, + #[doc = "EMMC"] + pub EMMC: EMMC, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + VCMAILBOX: VCMAILBOX { + _marker: PhantomData, + }, + CM_PCM: CM_PCM { + _marker: PhantomData, + }, + CM_PWM: CM_PWM { + _marker: PhantomData, + }, + GPIO: GPIO { + _marker: PhantomData, + }, + SYSTMR: SYSTMR { + _marker: PhantomData, + }, + UART0: UART0 { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + BSC0: BSC0 { + _marker: PhantomData, + }, + PWM0: PWM0 { + _marker: PhantomData, + }, + BSC1: BSC1 { + _marker: PhantomData, + }, + BSC2: BSC2 { + _marker: PhantomData, + }, + AUX: AUX { + _marker: PhantomData, + }, + UART1: UART1 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + LIC: LIC { + _marker: PhantomData, + }, + USB_OTG_GLOBAL: USB_OTG_GLOBAL { + _marker: PhantomData, + }, + USB_OTG_HOST: USB_OTG_HOST { + _marker: PhantomData, + }, + USB_OTG_DEVICE: USB_OTG_DEVICE { + _marker: PhantomData, + }, + USB_OTG_PWRCLK: USB_OTG_PWRCLK { + _marker: PhantomData, + }, + EMMC: EMMC { + _marker: PhantomData, + }, + } + } +} diff --git a/crates/bcm2837-lpa/src/lic.rs b/crates/bcm2837-lpa/src/lic.rs new file mode 100644 index 0000000..bc15cd4 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic.rs @@ -0,0 +1,65 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0200], + #[doc = "0x200 - Basic pending info"] + pub basic_pending: BASIC_PENDING, + #[doc = "0x204 - Pending state for interrupts 1 - 31"] + pub pending_1: PENDING_1, + #[doc = "0x208 - Pending state for interrupts 32 - 63"] + pub pending_2: PENDING_2, + #[doc = "0x20c - FIQ control"] + pub fiq_control: FIQ_CONTROL, + #[doc = "0x210 - Enable interrupts 1 - 31"] + pub enable_1: ENABLE_1, + #[doc = "0x214 - Enable interrupts 32 - 63"] + pub enable_2: ENABLE_2, + #[doc = "0x218 - Enable basic interrupts"] + pub enable_basic: ENABLE_BASIC, + #[doc = "0x21c - Disable interrupts 1 - 31"] + pub disable_1: DISABLE_1, + #[doc = "0x220 - Disable interrupts 32 - 63"] + pub disable_2: DISABLE_2, + #[doc = "0x224 - Disable basic interrupts"] + pub disable_basic: DISABLE_BASIC, +} +#[doc = "BASIC_PENDING (r) register accessor: an alias for `Reg`"] +pub type BASIC_PENDING = crate::Reg; +#[doc = "Basic pending info"] +pub mod basic_pending; +#[doc = "PENDING_1 (r) register accessor: an alias for `Reg`"] +pub type PENDING_1 = crate::Reg; +#[doc = "Pending state for interrupts 1 - 31"] +pub mod pending_1; +#[doc = "PENDING_2 (r) register accessor: an alias for `Reg`"] +pub type PENDING_2 = crate::Reg; +#[doc = "Pending state for interrupts 32 - 63"] +pub mod pending_2; +#[doc = "FIQ_CONTROL (rw) register accessor: an alias for `Reg`"] +pub type FIQ_CONTROL = crate::Reg; +#[doc = "FIQ control"] +pub mod fiq_control; +#[doc = "ENABLE_1 (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_1 = crate::Reg; +#[doc = "Enable interrupts 1 - 31"] +pub mod enable_1; +#[doc = "ENABLE_2 (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_2 = crate::Reg; +#[doc = "Enable interrupts 32 - 63"] +pub mod enable_2; +#[doc = "ENABLE_BASIC (rw) register accessor: an alias for `Reg`"] +pub type ENABLE_BASIC = crate::Reg; +#[doc = "Enable basic interrupts"] +pub mod enable_basic; +#[doc = "DISABLE_1 (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_1 = crate::Reg; +#[doc = "Disable interrupts 1 - 31"] +pub mod disable_1; +#[doc = "DISABLE_2 (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_2 = crate::Reg; +#[doc = "Disable interrupts 32 - 63"] +pub mod disable_2; +#[doc = "DISABLE_BASIC (rw) register accessor: an alias for `Reg`"] +pub type DISABLE_BASIC = crate::Reg; +#[doc = "Disable basic interrupts"] +pub mod disable_basic; diff --git a/crates/bcm2837-lpa/src/lic/basic_pending.rs b/crates/bcm2837-lpa/src/lic/basic_pending.rs new file mode 100644 index 0000000..c7dcea2 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/basic_pending.rs @@ -0,0 +1,177 @@ +#[doc = "Register `BASIC_PENDING` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `PENDING_1` reader - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] +pub type PENDING_1_R = crate::BitReader; +#[doc = "Field `PENDING_2` reader - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] +pub type PENDING_2_R = crate::BitReader; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] + #[inline(always)] + pub fn pending_1(&self) -> PENDING_1_R { + PENDING_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] + #[inline(always)] + pub fn pending_2(&self) -> PENDING_2_R { + PENDING_2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[doc = "Basic pending info\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [basic_pending](index.html) module"] +pub struct BASIC_PENDING_SPEC; +impl crate::RegisterSpec for BASIC_PENDING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [basic_pending::R](R) reader structure"] +impl crate::Readable for BASIC_PENDING_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASIC_PENDING to value 0"] +impl crate::Resettable for BASIC_PENDING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/disable_1.rs b/crates/bcm2837-lpa/src/lic/disable_1.rs new file mode 100644 index 0000000..5c8027d --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/disable_1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `DISABLE_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_1](index.html) module"] +pub struct DISABLE_1_SPEC; +impl crate::RegisterSpec for DISABLE_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_1::R](R) reader structure"] +impl crate::Readable for DISABLE_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_1::W](W) writer structure"] +impl crate::Writable for DISABLE_1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets DISABLE_1 to value 0"] +impl crate::Resettable for DISABLE_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/disable_2.rs b/crates/bcm2837-lpa/src/lic/disable_2.rs new file mode 100644 index 0000000..9334cf8 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/disable_2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `DISABLE_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_2](index.html) module"] +pub struct DISABLE_2_SPEC; +impl crate::RegisterSpec for DISABLE_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_2::R](R) reader structure"] +impl crate::Readable for DISABLE_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_2::W](W) writer structure"] +impl crate::Writable for DISABLE_2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets DISABLE_2 to value 0"] +impl crate::Resettable for DISABLE_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/disable_basic.rs b/crates/bcm2837-lpa/src/lic/disable_basic.rs new file mode 100644 index 0000000..df73f14 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/disable_basic.rs @@ -0,0 +1,187 @@ +#[doc = "Register `DISABLE_BASIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DISABLE_BASIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = + crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Disable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_basic](index.html) module"] +pub struct DISABLE_BASIC_SPEC; +impl crate::RegisterSpec for DISABLE_BASIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [disable_basic::R](R) reader structure"] +impl crate::Readable for DISABLE_BASIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [disable_basic::W](W) writer structure"] +impl crate::Writable for DISABLE_BASIC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; +} +#[doc = "`reset()` method sets DISABLE_BASIC to value 0"] +impl crate::Resettable for DISABLE_BASIC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/enable_1.rs b/crates/bcm2837-lpa/src/lic/enable_1.rs new file mode 100644 index 0000000..e9aa7ce --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/enable_1.rs @@ -0,0 +1,545 @@ +#[doc = "Register `ENABLE_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_0` writer - Timer 0"] +pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_1` writer - Timer 1"] +pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_2` writer - Timer 2"] +pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `TIMER_3` writer - Timer 3"] +pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_0` writer - H264 0"] +pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_1` writer - H264 1"] +pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `H264_2` writer - H264 2"] +pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `JPEG` writer - JPEG"] +pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `ISP` writer - ISP"] +pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - USB"] +pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `V3D` writer - V3D"] +pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` writer - Transposer"] +pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_0` writer - DMA 0"] +pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_1` writer - DMA 1"] +pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_2` writer - DMA 2"] +pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_3` writer - DMA 3"] +pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_4` writer - DMA 4"] +pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_5` writer - DMA 5"] +pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_6` writer - DMA 6"] +pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] +pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] +pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_11` writer - DMA 11"] +pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_12` writer - DMA 12"] +pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_13` writer - DMA 13"] +pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `DMA_14` writer - DMA 14"] +pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] +pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `ARM` writer - ARM"] +pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +#[doc = "Field `DMA_15` writer - DMA 15"] +pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + #[must_use] + pub fn timer_0(&mut self) -> TIMER_0_W<0> { + TIMER_0_W::new(self) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + #[must_use] + pub fn timer_1(&mut self) -> TIMER_1_W<1> { + TIMER_1_W::new(self) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + #[must_use] + pub fn timer_2(&mut self) -> TIMER_2_W<2> { + TIMER_2_W::new(self) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + #[must_use] + pub fn timer_3(&mut self) -> TIMER_3_W<3> { + TIMER_3_W::new(self) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + #[must_use] + pub fn h264_0(&mut self) -> H264_0_W<4> { + H264_0_W::new(self) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + #[must_use] + pub fn h264_1(&mut self) -> H264_1_W<5> { + H264_1_W::new(self) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + #[must_use] + pub fn h264_2(&mut self) -> H264_2_W<6> { + H264_2_W::new(self) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + #[must_use] + pub fn jpeg(&mut self) -> JPEG_W<7> { + JPEG_W::new(self) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + #[must_use] + pub fn isp(&mut self) -> ISP_W<8> { + ISP_W::new(self) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W<9> { + USB_W::new(self) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + #[must_use] + pub fn v3d(&mut self) -> V3D_W<10> { + V3D_W::new(self) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + #[must_use] + pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + TRANSPOSER_W::new(self) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + MULTICORE_SYNC_0_W::new(self) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + MULTICORE_SYNC_1_W::new(self) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + MULTICORE_SYNC_2_W::new(self) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + #[must_use] + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + MULTICORE_SYNC_3_W::new(self) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + #[must_use] + pub fn dma_0(&mut self) -> DMA_0_W<16> { + DMA_0_W::new(self) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + #[must_use] + pub fn dma_1(&mut self) -> DMA_1_W<17> { + DMA_1_W::new(self) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + #[must_use] + pub fn dma_2(&mut self) -> DMA_2_W<18> { + DMA_2_W::new(self) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + #[must_use] + pub fn dma_3(&mut self) -> DMA_3_W<19> { + DMA_3_W::new(self) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + #[must_use] + pub fn dma_4(&mut self) -> DMA_4_W<20> { + DMA_4_W::new(self) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + #[must_use] + pub fn dma_5(&mut self) -> DMA_5_W<21> { + DMA_5_W::new(self) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + #[must_use] + pub fn dma_6(&mut self) -> DMA_6_W<22> { + DMA_6_W::new(self) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + #[must_use] + pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + DMA_7_8_W::new(self) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + #[must_use] + pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + DMA_9_10_W::new(self) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + #[must_use] + pub fn dma_11(&mut self) -> DMA_11_W<25> { + DMA_11_W::new(self) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + #[must_use] + pub fn dma_12(&mut self) -> DMA_12_W<26> { + DMA_12_W::new(self) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + #[must_use] + pub fn dma_13(&mut self) -> DMA_13_W<27> { + DMA_13_W::new(self) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + #[must_use] + pub fn dma_14(&mut self) -> DMA_14_W<28> { + DMA_14_W::new(self) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + #[must_use] + pub fn aux(&mut self) -> AUX_W<29> { + AUX_W::new(self) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W<30> { + ARM_W::new(self) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + #[must_use] + pub fn dma_15(&mut self) -> DMA_15_W<31> { + DMA_15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_1](index.html) module"] +pub struct ENABLE_1_SPEC; +impl crate::RegisterSpec for ENABLE_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_1::R](R) reader structure"] +impl crate::Readable for ENABLE_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_1::W](W) writer structure"] +impl crate::Writable for ENABLE_1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets ENABLE_1 to value 0"] +impl crate::Resettable for ENABLE_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/enable_2.rs b/crates/bcm2837-lpa/src/lic/enable_2.rs new file mode 100644 index 0000000..45e156d --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/enable_2.rs @@ -0,0 +1,545 @@ +#[doc = "Register `ENABLE_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HDMI_CEC` writer - HDMI CEC"] +pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `HVS` writer - HVS"] +pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `RPIVID` writer - RPIVID"] +pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `SDC` writer - SDC"] +pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `DSI_0` writer - DSI 0"] +pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] +pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_0` writer - Camera 0"] +pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `CAMERA_1` writer - Camera 1"] +pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_0` writer - HDMI 0"] +pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `HDMI_1` writer - HDMI 1"] +pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] +pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `DSI_1` writer - DSI 1"] +pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] +pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `CPR` writer - CPR"] +pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `SMI` writer - SMI"] +pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_0` writer - GPIO 0"] +pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_1` writer - GPIO 1"] +pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_2` writer - GPIO 2"] +pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `GPIO_3` writer - GPIO 3"] +pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `I2C` writer - OR of all I2C"] +pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `SPI` writer - OR of all SPI"] +pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `PCM_I2S` writer - PCM/I2S"] +pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `SDHOST` writer - SDHOST"] +pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `UART` writer - OR of all PL011 UARTs"] +pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `VEC` writer - VEC"] +pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `CPG` writer - CPG"] +pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `RNG` writer - RNG"] +pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] +pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + #[must_use] + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + HDMI_CEC_W::new(self) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + #[must_use] + pub fn hvs(&mut self) -> HVS_W<1> { + HVS_W::new(self) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + #[must_use] + pub fn rpivid(&mut self) -> RPIVID_W<2> { + RPIVID_W::new(self) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + #[must_use] + pub fn sdc(&mut self) -> SDC_W<3> { + SDC_W::new(self) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + #[must_use] + pub fn dsi_0(&mut self) -> DSI_0_W<4> { + DSI_0_W::new(self) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + PIXEL_VALVE_2_W::new(self) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + #[must_use] + pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + CAMERA_0_W::new(self) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + #[must_use] + pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + CAMERA_1_W::new(self) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + #[must_use] + pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + HDMI_0_W::new(self) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + #[must_use] + pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + HDMI_1_W::new(self) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + PIXEL_VALVE_3_W::new(self) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + #[must_use] + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + SPI_BSC_SLAVE_W::new(self) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + #[must_use] + pub fn dsi_1(&mut self) -> DSI_1_W<12> { + DSI_1_W::new(self) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + PIXEL_VALVE_0_W::new(self) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + #[must_use] + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + PIXEL_VALVE_1_2_W::new(self) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + #[must_use] + pub fn cpr(&mut self) -> CPR_W<15> { + CPR_W::new(self) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + #[must_use] + pub fn smi(&mut self) -> SMI_W<16> { + SMI_W::new(self) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + #[must_use] + pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + GPIO_0_W::new(self) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + #[must_use] + pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + GPIO_1_W::new(self) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + #[must_use] + pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + GPIO_2_W::new(self) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + #[must_use] + pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + GPIO_3_W::new(self) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2C_W<21> { + I2C_W::new(self) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + #[must_use] + pub fn spi(&mut self) -> SPI_W<22> { + SPI_W::new(self) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + #[must_use] + pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + PCM_I2S_W::new(self) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + #[must_use] + pub fn sdhost(&mut self) -> SDHOST_W<24> { + SDHOST_W::new(self) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UART_W<25> { + UART_W::new(self) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + #[must_use] + pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + ETH_PCIE_W::new(self) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + #[must_use] + pub fn vec(&mut self) -> VEC_W<27> { + VEC_W::new(self) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + #[must_use] + pub fn cpg(&mut self) -> CPG_W<28> { + CPG_W::new(self) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + #[must_use] + pub fn rng(&mut self) -> RNG_W<29> { + RNG_W::new(self) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + #[must_use] + pub fn emmc(&mut self) -> EMMC_W<30> { + EMMC_W::new(self) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + #[must_use] + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + ETH_PCIE_SECURE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_2](index.html) module"] +pub struct ENABLE_2_SPEC; +impl crate::RegisterSpec for ENABLE_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_2::R](R) reader structure"] +impl crate::Readable for ENABLE_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_2::W](W) writer structure"] +impl crate::Writable for ENABLE_2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; +} +#[doc = "`reset()` method sets ENABLE_2 to value 0"] +impl crate::Resettable for ENABLE_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/enable_basic.rs b/crates/bcm2837-lpa/src/lic/enable_basic.rs new file mode 100644 index 0000000..b401deb --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/enable_basic.rs @@ -0,0 +1,186 @@ +#[doc = "Register `ENABLE_BASIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE_BASIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMER` reader - ARMC Timer"] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - ARMC Timer"] +pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `MAILBOX` reader - Mailbox"] +pub type MAILBOX_R = crate::BitReader; +#[doc = "Field `MAILBOX` writer - Mailbox"] +pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL0` reader - Doorbell 0"] +pub type DOORBELL0_R = crate::BitReader; +#[doc = "Field `DOORBELL0` writer - Doorbell 0"] +pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `DOORBELL1` reader - Doorbell 1"] +pub type DOORBELL1_R = crate::BitReader; +#[doc = "Field `DOORBELL1` writer - Doorbell 1"] +pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] +pub type VPU0_HALTED_R = crate::BitReader; +#[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] +pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] +pub type VPU1_HALTED_R = crate::BitReader; +#[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] +pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] +pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = + crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +#[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] +pub type ARM_AXI_ERROR_R = crate::BitReader; +#[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] +pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + pub fn mailbox(&self) -> MAILBOX_R { + MAILBOX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + pub fn doorbell0(&self) -> DOORBELL0_R { + DOORBELL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + pub fn doorbell1(&self) -> DOORBELL1_R { + DOORBELL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(&self) -> VPU0_HALTED_R { + VPU0_HALTED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(&self) -> VPU1_HALTED_R { + VPU1_HALTED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + pub fn arm_address_error(&self) -> ARM_ADDRESS_ERROR_R { + ARM_ADDRESS_ERROR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(&self) -> ARM_AXI_ERROR_R { + ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ARMC Timer"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W<0> { + TIMER_W::new(self) + } + #[doc = "Bit 1 - Mailbox"] + #[inline(always)] + #[must_use] + pub fn mailbox(&mut self) -> MAILBOX_W<1> { + MAILBOX_W::new(self) + } + #[doc = "Bit 2 - Doorbell 0"] + #[inline(always)] + #[must_use] + pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + DOORBELL0_W::new(self) + } + #[doc = "Bit 3 - Doorbell 1"] + #[inline(always)] + #[must_use] + pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + DOORBELL1_W::new(self) + } + #[doc = "Bit 4 - VPU0 halted"] + #[inline(always)] + #[must_use] + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + VPU0_HALTED_W::new(self) + } + #[doc = "Bit 5 - VPU1 halted"] + #[inline(always)] + #[must_use] + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + VPU1_HALTED_W::new(self) + } + #[doc = "Bit 6 - ARM address error"] + #[inline(always)] + #[must_use] + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + ARM_ADDRESS_ERROR_W::new(self) + } + #[doc = "Bit 7 - ARM AXI error"] + #[inline(always)] + #[must_use] + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + ARM_AXI_ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_basic](index.html) module"] +pub struct ENABLE_BASIC_SPEC; +impl crate::RegisterSpec for ENABLE_BASIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable_basic::R](R) reader structure"] +impl crate::Readable for ENABLE_BASIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable_basic::W](W) writer structure"] +impl crate::Writable for ENABLE_BASIC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; +} +#[doc = "`reset()` method sets ENABLE_BASIC to value 0"] +impl crate::Resettable for ENABLE_BASIC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/fiq_control.rs b/crates/bcm2837-lpa/src/lic/fiq_control.rs new file mode 100644 index 0000000..d1b5d51 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/fiq_control.rs @@ -0,0 +1,1054 @@ +#[doc = "Register `FIQ_CONTROL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIQ_CONTROL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SOURCE` reader - FIQ Source"] +pub type SOURCE_R = crate::FieldReader; +#[doc = "FIQ Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SOURCE_A { + #[doc = "0: Timer 0"] + TIMER_0 = 0, + #[doc = "1: Timer 1"] + TIMER_1 = 1, + #[doc = "2: Timer 2"] + TIMER_2 = 2, + #[doc = "3: Timer 3"] + TIMER_3 = 3, + #[doc = "4: H264 0"] + H264_0 = 4, + #[doc = "5: H264 1"] + H264_1 = 5, + #[doc = "6: H264 2"] + H264_2 = 6, + #[doc = "7: JPEG"] + JPEG = 7, + #[doc = "8: ISP"] + ISP = 8, + #[doc = "9: USB"] + USB = 9, + #[doc = "10: V3D"] + V3D = 10, + #[doc = "11: Transposer"] + TRANSPOSER = 11, + #[doc = "12: Multicore Sync 0"] + MULTICORE_SYNC_0 = 12, + #[doc = "13: Multicore Sync 1"] + MULTICORE_SYNC_1 = 13, + #[doc = "14: Multicore Sync 2"] + MULTICORE_SYNC_2 = 14, + #[doc = "15: Multicore Sync 3"] + MULTICORE_SYNC_3 = 15, + #[doc = "16: DMA 0"] + DMA_0 = 16, + #[doc = "17: DMA 1"] + DMA_1 = 17, + #[doc = "18: DMA 2"] + DMA_2 = 18, + #[doc = "19: DMA 3"] + DMA_3 = 19, + #[doc = "20: DMA 4"] + DMA_4 = 20, + #[doc = "21: DMA 5"] + DMA_5 = 21, + #[doc = "22: DMA 6"] + DMA_6 = 22, + #[doc = "23: OR of DMA 7 and 8"] + DMA_7_8 = 23, + #[doc = "24: OR of DMA 9 and 10"] + DMA_9_10 = 24, + #[doc = "25: DMA 11"] + DMA_11 = 25, + #[doc = "26: DMA 12"] + DMA_12 = 26, + #[doc = "27: DMA 13"] + DMA_13 = 27, + #[doc = "28: DMA 14"] + DMA_14 = 28, + #[doc = "29: OR of UART1, SPI1 and SPI2"] + AUX = 29, + #[doc = "30: ARM"] + ARM = 30, + #[doc = "31: DMA 15"] + DMA_15 = 31, + #[doc = "32: HDMI CEC"] + HDMI_CEC = 32, + #[doc = "33: HVS"] + HVS = 33, + #[doc = "34: RPIVID"] + RPIVID = 34, + #[doc = "35: SDC"] + SDC = 35, + #[doc = "36: DSI 0"] + DSI_0 = 36, + #[doc = "37: Pixel Valve 2"] + PIXEL_VALVE_2 = 37, + #[doc = "38: Camera 0"] + CAMERA_0 = 38, + #[doc = "39: Camera 1"] + CAMERA_1 = 39, + #[doc = "40: HDMI 0"] + HDMI_0 = 40, + #[doc = "41: HDMI 1"] + HDMI_1 = 41, + #[doc = "42: Pixel Valve 3"] + PIXEL_VALVE_3 = 42, + #[doc = "43: SPI/BSC Slave"] + SPI_BSC_SLAVE = 43, + #[doc = "44: DSI 1"] + DSI_1 = 44, + #[doc = "45: Pixel Valve 0"] + PIXEL_VALVE_0 = 45, + #[doc = "46: OR of Pixel Valve 1 and 2"] + PIXEL_VALVE_1_2 = 46, + #[doc = "47: CPR"] + CPR = 47, + #[doc = "48: SMI"] + SMI = 48, + #[doc = "49: GPIO 0"] + GPIO_0 = 49, + #[doc = "50: GPIO 1"] + GPIO_1 = 50, + #[doc = "51: GPIO 2"] + GPIO_2 = 51, + #[doc = "52: GPIO 3"] + GPIO_3 = 52, + #[doc = "53: OR of all I2C"] + I2C = 53, + #[doc = "54: OR of all SPI"] + SPI = 54, + #[doc = "55: PCM/I2S"] + PCM_I2S = 55, + #[doc = "56: SDHOST"] + SDHOST = 56, + #[doc = "57: OR of all PL011 UARTs"] + UART = 57, + #[doc = "58: OR of all ETH_PCIe L2"] + ETH_PCIE = 58, + #[doc = "59: VEC"] + VEC = 59, + #[doc = "60: CPG"] + CPG = 60, + #[doc = "61: RNG"] + RNG = 61, + #[doc = "62: OR of EMMC and EMMC2"] + EMMC = 62, + #[doc = "63: ETH_PCIe secure"] + ETH_PCIE_SECURE = 63, + #[doc = "64: ARMC Timer"] + TIMER = 64, + #[doc = "65: Mailbox"] + MAILBOX = 65, + #[doc = "66: Doorbell 0"] + DOORBELL0 = 66, + #[doc = "67: Doorbell 1"] + DOORBELL1 = 67, + #[doc = "68: VPU0 halted"] + VPU0_HALTED = 68, + #[doc = "69: VPU1 halted"] + VPU1_HALTED = 69, + #[doc = "70: ARM address error"] + ARM_ADDRESS_ERROR = 70, + #[doc = "71: ARM AXI error"] + ARM_AXI_ERROR = 71, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SOURCE_A) -> Self { + variant as _ + } +} +impl SOURCE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SOURCE_A::TIMER_0), + 1 => Some(SOURCE_A::TIMER_1), + 2 => Some(SOURCE_A::TIMER_2), + 3 => Some(SOURCE_A::TIMER_3), + 4 => Some(SOURCE_A::H264_0), + 5 => Some(SOURCE_A::H264_1), + 6 => Some(SOURCE_A::H264_2), + 7 => Some(SOURCE_A::JPEG), + 8 => Some(SOURCE_A::ISP), + 9 => Some(SOURCE_A::USB), + 10 => Some(SOURCE_A::V3D), + 11 => Some(SOURCE_A::TRANSPOSER), + 12 => Some(SOURCE_A::MULTICORE_SYNC_0), + 13 => Some(SOURCE_A::MULTICORE_SYNC_1), + 14 => Some(SOURCE_A::MULTICORE_SYNC_2), + 15 => Some(SOURCE_A::MULTICORE_SYNC_3), + 16 => Some(SOURCE_A::DMA_0), + 17 => Some(SOURCE_A::DMA_1), + 18 => Some(SOURCE_A::DMA_2), + 19 => Some(SOURCE_A::DMA_3), + 20 => Some(SOURCE_A::DMA_4), + 21 => Some(SOURCE_A::DMA_5), + 22 => Some(SOURCE_A::DMA_6), + 23 => Some(SOURCE_A::DMA_7_8), + 24 => Some(SOURCE_A::DMA_9_10), + 25 => Some(SOURCE_A::DMA_11), + 26 => Some(SOURCE_A::DMA_12), + 27 => Some(SOURCE_A::DMA_13), + 28 => Some(SOURCE_A::DMA_14), + 29 => Some(SOURCE_A::AUX), + 30 => Some(SOURCE_A::ARM), + 31 => Some(SOURCE_A::DMA_15), + 32 => Some(SOURCE_A::HDMI_CEC), + 33 => Some(SOURCE_A::HVS), + 34 => Some(SOURCE_A::RPIVID), + 35 => Some(SOURCE_A::SDC), + 36 => Some(SOURCE_A::DSI_0), + 37 => Some(SOURCE_A::PIXEL_VALVE_2), + 38 => Some(SOURCE_A::CAMERA_0), + 39 => Some(SOURCE_A::CAMERA_1), + 40 => Some(SOURCE_A::HDMI_0), + 41 => Some(SOURCE_A::HDMI_1), + 42 => Some(SOURCE_A::PIXEL_VALVE_3), + 43 => Some(SOURCE_A::SPI_BSC_SLAVE), + 44 => Some(SOURCE_A::DSI_1), + 45 => Some(SOURCE_A::PIXEL_VALVE_0), + 46 => Some(SOURCE_A::PIXEL_VALVE_1_2), + 47 => Some(SOURCE_A::CPR), + 48 => Some(SOURCE_A::SMI), + 49 => Some(SOURCE_A::GPIO_0), + 50 => Some(SOURCE_A::GPIO_1), + 51 => Some(SOURCE_A::GPIO_2), + 52 => Some(SOURCE_A::GPIO_3), + 53 => Some(SOURCE_A::I2C), + 54 => Some(SOURCE_A::SPI), + 55 => Some(SOURCE_A::PCM_I2S), + 56 => Some(SOURCE_A::SDHOST), + 57 => Some(SOURCE_A::UART), + 58 => Some(SOURCE_A::ETH_PCIE), + 59 => Some(SOURCE_A::VEC), + 60 => Some(SOURCE_A::CPG), + 61 => Some(SOURCE_A::RNG), + 62 => Some(SOURCE_A::EMMC), + 63 => Some(SOURCE_A::ETH_PCIE_SECURE), + 64 => Some(SOURCE_A::TIMER), + 65 => Some(SOURCE_A::MAILBOX), + 66 => Some(SOURCE_A::DOORBELL0), + 67 => Some(SOURCE_A::DOORBELL1), + 68 => Some(SOURCE_A::VPU0_HALTED), + 69 => Some(SOURCE_A::VPU1_HALTED), + 70 => Some(SOURCE_A::ARM_ADDRESS_ERROR), + 71 => Some(SOURCE_A::ARM_AXI_ERROR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TIMER_0`"] + #[inline(always)] + pub fn is_timer_0(&self) -> bool { + *self == SOURCE_A::TIMER_0 + } + #[doc = "Checks if the value of the field is `TIMER_1`"] + #[inline(always)] + pub fn is_timer_1(&self) -> bool { + *self == SOURCE_A::TIMER_1 + } + #[doc = "Checks if the value of the field is `TIMER_2`"] + #[inline(always)] + pub fn is_timer_2(&self) -> bool { + *self == SOURCE_A::TIMER_2 + } + #[doc = "Checks if the value of the field is `TIMER_3`"] + #[inline(always)] + pub fn is_timer_3(&self) -> bool { + *self == SOURCE_A::TIMER_3 + } + #[doc = "Checks if the value of the field is `H264_0`"] + #[inline(always)] + pub fn is_h264_0(&self) -> bool { + *self == SOURCE_A::H264_0 + } + #[doc = "Checks if the value of the field is `H264_1`"] + #[inline(always)] + pub fn is_h264_1(&self) -> bool { + *self == SOURCE_A::H264_1 + } + #[doc = "Checks if the value of the field is `H264_2`"] + #[inline(always)] + pub fn is_h264_2(&self) -> bool { + *self == SOURCE_A::H264_2 + } + #[doc = "Checks if the value of the field is `JPEG`"] + #[inline(always)] + pub fn is_jpeg(&self) -> bool { + *self == SOURCE_A::JPEG + } + #[doc = "Checks if the value of the field is `ISP`"] + #[inline(always)] + pub fn is_isp(&self) -> bool { + *self == SOURCE_A::ISP + } + #[doc = "Checks if the value of the field is `USB`"] + #[inline(always)] + pub fn is_usb(&self) -> bool { + *self == SOURCE_A::USB + } + #[doc = "Checks if the value of the field is `V3D`"] + #[inline(always)] + pub fn is_v3d(&self) -> bool { + *self == SOURCE_A::V3D + } + #[doc = "Checks if the value of the field is `TRANSPOSER`"] + #[inline(always)] + pub fn is_transposer(&self) -> bool { + *self == SOURCE_A::TRANSPOSER + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_0`"] + #[inline(always)] + pub fn is_multicore_sync_0(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_0 + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_1`"] + #[inline(always)] + pub fn is_multicore_sync_1(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_1 + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_2`"] + #[inline(always)] + pub fn is_multicore_sync_2(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_2 + } + #[doc = "Checks if the value of the field is `MULTICORE_SYNC_3`"] + #[inline(always)] + pub fn is_multicore_sync_3(&self) -> bool { + *self == SOURCE_A::MULTICORE_SYNC_3 + } + #[doc = "Checks if the value of the field is `DMA_0`"] + #[inline(always)] + pub fn is_dma_0(&self) -> bool { + *self == SOURCE_A::DMA_0 + } + #[doc = "Checks if the value of the field is `DMA_1`"] + #[inline(always)] + pub fn is_dma_1(&self) -> bool { + *self == SOURCE_A::DMA_1 + } + #[doc = "Checks if the value of the field is `DMA_2`"] + #[inline(always)] + pub fn is_dma_2(&self) -> bool { + *self == SOURCE_A::DMA_2 + } + #[doc = "Checks if the value of the field is `DMA_3`"] + #[inline(always)] + pub fn is_dma_3(&self) -> bool { + *self == SOURCE_A::DMA_3 + } + #[doc = "Checks if the value of the field is `DMA_4`"] + #[inline(always)] + pub fn is_dma_4(&self) -> bool { + *self == SOURCE_A::DMA_4 + } + #[doc = "Checks if the value of the field is `DMA_5`"] + #[inline(always)] + pub fn is_dma_5(&self) -> bool { + *self == SOURCE_A::DMA_5 + } + #[doc = "Checks if the value of the field is `DMA_6`"] + #[inline(always)] + pub fn is_dma_6(&self) -> bool { + *self == SOURCE_A::DMA_6 + } + #[doc = "Checks if the value of the field is `DMA_7_8`"] + #[inline(always)] + pub fn is_dma_7_8(&self) -> bool { + *self == SOURCE_A::DMA_7_8 + } + #[doc = "Checks if the value of the field is `DMA_9_10`"] + #[inline(always)] + pub fn is_dma_9_10(&self) -> bool { + *self == SOURCE_A::DMA_9_10 + } + #[doc = "Checks if the value of the field is `DMA_11`"] + #[inline(always)] + pub fn is_dma_11(&self) -> bool { + *self == SOURCE_A::DMA_11 + } + #[doc = "Checks if the value of the field is `DMA_12`"] + #[inline(always)] + pub fn is_dma_12(&self) -> bool { + *self == SOURCE_A::DMA_12 + } + #[doc = "Checks if the value of the field is `DMA_13`"] + #[inline(always)] + pub fn is_dma_13(&self) -> bool { + *self == SOURCE_A::DMA_13 + } + #[doc = "Checks if the value of the field is `DMA_14`"] + #[inline(always)] + pub fn is_dma_14(&self) -> bool { + *self == SOURCE_A::DMA_14 + } + #[doc = "Checks if the value of the field is `AUX`"] + #[inline(always)] + pub fn is_aux(&self) -> bool { + *self == SOURCE_A::AUX + } + #[doc = "Checks if the value of the field is `ARM`"] + #[inline(always)] + pub fn is_arm(&self) -> bool { + *self == SOURCE_A::ARM + } + #[doc = "Checks if the value of the field is `DMA_15`"] + #[inline(always)] + pub fn is_dma_15(&self) -> bool { + *self == SOURCE_A::DMA_15 + } + #[doc = "Checks if the value of the field is `HDMI_CEC`"] + #[inline(always)] + pub fn is_hdmi_cec(&self) -> bool { + *self == SOURCE_A::HDMI_CEC + } + #[doc = "Checks if the value of the field is `HVS`"] + #[inline(always)] + pub fn is_hvs(&self) -> bool { + *self == SOURCE_A::HVS + } + #[doc = "Checks if the value of the field is `RPIVID`"] + #[inline(always)] + pub fn is_rpivid(&self) -> bool { + *self == SOURCE_A::RPIVID + } + #[doc = "Checks if the value of the field is `SDC`"] + #[inline(always)] + pub fn is_sdc(&self) -> bool { + *self == SOURCE_A::SDC + } + #[doc = "Checks if the value of the field is `DSI_0`"] + #[inline(always)] + pub fn is_dsi_0(&self) -> bool { + *self == SOURCE_A::DSI_0 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_2`"] + #[inline(always)] + pub fn is_pixel_valve_2(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_2 + } + #[doc = "Checks if the value of the field is `CAMERA_0`"] + #[inline(always)] + pub fn is_camera_0(&self) -> bool { + *self == SOURCE_A::CAMERA_0 + } + #[doc = "Checks if the value of the field is `CAMERA_1`"] + #[inline(always)] + pub fn is_camera_1(&self) -> bool { + *self == SOURCE_A::CAMERA_1 + } + #[doc = "Checks if the value of the field is `HDMI_0`"] + #[inline(always)] + pub fn is_hdmi_0(&self) -> bool { + *self == SOURCE_A::HDMI_0 + } + #[doc = "Checks if the value of the field is `HDMI_1`"] + #[inline(always)] + pub fn is_hdmi_1(&self) -> bool { + *self == SOURCE_A::HDMI_1 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_3`"] + #[inline(always)] + pub fn is_pixel_valve_3(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_3 + } + #[doc = "Checks if the value of the field is `SPI_BSC_SLAVE`"] + #[inline(always)] + pub fn is_spi_bsc_slave(&self) -> bool { + *self == SOURCE_A::SPI_BSC_SLAVE + } + #[doc = "Checks if the value of the field is `DSI_1`"] + #[inline(always)] + pub fn is_dsi_1(&self) -> bool { + *self == SOURCE_A::DSI_1 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_0`"] + #[inline(always)] + pub fn is_pixel_valve_0(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_0 + } + #[doc = "Checks if the value of the field is `PIXEL_VALVE_1_2`"] + #[inline(always)] + pub fn is_pixel_valve_1_2(&self) -> bool { + *self == SOURCE_A::PIXEL_VALVE_1_2 + } + #[doc = "Checks if the value of the field is `CPR`"] + #[inline(always)] + pub fn is_cpr(&self) -> bool { + *self == SOURCE_A::CPR + } + #[doc = "Checks if the value of the field is `SMI`"] + #[inline(always)] + pub fn is_smi(&self) -> bool { + *self == SOURCE_A::SMI + } + #[doc = "Checks if the value of the field is `GPIO_0`"] + #[inline(always)] + pub fn is_gpio_0(&self) -> bool { + *self == SOURCE_A::GPIO_0 + } + #[doc = "Checks if the value of the field is `GPIO_1`"] + #[inline(always)] + pub fn is_gpio_1(&self) -> bool { + *self == SOURCE_A::GPIO_1 + } + #[doc = "Checks if the value of the field is `GPIO_2`"] + #[inline(always)] + pub fn is_gpio_2(&self) -> bool { + *self == SOURCE_A::GPIO_2 + } + #[doc = "Checks if the value of the field is `GPIO_3`"] + #[inline(always)] + pub fn is_gpio_3(&self) -> bool { + *self == SOURCE_A::GPIO_3 + } + #[doc = "Checks if the value of the field is `I2C`"] + #[inline(always)] + pub fn is_i2c(&self) -> bool { + *self == SOURCE_A::I2C + } + #[doc = "Checks if the value of the field is `SPI`"] + #[inline(always)] + pub fn is_spi(&self) -> bool { + *self == SOURCE_A::SPI + } + #[doc = "Checks if the value of the field is `PCM_I2S`"] + #[inline(always)] + pub fn is_pcm_i2s(&self) -> bool { + *self == SOURCE_A::PCM_I2S + } + #[doc = "Checks if the value of the field is `SDHOST`"] + #[inline(always)] + pub fn is_sdhost(&self) -> bool { + *self == SOURCE_A::SDHOST + } + #[doc = "Checks if the value of the field is `UART`"] + #[inline(always)] + pub fn is_uart(&self) -> bool { + *self == SOURCE_A::UART + } + #[doc = "Checks if the value of the field is `ETH_PCIE`"] + #[inline(always)] + pub fn is_eth_pcie(&self) -> bool { + *self == SOURCE_A::ETH_PCIE + } + #[doc = "Checks if the value of the field is `VEC`"] + #[inline(always)] + pub fn is_vec(&self) -> bool { + *self == SOURCE_A::VEC + } + #[doc = "Checks if the value of the field is `CPG`"] + #[inline(always)] + pub fn is_cpg(&self) -> bool { + *self == SOURCE_A::CPG + } + #[doc = "Checks if the value of the field is `RNG`"] + #[inline(always)] + pub fn is_rng(&self) -> bool { + *self == SOURCE_A::RNG + } + #[doc = "Checks if the value of the field is `EMMC`"] + #[inline(always)] + pub fn is_emmc(&self) -> bool { + *self == SOURCE_A::EMMC + } + #[doc = "Checks if the value of the field is `ETH_PCIE_SECURE`"] + #[inline(always)] + pub fn is_eth_pcie_secure(&self) -> bool { + *self == SOURCE_A::ETH_PCIE_SECURE + } + #[doc = "Checks if the value of the field is `TIMER`"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == SOURCE_A::TIMER + } + #[doc = "Checks if the value of the field is `MAILBOX`"] + #[inline(always)] + pub fn is_mailbox(&self) -> bool { + *self == SOURCE_A::MAILBOX + } + #[doc = "Checks if the value of the field is `DOORBELL0`"] + #[inline(always)] + pub fn is_doorbell0(&self) -> bool { + *self == SOURCE_A::DOORBELL0 + } + #[doc = "Checks if the value of the field is `DOORBELL1`"] + #[inline(always)] + pub fn is_doorbell1(&self) -> bool { + *self == SOURCE_A::DOORBELL1 + } + #[doc = "Checks if the value of the field is `VPU0_HALTED`"] + #[inline(always)] + pub fn is_vpu0_halted(&self) -> bool { + *self == SOURCE_A::VPU0_HALTED + } + #[doc = "Checks if the value of the field is `VPU1_HALTED`"] + #[inline(always)] + pub fn is_vpu1_halted(&self) -> bool { + *self == SOURCE_A::VPU1_HALTED + } + #[doc = "Checks if the value of the field is `ARM_ADDRESS_ERROR`"] + #[inline(always)] + pub fn is_arm_address_error(&self) -> bool { + *self == SOURCE_A::ARM_ADDRESS_ERROR + } + #[doc = "Checks if the value of the field is `ARM_AXI_ERROR`"] + #[inline(always)] + pub fn is_arm_axi_error(&self) -> bool { + *self == SOURCE_A::ARM_AXI_ERROR + } +} +#[doc = "Field `SOURCE` writer - FIQ Source"] +pub type SOURCE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, FIQ_CONTROL_SPEC, u8, SOURCE_A, 7, O>; +impl<'a, const O: u8> SOURCE_W<'a, O> { + #[doc = "Timer 0"] + #[inline(always)] + pub fn timer_0(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_0) + } + #[doc = "Timer 1"] + #[inline(always)] + pub fn timer_1(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_1) + } + #[doc = "Timer 2"] + #[inline(always)] + pub fn timer_2(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_2) + } + #[doc = "Timer 3"] + #[inline(always)] + pub fn timer_3(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER_3) + } + #[doc = "H264 0"] + #[inline(always)] + pub fn h264_0(self) -> &'a mut W { + self.variant(SOURCE_A::H264_0) + } + #[doc = "H264 1"] + #[inline(always)] + pub fn h264_1(self) -> &'a mut W { + self.variant(SOURCE_A::H264_1) + } + #[doc = "H264 2"] + #[inline(always)] + pub fn h264_2(self) -> &'a mut W { + self.variant(SOURCE_A::H264_2) + } + #[doc = "JPEG"] + #[inline(always)] + pub fn jpeg(self) -> &'a mut W { + self.variant(SOURCE_A::JPEG) + } + #[doc = "ISP"] + #[inline(always)] + pub fn isp(self) -> &'a mut W { + self.variant(SOURCE_A::ISP) + } + #[doc = "USB"] + #[inline(always)] + pub fn usb(self) -> &'a mut W { + self.variant(SOURCE_A::USB) + } + #[doc = "V3D"] + #[inline(always)] + pub fn v3d(self) -> &'a mut W { + self.variant(SOURCE_A::V3D) + } + #[doc = "Transposer"] + #[inline(always)] + pub fn transposer(self) -> &'a mut W { + self.variant(SOURCE_A::TRANSPOSER) + } + #[doc = "Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_0) + } + #[doc = "Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_1) + } + #[doc = "Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_2) + } + #[doc = "Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(self) -> &'a mut W { + self.variant(SOURCE_A::MULTICORE_SYNC_3) + } + #[doc = "DMA 0"] + #[inline(always)] + pub fn dma_0(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_0) + } + #[doc = "DMA 1"] + #[inline(always)] + pub fn dma_1(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_1) + } + #[doc = "DMA 2"] + #[inline(always)] + pub fn dma_2(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_2) + } + #[doc = "DMA 3"] + #[inline(always)] + pub fn dma_3(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_3) + } + #[doc = "DMA 4"] + #[inline(always)] + pub fn dma_4(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_4) + } + #[doc = "DMA 5"] + #[inline(always)] + pub fn dma_5(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_5) + } + #[doc = "DMA 6"] + #[inline(always)] + pub fn dma_6(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_6) + } + #[doc = "OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_7_8) + } + #[doc = "OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_9_10) + } + #[doc = "DMA 11"] + #[inline(always)] + pub fn dma_11(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_11) + } + #[doc = "DMA 12"] + #[inline(always)] + pub fn dma_12(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_12) + } + #[doc = "DMA 13"] + #[inline(always)] + pub fn dma_13(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_13) + } + #[doc = "DMA 14"] + #[inline(always)] + pub fn dma_14(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_14) + } + #[doc = "OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(self) -> &'a mut W { + self.variant(SOURCE_A::AUX) + } + #[doc = "ARM"] + #[inline(always)] + pub fn arm(self) -> &'a mut W { + self.variant(SOURCE_A::ARM) + } + #[doc = "DMA 15"] + #[inline(always)] + pub fn dma_15(self) -> &'a mut W { + self.variant(SOURCE_A::DMA_15) + } + #[doc = "HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(self) -> &'a mut W { + self.variant(SOURCE_A::HDMI_CEC) + } + #[doc = "HVS"] + #[inline(always)] + pub fn hvs(self) -> &'a mut W { + self.variant(SOURCE_A::HVS) + } + #[doc = "RPIVID"] + #[inline(always)] + pub fn rpivid(self) -> &'a mut W { + self.variant(SOURCE_A::RPIVID) + } + #[doc = "SDC"] + #[inline(always)] + pub fn sdc(self) -> &'a mut W { + self.variant(SOURCE_A::SDC) + } + #[doc = "DSI 0"] + #[inline(always)] + pub fn dsi_0(self) -> &'a mut W { + self.variant(SOURCE_A::DSI_0) + } + #[doc = "Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_2) + } + #[doc = "Camera 0"] + #[inline(always)] + pub fn camera_0(self) -> &'a mut W { + self.variant(SOURCE_A::CAMERA_0) + } + #[doc = "Camera 1"] + #[inline(always)] + pub fn camera_1(self) -> &'a mut W { + self.variant(SOURCE_A::CAMERA_1) + } + #[doc = "HDMI 0"] + #[inline(always)] + pub fn hdmi_0(self) -> &'a mut W { + self.variant(SOURCE_A::HDMI_0) + } + #[doc = "HDMI 1"] + #[inline(always)] + pub fn hdmi_1(self) -> &'a mut W { + self.variant(SOURCE_A::HDMI_1) + } + #[doc = "Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_3) + } + #[doc = "SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(self) -> &'a mut W { + self.variant(SOURCE_A::SPI_BSC_SLAVE) + } + #[doc = "DSI 1"] + #[inline(always)] + pub fn dsi_1(self) -> &'a mut W { + self.variant(SOURCE_A::DSI_1) + } + #[doc = "Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_0) + } + #[doc = "OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(self) -> &'a mut W { + self.variant(SOURCE_A::PIXEL_VALVE_1_2) + } + #[doc = "CPR"] + #[inline(always)] + pub fn cpr(self) -> &'a mut W { + self.variant(SOURCE_A::CPR) + } + #[doc = "SMI"] + #[inline(always)] + pub fn smi(self) -> &'a mut W { + self.variant(SOURCE_A::SMI) + } + #[doc = "GPIO 0"] + #[inline(always)] + pub fn gpio_0(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_0) + } + #[doc = "GPIO 1"] + #[inline(always)] + pub fn gpio_1(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_1) + } + #[doc = "GPIO 2"] + #[inline(always)] + pub fn gpio_2(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_2) + } + #[doc = "GPIO 3"] + #[inline(always)] + pub fn gpio_3(self) -> &'a mut W { + self.variant(SOURCE_A::GPIO_3) + } + #[doc = "OR of all I2C"] + #[inline(always)] + pub fn i2c(self) -> &'a mut W { + self.variant(SOURCE_A::I2C) + } + #[doc = "OR of all SPI"] + #[inline(always)] + pub fn spi(self) -> &'a mut W { + self.variant(SOURCE_A::SPI) + } + #[doc = "PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(self) -> &'a mut W { + self.variant(SOURCE_A::PCM_I2S) + } + #[doc = "SDHOST"] + #[inline(always)] + pub fn sdhost(self) -> &'a mut W { + self.variant(SOURCE_A::SDHOST) + } + #[doc = "OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(self) -> &'a mut W { + self.variant(SOURCE_A::UART) + } + #[doc = "OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(self) -> &'a mut W { + self.variant(SOURCE_A::ETH_PCIE) + } + #[doc = "VEC"] + #[inline(always)] + pub fn vec(self) -> &'a mut W { + self.variant(SOURCE_A::VEC) + } + #[doc = "CPG"] + #[inline(always)] + pub fn cpg(self) -> &'a mut W { + self.variant(SOURCE_A::CPG) + } + #[doc = "RNG"] + #[inline(always)] + pub fn rng(self) -> &'a mut W { + self.variant(SOURCE_A::RNG) + } + #[doc = "OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(self) -> &'a mut W { + self.variant(SOURCE_A::EMMC) + } + #[doc = "ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(self) -> &'a mut W { + self.variant(SOURCE_A::ETH_PCIE_SECURE) + } + #[doc = "ARMC Timer"] + #[inline(always)] + pub fn timer(self) -> &'a mut W { + self.variant(SOURCE_A::TIMER) + } + #[doc = "Mailbox"] + #[inline(always)] + pub fn mailbox(self) -> &'a mut W { + self.variant(SOURCE_A::MAILBOX) + } + #[doc = "Doorbell 0"] + #[inline(always)] + pub fn doorbell0(self) -> &'a mut W { + self.variant(SOURCE_A::DOORBELL0) + } + #[doc = "Doorbell 1"] + #[inline(always)] + pub fn doorbell1(self) -> &'a mut W { + self.variant(SOURCE_A::DOORBELL1) + } + #[doc = "VPU0 halted"] + #[inline(always)] + pub fn vpu0_halted(self) -> &'a mut W { + self.variant(SOURCE_A::VPU0_HALTED) + } + #[doc = "VPU1 halted"] + #[inline(always)] + pub fn vpu1_halted(self) -> &'a mut W { + self.variant(SOURCE_A::VPU1_HALTED) + } + #[doc = "ARM address error"] + #[inline(always)] + pub fn arm_address_error(self) -> &'a mut W { + self.variant(SOURCE_A::ARM_ADDRESS_ERROR) + } + #[doc = "ARM AXI error"] + #[inline(always)] + pub fn arm_axi_error(self) -> &'a mut W { + self.variant(SOURCE_A::ARM_AXI_ERROR) + } +} +#[doc = "Field `ENABLE` reader - FIQ Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - FIQ Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIQ_CONTROL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - FIQ Source"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - FIQ Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - FIQ Source"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W<0> { + SOURCE_W::new(self) + } + #[doc = "Bit 7 - FIQ Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<7> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIQ control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fiq_control](index.html) module"] +pub struct FIQ_CONTROL_SPEC; +impl crate::RegisterSpec for FIQ_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fiq_control::R](R) reader structure"] +impl crate::Readable for FIQ_CONTROL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fiq_control::W](W) writer structure"] +impl crate::Writable for FIQ_CONTROL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIQ_CONTROL to value 0"] +impl crate::Resettable for FIQ_CONTROL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/pending_1.rs b/crates/bcm2837-lpa/src/lic/pending_1.rs new file mode 100644 index 0000000..e4ae642 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/pending_1.rs @@ -0,0 +1,254 @@ +#[doc = "Register `PENDING_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TIMER_0` reader - Timer 0"] +pub type TIMER_0_R = crate::BitReader; +#[doc = "Field `TIMER_1` reader - Timer 1"] +pub type TIMER_1_R = crate::BitReader; +#[doc = "Field `TIMER_2` reader - Timer 2"] +pub type TIMER_2_R = crate::BitReader; +#[doc = "Field `TIMER_3` reader - Timer 3"] +pub type TIMER_3_R = crate::BitReader; +#[doc = "Field `H264_0` reader - H264 0"] +pub type H264_0_R = crate::BitReader; +#[doc = "Field `H264_1` reader - H264 1"] +pub type H264_1_R = crate::BitReader; +#[doc = "Field `H264_2` reader - H264 2"] +pub type H264_2_R = crate::BitReader; +#[doc = "Field `JPEG` reader - JPEG"] +pub type JPEG_R = crate::BitReader; +#[doc = "Field `ISP` reader - ISP"] +pub type ISP_R = crate::BitReader; +#[doc = "Field `USB` reader - USB"] +pub type USB_R = crate::BitReader; +#[doc = "Field `V3D` reader - V3D"] +pub type V3D_R = crate::BitReader; +#[doc = "Field `TRANSPOSER` reader - Transposer"] +pub type TRANSPOSER_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] +pub type MULTICORE_SYNC_0_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] +pub type MULTICORE_SYNC_1_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] +pub type MULTICORE_SYNC_2_R = crate::BitReader; +#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] +pub type MULTICORE_SYNC_3_R = crate::BitReader; +#[doc = "Field `DMA_0` reader - DMA 0"] +pub type DMA_0_R = crate::BitReader; +#[doc = "Field `DMA_1` reader - DMA 1"] +pub type DMA_1_R = crate::BitReader; +#[doc = "Field `DMA_2` reader - DMA 2"] +pub type DMA_2_R = crate::BitReader; +#[doc = "Field `DMA_3` reader - DMA 3"] +pub type DMA_3_R = crate::BitReader; +#[doc = "Field `DMA_4` reader - DMA 4"] +pub type DMA_4_R = crate::BitReader; +#[doc = "Field `DMA_5` reader - DMA 5"] +pub type DMA_5_R = crate::BitReader; +#[doc = "Field `DMA_6` reader - DMA 6"] +pub type DMA_6_R = crate::BitReader; +#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] +pub type DMA_7_8_R = crate::BitReader; +#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] +pub type DMA_9_10_R = crate::BitReader; +#[doc = "Field `DMA_11` reader - DMA 11"] +pub type DMA_11_R = crate::BitReader; +#[doc = "Field `DMA_12` reader - DMA 12"] +pub type DMA_12_R = crate::BitReader; +#[doc = "Field `DMA_13` reader - DMA 13"] +pub type DMA_13_R = crate::BitReader; +#[doc = "Field `DMA_14` reader - DMA 14"] +pub type DMA_14_R = crate::BitReader; +#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] +pub type AUX_R = crate::BitReader; +#[doc = "Field `ARM` reader - ARM"] +pub type ARM_R = crate::BitReader; +#[doc = "Field `DMA_15` reader - DMA 15"] +pub type DMA_15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Timer 0"] + #[inline(always)] + pub fn timer_0(&self) -> TIMER_0_R { + TIMER_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer 1"] + #[inline(always)] + pub fn timer_1(&self) -> TIMER_1_R { + TIMER_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timer 2"] + #[inline(always)] + pub fn timer_2(&self) -> TIMER_2_R { + TIMER_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timer 3"] + #[inline(always)] + pub fn timer_3(&self) -> TIMER_3_R { + TIMER_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - H264 0"] + #[inline(always)] + pub fn h264_0(&self) -> H264_0_R { + H264_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - H264 1"] + #[inline(always)] + pub fn h264_1(&self) -> H264_1_R { + H264_1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - H264 2"] + #[inline(always)] + pub fn h264_2(&self) -> H264_2_R { + H264_2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - JPEG"] + #[inline(always)] + pub fn jpeg(&self) -> JPEG_R { + JPEG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ISP"] + #[inline(always)] + pub fn isp(&self) -> ISP_R { + ISP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - USB"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - V3D"] + #[inline(always)] + pub fn v3d(&self) -> V3D_R { + V3D_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Transposer"] + #[inline(always)] + pub fn transposer(&self) -> TRANSPOSER_R { + TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Multicore Sync 0"] + #[inline(always)] + pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R { + MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Multicore Sync 1"] + #[inline(always)] + pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R { + MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Multicore Sync 2"] + #[inline(always)] + pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R { + MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Multicore Sync 3"] + #[inline(always)] + pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R { + MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - DMA 0"] + #[inline(always)] + pub fn dma_0(&self) -> DMA_0_R { + DMA_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DMA 1"] + #[inline(always)] + pub fn dma_1(&self) -> DMA_1_R { + DMA_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DMA 2"] + #[inline(always)] + pub fn dma_2(&self) -> DMA_2_R { + DMA_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DMA 3"] + #[inline(always)] + pub fn dma_3(&self) -> DMA_3_R { + DMA_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DMA 4"] + #[inline(always)] + pub fn dma_4(&self) -> DMA_4_R { + DMA_4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DMA 5"] + #[inline(always)] + pub fn dma_5(&self) -> DMA_5_R { + DMA_5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DMA 6"] + #[inline(always)] + pub fn dma_6(&self) -> DMA_6_R { + DMA_6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - OR of DMA 7 and 8"] + #[inline(always)] + pub fn dma_7_8(&self) -> DMA_7_8_R { + DMA_7_8_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - OR of DMA 9 and 10"] + #[inline(always)] + pub fn dma_9_10(&self) -> DMA_9_10_R { + DMA_9_10_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - DMA 11"] + #[inline(always)] + pub fn dma_11(&self) -> DMA_11_R { + DMA_11_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - DMA 12"] + #[inline(always)] + pub fn dma_12(&self) -> DMA_12_R { + DMA_12_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - DMA 13"] + #[inline(always)] + pub fn dma_13(&self) -> DMA_13_R { + DMA_13_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - DMA 14"] + #[inline(always)] + pub fn dma_14(&self) -> DMA_14_R { + DMA_14_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] + #[inline(always)] + pub fn aux(&self) -> AUX_R { + AUX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ARM"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - DMA 15"] + #[inline(always)] + pub fn dma_15(&self) -> DMA_15_R { + DMA_15_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Pending state for interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_1](index.html) module"] +pub struct PENDING_1_SPEC; +impl crate::RegisterSpec for PENDING_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pending_1::R](R) reader structure"] +impl crate::Readable for PENDING_1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDING_1 to value 0"] +impl crate::Resettable for PENDING_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/lic/pending_2.rs b/crates/bcm2837-lpa/src/lic/pending_2.rs new file mode 100644 index 0000000..f9a32c7 --- /dev/null +++ b/crates/bcm2837-lpa/src/lic/pending_2.rs @@ -0,0 +1,254 @@ +#[doc = "Register `PENDING_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HDMI_CEC` reader - HDMI CEC"] +pub type HDMI_CEC_R = crate::BitReader; +#[doc = "Field `HVS` reader - HVS"] +pub type HVS_R = crate::BitReader; +#[doc = "Field `RPIVID` reader - RPIVID"] +pub type RPIVID_R = crate::BitReader; +#[doc = "Field `SDC` reader - SDC"] +pub type SDC_R = crate::BitReader; +#[doc = "Field `DSI_0` reader - DSI 0"] +pub type DSI_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] +pub type PIXEL_VALVE_2_R = crate::BitReader; +#[doc = "Field `CAMERA_0` reader - Camera 0"] +pub type CAMERA_0_R = crate::BitReader; +#[doc = "Field `CAMERA_1` reader - Camera 1"] +pub type CAMERA_1_R = crate::BitReader; +#[doc = "Field `HDMI_0` reader - HDMI 0"] +pub type HDMI_0_R = crate::BitReader; +#[doc = "Field `HDMI_1` reader - HDMI 1"] +pub type HDMI_1_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] +pub type PIXEL_VALVE_3_R = crate::BitReader; +#[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] +pub type SPI_BSC_SLAVE_R = crate::BitReader; +#[doc = "Field `DSI_1` reader - DSI 1"] +pub type DSI_1_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] +pub type PIXEL_VALVE_0_R = crate::BitReader; +#[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] +pub type PIXEL_VALVE_1_2_R = crate::BitReader; +#[doc = "Field `CPR` reader - CPR"] +pub type CPR_R = crate::BitReader; +#[doc = "Field `SMI` reader - SMI"] +pub type SMI_R = crate::BitReader; +#[doc = "Field `GPIO_0` reader - GPIO 0"] +pub type GPIO_0_R = crate::BitReader; +#[doc = "Field `GPIO_1` reader - GPIO 1"] +pub type GPIO_1_R = crate::BitReader; +#[doc = "Field `GPIO_2` reader - GPIO 2"] +pub type GPIO_2_R = crate::BitReader; +#[doc = "Field `GPIO_3` reader - GPIO 3"] +pub type GPIO_3_R = crate::BitReader; +#[doc = "Field `I2C` reader - OR of all I2C"] +pub type I2C_R = crate::BitReader; +#[doc = "Field `SPI` reader - OR of all SPI"] +pub type SPI_R = crate::BitReader; +#[doc = "Field `PCM_I2S` reader - PCM/I2S"] +pub type PCM_I2S_R = crate::BitReader; +#[doc = "Field `SDHOST` reader - SDHOST"] +pub type SDHOST_R = crate::BitReader; +#[doc = "Field `UART` reader - OR of all PL011 UARTs"] +pub type UART_R = crate::BitReader; +#[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] +pub type ETH_PCIE_R = crate::BitReader; +#[doc = "Field `VEC` reader - VEC"] +pub type VEC_R = crate::BitReader; +#[doc = "Field `CPG` reader - CPG"] +pub type CPG_R = crate::BitReader; +#[doc = "Field `RNG` reader - RNG"] +pub type RNG_R = crate::BitReader; +#[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] +pub type EMMC_R = crate::BitReader; +#[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] +pub type ETH_PCIE_SECURE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - HDMI CEC"] + #[inline(always)] + pub fn hdmi_cec(&self) -> HDMI_CEC_R { + HDMI_CEC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HVS"] + #[inline(always)] + pub fn hvs(&self) -> HVS_R { + HVS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RPIVID"] + #[inline(always)] + pub fn rpivid(&self) -> RPIVID_R { + RPIVID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SDC"] + #[inline(always)] + pub fn sdc(&self) -> SDC_R { + SDC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DSI 0"] + #[inline(always)] + pub fn dsi_0(&self) -> DSI_0_R { + DSI_0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pixel Valve 2"] + #[inline(always)] + pub fn pixel_valve_2(&self) -> PIXEL_VALVE_2_R { + PIXEL_VALVE_2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Camera 0"] + #[inline(always)] + pub fn camera_0(&self) -> CAMERA_0_R { + CAMERA_0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Camera 1"] + #[inline(always)] + pub fn camera_1(&self) -> CAMERA_1_R { + CAMERA_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - HDMI 0"] + #[inline(always)] + pub fn hdmi_0(&self) -> HDMI_0_R { + HDMI_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HDMI 1"] + #[inline(always)] + pub fn hdmi_1(&self) -> HDMI_1_R { + HDMI_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pixel Valve 3"] + #[inline(always)] + pub fn pixel_valve_3(&self) -> PIXEL_VALVE_3_R { + PIXEL_VALVE_3_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SPI/BSC Slave"] + #[inline(always)] + pub fn spi_bsc_slave(&self) -> SPI_BSC_SLAVE_R { + SPI_BSC_SLAVE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DSI 1"] + #[inline(always)] + pub fn dsi_1(&self) -> DSI_1_R { + DSI_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pixel Valve 0"] + #[inline(always)] + pub fn pixel_valve_0(&self) -> PIXEL_VALVE_0_R { + PIXEL_VALVE_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] + #[inline(always)] + pub fn pixel_valve_1_2(&self) -> PIXEL_VALVE_1_2_R { + PIXEL_VALVE_1_2_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CPR"] + #[inline(always)] + pub fn cpr(&self) -> CPR_R { + CPR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - SMI"] + #[inline(always)] + pub fn smi(&self) -> SMI_R { + SMI_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - GPIO 0"] + #[inline(always)] + pub fn gpio_0(&self) -> GPIO_0_R { + GPIO_0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - GPIO 1"] + #[inline(always)] + pub fn gpio_1(&self) -> GPIO_1_R { + GPIO_1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - GPIO 2"] + #[inline(always)] + pub fn gpio_2(&self) -> GPIO_2_R { + GPIO_2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - GPIO 3"] + #[inline(always)] + pub fn gpio_3(&self) -> GPIO_3_R { + GPIO_3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - OR of all I2C"] + #[inline(always)] + pub fn i2c(&self) -> I2C_R { + I2C_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - OR of all SPI"] + #[inline(always)] + pub fn spi(&self) -> SPI_R { + SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - PCM/I2S"] + #[inline(always)] + pub fn pcm_i2s(&self) -> PCM_I2S_R { + PCM_I2S_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - SDHOST"] + #[inline(always)] + pub fn sdhost(&self) -> SDHOST_R { + SDHOST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - OR of all PL011 UARTs"] + #[inline(always)] + pub fn uart(&self) -> UART_R { + UART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - OR of all ETH_PCIe L2"] + #[inline(always)] + pub fn eth_pcie(&self) -> ETH_PCIE_R { + ETH_PCIE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - VEC"] + #[inline(always)] + pub fn vec(&self) -> VEC_R { + VEC_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - CPG"] + #[inline(always)] + pub fn cpg(&self) -> CPG_R { + CPG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - RNG"] + #[inline(always)] + pub fn rng(&self) -> RNG_R { + RNG_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - OR of EMMC and EMMC2"] + #[inline(always)] + pub fn emmc(&self) -> EMMC_R { + EMMC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ETH_PCIe secure"] + #[inline(always)] + pub fn eth_pcie_secure(&self) -> ETH_PCIE_SECURE_R { + ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Pending state for interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_2](index.html) module"] +pub struct PENDING_2_SPEC; +impl crate::RegisterSpec for PENDING_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pending_2::R](R) reader structure"] +impl crate::Readable for PENDING_2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDING_2 to value 0"] +impl crate::Resettable for PENDING_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/pwm0.rs b/crates/bcm2837-lpa/src/pwm0.rs new file mode 100644 index 0000000..4270433 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctl: CTL, + #[doc = "0x04 - Status"] + pub sta: STA, + #[doc = "0x08 - DMA control"] + pub dmac: DMAC, + _reserved3: [u8; 0x04], + #[doc = "0x10 - Range for channel 1"] + pub rng1: RNG1, + #[doc = "0x14 - Channel 1 data"] + pub dat1: DAT1, + #[doc = "0x18 - FIFO input"] + pub fif1: FIF1, + _reserved6: [u8; 0x04], + #[doc = "0x20 - Range for channel 2"] + pub rng2: RNG2, + #[doc = "0x24 - Channel 2 data"] + pub dat2: DAT2, +} +#[doc = "CTL (rw) register accessor: an alias for `Reg`"] +pub type CTL = crate::Reg; +#[doc = "Control"] +pub mod ctl; +#[doc = "STA (rw) register accessor: an alias for `Reg`"] +pub type STA = crate::Reg; +#[doc = "Status"] +pub mod sta; +#[doc = "DMAC (rw) register accessor: an alias for `Reg`"] +pub type DMAC = crate::Reg; +#[doc = "DMA control"] +pub mod dmac; +#[doc = "RNG1 (rw) register accessor: an alias for `Reg`"] +pub type RNG1 = crate::Reg; +#[doc = "Range for channel 1"] +pub mod rng1; +#[doc = "DAT1 (rw) register accessor: an alias for `Reg`"] +pub type DAT1 = crate::Reg; +#[doc = "Channel 1 data"] +pub mod dat1; +#[doc = "FIF1 (w) register accessor: an alias for `Reg`"] +pub type FIF1 = crate::Reg; +#[doc = "FIFO input"] +pub mod fif1; +#[doc = "RNG2 (rw) register accessor: an alias for `Reg`"] +pub type RNG2 = crate::Reg; +#[doc = "Range for channel 2"] +pub mod rng2; +#[doc = "DAT2 (rw) register accessor: an alias for `Reg`"] +pub type DAT2 = crate::Reg; +#[doc = "Channel 2 data"] +pub mod dat2; diff --git a/crates/bcm2837-lpa/src/pwm0/ctl.rs b/crates/bcm2837-lpa/src/pwm0/ctl.rs new file mode 100644 index 0000000..b41b326 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/ctl.rs @@ -0,0 +1,382 @@ +#[doc = "Register `CTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWEN1` reader - Enable channel 1"] +pub type PWEN1_R = crate::BitReader; +#[doc = "Field `PWEN1` writer - Enable channel 1"] +pub type PWEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MODE1` reader - Channel 1 mode"] +pub type MODE1_R = crate::BitReader; +#[doc = "Channel 1 mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE1_A { + #[doc = "0: `0`"] + PWM = 0, + #[doc = "1: `1`"] + SERIAL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE1_A) -> Self { + variant as u8 != 0 + } +} +impl MODE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE1_A { + match self.bits { + false => MODE1_A::PWM, + true => MODE1_A::SERIAL, + } + } + #[doc = "Checks if the value of the field is `PWM`"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == MODE1_A::PWM + } + #[doc = "Checks if the value of the field is `SERIAL`"] + #[inline(always)] + pub fn is_serial(&self) -> bool { + *self == MODE1_A::SERIAL + } +} +#[doc = "Field `MODE1` writer - Channel 1 mode"] +pub type MODE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE1_A, O>; +impl<'a, const O: u8> MODE1_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn pwm(self) -> &'a mut W { + self.variant(MODE1_A::PWM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn serial(self) -> &'a mut W { + self.variant(MODE1_A::SERIAL) + } +} +#[doc = "Field `RPTL1` reader - Repeat last value from FIFO for channel 1"] +pub type RPTL1_R = crate::BitReader; +#[doc = "Field `RPTL1` writer - Repeat last value from FIFO for channel 1"] +pub type RPTL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `SBIT1` reader - State when not transmitting on channel 1"] +pub type SBIT1_R = crate::BitReader; +#[doc = "Field `SBIT1` writer - State when not transmitting on channel 1"] +pub type SBIT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `POLA1` reader - Channel 1 polarity inverted"] +pub type POLA1_R = crate::BitReader; +#[doc = "Field `POLA1` writer - Channel 1 polarity inverted"] +pub type POLA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `USEF1` reader - Use FIFO for channel 1"] +pub type USEF1_R = crate::BitReader; +#[doc = "Field `USEF1` writer - Use FIFO for channel 1"] +pub type USEF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `CLRF1` reader - Clear FIFO"] +pub type CLRF1_R = crate::BitReader; +#[doc = "Field `CLRF1` writer - Clear FIFO"] +pub type CLRF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MSEN1` reader - M/S mode for channel 1"] +pub type MSEN1_R = crate::BitReader; +#[doc = "Field `MSEN1` writer - M/S mode for channel 1"] +pub type MSEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `PWEN2` reader - Enable channel 2"] +pub type PWEN2_R = crate::BitReader; +#[doc = "Field `PWEN2` writer - Enable channel 2"] +pub type PWEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MODE2` reader - Channel 2 mode"] +pub type MODE2_R = crate::BitReader; +#[doc = "Channel 2 mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE2_A { + #[doc = "0: `0`"] + PWM = 0, + #[doc = "1: `1`"] + SERIAL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE2_A) -> Self { + variant as u8 != 0 + } +} +impl MODE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODE2_A { + match self.bits { + false => MODE2_A::PWM, + true => MODE2_A::SERIAL, + } + } + #[doc = "Checks if the value of the field is `PWM`"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == MODE2_A::PWM + } + #[doc = "Checks if the value of the field is `SERIAL`"] + #[inline(always)] + pub fn is_serial(&self) -> bool { + *self == MODE2_A::SERIAL + } +} +#[doc = "Field `MODE2` writer - Channel 2 mode"] +pub type MODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE2_A, O>; +impl<'a, const O: u8> MODE2_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn pwm(self) -> &'a mut W { + self.variant(MODE2_A::PWM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn serial(self) -> &'a mut W { + self.variant(MODE2_A::SERIAL) + } +} +#[doc = "Field `RPTL2` reader - Repeat last value from FIFO for channel 2"] +pub type RPTL2_R = crate::BitReader; +#[doc = "Field `RPTL2` writer - Repeat last value from FIFO for channel 2"] +pub type RPTL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `SBIT2` reader - State when not transmitting on channel 2"] +pub type SBIT2_R = crate::BitReader; +#[doc = "Field `SBIT2` writer - State when not transmitting on channel 2"] +pub type SBIT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `POLA2` reader - Channel 2 polarity inverted"] +pub type POLA2_R = crate::BitReader; +#[doc = "Field `POLA2` writer - Channel 2 polarity inverted"] +pub type POLA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `USEF2` reader - Use FIFO for channel 2"] +pub type USEF2_R = crate::BitReader; +#[doc = "Field `USEF2` writer - Use FIFO for channel 2"] +pub type USEF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +#[doc = "Field `MSEN2` reader - M/S mode for channel 2"] +pub type MSEN2_R = crate::BitReader; +#[doc = "Field `MSEN2` writer - M/S mode for channel 2"] +pub type MSEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + pub fn pwen1(&self) -> PWEN1_R { + PWEN1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 mode"] + #[inline(always)] + pub fn mode1(&self) -> MODE1_R { + MODE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] + #[inline(always)] + pub fn rptl1(&self) -> RPTL1_R { + RPTL1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - State when not transmitting on channel 1"] + #[inline(always)] + pub fn sbit1(&self) -> SBIT1_R { + SBIT1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 1 polarity inverted"] + #[inline(always)] + pub fn pola1(&self) -> POLA1_R { + POLA1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Use FIFO for channel 1"] + #[inline(always)] + pub fn usef1(&self) -> USEF1_R { + USEF1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Clear FIFO"] + #[inline(always)] + pub fn clrf1(&self) -> CLRF1_R { + CLRF1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - M/S mode for channel 1"] + #[inline(always)] + pub fn msen1(&self) -> MSEN1_R { + MSEN1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable channel 2"] + #[inline(always)] + pub fn pwen2(&self) -> PWEN2_R { + PWEN2_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 2 mode"] + #[inline(always)] + pub fn mode2(&self) -> MODE2_R { + MODE2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] + #[inline(always)] + pub fn rptl2(&self) -> RPTL2_R { + RPTL2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - State when not transmitting on channel 2"] + #[inline(always)] + pub fn sbit2(&self) -> SBIT2_R { + SBIT2_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 2 polarity inverted"] + #[inline(always)] + pub fn pola2(&self) -> POLA2_R { + POLA2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Use FIFO for channel 2"] + #[inline(always)] + pub fn usef2(&self) -> USEF2_R { + USEF2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - M/S mode for channel 2"] + #[inline(always)] + pub fn msen2(&self) -> MSEN2_R { + MSEN2_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable channel 1"] + #[inline(always)] + #[must_use] + pub fn pwen1(&mut self) -> PWEN1_W<0> { + PWEN1_W::new(self) + } + #[doc = "Bit 1 - Channel 1 mode"] + #[inline(always)] + #[must_use] + pub fn mode1(&mut self) -> MODE1_W<1> { + MODE1_W::new(self) + } + #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] + #[inline(always)] + #[must_use] + pub fn rptl1(&mut self) -> RPTL1_W<2> { + RPTL1_W::new(self) + } + #[doc = "Bit 3 - State when not transmitting on channel 1"] + #[inline(always)] + #[must_use] + pub fn sbit1(&mut self) -> SBIT1_W<3> { + SBIT1_W::new(self) + } + #[doc = "Bit 4 - Channel 1 polarity inverted"] + #[inline(always)] + #[must_use] + pub fn pola1(&mut self) -> POLA1_W<4> { + POLA1_W::new(self) + } + #[doc = "Bit 5 - Use FIFO for channel 1"] + #[inline(always)] + #[must_use] + pub fn usef1(&mut self) -> USEF1_W<5> { + USEF1_W::new(self) + } + #[doc = "Bit 6 - Clear FIFO"] + #[inline(always)] + #[must_use] + pub fn clrf1(&mut self) -> CLRF1_W<6> { + CLRF1_W::new(self) + } + #[doc = "Bit 7 - M/S mode for channel 1"] + #[inline(always)] + #[must_use] + pub fn msen1(&mut self) -> MSEN1_W<7> { + MSEN1_W::new(self) + } + #[doc = "Bit 8 - Enable channel 2"] + #[inline(always)] + #[must_use] + pub fn pwen2(&mut self) -> PWEN2_W<8> { + PWEN2_W::new(self) + } + #[doc = "Bit 9 - Channel 2 mode"] + #[inline(always)] + #[must_use] + pub fn mode2(&mut self) -> MODE2_W<9> { + MODE2_W::new(self) + } + #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] + #[inline(always)] + #[must_use] + pub fn rptl2(&mut self) -> RPTL2_W<10> { + RPTL2_W::new(self) + } + #[doc = "Bit 11 - State when not transmitting on channel 2"] + #[inline(always)] + #[must_use] + pub fn sbit2(&mut self) -> SBIT2_W<11> { + SBIT2_W::new(self) + } + #[doc = "Bit 12 - Channel 2 polarity inverted"] + #[inline(always)] + #[must_use] + pub fn pola2(&mut self) -> POLA2_W<12> { + POLA2_W::new(self) + } + #[doc = "Bit 13 - Use FIFO for channel 2"] + #[inline(always)] + #[must_use] + pub fn usef2(&mut self) -> USEF2_W<13> { + USEF2_W::new(self) + } + #[doc = "Bit 15 - M/S mode for channel 2"] + #[inline(always)] + #[must_use] + pub fn msen2(&mut self) -> MSEN2_W<15> { + MSEN2_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"] +pub struct CTL_SPEC; +impl crate::RegisterSpec for CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctl::R](R) reader structure"] +impl crate::Readable for CTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"] +impl crate::Writable for CTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTL to value 0"] +impl crate::Resettable for CTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/pwm0/dat1.rs b/crates/bcm2837-lpa/src/pwm0/dat1.rs new file mode 100644 index 0000000..c197492 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/dat1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel 1 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat1](index.html) module"] +pub struct DAT1_SPEC; +impl crate::RegisterSpec for DAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dat1::R](R) reader structure"] +impl crate::Readable for DAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dat1::W](W) writer structure"] +impl crate::Writable for DAT1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAT1 to value 0"] +impl crate::Resettable for DAT1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/pwm0/dat2.rs b/crates/bcm2837-lpa/src/pwm0/dat2.rs new file mode 100644 index 0000000..b9e07a3 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/dat2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel 2 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat2](index.html) module"] +pub struct DAT2_SPEC; +impl crate::RegisterSpec for DAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dat2::R](R) reader structure"] +impl crate::Readable for DAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dat2::W](W) writer structure"] +impl crate::Writable for DAT2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAT2 to value 0"] +impl crate::Resettable for DAT2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/pwm0/dmac.rs b/crates/bcm2837-lpa/src/pwm0/dmac.rs new file mode 100644 index 0000000..b201822 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/dmac.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DMAC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMAC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DREQ` reader - DMA threshold for DREQ signal"] +pub type DREQ_R = crate::FieldReader; +#[doc = "Field `DREQ` writer - DMA threshold for DREQ signal"] +pub type DREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +#[doc = "Field `PANIC` reader - DMA threshold for panic signal"] +pub type PANIC_R = crate::FieldReader; +#[doc = "Field `PANIC` writer - DMA threshold for panic signal"] +pub type PANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +#[doc = "Field `ENAB` reader - DMA enabled"] +pub type ENAB_R = crate::BitReader; +#[doc = "Field `ENAB` writer - DMA enabled"] +pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] + #[inline(always)] + pub fn dreq(&self) -> DREQ_R { + DREQ_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA threshold for panic signal"] + #[inline(always)] + pub fn panic(&self) -> PANIC_R { + PANIC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 31 - DMA enabled"] + #[inline(always)] + pub fn enab(&self) -> ENAB_R { + ENAB_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] + #[inline(always)] + #[must_use] + pub fn dreq(&mut self) -> DREQ_W<0> { + DREQ_W::new(self) + } + #[doc = "Bits 8:15 - DMA threshold for panic signal"] + #[inline(always)] + #[must_use] + pub fn panic(&mut self) -> PANIC_W<8> { + PANIC_W::new(self) + } + #[doc = "Bit 31 - DMA enabled"] + #[inline(always)] + #[must_use] + pub fn enab(&mut self) -> ENAB_W<31> { + ENAB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac](index.html) module"] +pub struct DMAC_SPEC; +impl crate::RegisterSpec for DMAC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmac::R](R) reader structure"] +impl crate::Readable for DMAC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmac::W](W) writer structure"] +impl crate::Writable for DMAC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMAC to value 0"] +impl crate::Resettable for DMAC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/pwm0/fif1.rs b/crates/bcm2837-lpa/src/pwm0/fif1.rs new file mode 100644 index 0000000..e786328 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/fif1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FIF1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO input\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fif1](index.html) module"] +pub struct FIF1_SPEC; +impl crate::RegisterSpec for FIF1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fif1::W](W) writer structure"] +impl crate::Writable for FIF1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIF1 to value 0"] +impl crate::Resettable for FIF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/pwm0/rng1.rs b/crates/bcm2837-lpa/src/pwm0/rng1.rs new file mode 100644 index 0000000..b6f5446 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/rng1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RNG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RNG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Range for channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng1](index.html) module"] +pub struct RNG1_SPEC; +impl crate::RegisterSpec for RNG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rng1::R](R) reader structure"] +impl crate::Readable for RNG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rng1::W](W) writer structure"] +impl crate::Writable for RNG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG1 to value 0x20"] +impl crate::Resettable for RNG1_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/crates/bcm2837-lpa/src/pwm0/rng2.rs b/crates/bcm2837-lpa/src/pwm0/rng2.rs new file mode 100644 index 0000000..0cc95d5 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/rng2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RNG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RNG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Range for channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng2](index.html) module"] +pub struct RNG2_SPEC; +impl crate::RegisterSpec for RNG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rng2::R](R) reader structure"] +impl crate::Readable for RNG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rng2::W](W) writer structure"] +impl crate::Writable for RNG2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG2 to value 0x20"] +impl crate::Resettable for RNG2_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/crates/bcm2837-lpa/src/pwm0/sta.rs b/crates/bcm2837-lpa/src/pwm0/sta.rs new file mode 100644 index 0000000..f0b99b7 --- /dev/null +++ b/crates/bcm2837-lpa/src/pwm0/sta.rs @@ -0,0 +1,260 @@ +#[doc = "Register `STA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FULL1` reader - FIFO full"] +pub type FULL1_R = crate::BitReader; +#[doc = "Field `FULL1` writer - FIFO full"] +pub type FULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `EMPT1` reader - FIFO empty"] +pub type EMPT1_R = crate::BitReader; +#[doc = "Field `EMPT1` writer - FIFO empty"] +pub type EMPT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `WERR1` reader - FIFO write error"] +pub type WERR1_R = crate::BitReader; +#[doc = "Field `WERR1` writer - FIFO write error"] +pub type WERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `RERR1` reader - FIFO read error"] +pub type RERR1_R = crate::BitReader; +#[doc = "Field `RERR1` writer - FIFO read error"] +pub type RERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO1` reader - Channel 1 gap occurred"] +pub type GAPO1_R = crate::BitReader; +#[doc = "Field `GAPO1` writer - Channel 1 gap occurred"] +pub type GAPO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO2` reader - Channel 2 gap occurred"] +pub type GAPO2_R = crate::BitReader; +#[doc = "Field `GAPO2` writer - Channel 2 gap occurred"] +pub type GAPO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO3` reader - Channel 3 gap occurred"] +pub type GAPO3_R = crate::BitReader; +#[doc = "Field `GAPO3` writer - Channel 3 gap occurred"] +pub type GAPO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `GAPO4` reader - Channel 4 gap occurred"] +pub type GAPO4_R = crate::BitReader; +#[doc = "Field `GAPO4` writer - Channel 4 gap occurred"] +pub type GAPO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Bus error"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Bus error"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA1` reader - Channel 1 state"] +pub type STA1_R = crate::BitReader; +#[doc = "Field `STA1` writer - Channel 1 state"] +pub type STA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA2` reader - Channel 2 state"] +pub type STA2_R = crate::BitReader; +#[doc = "Field `STA2` writer - Channel 2 state"] +pub type STA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA3` reader - Channel 3 state"] +pub type STA3_R = crate::BitReader; +#[doc = "Field `STA3` writer - Channel 3 state"] +pub type STA3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +#[doc = "Field `STA4` reader - Channel 4 state"] +pub type STA4_R = crate::BitReader; +#[doc = "Field `STA4` writer - Channel 4 state"] +pub type STA4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - FIFO full"] + #[inline(always)] + pub fn full1(&self) -> FULL1_R { + FULL1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO empty"] + #[inline(always)] + pub fn empt1(&self) -> EMPT1_R { + EMPT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO write error"] + #[inline(always)] + pub fn werr1(&self) -> WERR1_R { + WERR1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO read error"] + #[inline(always)] + pub fn rerr1(&self) -> RERR1_R { + RERR1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 1 gap occurred"] + #[inline(always)] + pub fn gapo1(&self) -> GAPO1_R { + GAPO1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 2 gap occurred"] + #[inline(always)] + pub fn gapo2(&self) -> GAPO2_R { + GAPO2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 3 gap occurred"] + #[inline(always)] + pub fn gapo3(&self) -> GAPO3_R { + GAPO3_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 4 gap occurred"] + #[inline(always)] + pub fn gapo4(&self) -> GAPO4_R { + GAPO4_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Bus error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 1 state"] + #[inline(always)] + pub fn sta1(&self) -> STA1_R { + STA1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 2 state"] + #[inline(always)] + pub fn sta2(&self) -> STA2_R { + STA2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 3 state"] + #[inline(always)] + pub fn sta3(&self) -> STA3_R { + STA3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 4 state"] + #[inline(always)] + pub fn sta4(&self) -> STA4_R { + STA4_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FIFO full"] + #[inline(always)] + #[must_use] + pub fn full1(&mut self) -> FULL1_W<0> { + FULL1_W::new(self) + } + #[doc = "Bit 1 - FIFO empty"] + #[inline(always)] + #[must_use] + pub fn empt1(&mut self) -> EMPT1_W<1> { + EMPT1_W::new(self) + } + #[doc = "Bit 2 - FIFO write error"] + #[inline(always)] + #[must_use] + pub fn werr1(&mut self) -> WERR1_W<2> { + WERR1_W::new(self) + } + #[doc = "Bit 3 - FIFO read error"] + #[inline(always)] + #[must_use] + pub fn rerr1(&mut self) -> RERR1_W<3> { + RERR1_W::new(self) + } + #[doc = "Bit 4 - Channel 1 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo1(&mut self) -> GAPO1_W<4> { + GAPO1_W::new(self) + } + #[doc = "Bit 5 - Channel 2 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo2(&mut self) -> GAPO2_W<5> { + GAPO2_W::new(self) + } + #[doc = "Bit 6 - Channel 3 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo3(&mut self) -> GAPO3_W<6> { + GAPO3_W::new(self) + } + #[doc = "Bit 7 - Channel 4 gap occurred"] + #[inline(always)] + #[must_use] + pub fn gapo4(&mut self) -> GAPO4_W<7> { + GAPO4_W::new(self) + } + #[doc = "Bit 8 - Bus error"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<8> { + BERR_W::new(self) + } + #[doc = "Bit 9 - Channel 1 state"] + #[inline(always)] + #[must_use] + pub fn sta1(&mut self) -> STA1_W<9> { + STA1_W::new(self) + } + #[doc = "Bit 10 - Channel 2 state"] + #[inline(always)] + #[must_use] + pub fn sta2(&mut self) -> STA2_W<10> { + STA2_W::new(self) + } + #[doc = "Bit 11 - Channel 3 state"] + #[inline(always)] + #[must_use] + pub fn sta3(&mut self) -> STA3_W<11> { + STA3_W::new(self) + } + #[doc = "Bit 12 - Channel 4 state"] + #[inline(always)] + #[must_use] + pub fn sta4(&mut self) -> STA4_W<12> { + STA4_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"] +pub struct STA_SPEC; +impl crate::RegisterSpec for STA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sta::R](R) reader structure"] +impl crate::Readable for STA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sta::W](W) writer structure"] +impl crate::Writable for STA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STA to value 0"] +impl crate::Resettable for STA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi0.rs b/crates/bcm2837-lpa/src/spi0.rs new file mode 100644 index 0000000..88737df --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control and Status"] + pub cs: CS, + #[doc = "0x04 - FIFO access"] + pub fifo: FIFO, + #[doc = "0x08 - Clock divider"] + pub clk: CLK, + #[doc = "0x0c - Data length"] + pub dlen: DLEN, + #[doc = "0x10 - LoSSI output hold delay"] + pub ltoh: LTOH, + #[doc = "0x14 - "] + pub dc: DC, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control and Status"] +pub mod cs; +#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +pub type FIFO = crate::Reg; +#[doc = "FIFO access"] +pub mod fifo; +#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +pub type CLK = crate::Reg; +#[doc = "Clock divider"] +pub mod clk; +#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +pub type DLEN = crate::Reg; +#[doc = "Data length"] +pub mod dlen; +#[doc = "LTOH (rw) register accessor: an alias for `Reg`"] +pub type LTOH = crate::Reg; +#[doc = "LoSSI output hold delay"] +pub mod ltoh; +#[doc = "DC (rw) register accessor: an alias for `Reg`"] +pub type DC = crate::Reg; +#[doc = ""] +pub mod dc; diff --git a/crates/bcm2837-lpa/src/spi0/clk.rs b/crates/bcm2837-lpa/src/spi0/clk.rs new file mode 100644 index 0000000..ef3272e --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0/clk.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CLK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CDIV` reader - Clock divider"] +pub type CDIV_R = crate::FieldReader; +#[doc = "Field `CDIV` writer - Clock divider"] +pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Clock divider"] + #[inline(always)] + pub fn cdiv(&self) -> CDIV_R { + CDIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Clock divider"] + #[inline(always)] + #[must_use] + pub fn cdiv(&mut self) -> CDIV_W<0> { + CDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clk::R](R) reader structure"] +impl crate::Readable for CLK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +impl crate::Writable for CLK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi0/cs.rs b/crates/bcm2837-lpa/src/spi0/cs.rs new file mode 100644 index 0000000..50227aa --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0/cs.rs @@ -0,0 +1,446 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CS` reader - Chip select"] +pub type CS_R = crate::FieldReader; +#[doc = "Field `CS` writer - Chip select"] +pub type CS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +#[doc = "Field `CPHA` reader - Clock phase"] +pub type CPHA_R = crate::BitReader; +#[doc = "Field `CPHA` writer - Clock phase"] +pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CPOL` reader - Clock polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Field `CPOL` writer - Clock polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CLEAR` reader - Clear the FIFO(s)"] +pub type CLEAR_R = crate::FieldReader; +#[doc = "Clear the FIFO(s)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CLEAR_A { + #[doc = "1: `1`"] + TX = 1, + #[doc = "2: `10`"] + RX = 2, + #[doc = "3: `11`"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_A) -> Self { + variant as _ + } +} +impl CLEAR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CLEAR_A::TX), + 2 => Some(CLEAR_A::RX), + 3 => Some(CLEAR_A::BOTH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + *self == CLEAR_A::TX + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + *self == CLEAR_A::RX + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == CLEAR_A::BOTH + } +} +#[doc = "Field `CLEAR` writer - Clear the FIFO(s)"] +pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, CLEAR_A, 2, O>; +impl<'a, const O: u8> CLEAR_W<'a, O> { + #[doc = "`1`"] + #[inline(always)] + pub fn tx(self) -> &'a mut W { + self.variant(CLEAR_A::TX) + } + #[doc = "`10`"] + #[inline(always)] + pub fn rx(self) -> &'a mut W { + self.variant(CLEAR_A::RX) + } + #[doc = "`11`"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(CLEAR_A::BOTH) + } +} +#[doc = "Field `CSPOL` reader - Chip select polarity"] +pub type CSPOL_R = crate::BitReader; +#[doc = "Field `CSPOL` writer - Chip select polarity"] +pub type CSPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `TA` reader - Transfer active"] +pub type TA_R = crate::BitReader; +#[doc = "Field `TA` writer - Transfer active"] +pub type TA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - Enable DMA"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - Enable DMA"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `INTD` reader - Interrupt on done"] +pub type INTD_R = crate::BitReader; +#[doc = "Field `INTD` writer - Interrupt on done"] +pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `INTR` reader - Interrupt on RX"] +pub type INTR_R = crate::BitReader; +#[doc = "Field `INTR` writer - Interrupt on RX"] +pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `ADCS` reader - Automatically deassert chip select"] +pub type ADCS_R = crate::BitReader; +#[doc = "Field `ADCS` writer - Automatically deassert chip select"] +pub type ADCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `REN` reader - Read enable"] +pub type REN_R = crate::BitReader; +#[doc = "Field `REN` writer - Read enable"] +pub type REN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LEN` reader - LoSSI enable"] +pub type LEN_R = crate::BitReader; +#[doc = "Field `LEN` writer - LoSSI enable"] +pub type LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LMONO` reader - "] +pub type LMONO_R = crate::BitReader; +#[doc = "Field `LMONO` writer - "] +pub type LMONO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `TE_EN` reader - "] +pub type TE_EN_R = crate::BitReader; +#[doc = "Field `TE_EN` writer - "] +pub type TE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DONE` reader - Transfer is done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `RXD` reader - RX FIFO contains data"] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXD` reader - TX FIFO can accept data"] +pub type TXD_R = crate::BitReader; +#[doc = "Field `RXR` reader - RX FIFO has data to be read"] +pub type RXR_R = crate::BitReader; +#[doc = "Field `RXF` reader - RX FIFO full"] +pub type RXF_R = crate::BitReader; +#[doc = "Field `CSPOL0` reader - Chip select 0 polarity"] +pub type CSPOL0_R = crate::BitReader; +#[doc = "Field `CSPOL0` writer - Chip select 0 polarity"] +pub type CSPOL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CSPOL1` reader - Chip select 1 polarity"] +pub type CSPOL1_R = crate::BitReader; +#[doc = "Field `CSPOL1` writer - Chip select 1 polarity"] +pub type CSPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `CSPOL2` reader - Chip select 2 polarity"] +pub type CSPOL2_R = crate::BitReader; +#[doc = "Field `CSPOL2` writer - Chip select 2 polarity"] +pub type CSPOL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"] +pub type DMA_LEN_R = crate::BitReader; +#[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"] +pub type DMA_LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"] +pub type LEN_LONG_R = crate::BitReader; +#[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"] +pub type LEN_LONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Chip select"] + #[inline(always)] + pub fn cs(&self) -> CS_R { + CS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Clock phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clock polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Clear the FIFO(s)"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Chip select polarity"] + #[inline(always)] + pub fn cspol(&self) -> CSPOL_R { + CSPOL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transfer active"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable DMA"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on done"] + #[inline(always)] + pub fn intd(&self) -> INTD_R { + INTD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Automatically deassert chip select"] + #[inline(always)] + pub fn adcs(&self) -> ADCS_R { + ADCS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Read enable"] + #[inline(always)] + pub fn ren(&self) -> REN_R { + REN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - LoSSI enable"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn lmono(&self) -> LMONO_R { + LMONO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn te_en(&self) -> TE_EN_R { + TE_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Transfer is done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - RX FIFO contains data"] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - TX FIFO can accept data"] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RX FIFO has data to be read"] + #[inline(always)] + pub fn rxr(&self) -> RXR_R { + RXR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - RX FIFO full"] + #[inline(always)] + pub fn rxf(&self) -> RXF_R { + RXF_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Chip select 0 polarity"] + #[inline(always)] + pub fn cspol0(&self) -> CSPOL0_R { + CSPOL0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Chip select 1 polarity"] + #[inline(always)] + pub fn cspol1(&self) -> CSPOL1_R { + CSPOL1_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Chip select 2 polarity"] + #[inline(always)] + pub fn cspol2(&self) -> CSPOL2_R { + CSPOL2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable DMA in LoSSI mode"] + #[inline(always)] + pub fn dma_len(&self) -> DMA_LEN_R { + DMA_LEN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Enable long data word in LoSSI mode"] + #[inline(always)] + pub fn len_long(&self) -> LEN_LONG_R { + LEN_LONG_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Chip select"] + #[inline(always)] + #[must_use] + pub fn cs(&mut self) -> CS_W<0> { + CS_W::new(self) + } + #[doc = "Bit 2 - Clock phase"] + #[inline(always)] + #[must_use] + pub fn cpha(&mut self) -> CPHA_W<2> { + CPHA_W::new(self) + } + #[doc = "Bit 3 - Clock polarity"] + #[inline(always)] + #[must_use] + pub fn cpol(&mut self) -> CPOL_W<3> { + CPOL_W::new(self) + } + #[doc = "Bits 4:5 - Clear the FIFO(s)"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<4> { + CLEAR_W::new(self) + } + #[doc = "Bit 6 - Chip select polarity"] + #[inline(always)] + #[must_use] + pub fn cspol(&mut self) -> CSPOL_W<6> { + CSPOL_W::new(self) + } + #[doc = "Bit 7 - Transfer active"] + #[inline(always)] + #[must_use] + pub fn ta(&mut self) -> TA_W<7> { + TA_W::new(self) + } + #[doc = "Bit 8 - Enable DMA"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<8> { + DMAEN_W::new(self) + } + #[doc = "Bit 9 - Interrupt on done"] + #[inline(always)] + #[must_use] + pub fn intd(&mut self) -> INTD_W<9> { + INTD_W::new(self) + } + #[doc = "Bit 10 - Interrupt on RX"] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W<10> { + INTR_W::new(self) + } + #[doc = "Bit 11 - Automatically deassert chip select"] + #[inline(always)] + #[must_use] + pub fn adcs(&mut self) -> ADCS_W<11> { + ADCS_W::new(self) + } + #[doc = "Bit 12 - Read enable"] + #[inline(always)] + #[must_use] + pub fn ren(&mut self) -> REN_W<12> { + REN_W::new(self) + } + #[doc = "Bit 13 - LoSSI enable"] + #[inline(always)] + #[must_use] + pub fn len(&mut self) -> LEN_W<13> { + LEN_W::new(self) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn lmono(&mut self) -> LMONO_W<14> { + LMONO_W::new(self) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn te_en(&mut self) -> TE_EN_W<15> { + TE_EN_W::new(self) + } + #[doc = "Bit 21 - Chip select 0 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol0(&mut self) -> CSPOL0_W<21> { + CSPOL0_W::new(self) + } + #[doc = "Bit 22 - Chip select 1 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol1(&mut self) -> CSPOL1_W<22> { + CSPOL1_W::new(self) + } + #[doc = "Bit 23 - Chip select 2 polarity"] + #[inline(always)] + #[must_use] + pub fn cspol2(&mut self) -> CSPOL2_W<23> { + CSPOL2_W::new(self) + } + #[doc = "Bit 24 - Enable DMA in LoSSI mode"] + #[inline(always)] + #[must_use] + pub fn dma_len(&mut self) -> DMA_LEN_W<24> { + DMA_LEN_W::new(self) + } + #[doc = "Bit 25 - Enable long data word in LoSSI mode"] + #[inline(always)] + #[must_use] + pub fn len_long(&mut self) -> LEN_LONG_W<25> { + LEN_LONG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CS to value 0x0004_1000"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_1000; +} diff --git a/crates/bcm2837-lpa/src/spi0/dc.rs b/crates/bcm2837-lpa/src/spi0/dc.rs new file mode 100644 index 0000000..281dd71 --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0/dc.rs @@ -0,0 +1,125 @@ +#[doc = "Register `DC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDREQ` reader - DMA Write request threshold"] +pub type TDREQ_R = crate::FieldReader; +#[doc = "Field `TDREQ` writer - DMA Write request threshold"] +pub type TDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `TPANIC` reader - DMA write panic threshold"] +pub type TPANIC_R = crate::FieldReader; +#[doc = "Field `TPANIC` writer - DMA write panic threshold"] +pub type TPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `RDREQ` reader - DMA read request threshold"] +pub type RDREQ_R = crate::FieldReader; +#[doc = "Field `RDREQ` writer - DMA read request threshold"] +pub type RDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +#[doc = "Field `RPANIC` reader - DMA read panic threshold"] +pub type RPANIC_R = crate::FieldReader; +#[doc = "Field `RPANIC` writer - DMA read panic threshold"] +pub type RPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - DMA Write request threshold"] + #[inline(always)] + pub fn tdreq(&self) -> TDREQ_R { + TDREQ_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DMA write panic threshold"] + #[inline(always)] + pub fn tpanic(&self) -> TPANIC_R { + TPANIC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - DMA read request threshold"] + #[inline(always)] + pub fn rdreq(&self) -> RDREQ_R { + RDREQ_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - DMA read panic threshold"] + #[inline(always)] + pub fn rpanic(&self) -> RPANIC_R { + RPANIC_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - DMA Write request threshold"] + #[inline(always)] + #[must_use] + pub fn tdreq(&mut self) -> TDREQ_W<0> { + TDREQ_W::new(self) + } + #[doc = "Bits 8:15 - DMA write panic threshold"] + #[inline(always)] + #[must_use] + pub fn tpanic(&mut self) -> TPANIC_W<8> { + TPANIC_W::new(self) + } + #[doc = "Bits 16:23 - DMA read request threshold"] + #[inline(always)] + #[must_use] + pub fn rdreq(&mut self) -> RDREQ_W<16> { + RDREQ_W::new(self) + } + #[doc = "Bits 24:31 - DMA read panic threshold"] + #[inline(always)] + #[must_use] + pub fn rpanic(&mut self) -> RPANIC_W<24> { + RPANIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc](index.html) module"] +pub struct DC_SPEC; +impl crate::RegisterSpec for DC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dc::R](R) reader structure"] +impl crate::Readable for DC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dc::W](W) writer structure"] +impl crate::Writable for DC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DC to value 0x3020_1050"] +impl crate::Resettable for DC_SPEC { + const RESET_VALUE: Self::Ux = 0x3020_1050; +} diff --git a/crates/bcm2837-lpa/src/spi0/dlen.rs b/crates/bcm2837-lpa/src/spi0/dlen.rs new file mode 100644 index 0000000..25e2771 --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0/dlen.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLEN` reader - Data length"] +pub type DLEN_R = crate::FieldReader; +#[doc = "Field `DLEN` writer - Data length"] +pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + pub fn dlen(&self) -> DLEN_R { + DLEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Data length"] + #[inline(always)] + #[must_use] + pub fn dlen(&mut self) -> DLEN_W<0> { + DLEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +pub struct DLEN_SPEC; +impl crate::RegisterSpec for DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dlen::R](R) reader structure"] +impl crate::Readable for DLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +impl crate::Writable for DLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLEN to value 0"] +impl crate::Resettable for DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi0/fifo.rs b/crates/bcm2837-lpa/src/spi0/fifo.rs new file mode 100644 index 0000000..46d2ece --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0/fifo.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FIFO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo::R](R) reader structure"] +impl crate::Readable for FIFO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi0/ltoh.rs b/crates/bcm2837-lpa/src/spi0/ltoh.rs new file mode 100644 index 0000000..5d0ab3f --- /dev/null +++ b/crates/bcm2837-lpa/src/spi0/ltoh.rs @@ -0,0 +1,80 @@ +#[doc = "Register `LTOH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LTOH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOH` reader - Output hold delay"] +pub type TOH_R = crate::FieldReader; +#[doc = "Field `TOH` writer - Output hold delay"] +pub type TOH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LTOH_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Output hold delay"] + #[inline(always)] + pub fn toh(&self) -> TOH_R { + TOH_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Output hold delay"] + #[inline(always)] + #[must_use] + pub fn toh(&mut self) -> TOH_W<0> { + TOH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LoSSI output hold delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ltoh](index.html) module"] +pub struct LTOH_SPEC; +impl crate::RegisterSpec for LTOH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ltoh::R](R) reader structure"] +impl crate::Readable for LTOH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ltoh::W](W) writer structure"] +impl crate::Writable for LTOH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LTOH to value 0x01"] +impl crate::Resettable for LTOH_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/crates/bcm2837-lpa/src/spi1.rs b/crates/bcm2837-lpa/src/spi1.rs new file mode 100644 index 0000000..1547fcc --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control 0"] + pub cntl0: CNTL0, + #[doc = "0x04 - Control 1"] + pub cntl1: CNTL1, + #[doc = "0x08 - Status"] + pub stat: STAT, + #[doc = "0x0c - Read the RXFIFO without removing an entry"] + pub peek: PEEK, + #[doc = "0x10..0x20 - Writing to the FIFO will deassert CS at the end of the access"] + pub io: [IO; 4], + #[doc = "0x20..0x30 - Writing to the FIFO will maintain CS at the end of the access"] + pub txhold: [TXHOLD; 4], +} +#[doc = "CNTL0 (rw) register accessor: an alias for `Reg`"] +pub type CNTL0 = crate::Reg; +#[doc = "Control 0"] +pub mod cntl0; +#[doc = "CNTL1 (rw) register accessor: an alias for `Reg`"] +pub type CNTL1 = crate::Reg; +#[doc = "Control 1"] +pub mod cntl1; +#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "PEEK (r) register accessor: an alias for `Reg`"] +pub type PEEK = crate::Reg; +#[doc = "Read the RXFIFO without removing an entry"] +pub mod peek; +#[doc = "IO (rw) register accessor: an alias for `Reg`"] +pub type IO = crate::Reg; +#[doc = "Writing to the FIFO will deassert CS at the end of the access"] +pub mod io; +#[doc = "TXHOLD (rw) register accessor: an alias for `Reg`"] +pub type TXHOLD = crate::Reg; +#[doc = "Writing to the FIFO will maintain CS at the end of the access"] +pub mod txhold; diff --git a/crates/bcm2837-lpa/src/spi1/cntl0.rs b/crates/bcm2837-lpa/src/spi1/cntl0.rs new file mode 100644 index 0000000..b9354b5 --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1/cntl0.rs @@ -0,0 +1,335 @@ +#[doc = "Register `CNTL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFT_LENGTH` reader - Number of bits to shift"] +pub type SHIFT_LENGTH_R = crate::FieldReader; +#[doc = "Field `SHIFT_LENGTH` writer - Number of bits to shift"] +pub type SHIFT_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 6, O>; +#[doc = "Field `MSB_FIRST` reader - Shift out the most significant bit (MSB) first"] +pub type MSB_FIRST_R = crate::BitReader; +#[doc = "Field `MSB_FIRST` writer - Shift out the most significant bit (MSB) first"] +pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `INVERT_CLK` reader - Idle clock high"] +pub type INVERT_CLK_R = crate::BitReader; +#[doc = "Field `INVERT_CLK` writer - Idle clock high"] +pub type INVERT_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `OUT_RISING` reader - Data is clocked out on rising edge of CLK"] +pub type OUT_RISING_R = crate::BitReader; +#[doc = "Field `OUT_RISING` writer - Data is clocked out on rising edge of CLK"] +pub type OUT_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `CLEAR_FIFOS` reader - Clear FIFOs"] +pub type CLEAR_FIFOS_R = crate::BitReader; +#[doc = "Field `CLEAR_FIFOS` writer - Clear FIFOs"] +pub type CLEAR_FIFOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `IN_RISING` reader - Data is clocked in on rising edge of CLK"] +pub type IN_RISING_R = crate::BitReader; +#[doc = "Field `IN_RISING` writer - Data is clocked in on rising edge of CLK"] +pub type IN_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable the interface"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable the interface"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `DOUT_HOLD_TIME` reader - Controls extra DOUT hold time in system clock cycles"] +pub type DOUT_HOLD_TIME_R = crate::FieldReader; +#[doc = "Controls extra DOUT hold time in system clock cycles\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DOUT_HOLD_TIME_A { + #[doc = "0: `0`"] + _0 = 0, + #[doc = "1: `1`"] + _1 = 1, + #[doc = "2: `10`"] + _4 = 2, + #[doc = "3: `11`"] + _7 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOUT_HOLD_TIME_A) -> Self { + variant as _ + } +} +impl DOUT_HOLD_TIME_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOUT_HOLD_TIME_A { + match self.bits { + 0 => DOUT_HOLD_TIME_A::_0, + 1 => DOUT_HOLD_TIME_A::_1, + 2 => DOUT_HOLD_TIME_A::_4, + 3 => DOUT_HOLD_TIME_A::_7, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_1 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_4 + } + #[doc = "Checks if the value of the field is `_7`"] + #[inline(always)] + pub fn is_7(&self) -> bool { + *self == DOUT_HOLD_TIME_A::_7 + } +} +#[doc = "Field `DOUT_HOLD_TIME` writer - Controls extra DOUT hold time in system clock cycles"] +pub type DOUT_HOLD_TIME_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CNTL0_SPEC, u8, DOUT_HOLD_TIME_A, 2, O>; +impl<'a, const O: u8> DOUT_HOLD_TIME_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _0(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_0) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_1) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_4) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _7(self) -> &'a mut W { + self.variant(DOUT_HOLD_TIME_A::_7) + } +} +#[doc = "Field `VARIABLE_WIDTH` reader - Take shift length and data from FIFO"] +pub type VARIABLE_WIDTH_R = crate::BitReader; +#[doc = "Field `VARIABLE_WIDTH` writer - Take shift length and data from FIFO"] +pub type VARIABLE_WIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `VARIABLE_CS` reader - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] +pub type VARIABLE_CS_R = crate::BitReader; +#[doc = "Field `VARIABLE_CS` writer - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] +pub type VARIABLE_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `POST_INPUT` reader - Post input mode"] +pub type POST_INPUT_R = crate::BitReader; +#[doc = "Field `POST_INPUT` writer - Post input mode"] +pub type POST_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +#[doc = "Field `CHIP_SELECTS` reader - The CS pattern when active"] +pub type CHIP_SELECTS_R = crate::FieldReader; +#[doc = "Field `CHIP_SELECTS` writer - The CS pattern when active"] +pub type CHIP_SELECTS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 3, O>; +#[doc = "Field `SPEED` reader - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Field `SPEED` writer - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] +pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:5 - Number of bits to shift"] + #[inline(always)] + pub fn shift_length(&self) -> SHIFT_LENGTH_R { + SHIFT_LENGTH_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] + #[inline(always)] + pub fn msb_first(&self) -> MSB_FIRST_R { + MSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Idle clock high"] + #[inline(always)] + pub fn invert_clk(&self) -> INVERT_CLK_R { + INVERT_CLK_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] + #[inline(always)] + pub fn out_rising(&self) -> OUT_RISING_R { + OUT_RISING_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Clear FIFOs"] + #[inline(always)] + pub fn clear_fifos(&self) -> CLEAR_FIFOS_R { + CLEAR_FIFOS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] + #[inline(always)] + pub fn in_rising(&self) -> IN_RISING_R { + IN_RISING_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable the interface"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] + #[inline(always)] + pub fn dout_hold_time(&self) -> DOUT_HOLD_TIME_R { + DOUT_HOLD_TIME_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Take shift length and data from FIFO"] + #[inline(always)] + pub fn variable_width(&self) -> VARIABLE_WIDTH_R { + VARIABLE_WIDTH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] + #[inline(always)] + pub fn variable_cs(&self) -> VARIABLE_CS_R { + VARIABLE_CS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Post input mode"] + #[inline(always)] + pub fn post_input(&self) -> POST_INPUT_R { + POST_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - The CS pattern when active"] + #[inline(always)] + pub fn chip_selects(&self) -> CHIP_SELECTS_R { + CHIP_SELECTS_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:5 - Number of bits to shift"] + #[inline(always)] + #[must_use] + pub fn shift_length(&mut self) -> SHIFT_LENGTH_W<0> { + SHIFT_LENGTH_W::new(self) + } + #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] + #[inline(always)] + #[must_use] + pub fn msb_first(&mut self) -> MSB_FIRST_W<6> { + MSB_FIRST_W::new(self) + } + #[doc = "Bit 7 - Idle clock high"] + #[inline(always)] + #[must_use] + pub fn invert_clk(&mut self) -> INVERT_CLK_W<7> { + INVERT_CLK_W::new(self) + } + #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] + #[inline(always)] + #[must_use] + pub fn out_rising(&mut self) -> OUT_RISING_W<8> { + OUT_RISING_W::new(self) + } + #[doc = "Bit 9 - Clear FIFOs"] + #[inline(always)] + #[must_use] + pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W<9> { + CLEAR_FIFOS_W::new(self) + } + #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] + #[inline(always)] + #[must_use] + pub fn in_rising(&mut self) -> IN_RISING_W<10> { + IN_RISING_W::new(self) + } + #[doc = "Bit 11 - Enable the interface"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<11> { + ENABLE_W::new(self) + } + #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] + #[inline(always)] + #[must_use] + pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W<12> { + DOUT_HOLD_TIME_W::new(self) + } + #[doc = "Bit 14 - Take shift length and data from FIFO"] + #[inline(always)] + #[must_use] + pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W<14> { + VARIABLE_WIDTH_W::new(self) + } + #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] + #[inline(always)] + #[must_use] + pub fn variable_cs(&mut self) -> VARIABLE_CS_W<15> { + VARIABLE_CS_W::new(self) + } + #[doc = "Bit 16 - Post input mode"] + #[inline(always)] + #[must_use] + pub fn post_input(&mut self) -> POST_INPUT_W<16> { + POST_INPUT_W::new(self) + } + #[doc = "Bits 17:19 - The CS pattern when active"] + #[inline(always)] + #[must_use] + pub fn chip_selects(&mut self) -> CHIP_SELECTS_W<17> { + CHIP_SELECTS_W::new(self) + } + #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W<20> { + SPEED_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl0](index.html) module"] +pub struct CNTL0_SPEC; +impl crate::RegisterSpec for CNTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl0::R](R) reader structure"] +impl crate::Readable for CNTL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl0::W](W) writer structure"] +impl crate::Writable for CNTL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL0 to value 0x000e_0000"] +impl crate::Resettable for CNTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x000e_0000; +} diff --git a/crates/bcm2837-lpa/src/spi1/cntl1.rs b/crates/bcm2837-lpa/src/spi1/cntl1.rs new file mode 100644 index 0000000..c7d627b --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1/cntl1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CNTL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `KEEP_INPUT` reader - Don't clear the RX shift register before a new transaction"] +pub type KEEP_INPUT_R = crate::BitReader; +#[doc = "Field `KEEP_INPUT` writer - Don't clear the RX shift register before a new transaction"] +pub type KEEP_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `MSB_FIRST` reader - Shift the most significant bit first (MSB)"] +pub type MSB_FIRST_R = crate::BitReader; +#[doc = "Field `MSB_FIRST` writer - Shift the most significant bit first (MSB)"] +pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `DONE_ENABLE` reader - Enable DONE interrupt"] +pub type DONE_ENABLE_R = crate::BitReader; +#[doc = "Field `DONE_ENABLE` writer - Enable DONE interrupt"] +pub type DONE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `TXE_ENABLE` reader - Enable TX empty interrupt"] +pub type TXE_ENABLE_R = crate::BitReader; +#[doc = "Field `TXE_ENABLE` writer - Enable TX empty interrupt"] +pub type TXE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +#[doc = "Field `CS_HIGH_TIME` reader - Additional SPI clock cycles where CS is high"] +pub type CS_HIGH_TIME_R = crate::FieldReader; +#[doc = "Field `CS_HIGH_TIME` writer - Additional SPI clock cycles where CS is high"] +pub type CS_HIGH_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL1_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] + #[inline(always)] + pub fn keep_input(&self) -> KEEP_INPUT_R { + KEEP_INPUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] + #[inline(always)] + pub fn msb_first(&self) -> MSB_FIRST_R { + MSB_FIRST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Enable DONE interrupt"] + #[inline(always)] + pub fn done_enable(&self) -> DONE_ENABLE_R { + DONE_ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable TX empty interrupt"] + #[inline(always)] + pub fn txe_enable(&self) -> TXE_ENABLE_R { + TXE_ENABLE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] + #[inline(always)] + pub fn cs_high_time(&self) -> CS_HIGH_TIME_R { + CS_HIGH_TIME_R::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] + #[inline(always)] + #[must_use] + pub fn keep_input(&mut self) -> KEEP_INPUT_W<0> { + KEEP_INPUT_W::new(self) + } + #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] + #[inline(always)] + #[must_use] + pub fn msb_first(&mut self) -> MSB_FIRST_W<1> { + MSB_FIRST_W::new(self) + } + #[doc = "Bit 6 - Enable DONE interrupt"] + #[inline(always)] + #[must_use] + pub fn done_enable(&mut self) -> DONE_ENABLE_W<6> { + DONE_ENABLE_W::new(self) + } + #[doc = "Bit 7 - Enable TX empty interrupt"] + #[inline(always)] + #[must_use] + pub fn txe_enable(&mut self) -> TXE_ENABLE_W<7> { + TXE_ENABLE_W::new(self) + } + #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] + #[inline(always)] + #[must_use] + pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W<8> { + CS_HIGH_TIME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl1](index.html) module"] +pub struct CNTL1_SPEC; +impl crate::RegisterSpec for CNTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl1::R](R) reader structure"] +impl crate::Readable for CNTL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl1::W](W) writer structure"] +impl crate::Writable for CNTL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL1 to value 0"] +impl crate::Resettable for CNTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi1/io.rs b/crates/bcm2837-lpa/src/spi1/io.rs new file mode 100644 index 0000000..365004d --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1/io.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IO%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IO%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO data access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +pub struct IO_SPEC; +impl crate::RegisterSpec for IO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [io::R](R) reader structure"] +impl crate::Readable for IO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +impl crate::Writable for IO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IO%s to value 0"] +impl crate::Resettable for IO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi1/peek.rs b/crates/bcm2837-lpa/src/spi1/peek.rs new file mode 100644 index 0000000..b4a7333 --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1/peek.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PEEK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Read the RXFIFO without removing an entry\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek](index.html) module"] +pub struct PEEK_SPEC; +impl crate::RegisterSpec for PEEK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek::R](R) reader structure"] +impl crate::Readable for PEEK_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PEEK to value 0"] +impl crate::Resettable for PEEK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi1/stat.rs b/crates/bcm2837-lpa/src/spi1/stat.rs new file mode 100644 index 0000000..0dd56f6 --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1/stat.rs @@ -0,0 +1,185 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIT_COUNT` reader - Number of bits left to be processed."] +pub type BIT_COUNT_R = crate::FieldReader; +#[doc = "Field `BIT_COUNT` writer - Number of bits left to be processed."] +pub type BIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 6, O>; +#[doc = "Field `BUSY` reader - Indicates a transfer is ongoing"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `BUSY` writer - Indicates a transfer is ongoing"] +pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_EMPTY` reader - RX FIFO is empty"] +pub type RX_EMPTY_R = crate::BitReader; +#[doc = "Field `RX_EMPTY` writer - RX FIFO is empty"] +pub type RX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_FULL` reader - RX FIFO is full"] +pub type RX_FULL_R = crate::BitReader; +#[doc = "Field `RX_FULL` writer - RX FIFO is full"] +pub type RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - TX FIFO is empty"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - TX FIFO is empty"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_FULL` reader - TX FIFO is full"] +pub type TX_FULL_R = crate::BitReader; +#[doc = "Field `TX_FULL` writer - TX FIFO is full"] +pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_LEVEL` reader - Number of entries in RX FIFO"] +pub type RX_LEVEL_R = crate::FieldReader; +#[doc = "Field `RX_LEVEL` writer - Number of entries in RX FIFO"] +pub type RX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_LEVEL` reader - Number of entries in TX FIFO"] +pub type TX_LEVEL_R = crate::FieldReader; +#[doc = "Field `TX_LEVEL` writer - Number of entries in TX FIFO"] +pub type TX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:5 - Number of bits left to be processed."] + #[inline(always)] + pub fn bit_count(&self) -> BIT_COUNT_R { + BIT_COUNT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Indicates a transfer is ongoing"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RX FIFO is empty"] + #[inline(always)] + pub fn rx_empty(&self) -> RX_EMPTY_R { + RX_EMPTY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is full"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TX FIFO is empty"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO is full"] + #[inline(always)] + pub fn tx_full(&self) -> TX_FULL_R { + TX_FULL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 16:19 - Number of entries in RX FIFO"] + #[inline(always)] + pub fn rx_level(&self) -> RX_LEVEL_R { + RX_LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Number of entries in TX FIFO"] + #[inline(always)] + pub fn tx_level(&self) -> TX_LEVEL_R { + TX_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Number of bits left to be processed."] + #[inline(always)] + #[must_use] + pub fn bit_count(&mut self) -> BIT_COUNT_W<0> { + BIT_COUNT_W::new(self) + } + #[doc = "Bit 6 - Indicates a transfer is ongoing"] + #[inline(always)] + #[must_use] + pub fn busy(&mut self) -> BUSY_W<6> { + BUSY_W::new(self) + } + #[doc = "Bit 7 - RX FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn rx_empty(&mut self) -> RX_EMPTY_W<7> { + RX_EMPTY_W::new(self) + } + #[doc = "Bit 8 - RX FIFO is full"] + #[inline(always)] + #[must_use] + pub fn rx_full(&mut self) -> RX_FULL_W<8> { + RX_FULL_W::new(self) + } + #[doc = "Bit 9 - TX FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<9> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 10 - TX FIFO is full"] + #[inline(always)] + #[must_use] + pub fn tx_full(&mut self) -> TX_FULL_W<10> { + TX_FULL_W::new(self) + } + #[doc = "Bits 16:19 - Number of entries in RX FIFO"] + #[inline(always)] + #[must_use] + pub fn rx_level(&mut self) -> RX_LEVEL_W<16> { + RX_LEVEL_W::new(self) + } + #[doc = "Bits 24:27 - Number of entries in TX FIFO"] + #[inline(always)] + #[must_use] + pub fn tx_level(&mut self) -> TX_LEVEL_W<24> { + TX_LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/spi1/txhold.rs b/crates/bcm2837-lpa/src/spi1/txhold.rs new file mode 100644 index 0000000..a2ca31b --- /dev/null +++ b/crates/bcm2837-lpa/src/spi1/txhold.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TXHOLD%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXHOLD%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO data access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO data access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXHOLD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - FIFO data access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txhold](index.html) module"] +pub struct TXHOLD_SPEC; +impl crate::RegisterSpec for TXHOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txhold::R](R) reader structure"] +impl crate::Readable for TXHOLD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txhold::W](W) writer structure"] +impl crate::Writable for TXHOLD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TXHOLD%s to value 0"] +impl crate::Resettable for TXHOLD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr.rs b/crates/bcm2837-lpa/src/systmr.rs new file mode 100644 index 0000000..859ea09 --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr.rs @@ -0,0 +1,46 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control / Status"] + pub cs: CS, + #[doc = "0x04 - Lower 32 bits for the free running counter"] + pub clo: CLO, + #[doc = "0x08 - Higher 32 bits for the free running counter"] + pub chi: CHI, + #[doc = "0x0c - Compare channel 0"] + pub c0: C0, + #[doc = "0x10 - Compare channel 1"] + pub c1: C1, + #[doc = "0x14 - Compare channel 2"] + pub c2: C2, + #[doc = "0x18 - Compare channel 3"] + pub c3: C3, +} +#[doc = "CS (rw) register accessor: an alias for `Reg`"] +pub type CS = crate::Reg; +#[doc = "Control / Status"] +pub mod cs; +#[doc = "CLO (r) register accessor: an alias for `Reg`"] +pub type CLO = crate::Reg; +#[doc = "Lower 32 bits for the free running counter"] +pub mod clo; +#[doc = "CHI (r) register accessor: an alias for `Reg`"] +pub type CHI = crate::Reg; +#[doc = "Higher 32 bits for the free running counter"] +pub mod chi; +#[doc = "C0 (rw) register accessor: an alias for `Reg`"] +pub type C0 = crate::Reg; +#[doc = "Compare channel 0"] +pub mod c0; +#[doc = "C1 (rw) register accessor: an alias for `Reg`"] +pub type C1 = crate::Reg; +#[doc = "Compare channel 1"] +pub mod c1; +#[doc = "C2 (rw) register accessor: an alias for `Reg`"] +pub type C2 = crate::Reg; +#[doc = "Compare channel 2"] +pub mod c2; +#[doc = "C3 (rw) register accessor: an alias for `Reg`"] +pub type C3 = crate::Reg; +#[doc = "Compare channel 3"] +pub mod c3; diff --git a/crates/bcm2837-lpa/src/systmr/c0.rs b/crates/bcm2837-lpa/src/systmr/c0.rs new file mode 100644 index 0000000..20b09d2 --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/c0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c0](index.html) module"] +pub struct C0_SPEC; +impl crate::RegisterSpec for C0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c0::R](R) reader structure"] +impl crate::Readable for C0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c0::W](W) writer structure"] +impl crate::Writable for C0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C0 to value 0"] +impl crate::Resettable for C0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr/c1.rs b/crates/bcm2837-lpa/src/systmr/c1.rs new file mode 100644 index 0000000..87cf5ed --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/c1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1](index.html) module"] +pub struct C1_SPEC; +impl crate::RegisterSpec for C1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c1::R](R) reader structure"] +impl crate::Readable for C1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c1::W](W) writer structure"] +impl crate::Writable for C1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C1 to value 0"] +impl crate::Resettable for C1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr/c2.rs b/crates/bcm2837-lpa/src/systmr/c2.rs new file mode 100644 index 0000000..8c9c84b --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/c2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c2](index.html) module"] +pub struct C2_SPEC; +impl crate::RegisterSpec for C2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c2::R](R) reader structure"] +impl crate::Readable for C2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c2::W](W) writer structure"] +impl crate::Writable for C2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C2 to value 0"] +impl crate::Resettable for C2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr/c3.rs b/crates/bcm2837-lpa/src/systmr/c3.rs new file mode 100644 index 0000000..0ac0aa2 --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/c3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `C3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `C3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c3](index.html) module"] +pub struct C3_SPEC; +impl crate::RegisterSpec for C3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [c3::R](R) reader structure"] +impl crate::Readable for C3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [c3::W](W) writer structure"] +impl crate::Writable for C3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C3 to value 0"] +impl crate::Resettable for C3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr/chi.rs b/crates/bcm2837-lpa/src/systmr/chi.rs new file mode 100644 index 0000000..9f162ef --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/chi.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CHI` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Higher 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chi](index.html) module"] +pub struct CHI_SPEC; +impl crate::RegisterSpec for CHI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chi::R](R) reader structure"] +impl crate::Readable for CHI_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHI to value 0"] +impl crate::Resettable for CHI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr/clo.rs b/crates/bcm2837-lpa/src/systmr/clo.rs new file mode 100644 index 0000000..0a4b01f --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/clo.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CLO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Lower 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clo](index.html) module"] +pub struct CLO_SPEC; +impl crate::RegisterSpec for CLO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clo::R](R) reader structure"] +impl crate::Readable for CLO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CLO to value 0"] +impl crate::Resettable for CLO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/systmr/cs.rs b/crates/bcm2837-lpa/src/systmr/cs.rs new file mode 100644 index 0000000..dcb8ec2 --- /dev/null +++ b/crates/bcm2837-lpa/src/systmr/cs.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0` reader - System timer match 0"] +pub type M0_R = crate::BitReader; +#[doc = "Field `M0` writer - System timer match 0"] +pub type M0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M1` reader - System timer match 1"] +pub type M1_R = crate::BitReader; +#[doc = "Field `M1` writer - System timer match 1"] +pub type M1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M2` reader - System timer match 2"] +pub type M2_R = crate::BitReader; +#[doc = "Field `M2` writer - System timer match 2"] +pub type M2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +#[doc = "Field `M3` reader - System timer match 3"] +pub type M3_R = crate::BitReader; +#[doc = "Field `M3` writer - System timer match 3"] +pub type M3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - System timer match 0"] + #[inline(always)] + pub fn m0(&self) -> M0_R { + M0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - System timer match 1"] + #[inline(always)] + pub fn m1(&self) -> M1_R { + M1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - System timer match 2"] + #[inline(always)] + pub fn m2(&self) -> M2_R { + M2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - System timer match 3"] + #[inline(always)] + pub fn m3(&self) -> M3_R { + M3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - System timer match 0"] + #[inline(always)] + #[must_use] + pub fn m0(&mut self) -> M0_W<0> { + M0_W::new(self) + } + #[doc = "Bit 1 - System timer match 1"] + #[inline(always)] + #[must_use] + pub fn m1(&mut self) -> M1_W<1> { + M1_W::new(self) + } + #[doc = "Bit 2 - System timer match 2"] + #[inline(always)] + #[must_use] + pub fn m2(&mut self) -> M2_W<2> { + M2_W::new(self) + } + #[doc = "Bit 3 - System timer match 3"] + #[inline(always)] + #[must_use] + pub fn m3(&mut self) -> M3_W<3> { + M3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cs::R](R) reader structure"] +impl crate::Readable for CS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0.rs b/crates/bcm2837-lpa/src/uart0.rs new file mode 100644 index 0000000..aade8a9 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Data Register"] + pub dr: DR, + _reserved_1_ecr: [u8; 0x04], + _reserved2: [u8; 0x10], + #[doc = "0x18 - Flag Register"] + pub fr: FR, + _reserved3: [u8; 0x08], + #[doc = "0x24 - Integer Baud Rate Register"] + pub ibrd: IBRD, + #[doc = "0x28 - Fractional Baud Rate Register"] + pub fbrd: FBRD, + #[doc = "0x2c - Line Control Register"] + pub lcr_h: LCR_H, + #[doc = "0x30 - Control Register"] + pub cr: CR, + #[doc = "0x34 - Interrupt FIFO Level Select Register"] + pub ifls: IFLS, + #[doc = "0x38 - Interrupt Mask set_Clear Register"] + pub imsc: IMSC, + #[doc = "0x3c - Raw Interrupt Status Register"] + pub ris: RIS, + #[doc = "0x40 - Masked Interrupt Status Register"] + pub mis: MIS, + #[doc = "0x44 - Interrupt Clear Register"] + pub icr: ICR, + #[doc = "0x48 - DMA Control Register"] + pub dmacr: DMACR, +} +impl RegisterBlock { + #[doc = "0x04 - Error Clear Register"] + #[inline(always)] + pub const fn ecr(&self) -> &ECR { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } + #[doc = "0x04 - Receive Status Register"] + #[inline(always)] + pub const fn rsr(&self) -> &RSR { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } +} +#[doc = "DR (rw) register accessor: an alias for `Reg`"] +pub type DR = crate::Reg; +#[doc = "Data Register"] +pub mod dr; +#[doc = "RSR (r) register accessor: an alias for `Reg`"] +pub type RSR = crate::Reg; +#[doc = "Receive Status Register"] +pub mod rsr; +#[doc = "ECR (w) register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Clear Register"] +pub mod ecr; +#[doc = "FR (rw) register accessor: an alias for `Reg`"] +pub type FR = crate::Reg; +#[doc = "Flag Register"] +pub mod fr; +#[doc = "IBRD (rw) register accessor: an alias for `Reg`"] +pub type IBRD = crate::Reg; +#[doc = "Integer Baud Rate Register"] +pub mod ibrd; +#[doc = "FBRD (rw) register accessor: an alias for `Reg`"] +pub type FBRD = crate::Reg; +#[doc = "Fractional Baud Rate Register"] +pub mod fbrd; +#[doc = "LCR_H (rw) register accessor: an alias for `Reg`"] +pub type LCR_H = crate::Reg; +#[doc = "Line Control Register"] +pub mod lcr_h; +#[doc = "CR (rw) register accessor: an alias for `Reg`"] +pub type CR = crate::Reg; +#[doc = "Control Register"] +pub mod cr; +#[doc = "IFLS (rw) register accessor: an alias for `Reg`"] +pub type IFLS = crate::Reg; +#[doc = "Interrupt FIFO Level Select Register"] +pub mod ifls; +#[doc = "IMSC (rw) register accessor: an alias for `Reg`"] +pub type IMSC = crate::Reg; +#[doc = "Interrupt Mask set_Clear Register"] +pub mod imsc; +#[doc = "RIS (r) register accessor: an alias for `Reg`"] +pub type RIS = crate::Reg; +#[doc = "Raw Interrupt Status Register"] +pub mod ris; +#[doc = "MIS (r) register accessor: an alias for `Reg`"] +pub type MIS = crate::Reg; +#[doc = "Masked Interrupt Status Register"] +pub mod mis; +#[doc = "ICR (w) register accessor: an alias for `Reg`"] +pub type ICR = crate::Reg; +#[doc = "Interrupt Clear Register"] +pub mod icr; +#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +pub type DMACR = crate::Reg; +#[doc = "DMA Control Register"] +pub mod dmacr; diff --git a/crates/bcm2837-lpa/src/uart0/cr.rs b/crates/bcm2837-lpa/src/uart0/cr.rs new file mode 100644 index 0000000..6c47a00 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/cr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `CR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UARTEN` reader - UARTEN"] +pub type UARTEN_R = crate::BitReader; +#[doc = "Field `UARTEN` writer - UARTEN"] +pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `SIREN` reader - SIREN"] +pub type SIREN_R = crate::BitReader; +#[doc = "Field `SIREN` writer - SIREN"] +pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `SIRLP` reader - SIRLP"] +pub type SIRLP_R = crate::BitReader; +#[doc = "Field `SIRLP` writer - SIRLP"] +pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `TXE` reader - TXE"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `TXE` writer - TXE"] +pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RXE` reader - RXE"] +pub type RXE_R = crate::BitReader; +#[doc = "Field `RXE` writer - RXE"] +pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `DTR` reader - DTR"] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - DTR"] +pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RTS` reader - RTS"] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - RTS"] +pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `RTSEN` reader - RTSEN"] +pub type RTSEN_R = crate::BitReader; +#[doc = "Field `RTSEN` writer - RTSEN"] +pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +#[doc = "Field `CTSEN` reader - CTSEN"] +pub type CTSEN_R = crate::BitReader; +#[doc = "Field `CTSEN` writer - CTSEN"] +pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - UARTEN"] + #[inline(always)] + pub fn uarten(&self) -> UARTEN_R { + UARTEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SIREN"] + #[inline(always)] + pub fn siren(&self) -> SIREN_R { + SIREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SIRLP"] + #[inline(always)] + pub fn sirlp(&self) -> SIRLP_R { + SIRLP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - TXE"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RXE"] + #[inline(always)] + pub fn rxe(&self) -> RXE_R { + RXE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DTR"] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RTS"] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - RTSEN"] + #[inline(always)] + pub fn rtsen(&self) -> RTSEN_R { + RTSEN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CTSEN"] + #[inline(always)] + pub fn ctsen(&self) -> CTSEN_R { + CTSEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UARTEN"] + #[inline(always)] + #[must_use] + pub fn uarten(&mut self) -> UARTEN_W<0> { + UARTEN_W::new(self) + } + #[doc = "Bit 1 - SIREN"] + #[inline(always)] + #[must_use] + pub fn siren(&mut self) -> SIREN_W<1> { + SIREN_W::new(self) + } + #[doc = "Bit 2 - SIRLP"] + #[inline(always)] + #[must_use] + pub fn sirlp(&mut self) -> SIRLP_W<2> { + SIRLP_W::new(self) + } + #[doc = "Bit 8 - TXE"] + #[inline(always)] + #[must_use] + pub fn txe(&mut self) -> TXE_W<8> { + TXE_W::new(self) + } + #[doc = "Bit 9 - RXE"] + #[inline(always)] + #[must_use] + pub fn rxe(&mut self) -> RXE_W<9> { + RXE_W::new(self) + } + #[doc = "Bit 10 - DTR"] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W<10> { + DTR_W::new(self) + } + #[doc = "Bit 11 - RTS"] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W<11> { + RTS_W::new(self) + } + #[doc = "Bit 14 - RTSEN"] + #[inline(always)] + #[must_use] + pub fn rtsen(&mut self) -> RTSEN_W<14> { + RTSEN_W::new(self) + } + #[doc = "Bit 15 - CTSEN"] + #[inline(always)] + #[must_use] + pub fn ctsen(&mut self) -> CTSEN_W<15> { + CTSEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +pub struct CR_SPEC; +impl crate::RegisterSpec for CR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cr::R](R) reader structure"] +impl crate::Readable for CR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +impl crate::Writable for CR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CR to value 0"] +impl crate::Resettable for CR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/dmacr.rs b/crates/bcm2837-lpa/src/uart0/dmacr.rs new file mode 100644 index 0000000..8bd3632 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/dmacr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DMACR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMACR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXDMAE` reader - RXDMAE"] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `RXDMAE` writer - RXDMAE"] +pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +#[doc = "Field `TXDMAE` reader - TXDMAE"] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `TXDMAE` writer - TXDMAE"] +pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +#[doc = "Field `DMAONERR` reader - DMAONERR"] +pub type DMAONERR_R = crate::BitReader; +#[doc = "Field `DMAONERR` writer - DMAONERR"] +pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - RXDMAE"] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - TXDMAE"] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMAONERR"] + #[inline(always)] + pub fn dmaonerr(&self) -> DMAONERR_R { + DMAONERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RXDMAE"] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + RXDMAE_W::new(self) + } + #[doc = "Bit 1 - TXDMAE"] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W<1> { + TXDMAE_W::new(self) + } + #[doc = "Bit 2 - DMAONERR"] + #[inline(always)] + #[must_use] + pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + DMAONERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"] +pub struct DMACR_SPEC; +impl crate::RegisterSpec for DMACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmacr::R](R) reader structure"] +impl crate::Readable for DMACR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +impl crate::Writable for DMACR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMACR to value 0"] +impl crate::Resettable for DMACR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/dr.rs b/crates/bcm2837-lpa/src/uart0/dr.rs new file mode 100644 index 0000000..236d30b --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/dr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - DATA"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - DATA"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>; +#[doc = "Field `FE` reader - FE"] +pub type FE_R = crate::BitReader; +#[doc = "Field `FE` writer - FE"] +pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `PE` reader - PE"] +pub type PE_R = crate::BitReader; +#[doc = "Field `PE` writer - PE"] +pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `BE` reader - BE"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - BE"] +pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +#[doc = "Field `OE` reader - OE"] +pub type OE_R = crate::BitReader; +#[doc = "Field `OE` writer - OE"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:7 - DATA"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - FE"] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PE"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - BE"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - OE"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - DATA"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Bit 8 - FE"] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W<8> { + FE_W::new(self) + } + #[doc = "Bit 9 - PE"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W<9> { + PE_W::new(self) + } + #[doc = "Bit 10 - BE"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W<10> { + BE_W::new(self) + } + #[doc = "Bit 11 - OE"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<11> { + OE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] +pub struct DR_SPEC; +impl crate::RegisterSpec for DR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dr::R](R) reader structure"] +impl crate::Readable for DR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] +impl crate::Writable for DR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DR to value 0"] +impl crate::Resettable for DR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/ecr.rs b/crates/bcm2837-lpa/src/uart0/ecr.rs new file mode 100644 index 0000000..f469e97 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/ecr.rs @@ -0,0 +1,76 @@ +#[doc = "Register `ECR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FE` writer - FE"] +pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `PE` writer - PE"] +pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `BE` writer - BE"] +pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +#[doc = "Field `OE` writer - OE"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - FE"] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W<0> { + FE_W::new(self) + } + #[doc = "Bit 1 - PE"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W<1> { + PE_W::new(self) + } + #[doc = "Bit 2 - BE"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W<2> { + BE_W::new(self) + } + #[doc = "Bit 3 - OE"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<3> { + OE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Error Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"] +impl crate::Writable for ECR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/fbrd.rs b/crates/bcm2837-lpa/src/uart0/fbrd.rs new file mode 100644 index 0000000..14ae9a3 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/fbrd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `FBRD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FBRD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDDIVFRAC` reader - BAUDDIVFRAC"] +pub type BAUDDIVFRAC_R = crate::FieldReader; +#[doc = "Field `BAUDDIVFRAC` writer - BAUDDIVFRAC"] +pub type BAUDDIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBRD_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - BAUDDIVFRAC"] + #[inline(always)] + pub fn bauddivfrac(&self) -> BAUDDIVFRAC_R { + BAUDDIVFRAC_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - BAUDDIVFRAC"] + #[inline(always)] + #[must_use] + pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W<0> { + BAUDDIVFRAC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbrd](index.html) module"] +pub struct FBRD_SPEC; +impl crate::RegisterSpec for FBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fbrd::R](R) reader structure"] +impl crate::Readable for FBRD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fbrd::W](W) writer structure"] +impl crate::Writable for FBRD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FBRD to value 0"] +impl crate::Resettable for FBRD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/fr.rs b/crates/bcm2837-lpa/src/uart0/fr.rs new file mode 100644 index 0000000..641becc --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/fr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `FR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - CTS"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `CTS` writer - CTS"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `DSR` reader - DSR"] +pub type DSR_R = crate::BitReader; +#[doc = "Field `DSR` writer - DSR"] +pub type DSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `DCD` reader - DCD"] +pub type DCD_R = crate::BitReader; +#[doc = "Field `DCD` writer - DCD"] +pub type DCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `BUSY` reader - BUSY"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `BUSY` writer - BUSY"] +pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RXFE` reader - RXFE"] +pub type RXFE_R = crate::BitReader; +#[doc = "Field `RXFE` writer - RXFE"] +pub type RXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `TXFF` reader - TXFF"] +pub type TXFF_R = crate::BitReader; +#[doc = "Field `TXFF` writer - TXFF"] +pub type TXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RXFF` reader - RXFF"] +pub type RXFF_R = crate::BitReader; +#[doc = "Field `RXFF` writer - RXFF"] +pub type RXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `TXFE` reader - TXFE"] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `TXFE` writer - TXFE"] +pub type TXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +#[doc = "Field `RI` reader - RI"] +pub type RI_R = crate::BitReader; +#[doc = "Field `RI` writer - RI"] +pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - CTS"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DSR"] + #[inline(always)] + pub fn dsr(&self) -> DSR_R { + DSR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCD"] + #[inline(always)] + pub fn dcd(&self) -> DCD_R { + DCD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BUSY"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXFE"] + #[inline(always)] + pub fn rxfe(&self) -> RXFE_R { + RXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXFF"] + #[inline(always)] + pub fn txff(&self) -> TXFF_R { + TXFF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RXFF"] + #[inline(always)] + pub fn rxff(&self) -> RXFF_R { + RXFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TXFE"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RI"] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CTS"] + #[inline(always)] + #[must_use] + pub fn cts(&mut self) -> CTS_W<0> { + CTS_W::new(self) + } + #[doc = "Bit 1 - DSR"] + #[inline(always)] + #[must_use] + pub fn dsr(&mut self) -> DSR_W<1> { + DSR_W::new(self) + } + #[doc = "Bit 2 - DCD"] + #[inline(always)] + #[must_use] + pub fn dcd(&mut self) -> DCD_W<2> { + DCD_W::new(self) + } + #[doc = "Bit 3 - BUSY"] + #[inline(always)] + #[must_use] + pub fn busy(&mut self) -> BUSY_W<3> { + BUSY_W::new(self) + } + #[doc = "Bit 4 - RXFE"] + #[inline(always)] + #[must_use] + pub fn rxfe(&mut self) -> RXFE_W<4> { + RXFE_W::new(self) + } + #[doc = "Bit 5 - TXFF"] + #[inline(always)] + #[must_use] + pub fn txff(&mut self) -> TXFF_W<5> { + TXFF_W::new(self) + } + #[doc = "Bit 6 - RXFF"] + #[inline(always)] + #[must_use] + pub fn rxff(&mut self) -> RXFF_W<6> { + RXFF_W::new(self) + } + #[doc = "Bit 7 - TXFE"] + #[inline(always)] + #[must_use] + pub fn txfe(&mut self) -> TXFE_W<7> { + TXFE_W::new(self) + } + #[doc = "Bit 8 - RI"] + #[inline(always)] + #[must_use] + pub fn ri(&mut self) -> RI_W<8> { + RI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +pub struct FR_SPEC; +impl crate::RegisterSpec for FR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fr::R](R) reader structure"] +impl crate::Readable for FR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] +impl crate::Writable for FR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FR to value 0"] +impl crate::Resettable for FR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/ibrd.rs b/crates/bcm2837-lpa/src/uart0/ibrd.rs new file mode 100644 index 0000000..65af80e --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/ibrd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IBRD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IBRD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUDDIVINT` reader - BAUDDIVINT"] +pub type BAUDDIVINT_R = crate::FieldReader; +#[doc = "Field `BAUDDIVINT` writer - BAUDDIVINT"] +pub type BAUDDIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IBRD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - BAUDDIVINT"] + #[inline(always)] + pub fn bauddivint(&self) -> BAUDDIVINT_R { + BAUDDIVINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - BAUDDIVINT"] + #[inline(always)] + #[must_use] + pub fn bauddivint(&mut self) -> BAUDDIVINT_W<0> { + BAUDDIVINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Integer Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ibrd](index.html) module"] +pub struct IBRD_SPEC; +impl crate::RegisterSpec for IBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ibrd::R](R) reader structure"] +impl crate::Readable for IBRD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ibrd::W](W) writer structure"] +impl crate::Writable for IBRD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IBRD to value 0"] +impl crate::Resettable for IBRD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/icr.rs b/crates/bcm2837-lpa/src/uart0/icr.rs new file mode 100644 index 0000000..509869e --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/icr.rs @@ -0,0 +1,132 @@ +#[doc = "Register `ICR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIMIC` writer - RIMIC"] +pub type RIMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `CTSMIC` writer - CTSMIC"] +pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `DCDMIC` writer - DCDMIC"] +pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `DSRMIC` writer - DSRMIC"] +pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `RXIC` writer - RXIC"] +pub type RXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `TXIC` writer - TXIC"] +pub type TXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `RTIC` writer - RTIC"] +pub type RTIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `FEIC` writer - FEIC"] +pub type FEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `PEIC` writer - PEIC"] +pub type PEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `BEIC` writer - BEIC"] +pub type BEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +#[doc = "Field `OEIC` writer - OEIC"] +pub type OEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - RIMIC"] + #[inline(always)] + #[must_use] + pub fn rimic(&mut self) -> RIMIC_W<0> { + RIMIC_W::new(self) + } + #[doc = "Bit 1 - CTSMIC"] + #[inline(always)] + #[must_use] + pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + CTSMIC_W::new(self) + } + #[doc = "Bit 2 - DCDMIC"] + #[inline(always)] + #[must_use] + pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + DCDMIC_W::new(self) + } + #[doc = "Bit 3 - DSRMIC"] + #[inline(always)] + #[must_use] + pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + DSRMIC_W::new(self) + } + #[doc = "Bit 4 - RXIC"] + #[inline(always)] + #[must_use] + pub fn rxic(&mut self) -> RXIC_W<4> { + RXIC_W::new(self) + } + #[doc = "Bit 5 - TXIC"] + #[inline(always)] + #[must_use] + pub fn txic(&mut self) -> TXIC_W<5> { + TXIC_W::new(self) + } + #[doc = "Bit 6 - RTIC"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W<6> { + RTIC_W::new(self) + } + #[doc = "Bit 7 - FEIC"] + #[inline(always)] + #[must_use] + pub fn feic(&mut self) -> FEIC_W<7> { + FEIC_W::new(self) + } + #[doc = "Bit 8 - PEIC"] + #[inline(always)] + #[must_use] + pub fn peic(&mut self) -> PEIC_W<8> { + PEIC_W::new(self) + } + #[doc = "Bit 9 - BEIC"] + #[inline(always)] + #[must_use] + pub fn beic(&mut self) -> BEIC_W<9> { + BEIC_W::new(self) + } + #[doc = "Bit 10 - OEIC"] + #[inline(always)] + #[must_use] + pub fn oeic(&mut self) -> OEIC_W<10> { + OEIC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +pub struct ICR_SPEC; +impl crate::RegisterSpec for ICR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +impl crate::Writable for ICR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for ICR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/ifls.rs b/crates/bcm2837-lpa/src/uart0/ifls.rs new file mode 100644 index 0000000..0cfe8d5 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/ifls.rs @@ -0,0 +1,95 @@ +#[doc = "Register `IFLS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IFLS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXIFLSEL` reader - TXIFLSEL"] +pub type TXIFLSEL_R = crate::FieldReader; +#[doc = "Field `TXIFLSEL` writer - TXIFLSEL"] +pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +#[doc = "Field `RXIFLSEL` reader - RXIFLSEL"] +pub type RXIFLSEL_R = crate::FieldReader; +#[doc = "Field `RXIFLSEL` writer - RXIFLSEL"] +pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - TXIFLSEL"] + #[inline(always)] + pub fn txiflsel(&self) -> TXIFLSEL_R { + TXIFLSEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - RXIFLSEL"] + #[inline(always)] + pub fn rxiflsel(&self) -> RXIFLSEL_R { + RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - TXIFLSEL"] + #[inline(always)] + #[must_use] + pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + TXIFLSEL_W::new(self) + } + #[doc = "Bits 3:5 - RXIFLSEL"] + #[inline(always)] + #[must_use] + pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + RXIFLSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifls](index.html) module"] +pub struct IFLS_SPEC; +impl crate::RegisterSpec for IFLS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ifls::R](R) reader structure"] +impl crate::Readable for IFLS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ifls::W](W) writer structure"] +impl crate::Writable for IFLS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IFLS to value 0"] +impl crate::Resettable for IFLS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/imsc.rs b/crates/bcm2837-lpa/src/uart0/imsc.rs new file mode 100644 index 0000000..1b0fb46 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/imsc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `IMSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IMSC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIMIM` reader - RIMIM"] +pub type RIMIM_R = crate::BitReader; +#[doc = "Field `RIMIM` writer - RIMIM"] +pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `CTSMIM` reader - CTSMIM"] +pub type CTSMIM_R = crate::BitReader; +#[doc = "Field `CTSMIM` writer - CTSMIM"] +pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `DCDMIM` reader - DCDMIM"] +pub type DCDMIM_R = crate::BitReader; +#[doc = "Field `DCDMIM` writer - DCDMIM"] +pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `DSRMIM` reader - DSRMIM"] +pub type DSRMIM_R = crate::BitReader; +#[doc = "Field `DSRMIM` writer - DSRMIM"] +pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `RXIM` reader - RXIM"] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `RXIM` writer - RXIM"] +pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `TXIM` reader - TXIM"] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `TXIM` writer - TXIM"] +pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `RTIM` reader - RTIM"] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `RTIM` writer - RTIM"] +pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `FEIM` reader - FEIM"] +pub type FEIM_R = crate::BitReader; +#[doc = "Field `FEIM` writer - FEIM"] +pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `PEIM` reader - PEIM"] +pub type PEIM_R = crate::BitReader; +#[doc = "Field `PEIM` writer - PEIM"] +pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `BEIM` reader - BEIM"] +pub type BEIM_R = crate::BitReader; +#[doc = "Field `BEIM` writer - BEIM"] +pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +#[doc = "Field `OEIM` reader - OEIM"] +pub type OEIM_R = crate::BitReader; +#[doc = "Field `OEIM` writer - OEIM"] +pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - RIMIM"] + #[inline(always)] + pub fn rimim(&self) -> RIMIM_R { + RIMIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSMIM"] + #[inline(always)] + pub fn ctsmim(&self) -> CTSMIM_R { + CTSMIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDMIM"] + #[inline(always)] + pub fn dcdmim(&self) -> DCDMIM_R { + DCDMIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRMIM"] + #[inline(always)] + pub fn dsrmim(&self) -> DSRMIM_R { + DSRMIM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXIM"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXIM"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTIM"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FEIM"] + #[inline(always)] + pub fn feim(&self) -> FEIM_R { + FEIM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PEIM"] + #[inline(always)] + pub fn peim(&self) -> PEIM_R { + PEIM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BEIM"] + #[inline(always)] + pub fn beim(&self) -> BEIM_R { + BEIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OEIM"] + #[inline(always)] + pub fn oeim(&self) -> OEIM_R { + OEIM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RIMIM"] + #[inline(always)] + #[must_use] + pub fn rimim(&mut self) -> RIMIM_W<0> { + RIMIM_W::new(self) + } + #[doc = "Bit 1 - CTSMIM"] + #[inline(always)] + #[must_use] + pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + CTSMIM_W::new(self) + } + #[doc = "Bit 2 - DCDMIM"] + #[inline(always)] + #[must_use] + pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + DCDMIM_W::new(self) + } + #[doc = "Bit 3 - DSRMIM"] + #[inline(always)] + #[must_use] + pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + DSRMIM_W::new(self) + } + #[doc = "Bit 4 - RXIM"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W<4> { + RXIM_W::new(self) + } + #[doc = "Bit 5 - TXIM"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W<5> { + TXIM_W::new(self) + } + #[doc = "Bit 6 - RTIM"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W<6> { + RTIM_W::new(self) + } + #[doc = "Bit 7 - FEIM"] + #[inline(always)] + #[must_use] + pub fn feim(&mut self) -> FEIM_W<7> { + FEIM_W::new(self) + } + #[doc = "Bit 8 - PEIM"] + #[inline(always)] + #[must_use] + pub fn peim(&mut self) -> PEIM_W<8> { + PEIM_W::new(self) + } + #[doc = "Bit 9 - BEIM"] + #[inline(always)] + #[must_use] + pub fn beim(&mut self) -> BEIM_W<9> { + BEIM_W::new(self) + } + #[doc = "Bit 10 - OEIM"] + #[inline(always)] + #[must_use] + pub fn oeim(&mut self) -> OEIM_W<10> { + OEIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Mask set_Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"] +pub struct IMSC_SPEC; +impl crate::RegisterSpec for IMSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [imsc::R](R) reader structure"] +impl crate::Readable for IMSC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"] +impl crate::Writable for IMSC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMSC to value 0"] +impl crate::Resettable for IMSC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/lcr_h.rs b/crates/bcm2837-lpa/src/uart0/lcr_h.rs new file mode 100644 index 0000000..6e02317 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/lcr_h.rs @@ -0,0 +1,170 @@ +#[doc = "Register `LCR_H` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LCR_H` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BRK` reader - BRK"] +pub type BRK_R = crate::BitReader; +#[doc = "Field `BRK` writer - BRK"] +pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `PEN` reader - PEN"] +pub type PEN_R = crate::BitReader; +#[doc = "Field `PEN` writer - PEN"] +pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `EPS` reader - EPS"] +pub type EPS_R = crate::BitReader; +#[doc = "Field `EPS` writer - EPS"] +pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `STP2` reader - STP2"] +pub type STP2_R = crate::BitReader; +#[doc = "Field `STP2` writer - STP2"] +pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `FEN` reader - FEN"] +pub type FEN_R = crate::BitReader; +#[doc = "Field `FEN` writer - FEN"] +pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +#[doc = "Field `WLEN` reader - WLEN"] +pub type WLEN_R = crate::FieldReader; +#[doc = "Field `WLEN` writer - WLEN"] +pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_H_SPEC, u8, u8, 2, O>; +#[doc = "Field `SPS` reader - SPS"] +pub type SPS_R = crate::BitReader; +#[doc = "Field `SPS` writer - SPS"] +pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - BRK"] + #[inline(always)] + pub fn brk(&self) -> BRK_R { + BRK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PEN"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - EPS"] + #[inline(always)] + pub fn eps(&self) -> EPS_R { + EPS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STP2"] + #[inline(always)] + pub fn stp2(&self) -> STP2_R { + STP2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - FEN"] + #[inline(always)] + pub fn fen(&self) -> FEN_R { + FEN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - WLEN"] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - SPS"] + #[inline(always)] + pub fn sps(&self) -> SPS_R { + SPS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - BRK"] + #[inline(always)] + #[must_use] + pub fn brk(&mut self) -> BRK_W<0> { + BRK_W::new(self) + } + #[doc = "Bit 1 - PEN"] + #[inline(always)] + #[must_use] + pub fn pen(&mut self) -> PEN_W<1> { + PEN_W::new(self) + } + #[doc = "Bit 2 - EPS"] + #[inline(always)] + #[must_use] + pub fn eps(&mut self) -> EPS_W<2> { + EPS_W::new(self) + } + #[doc = "Bit 3 - STP2"] + #[inline(always)] + #[must_use] + pub fn stp2(&mut self) -> STP2_W<3> { + STP2_W::new(self) + } + #[doc = "Bit 4 - FEN"] + #[inline(always)] + #[must_use] + pub fn fen(&mut self) -> FEN_W<4> { + FEN_W::new(self) + } + #[doc = "Bits 5:6 - WLEN"] + #[inline(always)] + #[must_use] + pub fn wlen(&mut self) -> WLEN_W<5> { + WLEN_W::new(self) + } + #[doc = "Bit 7 - SPS"] + #[inline(always)] + #[must_use] + pub fn sps(&mut self) -> SPS_W<7> { + SPS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_h](index.html) module"] +pub struct LCR_H_SPEC; +impl crate::RegisterSpec for LCR_H_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lcr_h::R](R) reader structure"] +impl crate::Readable for LCR_H_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lcr_h::W](W) writer structure"] +impl crate::Writable for LCR_H_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCR_H to value 0"] +impl crate::Resettable for LCR_H_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/mis.rs b/crates/bcm2837-lpa/src/uart0/mis.rs new file mode 100644 index 0000000..ce802e5 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/mis.rs @@ -0,0 +1,107 @@ +#[doc = "Register `MIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RIMMIS` reader - RIMMIS"] +pub type RIMMIS_R = crate::BitReader; +#[doc = "Field `CTSMMIS` reader - CTSMMIS"] +pub type CTSMMIS_R = crate::BitReader; +#[doc = "Field `DCDMMIS` reader - DCDMMIS"] +pub type DCDMMIS_R = crate::BitReader; +#[doc = "Field `DSRMMIS` reader - DSRMMIS"] +pub type DSRMMIS_R = crate::BitReader; +#[doc = "Field `RXMIS` reader - RXMIS"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `TXMIS` reader - TXMIS"] +pub type TXMIS_R = crate::BitReader; +#[doc = "Field `RTMIS` reader - RTMIS"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `FEMIS` reader - FEMIS"] +pub type FEMIS_R = crate::BitReader; +#[doc = "Field `PEMIS` reader - PEMIS"] +pub type PEMIS_R = crate::BitReader; +#[doc = "Field `BEMIS` reader - BEMIS"] +pub type BEMIS_R = crate::BitReader; +#[doc = "Field `OEMIS` reader - OEMIS"] +pub type OEMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RIMMIS"] + #[inline(always)] + pub fn rimmis(&self) -> RIMMIS_R { + RIMMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSMMIS"] + #[inline(always)] + pub fn ctsmmis(&self) -> CTSMMIS_R { + CTSMMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDMMIS"] + #[inline(always)] + pub fn dcdmmis(&self) -> DCDMMIS_R { + DCDMMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRMMIS"] + #[inline(always)] + pub fn dsrmmis(&self) -> DSRMMIS_R { + DSRMMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXMIS"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXMIS"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTMIS"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FEMIS"] + #[inline(always)] + pub fn femis(&self) -> FEMIS_R { + FEMIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PEMIS"] + #[inline(always)] + pub fn pemis(&self) -> PEMIS_R { + PEMIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BEMIS"] + #[inline(always)] + pub fn bemis(&self) -> BEMIS_R { + BEMIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OEMIS"] + #[inline(always)] + pub fn oemis(&self) -> OEMIS_R { + OEMIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Masked Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"] +pub struct MIS_SPEC; +impl crate::RegisterSpec for MIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mis::R](R) reader structure"] +impl crate::Readable for MIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MIS to value 0"] +impl crate::Resettable for MIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/ris.rs b/crates/bcm2837-lpa/src/uart0/ris.rs new file mode 100644 index 0000000..0ab6b9d --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/ris.rs @@ -0,0 +1,107 @@ +#[doc = "Register `RIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RIRMIS` reader - RIRMIS"] +pub type RIRMIS_R = crate::BitReader; +#[doc = "Field `CTSRMIS` reader - CTSRMIS"] +pub type CTSRMIS_R = crate::BitReader; +#[doc = "Field `DCDRMIS` reader - DCDRMIS"] +pub type DCDRMIS_R = crate::BitReader; +#[doc = "Field `DSRRMIS` reader - DSRRMIS"] +pub type DSRRMIS_R = crate::BitReader; +#[doc = "Field `RXRIS` reader - RXRIS"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `TXRIS` reader - TXRIS"] +pub type TXRIS_R = crate::BitReader; +#[doc = "Field `RTRIS` reader - RTRIS"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `FERIS` reader - FERIS"] +pub type FERIS_R = crate::BitReader; +#[doc = "Field `PERIS` reader - PERIS"] +pub type PERIS_R = crate::BitReader; +#[doc = "Field `BERIS` reader - BERIS"] +pub type BERIS_R = crate::BitReader; +#[doc = "Field `OERIS` reader - OERIS"] +pub type OERIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - RIRMIS"] + #[inline(always)] + pub fn rirmis(&self) -> RIRMIS_R { + RIRMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CTSRMIS"] + #[inline(always)] + pub fn ctsrmis(&self) -> CTSRMIS_R { + CTSRMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DCDRMIS"] + #[inline(always)] + pub fn dcdrmis(&self) -> DCDRMIS_R { + DCDRMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DSRRMIS"] + #[inline(always)] + pub fn dsrrmis(&self) -> DSRRMIS_R { + DSRRMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RXRIS"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TXRIS"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTRIS"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - FERIS"] + #[inline(always)] + pub fn feris(&self) -> FERIS_R { + FERIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - PERIS"] + #[inline(always)] + pub fn peris(&self) -> PERIS_R { + PERIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BERIS"] + #[inline(always)] + pub fn beris(&self) -> BERIS_R { + BERIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - OERIS"] + #[inline(always)] + pub fn oeris(&self) -> OERIS_R { + OERIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](index.html) module"] +pub struct RIS_SPEC; +impl crate::RegisterSpec for RIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ris::R](R) reader structure"] +impl crate::Readable for RIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RIS to value 0"] +impl crate::Resettable for RIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart0/rsr.rs b/crates/bcm2837-lpa/src/uart0/rsr.rs new file mode 100644 index 0000000..90a9e0d --- /dev/null +++ b/crates/bcm2837-lpa/src/uart0/rsr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `RSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FE` reader - FE"] +pub type FE_R = crate::BitReader; +#[doc = "Field `PE` reader - PE"] +pub type PE_R = crate::BitReader; +#[doc = "Field `BE` reader - BE"] +pub type BE_R = crate::BitReader; +#[doc = "Field `OE` reader - OE"] +pub type OE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - FE"] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PE"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BE"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - OE"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +pub struct RSR_SPEC; +impl crate::RegisterSpec for RSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rsr::R](R) reader structure"] +impl crate::Readable for RSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RSR to value 0"] +impl crate::Resettable for RSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1.rs b/crates/bcm2837-lpa/src/uart1.rs new file mode 100644 index 0000000..a87a1e5 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_io: [u8; 0x04], + _reserved_1_ier: [u8; 0x04], + #[doc = "0x08 - Interrupt Identify"] + pub iir: IIR, + #[doc = "0x0c - Line control"] + pub lcr: LCR, + #[doc = "0x10 - Modem Control"] + pub mcr: MCR, + #[doc = "0x14 - Line Status"] + pub lsr: LSR, + #[doc = "0x18 - Modem Status"] + pub msr: MSR, + #[doc = "0x1c - Scratch"] + pub scratch: SCRATCH, + _reserved8: [u8; 0x03], + #[doc = "0x20 - Control"] + pub cntl: CNTL, + #[doc = "0x24 - Status"] + pub stat: STAT, + #[doc = "0x28 - Baudrate"] + pub baud: BAUD, +} +impl RegisterBlock { + #[doc = "0x00 - Lower bits of baudrate when DLAB is set"] + #[inline(always)] + pub const fn baudl(&self) -> &BAUDL { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00 - I/O Data"] + #[inline(always)] + pub const fn io(&self) -> &IO { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x04 - High bits of baudrate when DLAB is set"] + #[inline(always)] + pub const fn baudh(&self) -> &BAUDH { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } + #[doc = "0x04 - Interrupt Enable"] + #[inline(always)] + pub const fn ier(&self) -> &IER { + unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + } +} +#[doc = "IO (rw) register accessor: an alias for `Reg`"] +pub type IO = crate::Reg; +#[doc = "I/O Data"] +pub mod io; +#[doc = "BAUDL (rw) register accessor: an alias for `Reg`"] +pub type BAUDL = crate::Reg; +#[doc = "Lower bits of baudrate when DLAB is set"] +pub mod baudl; +#[doc = "IER (rw) register accessor: an alias for `Reg`"] +pub type IER = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ier; +#[doc = "BAUDH (rw) register accessor: an alias for `Reg`"] +pub type BAUDH = crate::Reg; +#[doc = "High bits of baudrate when DLAB is set"] +pub mod baudh; +#[doc = "IIR (rw) register accessor: an alias for `Reg`"] +pub type IIR = crate::Reg; +#[doc = "Interrupt Identify"] +pub mod iir; +#[doc = "LCR (rw) register accessor: an alias for `Reg`"] +pub type LCR = crate::Reg; +#[doc = "Line control"] +pub mod lcr; +#[doc = "MCR (rw) register accessor: an alias for `Reg`"] +pub type MCR = crate::Reg; +#[doc = "Modem Control"] +pub mod mcr; +#[doc = "LSR (rw) register accessor: an alias for `Reg`"] +pub type LSR = crate::Reg; +#[doc = "Line Status"] +pub mod lsr; +#[doc = "MSR (rw) register accessor: an alias for `Reg`"] +pub type MSR = crate::Reg; +#[doc = "Modem Status"] +pub mod msr; +#[doc = "SCRATCH (rw) register accessor: an alias for `Reg`"] +pub type SCRATCH = crate::Reg; +#[doc = "Scratch"] +pub mod scratch; +#[doc = "CNTL (rw) register accessor: an alias for `Reg`"] +pub type CNTL = crate::Reg; +#[doc = "Control"] +pub mod cntl; +#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Status"] +pub mod stat; +#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "Baudrate"] +pub mod baud; diff --git a/crates/bcm2837-lpa/src/uart1/baud.rs b/crates/bcm2837-lpa/src/uart1/baud.rs new file mode 100644 index 0000000..088c774 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/baud.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Baudrate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/baudh.rs b/crates/bcm2837-lpa/src/uart1/baudh.rs new file mode 100644 index 0000000..8c30695 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/baudh.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUDH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "High bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudh](index.html) module"] +pub struct BAUDH_SPEC; +impl crate::RegisterSpec for BAUDH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baudh::R](R) reader structure"] +impl crate::Readable for BAUDH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudh::W](W) writer structure"] +impl crate::Writable for BAUDH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUDH to value 0"] +impl crate::Resettable for BAUDH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/baudl.rs b/crates/bcm2837-lpa/src/uart1/baudl.rs new file mode 100644 index 0000000..ca7c9f0 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/baudl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BAUDL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUDL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lower bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudl](index.html) module"] +pub struct BAUDL_SPEC; +impl crate::RegisterSpec for BAUDL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baudl::R](R) reader structure"] +impl crate::Readable for BAUDL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baudl::W](W) writer structure"] +impl crate::Writable for BAUDL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUDL to value 0"] +impl crate::Resettable for BAUDL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/cntl.rs b/crates/bcm2837-lpa/src/uart1/cntl.rs new file mode 100644 index 0000000..4125093 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/cntl.rs @@ -0,0 +1,291 @@ +#[doc = "Register `CNTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RX_ENABLE` reader - Enable receive"] +pub type RX_ENABLE_R = crate::BitReader; +#[doc = "Field `RX_ENABLE` writer - Enable receive"] +pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `TX_ENABLE` reader - Enable transmit"] +pub type TX_ENABLE_R = crate::BitReader; +#[doc = "Field `TX_ENABLE` writer - Enable transmit"] +pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `RTS_ENABLE` reader - Enable auto receive flow control with RTS"] +pub type RTS_ENABLE_R = crate::BitReader; +#[doc = "Field `RTS_ENABLE` writer - Enable auto receive flow control with RTS"] +pub type RTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `CTS_ENABLE` reader - Enable auto transmit flow control with CTS"] +pub type CTS_ENABLE_R = crate::BitReader; +#[doc = "Field `CTS_ENABLE` writer - Enable auto transmit flow control with CTS"] +pub type CTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +#[doc = "Field `RTS_FIFO_LEVEL` reader - FIFO level to de-assert RTS"] +pub type RTS_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "FIFO level to de-assert RTS\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FIFO_LEVEL_A { + #[doc = "0: 3 empty spaces"] + _3EMPTY = 0, + #[doc = "1: 2 empty spaces"] + _2EMPTY = 1, + #[doc = "2: 1 empty spaces"] + _1EMPTY = 2, + #[doc = "3: 4 empty spaces"] + _4EMPTY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FIFO_LEVEL_A) -> Self { + variant as _ + } +} +impl RTS_FIFO_LEVEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FIFO_LEVEL_A { + match self.bits { + 0 => FIFO_LEVEL_A::_3EMPTY, + 1 => FIFO_LEVEL_A::_2EMPTY, + 2 => FIFO_LEVEL_A::_1EMPTY, + 3 => FIFO_LEVEL_A::_4EMPTY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_3EMPTY`"] + #[inline(always)] + pub fn is_3empty(&self) -> bool { + *self == FIFO_LEVEL_A::_3EMPTY + } + #[doc = "Checks if the value of the field is `_2EMPTY`"] + #[inline(always)] + pub fn is_2empty(&self) -> bool { + *self == FIFO_LEVEL_A::_2EMPTY + } + #[doc = "Checks if the value of the field is `_1EMPTY`"] + #[inline(always)] + pub fn is_1empty(&self) -> bool { + *self == FIFO_LEVEL_A::_1EMPTY + } + #[doc = "Checks if the value of the field is `_4EMPTY`"] + #[inline(always)] + pub fn is_4empty(&self) -> bool { + *self == FIFO_LEVEL_A::_4EMPTY + } +} +#[doc = "Field `RTS_FIFO_LEVEL` writer - FIFO level to de-assert RTS"] +pub type RTS_FIFO_LEVEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CNTL_SPEC, u8, FIFO_LEVEL_A, 2, O>; +impl<'a, const O: u8> RTS_FIFO_LEVEL_W<'a, O> { + #[doc = "3 empty spaces"] + #[inline(always)] + pub fn _3empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_3EMPTY) + } + #[doc = "2 empty spaces"] + #[inline(always)] + pub fn _2empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_2EMPTY) + } + #[doc = "1 empty spaces"] + #[inline(always)] + pub fn _1empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_1EMPTY) + } + #[doc = "4 empty spaces"] + #[inline(always)] + pub fn _4empty(self) -> &'a mut W { + self.variant(FIFO_LEVEL_A::_4EMPTY) + } +} +#[doc = "Field `RTS_ASSERT` reader - RTS assert level"] +pub use CTS_ASSERT_R as RTS_ASSERT_R; +#[doc = "Field `RTS_ASSERT` writer - RTS assert level"] +pub use CTS_ASSERT_W as RTS_ASSERT_W; +#[doc = "Field `CTS_ASSERT` reader - CTS assert level"] +pub type CTS_ASSERT_R = crate::BitReader; +#[doc = "CTS assert level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ASSERT_LEVEL_A { + #[doc = "0: Assert high"] + HIGH = 0, + #[doc = "1: Assert low"] + LOW = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ASSERT_LEVEL_A) -> Self { + variant as u8 != 0 + } +} +impl CTS_ASSERT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ASSERT_LEVEL_A { + match self.bits { + false => ASSERT_LEVEL_A::HIGH, + true => ASSERT_LEVEL_A::LOW, + } + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == ASSERT_LEVEL_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == ASSERT_LEVEL_A::LOW + } +} +#[doc = "Field `CTS_ASSERT` writer - CTS assert level"] +pub type CTS_ASSERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, ASSERT_LEVEL_A, O>; +impl<'a, const O: u8> CTS_ASSERT_W<'a, O> { + #[doc = "Assert high"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(ASSERT_LEVEL_A::HIGH) + } + #[doc = "Assert low"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(ASSERT_LEVEL_A::LOW) + } +} +impl R { + #[doc = "Bit 0 - Enable receive"] + #[inline(always)] + pub fn rx_enable(&self) -> RX_ENABLE_R { + RX_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable transmit"] + #[inline(always)] + pub fn tx_enable(&self) -> TX_ENABLE_R { + TX_ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable auto receive flow control with RTS"] + #[inline(always)] + pub fn rts_enable(&self) -> RTS_ENABLE_R { + RTS_ENABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] + #[inline(always)] + pub fn cts_enable(&self) -> CTS_ENABLE_R { + CTS_ENABLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] + #[inline(always)] + pub fn rts_fifo_level(&self) -> RTS_FIFO_LEVEL_R { + RTS_FIFO_LEVEL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - RTS assert level"] + #[inline(always)] + pub fn rts_assert(&self) -> RTS_ASSERT_R { + RTS_ASSERT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS assert level"] + #[inline(always)] + pub fn cts_assert(&self) -> CTS_ASSERT_R { + CTS_ASSERT_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable receive"] + #[inline(always)] + #[must_use] + pub fn rx_enable(&mut self) -> RX_ENABLE_W<0> { + RX_ENABLE_W::new(self) + } + #[doc = "Bit 1 - Enable transmit"] + #[inline(always)] + #[must_use] + pub fn tx_enable(&mut self) -> TX_ENABLE_W<1> { + TX_ENABLE_W::new(self) + } + #[doc = "Bit 2 - Enable auto receive flow control with RTS"] + #[inline(always)] + #[must_use] + pub fn rts_enable(&mut self) -> RTS_ENABLE_W<2> { + RTS_ENABLE_W::new(self) + } + #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] + #[inline(always)] + #[must_use] + pub fn cts_enable(&mut self) -> CTS_ENABLE_W<3> { + CTS_ENABLE_W::new(self) + } + #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] + #[inline(always)] + #[must_use] + pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W<4> { + RTS_FIFO_LEVEL_W::new(self) + } + #[doc = "Bit 6 - RTS assert level"] + #[inline(always)] + #[must_use] + pub fn rts_assert(&mut self) -> RTS_ASSERT_W<6> { + RTS_ASSERT_W::new(self) + } + #[doc = "Bit 7 - CTS assert level"] + #[inline(always)] + #[must_use] + pub fn cts_assert(&mut self) -> CTS_ASSERT_W<7> { + CTS_ASSERT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] +pub struct CNTL_SPEC; +impl crate::RegisterSpec for CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cntl::R](R) reader structure"] +impl crate::Readable for CNTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] +impl crate::Writable for CNTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL to value 0"] +impl crate::Resettable for CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/ier.rs b/crates/bcm2837-lpa/src/uart1/ier.rs new file mode 100644 index 0000000..450afd5 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/ier.rs @@ -0,0 +1,95 @@ +#[doc = "Register `IER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO is empty"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Transmit FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<1> { + TX_READY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +pub struct IER_SPEC; +impl crate::RegisterSpec for IER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ier::R](R) reader structure"] +impl crate::Readable for IER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +impl crate::Writable for IER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/iir.rs b/crates/bcm2837-lpa/src/uart1/iir.rs new file mode 100644 index 0000000..6f66eac --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/iir.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `nPENDING` reader - No pending interrupt"] +pub type N_PENDING_R = crate::BitReader; +#[doc = "Field `nPENDING` writer - No pending interrupt"] +pub type N_PENDING_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - No pending interrupt"] + #[inline(always)] + pub fn n_pending(&self) -> N_PENDING_R { + N_PENDING_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO is empty"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - No pending interrupt"] + #[inline(always)] + #[must_use] + pub fn n_pending(&mut self) -> N_PENDING_W<0> { + N_PENDING_W::new(self) + } + #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<1> { + DATA_READY_W::new(self) + } + #[doc = "Bit 2 - Transmit FIFO is empty"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<2> { + TX_READY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Identify\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iir](index.html) module"] +pub struct IIR_SPEC; +impl crate::RegisterSpec for IIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [iir::R](R) reader structure"] +impl crate::Readable for IIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [iir::W](W) writer structure"] +impl crate::Writable for IIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IIR to value 0xb001"] +impl crate::Resettable for IIR_SPEC { + const RESET_VALUE: Self::Ux = 0xb001; +} diff --git a/crates/bcm2837-lpa/src/uart1/io.rs b/crates/bcm2837-lpa/src/uart1/io.rs new file mode 100644 index 0000000..84cd075 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/io.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - FIFO access"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - FIFO access"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - FIFO access"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - FIFO access"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I/O Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +pub struct IO_SPEC; +impl crate::RegisterSpec for IO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [io::R](R) reader structure"] +impl crate::Readable for IO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +impl crate::Writable for IO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IO to value 0"] +impl crate::Resettable for IO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/lcr.rs b/crates/bcm2837-lpa/src/uart1/lcr.rs new file mode 100644 index 0000000..16b3c2b --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/lcr.rs @@ -0,0 +1,158 @@ +#[doc = "Register `LCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_SIZE` reader - UART word size"] +pub type DATA_SIZE_R = crate::FieldReader; +#[doc = "UART word size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: 7 bit"] + _7BIT = 0, + #[doc = "3: 8 bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::_7BIT), + 3 => Some(MODE_A::_8BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_7BIT`"] + #[inline(always)] + pub fn is_7bit(&self) -> bool { + *self == MODE_A::_7BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == MODE_A::_8BIT + } +} +#[doc = "Field `DATA_SIZE` writer - UART word size"] +pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_SPEC, u8, MODE_A, 2, O>; +impl<'a, const O: u8> DATA_SIZE_W<'a, O> { + #[doc = "7 bit"] + #[inline(always)] + pub fn _7bit(self) -> &'a mut W { + self.variant(MODE_A::_7BIT) + } + #[doc = "8 bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(MODE_A::_8BIT) + } +} +#[doc = "Field `BREAK` reader - Pull TX low continuously to send break"] +pub type BREAK_R = crate::BitReader; +#[doc = "Field `BREAK` writer - Pull TX low continuously to send break"] +pub type BREAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +#[doc = "Field `DLAB` reader - First two registers are baudrate"] +pub type DLAB_R = crate::BitReader; +#[doc = "Field `DLAB` writer - First two registers are baudrate"] +pub type DLAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - UART word size"] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 6 - Pull TX low continuously to send break"] + #[inline(always)] + pub fn break_(&self) -> BREAK_R { + BREAK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - First two registers are baudrate"] + #[inline(always)] + pub fn dlab(&self) -> DLAB_R { + DLAB_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - UART word size"] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W<0> { + DATA_SIZE_W::new(self) + } + #[doc = "Bit 6 - Pull TX low continuously to send break"] + #[inline(always)] + #[must_use] + pub fn break_(&mut self) -> BREAK_W<6> { + BREAK_W::new(self) + } + #[doc = "Bit 7 - First two registers are baudrate"] + #[inline(always)] + #[must_use] + pub fn dlab(&mut self) -> DLAB_W<7> { + DLAB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](index.html) module"] +pub struct LCR_SPEC; +impl crate::RegisterSpec for LCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lcr::R](R) reader structure"] +impl crate::Readable for LCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lcr::W](W) writer structure"] +impl crate::Writable for LCR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCR to value 0"] +impl crate::Resettable for LCR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/lsr.rs b/crates/bcm2837-lpa/src/uart1/lsr.rs new file mode 100644 index 0000000..ba34ba7 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/lsr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `LSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least one byte"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least one byte"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] +pub type RX_OVERRUN_R = crate::BitReader; +#[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] +pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - Transmit FIFO has room for at least one byte"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - Transmit FIFO has room for at least one byte"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +#[doc = "Field `TX_IDLE` reader - Transmit FIFO empty and all bits shifted out"] +pub type TX_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IDLE` writer - Transmit FIFO empty and all bits shifted out"] +pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least one byte"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive FIFO overrun"] + #[inline(always)] + pub fn rx_overrun(&self) -> RX_OVERRUN_R { + RX_OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least one byte"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Receive FIFO overrun"] + #[inline(always)] + #[must_use] + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<1> { + RX_OVERRUN_W::new(self) + } + #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<5> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] + #[inline(always)] + #[must_use] + pub fn tx_idle(&mut self) -> TX_IDLE_W<6> { + TX_IDLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Line Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +pub struct LSR_SPEC; +impl crate::RegisterSpec for LSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lsr::R](R) reader structure"] +impl crate::Readable for LSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +impl crate::Writable for LSR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LSR to value 0"] +impl crate::Resettable for LSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/mcr.rs b/crates/bcm2837-lpa/src/uart1/mcr.rs new file mode 100644 index 0000000..89de0a8 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/mcr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RTS` reader - RTS is low"] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - RTS is low"] +pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - RTS is low"] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - RTS is low"] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W<1> { + RTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Modem Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"] +pub struct MCR_SPEC; +impl crate::RegisterSpec for MCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcr::R](R) reader structure"] +impl crate::Readable for MCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"] +impl crate::Writable for MCR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for MCR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/msr.rs b/crates/bcm2837-lpa/src/uart1/msr.rs new file mode 100644 index 0000000..3960539 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/msr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `MSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTS` reader - CTS is low"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `CTS` writer - CTS is low"] +pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSR_SPEC, bool, O>; +impl R { + #[doc = "Bit 4 - CTS is low"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - CTS is low"] + #[inline(always)] + #[must_use] + pub fn cts(&mut self) -> CTS_W<4> { + CTS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Modem Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](index.html) module"] +pub struct MSR_SPEC; +impl crate::RegisterSpec for MSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [msr::R](R) reader structure"] +impl crate::Readable for MSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [msr::W](W) writer structure"] +impl crate::Writable for MSR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MSR to value 0"] +impl crate::Resettable for MSR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/scratch.rs b/crates/bcm2837-lpa/src/uart1/scratch.rs new file mode 100644 index 0000000..c85f068 --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/scratch.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCRATCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCRATCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scratch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch](index.html) module"] +pub struct SCRATCH_SPEC; +impl crate::RegisterSpec for SCRATCH_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scratch::R](R) reader structure"] +impl crate::Readable for SCRATCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scratch::W](W) writer structure"] +impl crate::Writable for SCRATCH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCRATCH to value 0"] +impl crate::Resettable for SCRATCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/uart1/stat.rs b/crates/bcm2837-lpa/src/uart1/stat.rs new file mode 100644 index 0000000..114015e --- /dev/null +++ b/crates/bcm2837-lpa/src/uart1/stat.rs @@ -0,0 +1,245 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA_READY` reader - Receive FIFO has at least one symbol"] +pub type DATA_READY_R = crate::BitReader; +#[doc = "Field `DATA_READY` writer - Receive FIFO has at least one symbol"] +pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_READY` reader - Transmit FIFO has space for at least one symbol"] +pub type TX_READY_R = crate::BitReader; +#[doc = "Field `TX_READY` writer - Transmit FIFO has space for at least one symbol"] +pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_IDLE` reader - Receiver is idle"] +pub type RX_IDLE_R = crate::BitReader; +#[doc = "Field `RX_IDLE` writer - Receiver is idle"] +pub type RX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_IDLE` reader - Transmitter is idle"] +pub type TX_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IDLE` writer - Transmitter is idle"] +pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] +pub type RX_OVERRUN_R = crate::BitReader; +#[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] +pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_FULL` reader - Transmit FIFO is full"] +pub type TX_FULL_R = crate::BitReader; +#[doc = "Field `TX_FULL` writer - Transmit FIFO is full"] +pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RTS_STATUS` reader - RTS state"] +pub type RTS_STATUS_R = crate::BitReader; +#[doc = "Field `RTS_STATUS` writer - RTS state"] +pub type RTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `CTS_STATUS` reader - CTS state"] +pub type CTS_STATUS_R = crate::BitReader; +#[doc = "Field `CTS_STATUS` writer - CTS state"] +pub type CTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_EMPTY` reader - Transmit FIFO is completely empty"] +pub type TX_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EMPTY` writer - Transmit FIFO is completely empty"] +pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `TX_DONE` reader - Transmit FIFO is empty and transmitter is idle"] +pub type TX_DONE_R = crate::BitReader; +#[doc = "Field `TX_DONE` writer - Transmit FIFO is empty and transmitter is idle"] +pub type TX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +#[doc = "Field `RX_FIFO_LEVEL` reader - How many entries are filled in the RX FIFO"] +pub type RX_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "Field `RX_FIFO_LEVEL` writer - How many entries are filled in the RX FIFO"] +pub type RX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +#[doc = "Field `TX_FIFO_LEVEL` reader - How many entries are filled in the TX FIFO"] +pub type TX_FIFO_LEVEL_R = crate::FieldReader; +#[doc = "Field `TX_FIFO_LEVEL` writer - How many entries are filled in the TX FIFO"] +pub type TX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Receive FIFO has at least one symbol"] + #[inline(always)] + pub fn data_ready(&self) -> DATA_READY_R { + DATA_READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receiver is idle"] + #[inline(always)] + pub fn rx_idle(&self) -> RX_IDLE_R { + RX_IDLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmitter is idle"] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO overrun"] + #[inline(always)] + pub fn rx_overrun(&self) -> RX_OVERRUN_R { + RX_OVERRUN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO is full"] + #[inline(always)] + pub fn tx_full(&self) -> TX_FULL_R { + TX_FULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTS state"] + #[inline(always)] + pub fn rts_status(&self) -> RTS_STATUS_R { + RTS_STATUS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS state"] + #[inline(always)] + pub fn cts_status(&self) -> CTS_STATUS_R { + CTS_STATUS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit FIFO is completely empty"] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] + #[inline(always)] + pub fn tx_done(&self) -> TX_DONE_R { + TX_DONE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] + #[inline(always)] + pub fn rx_fifo_level(&self) -> RX_FIFO_LEVEL_R { + RX_FIFO_LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] + #[inline(always)] + pub fn tx_fifo_level(&self) -> TX_FIFO_LEVEL_R { + TX_FIFO_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Receive FIFO has at least one symbol"] + #[inline(always)] + #[must_use] + pub fn data_ready(&mut self) -> DATA_READY_W<0> { + DATA_READY_W::new(self) + } + #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] + #[inline(always)] + #[must_use] + pub fn tx_ready(&mut self) -> TX_READY_W<1> { + TX_READY_W::new(self) + } + #[doc = "Bit 2 - Receiver is idle"] + #[inline(always)] + #[must_use] + pub fn rx_idle(&mut self) -> RX_IDLE_W<2> { + RX_IDLE_W::new(self) + } + #[doc = "Bit 3 - Transmitter is idle"] + #[inline(always)] + #[must_use] + pub fn tx_idle(&mut self) -> TX_IDLE_W<3> { + TX_IDLE_W::new(self) + } + #[doc = "Bit 4 - Receive FIFO overrun"] + #[inline(always)] + #[must_use] + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<4> { + RX_OVERRUN_W::new(self) + } + #[doc = "Bit 5 - Transmit FIFO is full"] + #[inline(always)] + #[must_use] + pub fn tx_full(&mut self) -> TX_FULL_W<5> { + TX_FULL_W::new(self) + } + #[doc = "Bit 6 - RTS state"] + #[inline(always)] + #[must_use] + pub fn rts_status(&mut self) -> RTS_STATUS_W<6> { + RTS_STATUS_W::new(self) + } + #[doc = "Bit 7 - CTS state"] + #[inline(always)] + #[must_use] + pub fn cts_status(&mut self) -> CTS_STATUS_W<7> { + CTS_STATUS_W::new(self) + } + #[doc = "Bit 8 - Transmit FIFO is completely empty"] + #[inline(always)] + #[must_use] + pub fn tx_empty(&mut self) -> TX_EMPTY_W<8> { + TX_EMPTY_W::new(self) + } + #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] + #[inline(always)] + #[must_use] + pub fn tx_done(&mut self) -> TX_DONE_W<9> { + TX_DONE_W::new(self) + } + #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W<16> { + RX_FIFO_LEVEL_W::new(self) + } + #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W<24> { + TX_FIFO_LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device.rs b/crates/bcm2837-lpa/src/usb_otg_device.rs new file mode 100644 index 0000000..8050e54 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device.rs @@ -0,0 +1,179 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS device configuration register"] + pub dcfg: DCFG, + #[doc = "0x04 - OTG_HS device control register"] + pub dctl: DCTL, + #[doc = "0x08 - OTG_HS device status register"] + pub dsts: DSTS, + _reserved3: [u8; 0x04], + #[doc = "0x10 - OTG_HS device IN endpoint common interrupt mask register"] + pub diepmsk: DIEPMSK, + #[doc = "0x14 - OTG_HS device OUT endpoint common interrupt mask register"] + pub doepmsk: DOEPMSK, + #[doc = "0x18 - OTG_HS device all endpoints interrupt register"] + pub daint: DAINT, + #[doc = "0x1c - OTG_HS all endpoints interrupt mask register"] + pub daintmsk: DAINTMSK, + _reserved7: [u8; 0x08], + #[doc = "0x28 - OTG_HS device VBUS discharge time register"] + pub dvbusdis: DVBUSDIS, + #[doc = "0x2c - OTG_HS device VBUS pulsing time register"] + pub dvbuspulse: DVBUSPULSE, + #[doc = "0x30 - OTG_HS Device threshold control register"] + pub dthrctl: DTHRCTL, + #[doc = "0x34 - OTG_HS device IN endpoint FIFO empty interrupt mask register"] + pub diepempmsk: DIEPEMPMSK, + #[doc = "0x38 - OTG_HS device each endpoint interrupt register"] + pub deachint: DEACHINT, + #[doc = "0x3c - OTG_HS device each endpoint interrupt register mask"] + pub deachintmsk: DEACHINTMSK, + #[doc = "0x40 - OTG_HS device each in endpoint-1 interrupt register"] + pub diepeachmsk1: DIEPEACHMSK1, + _reserved14: [u8; 0x3c], + #[doc = "0x80 - OTG_HS device each OUT endpoint-1 interrupt register"] + pub doepeachmsk1: DOEPEACHMSK1, + _reserved15: [u8; 0x7c], + #[doc = "0x100..0x11c - IN Endpoint %s"] + pub in_endpoint0: IN_ENDPOINT, + _reserved16: [u8; 0x04], + #[doc = "0x120..0x13c - IN Endpoint %s"] + pub in_endpoint1: IN_ENDPOINT, + _reserved17: [u8; 0x04], + #[doc = "0x140..0x15c - IN Endpoint %s"] + pub in_endpoint2: IN_ENDPOINT, + _reserved18: [u8; 0x04], + #[doc = "0x160..0x17c - IN Endpoint %s"] + pub in_endpoint3: IN_ENDPOINT, + _reserved19: [u8; 0x04], + #[doc = "0x180..0x19c - IN Endpoint %s"] + pub in_endpoint4: IN_ENDPOINT, + _reserved20: [u8; 0x04], + #[doc = "0x1a0..0x1bc - IN Endpoint %s"] + pub in_endpoint5: IN_ENDPOINT, + _reserved21: [u8; 0x04], + #[doc = "0x1c0..0x1dc - IN Endpoint %s"] + pub in_endpoint6: IN_ENDPOINT, + _reserved22: [u8; 0x04], + #[doc = "0x1e0..0x1fc - IN Endpoint %s"] + pub in_endpoint7: IN_ENDPOINT, + _reserved23: [u8; 0x04], + #[doc = "0x200..0x21c - IN Endpoint %s"] + pub in_endpoint8: IN_ENDPOINT, + _reserved24: [u8; 0x04], + #[doc = "0x220..0x23c - IN Endpoint %s"] + pub in_endpoint9: IN_ENDPOINT, + _reserved25: [u8; 0x04], + #[doc = "0x240..0x25c - IN Endpoint %s"] + pub in_endpoint10: IN_ENDPOINT, + _reserved26: [u8; 0x04], + #[doc = "0x260..0x27c - IN Endpoint %s"] + pub in_endpoint11: IN_ENDPOINT, + _reserved27: [u8; 0x84], + #[doc = "0x300..0x318 - OUT Endpoint %s"] + pub out_endpoint0: OUT_ENDPOINT, + _reserved28: [u8; 0x08], + #[doc = "0x320..0x338 - OUT Endpoint %s"] + pub out_endpoint1: OUT_ENDPOINT, + _reserved29: [u8; 0x08], + #[doc = "0x340..0x358 - OUT Endpoint %s"] + pub out_endpoint2: OUT_ENDPOINT, + _reserved30: [u8; 0x08], + #[doc = "0x360..0x378 - OUT Endpoint %s"] + pub out_endpoint3: OUT_ENDPOINT, + _reserved31: [u8; 0x08], + #[doc = "0x380..0x398 - OUT Endpoint %s"] + pub out_endpoint4: OUT_ENDPOINT, + _reserved32: [u8; 0x08], + #[doc = "0x3a0..0x3b8 - OUT Endpoint %s"] + pub out_endpoint5: OUT_ENDPOINT, + _reserved33: [u8; 0x08], + #[doc = "0x3c0..0x3d8 - OUT Endpoint %s"] + pub out_endpoint6: OUT_ENDPOINT, + _reserved34: [u8; 0x08], + #[doc = "0x3e0..0x3f8 - OUT Endpoint %s"] + pub out_endpoint7: OUT_ENDPOINT, + _reserved35: [u8; 0x08], + #[doc = "0x400..0x418 - OUT Endpoint %s"] + pub out_endpoint8: OUT_ENDPOINT, + _reserved36: [u8; 0x08], + #[doc = "0x420..0x438 - OUT Endpoint %s"] + pub out_endpoint9: OUT_ENDPOINT, + _reserved37: [u8; 0x08], + #[doc = "0x440..0x458 - OUT Endpoint %s"] + pub out_endpoint10: OUT_ENDPOINT, + _reserved38: [u8; 0x08], + #[doc = "0x460..0x478 - OUT Endpoint %s"] + pub out_endpoint11: OUT_ENDPOINT, +} +#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "OTG_HS device configuration register"] +pub mod dcfg; +#[doc = "DCTL (rw) register accessor: an alias for `Reg`"] +pub type DCTL = crate::Reg; +#[doc = "OTG_HS device control register"] +pub mod dctl; +#[doc = "DSTS (r) register accessor: an alias for `Reg`"] +pub type DSTS = crate::Reg; +#[doc = "OTG_HS device status register"] +pub mod dsts; +#[doc = "DIEPMSK (rw) register accessor: an alias for `Reg`"] +pub type DIEPMSK = crate::Reg; +#[doc = "OTG_HS device IN endpoint common interrupt mask register"] +pub mod diepmsk; +#[doc = "DOEPMSK (rw) register accessor: an alias for `Reg`"] +pub type DOEPMSK = crate::Reg; +#[doc = "OTG_HS device OUT endpoint common interrupt mask register"] +pub mod doepmsk; +#[doc = "DAINT (r) register accessor: an alias for `Reg`"] +pub type DAINT = crate::Reg; +#[doc = "OTG_HS device all endpoints interrupt register"] +pub mod daint; +#[doc = "DAINTMSK (rw) register accessor: an alias for `Reg`"] +pub type DAINTMSK = crate::Reg; +#[doc = "OTG_HS all endpoints interrupt mask register"] +pub mod daintmsk; +#[doc = "DVBUSDIS (rw) register accessor: an alias for `Reg`"] +pub type DVBUSDIS = crate::Reg; +#[doc = "OTG_HS device VBUS discharge time register"] +pub mod dvbusdis; +#[doc = "DVBUSPULSE (rw) register accessor: an alias for `Reg`"] +pub type DVBUSPULSE = crate::Reg; +#[doc = "OTG_HS device VBUS pulsing time register"] +pub mod dvbuspulse; +#[doc = "DTHRCTL (rw) register accessor: an alias for `Reg`"] +pub type DTHRCTL = crate::Reg; +#[doc = "OTG_HS Device threshold control register"] +pub mod dthrctl; +#[doc = "DIEPEMPMSK (rw) register accessor: an alias for `Reg`"] +pub type DIEPEMPMSK = crate::Reg; +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register"] +pub mod diepempmsk; +#[doc = "DEACHINT (rw) register accessor: an alias for `Reg`"] +pub type DEACHINT = crate::Reg; +#[doc = "OTG_HS device each endpoint interrupt register"] +pub mod deachint; +#[doc = "DEACHINTMSK (rw) register accessor: an alias for `Reg`"] +pub type DEACHINTMSK = crate::Reg; +#[doc = "OTG_HS device each endpoint interrupt register mask"] +pub mod deachintmsk; +#[doc = "DIEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +pub type DIEPEACHMSK1 = crate::Reg; +#[doc = "OTG_HS device each in endpoint-1 interrupt register"] +pub mod diepeachmsk1; +#[doc = "DOEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +pub type DOEPEACHMSK1 = crate::Reg; +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register"] +pub mod doepeachmsk1; +#[doc = "IN Endpoint %s"] +pub use self::in_endpoint::IN_ENDPOINT; +#[doc = r"Cluster"] +#[doc = "IN Endpoint %s"] +pub mod in_endpoint; +#[doc = "OUT Endpoint %s"] +pub use self::out_endpoint::OUT_ENDPOINT; +#[doc = r"Cluster"] +#[doc = "OUT Endpoint %s"] +pub mod out_endpoint; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/daint.rs b/crates/bcm2837-lpa/src/usb_otg_device/daint.rs new file mode 100644 index 0000000..14c25b3 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/daint.rs @@ -0,0 +1,44 @@ +#[doc = "Register `DAINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IEPINT` reader - IN endpoint interrupt bits"] +pub type IEPINT_R = crate::FieldReader; +#[doc = "Field `OEPINT` reader - OUT endpoint interrupt bits"] +pub type OEPINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - IN endpoint interrupt bits"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - OUT endpoint interrupt bits"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "OTG_HS device all endpoints interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](index.html) module"] +pub struct DAINT_SPEC; +impl crate::RegisterSpec for DAINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [daint::R](R) reader structure"] +impl crate::Readable for DAINT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DAINT to value 0"] +impl crate::Resettable for DAINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs new file mode 100644 index 0000000..bf7c858 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DAINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DAINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEPM` reader - IN EP interrupt mask bits"] +pub type IEPM_R = crate::FieldReader; +#[doc = "Field `IEPM` writer - IN EP interrupt mask bits"] +pub type IEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +#[doc = "Field `OEPM` reader - OUT EP interrupt mask bits"] +pub type OEPM_R = crate::FieldReader; +#[doc = "Field `OEPM` writer - OUT EP interrupt mask bits"] +pub type OEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN EP interrupt mask bits"] + #[inline(always)] + pub fn iepm(&self) -> IEPM_R { + IEPM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] + #[inline(always)] + pub fn oepm(&self) -> OEPM_R { + OEPM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN EP interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn iepm(&mut self) -> IEPM_W<0> { + IEPM_W::new(self) + } + #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn oepm(&mut self) -> OEPM_W<16> { + OEPM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS all endpoints interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](index.html) module"] +pub struct DAINTMSK_SPEC; +impl crate::RegisterSpec for DAINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [daintmsk::R](R) reader structure"] +impl crate::Readable for DAINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [daintmsk::W](W) writer structure"] +impl crate::Writable for DAINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAINTMSK to value 0"] +impl crate::Resettable for DAINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs b/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs new file mode 100644 index 0000000..ad6ef16 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSPD` reader - Device speed"] +pub type DSPD_R = crate::FieldReader; +#[doc = "Field `DSPD` writer - Device speed"] +pub type DSPD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `NZLSOHSK` reader - Nonzero-length status OUT handshake"] +pub type NZLSOHSK_R = crate::BitReader; +#[doc = "Field `NZLSOHSK` writer - Nonzero-length status OUT handshake"] +pub type NZLSOHSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCFG_SPEC, bool, O>; +#[doc = "Field `DAD` reader - Device address"] +pub type DAD_R = crate::FieldReader; +#[doc = "Field `DAD` writer - Device address"] +pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 7, O>; +#[doc = "Field `PFIVL` reader - Periodic (micro)frame interval"] +pub type PFIVL_R = crate::FieldReader; +#[doc = "Field `PFIVL` writer - Periodic (micro)frame interval"] +pub type PFIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `PERSCHIVL` reader - Periodic scheduling interval"] +pub type PERSCHIVL_R = crate::FieldReader; +#[doc = "Field `PERSCHIVL` writer - Periodic scheduling interval"] +pub type PERSCHIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:1 - Device speed"] + #[inline(always)] + pub fn dspd(&self) -> DSPD_R { + DSPD_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Nonzero-length status OUT handshake"] + #[inline(always)] + pub fn nzlsohsk(&self) -> NZLSOHSK_R { + NZLSOHSK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:10 - Device address"] + #[inline(always)] + pub fn dad(&self) -> DAD_R { + DAD_R::new(((self.bits >> 4) & 0x7f) as u8) + } + #[doc = "Bits 11:12 - Periodic (micro)frame interval"] + #[inline(always)] + pub fn pfivl(&self) -> PFIVL_R { + PFIVL_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bits 24:25 - Periodic scheduling interval"] + #[inline(always)] + pub fn perschivl(&self) -> PERSCHIVL_R { + PERSCHIVL_R::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Device speed"] + #[inline(always)] + #[must_use] + pub fn dspd(&mut self) -> DSPD_W<0> { + DSPD_W::new(self) + } + #[doc = "Bit 2 - Nonzero-length status OUT handshake"] + #[inline(always)] + #[must_use] + pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<2> { + NZLSOHSK_W::new(self) + } + #[doc = "Bits 4:10 - Device address"] + #[inline(always)] + #[must_use] + pub fn dad(&mut self) -> DAD_W<4> { + DAD_W::new(self) + } + #[doc = "Bits 11:12 - Periodic (micro)frame interval"] + #[inline(always)] + #[must_use] + pub fn pfivl(&mut self) -> PFIVL_W<11> { + PFIVL_W::new(self) + } + #[doc = "Bits 24:25 - Periodic scheduling interval"] + #[inline(always)] + #[must_use] + pub fn perschivl(&mut self) -> PERSCHIVL_W<24> { + PERSCHIVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCFG to value 0x0220_0000"] +impl crate::Resettable for DCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_0000; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs b/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs new file mode 100644 index 0000000..ed73ebd --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs @@ -0,0 +1,171 @@ +#[doc = "Register `DCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RWUSIG` reader - Remote wakeup signaling"] +pub type RWUSIG_R = crate::BitReader; +#[doc = "Field `RWUSIG` writer - Remote wakeup signaling"] +pub type RWUSIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `SDIS` reader - Soft disconnect"] +pub type SDIS_R = crate::BitReader; +#[doc = "Field `SDIS` writer - Soft disconnect"] +pub type SDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `GINSTS` reader - Global IN NAK status"] +pub type GINSTS_R = crate::BitReader; +#[doc = "Field `GONSTS` reader - Global OUT NAK status"] +pub type GONSTS_R = crate::BitReader; +#[doc = "Field `TCTL` reader - Test control"] +pub type TCTL_R = crate::FieldReader; +#[doc = "Field `TCTL` writer - Test control"] +pub type TCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTL_SPEC, u8, u8, 3, O>; +#[doc = "Field `SGINAK` writer - Set global IN NAK"] +pub type SGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `CGINAK` writer - Clear global IN NAK"] +pub type CGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `SGONAK` writer - Set global OUT NAK"] +pub type SGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `CGONAK` writer - Clear global OUT NAK"] +pub type CGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +#[doc = "Field `POPRGDNE` reader - Power-on programming done"] +pub type POPRGDNE_R = crate::BitReader; +#[doc = "Field `POPRGDNE` writer - Power-on programming done"] +pub type POPRGDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Remote wakeup signaling"] + #[inline(always)] + pub fn rwusig(&self) -> RWUSIG_R { + RWUSIG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Soft disconnect"] + #[inline(always)] + pub fn sdis(&self) -> SDIS_R { + SDIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Global IN NAK status"] + #[inline(always)] + pub fn ginsts(&self) -> GINSTS_R { + GINSTS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Global OUT NAK status"] + #[inline(always)] + pub fn gonsts(&self) -> GONSTS_R { + GONSTS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Test control"] + #[inline(always)] + pub fn tctl(&self) -> TCTL_R { + TCTL_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 11 - Power-on programming done"] + #[inline(always)] + pub fn poprgdne(&self) -> POPRGDNE_R { + POPRGDNE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remote wakeup signaling"] + #[inline(always)] + #[must_use] + pub fn rwusig(&mut self) -> RWUSIG_W<0> { + RWUSIG_W::new(self) + } + #[doc = "Bit 1 - Soft disconnect"] + #[inline(always)] + #[must_use] + pub fn sdis(&mut self) -> SDIS_W<1> { + SDIS_W::new(self) + } + #[doc = "Bits 4:6 - Test control"] + #[inline(always)] + #[must_use] + pub fn tctl(&mut self) -> TCTL_W<4> { + TCTL_W::new(self) + } + #[doc = "Bit 7 - Set global IN NAK"] + #[inline(always)] + #[must_use] + pub fn sginak(&mut self) -> SGINAK_W<7> { + SGINAK_W::new(self) + } + #[doc = "Bit 8 - Clear global IN NAK"] + #[inline(always)] + #[must_use] + pub fn cginak(&mut self) -> CGINAK_W<8> { + CGINAK_W::new(self) + } + #[doc = "Bit 9 - Set global OUT NAK"] + #[inline(always)] + #[must_use] + pub fn sgonak(&mut self) -> SGONAK_W<9> { + SGONAK_W::new(self) + } + #[doc = "Bit 10 - Clear global OUT NAK"] + #[inline(always)] + #[must_use] + pub fn cgonak(&mut self) -> CGONAK_W<10> { + CGONAK_W::new(self) + } + #[doc = "Bit 11 - Power-on programming done"] + #[inline(always)] + #[must_use] + pub fn poprgdne(&mut self) -> POPRGDNE_W<11> { + POPRGDNE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](index.html) module"] +pub struct DCTL_SPEC; +impl crate::RegisterSpec for DCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dctl::R](R) reader structure"] +impl crate::Readable for DCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dctl::W](W) writer structure"] +impl crate::Writable for DCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCTL to value 0"] +impl crate::Resettable for DCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs b/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs new file mode 100644 index 0000000..b2e2a0b --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEACHINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEACHINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEP1INT` reader - IN endpoint 1interrupt bit"] +pub type IEP1INT_R = crate::BitReader; +#[doc = "Field `IEP1INT` writer - IN endpoint 1interrupt bit"] +pub type IEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +#[doc = "Field `OEP1INT` reader - OUT endpoint 1 interrupt bit"] +pub type OEP1INT_R = crate::BitReader; +#[doc = "Field `OEP1INT` writer - OUT endpoint 1 interrupt bit"] +pub type OEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - IN endpoint 1interrupt bit"] + #[inline(always)] + pub fn iep1int(&self) -> IEP1INT_R { + IEP1INT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] + #[inline(always)] + pub fn oep1int(&self) -> OEP1INT_R { + OEP1INT_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - IN endpoint 1interrupt bit"] + #[inline(always)] + #[must_use] + pub fn iep1int(&mut self) -> IEP1INT_W<1> { + IEP1INT_W::new(self) + } + #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] + #[inline(always)] + #[must_use] + pub fn oep1int(&mut self) -> OEP1INT_W<17> { + OEP1INT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each endpoint interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachint](index.html) module"] +pub struct DEACHINT_SPEC; +impl crate::RegisterSpec for DEACHINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deachint::R](R) reader structure"] +impl crate::Readable for DEACHINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [deachint::W](W) writer structure"] +impl crate::Writable for DEACHINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEACHINT to value 0"] +impl crate::Resettable for DEACHINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs new file mode 100644 index 0000000..635cecf --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DEACHINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEACHINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IEP1INTM` reader - IN Endpoint 1 interrupt mask bit"] +pub type IEP1INTM_R = crate::BitReader; +#[doc = "Field `IEP1INTM` writer - IN Endpoint 1 interrupt mask bit"] +pub type IEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +#[doc = "Field `OEP1INTM` reader - OUT Endpoint 1 interrupt mask bit"] +pub type OEP1INTM_R = crate::BitReader; +#[doc = "Field `OEP1INTM` writer - OUT Endpoint 1 interrupt mask bit"] +pub type OEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] + #[inline(always)] + pub fn iep1intm(&self) -> IEP1INTM_R { + IEP1INTM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] + #[inline(always)] + pub fn oep1intm(&self) -> OEP1INTM_R { + OEP1INTM_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] + #[inline(always)] + #[must_use] + pub fn iep1intm(&mut self) -> IEP1INTM_W<1> { + IEP1INTM_W::new(self) + } + #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] + #[inline(always)] + #[must_use] + pub fn oep1intm(&mut self) -> OEP1INTM_W<17> { + OEP1INTM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each endpoint interrupt register mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachintmsk](index.html) module"] +pub struct DEACHINTMSK_SPEC; +impl crate::RegisterSpec for DEACHINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [deachintmsk::R](R) reader structure"] +impl crate::Readable for DEACHINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [deachintmsk::W](W) writer structure"] +impl crate::Writable for DEACHINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEACHINTMSK to value 0"] +impl crate::Resettable for DEACHINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs b/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs new file mode 100644 index 0000000..6e00947 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs @@ -0,0 +1,200 @@ +#[doc = "Register `DIEPEACHMSK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPEACHMSK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - FIFO underrun mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - FIFO underrun mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<13> { + NAKM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepeachmsk1](index.html) module"] +pub struct DIEPEACHMSK1_SPEC; +impl crate::RegisterSpec for DIEPEACHMSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepeachmsk1::R](R) reader structure"] +impl crate::Readable for DIEPEACHMSK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepeachmsk1::W](W) writer structure"] +impl crate::Writable for DIEPEACHMSK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPEACHMSK1 to value 0"] +impl crate::Resettable for DIEPEACHMSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs new file mode 100644 index 0000000..8e5b978 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs @@ -0,0 +1,81 @@ +#[doc = "Register `DIEPEMPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPEMPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXFEM` reader - IN EP Tx FIFO empty interrupt mask bits"] +pub type INEPTXFEM_R = crate::FieldReader; +#[doc = "Field `INEPTXFEM` writer - IN EP Tx FIFO empty interrupt mask bits"] +pub type INEPTXFEM_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, DIEPEMPMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] + #[inline(always)] + pub fn ineptxfem(&self) -> INEPTXFEM_R { + INEPTXFEM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] + #[inline(always)] + #[must_use] + pub fn ineptxfem(&mut self) -> INEPTXFEM_W<0> { + INEPTXFEM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](index.html) module"] +pub struct DIEPEMPMSK_SPEC; +impl crate::RegisterSpec for DIEPEMPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepempmsk::R](R) reader structure"] +impl crate::Readable for DIEPEMPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepempmsk::W](W) writer structure"] +impl crate::Writable for DIEPEMPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPEMPMSK to value 0"] +impl crate::Resettable for DIEPEMPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs new file mode 100644 index 0000000..6411ce9 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs @@ -0,0 +1,185 @@ +#[doc = "Register `DIEPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - FIFO underrun mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - FIFO underrun mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - FIFO underrun mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"] +pub struct DIEPMSK_SPEC; +impl crate::RegisterSpec for DIEPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepmsk::R](R) reader structure"] +impl crate::Readable for DIEPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"] +impl crate::Writable for DIEPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPMSK to value 0"] +impl crate::Resettable for DIEPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs b/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs new file mode 100644 index 0000000..31a5ab1 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs @@ -0,0 +1,230 @@ +#[doc = "Register `DOEPEACHMSK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPEACHMSK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TOM` reader - Timeout condition mask"] +pub type TOM_R = crate::BitReader; +#[doc = "Field `TOM` writer - Timeout condition mask"] +pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_R = crate::BitReader; +#[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] +pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] +pub type INEPNMM_R = crate::BitReader; +#[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] +pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] +pub type INEPNEM_R = crate::BitReader; +#[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] +pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `TXFURM` reader - OUT packet error mask"] +pub type TXFURM_R = crate::BitReader; +#[doc = "Field `TXFURM` writer - OUT packet error mask"] +pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BIM` reader - BNA interrupt mask"] +pub type BIM_R = crate::BitReader; +#[doc = "Field `BIM` writer - BNA interrupt mask"] +pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `BERRM` reader - Bubble error interrupt mask"] +pub type BERRM_R = crate::BitReader; +#[doc = "Field `BERRM` writer - Bubble error interrupt mask"] +pub type BERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +#[doc = "Field `NYETM` reader - NYET interrupt mask"] +pub type NYETM_R = crate::BitReader; +#[doc = "Field `NYETM` writer - NYET interrupt mask"] +pub type NYETM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition mask"] + #[inline(always)] + pub fn tom(&self) -> TOM_R { + TOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + pub fn ittxfemsk(&self) -> ITTXFEMSK_R { + ITTXFEMSK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + pub fn inepnmm(&self) -> INEPNMM_R { + INEPNMM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + pub fn inepnem(&self) -> INEPNEM_R { + INEPNEM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + pub fn txfurm(&self) -> TXFURM_R { + TXFURM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn bim(&self) -> BIM_R { + BIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Bubble error interrupt mask"] + #[inline(always)] + pub fn berrm(&self) -> BERRM_R { + BERRM_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NYET interrupt mask"] + #[inline(always)] + pub fn nyetm(&self) -> NYETM_R { + NYETM_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - Timeout condition mask"] + #[inline(always)] + #[must_use] + pub fn tom(&mut self) -> TOM_W<3> { + TOM_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + ITTXFEMSK_W::new(self) + } + #[doc = "Bit 5 - IN token received with EP mismatch mask"] + #[inline(always)] + #[must_use] + pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + INEPNMM_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn inepnem(&mut self) -> INEPNEM_W<6> { + INEPNEM_W::new(self) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + #[must_use] + pub fn txfurm(&mut self) -> TXFURM_W<8> { + TXFURM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn bim(&mut self) -> BIM_W<9> { + BIM_W::new(self) + } + #[doc = "Bit 12 - Bubble error interrupt mask"] + #[inline(always)] + #[must_use] + pub fn berrm(&mut self) -> BERRM_W<12> { + BERRM_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<13> { + NAKM_W::new(self) + } + #[doc = "Bit 14 - NYET interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nyetm(&mut self) -> NYETM_W<14> { + NYETM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepeachmsk1](index.html) module"] +pub struct DOEPEACHMSK1_SPEC; +impl crate::RegisterSpec for DOEPEACHMSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepeachmsk1::R](R) reader structure"] +impl crate::Readable for DOEPEACHMSK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepeachmsk1::W](W) writer structure"] +impl crate::Writable for DOEPEACHMSK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPEACHMSK1 to value 0"] +impl crate::Resettable for DOEPEACHMSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs new file mode 100644 index 0000000..46e5ca8 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs @@ -0,0 +1,170 @@ +#[doc = "Register `DOEPMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] +pub type EPDM_R = crate::BitReader; +#[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] +pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `STUPM` reader - SETUP phase done mask"] +pub type STUPM_R = crate::BitReader; +#[doc = "Field `STUPM` writer - SETUP phase done mask"] +pub type STUPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `OTEPDM` reader - OUT token received when endpoint disabled mask"] +pub type OTEPDM_R = crate::BitReader; +#[doc = "Field `OTEPDM` writer - OUT token received when endpoint disabled mask"] +pub type OTEPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received mask"] +pub type B2BSTUP_R = crate::BitReader; +#[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received mask"] +pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `OPEM` reader - OUT packet error mask"] +pub type OPEM_R = crate::BitReader; +#[doc = "Field `OPEM` writer - OUT packet error mask"] +pub type OPEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +#[doc = "Field `BOIM` reader - BNA interrupt mask"] +pub type BOIM_R = crate::BitReader; +#[doc = "Field `BOIM` writer - BNA interrupt mask"] +pub type BOIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + pub fn epdm(&self) -> EPDM_R { + EPDM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - SETUP phase done mask"] + #[inline(always)] + pub fn stupm(&self) -> STUPM_R { + STUPM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] + #[inline(always)] + pub fn otepdm(&self) -> OTEPDM_R { + OTEPDM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] + #[inline(always)] + pub fn b2bstup(&self) -> B2BSTUP_R { + B2BSTUP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + pub fn opem(&self) -> OPEM_R { + OPEM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + pub fn boim(&self) -> BOIM_R { + BOIM_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epdm(&mut self) -> EPDM_W<1> { + EPDM_W::new(self) + } + #[doc = "Bit 3 - SETUP phase done mask"] + #[inline(always)] + #[must_use] + pub fn stupm(&mut self) -> STUPM_W<3> { + STUPM_W::new(self) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] + #[inline(always)] + #[must_use] + pub fn otepdm(&mut self) -> OTEPDM_W<4> { + OTEPDM_W::new(self) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] + #[inline(always)] + #[must_use] + pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + B2BSTUP_W::new(self) + } + #[doc = "Bit 8 - OUT packet error mask"] + #[inline(always)] + #[must_use] + pub fn opem(&mut self) -> OPEM_W<8> { + OPEM_W::new(self) + } + #[doc = "Bit 9 - BNA interrupt mask"] + #[inline(always)] + #[must_use] + pub fn boim(&mut self) -> BOIM_W<9> { + BOIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](index.html) module"] +pub struct DOEPMSK_SPEC; +impl crate::RegisterSpec for DOEPMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepmsk::R](R) reader structure"] +impl crate::Readable for DOEPMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepmsk::W](W) writer structure"] +impl crate::Writable for DOEPMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPMSK to value 0"] +impl crate::Resettable for DOEPMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs b/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs new file mode 100644 index 0000000..ddf0900 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs @@ -0,0 +1,58 @@ +#[doc = "Register `DSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUSPSTS` reader - Suspend status"] +pub type SUSPSTS_R = crate::BitReader; +#[doc = "Field `ENUMSPD` reader - Enumerated speed"] +pub type ENUMSPD_R = crate::FieldReader; +#[doc = "Field `EERR` reader - Erratic error"] +pub type EERR_R = crate::BitReader; +#[doc = "Field `FNSOF` reader - Frame number of the received SOF"] +pub type FNSOF_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Suspend status"] + #[inline(always)] + pub fn suspsts(&self) -> SUSPSTS_R { + SUSPSTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Enumerated speed"] + #[inline(always)] + pub fn enumspd(&self) -> ENUMSPD_R { + ENUMSPD_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Erratic error"] + #[inline(always)] + pub fn eerr(&self) -> EERR_R { + EERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:21 - Frame number of the received SOF"] + #[inline(always)] + pub fn fnsof(&self) -> FNSOF_R { + FNSOF_R::new(((self.bits >> 8) & 0x3fff) as u16) + } +} +#[doc = "OTG_HS device status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](index.html) module"] +pub struct DSTS_SPEC; +impl crate::RegisterSpec for DSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dsts::R](R) reader structure"] +impl crate::Readable for DSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DSTS to value 0x10"] +impl crate::Resettable for DSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs b/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs new file mode 100644 index 0000000..ea85092 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DTHRCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DTHRCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NONISOTHREN` reader - Nonisochronous IN endpoints threshold enable"] +pub type NONISOTHREN_R = crate::BitReader; +#[doc = "Field `NONISOTHREN` writer - Nonisochronous IN endpoints threshold enable"] +pub type NONISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `ISOTHREN` reader - ISO IN endpoint threshold enable"] +pub type ISOTHREN_R = crate::BitReader; +#[doc = "Field `ISOTHREN` writer - ISO IN endpoint threshold enable"] +pub type ISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `TXTHRLEN` reader - Transmit threshold length"] +pub type TXTHRLEN_R = crate::FieldReader; +#[doc = "Field `TXTHRLEN` writer - Transmit threshold length"] +pub type TXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +#[doc = "Field `RXTHREN` reader - Receive threshold enable"] +pub type RXTHREN_R = crate::BitReader; +#[doc = "Field `RXTHREN` writer - Receive threshold enable"] +pub type RXTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +#[doc = "Field `RXTHRLEN` reader - Receive threshold length"] +pub type RXTHRLEN_R = crate::FieldReader; +#[doc = "Field `RXTHRLEN` writer - Receive threshold length"] +pub type RXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +#[doc = "Field `ARPEN` reader - Arbiter parking enable"] +pub type ARPEN_R = crate::BitReader; +#[doc = "Field `ARPEN` writer - Arbiter parking enable"] +pub type ARPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] + #[inline(always)] + pub fn nonisothren(&self) -> NONISOTHREN_R { + NONISOTHREN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ISO IN endpoint threshold enable"] + #[inline(always)] + pub fn isothren(&self) -> ISOTHREN_R { + ISOTHREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:10 - Transmit threshold length"] + #[inline(always)] + pub fn txthrlen(&self) -> TXTHRLEN_R { + TXTHRLEN_R::new(((self.bits >> 2) & 0x01ff) as u16) + } + #[doc = "Bit 16 - Receive threshold enable"] + #[inline(always)] + pub fn rxthren(&self) -> RXTHREN_R { + RXTHREN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:25 - Receive threshold length"] + #[inline(always)] + pub fn rxthrlen(&self) -> RXTHRLEN_R { + RXTHRLEN_R::new(((self.bits >> 17) & 0x01ff) as u16) + } + #[doc = "Bit 27 - Arbiter parking enable"] + #[inline(always)] + pub fn arpen(&self) -> ARPEN_R { + ARPEN_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] + #[inline(always)] + #[must_use] + pub fn nonisothren(&mut self) -> NONISOTHREN_W<0> { + NONISOTHREN_W::new(self) + } + #[doc = "Bit 1 - ISO IN endpoint threshold enable"] + #[inline(always)] + #[must_use] + pub fn isothren(&mut self) -> ISOTHREN_W<1> { + ISOTHREN_W::new(self) + } + #[doc = "Bits 2:10 - Transmit threshold length"] + #[inline(always)] + #[must_use] + pub fn txthrlen(&mut self) -> TXTHRLEN_W<2> { + TXTHRLEN_W::new(self) + } + #[doc = "Bit 16 - Receive threshold enable"] + #[inline(always)] + #[must_use] + pub fn rxthren(&mut self) -> RXTHREN_W<16> { + RXTHREN_W::new(self) + } + #[doc = "Bits 17:25 - Receive threshold length"] + #[inline(always)] + #[must_use] + pub fn rxthrlen(&mut self) -> RXTHRLEN_W<17> { + RXTHRLEN_W::new(self) + } + #[doc = "Bit 27 - Arbiter parking enable"] + #[inline(always)] + #[must_use] + pub fn arpen(&mut self) -> ARPEN_W<27> { + ARPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Device threshold control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](index.html) module"] +pub struct DTHRCTL_SPEC; +impl crate::RegisterSpec for DTHRCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dthrctl::R](R) reader structure"] +impl crate::Readable for DTHRCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dthrctl::W](W) writer structure"] +impl crate::Writable for DTHRCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DTHRCTL to value 0"] +impl crate::Resettable for DTHRCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs b/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs new file mode 100644 index 0000000..403e00a --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DVBUSDIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DVBUSDIS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VBUSDT` reader - Device VBUS discharge time"] +pub type VBUSDT_R = crate::FieldReader; +#[doc = "Field `VBUSDT` writer - Device VBUS discharge time"] +pub type VBUSDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSDIS_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Device VBUS discharge time"] + #[inline(always)] + pub fn vbusdt(&self) -> VBUSDT_R { + VBUSDT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Device VBUS discharge time"] + #[inline(always)] + #[must_use] + pub fn vbusdt(&mut self) -> VBUSDT_W<0> { + VBUSDT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device VBUS discharge time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](index.html) module"] +pub struct DVBUSDIS_SPEC; +impl crate::RegisterSpec for DVBUSDIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dvbusdis::R](R) reader structure"] +impl crate::Readable for DVBUSDIS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dvbusdis::W](W) writer structure"] +impl crate::Writable for DVBUSDIS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DVBUSDIS to value 0x17d7"] +impl crate::Resettable for DVBUSDIS_SPEC { + const RESET_VALUE: Self::Ux = 0x17d7; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs b/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs new file mode 100644 index 0000000..4871f7b --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DVBUSPULSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DVBUSPULSE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DVBUSP` reader - Device VBUS pulsing time"] +pub type DVBUSP_R = crate::FieldReader; +#[doc = "Field `DVBUSP` writer - Device VBUS pulsing time"] +pub type DVBUSP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSPULSE_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Device VBUS pulsing time"] + #[inline(always)] + pub fn dvbusp(&self) -> DVBUSP_R { + DVBUSP_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Device VBUS pulsing time"] + #[inline(always)] + #[must_use] + pub fn dvbusp(&mut self) -> DVBUSP_W<0> { + DVBUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device VBUS pulsing time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](index.html) module"] +pub struct DVBUSPULSE_SPEC; +impl crate::RegisterSpec for DVBUSPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dvbuspulse::R](R) reader structure"] +impl crate::Readable for DVBUSPULSE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](W) writer structure"] +impl crate::Writable for DVBUSPULSE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DVBUSPULSE to value 0x05b8"] +impl crate::Resettable for DVBUSPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x05b8; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs new file mode 100644 index 0000000..5fd5349 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs @@ -0,0 +1,36 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct IN_ENDPOINT { + #[doc = "0x00 - Control"] + pub diepctl0: DIEPCTL0, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Interrupt"] + pub diepint: DIEPINT, + _reserved2: [u8; 0x04], + #[doc = "0x10 - Transfer size"] + pub dieptsiz: DIEPTSIZ, + #[doc = "0x14 - DMA address"] + pub diepdma: DIEPDMA, + #[doc = "0x18 - Transmit FIFO status"] + pub dtxfsts: DTXFSTS, +} +#[doc = "DIEPCTL0 (rw) register accessor: an alias for `Reg`"] +pub type DIEPCTL0 = crate::Reg; +#[doc = "Control"] +pub mod diepctl0; +#[doc = "DIEPINT (rw) register accessor: an alias for `Reg`"] +pub type DIEPINT = crate::Reg; +#[doc = "Interrupt"] +pub mod diepint; +#[doc = "DIEPTSIZ (rw) register accessor: an alias for `Reg`"] +pub type DIEPTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod dieptsiz; +#[doc = "DIEPDMA (rw) register accessor: an alias for `Reg`"] +pub type DIEPDMA = crate::Reg; +#[doc = "DMA address"] +pub mod diepdma; +#[doc = "DTXFSTS (r) register accessor: an alias for `Reg`"] +pub type DTXFSTS = crate::Reg; +#[doc = "Transmit FIFO status"] +pub mod dtxfsts; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs new file mode 100644 index 0000000..b8fa051 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs @@ -0,0 +1,216 @@ +#[doc = "Register `DIEPCTL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPCTL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `MPSIZ` writer - Maximum packet size"] +pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u16, u16, 11, O>; +#[doc = "Field `USBAEP` reader - USB active endpoint"] +pub type USBAEP_R = crate::BitReader; +#[doc = "Field `USBAEP` writer - USB active endpoint"] +pub type USBAEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EONUM_DPID` reader - Even/odd frame"] +pub type EONUM_DPID_R = crate::BitReader; +#[doc = "Field `NAKSTS` reader - NAK status"] +pub type NAKSTS_R = crate::BitReader; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `EPTYP` writer - Endpoint type"] +pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 2, O>; +#[doc = "Field `Stall` reader - STALL handshake"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `Stall` writer - STALL handshake"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `TXFNUM` reader - TxFIFO number"] +pub type TXFNUM_R = crate::FieldReader; +#[doc = "Field `TXFNUM` writer - TxFIFO number"] +pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `CNAK` writer - Clear NAK"] +pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SNAK` writer - Set NAK"] +pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SD0PID_SEVNFRM` writer - Set DATA0 PID"] +pub type SD0PID_SEVNFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `SODDFRM` writer - Set odd frame"] +pub type SODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EPDIS` reader - Endpoint disable"] +pub type EPDIS_R = crate::BitReader; +#[doc = "Field `EPDIS` writer - Endpoint disable"] +pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +#[doc = "Field `EPENA` reader - Endpoint enable"] +pub type EPENA_R = crate::BitReader; +#[doc = "Field `EPENA` writer - Endpoint enable"] +pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + pub fn usbaep(&self) -> USBAEP_R { + USBAEP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Even/odd frame"] + #[inline(always)] + pub fn eonum_dpid(&self) -> EONUM_DPID_R { + EONUM_DPID_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NAK status"] + #[inline(always)] + pub fn naksts(&self) -> NAKSTS_R { + NAKSTS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:25 - TxFIFO number"] + #[inline(always)] + pub fn txfnum(&self) -> TXFNUM_R { + TXFNUM_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + pub fn epdis(&self) -> EPDIS_R { + EPDIS_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + pub fn epena(&self) -> EPENA_R { + EPENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + #[must_use] + pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + MPSIZ_W::new(self) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + #[must_use] + pub fn usbaep(&mut self) -> USBAEP_W<15> { + USBAEP_W::new(self) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + #[must_use] + pub fn eptyp(&mut self) -> EPTYP_W<18> { + EPTYP_W::new(self) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<21> { + STALL_W::new(self) + } + #[doc = "Bits 22:25 - TxFIFO number"] + #[inline(always)] + #[must_use] + pub fn txfnum(&mut self) -> TXFNUM_W<22> { + TXFNUM_W::new(self) + } + #[doc = "Bit 26 - Clear NAK"] + #[inline(always)] + #[must_use] + pub fn cnak(&mut self) -> CNAK_W<26> { + CNAK_W::new(self) + } + #[doc = "Bit 27 - Set NAK"] + #[inline(always)] + #[must_use] + pub fn snak(&mut self) -> SNAK_W<27> { + SNAK_W::new(self) + } + #[doc = "Bit 28 - Set DATA0 PID"] + #[inline(always)] + #[must_use] + pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<28> { + SD0PID_SEVNFRM_W::new(self) + } + #[doc = "Bit 29 - Set odd frame"] + #[inline(always)] + #[must_use] + pub fn soddfrm(&mut self) -> SODDFRM_W<29> { + SODDFRM_W::new(self) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + #[must_use] + pub fn epdis(&mut self) -> EPDIS_W<30> { + EPDIS_W::new(self) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + #[must_use] + pub fn epena(&mut self) -> EPENA_W<31> { + EPENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepctl0](index.html) module"] +pub struct DIEPCTL0_SPEC; +impl crate::RegisterSpec for DIEPCTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepctl0::R](R) reader structure"] +impl crate::Readable for DIEPCTL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepctl0::W](W) writer structure"] +impl crate::Writable for DIEPCTL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPCTL0 to value 0"] +impl crate::Resettable for DIEPCTL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs new file mode 100644 index 0000000..321905e --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DIEPDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepdma](index.html) module"] +pub struct DIEPDMA_SPEC; +impl crate::RegisterSpec for DIEPDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepdma::R](R) reader structure"] +impl crate::Readable for DIEPDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepdma::W](W) writer structure"] +impl crate::Writable for DIEPDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPDMA to value 0"] +impl crate::Resettable for DIEPDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs new file mode 100644 index 0000000..f85ca85 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs @@ -0,0 +1,222 @@ +#[doc = "Register `DIEPINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed interrupt"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed interrupt"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] +pub type EPDISD_R = crate::BitReader; +#[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] +pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `TOC` reader - Timeout condition"] +pub type TOC_R = crate::BitReader; +#[doc = "Field `TOC` writer - Timeout condition"] +pub type TOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `ITTXFE` reader - IN token received when TxFIFO is empty"] +pub type ITTXFE_R = crate::BitReader; +#[doc = "Field `ITTXFE` writer - IN token received when TxFIFO is empty"] +pub type ITTXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `INEPNE` reader - IN endpoint NAK effective"] +pub type INEPNE_R = crate::BitReader; +#[doc = "Field `INEPNE` writer - IN endpoint NAK effective"] +pub type INEPNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `TXFE` reader - Transmit FIFO empty"] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `TXFIFOUDRN` reader - Transmit Fifo Underrun"] +pub type TXFIFOUDRN_R = crate::BitReader; +#[doc = "Field `TXFIFOUDRN` writer - Transmit Fifo Underrun"] +pub type TXFIFOUDRN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `BNA` reader - Buffer not available interrupt"] +pub type BNA_R = crate::BitReader; +#[doc = "Field `BNA` writer - Buffer not available interrupt"] +pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `PKTDRPSTS` reader - Packet dropped status"] +pub type PKTDRPSTS_R = crate::BitReader; +#[doc = "Field `PKTDRPSTS` writer - Packet dropped status"] +pub type PKTDRPSTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Babble error interrupt"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Babble error interrupt"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +#[doc = "Field `NAK` reader - NAK interrupt"] +pub type NAK_R = crate::BitReader; +#[doc = "Field `NAK` writer - NAK interrupt"] +pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + pub fn epdisd(&self) -> EPDISD_R { + EPDISD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Timeout condition"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - IN token received when TxFIFO is empty"] + #[inline(always)] + pub fn ittxfe(&self) -> ITTXFE_R { + ITTXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - IN endpoint NAK effective"] + #[inline(always)] + pub fn inepne(&self) -> INEPNE_R { + INEPNE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transmit FIFO empty"] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit Fifo Underrun"] + #[inline(always)] + pub fn txfifoudrn(&self) -> TXFIFOUDRN_R { + TXFIFOUDRN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Buffer not available interrupt"] + #[inline(always)] + pub fn bna(&self) -> BNA_R { + BNA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - Packet dropped status"] + #[inline(always)] + pub fn pktdrpsts(&self) -> PKTDRPSTS_R { + PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Babble error interrupt"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NAK interrupt"] + #[inline(always)] + pub fn nak(&self) -> NAK_R { + NAK_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + #[must_use] + pub fn epdisd(&mut self) -> EPDISD_W<1> { + EPDISD_W::new(self) + } + #[doc = "Bit 3 - Timeout condition"] + #[inline(always)] + #[must_use] + pub fn toc(&mut self) -> TOC_W<3> { + TOC_W::new(self) + } + #[doc = "Bit 4 - IN token received when TxFIFO is empty"] + #[inline(always)] + #[must_use] + pub fn ittxfe(&mut self) -> ITTXFE_W<4> { + ITTXFE_W::new(self) + } + #[doc = "Bit 6 - IN endpoint NAK effective"] + #[inline(always)] + #[must_use] + pub fn inepne(&mut self) -> INEPNE_W<6> { + INEPNE_W::new(self) + } + #[doc = "Bit 8 - Transmit Fifo Underrun"] + #[inline(always)] + #[must_use] + pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<8> { + TXFIFOUDRN_W::new(self) + } + #[doc = "Bit 9 - Buffer not available interrupt"] + #[inline(always)] + #[must_use] + pub fn bna(&mut self) -> BNA_W<9> { + BNA_W::new(self) + } + #[doc = "Bit 11 - Packet dropped status"] + #[inline(always)] + #[must_use] + pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<11> { + PKTDRPSTS_W::new(self) + } + #[doc = "Bit 12 - Babble error interrupt"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<12> { + BERR_W::new(self) + } + #[doc = "Bit 13 - NAK interrupt"] + #[inline(always)] + #[must_use] + pub fn nak(&mut self) -> NAK_W<13> { + NAK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepint](index.html) module"] +pub struct DIEPINT_SPEC; +impl crate::RegisterSpec for DIEPINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [diepint::R](R) reader structure"] +impl crate::Readable for DIEPINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [diepint::W](W) writer structure"] +impl crate::Writable for DIEPINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPINT to value 0x80"] +impl crate::Resettable for DIEPINT_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs new file mode 100644 index 0000000..7f94dcb --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 7, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::FieldReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 19:20 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bits 19:20 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptsiz](index.html) module"] +pub struct DIEPTSIZ_SPEC; +impl crate::RegisterSpec for DIEPTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptsiz::R](R) reader structure"] +impl crate::Readable for DIEPTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptsiz::W](W) writer structure"] +impl crate::Writable for DIEPTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTSIZ to value 0"] +impl crate::Resettable for DIEPTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs new file mode 100644 index 0000000..c962826 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DTXFSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INEPTFSAV` reader - IN endpoint TxFIFO space avail"] +pub type INEPTFSAV_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - IN endpoint TxFIFO space avail"] + #[inline(always)] + pub fn ineptfsav(&self) -> INEPTFSAV_R { + INEPTFSAV_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Transmit FIFO status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtxfsts](index.html) module"] +pub struct DTXFSTS_SPEC; +impl crate::RegisterSpec for DTXFSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dtxfsts::R](R) reader structure"] +impl crate::Readable for DTXFSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DTXFSTS to value 0"] +impl crate::Resettable for DTXFSTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs new file mode 100644 index 0000000..a3a9e56 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs @@ -0,0 +1,30 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct OUT_ENDPOINT { + #[doc = "0x00 - Control"] + pub doepctl: DOEPCTL, + _reserved1: [u8; 0x04], + #[doc = "0x08 - Interrupt"] + pub doepint: DOEPINT, + _reserved2: [u8; 0x04], + #[doc = "0x10 - Transfer size"] + pub doeptsiz: DOEPTSIZ, + #[doc = "0x14 - DMA address"] + pub doepdma: DOEPDMA, +} +#[doc = "DOEPCTL (rw) register accessor: an alias for `Reg`"] +pub type DOEPCTL = crate::Reg; +#[doc = "Control"] +pub mod doepctl; +#[doc = "DOEPINT (rw) register accessor: an alias for `Reg`"] +pub type DOEPINT = crate::Reg; +#[doc = "Interrupt"] +pub mod doepint; +#[doc = "DOEPTSIZ (rw) register accessor: an alias for `Reg`"] +pub type DOEPTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod doeptsiz; +#[doc = "DOEPDMA (rw) register accessor: an alias for `Reg`"] +pub type DOEPDMA = crate::Reg; +#[doc = "DMA address"] +pub mod doepdma; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs new file mode 100644 index 0000000..2f6baf5 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs @@ -0,0 +1,154 @@ +#[doc = "Register `DOEPCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `USBAEP` reader - USB active endpoint"] +pub type USBAEP_R = crate::BitReader; +#[doc = "Field `NAKSTS` reader - NAK status"] +pub type NAKSTS_R = crate::BitReader; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `SNPM` reader - Snoop mode"] +pub type SNPM_R = crate::BitReader; +#[doc = "Field `SNPM` writer - Snoop mode"] +pub type SNPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `Stall` reader - STALL handshake"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `Stall` writer - STALL handshake"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `CNAK` writer - Clear NAK"] +pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `SNAK` writer - Set NAK"] +pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +#[doc = "Field `EPDIS` reader - Endpoint disable"] +pub type EPDIS_R = crate::BitReader; +#[doc = "Field `EPENA` writer - Endpoint enable"] +pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - USB active endpoint"] + #[inline(always)] + pub fn usbaep(&self) -> USBAEP_R { + USBAEP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - NAK status"] + #[inline(always)] + pub fn naksts(&self) -> NAKSTS_R { + NAKSTS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Snoop mode"] + #[inline(always)] + pub fn snpm(&self) -> SNPM_R { + SNPM_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 30 - Endpoint disable"] + #[inline(always)] + pub fn epdis(&self) -> EPDIS_R { + EPDIS_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 20 - Snoop mode"] + #[inline(always)] + #[must_use] + pub fn snpm(&mut self) -> SNPM_W<20> { + SNPM_W::new(self) + } + #[doc = "Bit 21 - STALL handshake"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<21> { + STALL_W::new(self) + } + #[doc = "Bit 26 - Clear NAK"] + #[inline(always)] + #[must_use] + pub fn cnak(&mut self) -> CNAK_W<26> { + CNAK_W::new(self) + } + #[doc = "Bit 27 - Set NAK"] + #[inline(always)] + #[must_use] + pub fn snak(&mut self) -> SNAK_W<27> { + SNAK_W::new(self) + } + #[doc = "Bit 31 - Endpoint enable"] + #[inline(always)] + #[must_use] + pub fn epena(&mut self) -> EPENA_W<31> { + EPENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepctl](index.html) module"] +pub struct DOEPCTL_SPEC; +impl crate::RegisterSpec for DOEPCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepctl::R](R) reader structure"] +impl crate::Readable for DOEPCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepctl::W](W) writer structure"] +impl crate::Writable for DOEPCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPCTL to value 0x8000"] +impl crate::Resettable for DOEPCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs new file mode 100644 index 0000000..92089f0 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DOEPDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepdma](index.html) module"] +pub struct DOEPDMA_SPEC; +impl crate::RegisterSpec for DOEPDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepdma::R](R) reader structure"] +impl crate::Readable for DOEPDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepdma::W](W) writer structure"] +impl crate::Writable for DOEPDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPDMA to value 0"] +impl crate::Resettable for DOEPDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs new file mode 100644 index 0000000..365d667 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DOEPINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed interrupt"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed interrupt"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] +pub type EPDISD_R = crate::BitReader; +#[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] +pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `STUP` reader - SETUP phase done"] +pub type STUP_R = crate::BitReader; +#[doc = "Field `STUP` writer - SETUP phase done"] +pub type STUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `OTEPDIS` reader - OUT token received when endpoint disabled"] +pub type OTEPDIS_R = crate::BitReader; +#[doc = "Field `OTEPDIS` writer - OUT token received when endpoint disabled"] +pub type OTEPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received"] +pub type B2BSTUP_R = crate::BitReader; +#[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received"] +pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +#[doc = "Field `NYET` reader - NYET interrupt"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - NYET interrupt"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + pub fn epdisd(&self) -> EPDISD_R { + EPDISD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - SETUP phase done"] + #[inline(always)] + pub fn stup(&self) -> STUP_R { + STUP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled"] + #[inline(always)] + pub fn otepdis(&self) -> OTEPDIS_R { + OTEPDIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received"] + #[inline(always)] + pub fn b2bstup(&self) -> B2BSTUP_R { + B2BSTUP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 14 - NYET interrupt"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed interrupt"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Endpoint disabled interrupt"] + #[inline(always)] + #[must_use] + pub fn epdisd(&mut self) -> EPDISD_W<1> { + EPDISD_W::new(self) + } + #[doc = "Bit 3 - SETUP phase done"] + #[inline(always)] + #[must_use] + pub fn stup(&mut self) -> STUP_W<3> { + STUP_W::new(self) + } + #[doc = "Bit 4 - OUT token received when endpoint disabled"] + #[inline(always)] + #[must_use] + pub fn otepdis(&mut self) -> OTEPDIS_W<4> { + OTEPDIS_W::new(self) + } + #[doc = "Bit 6 - Back-to-back SETUP packets received"] + #[inline(always)] + #[must_use] + pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + B2BSTUP_W::new(self) + } + #[doc = "Bit 14 - NYET interrupt"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<14> { + NYET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepint](index.html) module"] +pub struct DOEPINT_SPEC; +impl crate::RegisterSpec for DOEPINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doepint::R](R) reader structure"] +impl crate::Readable for DOEPINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doepint::W](W) writer structure"] +impl crate::Writable for DOEPINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPINT to value 0x80"] +impl crate::Resettable for DOEPINT_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs new file mode 100644 index 0000000..0f78e4d --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DOEPTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DOEPTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 7, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::BitReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPTSIZ_SPEC, bool, O>; +#[doc = "Field `STUPCNT` reader - SETUP packet count"] +pub type STUPCNT_R = crate::FieldReader; +#[doc = "Field `STUPCNT` writer - SETUP packet count"] +pub type STUPCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 19 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 29:30 - SETUP packet count"] + #[inline(always)] + pub fn stupcnt(&self) -> STUPCNT_R { + STUPCNT_R::new(((self.bits >> 29) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bit 19 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Bits 29:30 - SETUP packet count"] + #[inline(always)] + #[must_use] + pub fn stupcnt(&mut self) -> STUPCNT_W<29> { + STUPCNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doeptsiz](index.html) module"] +pub struct DOEPTSIZ_SPEC; +impl crate::RegisterSpec for DOEPTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [doeptsiz::R](R) reader structure"] +impl crate::Readable for DOEPTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [doeptsiz::W](W) writer structure"] +impl crate::Writable for DOEPTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DOEPTSIZ to value 0"] +impl crate::Resettable for DOEPTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global.rs b/crates/bcm2837-lpa/src/usb_otg_global.rs new file mode 100644 index 0000000..a6b35cb --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global.rs @@ -0,0 +1,198 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS control and status register"] + pub gotgctl: GOTGCTL, + #[doc = "0x04 - OTG_HS interrupt register"] + pub gotgint: GOTGINT, + #[doc = "0x08 - OTG_HS AHB configuration register"] + pub gahbcfg: GAHBCFG, + #[doc = "0x0c - OTG_HS USB configuration register"] + pub gusbcfg: GUSBCFG, + #[doc = "0x10 - OTG_HS reset register"] + pub grstctl: GRSTCTL, + #[doc = "0x14 - OTG_HS core interrupt register"] + pub gintsts: GINTSTS, + #[doc = "0x18 - OTG_HS interrupt mask register"] + pub gintmsk: GINTMSK, + _reserved_7_grxstsr: [u8; 0x04], + _reserved_8_grxstsp: [u8; 0x04], + #[doc = "0x24 - OTG_HS Receive FIFO size register"] + pub grxfsiz: GRXFSIZ, + _reserved_10_gnptxfsiz_host: [u8; 0x04], + #[doc = "0x2c - OTG_HS nonperiodic transmit FIFO/queue status register"] + pub gnptxsts: GNPTXSTS, + _reserved12: [u8; 0x08], + #[doc = "0x38 - OTG_HS general core configuration register"] + pub gccfg: GCCFG, + #[doc = "0x3c - OTG_HS core ID register"] + pub cid: CID, + #[doc = "0x40 - OTG_HS vendor ID register"] + pub vid: VID, + #[doc = "0x44 - Direction"] + pub hw_direction: HW_DIRECTION, + #[doc = "0x48 - Hardware Config 0"] + pub hw_config0: HW_CONFIG0, + _reserved17: [u8; 0xb4], + #[doc = "0x100 - OTG_HS Host periodic transmit FIFO size register"] + pub hptxfsiz: HPTXFSIZ, + #[doc = "0x104 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf1: DIEPTXF1, + #[doc = "0x108 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf2: DIEPTXF2, + _reserved20: [u8; 0x10], + #[doc = "0x11c - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf3: DIEPTXF3, + #[doc = "0x120 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf4: DIEPTXF4, + #[doc = "0x124 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf5: DIEPTXF5, + #[doc = "0x128 - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf6: DIEPTXF6, + #[doc = "0x12c - OTG_HS device IN endpoint transmit FIFO size register"] + pub dieptxf7: DIEPTXF7, +} +impl RegisterBlock { + #[doc = "0x1c - OTG_HS Receive status debug read register (peripheral mode mode)"] + #[inline(always)] + pub const fn grxstsr_peripheral(&self) -> &GRXSTSR_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(28usize).cast() } + } + #[doc = "0x1c - OTG_HS Receive status debug read register (host mode)"] + #[inline(always)] + pub const fn grxstsr_host(&self) -> &GRXSTSR_HOST { + unsafe { &*(self as *const Self).cast::().add(28usize).cast() } + } + #[doc = "0x20 - OTG_HS status read and pop register (peripheral mode)"] + #[inline(always)] + pub const fn grxstsp_peripheral(&self) -> &GRXSTSP_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(32usize).cast() } + } + #[doc = "0x20 - OTG_HS status read and pop register (host mode)"] + #[inline(always)] + pub const fn grxstsp_host(&self) -> &GRXSTSP_HOST { + unsafe { &*(self as *const Self).cast::().add(32usize).cast() } + } + #[doc = "0x28 - Endpoint 0 transmit FIFO size (peripheral mode)"] + #[inline(always)] + pub const fn tx0fsiz_peripheral(&self) -> &TX0FSIZ_PERIPHERAL { + unsafe { &*(self as *const Self).cast::().add(40usize).cast() } + } + #[doc = "0x28 - OTG_HS nonperiodic transmit FIFO size register (host mode)"] + #[inline(always)] + pub const fn gnptxfsiz_host(&self) -> &GNPTXFSIZ_HOST { + unsafe { &*(self as *const Self).cast::().add(40usize).cast() } + } +} +#[doc = "GOTGCTL (rw) register accessor: an alias for `Reg`"] +pub type GOTGCTL = crate::Reg; +#[doc = "OTG_HS control and status register"] +pub mod gotgctl; +#[doc = "GOTGINT (rw) register accessor: an alias for `Reg`"] +pub type GOTGINT = crate::Reg; +#[doc = "OTG_HS interrupt register"] +pub mod gotgint; +#[doc = "GAHBCFG (rw) register accessor: an alias for `Reg`"] +pub type GAHBCFG = crate::Reg; +#[doc = "OTG_HS AHB configuration register"] +pub mod gahbcfg; +#[doc = "GUSBCFG (rw) register accessor: an alias for `Reg`"] +pub type GUSBCFG = crate::Reg; +#[doc = "OTG_HS USB configuration register"] +pub mod gusbcfg; +#[doc = "GRSTCTL (rw) register accessor: an alias for `Reg`"] +pub type GRSTCTL = crate::Reg; +#[doc = "OTG_HS reset register"] +pub mod grstctl; +#[doc = "GINTSTS (rw) register accessor: an alias for `Reg`"] +pub type GINTSTS = crate::Reg; +#[doc = "OTG_HS core interrupt register"] +pub mod gintsts; +#[doc = "GINTMSK (rw) register accessor: an alias for `Reg`"] +pub type GINTMSK = crate::Reg; +#[doc = "OTG_HS interrupt mask register"] +pub mod gintmsk; +#[doc = "GRXSTSR_Host (r) register accessor: an alias for `Reg`"] +pub type GRXSTSR_HOST = crate::Reg; +#[doc = "OTG_HS Receive status debug read register (host mode)"] +pub mod grxstsr_host; +#[doc = "GRXSTSP_Host (r) register accessor: an alias for `Reg`"] +pub type GRXSTSP_HOST = crate::Reg; +#[doc = "OTG_HS status read and pop register (host mode)"] +pub mod grxstsp_host; +#[doc = "GRXFSIZ (rw) register accessor: an alias for `Reg`"] +pub type GRXFSIZ = crate::Reg; +#[doc = "OTG_HS Receive FIFO size register"] +pub mod grxfsiz; +#[doc = "GNPTXFSIZ_Host (rw) register accessor: an alias for `Reg`"] +pub type GNPTXFSIZ_HOST = crate::Reg; +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)"] +pub mod gnptxfsiz_host; +#[doc = "TX0FSIZ_Peripheral (rw) register accessor: an alias for `Reg`"] +pub type TX0FSIZ_PERIPHERAL = crate::Reg; +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)"] +pub mod tx0fsiz_peripheral; +#[doc = "GNPTXSTS (r) register accessor: an alias for `Reg`"] +pub type GNPTXSTS = crate::Reg; +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register"] +pub mod gnptxsts; +#[doc = "GCCFG (rw) register accessor: an alias for `Reg`"] +pub type GCCFG = crate::Reg; +#[doc = "OTG_HS general core configuration register"] +pub mod gccfg; +#[doc = "CID (rw) register accessor: an alias for `Reg`"] +pub type CID = crate::Reg; +#[doc = "OTG_HS core ID register"] +pub mod cid; +#[doc = "VID (r) register accessor: an alias for `Reg`"] +pub type VID = crate::Reg; +#[doc = "OTG_HS vendor ID register"] +pub mod vid; +#[doc = "HW_DIRECTION (r) register accessor: an alias for `Reg`"] +pub type HW_DIRECTION = crate::Reg; +#[doc = "Direction"] +pub mod hw_direction; +#[doc = "HW_CONFIG0 (r) register accessor: an alias for `Reg`"] +pub type HW_CONFIG0 = crate::Reg; +#[doc = "Hardware Config 0"] +pub mod hw_config0; +#[doc = "HPTXFSIZ (rw) register accessor: an alias for `Reg`"] +pub type HPTXFSIZ = crate::Reg; +#[doc = "OTG_HS Host periodic transmit FIFO size register"] +pub mod hptxfsiz; +#[doc = "DIEPTXF1 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF1 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf1; +#[doc = "DIEPTXF2 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF2 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf2; +#[doc = "DIEPTXF3 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF3 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf3; +#[doc = "DIEPTXF4 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF4 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf4; +#[doc = "DIEPTXF5 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF5 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf5; +#[doc = "DIEPTXF6 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF6 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf6; +#[doc = "DIEPTXF7 (rw) register accessor: an alias for `Reg`"] +pub type DIEPTXF7 = crate::Reg; +#[doc = "OTG_HS device IN endpoint transmit FIFO size register"] +pub mod dieptxf7; +#[doc = "GRXSTSR_Peripheral (r) register accessor: an alias for `Reg`"] +pub type GRXSTSR_PERIPHERAL = crate::Reg; +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)"] +pub mod grxstsr_peripheral; +#[doc = "GRXSTSP_Peripheral (r) register accessor: an alias for `Reg`"] +pub type GRXSTSP_PERIPHERAL = crate::Reg; +#[doc = "OTG_HS status read and pop register (peripheral mode)"] +pub mod grxstsp_peripheral; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/cid.rs b/crates/bcm2837-lpa/src/usb_otg_global/cid.rs new file mode 100644 index 0000000..5a8ef55 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/cid.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRODUCT_ID` reader - Product ID field"] +pub type PRODUCT_ID_R = crate::FieldReader; +#[doc = "Field `PRODUCT_ID` writer - Product ID field"] +pub type PRODUCT_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CID_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Product ID field"] + #[inline(always)] + pub fn product_id(&self) -> PRODUCT_ID_R { + PRODUCT_ID_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Product ID field"] + #[inline(always)] + #[must_use] + pub fn product_id(&mut self) -> PRODUCT_ID_W<0> { + PRODUCT_ID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS core ID register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +pub struct CID_SPEC; +impl crate::RegisterSpec for CID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid::R](R) reader structure"] +impl crate::Readable for CID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +impl crate::Writable for CID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CID to value 0x1200"] +impl crate::Resettable for CID_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs new file mode 100644 index 0000000..b79803c --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](index.html) module"] +pub struct DIEPTXF1_SPEC; +impl crate::RegisterSpec for DIEPTXF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf1::R](R) reader structure"] +impl crate::Readable for DIEPTXF1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf1::W](W) writer structure"] +impl crate::Writable for DIEPTXF1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF1 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF1_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs new file mode 100644 index 0000000..cdf9d1b --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](index.html) module"] +pub struct DIEPTXF2_SPEC; +impl crate::RegisterSpec for DIEPTXF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf2::R](R) reader structure"] +impl crate::Readable for DIEPTXF2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf2::W](W) writer structure"] +impl crate::Writable for DIEPTXF2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF2 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF2_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs new file mode 100644 index 0000000..8eaba75 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](index.html) module"] +pub struct DIEPTXF3_SPEC; +impl crate::RegisterSpec for DIEPTXF3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf3::R](R) reader structure"] +impl crate::Readable for DIEPTXF3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf3::W](W) writer structure"] +impl crate::Writable for DIEPTXF3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF3 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF3_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs new file mode 100644 index 0000000..6b30646 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](index.html) module"] +pub struct DIEPTXF4_SPEC; +impl crate::RegisterSpec for DIEPTXF4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf4::R](R) reader structure"] +impl crate::Readable for DIEPTXF4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf4::W](W) writer structure"] +impl crate::Writable for DIEPTXF4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF4 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF4_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs new file mode 100644 index 0000000..e2b7d98 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](index.html) module"] +pub struct DIEPTXF5_SPEC; +impl crate::RegisterSpec for DIEPTXF5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf5::R](R) reader structure"] +impl crate::Readable for DIEPTXF5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf5::W](W) writer structure"] +impl crate::Writable for DIEPTXF5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF5 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF5_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs new file mode 100644 index 0000000..da38751 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](index.html) module"] +pub struct DIEPTXF6_SPEC; +impl crate::RegisterSpec for DIEPTXF6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf6::R](R) reader structure"] +impl crate::Readable for DIEPTXF6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf6::W](W) writer structure"] +impl crate::Writable for DIEPTXF6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF6 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF6_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs new file mode 100644 index 0000000..811d528 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DIEPTXF7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIEPTXF7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_R = crate::FieldReader; +#[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] +pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +#[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] +pub type INEPTXFD_R = crate::FieldReader; +#[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] +pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + pub fn ineptxsa(&self) -> INEPTXSA_R { + INEPTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + pub fn ineptxfd(&self) -> INEPTXFD_R { + INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + INEPTXSA_W::new(self) + } + #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + INEPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf7](index.html) module"] +pub struct DIEPTXF7_SPEC; +impl crate::RegisterSpec for DIEPTXF7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dieptxf7::R](R) reader structure"] +impl crate::Readable for DIEPTXF7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dieptxf7::W](W) writer structure"] +impl crate::Writable for DIEPTXF7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIEPTXF7 to value 0x0200_0400"] +impl crate::Resettable for DIEPTXF7_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0400; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs b/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs new file mode 100644 index 0000000..987d389 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs @@ -0,0 +1,230 @@ +#[doc = "Register `GAHBCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAHBCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GINT` reader - Global interrupt mask"] +pub type GINT_R = crate::BitReader; +#[doc = "Field `GINT` writer - Global interrupt mask"] +pub type GINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `AXI_BURST` reader - Maximum AXI burst length"] +pub type AXI_BURST_R = crate::FieldReader; +#[doc = "Maximum AXI burst length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BURST_A { + #[doc = "0: `0`"] + _4 = 0, + #[doc = "1: `1`"] + _3 = 1, + #[doc = "2: `10`"] + _2 = 2, + #[doc = "3: `11`"] + _1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BURST_A) -> Self { + variant as _ + } +} +impl AXI_BURST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BURST_A { + match self.bits { + 0 => BURST_A::_4, + 1 => BURST_A::_3, + 2 => BURST_A::_2, + 3 => BURST_A::_1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == BURST_A::_4 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + *self == BURST_A::_3 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == BURST_A::_2 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == BURST_A::_1 + } +} +#[doc = "Field `AXI_BURST` writer - Maximum AXI burst length"] +pub type AXI_BURST_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GAHBCFG_SPEC, u8, BURST_A, 2, O>; +impl<'a, const O: u8> AXI_BURST_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(BURST_A::_4) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _3(self) -> &'a mut W { + self.variant(BURST_A::_3) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(BURST_A::_2) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(BURST_A::_1) + } +} +#[doc = "Field `AXI_WAIT` reader - Wait for all AXI writes before signaling DMA"] +pub type AXI_WAIT_R = crate::BitReader; +#[doc = "Field `AXI_WAIT` writer - Wait for all AXI writes before signaling DMA"] +pub type AXI_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - DMA enable"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - DMA enable"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `TXFELVL` reader - TxFIFO empty level"] +pub type TXFELVL_R = crate::BitReader; +#[doc = "Field `TXFELVL` writer - TxFIFO empty level"] +pub type TXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +#[doc = "Field `PTXFELVL` reader - Periodic TxFIFO empty level"] +pub type PTXFELVL_R = crate::BitReader; +#[doc = "Field `PTXFELVL` writer - Periodic TxFIFO empty level"] +pub type PTXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Global interrupt mask"] + #[inline(always)] + pub fn gint(&self) -> GINT_R { + GINT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Maximum AXI burst length"] + #[inline(always)] + pub fn axi_burst(&self) -> AXI_BURST_R { + AXI_BURST_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] + #[inline(always)] + pub fn axi_wait(&self) -> AXI_WAIT_R { + AXI_WAIT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DMA enable"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - TxFIFO empty level"] + #[inline(always)] + pub fn txfelvl(&self) -> TXFELVL_R { + TXFELVL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Periodic TxFIFO empty level"] + #[inline(always)] + pub fn ptxfelvl(&self) -> PTXFELVL_R { + PTXFELVL_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Global interrupt mask"] + #[inline(always)] + #[must_use] + pub fn gint(&mut self) -> GINT_W<0> { + GINT_W::new(self) + } + #[doc = "Bits 1:2 - Maximum AXI burst length"] + #[inline(always)] + #[must_use] + pub fn axi_burst(&mut self) -> AXI_BURST_W<1> { + AXI_BURST_W::new(self) + } + #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] + #[inline(always)] + #[must_use] + pub fn axi_wait(&mut self) -> AXI_WAIT_W<4> { + AXI_WAIT_W::new(self) + } + #[doc = "Bit 5 - DMA enable"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<5> { + DMAEN_W::new(self) + } + #[doc = "Bit 7 - TxFIFO empty level"] + #[inline(always)] + #[must_use] + pub fn txfelvl(&mut self) -> TXFELVL_W<7> { + TXFELVL_W::new(self) + } + #[doc = "Bit 8 - Periodic TxFIFO empty level"] + #[inline(always)] + #[must_use] + pub fn ptxfelvl(&mut self) -> PTXFELVL_W<8> { + PTXFELVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS AHB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](index.html) module"] +pub struct GAHBCFG_SPEC; +impl crate::RegisterSpec for GAHBCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gahbcfg::R](R) reader structure"] +impl crate::Readable for GAHBCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gahbcfg::W](W) writer structure"] +impl crate::Writable for GAHBCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAHBCFG to value 0"] +impl crate::Resettable for GAHBCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs b/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs new file mode 100644 index 0000000..4dbbf5c --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs @@ -0,0 +1,155 @@ +#[doc = "Register `GCCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GCCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWRDWN` reader - Power down"] +pub type PWRDWN_R = crate::BitReader; +#[doc = "Field `PWRDWN` writer - Power down"] +pub type PWRDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `I2CPADEN` reader - Enable I2C bus connection for the external I2C PHY interface"] +pub type I2CPADEN_R = crate::BitReader; +#[doc = "Field `I2CPADEN` writer - Enable I2C bus connection for the external I2C PHY interface"] +pub type I2CPADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `VBUSASEN` reader - Enable the VBUS sensing device"] +pub type VBUSASEN_R = crate::BitReader; +#[doc = "Field `VBUSASEN` writer - Enable the VBUS sensing device"] +pub type VBUSASEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `VBUSBSEN` reader - Enable the VBUS sensing device"] +pub type VBUSBSEN_R = crate::BitReader; +#[doc = "Field `VBUSBSEN` writer - Enable the VBUS sensing device"] +pub type VBUSBSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `SOFOUTEN` reader - SOF output enable"] +pub type SOFOUTEN_R = crate::BitReader; +#[doc = "Field `SOFOUTEN` writer - SOF output enable"] +pub type SOFOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +#[doc = "Field `NOVBUSSENS` reader - VBUS sensing disable option"] +pub type NOVBUSSENS_R = crate::BitReader; +#[doc = "Field `NOVBUSSENS` writer - VBUS sensing disable option"] +pub type NOVBUSSENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +impl R { + #[doc = "Bit 16 - Power down"] + #[inline(always)] + pub fn pwrdwn(&self) -> PWRDWN_R { + PWRDWN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] + #[inline(always)] + pub fn i2cpaden(&self) -> I2CPADEN_R { + I2CPADEN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable the VBUS sensing device"] + #[inline(always)] + pub fn vbusasen(&self) -> VBUSASEN_R { + VBUSASEN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable the VBUS sensing device"] + #[inline(always)] + pub fn vbusbsen(&self) -> VBUSBSEN_R { + VBUSBSEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - SOF output enable"] + #[inline(always)] + pub fn sofouten(&self) -> SOFOUTEN_R { + SOFOUTEN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - VBUS sensing disable option"] + #[inline(always)] + pub fn novbussens(&self) -> NOVBUSSENS_R { + NOVBUSSENS_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 16 - Power down"] + #[inline(always)] + #[must_use] + pub fn pwrdwn(&mut self) -> PWRDWN_W<16> { + PWRDWN_W::new(self) + } + #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] + #[inline(always)] + #[must_use] + pub fn i2cpaden(&mut self) -> I2CPADEN_W<17> { + I2CPADEN_W::new(self) + } + #[doc = "Bit 18 - Enable the VBUS sensing device"] + #[inline(always)] + #[must_use] + pub fn vbusasen(&mut self) -> VBUSASEN_W<18> { + VBUSASEN_W::new(self) + } + #[doc = "Bit 19 - Enable the VBUS sensing device"] + #[inline(always)] + #[must_use] + pub fn vbusbsen(&mut self) -> VBUSBSEN_W<19> { + VBUSBSEN_W::new(self) + } + #[doc = "Bit 20 - SOF output enable"] + #[inline(always)] + #[must_use] + pub fn sofouten(&mut self) -> SOFOUTEN_W<20> { + SOFOUTEN_W::new(self) + } + #[doc = "Bit 21 - VBUS sensing disable option"] + #[inline(always)] + #[must_use] + pub fn novbussens(&mut self) -> NOVBUSSENS_W<21> { + NOVBUSSENS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS general core configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gccfg](index.html) module"] +pub struct GCCFG_SPEC; +impl crate::RegisterSpec for GCCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gccfg::R](R) reader structure"] +impl crate::Readable for GCCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gccfg::W](W) writer structure"] +impl crate::Writable for GCCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GCCFG to value 0"] +impl crate::Resettable for GCCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs new file mode 100644 index 0000000..d3fdb2d --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs @@ -0,0 +1,447 @@ +#[doc = "Register `GINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MMISM` reader - Mode mismatch interrupt mask"] +pub type MMISM_R = crate::BitReader; +#[doc = "Field `MMISM` writer - Mode mismatch interrupt mask"] +pub type MMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `OTGINT` reader - OTG interrupt mask"] +pub type OTGINT_R = crate::BitReader; +#[doc = "Field `OTGINT` writer - OTG interrupt mask"] +pub type OTGINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `SOFM` reader - Start of frame mask"] +pub type SOFM_R = crate::BitReader; +#[doc = "Field `SOFM` writer - Start of frame mask"] +pub type SOFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `RXFLVLM` reader - Receive FIFO nonempty mask"] +pub type RXFLVLM_R = crate::BitReader; +#[doc = "Field `RXFLVLM` writer - Receive FIFO nonempty mask"] +pub type RXFLVLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `NPTXFEM` reader - Nonperiodic TxFIFO empty mask"] +pub type NPTXFEM_R = crate::BitReader; +#[doc = "Field `NPTXFEM` writer - Nonperiodic TxFIFO empty mask"] +pub type NPTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `GINAKEFFM` reader - Global nonperiodic IN NAK effective mask"] +pub type GINAKEFFM_R = crate::BitReader; +#[doc = "Field `GINAKEFFM` writer - Global nonperiodic IN NAK effective mask"] +pub type GINAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `GONAKEFFM` reader - Global OUT NAK effective mask"] +pub type GONAKEFFM_R = crate::BitReader; +#[doc = "Field `GONAKEFFM` writer - Global OUT NAK effective mask"] +pub type GONAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ESUSPM` reader - Early suspend mask"] +pub type ESUSPM_R = crate::BitReader; +#[doc = "Field `ESUSPM` writer - Early suspend mask"] +pub type ESUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `USBSUSPM` reader - USB suspend mask"] +pub type USBSUSPM_R = crate::BitReader; +#[doc = "Field `USBSUSPM` writer - USB suspend mask"] +pub type USBSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `USBRST` reader - USB reset mask"] +pub type USBRST_R = crate::BitReader; +#[doc = "Field `USBRST` writer - USB reset mask"] +pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ENUMDNEM` reader - Enumeration done mask"] +pub type ENUMDNEM_R = crate::BitReader; +#[doc = "Field `ENUMDNEM` writer - Enumeration done mask"] +pub type ENUMDNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `ISOODRPM` reader - Isochronous OUT packet dropped interrupt mask"] +pub type ISOODRPM_R = crate::BitReader; +#[doc = "Field `ISOODRPM` writer - Isochronous OUT packet dropped interrupt mask"] +pub type ISOODRPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `EOPFM` reader - End of periodic frame interrupt mask"] +pub type EOPFM_R = crate::BitReader; +#[doc = "Field `EOPFM` writer - End of periodic frame interrupt mask"] +pub type EOPFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `EPMISM` reader - Endpoint mismatch interrupt mask"] +pub type EPMISM_R = crate::BitReader; +#[doc = "Field `EPMISM` writer - Endpoint mismatch interrupt mask"] +pub type EPMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `IEPINT` reader - IN endpoints interrupt mask"] +pub type IEPINT_R = crate::BitReader; +#[doc = "Field `IEPINT` writer - IN endpoints interrupt mask"] +pub type IEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `OEPINT` reader - OUT endpoints interrupt mask"] +pub type OEPINT_R = crate::BitReader; +#[doc = "Field `OEPINT` writer - OUT endpoints interrupt mask"] +pub type OEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `IISOIXFRM` reader - Incomplete isochronous IN transfer mask"] +pub type IISOIXFRM_R = crate::BitReader; +#[doc = "Field `IISOIXFRM` writer - Incomplete isochronous IN transfer mask"] +pub type IISOIXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PXFRM_IISOOXFRM` reader - Incomplete periodic transfer mask"] +pub type PXFRM_IISOOXFRM_R = crate::BitReader; +#[doc = "Field `PXFRM_IISOOXFRM` writer - Incomplete periodic transfer mask"] +pub type PXFRM_IISOOXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `FSUSPM` reader - Data fetch suspended mask"] +pub type FSUSPM_R = crate::BitReader; +#[doc = "Field `FSUSPM` writer - Data fetch suspended mask"] +pub type FSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PRTIM` reader - Host port interrupt mask"] +pub type PRTIM_R = crate::BitReader; +#[doc = "Field `HCIM` reader - Host channels interrupt mask"] +pub type HCIM_R = crate::BitReader; +#[doc = "Field `HCIM` writer - Host channels interrupt mask"] +pub type HCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `PTXFEM` reader - Periodic TxFIFO empty mask"] +pub type PTXFEM_R = crate::BitReader; +#[doc = "Field `PTXFEM` writer - Periodic TxFIFO empty mask"] +pub type PTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `CIDSCHGM` reader - Connector ID status change mask"] +pub type CIDSCHGM_R = crate::BitReader; +#[doc = "Field `CIDSCHGM` writer - Connector ID status change mask"] +pub type CIDSCHGM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `DISCINT` reader - Disconnect detected interrupt mask"] +pub type DISCINT_R = crate::BitReader; +#[doc = "Field `DISCINT` writer - Disconnect detected interrupt mask"] +pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `SRQIM` reader - Session request/new session detected interrupt mask"] +pub type SRQIM_R = crate::BitReader; +#[doc = "Field `SRQIM` writer - Session request/new session detected interrupt mask"] +pub type SRQIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +#[doc = "Field `WUIM` reader - Resume/remote wakeup detected interrupt mask"] +pub type WUIM_R = crate::BitReader; +#[doc = "Field `WUIM` writer - Resume/remote wakeup detected interrupt mask"] +pub type WUIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Mode mismatch interrupt mask"] + #[inline(always)] + pub fn mmism(&self) -> MMISM_R { + MMISM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OTG interrupt mask"] + #[inline(always)] + pub fn otgint(&self) -> OTGINT_R { + OTGINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start of frame mask"] + #[inline(always)] + pub fn sofm(&self) -> SOFM_R { + SOFM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO nonempty mask"] + #[inline(always)] + pub fn rxflvlm(&self) -> RXFLVLM_R { + RXFLVLM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] + #[inline(always)] + pub fn nptxfem(&self) -> NPTXFEM_R { + NPTXFEM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] + #[inline(always)] + pub fn ginakeffm(&self) -> GINAKEFFM_R { + GINAKEFFM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global OUT NAK effective mask"] + #[inline(always)] + pub fn gonakeffm(&self) -> GONAKEFFM_R { + GONAKEFFM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Early suspend mask"] + #[inline(always)] + pub fn esuspm(&self) -> ESUSPM_R { + ESUSPM_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB suspend mask"] + #[inline(always)] + pub fn usbsuspm(&self) -> USBSUSPM_R { + USBSUSPM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - USB reset mask"] + #[inline(always)] + pub fn usbrst(&self) -> USBRST_R { + USBRST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enumeration done mask"] + #[inline(always)] + pub fn enumdnem(&self) -> ENUMDNEM_R { + ENUMDNEM_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] + #[inline(always)] + pub fn isoodrpm(&self) -> ISOODRPM_R { + ISOODRPM_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - End of periodic frame interrupt mask"] + #[inline(always)] + pub fn eopfm(&self) -> EOPFM_R { + EOPFM_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] + #[inline(always)] + pub fn epmism(&self) -> EPMISM_R { + EPMISM_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - IN endpoints interrupt mask"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OUT endpoints interrupt mask"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] + #[inline(always)] + pub fn iisoixfrm(&self) -> IISOIXFRM_R { + IISOIXFRM_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Incomplete periodic transfer mask"] + #[inline(always)] + pub fn pxfrm_iisooxfrm(&self) -> PXFRM_IISOOXFRM_R { + PXFRM_IISOOXFRM_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data fetch suspended mask"] + #[inline(always)] + pub fn fsuspm(&self) -> FSUSPM_R { + FSUSPM_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Host port interrupt mask"] + #[inline(always)] + pub fn prtim(&self) -> PRTIM_R { + PRTIM_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Host channels interrupt mask"] + #[inline(always)] + pub fn hcim(&self) -> HCIM_R { + HCIM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Periodic TxFIFO empty mask"] + #[inline(always)] + pub fn ptxfem(&self) -> PTXFEM_R { + PTXFEM_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Connector ID status change mask"] + #[inline(always)] + pub fn cidschgm(&self) -> CIDSCHGM_R { + CIDSCHGM_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Disconnect detected interrupt mask"] + #[inline(always)] + pub fn discint(&self) -> DISCINT_R { + DISCINT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Session request/new session detected interrupt mask"] + #[inline(always)] + pub fn srqim(&self) -> SRQIM_R { + SRQIM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] + #[inline(always)] + pub fn wuim(&self) -> WUIM_R { + WUIM_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Mode mismatch interrupt mask"] + #[inline(always)] + #[must_use] + pub fn mmism(&mut self) -> MMISM_W<1> { + MMISM_W::new(self) + } + #[doc = "Bit 2 - OTG interrupt mask"] + #[inline(always)] + #[must_use] + pub fn otgint(&mut self) -> OTGINT_W<2> { + OTGINT_W::new(self) + } + #[doc = "Bit 3 - Start of frame mask"] + #[inline(always)] + #[must_use] + pub fn sofm(&mut self) -> SOFM_W<3> { + SOFM_W::new(self) + } + #[doc = "Bit 4 - Receive FIFO nonempty mask"] + #[inline(always)] + #[must_use] + pub fn rxflvlm(&mut self) -> RXFLVLM_W<4> { + RXFLVLM_W::new(self) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn nptxfem(&mut self) -> NPTXFEM_W<5> { + NPTXFEM_W::new(self) + } + #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn ginakeffm(&mut self) -> GINAKEFFM_W<6> { + GINAKEFFM_W::new(self) + } + #[doc = "Bit 7 - Global OUT NAK effective mask"] + #[inline(always)] + #[must_use] + pub fn gonakeffm(&mut self) -> GONAKEFFM_W<7> { + GONAKEFFM_W::new(self) + } + #[doc = "Bit 10 - Early suspend mask"] + #[inline(always)] + #[must_use] + pub fn esuspm(&mut self) -> ESUSPM_W<10> { + ESUSPM_W::new(self) + } + #[doc = "Bit 11 - USB suspend mask"] + #[inline(always)] + #[must_use] + pub fn usbsuspm(&mut self) -> USBSUSPM_W<11> { + USBSUSPM_W::new(self) + } + #[doc = "Bit 12 - USB reset mask"] + #[inline(always)] + #[must_use] + pub fn usbrst(&mut self) -> USBRST_W<12> { + USBRST_W::new(self) + } + #[doc = "Bit 13 - Enumeration done mask"] + #[inline(always)] + #[must_use] + pub fn enumdnem(&mut self) -> ENUMDNEM_W<13> { + ENUMDNEM_W::new(self) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] + #[inline(always)] + #[must_use] + pub fn isoodrpm(&mut self) -> ISOODRPM_W<14> { + ISOODRPM_W::new(self) + } + #[doc = "Bit 15 - End of periodic frame interrupt mask"] + #[inline(always)] + #[must_use] + pub fn eopfm(&mut self) -> EOPFM_W<15> { + EOPFM_W::new(self) + } + #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] + #[inline(always)] + #[must_use] + pub fn epmism(&mut self) -> EPMISM_W<17> { + EPMISM_W::new(self) + } + #[doc = "Bit 18 - IN endpoints interrupt mask"] + #[inline(always)] + #[must_use] + pub fn iepint(&mut self) -> IEPINT_W<18> { + IEPINT_W::new(self) + } + #[doc = "Bit 19 - OUT endpoints interrupt mask"] + #[inline(always)] + #[must_use] + pub fn oepint(&mut self) -> OEPINT_W<19> { + OEPINT_W::new(self) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] + #[inline(always)] + #[must_use] + pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<20> { + IISOIXFRM_W::new(self) + } + #[doc = "Bit 21 - Incomplete periodic transfer mask"] + #[inline(always)] + #[must_use] + pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<21> { + PXFRM_IISOOXFRM_W::new(self) + } + #[doc = "Bit 22 - Data fetch suspended mask"] + #[inline(always)] + #[must_use] + pub fn fsuspm(&mut self) -> FSUSPM_W<22> { + FSUSPM_W::new(self) + } + #[doc = "Bit 25 - Host channels interrupt mask"] + #[inline(always)] + #[must_use] + pub fn hcim(&mut self) -> HCIM_W<25> { + HCIM_W::new(self) + } + #[doc = "Bit 26 - Periodic TxFIFO empty mask"] + #[inline(always)] + #[must_use] + pub fn ptxfem(&mut self) -> PTXFEM_W<26> { + PTXFEM_W::new(self) + } + #[doc = "Bit 28 - Connector ID status change mask"] + #[inline(always)] + #[must_use] + pub fn cidschgm(&mut self) -> CIDSCHGM_W<28> { + CIDSCHGM_W::new(self) + } + #[doc = "Bit 29 - Disconnect detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn discint(&mut self) -> DISCINT_W<29> { + DISCINT_W::new(self) + } + #[doc = "Bit 30 - Session request/new session detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn srqim(&mut self) -> SRQIM_W<30> { + SRQIM_W::new(self) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] + #[inline(always)] + #[must_use] + pub fn wuim(&mut self) -> WUIM_W<31> { + WUIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](index.html) module"] +pub struct GINTMSK_SPEC; +impl crate::RegisterSpec for GINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gintmsk::R](R) reader structure"] +impl crate::Readable for GINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gintmsk::W](W) writer structure"] +impl crate::Writable for GINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GINTMSK to value 0"] +impl crate::Resettable for GINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs b/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs new file mode 100644 index 0000000..4dd3aa9 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs @@ -0,0 +1,367 @@ +#[doc = "Register `GINTSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GINTSTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMOD` reader - Current mode of operation"] +pub type CMOD_R = crate::BitReader; +#[doc = "Field `MMIS` reader - Mode mismatch interrupt"] +pub type MMIS_R = crate::BitReader; +#[doc = "Field `MMIS` writer - Mode mismatch interrupt"] +pub type MMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `OTGINT` reader - OTG interrupt"] +pub type OTGINT_R = crate::BitReader; +#[doc = "Field `SOF` reader - Start of frame"] +pub type SOF_R = crate::BitReader; +#[doc = "Field `SOF` writer - Start of frame"] +pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `RXFLVL` reader - RxFIFO nonempty"] +pub type RXFLVL_R = crate::BitReader; +#[doc = "Field `NPTXFE` reader - Nonperiodic TxFIFO empty"] +pub type NPTXFE_R = crate::BitReader; +#[doc = "Field `GINAKEFF` reader - Global IN nonperiodic NAK effective"] +pub type GINAKEFF_R = crate::BitReader; +#[doc = "Field `BOUTNAKEFF` reader - Global OUT NAK effective"] +pub type BOUTNAKEFF_R = crate::BitReader; +#[doc = "Field `ESUSP` reader - Early suspend"] +pub type ESUSP_R = crate::BitReader; +#[doc = "Field `ESUSP` writer - Early suspend"] +pub type ESUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `USBSUSP` reader - USB suspend"] +pub type USBSUSP_R = crate::BitReader; +#[doc = "Field `USBSUSP` writer - USB suspend"] +pub type USBSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `USBRST` reader - USB reset"] +pub type USBRST_R = crate::BitReader; +#[doc = "Field `USBRST` writer - USB reset"] +pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `ENUMDNE` reader - Enumeration done"] +pub type ENUMDNE_R = crate::BitReader; +#[doc = "Field `ENUMDNE` writer - Enumeration done"] +pub type ENUMDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `ISOODRP` reader - Isochronous OUT packet dropped interrupt"] +pub type ISOODRP_R = crate::BitReader; +#[doc = "Field `ISOODRP` writer - Isochronous OUT packet dropped interrupt"] +pub type ISOODRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `EOPF` reader - End of periodic frame interrupt"] +pub type EOPF_R = crate::BitReader; +#[doc = "Field `EOPF` writer - End of periodic frame interrupt"] +pub type EOPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `IEPINT` reader - IN endpoint interrupt"] +pub type IEPINT_R = crate::BitReader; +#[doc = "Field `OEPINT` reader - OUT endpoint interrupt"] +pub type OEPINT_R = crate::BitReader; +#[doc = "Field `IISOIXFR` reader - Incomplete isochronous IN transfer"] +pub type IISOIXFR_R = crate::BitReader; +#[doc = "Field `IISOIXFR` writer - Incomplete isochronous IN transfer"] +pub type IISOIXFR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `PXFR_INCOMPISOOUT` reader - Incomplete periodic transfer"] +pub type PXFR_INCOMPISOOUT_R = crate::BitReader; +#[doc = "Field `PXFR_INCOMPISOOUT` writer - Incomplete periodic transfer"] +pub type PXFR_INCOMPISOOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `DATAFSUSP` reader - Data fetch suspended"] +pub type DATAFSUSP_R = crate::BitReader; +#[doc = "Field `DATAFSUSP` writer - Data fetch suspended"] +pub type DATAFSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `HPRTINT` reader - Host port interrupt"] +pub type HPRTINT_R = crate::BitReader; +#[doc = "Field `HCINT` reader - Host channels interrupt"] +pub type HCINT_R = crate::BitReader; +#[doc = "Field `PTXFE` reader - Periodic TxFIFO empty"] +pub type PTXFE_R = crate::BitReader; +#[doc = "Field `CIDSCHG` reader - Connector ID status change"] +pub type CIDSCHG_R = crate::BitReader; +#[doc = "Field `CIDSCHG` writer - Connector ID status change"] +pub type CIDSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `DISCINT` reader - Disconnect detected interrupt"] +pub type DISCINT_R = crate::BitReader; +#[doc = "Field `DISCINT` writer - Disconnect detected interrupt"] +pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `SRQINT` reader - Session request/new session detected interrupt"] +pub type SRQINT_R = crate::BitReader; +#[doc = "Field `SRQINT` writer - Session request/new session detected interrupt"] +pub type SRQINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +#[doc = "Field `WKUINT` reader - Resume/remote wakeup detected interrupt"] +pub type WKUINT_R = crate::BitReader; +#[doc = "Field `WKUINT` writer - Resume/remote wakeup detected interrupt"] +pub type WKUINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Current mode of operation"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mode mismatch interrupt"] + #[inline(always)] + pub fn mmis(&self) -> MMIS_R { + MMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - OTG interrupt"] + #[inline(always)] + pub fn otgint(&self) -> OTGINT_R { + OTGINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start of frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RxFIFO nonempty"] + #[inline(always)] + pub fn rxflvl(&self) -> RXFLVL_R { + RXFLVL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Nonperiodic TxFIFO empty"] + #[inline(always)] + pub fn nptxfe(&self) -> NPTXFE_R { + NPTXFE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Global IN nonperiodic NAK effective"] + #[inline(always)] + pub fn ginakeff(&self) -> GINAKEFF_R { + GINAKEFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Global OUT NAK effective"] + #[inline(always)] + pub fn boutnakeff(&self) -> BOUTNAKEFF_R { + BOUTNAKEFF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Early suspend"] + #[inline(always)] + pub fn esusp(&self) -> ESUSP_R { + ESUSP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - USB suspend"] + #[inline(always)] + pub fn usbsusp(&self) -> USBSUSP_R { + USBSUSP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - USB reset"] + #[inline(always)] + pub fn usbrst(&self) -> USBRST_R { + USBRST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enumeration done"] + #[inline(always)] + pub fn enumdne(&self) -> ENUMDNE_R { + ENUMDNE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] + #[inline(always)] + pub fn isoodrp(&self) -> ISOODRP_R { + ISOODRP_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - End of periodic frame interrupt"] + #[inline(always)] + pub fn eopf(&self) -> EOPF_R { + EOPF_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 18 - IN endpoint interrupt"] + #[inline(always)] + pub fn iepint(&self) -> IEPINT_R { + IEPINT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - OUT endpoint interrupt"] + #[inline(always)] + pub fn oepint(&self) -> OEPINT_R { + OEPINT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer"] + #[inline(always)] + pub fn iisoixfr(&self) -> IISOIXFR_R { + IISOIXFR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Incomplete periodic transfer"] + #[inline(always)] + pub fn pxfr_incompisoout(&self) -> PXFR_INCOMPISOOUT_R { + PXFR_INCOMPISOOUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Data fetch suspended"] + #[inline(always)] + pub fn datafsusp(&self) -> DATAFSUSP_R { + DATAFSUSP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Host port interrupt"] + #[inline(always)] + pub fn hprtint(&self) -> HPRTINT_R { + HPRTINT_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Host channels interrupt"] + #[inline(always)] + pub fn hcint(&self) -> HCINT_R { + HCINT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Periodic TxFIFO empty"] + #[inline(always)] + pub fn ptxfe(&self) -> PTXFE_R { + PTXFE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Connector ID status change"] + #[inline(always)] + pub fn cidschg(&self) -> CIDSCHG_R { + CIDSCHG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Disconnect detected interrupt"] + #[inline(always)] + pub fn discint(&self) -> DISCINT_R { + DISCINT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Session request/new session detected interrupt"] + #[inline(always)] + pub fn srqint(&self) -> SRQINT_R { + SRQINT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] + #[inline(always)] + pub fn wkuint(&self) -> WKUINT_R { + WKUINT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Mode mismatch interrupt"] + #[inline(always)] + #[must_use] + pub fn mmis(&mut self) -> MMIS_W<1> { + MMIS_W::new(self) + } + #[doc = "Bit 3 - Start of frame"] + #[inline(always)] + #[must_use] + pub fn sof(&mut self) -> SOF_W<3> { + SOF_W::new(self) + } + #[doc = "Bit 10 - Early suspend"] + #[inline(always)] + #[must_use] + pub fn esusp(&mut self) -> ESUSP_W<10> { + ESUSP_W::new(self) + } + #[doc = "Bit 11 - USB suspend"] + #[inline(always)] + #[must_use] + pub fn usbsusp(&mut self) -> USBSUSP_W<11> { + USBSUSP_W::new(self) + } + #[doc = "Bit 12 - USB reset"] + #[inline(always)] + #[must_use] + pub fn usbrst(&mut self) -> USBRST_W<12> { + USBRST_W::new(self) + } + #[doc = "Bit 13 - Enumeration done"] + #[inline(always)] + #[must_use] + pub fn enumdne(&mut self) -> ENUMDNE_W<13> { + ENUMDNE_W::new(self) + } + #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] + #[inline(always)] + #[must_use] + pub fn isoodrp(&mut self) -> ISOODRP_W<14> { + ISOODRP_W::new(self) + } + #[doc = "Bit 15 - End of periodic frame interrupt"] + #[inline(always)] + #[must_use] + pub fn eopf(&mut self) -> EOPF_W<15> { + EOPF_W::new(self) + } + #[doc = "Bit 20 - Incomplete isochronous IN transfer"] + #[inline(always)] + #[must_use] + pub fn iisoixfr(&mut self) -> IISOIXFR_W<20> { + IISOIXFR_W::new(self) + } + #[doc = "Bit 21 - Incomplete periodic transfer"] + #[inline(always)] + #[must_use] + pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<21> { + PXFR_INCOMPISOOUT_W::new(self) + } + #[doc = "Bit 22 - Data fetch suspended"] + #[inline(always)] + #[must_use] + pub fn datafsusp(&mut self) -> DATAFSUSP_W<22> { + DATAFSUSP_W::new(self) + } + #[doc = "Bit 28 - Connector ID status change"] + #[inline(always)] + #[must_use] + pub fn cidschg(&mut self) -> CIDSCHG_W<28> { + CIDSCHG_W::new(self) + } + #[doc = "Bit 29 - Disconnect detected interrupt"] + #[inline(always)] + #[must_use] + pub fn discint(&mut self) -> DISCINT_W<29> { + DISCINT_W::new(self) + } + #[doc = "Bit 30 - Session request/new session detected interrupt"] + #[inline(always)] + #[must_use] + pub fn srqint(&mut self) -> SRQINT_W<30> { + SRQINT_W::new(self) + } + #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] + #[inline(always)] + #[must_use] + pub fn wkuint(&mut self) -> WKUINT_W<31> { + WKUINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS core interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](index.html) module"] +pub struct GINTSTS_SPEC; +impl crate::RegisterSpec for GINTSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gintsts::R](R) reader structure"] +impl crate::Readable for GINTSTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gintsts::W](W) writer structure"] +impl crate::Writable for GINTSTS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GINTSTS to value 0x0400_0020"] +impl crate::Resettable for GINTSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0020; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs b/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs new file mode 100644 index 0000000..89a5540 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs @@ -0,0 +1,97 @@ +#[doc = "Register `GNPTXFSIZ_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GNPTXFSIZ_Host` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NPTXFSA` reader - Nonperiodic transmit RAM start address"] +pub type NPTXFSA_R = crate::FieldReader; +#[doc = "Field `NPTXFSA` writer - Nonperiodic transmit RAM start address"] +pub type NPTXFSA_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +#[doc = "Field `NPTXFD` reader - Nonperiodic TxFIFO depth"] +pub type NPTXFD_R = crate::FieldReader; +#[doc = "Field `NPTXFD` writer - Nonperiodic TxFIFO depth"] +pub type NPTXFD_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] + #[inline(always)] + pub fn nptxfsa(&self) -> NPTXFSA_R { + NPTXFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] + #[inline(always)] + pub fn nptxfd(&self) -> NPTXFD_R { + NPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn nptxfsa(&mut self) -> NPTXFSA_W<0> { + NPTXFSA_W::new(self) + } + #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn nptxfd(&mut self) -> NPTXFD_W<16> { + NPTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz_host](index.html) module"] +pub struct GNPTXFSIZ_HOST_SPEC; +impl crate::RegisterSpec for GNPTXFSIZ_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gnptxfsiz_host::R](R) reader structure"] +impl crate::Readable for GNPTXFSIZ_HOST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gnptxfsiz_host::W](W) writer structure"] +impl crate::Writable for GNPTXFSIZ_HOST_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GNPTXFSIZ_Host to value 0x0200"] +impl crate::Resettable for GNPTXFSIZ_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs b/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs new file mode 100644 index 0000000..65ffd12 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs @@ -0,0 +1,51 @@ +#[doc = "Register `GNPTXSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `NPTXFSAV` reader - Nonperiodic TxFIFO space available"] +pub type NPTXFSAV_R = crate::FieldReader; +#[doc = "Field `NPTQXSAV` reader - Nonperiodic transmit request queue space available"] +pub type NPTQXSAV_R = crate::FieldReader; +#[doc = "Field `NPTXQTOP` reader - Top of the nonperiodic transmit request queue"] +pub type NPTXQTOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Nonperiodic TxFIFO space available"] + #[inline(always)] + pub fn nptxfsav(&self) -> NPTXFSAV_R { + NPTXFSAV_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Nonperiodic transmit request queue space available"] + #[inline(always)] + pub fn nptqxsav(&self) -> NPTQXSAV_R { + NPTQXSAV_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:30 - Top of the nonperiodic transmit request queue"] + #[inline(always)] + pub fn nptxqtop(&self) -> NPTXQTOP_R { + NPTXQTOP_R::new(((self.bits >> 24) & 0x7f) as u8) + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](index.html) module"] +pub struct GNPTXSTS_SPEC; +impl crate::RegisterSpec for GNPTXSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gnptxsts::R](R) reader structure"] +impl crate::Readable for GNPTXSTS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GNPTXSTS to value 0x0008_0200"] +impl crate::Resettable for GNPTXSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0200; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs b/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs new file mode 100644 index 0000000..6576636 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs @@ -0,0 +1,167 @@ +#[doc = "Register `GOTGCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GOTGCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRQSCS` reader - Session request success"] +pub type SRQSCS_R = crate::BitReader; +#[doc = "Field `SRQ` reader - Session request"] +pub type SRQ_R = crate::BitReader; +#[doc = "Field `SRQ` writer - Session request"] +pub type SRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `HNGSCS` reader - Host negotiation success"] +pub type HNGSCS_R = crate::BitReader; +#[doc = "Field `HNPRQ` reader - HNP request"] +pub type HNPRQ_R = crate::BitReader; +#[doc = "Field `HNPRQ` writer - HNP request"] +pub type HNPRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `HSHNPEN` reader - Host set HNP enable"] +pub type HSHNPEN_R = crate::BitReader; +#[doc = "Field `HSHNPEN` writer - Host set HNP enable"] +pub type HSHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `DHNPEN` reader - Device HNP enabled"] +pub type DHNPEN_R = crate::BitReader; +#[doc = "Field `DHNPEN` writer - Device HNP enabled"] +pub type DHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +#[doc = "Field `CIDSTS` reader - Connector ID status"] +pub type CIDSTS_R = crate::BitReader; +#[doc = "Field `DBCT` reader - Long/short debounce time"] +pub type DBCT_R = crate::BitReader; +#[doc = "Field `ASVLD` reader - A-session valid"] +pub type ASVLD_R = crate::BitReader; +#[doc = "Field `BSVLD` reader - B-session valid"] +pub type BSVLD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Session request success"] + #[inline(always)] + pub fn srqscs(&self) -> SRQSCS_R { + SRQSCS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Session request"] + #[inline(always)] + pub fn srq(&self) -> SRQ_R { + SRQ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Host negotiation success"] + #[inline(always)] + pub fn hngscs(&self) -> HNGSCS_R { + HNGSCS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HNP request"] + #[inline(always)] + pub fn hnprq(&self) -> HNPRQ_R { + HNPRQ_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Host set HNP enable"] + #[inline(always)] + pub fn hshnpen(&self) -> HSHNPEN_R { + HSHNPEN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Device HNP enabled"] + #[inline(always)] + pub fn dhnpen(&self) -> DHNPEN_R { + DHNPEN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Connector ID status"] + #[inline(always)] + pub fn cidsts(&self) -> CIDSTS_R { + CIDSTS_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Long/short debounce time"] + #[inline(always)] + pub fn dbct(&self) -> DBCT_R { + DBCT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - A-session valid"] + #[inline(always)] + pub fn asvld(&self) -> ASVLD_R { + ASVLD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - B-session valid"] + #[inline(always)] + pub fn bsvld(&self) -> BSVLD_R { + BSVLD_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Session request"] + #[inline(always)] + #[must_use] + pub fn srq(&mut self) -> SRQ_W<1> { + SRQ_W::new(self) + } + #[doc = "Bit 9 - HNP request"] + #[inline(always)] + #[must_use] + pub fn hnprq(&mut self) -> HNPRQ_W<9> { + HNPRQ_W::new(self) + } + #[doc = "Bit 10 - Host set HNP enable"] + #[inline(always)] + #[must_use] + pub fn hshnpen(&mut self) -> HSHNPEN_W<10> { + HSHNPEN_W::new(self) + } + #[doc = "Bit 11 - Device HNP enabled"] + #[inline(always)] + #[must_use] + pub fn dhnpen(&mut self) -> DHNPEN_W<11> { + DHNPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](index.html) module"] +pub struct GOTGCTL_SPEC; +impl crate::RegisterSpec for GOTGCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gotgctl::R](R) reader structure"] +impl crate::Readable for GOTGCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gotgctl::W](W) writer structure"] +impl crate::Writable for GOTGCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOTGCTL to value 0x0800"] +impl crate::Resettable for GOTGCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs b/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs new file mode 100644 index 0000000..b2c3ab9 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs @@ -0,0 +1,155 @@ +#[doc = "Register `GOTGINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GOTGINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEDET` reader - Session end detected"] +pub type SEDET_R = crate::BitReader; +#[doc = "Field `SEDET` writer - Session end detected"] +pub type SEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `SRSSCHG` reader - Session request success status change"] +pub type SRSSCHG_R = crate::BitReader; +#[doc = "Field `SRSSCHG` writer - Session request success status change"] +pub type SRSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `HNSSCHG` reader - Host negotiation success status change"] +pub type HNSSCHG_R = crate::BitReader; +#[doc = "Field `HNSSCHG` writer - Host negotiation success status change"] +pub type HNSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `HNGDET` reader - Host negotiation detected"] +pub type HNGDET_R = crate::BitReader; +#[doc = "Field `HNGDET` writer - Host negotiation detected"] +pub type HNGDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `ADTOCHG` reader - A-device timeout change"] +pub type ADTOCHG_R = crate::BitReader; +#[doc = "Field `ADTOCHG` writer - A-device timeout change"] +pub type ADTOCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +#[doc = "Field `DBCDNE` reader - Debounce done"] +pub type DBCDNE_R = crate::BitReader; +#[doc = "Field `DBCDNE` writer - Debounce done"] +pub type DBCDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 2 - Session end detected"] + #[inline(always)] + pub fn sedet(&self) -> SEDET_R { + SEDET_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Session request success status change"] + #[inline(always)] + pub fn srsschg(&self) -> SRSSCHG_R { + SRSSCHG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Host negotiation success status change"] + #[inline(always)] + pub fn hnsschg(&self) -> HNSSCHG_R { + HNSSCHG_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 17 - Host negotiation detected"] + #[inline(always)] + pub fn hngdet(&self) -> HNGDET_R { + HNGDET_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - A-device timeout change"] + #[inline(always)] + pub fn adtochg(&self) -> ADTOCHG_R { + ADTOCHG_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Debounce done"] + #[inline(always)] + pub fn dbcdne(&self) -> DBCDNE_R { + DBCDNE_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Session end detected"] + #[inline(always)] + #[must_use] + pub fn sedet(&mut self) -> SEDET_W<2> { + SEDET_W::new(self) + } + #[doc = "Bit 8 - Session request success status change"] + #[inline(always)] + #[must_use] + pub fn srsschg(&mut self) -> SRSSCHG_W<8> { + SRSSCHG_W::new(self) + } + #[doc = "Bit 9 - Host negotiation success status change"] + #[inline(always)] + #[must_use] + pub fn hnsschg(&mut self) -> HNSSCHG_W<9> { + HNSSCHG_W::new(self) + } + #[doc = "Bit 17 - Host negotiation detected"] + #[inline(always)] + #[must_use] + pub fn hngdet(&mut self) -> HNGDET_W<17> { + HNGDET_W::new(self) + } + #[doc = "Bit 18 - A-device timeout change"] + #[inline(always)] + #[must_use] + pub fn adtochg(&mut self) -> ADTOCHG_W<18> { + ADTOCHG_W::new(self) + } + #[doc = "Bit 19 - Debounce done"] + #[inline(always)] + #[must_use] + pub fn dbcdne(&mut self) -> DBCDNE_W<19> { + DBCDNE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](index.html) module"] +pub struct GOTGINT_SPEC; +impl crate::RegisterSpec for GOTGINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gotgint::R](R) reader structure"] +impl crate::Readable for GOTGINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gotgint::W](W) writer structure"] +impl crate::Writable for GOTGINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOTGINT to value 0"] +impl crate::Resettable for GOTGINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs b/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs new file mode 100644 index 0000000..c3f83dc --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs @@ -0,0 +1,169 @@ +#[doc = "Register `GRSTCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GRSTCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CSRST` reader - Core soft reset"] +pub type CSRST_R = crate::BitReader; +#[doc = "Field `CSRST` writer - Core soft reset"] +pub type CSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `HSRST` reader - HCLK soft reset"] +pub type HSRST_R = crate::BitReader; +#[doc = "Field `HSRST` writer - HCLK soft reset"] +pub type HSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `FCRST` reader - Host frame counter reset"] +pub type FCRST_R = crate::BitReader; +#[doc = "Field `FCRST` writer - Host frame counter reset"] +pub type FCRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `RXFFLSH` reader - RxFIFO flush"] +pub type RXFFLSH_R = crate::BitReader; +#[doc = "Field `RXFFLSH` writer - RxFIFO flush"] +pub type RXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `TXFFLSH` reader - TxFIFO flush"] +pub type TXFFLSH_R = crate::BitReader; +#[doc = "Field `TXFFLSH` writer - TxFIFO flush"] +pub type TXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +#[doc = "Field `TXFNUM` reader - TxFIFO number"] +pub type TXFNUM_R = crate::FieldReader; +#[doc = "Field `TXFNUM` writer - TxFIFO number"] +pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, u8, 5, O>; +#[doc = "Field `DMAREQ` reader - DMA request signal"] +pub type DMAREQ_R = crate::BitReader; +#[doc = "Field `AHBIDL` reader - AHB master idle"] +pub type AHBIDL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Core soft reset"] + #[inline(always)] + pub fn csrst(&self) -> CSRST_R { + CSRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HCLK soft reset"] + #[inline(always)] + pub fn hsrst(&self) -> HSRST_R { + HSRST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host frame counter reset"] + #[inline(always)] + pub fn fcrst(&self) -> FCRST_R { + FCRST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - RxFIFO flush"] + #[inline(always)] + pub fn rxfflsh(&self) -> RXFFLSH_R { + RXFFLSH_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TxFIFO flush"] + #[inline(always)] + pub fn txfflsh(&self) -> TXFFLSH_R { + TXFFLSH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:10 - TxFIFO number"] + #[inline(always)] + pub fn txfnum(&self) -> TXFNUM_R { + TXFNUM_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bit 30 - DMA request signal"] + #[inline(always)] + pub fn dmareq(&self) -> DMAREQ_R { + DMAREQ_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - AHB master idle"] + #[inline(always)] + pub fn ahbidl(&self) -> AHBIDL_R { + AHBIDL_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Core soft reset"] + #[inline(always)] + #[must_use] + pub fn csrst(&mut self) -> CSRST_W<0> { + CSRST_W::new(self) + } + #[doc = "Bit 1 - HCLK soft reset"] + #[inline(always)] + #[must_use] + pub fn hsrst(&mut self) -> HSRST_W<1> { + HSRST_W::new(self) + } + #[doc = "Bit 2 - Host frame counter reset"] + #[inline(always)] + #[must_use] + pub fn fcrst(&mut self) -> FCRST_W<2> { + FCRST_W::new(self) + } + #[doc = "Bit 4 - RxFIFO flush"] + #[inline(always)] + #[must_use] + pub fn rxfflsh(&mut self) -> RXFFLSH_W<4> { + RXFFLSH_W::new(self) + } + #[doc = "Bit 5 - TxFIFO flush"] + #[inline(always)] + #[must_use] + pub fn txfflsh(&mut self) -> TXFFLSH_W<5> { + TXFFLSH_W::new(self) + } + #[doc = "Bits 6:10 - TxFIFO number"] + #[inline(always)] + #[must_use] + pub fn txfnum(&mut self) -> TXFNUM_W<6> { + TXFNUM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"] +pub struct GRSTCTL_SPEC; +impl crate::RegisterSpec for GRSTCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grstctl::R](R) reader structure"] +impl crate::Readable for GRSTCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"] +impl crate::Writable for GRSTCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GRSTCTL to value 0x2000_0000"] +impl crate::Resettable for GRSTCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_0000; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs new file mode 100644 index 0000000..ec6ba8c --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GRXFSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GRXFSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFD` reader - RxFIFO depth"] +pub type RXFD_R = crate::FieldReader; +#[doc = "Field `RXFD` writer - RxFIFO depth"] +pub type RXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRXFSIZ_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - RxFIFO depth"] + #[inline(always)] + pub fn rxfd(&self) -> RXFD_R { + RXFD_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn rxfd(&mut self) -> RXFD_W<0> { + RXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Receive FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](index.html) module"] +pub struct GRXFSIZ_SPEC; +impl crate::RegisterSpec for GRXFSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxfsiz::R](R) reader structure"] +impl crate::Readable for GRXFSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [grxfsiz::W](W) writer structure"] +impl crate::Writable for GRXFSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GRXFSIZ to value 0x0200"] +impl crate::Resettable for GRXFSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs new file mode 100644 index 0000000..a0231ff --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GRXSTSP_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHNUM` reader - Channel number"] +pub type CHNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Channel number"] + #[inline(always)] + pub fn chnum(&self) -> CHNUM_R { + CHNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[doc = "OTG_HS status read and pop register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_host](index.html) module"] +pub struct GRXSTSP_HOST_SPEC; +impl crate::RegisterSpec for GRXSTSP_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsp_host::R](R) reader structure"] +impl crate::Readable for GRXSTSP_HOST_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSP_Host to value 0"] +impl crate::Resettable for GRXSTSP_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs new file mode 100644 index 0000000..5de1533 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GRXSTSP_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +#[doc = "Field `FRMNUM` reader - Frame number"] +pub type FRMNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:24 - Frame number"] + #[inline(always)] + pub fn frmnum(&self) -> FRMNUM_R { + FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } +} +#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_peripheral](index.html) module"] +pub struct GRXSTSP_PERIPHERAL_SPEC; +impl crate::RegisterSpec for GRXSTSP_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsp_peripheral::R](R) reader structure"] +impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSP_Peripheral to value 0"] +impl crate::Resettable for GRXSTSP_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs new file mode 100644 index 0000000..399a9f8 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs @@ -0,0 +1,58 @@ +#[doc = "Register `GRXSTSR_Host` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHNUM` reader - Channel number"] +pub type CHNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Channel number"] + #[inline(always)] + pub fn chnum(&self) -> CHNUM_R { + CHNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[doc = "OTG_HS Receive status debug read register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_host](index.html) module"] +pub struct GRXSTSR_HOST_SPEC; +impl crate::RegisterSpec for GRXSTSR_HOST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsr_host::R](R) reader structure"] +impl crate::Readable for GRXSTSR_HOST_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSR_Host to value 0"] +impl crate::Resettable for GRXSTSR_HOST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs new file mode 100644 index 0000000..89558d9 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs @@ -0,0 +1,65 @@ +#[doc = "Register `GRXSTSR_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `BCNT` reader - Byte count"] +pub type BCNT_R = crate::FieldReader; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `PKTSTS` reader - Packet status"] +pub type PKTSTS_R = crate::FieldReader; +#[doc = "Field `FRMNUM` reader - Frame number"] +pub type FRMNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:14 - Byte count"] + #[inline(always)] + pub fn bcnt(&self) -> BCNT_R { + BCNT_R::new(((self.bits >> 4) & 0x07ff) as u16) + } + #[doc = "Bits 15:16 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:20 - Packet status"] + #[inline(always)] + pub fn pktsts(&self) -> PKTSTS_R { + PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:24 - Frame number"] + #[inline(always)] + pub fn frmnum(&self) -> FRMNUM_R { + FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } +} +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_peripheral](index.html) module"] +pub struct GRXSTSR_PERIPHERAL_SPEC; +impl crate::RegisterSpec for GRXSTSR_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [grxstsr_peripheral::R](R) reader structure"] +impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets GRXSTSR_Peripheral to value 0"] +impl crate::Resettable for GRXSTSR_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs b/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs new file mode 100644 index 0000000..a958441 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs @@ -0,0 +1,625 @@ +#[doc = "Register `GUSBCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GUSBCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOCAL` reader - FS timeout calibration"] +pub type TOCAL_R = crate::FieldReader; +#[doc = "Field `TOCAL` writer - FS timeout calibration"] +pub type TOCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `PHYIF` reader - PHY Interface width"] +pub type PHYIF_R = crate::BitReader; +#[doc = "PHY Interface width\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYIF_A { + #[doc = "0: `0`"] + _8BIT = 0, + #[doc = "1: `1`"] + _16BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYIF_A) -> Self { + variant as u8 != 0 + } +} +impl PHYIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYIF_A { + match self.bits { + false => PHYIF_A::_8BIT, + true => PHYIF_A::_16BIT, + } + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == PHYIF_A::_8BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == PHYIF_A::_16BIT + } +} +#[doc = "Field `PHYIF` writer - PHY Interface width"] +pub type PHYIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYIF_A, O>; +impl<'a, const O: u8> PHYIF_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(PHYIF_A::_8BIT) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(PHYIF_A::_16BIT) + } +} +#[doc = "Field `PHYTYPE` reader - PHY Type"] +pub type PHYTYPE_R = crate::BitReader; +#[doc = "PHY Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYTYPE_A { + #[doc = "0: `0`"] + UTMI = 0, + #[doc = "1: `1`"] + ULPI = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYTYPE_A) -> Self { + variant as u8 != 0 + } +} +impl PHYTYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYTYPE_A { + match self.bits { + false => PHYTYPE_A::UTMI, + true => PHYTYPE_A::ULPI, + } + } + #[doc = "Checks if the value of the field is `UTMI`"] + #[inline(always)] + pub fn is_utmi(&self) -> bool { + *self == PHYTYPE_A::UTMI + } + #[doc = "Checks if the value of the field is `ULPI`"] + #[inline(always)] + pub fn is_ulpi(&self) -> bool { + *self == PHYTYPE_A::ULPI + } +} +#[doc = "Field `PHYTYPE` writer - PHY Type"] +pub type PHYTYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYTYPE_A, O>; +impl<'a, const O: u8> PHYTYPE_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn utmi(self) -> &'a mut W { + self.variant(PHYTYPE_A::UTMI) + } + #[doc = "`1`"] + #[inline(always)] + pub fn ulpi(self) -> &'a mut W { + self.variant(PHYTYPE_A::ULPI) + } +} +#[doc = "Field `FSIF` reader - Full speed interface"] +pub type FSIF_R = crate::BitReader; +#[doc = "Full speed interface\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FSIF_A { + #[doc = "0: `0`"] + _6PIN = 0, + #[doc = "1: `1`"] + _3PIN = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FSIF_A) -> Self { + variant as u8 != 0 + } +} +impl FSIF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSIF_A { + match self.bits { + false => FSIF_A::_6PIN, + true => FSIF_A::_3PIN, + } + } + #[doc = "Checks if the value of the field is `_6PIN`"] + #[inline(always)] + pub fn is_6pin(&self) -> bool { + *self == FSIF_A::_6PIN + } + #[doc = "Checks if the value of the field is `_3PIN`"] + #[inline(always)] + pub fn is_3pin(&self) -> bool { + *self == FSIF_A::_3PIN + } +} +#[doc = "Field `FSIF` writer - Full speed interface"] +pub type FSIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, FSIF_A, O>; +impl<'a, const O: u8> FSIF_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn _6pin(self) -> &'a mut W { + self.variant(FSIF_A::_6PIN) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _3pin(self) -> &'a mut W { + self.variant(FSIF_A::_3PIN) + } +} +#[doc = "Field `PHYSEL` reader - Transceiver select"] +pub type PHYSEL_R = crate::BitReader; +#[doc = "Transceiver select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PHYSEL_A { + #[doc = "0: `0`"] + USB20 = 0, + #[doc = "1: `1`"] + USB11 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PHYSEL_A) -> Self { + variant as u8 != 0 + } +} +impl PHYSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PHYSEL_A { + match self.bits { + false => PHYSEL_A::USB20, + true => PHYSEL_A::USB11, + } + } + #[doc = "Checks if the value of the field is `USB20`"] + #[inline(always)] + pub fn is_usb20(&self) -> bool { + *self == PHYSEL_A::USB20 + } + #[doc = "Checks if the value of the field is `USB11`"] + #[inline(always)] + pub fn is_usb11(&self) -> bool { + *self == PHYSEL_A::USB11 + } +} +#[doc = "Field `PHYSEL` writer - Transceiver select"] +pub type PHYSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYSEL_A, O>; +impl<'a, const O: u8> PHYSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn usb20(self) -> &'a mut W { + self.variant(PHYSEL_A::USB20) + } + #[doc = "`1`"] + #[inline(always)] + pub fn usb11(self) -> &'a mut W { + self.variant(PHYSEL_A::USB11) + } +} +#[doc = "Field `DDRSEL` reader - ULPI data rate"] +pub type DDRSEL_R = crate::BitReader; +#[doc = "ULPI data rate\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DDRSEL_A { + #[doc = "0: `0`"] + SINGLE = 0, + #[doc = "1: `1`"] + DOUBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DDRSEL_A) -> Self { + variant as u8 != 0 + } +} +impl DDRSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DDRSEL_A { + match self.bits { + false => DDRSEL_A::SINGLE, + true => DDRSEL_A::DOUBLE, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == DDRSEL_A::SINGLE + } + #[doc = "Checks if the value of the field is `DOUBLE`"] + #[inline(always)] + pub fn is_double(&self) -> bool { + *self == DDRSEL_A::DOUBLE + } +} +#[doc = "Field `DDRSEL` writer - ULPI data rate"] +pub type DDRSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, DDRSEL_A, O>; +impl<'a, const O: u8> DDRSEL_W<'a, O> { + #[doc = "`0`"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(DDRSEL_A::SINGLE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn double(self) -> &'a mut W { + self.variant(DDRSEL_A::DOUBLE) + } +} +#[doc = "Field `SRPCAP` reader - SRP-capable"] +pub type SRPCAP_R = crate::BitReader; +#[doc = "Field `SRPCAP` writer - SRP-capable"] +pub type SRPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `HNPCAP` reader - HNP-capable"] +pub type HNPCAP_R = crate::BitReader; +#[doc = "Field `HNPCAP` writer - HNP-capable"] +pub type HNPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `TRDT` reader - USB turnaround time"] +pub type TRDT_R = crate::FieldReader; +#[doc = "Field `TRDT` writer - USB turnaround time"] +pub type TRDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 4, O>; +#[doc = "Field `PHYLPCS` reader - PHY Low-power clock select"] +pub type PHYLPCS_R = crate::BitReader; +#[doc = "Field `PHYLPCS` writer - PHY Low-power clock select"] +pub type PHYLPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIFSLS` reader - ULPI FS/LS select"] +pub type ULPIFSLS_R = crate::BitReader; +#[doc = "Field `ULPIFSLS` writer - ULPI FS/LS select"] +pub type ULPIFSLS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIAR` reader - ULPI Auto-resume"] +pub type ULPIAR_R = crate::BitReader; +#[doc = "Field `ULPIAR` writer - ULPI Auto-resume"] +pub type ULPIAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPICSM` reader - ULPI Clock SuspendM"] +pub type ULPICSM_R = crate::BitReader; +#[doc = "Field `ULPICSM` writer - ULPI Clock SuspendM"] +pub type ULPICSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIEVBUSD` reader - ULPI External VBUS Drive"] +pub type ULPIEVBUSD_R = crate::BitReader; +#[doc = "Field `ULPIEVBUSD` writer - ULPI External VBUS Drive"] +pub type ULPIEVBUSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIEVBUSI` reader - ULPI external VBUS indicator"] +pub type ULPIEVBUSI_R = crate::BitReader; +#[doc = "Field `ULPIEVBUSI` writer - ULPI external VBUS indicator"] +pub type ULPIEVBUSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `TSDPS` reader - TermSel DLine pulsing selection"] +pub type TSDPS_R = crate::BitReader; +#[doc = "Field `TSDPS` writer - TermSel DLine pulsing selection"] +pub type TSDPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `PCCI` reader - Indicator complement"] +pub type PCCI_R = crate::BitReader; +#[doc = "Field `PCCI` writer - Indicator complement"] +pub type PCCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `PTCI` reader - Indicator pass through"] +pub type PTCI_R = crate::BitReader; +#[doc = "Field `PTCI` writer - Indicator pass through"] +pub type PTCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `ULPIIPD` reader - ULPI interface protect disable"] +pub type ULPIIPD_R = crate::BitReader; +#[doc = "Field `ULPIIPD` writer - ULPI interface protect disable"] +pub type ULPIIPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `FHMOD` reader - Forced host mode"] +pub type FHMOD_R = crate::BitReader; +#[doc = "Field `FHMOD` writer - Forced host mode"] +pub type FHMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `FDMOD` reader - Forced peripheral mode"] +pub type FDMOD_R = crate::BitReader; +#[doc = "Field `FDMOD` writer - Forced peripheral mode"] +pub type FDMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +#[doc = "Field `CTXPKT` reader - Corrupt Tx packet"] +pub type CTXPKT_R = crate::BitReader; +#[doc = "Field `CTXPKT` writer - Corrupt Tx packet"] +pub type CTXPKT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - FS timeout calibration"] + #[inline(always)] + pub fn tocal(&self) -> TOCAL_R { + TOCAL_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - PHY Interface width"] + #[inline(always)] + pub fn phyif(&self) -> PHYIF_R { + PHYIF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PHY Type"] + #[inline(always)] + pub fn phytype(&self) -> PHYTYPE_R { + PHYTYPE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Full speed interface"] + #[inline(always)] + pub fn fsif(&self) -> FSIF_R { + FSIF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transceiver select"] + #[inline(always)] + pub fn physel(&self) -> PHYSEL_R { + PHYSEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ULPI data rate"] + #[inline(always)] + pub fn ddrsel(&self) -> DDRSEL_R { + DDRSEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SRP-capable"] + #[inline(always)] + pub fn srpcap(&self) -> SRPCAP_R { + SRPCAP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HNP-capable"] + #[inline(always)] + pub fn hnpcap(&self) -> HNPCAP_R { + HNPCAP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - USB turnaround time"] + #[inline(always)] + pub fn trdt(&self) -> TRDT_R { + TRDT_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bit 15 - PHY Low-power clock select"] + #[inline(always)] + pub fn phylpcs(&self) -> PHYLPCS_R { + PHYLPCS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - ULPI FS/LS select"] + #[inline(always)] + pub fn ulpifsls(&self) -> ULPIFSLS_R { + ULPIFSLS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - ULPI Auto-resume"] + #[inline(always)] + pub fn ulpiar(&self) -> ULPIAR_R { + ULPIAR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - ULPI Clock SuspendM"] + #[inline(always)] + pub fn ulpicsm(&self) -> ULPICSM_R { + ULPICSM_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - ULPI External VBUS Drive"] + #[inline(always)] + pub fn ulpievbusd(&self) -> ULPIEVBUSD_R { + ULPIEVBUSD_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - ULPI external VBUS indicator"] + #[inline(always)] + pub fn ulpievbusi(&self) -> ULPIEVBUSI_R { + ULPIEVBUSI_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - TermSel DLine pulsing selection"] + #[inline(always)] + pub fn tsdps(&self) -> TSDPS_R { + TSDPS_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Indicator complement"] + #[inline(always)] + pub fn pcci(&self) -> PCCI_R { + PCCI_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Indicator pass through"] + #[inline(always)] + pub fn ptci(&self) -> PTCI_R { + PTCI_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - ULPI interface protect disable"] + #[inline(always)] + pub fn ulpiipd(&self) -> ULPIIPD_R { + ULPIIPD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 29 - Forced host mode"] + #[inline(always)] + pub fn fhmod(&self) -> FHMOD_R { + FHMOD_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Forced peripheral mode"] + #[inline(always)] + pub fn fdmod(&self) -> FDMOD_R { + FDMOD_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Corrupt Tx packet"] + #[inline(always)] + pub fn ctxpkt(&self) -> CTXPKT_R { + CTXPKT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - FS timeout calibration"] + #[inline(always)] + #[must_use] + pub fn tocal(&mut self) -> TOCAL_W<0> { + TOCAL_W::new(self) + } + #[doc = "Bit 3 - PHY Interface width"] + #[inline(always)] + #[must_use] + pub fn phyif(&mut self) -> PHYIF_W<3> { + PHYIF_W::new(self) + } + #[doc = "Bit 4 - PHY Type"] + #[inline(always)] + #[must_use] + pub fn phytype(&mut self) -> PHYTYPE_W<4> { + PHYTYPE_W::new(self) + } + #[doc = "Bit 5 - Full speed interface"] + #[inline(always)] + #[must_use] + pub fn fsif(&mut self) -> FSIF_W<5> { + FSIF_W::new(self) + } + #[doc = "Bit 6 - Transceiver select"] + #[inline(always)] + #[must_use] + pub fn physel(&mut self) -> PHYSEL_W<6> { + PHYSEL_W::new(self) + } + #[doc = "Bit 7 - ULPI data rate"] + #[inline(always)] + #[must_use] + pub fn ddrsel(&mut self) -> DDRSEL_W<7> { + DDRSEL_W::new(self) + } + #[doc = "Bit 8 - SRP-capable"] + #[inline(always)] + #[must_use] + pub fn srpcap(&mut self) -> SRPCAP_W<8> { + SRPCAP_W::new(self) + } + #[doc = "Bit 9 - HNP-capable"] + #[inline(always)] + #[must_use] + pub fn hnpcap(&mut self) -> HNPCAP_W<9> { + HNPCAP_W::new(self) + } + #[doc = "Bits 10:13 - USB turnaround time"] + #[inline(always)] + #[must_use] + pub fn trdt(&mut self) -> TRDT_W<10> { + TRDT_W::new(self) + } + #[doc = "Bit 15 - PHY Low-power clock select"] + #[inline(always)] + #[must_use] + pub fn phylpcs(&mut self) -> PHYLPCS_W<15> { + PHYLPCS_W::new(self) + } + #[doc = "Bit 17 - ULPI FS/LS select"] + #[inline(always)] + #[must_use] + pub fn ulpifsls(&mut self) -> ULPIFSLS_W<17> { + ULPIFSLS_W::new(self) + } + #[doc = "Bit 18 - ULPI Auto-resume"] + #[inline(always)] + #[must_use] + pub fn ulpiar(&mut self) -> ULPIAR_W<18> { + ULPIAR_W::new(self) + } + #[doc = "Bit 19 - ULPI Clock SuspendM"] + #[inline(always)] + #[must_use] + pub fn ulpicsm(&mut self) -> ULPICSM_W<19> { + ULPICSM_W::new(self) + } + #[doc = "Bit 20 - ULPI External VBUS Drive"] + #[inline(always)] + #[must_use] + pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<20> { + ULPIEVBUSD_W::new(self) + } + #[doc = "Bit 21 - ULPI external VBUS indicator"] + #[inline(always)] + #[must_use] + pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<21> { + ULPIEVBUSI_W::new(self) + } + #[doc = "Bit 22 - TermSel DLine pulsing selection"] + #[inline(always)] + #[must_use] + pub fn tsdps(&mut self) -> TSDPS_W<22> { + TSDPS_W::new(self) + } + #[doc = "Bit 23 - Indicator complement"] + #[inline(always)] + #[must_use] + pub fn pcci(&mut self) -> PCCI_W<23> { + PCCI_W::new(self) + } + #[doc = "Bit 24 - Indicator pass through"] + #[inline(always)] + #[must_use] + pub fn ptci(&mut self) -> PTCI_W<24> { + PTCI_W::new(self) + } + #[doc = "Bit 25 - ULPI interface protect disable"] + #[inline(always)] + #[must_use] + pub fn ulpiipd(&mut self) -> ULPIIPD_W<25> { + ULPIIPD_W::new(self) + } + #[doc = "Bit 29 - Forced host mode"] + #[inline(always)] + #[must_use] + pub fn fhmod(&mut self) -> FHMOD_W<29> { + FHMOD_W::new(self) + } + #[doc = "Bit 30 - Forced peripheral mode"] + #[inline(always)] + #[must_use] + pub fn fdmod(&mut self) -> FDMOD_W<30> { + FDMOD_W::new(self) + } + #[doc = "Bit 31 - Corrupt Tx packet"] + #[inline(always)] + #[must_use] + pub fn ctxpkt(&mut self) -> CTXPKT_W<31> { + CTXPKT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS USB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](index.html) module"] +pub struct GUSBCFG_SPEC; +impl crate::RegisterSpec for GUSBCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gusbcfg::R](R) reader structure"] +impl crate::Readable for GUSBCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gusbcfg::W](W) writer structure"] +impl crate::Writable for GUSBCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GUSBCFG to value 0x0a00"] +impl crate::Resettable for GUSBCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0a00; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs b/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs new file mode 100644 index 0000000..c50a180 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs @@ -0,0 +1,95 @@ +#[doc = "Register `HPTXFSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPTXFSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTXSA` reader - Host periodic TxFIFO start address"] +pub type PTXSA_R = crate::FieldReader; +#[doc = "Field `PTXSA` writer - Host periodic TxFIFO start address"] +pub type PTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +#[doc = "Field `PTXFD` reader - Host periodic TxFIFO depth"] +pub type PTXFD_R = crate::FieldReader; +#[doc = "Field `PTXFD` writer - Host periodic TxFIFO depth"] +pub type PTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] + #[inline(always)] + pub fn ptxsa(&self) -> PTXSA_R { + PTXSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] + #[inline(always)] + pub fn ptxfd(&self) -> PTXFD_R { + PTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] + #[inline(always)] + #[must_use] + pub fn ptxsa(&mut self) -> PTXSA_W<0> { + PTXSA_W::new(self) + } + #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn ptxfd(&mut self) -> PTXFD_W<16> { + PTXFD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](index.html) module"] +pub struct HPTXFSIZ_SPEC; +impl crate::RegisterSpec for HPTXFSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hptxfsiz::R](R) reader structure"] +impl crate::Readable for HPTXFSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](W) writer structure"] +impl crate::Writable for HPTXFSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPTXFSIZ to value 0x0200_0600"] +impl crate::Resettable for HPTXFSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0600; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs b/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs new file mode 100644 index 0000000..13715b7 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs @@ -0,0 +1,348 @@ +#[doc = "Register `HW_CONFIG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OPERATING_MODE` reader - Operating Mode"] +pub type OPERATING_MODE_R = crate::FieldReader; +#[doc = "Operating Mode"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OPERATING_MODE_A { + #[doc = "0: `0`"] + HNP_SRP_CAPABLE = 0, + #[doc = "1: `1`"] + SRP_ONLY_CAPABLE = 1, + #[doc = "2: `10`"] + NO_HNP_SRP_CAPABLE = 2, + #[doc = "3: `11`"] + SRP_CAPABLE_DEVICE = 3, + #[doc = "4: `100`"] + NO_SRP_CAPABLE_DEVICE = 4, + #[doc = "5: `101`"] + SRP_CAPABLE_HOST = 5, + #[doc = "6: `110`"] + NO_SRP_CAPABLE_HOST = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OPERATING_MODE_A) -> Self { + variant as _ + } +} +impl OPERATING_MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OPERATING_MODE_A::HNP_SRP_CAPABLE), + 1 => Some(OPERATING_MODE_A::SRP_ONLY_CAPABLE), + 2 => Some(OPERATING_MODE_A::NO_HNP_SRP_CAPABLE), + 3 => Some(OPERATING_MODE_A::SRP_CAPABLE_DEVICE), + 4 => Some(OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE), + 5 => Some(OPERATING_MODE_A::SRP_CAPABLE_HOST), + 6 => Some(OPERATING_MODE_A::NO_SRP_CAPABLE_HOST), + _ => None, + } + } + #[doc = "Checks if the value of the field is `HNP_SRP_CAPABLE`"] + #[inline(always)] + pub fn is_hnp_srp_capable(&self) -> bool { + *self == OPERATING_MODE_A::HNP_SRP_CAPABLE + } + #[doc = "Checks if the value of the field is `SRP_ONLY_CAPABLE`"] + #[inline(always)] + pub fn is_srp_only_capable(&self) -> bool { + *self == OPERATING_MODE_A::SRP_ONLY_CAPABLE + } + #[doc = "Checks if the value of the field is `NO_HNP_SRP_CAPABLE`"] + #[inline(always)] + pub fn is_no_hnp_srp_capable(&self) -> bool { + *self == OPERATING_MODE_A::NO_HNP_SRP_CAPABLE + } + #[doc = "Checks if the value of the field is `SRP_CAPABLE_DEVICE`"] + #[inline(always)] + pub fn is_srp_capable_device(&self) -> bool { + *self == OPERATING_MODE_A::SRP_CAPABLE_DEVICE + } + #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_DEVICE`"] + #[inline(always)] + pub fn is_no_srp_capable_device(&self) -> bool { + *self == OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE + } + #[doc = "Checks if the value of the field is `SRP_CAPABLE_HOST`"] + #[inline(always)] + pub fn is_srp_capable_host(&self) -> bool { + *self == OPERATING_MODE_A::SRP_CAPABLE_HOST + } + #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_HOST`"] + #[inline(always)] + pub fn is_no_srp_capable_host(&self) -> bool { + *self == OPERATING_MODE_A::NO_SRP_CAPABLE_HOST + } +} +#[doc = "Field `ARCHITECTURE` reader - Architecture"] +pub type ARCHITECTURE_R = crate::FieldReader; +#[doc = "Architecture"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ARCHITECTURE_A { + #[doc = "0: `0`"] + SLAVE_ONLY = 0, + #[doc = "1: `1`"] + EXTERNAL_DMA = 1, + #[doc = "2: `10`"] + INTERNAL_DMA = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ARCHITECTURE_A) -> Self { + variant as _ + } +} +impl ARCHITECTURE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ARCHITECTURE_A::SLAVE_ONLY), + 1 => Some(ARCHITECTURE_A::EXTERNAL_DMA), + 2 => Some(ARCHITECTURE_A::INTERNAL_DMA), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SLAVE_ONLY`"] + #[inline(always)] + pub fn is_slave_only(&self) -> bool { + *self == ARCHITECTURE_A::SLAVE_ONLY + } + #[doc = "Checks if the value of the field is `EXTERNAL_DMA`"] + #[inline(always)] + pub fn is_external_dma(&self) -> bool { + *self == ARCHITECTURE_A::EXTERNAL_DMA + } + #[doc = "Checks if the value of the field is `INTERNAL_DMA`"] + #[inline(always)] + pub fn is_internal_dma(&self) -> bool { + *self == ARCHITECTURE_A::INTERNAL_DMA + } +} +#[doc = "Field `POINT_TO_POINT` reader - Point to Point"] +pub type POINT_TO_POINT_R = crate::BitReader; +#[doc = "Field `HIGH_SPEED_PHY` reader - High Speed Physical"] +pub type HIGH_SPEED_PHY_R = crate::FieldReader; +#[doc = "High Speed Physical"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HIGH_SPEED_PHY_A { + #[doc = "0: `0`"] + NOT_SUPPORTED = 0, + #[doc = "1: `1`"] + UTMI = 1, + #[doc = "2: `10`"] + ULPI = 2, + #[doc = "3: `11`"] + UTMI_ULPI = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HIGH_SPEED_PHY_A) -> Self { + variant as _ + } +} +impl HIGH_SPEED_PHY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HIGH_SPEED_PHY_A { + match self.bits { + 0 => HIGH_SPEED_PHY_A::NOT_SUPPORTED, + 1 => HIGH_SPEED_PHY_A::UTMI, + 2 => HIGH_SPEED_PHY_A::ULPI, + 3 => HIGH_SPEED_PHY_A::UTMI_ULPI, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NOT_SUPPORTED`"] + #[inline(always)] + pub fn is_not_supported(&self) -> bool { + *self == HIGH_SPEED_PHY_A::NOT_SUPPORTED + } + #[doc = "Checks if the value of the field is `UTMI`"] + #[inline(always)] + pub fn is_utmi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::UTMI + } + #[doc = "Checks if the value of the field is `ULPI`"] + #[inline(always)] + pub fn is_ulpi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::ULPI + } + #[doc = "Checks if the value of the field is `UTMI_ULPI`"] + #[inline(always)] + pub fn is_utmi_ulpi(&self) -> bool { + *self == HIGH_SPEED_PHY_A::UTMI_ULPI + } +} +#[doc = "Field `FULL_SPEED_PHY` reader - Full Speed Physical"] +pub type FULL_SPEED_PHY_R = crate::FieldReader; +#[doc = "Full Speed Physical"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FULL_SPEED_PHY_A { + #[doc = "0: `0`"] + PHY0 = 0, + #[doc = "1: `1`"] + DEDICATED = 1, + #[doc = "2: `10`"] + PHY2 = 2, + #[doc = "3: `11`"] + PHY3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FULL_SPEED_PHY_A) -> Self { + variant as _ + } +} +impl FULL_SPEED_PHY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FULL_SPEED_PHY_A { + match self.bits { + 0 => FULL_SPEED_PHY_A::PHY0, + 1 => FULL_SPEED_PHY_A::DEDICATED, + 2 => FULL_SPEED_PHY_A::PHY2, + 3 => FULL_SPEED_PHY_A::PHY3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PHY0`"] + #[inline(always)] + pub fn is_phy0(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY0 + } + #[doc = "Checks if the value of the field is `DEDICATED`"] + #[inline(always)] + pub fn is_dedicated(&self) -> bool { + *self == FULL_SPEED_PHY_A::DEDICATED + } + #[doc = "Checks if the value of the field is `PHY2`"] + #[inline(always)] + pub fn is_phy2(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY2 + } + #[doc = "Checks if the value of the field is `PHY3`"] + #[inline(always)] + pub fn is_phy3(&self) -> bool { + *self == FULL_SPEED_PHY_A::PHY3 + } +} +#[doc = "Field `DEVICE_END_POINT_COUNT` reader - Device end point count"] +pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; +#[doc = "Field `HOST_CHANNEL_COUNT` reader - Host channel count"] +pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; +#[doc = "Field `SUPPORTS_PERIODIC_ENDPOINTS` reader - Supports periodic endpoints"] +pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; +#[doc = "Field `DYNAMIC_FIFO` reader - Dynamic FIFO"] +pub type DYNAMIC_FIFO_R = crate::BitReader; +#[doc = "Field `MULTI_PROC_INT` reader - Multi proc int"] +pub type MULTI_PROC_INT_R = crate::BitReader; +#[doc = "Field `NON_PERIODIC_QUEUE_DEPTH` reader - Non periodic queue depth"] +pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `HOST_PERIODIC_QUEUE_DEPTH` reader - Host periodic queue depth"] +pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `DEVICE_TOKEN_QUEUE_DEPTH` reader - Device token queue depth"] +pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; +#[doc = "Field `ENABLE_IC_USB` reader - Enable IC USB"] +pub type ENABLE_IC_USB_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Operating Mode"] + #[inline(always)] + pub fn operating_mode(&self) -> OPERATING_MODE_R { + OPERATING_MODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Architecture"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Point to Point"] + #[inline(always)] + pub fn point_to_point(&self) -> POINT_TO_POINT_R { + POINT_TO_POINT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - High Speed Physical"] + #[inline(always)] + pub fn high_speed_phy(&self) -> HIGH_SPEED_PHY_R { + HIGH_SPEED_PHY_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Full Speed Physical"] + #[inline(always)] + pub fn full_speed_phy(&self) -> FULL_SPEED_PHY_R { + FULL_SPEED_PHY_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:13 - Device end point count"] + #[inline(always)] + pub fn device_end_point_count(&self) -> DEVICE_END_POINT_COUNT_R { + DEVICE_END_POINT_COUNT_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:17 - Host channel count"] + #[inline(always)] + pub fn host_channel_count(&self) -> HOST_CHANNEL_COUNT_R { + HOST_CHANNEL_COUNT_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bit 18 - Supports periodic endpoints"] + #[inline(always)] + pub fn supports_periodic_endpoints(&self) -> SUPPORTS_PERIODIC_ENDPOINTS_R { + SUPPORTS_PERIODIC_ENDPOINTS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Dynamic FIFO"] + #[inline(always)] + pub fn dynamic_fifo(&self) -> DYNAMIC_FIFO_R { + DYNAMIC_FIFO_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Multi proc int"] + #[inline(always)] + pub fn multi_proc_int(&self) -> MULTI_PROC_INT_R { + MULTI_PROC_INT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 22:23 - Non periodic queue depth"] + #[inline(always)] + pub fn non_periodic_queue_depth(&self) -> NON_PERIODIC_QUEUE_DEPTH_R { + NON_PERIODIC_QUEUE_DEPTH_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Host periodic queue depth"] + #[inline(always)] + pub fn host_periodic_queue_depth(&self) -> HOST_PERIODIC_QUEUE_DEPTH_R { + HOST_PERIODIC_QUEUE_DEPTH_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:30 - Device token queue depth"] + #[inline(always)] + pub fn device_token_queue_depth(&self) -> DEVICE_TOKEN_QUEUE_DEPTH_R { + DEVICE_TOKEN_QUEUE_DEPTH_R::new(((self.bits >> 26) & 0x1f) as u8) + } + #[doc = "Bit 31 - Enable IC USB"] + #[inline(always)] + pub fn enable_ic_usb(&self) -> ENABLE_IC_USB_R { + ENABLE_IC_USB_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Hardware Config 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_config0](index.html) module"] +pub struct HW_CONFIG0_SPEC; +impl crate::RegisterSpec for HW_CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hw_config0::R](R) reader structure"] +impl crate::Readable for HW_CONFIG0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs b/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs new file mode 100644 index 0000000..1ca29d0 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs @@ -0,0 +1,157 @@ +#[doc = "Register `HW_DIRECTION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DIRECTION[0-15]` reader - Direction %s"] +pub type DIRECTION_R = crate::FieldReader; +#[doc = "Direction %s"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + BIDIR = 0, + #[doc = "1: `1`"] + IN = 1, + #[doc = "2: `10`"] + OUT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as _ + } +} +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DIRECTION_A::BIDIR), + 1 => Some(DIRECTION_A::IN), + 2 => Some(DIRECTION_A::OUT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BIDIR`"] + #[inline(always)] + pub fn is_bidir(&self) -> bool { + *self == DIRECTION_A::BIDIR + } + #[doc = "Checks if the value of the field is `IN`"] + #[inline(always)] + pub fn is_in(&self) -> bool { + *self == DIRECTION_A::IN + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + *self == DIRECTION_A::OUT + } +} +impl R { + #[doc = "Direction [0-15]"] + #[inline(always)] + pub unsafe fn direction(&self, n: u8) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> (n * 2)) & 3) as u8) + } + #[doc = "Bits 0:1 - Direction 0"] + #[inline(always)] + pub fn direction0(&self) -> DIRECTION_R { + DIRECTION_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Direction 1"] + #[inline(always)] + pub fn direction1(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Direction 2"] + #[inline(always)] + pub fn direction2(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Direction 3"] + #[inline(always)] + pub fn direction3(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Direction 4"] + #[inline(always)] + pub fn direction4(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Direction 5"] + #[inline(always)] + pub fn direction5(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Direction 6"] + #[inline(always)] + pub fn direction6(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Direction 7"] + #[inline(always)] + pub fn direction7(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Direction 8"] + #[inline(always)] + pub fn direction8(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Direction 9"] + #[inline(always)] + pub fn direction9(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Direction 10"] + #[inline(always)] + pub fn direction10(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Direction 11"] + #[inline(always)] + pub fn direction11(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Direction 12"] + #[inline(always)] + pub fn direction12(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Direction 13"] + #[inline(always)] + pub fn direction13(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - Direction 14"] + #[inline(always)] + pub fn direction14(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Direction 15"] + #[inline(always)] + pub fn direction15(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[doc = "Direction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_direction](index.html) module"] +pub struct HW_DIRECTION_SPEC; +impl crate::RegisterSpec for HW_DIRECTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hw_direction::R](R) reader structure"] +impl crate::Readable for HW_DIRECTION_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs b/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs new file mode 100644 index 0000000..8734146 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs @@ -0,0 +1,97 @@ +#[doc = "Register `TX0FSIZ_Peripheral` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TX0FSIZ_Peripheral` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TX0FSA` reader - Endpoint 0 transmit RAM start address"] +pub type TX0FSA_R = crate::FieldReader; +#[doc = "Field `TX0FSA` writer - Endpoint 0 transmit RAM start address"] +pub type TX0FSA_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +#[doc = "Field `TX0FD` reader - Endpoint 0 TxFIFO depth"] +pub type TX0FD_R = crate::FieldReader; +#[doc = "Field `TX0FD` writer - Endpoint 0 TxFIFO depth"] +pub type TX0FD_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] + #[inline(always)] + pub fn tx0fsa(&self) -> TX0FSA_R { + TX0FSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] + #[inline(always)] + pub fn tx0fd(&self) -> TX0FD_R { + TX0FD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] + #[inline(always)] + #[must_use] + pub fn tx0fsa(&mut self) -> TX0FSA_W<0> { + TX0FSA_W::new(self) + } + #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] + #[inline(always)] + #[must_use] + pub fn tx0fd(&mut self) -> TX0FD_W<16> { + TX0FD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx0fsiz_peripheral](index.html) module"] +pub struct TX0FSIZ_PERIPHERAL_SPEC; +impl crate::RegisterSpec for TX0FSIZ_PERIPHERAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx0fsiz_peripheral::R](R) reader structure"] +impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tx0fsiz_peripheral::W](W) writer structure"] +impl crate::Writable for TX0FSIZ_PERIPHERAL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX0FSIZ_Peripheral to value 0x0200"] +impl crate::Resettable for TX0FSIZ_PERIPHERAL_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/vid.rs b/crates/bcm2837-lpa/src/usb_otg_global/vid.rs new file mode 100644 index 0000000..ae468f7 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_global/vid.rs @@ -0,0 +1,24 @@ +#[doc = "Register `VID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "OTG_HS vendor ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vid](index.html) module"] +pub struct VID_SPEC; +impl crate::RegisterSpec for VID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vid::R](R) reader structure"] +impl crate::Readable for VID_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host.rs b/crates/bcm2837-lpa/src/usb_otg_host.rs new file mode 100644 index 0000000..c2b6fb8 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host.rs @@ -0,0 +1,89 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - OTG_HS host configuration register"] + pub hcfg: HCFG, + #[doc = "0x04 - OTG_HS Host frame interval register"] + pub hfir: HFIR, + #[doc = "0x08 - OTG_HS host frame number/frame time remaining register"] + pub hfnum: HFNUM, + _reserved3: [u8; 0x04], + #[doc = "0x10 - Host periodic transmit FIFO/queue status register"] + pub hptxsts: HPTXSTS, + #[doc = "0x14 - OTG_HS Host all channels interrupt register"] + pub haint: HAINT, + #[doc = "0x18 - OTG_HS host all channels interrupt mask register"] + pub haintmsk: HAINTMSK, + _reserved6: [u8; 0x24], + #[doc = "0x40 - OTG_HS host port control and status register"] + pub hprt: HPRT, + _reserved7: [u8; 0xbc], + #[doc = "0x100..0x118 - Host channel %s"] + pub host_channel0: HOST_CHANNEL, + _reserved8: [u8; 0x08], + #[doc = "0x120..0x138 - Host channel %s"] + pub host_channel1: HOST_CHANNEL, + _reserved9: [u8; 0x08], + #[doc = "0x140..0x158 - Host channel %s"] + pub host_channel2: HOST_CHANNEL, + _reserved10: [u8; 0x08], + #[doc = "0x160..0x178 - Host channel %s"] + pub host_channel3: HOST_CHANNEL, + _reserved11: [u8; 0x08], + #[doc = "0x180..0x198 - Host channel %s"] + pub host_channel4: HOST_CHANNEL, + _reserved12: [u8; 0x08], + #[doc = "0x1a0..0x1b8 - Host channel %s"] + pub host_channel5: HOST_CHANNEL, + _reserved13: [u8; 0x08], + #[doc = "0x1c0..0x1d8 - Host channel %s"] + pub host_channel6: HOST_CHANNEL, + _reserved14: [u8; 0x08], + #[doc = "0x1e0..0x1f8 - Host channel %s"] + pub host_channel7: HOST_CHANNEL, + _reserved15: [u8; 0x08], + #[doc = "0x200..0x218 - Host channel %s"] + pub host_channel8: HOST_CHANNEL, + _reserved16: [u8; 0x08], + #[doc = "0x220..0x238 - Host channel %s"] + pub host_channel9: HOST_CHANNEL, + _reserved17: [u8; 0x08], + #[doc = "0x240..0x258 - Host channel %s"] + pub host_channel10: HOST_CHANNEL, + _reserved18: [u8; 0x08], + #[doc = "0x260..0x278 - Host channel %s"] + pub host_channel11: HOST_CHANNEL, +} +#[doc = "HCFG (rw) register accessor: an alias for `Reg`"] +pub type HCFG = crate::Reg; +#[doc = "OTG_HS host configuration register"] +pub mod hcfg; +#[doc = "HFIR (rw) register accessor: an alias for `Reg`"] +pub type HFIR = crate::Reg; +#[doc = "OTG_HS Host frame interval register"] +pub mod hfir; +#[doc = "HFNUM (r) register accessor: an alias for `Reg`"] +pub type HFNUM = crate::Reg; +#[doc = "OTG_HS host frame number/frame time remaining register"] +pub mod hfnum; +#[doc = "HPTXSTS (rw) register accessor: an alias for `Reg`"] +pub type HPTXSTS = crate::Reg; +#[doc = "Host periodic transmit FIFO/queue status register"] +pub mod hptxsts; +#[doc = "HAINT (r) register accessor: an alias for `Reg`"] +pub type HAINT = crate::Reg; +#[doc = "OTG_HS Host all channels interrupt register"] +pub mod haint; +#[doc = "HAINTMSK (rw) register accessor: an alias for `Reg`"] +pub type HAINTMSK = crate::Reg; +#[doc = "OTG_HS host all channels interrupt mask register"] +pub mod haintmsk; +#[doc = "HPRT (rw) register accessor: an alias for `Reg`"] +pub type HPRT = crate::Reg; +#[doc = "OTG_HS host port control and status register"] +pub mod hprt; +#[doc = "Host channel %s"] +pub use self::host_channel::HOST_CHANNEL; +#[doc = r"Cluster"] +#[doc = "Host channel %s"] +pub mod host_channel; diff --git a/crates/bcm2837-lpa/src/usb_otg_host/haint.rs b/crates/bcm2837-lpa/src/usb_otg_host/haint.rs new file mode 100644 index 0000000..16455f3 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/haint.rs @@ -0,0 +1,37 @@ +#[doc = "Register `HAINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `HAINT` reader - Channel interrupts"] +pub type HAINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Channel interrupts"] + #[inline(always)] + pub fn haint(&self) -> HAINT_R { + HAINT_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "OTG_HS Host all channels interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](index.html) module"] +pub struct HAINT_SPEC; +impl crate::RegisterSpec for HAINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [haint::R](R) reader structure"] +impl crate::Readable for HAINT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HAINT to value 0"] +impl crate::Resettable for HAINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs new file mode 100644 index 0000000..69df5e9 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HAINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HAINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HAINTM` reader - Channel interrupt mask"] +pub type HAINTM_R = crate::FieldReader; +#[doc = "Field `HAINTM` writer - Channel interrupt mask"] +pub type HAINTM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HAINTMSK_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Channel interrupt mask"] + #[inline(always)] + pub fn haintm(&self) -> HAINTM_R { + HAINTM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Channel interrupt mask"] + #[inline(always)] + #[must_use] + pub fn haintm(&mut self) -> HAINTM_W<0> { + HAINTM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host all channels interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](index.html) module"] +pub struct HAINTMSK_SPEC; +impl crate::RegisterSpec for HAINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [haintmsk::R](R) reader structure"] +impl crate::Readable for HAINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [haintmsk::W](W) writer structure"] +impl crate::Writable for HAINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HAINTMSK to value 0"] +impl crate::Resettable for HAINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs b/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs new file mode 100644 index 0000000..17f4b01 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs @@ -0,0 +1,87 @@ +#[doc = "Register `HCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FSLSPCS` reader - FS/LS PHY clock select"] +pub type FSLSPCS_R = crate::FieldReader; +#[doc = "Field `FSLSPCS` writer - FS/LS PHY clock select"] +pub type FSLSPCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 2, O>; +#[doc = "Field `FSLSS` reader - FS- and LS-only support"] +pub type FSLSS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - FS/LS PHY clock select"] + #[inline(always)] + pub fn fslspcs(&self) -> FSLSPCS_R { + FSLSPCS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - FS- and LS-only support"] + #[inline(always)] + pub fn fslss(&self) -> FSLSS_R { + FSLSS_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - FS/LS PHY clock select"] + #[inline(always)] + #[must_use] + pub fn fslspcs(&mut self) -> FSLSPCS_W<0> { + FSLSPCS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"] +pub struct HCFG_SPEC; +impl crate::RegisterSpec for HCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcfg::R](R) reader structure"] +impl crate::Readable for HCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"] +impl crate::Writable for HCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCFG to value 0"] +impl crate::Resettable for HCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs b/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs new file mode 100644 index 0000000..9182ff2 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HFIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HFIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FRIVL` reader - Frame interval"] +pub type FRIVL_R = crate::FieldReader; +#[doc = "Field `FRIVL` writer - Frame interval"] +pub type FRIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFIR_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Frame interval"] + #[inline(always)] + pub fn frivl(&self) -> FRIVL_R { + FRIVL_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Frame interval"] + #[inline(always)] + #[must_use] + pub fn frivl(&mut self) -> FRIVL_W<0> { + FRIVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS Host frame interval register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](index.html) module"] +pub struct HFIR_SPEC; +impl crate::RegisterSpec for HFIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfir::R](R) reader structure"] +impl crate::Readable for HFIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hfir::W](W) writer structure"] +impl crate::Writable for HFIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HFIR to value 0xea60"] +impl crate::Resettable for HFIR_SPEC { + const RESET_VALUE: Self::Ux = 0xea60; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs b/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs new file mode 100644 index 0000000..0df982a --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HFNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FRNUM` reader - Frame number"] +pub type FRNUM_R = crate::FieldReader; +#[doc = "Field `FTREM` reader - Frame time remaining"] +pub type FTREM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Frame number"] + #[inline(always)] + pub fn frnum(&self) -> FRNUM_R { + FRNUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Frame time remaining"] + #[inline(always)] + pub fn ftrem(&self) -> FTREM_R { + FTREM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "OTG_HS host frame number/frame time remaining register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](index.html) module"] +pub struct HFNUM_SPEC; +impl crate::RegisterSpec for HFNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hfnum::R](R) reader structure"] +impl crate::Readable for HFNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HFNUM to value 0x3fff"] +impl crate::Resettable for HFNUM_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs new file mode 100644 index 0000000..ee4a815 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs @@ -0,0 +1,40 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct HOST_CHANNEL { + #[doc = "0x00 - Characteristics register"] + pub hcchar: HCCHAR, + #[doc = "0x04 - Split control register"] + pub hcsplt: HCSPLT, + #[doc = "0x08 - Interrupt register"] + pub hcint: HCINT, + #[doc = "0x0c - Interrupt mask"] + pub hcintmsk: HCINTMSK, + #[doc = "0x10 - Transfer size"] + pub hctsiz: HCTSIZ, + #[doc = "0x14 - DMA address"] + pub hcdma: HCDMA, +} +#[doc = "HCCHAR (rw) register accessor: an alias for `Reg`"] +pub type HCCHAR = crate::Reg; +#[doc = "Characteristics register"] +pub mod hcchar; +#[doc = "HCSPLT (rw) register accessor: an alias for `Reg`"] +pub type HCSPLT = crate::Reg; +#[doc = "Split control register"] +pub mod hcsplt; +#[doc = "HCINT (rw) register accessor: an alias for `Reg`"] +pub type HCINT = crate::Reg; +#[doc = "Interrupt register"] +pub mod hcint; +#[doc = "HCINTMSK (rw) register accessor: an alias for `Reg`"] +pub type HCINTMSK = crate::Reg; +#[doc = "Interrupt mask"] +pub mod hcintmsk; +#[doc = "HCTSIZ (rw) register accessor: an alias for `Reg`"] +pub type HCTSIZ = crate::Reg; +#[doc = "Transfer size"] +pub mod hctsiz; +#[doc = "HCDMA (rw) register accessor: an alias for `Reg`"] +pub type HCDMA = crate::Reg; +#[doc = "DMA address"] +pub mod hcdma; diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs new file mode 100644 index 0000000..d73f560 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs @@ -0,0 +1,215 @@ +#[doc = "Register `HCCHAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCCHAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MPSIZ` reader - Maximum packet size"] +pub type MPSIZ_R = crate::FieldReader; +#[doc = "Field `MPSIZ` writer - Maximum packet size"] +pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u16, u16, 11, O>; +#[doc = "Field `EPNUM` reader - Endpoint number"] +pub type EPNUM_R = crate::FieldReader; +#[doc = "Field `EPNUM` writer - Endpoint number"] +pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 4, O>; +#[doc = "Field `EPDIR` reader - Endpoint direction"] +pub type EPDIR_R = crate::BitReader; +#[doc = "Field `EPDIR` writer - Endpoint direction"] +pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `LSDEV` reader - Low-speed device"] +pub type LSDEV_R = crate::BitReader; +#[doc = "Field `LSDEV` writer - Low-speed device"] +pub type LSDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `EPTYP` reader - Endpoint type"] +pub type EPTYP_R = crate::FieldReader; +#[doc = "Field `EPTYP` writer - Endpoint type"] +pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +#[doc = "Field `MC` reader - Multi Count (MC) / Error Count (EC)"] +pub type MC_R = crate::FieldReader; +#[doc = "Field `MC` writer - Multi Count (MC) / Error Count (EC)"] +pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +#[doc = "Field `DAD` reader - Device address"] +pub type DAD_R = crate::FieldReader; +#[doc = "Field `DAD` writer - Device address"] +pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 7, O>; +#[doc = "Field `ODDFRM` reader - Odd frame"] +pub type ODDFRM_R = crate::BitReader; +#[doc = "Field `ODDFRM` writer - Odd frame"] +pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `CHDIS` reader - Channel disable"] +pub type CHDIS_R = crate::BitReader; +#[doc = "Field `CHDIS` writer - Channel disable"] +pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +#[doc = "Field `CHENA` reader - Channel enable"] +pub type CHENA_R = crate::BitReader; +#[doc = "Field `CHENA` writer - Channel enable"] +pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + pub fn mpsiz(&self) -> MPSIZ_R { + MPSIZ_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:14 - Endpoint number"] + #[inline(always)] + pub fn epnum(&self) -> EPNUM_R { + EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8) + } + #[doc = "Bit 15 - Endpoint direction"] + #[inline(always)] + pub fn epdir(&self) -> EPDIR_R { + EPDIR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Low-speed device"] + #[inline(always)] + pub fn lsdev(&self) -> LSDEV_R { + LSDEV_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + pub fn eptyp(&self) -> EPTYP_R { + EPTYP_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] + #[inline(always)] + pub fn mc(&self) -> MC_R { + MC_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:28 - Device address"] + #[inline(always)] + pub fn dad(&self) -> DAD_R { + DAD_R::new(((self.bits >> 22) & 0x7f) as u8) + } + #[doc = "Bit 29 - Odd frame"] + #[inline(always)] + pub fn oddfrm(&self) -> ODDFRM_R { + ODDFRM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Channel disable"] + #[inline(always)] + pub fn chdis(&self) -> CHDIS_R { + CHDIS_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Channel enable"] + #[inline(always)] + pub fn chena(&self) -> CHENA_R { + CHENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Maximum packet size"] + #[inline(always)] + #[must_use] + pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + MPSIZ_W::new(self) + } + #[doc = "Bits 11:14 - Endpoint number"] + #[inline(always)] + #[must_use] + pub fn epnum(&mut self) -> EPNUM_W<11> { + EPNUM_W::new(self) + } + #[doc = "Bit 15 - Endpoint direction"] + #[inline(always)] + #[must_use] + pub fn epdir(&mut self) -> EPDIR_W<15> { + EPDIR_W::new(self) + } + #[doc = "Bit 17 - Low-speed device"] + #[inline(always)] + #[must_use] + pub fn lsdev(&mut self) -> LSDEV_W<17> { + LSDEV_W::new(self) + } + #[doc = "Bits 18:19 - Endpoint type"] + #[inline(always)] + #[must_use] + pub fn eptyp(&mut self) -> EPTYP_W<18> { + EPTYP_W::new(self) + } + #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] + #[inline(always)] + #[must_use] + pub fn mc(&mut self) -> MC_W<20> { + MC_W::new(self) + } + #[doc = "Bits 22:28 - Device address"] + #[inline(always)] + #[must_use] + pub fn dad(&mut self) -> DAD_W<22> { + DAD_W::new(self) + } + #[doc = "Bit 29 - Odd frame"] + #[inline(always)] + #[must_use] + pub fn oddfrm(&mut self) -> ODDFRM_W<29> { + ODDFRM_W::new(self) + } + #[doc = "Bit 30 - Channel disable"] + #[inline(always)] + #[must_use] + pub fn chdis(&mut self) -> CHDIS_W<30> { + CHDIS_W::new(self) + } + #[doc = "Bit 31 - Channel enable"] + #[inline(always)] + #[must_use] + pub fn chena(&mut self) -> CHENA_W<31> { + CHENA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Characteristics register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcchar](index.html) module"] +pub struct HCCHAR_SPEC; +impl crate::RegisterSpec for HCCHAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcchar::R](R) reader structure"] +impl crate::Readable for HCCHAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcchar::W](W) writer structure"] +impl crate::Writable for HCCHAR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCCHAR to value 0"] +impl crate::Resettable for HCCHAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs new file mode 100644 index 0000000..bfcef2a --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs @@ -0,0 +1,80 @@ +#[doc = "Register `HCDMA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCDMA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMAADDR` reader - DMA address"] +pub type DMAADDR_R = crate::FieldReader; +#[doc = "Field `DMAADDR` writer - DMA address"] +pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCDMA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + pub fn dmaaddr(&self) -> DMAADDR_R { + DMAADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - DMA address"] + #[inline(always)] + #[must_use] + pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + DMAADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcdma](index.html) module"] +pub struct HCDMA_SPEC; +impl crate::RegisterSpec for HCDMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcdma::R](R) reader structure"] +impl crate::Readable for HCDMA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcdma::W](W) writer structure"] +impl crate::Writable for HCDMA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCDMA to value 0"] +impl crate::Resettable for HCDMA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs new file mode 100644 index 0000000..a8ef9ea --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs @@ -0,0 +1,230 @@ +#[doc = "Register `HCINT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCINT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRC` reader - Transfer completed"] +pub type XFRC_R = crate::BitReader; +#[doc = "Field `XFRC` writer - Transfer completed"] +pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `CHH` reader - Channel halted"] +pub type CHH_R = crate::BitReader; +#[doc = "Field `CHH` writer - Channel halted"] +pub type CHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `AHBERR` reader - AHB error"] +pub type AHBERR_R = crate::BitReader; +#[doc = "Field `AHBERR` writer - AHB error"] +pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `STALL` reader - STALL response received interrupt"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `STALL` writer - STALL response received interrupt"] +pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `NAK` reader - NAK response received interrupt"] +pub type NAK_R = crate::BitReader; +#[doc = "Field `NAK` writer - NAK response received interrupt"] +pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `ACK` reader - ACK response received/transmitted interrupt"] +pub type ACK_R = crate::BitReader; +#[doc = "Field `ACK` writer - ACK response received/transmitted interrupt"] +pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `NYET` reader - Response received interrupt"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - Response received interrupt"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `TXERR` reader - Transaction error"] +pub type TXERR_R = crate::BitReader; +#[doc = "Field `TXERR` writer - Transaction error"] +pub type TXERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `BBERR` reader - Babble error"] +pub type BBERR_R = crate::BitReader; +#[doc = "Field `BBERR` writer - Babble error"] +pub type BBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `FRMOR` reader - Frame overrun"] +pub type FRMOR_R = crate::BitReader; +#[doc = "Field `FRMOR` writer - Frame overrun"] +pub type FRMOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +#[doc = "Field `DTERR` reader - Data toggle error"] +pub type DTERR_R = crate::BitReader; +#[doc = "Field `DTERR` writer - Data toggle error"] +pub type DTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed"] + #[inline(always)] + pub fn xfrc(&self) -> XFRC_R { + XFRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel halted"] + #[inline(always)] + pub fn chh(&self) -> CHH_R { + CHH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + pub fn ahberr(&self) -> AHBERR_R { + AHBERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STALL response received interrupt"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NAK response received interrupt"] + #[inline(always)] + pub fn nak(&self) -> NAK_R { + NAK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt"] + #[inline(always)] + pub fn ack(&self) -> ACK_R { + ACK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Response received interrupt"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transaction error"] + #[inline(always)] + pub fn txerr(&self) -> TXERR_R { + TXERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Babble error"] + #[inline(always)] + pub fn bberr(&self) -> BBERR_R { + BBERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame overrun"] + #[inline(always)] + pub fn frmor(&self) -> FRMOR_R { + FRMOR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data toggle error"] + #[inline(always)] + pub fn dterr(&self) -> DTERR_R { + DTERR_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed"] + #[inline(always)] + #[must_use] + pub fn xfrc(&mut self) -> XFRC_W<0> { + XFRC_W::new(self) + } + #[doc = "Bit 1 - Channel halted"] + #[inline(always)] + #[must_use] + pub fn chh(&mut self) -> CHH_W<1> { + CHH_W::new(self) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + #[must_use] + pub fn ahberr(&mut self) -> AHBERR_W<2> { + AHBERR_W::new(self) + } + #[doc = "Bit 3 - STALL response received interrupt"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W<3> { + STALL_W::new(self) + } + #[doc = "Bit 4 - NAK response received interrupt"] + #[inline(always)] + #[must_use] + pub fn nak(&mut self) -> NAK_W<4> { + NAK_W::new(self) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt"] + #[inline(always)] + #[must_use] + pub fn ack(&mut self) -> ACK_W<5> { + ACK_W::new(self) + } + #[doc = "Bit 6 - Response received interrupt"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<6> { + NYET_W::new(self) + } + #[doc = "Bit 7 - Transaction error"] + #[inline(always)] + #[must_use] + pub fn txerr(&mut self) -> TXERR_W<7> { + TXERR_W::new(self) + } + #[doc = "Bit 8 - Babble error"] + #[inline(always)] + #[must_use] + pub fn bberr(&mut self) -> BBERR_W<8> { + BBERR_W::new(self) + } + #[doc = "Bit 9 - Frame overrun"] + #[inline(always)] + #[must_use] + pub fn frmor(&mut self) -> FRMOR_W<9> { + FRMOR_W::new(self) + } + #[doc = "Bit 10 - Data toggle error"] + #[inline(always)] + #[must_use] + pub fn dterr(&mut self) -> DTERR_W<10> { + DTERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcint](index.html) module"] +pub struct HCINT_SPEC; +impl crate::RegisterSpec for HCINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcint::R](R) reader structure"] +impl crate::Readable for HCINT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcint::W](W) writer structure"] +impl crate::Writable for HCINT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCINT to value 0"] +impl crate::Resettable for HCINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs new file mode 100644 index 0000000..e158cb4 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs @@ -0,0 +1,230 @@ +#[doc = "Register `HCINTMSK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCINTMSK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRCM` reader - Transfer completed mask"] +pub type XFRCM_R = crate::BitReader; +#[doc = "Field `XFRCM` writer - Transfer completed mask"] +pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `CHHM` reader - Channel halted mask"] +pub type CHHM_R = crate::BitReader; +#[doc = "Field `CHHM` writer - Channel halted mask"] +pub type CHHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `AHBERR` reader - AHB error"] +pub type AHBERR_R = crate::BitReader; +#[doc = "Field `AHBERR` writer - AHB error"] +pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `STALLM` reader - STALL response received interrupt mask"] +pub type STALLM_R = crate::BitReader; +#[doc = "Field `STALLM` writer - STALL response received interrupt mask"] +pub type STALLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `NAKM` reader - NAK response received interrupt mask"] +pub type NAKM_R = crate::BitReader; +#[doc = "Field `NAKM` writer - NAK response received interrupt mask"] +pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `ACKM` reader - ACK response received/transmitted interrupt mask"] +pub type ACKM_R = crate::BitReader; +#[doc = "Field `ACKM` writer - ACK response received/transmitted interrupt mask"] +pub type ACKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `NYET` reader - response received interrupt mask"] +pub type NYET_R = crate::BitReader; +#[doc = "Field `NYET` writer - response received interrupt mask"] +pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `TXERRM` reader - Transaction error mask"] +pub type TXERRM_R = crate::BitReader; +#[doc = "Field `TXERRM` writer - Transaction error mask"] +pub type TXERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `BBERRM` reader - Babble error mask"] +pub type BBERRM_R = crate::BitReader; +#[doc = "Field `BBERRM` writer - Babble error mask"] +pub type BBERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `FRMORM` reader - Frame overrun mask"] +pub type FRMORM_R = crate::BitReader; +#[doc = "Field `FRMORM` writer - Frame overrun mask"] +pub type FRMORM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +#[doc = "Field `DTERRM` reader - Data toggle error mask"] +pub type DTERRM_R = crate::BitReader; +#[doc = "Field `DTERRM` writer - Data toggle error mask"] +pub type DTERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer completed mask"] + #[inline(always)] + pub fn xfrcm(&self) -> XFRCM_R { + XFRCM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel halted mask"] + #[inline(always)] + pub fn chhm(&self) -> CHHM_R { + CHHM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + pub fn ahberr(&self) -> AHBERR_R { + AHBERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STALL response received interrupt mask"] + #[inline(always)] + pub fn stallm(&self) -> STALLM_R { + STALLM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NAK response received interrupt mask"] + #[inline(always)] + pub fn nakm(&self) -> NAKM_R { + NAKM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] + #[inline(always)] + pub fn ackm(&self) -> ACKM_R { + ACKM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - response received interrupt mask"] + #[inline(always)] + pub fn nyet(&self) -> NYET_R { + NYET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transaction error mask"] + #[inline(always)] + pub fn txerrm(&self) -> TXERRM_R { + TXERRM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Babble error mask"] + #[inline(always)] + pub fn bberrm(&self) -> BBERRM_R { + BBERRM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Frame overrun mask"] + #[inline(always)] + pub fn frmorm(&self) -> FRMORM_R { + FRMORM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data toggle error mask"] + #[inline(always)] + pub fn dterrm(&self) -> DTERRM_R { + DTERRM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer completed mask"] + #[inline(always)] + #[must_use] + pub fn xfrcm(&mut self) -> XFRCM_W<0> { + XFRCM_W::new(self) + } + #[doc = "Bit 1 - Channel halted mask"] + #[inline(always)] + #[must_use] + pub fn chhm(&mut self) -> CHHM_W<1> { + CHHM_W::new(self) + } + #[doc = "Bit 2 - AHB error"] + #[inline(always)] + #[must_use] + pub fn ahberr(&mut self) -> AHBERR_W<2> { + AHBERR_W::new(self) + } + #[doc = "Bit 3 - STALL response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn stallm(&mut self) -> STALLM_W<3> { + STALLM_W::new(self) + } + #[doc = "Bit 4 - NAK response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nakm(&mut self) -> NAKM_W<4> { + NAKM_W::new(self) + } + #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] + #[inline(always)] + #[must_use] + pub fn ackm(&mut self) -> ACKM_W<5> { + ACKM_W::new(self) + } + #[doc = "Bit 6 - response received interrupt mask"] + #[inline(always)] + #[must_use] + pub fn nyet(&mut self) -> NYET_W<6> { + NYET_W::new(self) + } + #[doc = "Bit 7 - Transaction error mask"] + #[inline(always)] + #[must_use] + pub fn txerrm(&mut self) -> TXERRM_W<7> { + TXERRM_W::new(self) + } + #[doc = "Bit 8 - Babble error mask"] + #[inline(always)] + #[must_use] + pub fn bberrm(&mut self) -> BBERRM_W<8> { + BBERRM_W::new(self) + } + #[doc = "Bit 9 - Frame overrun mask"] + #[inline(always)] + #[must_use] + pub fn frmorm(&mut self) -> FRMORM_W<9> { + FRMORM_W::new(self) + } + #[doc = "Bit 10 - Data toggle error mask"] + #[inline(always)] + #[must_use] + pub fn dterrm(&mut self) -> DTERRM_W<10> { + DTERRM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcintmsk](index.html) module"] +pub struct HCINTMSK_SPEC; +impl crate::RegisterSpec for HCINTMSK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcintmsk::R](R) reader structure"] +impl crate::Readable for HCINTMSK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcintmsk::W](W) writer structure"] +impl crate::Writable for HCINTMSK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCINTMSK to value 0"] +impl crate::Resettable for HCINTMSK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs new file mode 100644 index 0000000..b20ca79 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs @@ -0,0 +1,140 @@ +#[doc = "Register `HCSPLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCSPLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRTADDR` reader - Port address"] +pub type PRTADDR_R = crate::FieldReader; +#[doc = "Field `PRTADDR` writer - Port address"] +pub type PRTADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +#[doc = "Field `HUBADDR` reader - Hub address"] +pub type HUBADDR_R = crate::FieldReader; +#[doc = "Field `HUBADDR` writer - Hub address"] +pub type HUBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +#[doc = "Field `XACTPOS` reader - XACTPOS"] +pub type XACTPOS_R = crate::FieldReader; +#[doc = "Field `XACTPOS` writer - XACTPOS"] +pub type XACTPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 2, O>; +#[doc = "Field `COMPLSPLT` reader - Do complete split"] +pub type COMPLSPLT_R = crate::BitReader; +#[doc = "Field `COMPLSPLT` writer - Do complete split"] +pub type COMPLSPLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +#[doc = "Field `SPLITEN` reader - Split enable"] +pub type SPLITEN_R = crate::BitReader; +#[doc = "Field `SPLITEN` writer - Split enable"] +pub type SPLITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Port address"] + #[inline(always)] + pub fn prtaddr(&self) -> PRTADDR_R { + PRTADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Hub address"] + #[inline(always)] + pub fn hubaddr(&self) -> HUBADDR_R { + HUBADDR_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:15 - XACTPOS"] + #[inline(always)] + pub fn xactpos(&self) -> XACTPOS_R { + XACTPOS_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - Do complete split"] + #[inline(always)] + pub fn complsplt(&self) -> COMPLSPLT_R { + COMPLSPLT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 31 - Split enable"] + #[inline(always)] + pub fn spliten(&self) -> SPLITEN_R { + SPLITEN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Port address"] + #[inline(always)] + #[must_use] + pub fn prtaddr(&mut self) -> PRTADDR_W<0> { + PRTADDR_W::new(self) + } + #[doc = "Bits 7:13 - Hub address"] + #[inline(always)] + #[must_use] + pub fn hubaddr(&mut self) -> HUBADDR_W<7> { + HUBADDR_W::new(self) + } + #[doc = "Bits 14:15 - XACTPOS"] + #[inline(always)] + #[must_use] + pub fn xactpos(&mut self) -> XACTPOS_W<14> { + XACTPOS_W::new(self) + } + #[doc = "Bit 16 - Do complete split"] + #[inline(always)] + #[must_use] + pub fn complsplt(&mut self) -> COMPLSPLT_W<16> { + COMPLSPLT_W::new(self) + } + #[doc = "Bit 31 - Split enable"] + #[inline(always)] + #[must_use] + pub fn spliten(&mut self) -> SPLITEN_W<31> { + SPLITEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Split control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcsplt](index.html) module"] +pub struct HCSPLT_SPEC; +impl crate::RegisterSpec for HCSPLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hcsplt::R](R) reader structure"] +impl crate::Readable for HCSPLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hcsplt::W](W) writer structure"] +impl crate::Writable for HCSPLT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCSPLT to value 0"] +impl crate::Resettable for HCSPLT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs new file mode 100644 index 0000000..a7361fd --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs @@ -0,0 +1,110 @@ +#[doc = "Register `HCTSIZ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HCTSIZ` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XFRSIZ` reader - Transfer size"] +pub type XFRSIZ_R = crate::FieldReader; +#[doc = "Field `XFRSIZ` writer - Transfer size"] +pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u32, u32, 19, O>; +#[doc = "Field `PKTCNT` reader - Packet count"] +pub type PKTCNT_R = crate::FieldReader; +#[doc = "Field `PKTCNT` writer - Packet count"] +pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u16, u16, 10, O>; +#[doc = "Field `DPID` reader - Data PID"] +pub type DPID_R = crate::FieldReader; +#[doc = "Field `DPID` writer - Data PID"] +pub type DPID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:18 - Transfer size"] + #[inline(always)] + pub fn xfrsiz(&self) -> XFRSIZ_R { + XFRSIZ_R::new(self.bits & 0x0007_ffff) + } + #[doc = "Bits 19:28 - Packet count"] + #[inline(always)] + pub fn pktcnt(&self) -> PKTCNT_R { + PKTCNT_R::new(((self.bits >> 19) & 0x03ff) as u16) + } + #[doc = "Bits 29:30 - Data PID"] + #[inline(always)] + pub fn dpid(&self) -> DPID_R { + DPID_R::new(((self.bits >> 29) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:18 - Transfer size"] + #[inline(always)] + #[must_use] + pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + XFRSIZ_W::new(self) + } + #[doc = "Bits 19:28 - Packet count"] + #[inline(always)] + #[must_use] + pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + PKTCNT_W::new(self) + } + #[doc = "Bits 29:30 - Data PID"] + #[inline(always)] + #[must_use] + pub fn dpid(&mut self) -> DPID_W<29> { + DPID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctsiz](index.html) module"] +pub struct HCTSIZ_SPEC; +impl crate::RegisterSpec for HCTSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hctsiz::R](R) reader structure"] +impl crate::Readable for HCTSIZ_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hctsiz::W](W) writer structure"] +impl crate::Writable for HCTSIZ_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HCTSIZ to value 0"] +impl crate::Resettable for HCTSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs b/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs new file mode 100644 index 0000000..cb893f3 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs @@ -0,0 +1,228 @@ +#[doc = "Register `HPRT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPRT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PCSTS` reader - Port connect status"] +pub type PCSTS_R = crate::BitReader; +#[doc = "Field `PCDET` reader - Port connect detected"] +pub type PCDET_R = crate::BitReader; +#[doc = "Field `PCDET` writer - Port connect detected"] +pub type PCDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PENA` reader - Port enable"] +pub type PENA_R = crate::BitReader; +#[doc = "Field `PENA` writer - Port enable"] +pub type PENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PENCHNG` reader - Port enable/disable change"] +pub type PENCHNG_R = crate::BitReader; +#[doc = "Field `PENCHNG` writer - Port enable/disable change"] +pub type PENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `POCA` reader - Port overcurrent active"] +pub type POCA_R = crate::BitReader; +#[doc = "Field `POCCHNG` reader - Port overcurrent change"] +pub type POCCHNG_R = crate::BitReader; +#[doc = "Field `POCCHNG` writer - Port overcurrent change"] +pub type POCCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PRES` reader - Port resume"] +pub type PRES_R = crate::BitReader; +#[doc = "Field `PRES` writer - Port resume"] +pub type PRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PSUSP` reader - Port suspend"] +pub type PSUSP_R = crate::BitReader; +#[doc = "Field `PSUSP` writer - Port suspend"] +pub type PSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PRST` reader - Port reset"] +pub type PRST_R = crate::BitReader; +#[doc = "Field `PRST` writer - Port reset"] +pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PLSTS` reader - Port line status"] +pub type PLSTS_R = crate::FieldReader; +#[doc = "Field `PPWR` reader - Port power"] +pub type PPWR_R = crate::BitReader; +#[doc = "Field `PPWR` writer - Port power"] +pub type PPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +#[doc = "Field `PTCTL` reader - Port test control"] +pub type PTCTL_R = crate::FieldReader; +#[doc = "Field `PTCTL` writer - Port test control"] +pub type PTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, u8, 4, O>; +#[doc = "Field `PSPD` reader - Port speed"] +pub type PSPD_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Port connect status"] + #[inline(always)] + pub fn pcsts(&self) -> PCSTS_R { + PCSTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Port connect detected"] + #[inline(always)] + pub fn pcdet(&self) -> PCDET_R { + PCDET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Port enable"] + #[inline(always)] + pub fn pena(&self) -> PENA_R { + PENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Port enable/disable change"] + #[inline(always)] + pub fn penchng(&self) -> PENCHNG_R { + PENCHNG_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Port overcurrent active"] + #[inline(always)] + pub fn poca(&self) -> POCA_R { + POCA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Port overcurrent change"] + #[inline(always)] + pub fn pocchng(&self) -> POCCHNG_R { + POCCHNG_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Port resume"] + #[inline(always)] + pub fn pres(&self) -> PRES_R { + PRES_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Port suspend"] + #[inline(always)] + pub fn psusp(&self) -> PSUSP_R { + PSUSP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Port reset"] + #[inline(always)] + pub fn prst(&self) -> PRST_R { + PRST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 10:11 - Port line status"] + #[inline(always)] + pub fn plsts(&self) -> PLSTS_R { + PLSTS_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Port power"] + #[inline(always)] + pub fn ppwr(&self) -> PPWR_R { + PPWR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - Port test control"] + #[inline(always)] + pub fn ptctl(&self) -> PTCTL_R { + PTCTL_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:18 - Port speed"] + #[inline(always)] + pub fn pspd(&self) -> PSPD_R { + PSPD_R::new(((self.bits >> 17) & 3) as u8) + } +} +impl W { + #[doc = "Bit 1 - Port connect detected"] + #[inline(always)] + #[must_use] + pub fn pcdet(&mut self) -> PCDET_W<1> { + PCDET_W::new(self) + } + #[doc = "Bit 2 - Port enable"] + #[inline(always)] + #[must_use] + pub fn pena(&mut self) -> PENA_W<2> { + PENA_W::new(self) + } + #[doc = "Bit 3 - Port enable/disable change"] + #[inline(always)] + #[must_use] + pub fn penchng(&mut self) -> PENCHNG_W<3> { + PENCHNG_W::new(self) + } + #[doc = "Bit 5 - Port overcurrent change"] + #[inline(always)] + #[must_use] + pub fn pocchng(&mut self) -> POCCHNG_W<5> { + POCCHNG_W::new(self) + } + #[doc = "Bit 6 - Port resume"] + #[inline(always)] + #[must_use] + pub fn pres(&mut self) -> PRES_W<6> { + PRES_W::new(self) + } + #[doc = "Bit 7 - Port suspend"] + #[inline(always)] + #[must_use] + pub fn psusp(&mut self) -> PSUSP_W<7> { + PSUSP_W::new(self) + } + #[doc = "Bit 8 - Port reset"] + #[inline(always)] + #[must_use] + pub fn prst(&mut self) -> PRST_W<8> { + PRST_W::new(self) + } + #[doc = "Bit 12 - Port power"] + #[inline(always)] + #[must_use] + pub fn ppwr(&mut self) -> PPWR_W<12> { + PPWR_W::new(self) + } + #[doc = "Bits 13:16 - Port test control"] + #[inline(always)] + #[must_use] + pub fn ptctl(&mut self) -> PTCTL_W<13> { + PTCTL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OTG_HS host port control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"] +pub struct HPRT_SPEC; +impl crate::RegisterSpec for HPRT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hprt::R](R) reader structure"] +impl crate::Readable for HPRT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"] +impl crate::Writable for HPRT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPRT to value 0"] +impl crate::Resettable for HPRT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs b/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs new file mode 100644 index 0000000..3cb5895 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs @@ -0,0 +1,94 @@ +#[doc = "Register `HPTXSTS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HPTXSTS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PTXFSAVL` reader - Periodic transmit data FIFO space available"] +pub type PTXFSAVL_R = crate::FieldReader; +#[doc = "Field `PTXFSAVL` writer - Periodic transmit data FIFO space available"] +pub type PTXFSAVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXSTS_SPEC, u16, u16, 16, O>; +#[doc = "Field `PTXQSAV` reader - Periodic transmit request queue space available"] +pub type PTXQSAV_R = crate::FieldReader; +#[doc = "Field `PTXQTOP` reader - Top of the periodic transmit request queue"] +pub type PTXQTOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] + #[inline(always)] + pub fn ptxfsavl(&self) -> PTXFSAVL_R { + PTXFSAVL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Periodic transmit request queue space available"] + #[inline(always)] + pub fn ptxqsav(&self) -> PTXQSAV_R { + PTXQSAV_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Top of the periodic transmit request queue"] + #[inline(always)] + pub fn ptxqtop(&self) -> PTXQTOP_R { + PTXQTOP_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] + #[inline(always)] + #[must_use] + pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<0> { + PTXFSAVL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Host periodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](index.html) module"] +pub struct HPTXSTS_SPEC; +impl crate::RegisterSpec for HPTXSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hptxsts::R](R) reader structure"] +impl crate::Readable for HPTXSTS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hptxsts::W](W) writer structure"] +impl crate::Writable for HPTXSTS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPTXSTS to value 0x0008_0100"] +impl crate::Resettable for HPTXSTS_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0100; +} diff --git a/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs b/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs new file mode 100644 index 0000000..67a9eb5 --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - power and clock gating control"] + pub pcgcctl: PCGCCTL, +} +#[doc = "PCGCCTL (rw) register accessor: an alias for `Reg`"] +pub type PCGCCTL = crate::Reg; +#[doc = "power and clock gating control"] +pub mod pcgcctl; diff --git a/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs b/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs new file mode 100644 index 0000000..061312d --- /dev/null +++ b/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs @@ -0,0 +1,293 @@ +#[doc = "Register `PCGCCTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCGCCTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STPPCLK` reader - Stop PHY clock"] +pub type STPPCLK_R = crate::BitReader; +#[doc = "Field `STPPCLK` writer - Stop PHY clock"] +pub type STPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `GATEHCLK` reader - Gate HCLK"] +pub type GATEHCLK_R = crate::BitReader; +#[doc = "Field `GATEHCLK` writer - Gate HCLK"] +pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PWRCLMP` reader - Power clamp"] +pub type PWRCLMP_R = crate::BitReader; +#[doc = "Field `PWRCLMP` writer - Power clamp"] +pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RSTPDWNMODULE` reader - Power down modules"] +pub type RSTPDWNMODULE_R = crate::BitReader; +#[doc = "Field `RSTPDWNMODULE` writer - Power down modules"] +pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PHYSUSP` reader - PHY Suspended"] +pub type PHYSUSP_R = crate::BitReader; +#[doc = "Field `PHYSUSP` writer - PHY Suspended"] +pub type PHYSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ENABLE_L1GATING` reader - Enable sleep clock gating"] +pub type ENABLE_L1GATING_R = crate::BitReader; +#[doc = "Field `ENABLE_L1GATING` writer - Enable sleep clock gating"] +pub type ENABLE_L1GATING_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `PHYSLEEP` reader - PHY is in sleep mode"] +pub type PHYSLEEP_R = crate::BitReader; +#[doc = "Field `PHYSLEEP` writer - PHY is in sleep mode"] +pub type PHYSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `DEEPSLEEP` reader - PHY is in deep sleep"] +pub type DEEPSLEEP_R = crate::BitReader; +#[doc = "Field `DEEPSLEEP` writer - PHY is in deep sleep"] +pub type DEEPSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"] +pub type RESETAFTERSUSP_R = crate::BitReader; +#[doc = "Field `RESETAFTERSUSP` writer - Reset after suspend"] +pub type RESETAFTERSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESTOREMODE` reader - Restore mode"] +pub type RESTOREMODE_R = crate::BitReader; +#[doc = "Field `RESTOREMODE` writer - Restore mode"] +pub type RESTOREMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ENEXTNDEDHIBER` reader - Enable extended hibernation"] +pub type ENEXTNDEDHIBER_R = crate::BitReader; +#[doc = "Field `ENEXTNDEDHIBER` writer - Enable extended hibernation"] +pub type ENEXTNDEDHIBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `EXTNDEDHIBERNATIONCLAMP` reader - Extended hibernation clamp"] +pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; +#[doc = "Field `EXTNDEDHIBERNATIONCLAMP` writer - Extended hibernation clamp"] +pub type EXTNDEDHIBERNATIONCLAMP_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `EXTNDEDHIBERNATIONSWITCH` reader - Extended hibernation switch"] +pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; +#[doc = "Field `EXTNDEDHIBERNATIONSWITCH` writer - Extended hibernation switch"] +pub type EXTNDEDHIBERNATIONSWITCH_W<'a, const O: u8> = + crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `ESSREGRESTORED` reader - Essential register values restored"] +pub type ESSREGRESTORED_R = crate::BitReader; +#[doc = "Field `ESSREGRESTORED` writer - Essential register values restored"] +pub type ESSREGRESTORED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +#[doc = "Field `RESTORE_VALUE` reader - Restore value"] +pub type RESTORE_VALUE_R = crate::FieldReader; +#[doc = "Field `RESTORE_VALUE` writer - Restore value"] +pub type RESTORE_VALUE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PCGCCTL_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bit 0 - Stop PHY clock"] + #[inline(always)] + pub fn stppclk(&self) -> STPPCLK_R { + STPPCLK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gate HCLK"] + #[inline(always)] + pub fn gatehclk(&self) -> GATEHCLK_R { + GATEHCLK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Power clamp"] + #[inline(always)] + pub fn pwrclmp(&self) -> PWRCLMP_R { + PWRCLMP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Power down modules"] + #[inline(always)] + pub fn rstpdwnmodule(&self) -> RSTPDWNMODULE_R { + RSTPDWNMODULE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PHY Suspended"] + #[inline(always)] + pub fn physusp(&self) -> PHYSUSP_R { + PHYSUSP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable sleep clock gating"] + #[inline(always)] + pub fn enable_l1gating(&self) -> ENABLE_L1GATING_R { + ENABLE_L1GATING_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - PHY is in sleep mode"] + #[inline(always)] + pub fn physleep(&self) -> PHYSLEEP_R { + PHYSLEEP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - PHY is in deep sleep"] + #[inline(always)] + pub fn deepsleep(&self) -> DEEPSLEEP_R { + DEEPSLEEP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reset after suspend"] + #[inline(always)] + pub fn resetaftersusp(&self) -> RESETAFTERSUSP_R { + RESETAFTERSUSP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Restore mode"] + #[inline(always)] + pub fn restoremode(&self) -> RESTOREMODE_R { + RESTOREMODE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable extended hibernation"] + #[inline(always)] + pub fn enextndedhiber(&self) -> ENEXTNDEDHIBER_R { + ENEXTNDEDHIBER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Extended hibernation clamp"] + #[inline(always)] + pub fn extndedhibernationclamp(&self) -> EXTNDEDHIBERNATIONCLAMP_R { + EXTNDEDHIBERNATIONCLAMP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Extended hibernation switch"] + #[inline(always)] + pub fn extndedhibernationswitch(&self) -> EXTNDEDHIBERNATIONSWITCH_R { + EXTNDEDHIBERNATIONSWITCH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Essential register values restored"] + #[inline(always)] + pub fn essregrestored(&self) -> ESSREGRESTORED_R { + ESSREGRESTORED_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:31 - Restore value"] + #[inline(always)] + pub fn restore_value(&self) -> RESTORE_VALUE_R { + RESTORE_VALUE_R::new((self.bits >> 14) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bit 0 - Stop PHY clock"] + #[inline(always)] + #[must_use] + pub fn stppclk(&mut self) -> STPPCLK_W<0> { + STPPCLK_W::new(self) + } + #[doc = "Bit 1 - Gate HCLK"] + #[inline(always)] + #[must_use] + pub fn gatehclk(&mut self) -> GATEHCLK_W<1> { + GATEHCLK_W::new(self) + } + #[doc = "Bit 2 - Power clamp"] + #[inline(always)] + #[must_use] + pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> { + PWRCLMP_W::new(self) + } + #[doc = "Bit 3 - Power down modules"] + #[inline(always)] + #[must_use] + pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> { + RSTPDWNMODULE_W::new(self) + } + #[doc = "Bit 4 - PHY Suspended"] + #[inline(always)] + #[must_use] + pub fn physusp(&mut self) -> PHYSUSP_W<4> { + PHYSUSP_W::new(self) + } + #[doc = "Bit 5 - Enable sleep clock gating"] + #[inline(always)] + #[must_use] + pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W<5> { + ENABLE_L1GATING_W::new(self) + } + #[doc = "Bit 6 - PHY is in sleep mode"] + #[inline(always)] + #[must_use] + pub fn physleep(&mut self) -> PHYSLEEP_W<6> { + PHYSLEEP_W::new(self) + } + #[doc = "Bit 7 - PHY is in deep sleep"] + #[inline(always)] + #[must_use] + pub fn deepsleep(&mut self) -> DEEPSLEEP_W<7> { + DEEPSLEEP_W::new(self) + } + #[doc = "Bit 8 - Reset after suspend"] + #[inline(always)] + #[must_use] + pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<8> { + RESETAFTERSUSP_W::new(self) + } + #[doc = "Bit 9 - Restore mode"] + #[inline(always)] + #[must_use] + pub fn restoremode(&mut self) -> RESTOREMODE_W<9> { + RESTOREMODE_W::new(self) + } + #[doc = "Bit 10 - Enable extended hibernation"] + #[inline(always)] + #[must_use] + pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W<10> { + ENEXTNDEDHIBER_W::new(self) + } + #[doc = "Bit 11 - Extended hibernation clamp"] + #[inline(always)] + #[must_use] + pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W<11> { + EXTNDEDHIBERNATIONCLAMP_W::new(self) + } + #[doc = "Bit 12 - Extended hibernation switch"] + #[inline(always)] + #[must_use] + pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W<12> { + EXTNDEDHIBERNATIONSWITCH_W::new(self) + } + #[doc = "Bit 13 - Essential register values restored"] + #[inline(always)] + #[must_use] + pub fn essregrestored(&mut self) -> ESSREGRESTORED_W<13> { + ESSREGRESTORED_W::new(self) + } + #[doc = "Bits 14:31 - Restore value"] + #[inline(always)] + #[must_use] + pub fn restore_value(&mut self) -> RESTORE_VALUE_W<14> { + RESTORE_VALUE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "power and clock gating control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"] +pub struct PCGCCTL_SPEC; +impl crate::RegisterSpec for PCGCCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"] +impl crate::Readable for PCGCCTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"] +impl crate::Writable for PCGCCTL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCGCCTL to value 0x200b_8000"] +impl crate::Resettable for PCGCCTL_SPEC { + const RESET_VALUE: Self::Ux = 0x200b_8000; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox.rs b/crates/bcm2837-lpa/src/vcmailbox.rs new file mode 100644 index 0000000..7490467 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox.rs @@ -0,0 +1,66 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Read messages from the VideoCore"] + pub read: READ, + _reserved1: [u8; 0x0c], + #[doc = "0x10 - "] + pub peek0: PEEK0, + #[doc = "0x14 - "] + pub sender0: SENDER0, + #[doc = "0x18 - "] + pub status0: STATUS0, + #[doc = "0x1c - "] + pub config0: CONFIG0, + #[doc = "0x20 - Write messages to the VideoCore"] + pub write: WRITE, + _reserved6: [u8; 0x0c], + #[doc = "0x30 - "] + pub peek1: PEEK1, + #[doc = "0x34 - "] + pub sender1: SENDER1, + #[doc = "0x38 - "] + pub status1: STATUS1, + #[doc = "0x3c - "] + pub config1: CONFIG1, +} +#[doc = "READ (r) register accessor: an alias for `Reg`"] +pub type READ = crate::Reg; +#[doc = "Read messages from the VideoCore"] +pub mod read; +#[doc = "PEEK0 (rw) register accessor: an alias for `Reg`"] +pub type PEEK0 = crate::Reg; +#[doc = ""] +pub mod peek0; +#[doc = "SENDER0 (rw) register accessor: an alias for `Reg`"] +pub type SENDER0 = crate::Reg; +#[doc = ""] +pub mod sender0; +#[doc = "STATUS0 (r) register accessor: an alias for `Reg`"] +pub type STATUS0 = crate::Reg; +#[doc = ""] +pub mod status0; +#[doc = "CONFIG0 (rw) register accessor: an alias for `Reg`"] +pub type CONFIG0 = crate::Reg; +#[doc = ""] +pub mod config0; +#[doc = "WRITE (w) register accessor: an alias for `Reg`"] +pub type WRITE = crate::Reg; +#[doc = "Write messages to the VideoCore"] +pub mod write; +#[doc = "PEEK1 (rw) register accessor: an alias for `Reg`"] +pub type PEEK1 = crate::Reg; +#[doc = ""] +pub mod peek1; +#[doc = "SENDER1 (rw) register accessor: an alias for `Reg`"] +pub type SENDER1 = crate::Reg; +#[doc = ""] +pub mod sender1; +#[doc = "STATUS1 (rw) register accessor: an alias for `Reg`"] +pub type STATUS1 = crate::Reg; +#[doc = ""] +pub mod status1; +#[doc = "CONFIG1 (rw) register accessor: an alias for `Reg`"] +pub type CONFIG1 = crate::Reg; +#[doc = ""] +pub mod config1; diff --git a/crates/bcm2837-lpa/src/vcmailbox/config0.rs b/crates/bcm2837-lpa/src/vcmailbox/config0.rs new file mode 100644 index 0000000..dce060f --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/config0.rs @@ -0,0 +1,76 @@ +#[doc = "Register `CONFIG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IRQEN` reader - Enable the interrupt when data is available"] +pub type IRQEN_R = crate::BitReader; +#[doc = "Field `IRQEN` writer - Enable the interrupt when data is available"] +pub type IRQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG0_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Enable the interrupt when data is available"] + #[inline(always)] + pub fn irqen(&self) -> IRQEN_R { + IRQEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the interrupt when data is available"] + #[inline(always)] + #[must_use] + pub fn irqen(&mut self) -> IRQEN_W<0> { + IRQEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config0](index.html) module"] +pub struct CONFIG0_SPEC; +impl crate::RegisterSpec for CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config0::R](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config0::W](W) writer structure"] +impl crate::Writable for CONFIG0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/config1.rs b/crates/bcm2837-lpa/src/vcmailbox/config1.rs new file mode 100644 index 0000000..3c238a6 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/config1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `CONFIG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config1](index.html) module"] +pub struct CONFIG1_SPEC; +impl crate::RegisterSpec for CONFIG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config1::R](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config1::W](W) writer structure"] +impl crate::Writable for CONFIG1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/peek0.rs b/crates/bcm2837-lpa/src/vcmailbox/peek0.rs new file mode 100644 index 0000000..3b63843 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/peek0.rs @@ -0,0 +1,59 @@ +#[doc = "Register `PEEK0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PEEK0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek0](index.html) module"] +pub struct PEEK0_SPEC; +impl crate::RegisterSpec for PEEK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek0::R](R) reader structure"] +impl crate::Readable for PEEK0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peek0::W](W) writer structure"] +impl crate::Writable for PEEK0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/peek1.rs b/crates/bcm2837-lpa/src/vcmailbox/peek1.rs new file mode 100644 index 0000000..2431cc4 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/peek1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `PEEK1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PEEK1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek1](index.html) module"] +pub struct PEEK1_SPEC; +impl crate::RegisterSpec for PEEK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peek1::R](R) reader structure"] +impl crate::Readable for PEEK1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peek1::W](W) writer structure"] +impl crate::Writable for PEEK1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/read.rs b/crates/bcm2837-lpa/src/vcmailbox/read.rs new file mode 100644 index 0000000..60b2d04 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/read.rs @@ -0,0 +1,24 @@ +#[doc = "Register `READ` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Read messages from the VideoCore\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [read](index.html) module"] +pub struct READ_SPEC; +impl crate::RegisterSpec for READ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [read::R](R) reader structure"] +impl crate::Readable for READ_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/sender0.rs b/crates/bcm2837-lpa/src/vcmailbox/sender0.rs new file mode 100644 index 0000000..cbeb2f1 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/sender0.rs @@ -0,0 +1,59 @@ +#[doc = "Register `SENDER0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SENDER0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender0](index.html) module"] +pub struct SENDER0_SPEC; +impl crate::RegisterSpec for SENDER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sender0::R](R) reader structure"] +impl crate::Readable for SENDER0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sender0::W](W) writer structure"] +impl crate::Writable for SENDER0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/sender1.rs b/crates/bcm2837-lpa/src/vcmailbox/sender1.rs new file mode 100644 index 0000000..1537c2d --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/sender1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `SENDER1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SENDER1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender1](index.html) module"] +pub struct SENDER1_SPEC; +impl crate::RegisterSpec for SENDER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sender1::R](R) reader structure"] +impl crate::Readable for SENDER1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sender1::W](W) writer structure"] +impl crate::Writable for SENDER1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/status0.rs b/crates/bcm2837-lpa/src/vcmailbox/status0.rs new file mode 100644 index 0000000..035e2a4 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/status0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `STATUS0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EMPTY` reader - "] +pub type EMPTY_R = crate::BitReader; +#[doc = "Field `FULL` reader - "] +pub type FULL_R = crate::BitReader; +impl R { + #[doc = "Bit 30"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status0](index.html) module"] +pub struct STATUS0_SPEC; +impl crate::RegisterSpec for STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status0::R](R) reader structure"] +impl crate::Readable for STATUS0_SPEC { + type Reader = R; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/status1.rs b/crates/bcm2837-lpa/src/vcmailbox/status1.rs new file mode 100644 index 0000000..1a7b501 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/status1.rs @@ -0,0 +1,59 @@ +#[doc = "Register `STATUS1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status1](index.html) module"] +pub struct STATUS1_SPEC; +impl crate::RegisterSpec for STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status1::R](R) reader structure"] +impl crate::Readable for STATUS1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status1::W](W) writer structure"] +impl crate::Writable for STATUS1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/crates/bcm2837-lpa/src/vcmailbox/write.rs b/crates/bcm2837-lpa/src/vcmailbox/write.rs new file mode 100644 index 0000000..4e09735 --- /dev/null +++ b/crates/bcm2837-lpa/src/vcmailbox/write.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WRITE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write messages to the VideoCore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [write](index.html) module"] +pub struct WRITE_SPEC; +impl crate::RegisterSpec for WRITE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [write::W](W) writer structure"] +impl crate::Writable for WRITE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} diff --git a/gen.sh b/gen.sh new file mode 100755 index 0000000..0c9c7ce --- /dev/null +++ b/gen.sh @@ -0,0 +1,22 @@ +#!/bin/sh -e + +print_usage() { + echo 'Usage: gen.sh MCU_NAME' >&2 +} + +if [ $# -ne 1 ]; then + print_usage + exit 1 +fi + +mcu_name=$1 + +cd "crates/${mcu_name}-lpa/" + +svd2rust -i "../../peripherals/svd/gen/${mcu_name}_lpa.svd" --target none \ + --atomics + +rm -rf src/ +form -i lib.rs -o src/ +rm lib.rs +cargo fmt diff --git a/peripherals b/peripherals new file mode 160000 index 0000000..6bc44a4 --- /dev/null +++ b/peripherals @@ -0,0 +1 @@ +Subproject commit 6bc44a4fd5c956249b9d8815f66a9df41b5791b1