Example use of VIXL

src/coreclr/inc/clr_std/utility

@@ -84,6 +84,8 @@ namespace std
         {   // construct from compatible pair
         }
 
+        constexpr pair(const pair&) = default;    ///< Copy constructor
+
         void swap(_Myt& _Right)
         {   // exchange contents with _Right
             if (this != &_Right)
@@ -243,6 +245,11 @@ namespace std
         return (_Pair.second);
     }
 
+    template<typename _T1, typename _T2>
+    inline pair<_T1, _T2>
+    make_pair(_T1 __x, _T2 __y)
+    { return std::pair<_T1, _T2>(__x, __y); }
+
 } // namespace std
 
 #endif /* __clr_std_utility_h__ */

src/coreclr/jit/CMakeLists.txt

@@ -1,5 +1,7 @@
 set(CMAKE_INCLUDE_CURRENT_DIR ON)
 
+set(CMAKE_EXTRA_INCLUDE_FILES signal.h)
+
 include_directories("./jitstd")
 include_directories("../inc")
 
@@ -241,6 +243,21 @@ set( JIT_ARM64_SOURCES
   unwindarm64.cpp
   hwintrinsicarm64.cpp
   hwintrinsiccodegenarm64.cpp
+  vixl/code-buffer-vixl.cc
+  vixl/compiler-intrinsics-vixl.cc
+  vixl/cpu-features.cc
+  vixl/utils-vixl.cc
+  vixl/aarch64/assembler-aarch64.cc
+  vixl/aarch64/assembler-sve-aarch64.cc
+  vixl/aarch64/cpu-aarch64.cc
+  vixl/aarch64/cpu-features-auditor-aarch64.cc
+  vixl/aarch64/decoder-aarch64.cc
+  vixl/aarch64/disasm-aarch64.cc
+  vixl/aarch64/instructions-aarch64.cc
+  vixl/aarch64/macro-assembler-aarch64.cc
+  vixl/aarch64/macro-assembler-sve-aarch64.cc
+  vixl/aarch64/operands-aarch64.cc
+  vixl/aarch64/registers-aarch64.cc
 )
 
 set( JIT_ARMV6_SOURCES
@@ -402,6 +419,31 @@ set( JIT_ARM64_HEADERS
     instrsarm64.h
     registerarm64.h
     simdashwintrinsiclistarm64.h
+    abi-aarch64.h
+  assembler-aarch64.h
+  constants-aarch64.h
+  cpu-aarch64.h
+  cpu-features-auditor-aarch64.h
+  decoder-aarch64.h
+  decoder-constants-aarch64.h
+  disasm-aarch64.h
+  instructions-aarch64.h
+  macro-assembler-aarch64.h
+  operands-aarch64.h
+  registers-aarch64.h
+  vixl/aarch64/assembler-base-vixl.h
+  vixl/aarch64/code-buffer-vixl.h
+  vixl/aarch64/code-generation-scopes-vixl.h
+  vixl/aarch64/compiler-intrinsics-vixl.h
+  vixl/cpu-features.h
+  vixl/globals-vixl.h
+  vixl/invalset-vixl.h
+  vixl/macro-assembler-interface.h
+  vixl/simulator-constants-aarch64.h
+  vixl/platform-vixl.h
+  vixl/pool-manager-impl.h
+  vixl/pool-manager.h
+  vixl/utils-vixl.h
 )
 
 set( JIT_ARM_HEADERS

src/coreclr/jit/codegen.h

@@ -13,6 +13,8 @@
 #include "compiler.h" // temporary??
 #include "regset.h"
 #include "jitgcinfo.h"
+#include "vixl/aarch64/macro-assembler-aarch64.h"
+#include "vixl/aarch64/disasm-aarch64.h"
 
 class CodeGen final : public CodeGenInterface
 {
@@ -35,6 +37,10 @@ class CodeGen final : public CodeGenInterface
         GenTree* addr, bool fold, bool* revPtr, GenTree** rv1Ptr, GenTree** rv2Ptr, unsigned* mulPtr, ssize_t* cnsPtr);
 
 private:
+
+    vixl::aarch64::MacroAssembler vixlMasm;
+    vixl::aarch64::PrintDisassembler vixlDisasm;
+
 #if defined(TARGET_XARCH)
     // Bit masks used in negating a float or double number.
     // This is to avoid creating more than one data constant for these bitmasks when a

src/coreclr/jit/codegenarmarch.cpp

@@ -1573,15 +1573,59 @@ void CodeGen::genCodeForShift(GenTree* tree)
 
     GenTree* operand = tree->gtGetOp1();
     GenTree* shiftBy = tree->gtGetOp2();
+
+    vixl::aarch64::Register dest_reg(tree->GetRegNum(), size * vixl::kBitsPerByte);
+    vixl::aarch64::Register operand_reg(operand->GetRegNum(), size * vixl::kBitsPerByte);
+
+
     if (!shiftBy->IsCnsIntOrI())
     {
         GetEmitter()->emitIns_R_R_R(ins, size, dstReg, operand->GetRegNum(), shiftBy->GetRegNum());
+
+        vixl::aarch64::Register shiftBy_reg(shiftBy->GetRegNum(), size * vixl::kBitsPerByte);
+
+        switch(tree->gtOper)
+        {
+        case GT_LSH:
+            vixlMasm.Lsl(dest_reg, operand_reg, shiftBy_reg);
+            break;
+        case GT_RSH:
+            vixlMasm.Asr(dest_reg, operand_reg, shiftBy_reg);
+            break;
+        case GT_RSZ:
+            vixlMasm.Lsr(dest_reg, operand_reg, shiftBy_reg);
+            break;
+        case GT_ROR:
+            vixlMasm.Ror(dest_reg, operand_reg, shiftBy_reg);
+            break;
+        default:
+            assert(false);
+        }
+
     }
     else
     {
         unsigned immWidth   = emitter::getBitWidth(size); // For ARM64, immWidth will be set to 32 or 64
         unsigned shiftByImm = (unsigned)shiftBy->AsIntCon()->gtIconVal & (immWidth - 1);
         GetEmitter()->emitIns_R_R_I(ins, size, dstReg, operand->GetRegNum(), shiftByImm);
+
+        switch(tree->gtOper)
+        {
+        case GT_LSH:
+            vixlMasm.Lsl(dest_reg, operand_reg, shiftByImm);
+            break;
+        case GT_RSH:
+            vixlMasm.Asr(dest_reg, operand_reg, shiftByImm);
+            break;
+        case GT_RSZ:
+            vixlMasm.Lsr(dest_reg, operand_reg, shiftByImm);
+            break;
+        case GT_ROR:
+            vixlMasm.Ror(dest_reg, operand_reg, shiftByImm);
+            break;
+        default:
+            assert(false);
+        }
     }
 
     genProduceReg(tree);

src/coreclr/jit/codegencommon.cpp

@@ -83,7 +83,8 @@ void CodeGenInterface::CopyRegisterInfo()
 
 /*****************************************************************************/
 
-CodeGen::CodeGen(Compiler* theCompiler) : CodeGenInterface(theCompiler)
+CodeGen::CodeGen(Compiler* theCompiler)
+    : CodeGenInterface(theCompiler), vixlMasm(theCompiler), vixlDisasm(theCompiler, jitstdout())
 {
 #if defined(TARGET_XARCH)
     negBitmaskFlt  = nullptr;

src/coreclr/jit/codegenlinear.cpp

@@ -16,6 +16,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
 #include "emit.h"
 #include "codegen.h"
+#include "vixl/aarch64/macro-assembler-aarch64.h"
+#include "vixl/aarch64/disasm-aarch64.h"
 
 //------------------------------------------------------------------------
 // genInitializeRegisterState: Initialize the register state contained in 'regSet'.
@@ -162,6 +164,11 @@ void CodeGen::genCodeForBBlist()
     /* Initialize structures used in the block list iteration */
     genInitialize();
 
+    // Clear the VIXL buffer and get a label pointing to the start.
+    vixl::aarch64::Label vixlCodeStart, vixlCodeEnd;
+    vixlMasm.Reset();
+    vixlMasm.Bind(&vixlCodeStart);
+
     /*-------------------------------------------------------------------------
      *
      *  Walk the basic blocks and generate code for each one
@@ -839,6 +846,34 @@ void CodeGen::genCodeForBBlist()
 #endif // DEBUG
     }  //------------------ END-FOR each block of the method -------------------
 
+
+    // Tell vixl we've finished generating code and get a label pointing to the end
+    vixlMasm.Bind(&vixlCodeEnd);
+    vixlMasm.FinalizeCode();
+    vixl::aarch64::Instruction* vixlAddressStart = vixlMasm.GetLabelAddress<vixl::aarch64::Instruction*>(&vixlCodeStart);
+    vixl::aarch64::Instruction* vixlAddressEnd   = vixlMasm.GetLabelAddress<vixl::aarch64::Instruction*>(&vixlCodeEnd);
+
+    // We should now have a buffer containing some instructions.
+
+    // Disassemble the buffer to the jit standard output.
+    if (vixlAddressStart != vixlAddressEnd)
+    {
+        JITDUMP("Ready for disassmble: %s this=%p compiler=%p\n", compiler->info.compFullName, this, compiler);
+
+        if (compiler->verbose)
+        {
+            JITDUMP("About to disassmble: %s\n", compiler->info.compFullName);
+            // Bug: The next few lines never complete.
+            // However, when debugging in gdb sometimes this will complete.
+            // For example: "break exit; run"
+            // when stepping through in gdb, after the disassembler has printed, another thread will
+            // jump in and start work. Then a few more steps later, the rest of the program will compile
+            // and suddenly everything has exited.
+            vixlDisasm.DisassembleBuffer(vixlAddressStart, vixlAddressEnd);
+            JITDUMP("Finished disassmble\n");
+        }
+    }
+
     // There could be variables alive at this point. For example see lvaKeepAliveAndReportThis.
     // This call is for cleaning the GC refs
     genUpdateLife(VarSetOps::MakeEmpty(compiler));

src/coreclr/jit/jitstd/vector.h

@@ -318,7 +318,7 @@ vector<T, Allocator>::vector(const vector<Alt, AltAllocator>& vec)
 template <typename T, typename Allocator>
 vector<T, Allocator>::vector(const vector<T, Allocator>& vec)
     : m_allocator(vec.m_allocator)
-    , m_pArray(m_allocator.allocate(vec.m_nSize))
+    , m_pArray(vec.m_nSize>0 ? m_allocator.allocate(vec.m_nSize) : nullptr)
     , m_nSize(vec.m_nSize)
     , m_nCapacity(vec.m_nSize)
 {

src/coreclr/jit/vixl/LICENCE

@@ -0,0 +1,30 @@
+LICENCE
+=======
+
+The software in this repository is covered by the following licence.
+
+// Copyright 2015, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.