[TM10028000] - Computer Architecture

This folder is used for my notes for the TM10028000 - Computer Architecture class.

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Course Summary #1 (chapter1-6.pdf)

• Instructor
• Table of Contents
• Introduction
• Class of Computers
• Defining Computer Architecture
• Trends in Technology
• Define and Quantity Dependability
• Definition of Performance
• 5 Quantitative Principles of Computer Design
• Fallacies and Pitfalls

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Course Summary #2 (chapter2.pdf)

• Von Neumann Model: An Execution Model of Computers
• Classifying Instruction Set Architectures
• Classification of Instructions based on Number of Operands
• Memory Addressing
• Addressing Mode
• Type and Size of Operands
• Operations in the Instruction Set
• Instructions for Control Flow
• Encoding an Instruction Set
• Example: MIPS Architecture
• Fallacies and Pitfalls
• Conclusion

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Course Summary #3 (chapter3.pdf)

• How computers handle machine instructions
  • How to Process Machine Instructions
  • Basic Steps of Execution of Machine Instructions
  • Features of the General-Purpose Register Processor
  • How to Improve Throughput of Machine Instructions Processing
• What is Pipelining?
  • Pipelining: A Mechanism to Increase the Throughput in General-Purpose Register Architecture Processors
  • Example of a Pipelined RISC Processor (Cont’d)
  • A RISC Data Path Drawn in a Pipeline Fashion
  • A Pipeline with Pipeline Registers
  • Basic Performance Issues in Pipelining
  • Major Hurdle of Pipelining: Pipeline Hazards
  • Performance of Pipelines with Stalls
  • Performance of Pipelines with Stalls (cont’d)
• The Major Hurdle of Pipelining-Pipeline Hazards
  • Structure Hazards
  • A Processor with Only One Memory Port
  • A Pipeline Stalled for a Structural Hazard
  • Consideration about Structural Hazard
  • Data Hazards
  • Minimizing Data Hazard Stalls by Forwarding
  • Data forwarding
  • Implementation of Data Forwarding
  • Data Hazards Requiring Stalls
  • Pipeline Interlocking to Preserve Correct Execution
  • Control (Branch) Hazards
  • Reducing Pipeline Branch Penalties
  • Scheduling the Branch Delay Slot
  • Implementation of the MIPS Data Path (non-pipelined)
• How is Pipelining Implemented?
  • Simple (Non-Pipelined) Implementation of MIPS in 5 cycles
  • Implementation of the Pipelined MIPS Data Path
  • Events on Every Pipe Stage
  • Implementing the Control for the MIPS Pipeline
  • Data Path for Forwarding
  • Dealing with Branches in the Pipeline
• Extending the MIPS Pipeline to Handle Muticycle Operations
  • Pipeline timing (independent operations)
  • Hazards in Longer Latency Pipelines
  • Three Checks before Instruction Issue
• Example: MIPS R4000 Pipeline
  • A 2-cycle Load Delay of R4000
  • A 3-cycle Load Delay of R4000
  • Performance of the R4000 Pipeline
  • Fammacies and Pitfalls
• Conclusion

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Course Summary #4 (chapter4.pdf)

• Introduction
  • Memory Wall Problem and The Principle of Locality
  • Levels of the Memory Hierarchy
  • Terminology
• Cache Performance
  • Definition
  • Four memory hierarchy questions
    • Q1: Where can a block be placed in the upper level?
    • Q2: How is a block found if it is in the upper level?
    • Q3: Which block should be replaced on a miss?
    • Q4: What happens on a write?
  • Two options on a write miss
  • Miss Comparison of Instruction, Data and Unified Caches
  • Cache Performance
  • How Memory Time can be Improved by Caches: Six Basic Cache Optimizations
  • 3C’s of Cache Misses
  • 1. Larger Block Size to Reduce Miss Rate
  • 2. Larger Caches to Reduces Miss Rate
  • 3. Higher Associativity to Reduce Miss Rate
  • 4. Multilevel Caches to Reduce Miss Penalty
  • Design of 2nd Level Cache: Inclusion or Exclusion?
  • 5. Giving Priority to Read Misses over Writes to Reduce Miss Penalty
  • Solutions to Read-After-Write Hazard in Memory
  • 6. Avoiding Address Translation During Indexing of the Cache to Reduce Hit Time
• Ten Cache Optimizations
  • 1. Small and simple first-level caches to reduce hit time and power
  • 2. Way prediction to reduce hit time
  • 3. Pipelined cache access to increase cache bandwidth
  • 4. Non-blocking caches to increase cache bandwidth
  • 5. Multi-banked caches to increase cache bandwidth
  • 6. Critical word first and early restart to reduce miss penalty
  • 7. Merging write buffer to reduce miss penalty
  • 8. Compiler optimizations to reduce miss rate
  • 9. Hardware prefetching of instructions and data to reduce miss penalty or miss rate
  • 10. Compiler-controlled prefetching to reduce miss penalty or miss rate
• Virtual Memory
  • Terminology
  • Further Difference Between Caches and Virtual Memory
  • Paging versus Segmentation
  • Four Memory Hierarchy Questions for Virtual Memory
  • Techniques for Fast Address Translation
  • Fast Translation Using a TLB
  • TLB Miss
  • Page Fault Handler
  • Selecting a Page Size
  • Protection with Virtual Memory
  • Implementing Protection with Virtual Memory
  • Memory Hierarchies in the ARM Cortex-A8
  • 2-Level TLB Organization
  • 3-Level Cache Organization
  • Implemented Miss Penalty Reduction Mechanisms in Nehalem-EX
  • Fallacies and Pitfalls
  • Conclusions

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Course Summary #5 (chapter5.pdf)

1. Trends in Computer Architecture Design
   • Techniques to Avoid Pipeline-Stalls
2. Importance of Data Dependences and Hazards
3. Data Dependences
   • Name Dependences
4. Data Hazards
   • Types of Data Hazards
5. Exploiting Instruction-Level Parallelism with Hardware Approaches
   • Overcoming Data Hazards with Dynamic Scheduling
   • Dynamic Scheduling: The Idea
   • Some Concerns about Dynamic Scheduling
   • New Pipeline Staging for Out-Of-Order Execution
   • Basic Dynamic Scheduling
   • Scoreboarding (First introduced in CDC6600)
   • The basic four steps for scoreboarding
   • Data Structures for Scoreboarding
   • Required Checks and Bookkeeping Actions
   • Factors Limiting the Scoreboard Performance
6. Tomasulo’s Approach: Solve the Problems of Scoreboarding!
   • Dynamic Scheduling with Register Renaming
   • Reservation Stations for Register Renaming
   • The Advantages of Tomasulo’s Approach
   • Pipeline Stages for Tomasulo’s Approach
   • Dynamic Scheduling Example by Tomasulo’s Approach
   • Dynamic Disambiguation of Memory Addresses
   • Summary of the Tomasulo’s Approach
7. Reducing Branch Costs with Dynamic Hardware Prediction
   • Control (Branch) Hazards
   • Basic Branch Prediction and Branch-Prediction Buffers
   • 1-bit Prediction Scheme
   • 2-bit Prediction Scheme
   • What Kind of Accuracy Can Be Expected From A 2-bit Branch Prediction
   • How Can We Improve the Accuracy of Branch Prediction?
   • Correlating/Two-Level Predictors: Basic Idea
   • (m, n) Predictors
   • Comparison of 2-bit predictors
   • Pipelining with Branch Prediction
   • Penalties of Branch Misprediction
8. Taking Advantage of More ILP with Multiple Issue
   • Characterization of Superscalar Processors
   • Statically Scheduled Superscalar Processors
   • Multiple Instruction Issue with Dynamic Scheduling
   • Factors Limiting Performance of the Two-Issue Dynamically Scheduled Pipeline
9. Speculation
   • Hardware-based Speculation: Three Key Ideas
   • Extension of Tomasulo’s Algorithm for Speculation: Basic Idea
   • Implementation
   • Pipe Stages for Speculation
   • Loop Unrolling with Speculation
   • Multiple Issue with Speculation
10. The ARM Cortex-A8
    • Decode and Execution
    • Performance of A8
    • A8 vs. A9
11. The Intel Core i7
    • Ratio of Wasted Work in Speculation
    • CPI for SPECCPU2006 on Core i7
12. Exploiting Instruction-Level Parallelism with Software Approaches

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Course Summary #6 (chapter6.pdf)

WIP