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1 parent f34b4f5 commit ff3b9d0Copy full SHA for ff3b9d0
port/wch/ch32v/src/hals/usart.zig
@@ -209,6 +209,11 @@ pub const USART = enum(u2) {
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}
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/// Check for errors and return them
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+ /// TRM 18.10.1 (USARTx_STATR): PE/FE/NE (and IDLE) are cleared by reading the status register
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+ /// then reading the data register. ORE is also cleared by the SR→DR read sequence. Note the TRM
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+ /// caveat for PE:
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+ /// > Before this bit is cleared, the software must wait for RXNE to be set.
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+ /// Our call sites only invoke check_errors() after RXNE is set.
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fn check_errors(usart: USART) ReceiveError!void {
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const regs = usart.get_regs();
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const status = regs.STATR.read();
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