We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Updated FPGA family feature matrix (markdown)
Fix typo (mergeing -> merging)
Created PR Labels (markdown)
Mistral's gotten a bit more mature now.
Fix dead clifford.at/yosys links
Add Intel Cyclone V
Add MachXO2 to the table, plus symbol legend.
Created FPGA family feature matrix (markdown)
Updated VHDL frontend efforts (markdown)
Created VHDL frontend efforts (markdown)
Updated Home (markdown)
Mention that open_hw command is required
Initial page
Placeholder to help me remember what I want to write about
Copied from issue #263
Just a note that post-synthesis simulation also has to be explained
Note that this page is WIP
Initial page. A lot of stuff is missing, I will continue a bit later.
Footer with links that are otherwise not provided by GitHub
typo
Initial Home page