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segfault in proc_dlatch when latch is driven by conflicting drivers
bug
#4692
opened Oct 30, 2024 by
gadfort
Assert
flow.wire_comb_defs[it].size() == 1
in write_cxxrtl
bug
cxxrtl
#4664
opened Oct 14, 2024 by
rroohhh
ABC: execution of command failed return code 139.
ABC
bug
dependencies
#4473
opened Jul 2, 2024 by
kareefardi
CologneChip synthesis fails silently (simulation discrepancies)
bug
#4457
opened Jun 15, 2024 by
tarik-ibrahimovic
Yosys Verilog Parsing Error: Unable to Synthesize After Reading File
bug
#4427
opened Jun 4, 2024 by
PerryLogic
CXXRTL: >20x compile time regression with clang++-18
bug
cxxrtl
pending-verification
This issue is pending verification and/or reproduction
#4419
opened May 27, 2024 by
Wren6991
Yosys seems to handle bit operations on empty strings inconsistently with the original design.
bug
#4395
opened May 13, 2024 by
Noah-S-E
Wired-or (wor) wires generate $or / $reduce_or cells in output
bug
#4389
opened May 10, 2024 by
jswrightoc
Spurious warnings "select out of bounds on signal" when there is no such thing ...
bug
#4363
opened Apr 29, 2024 by
smunaut
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