@@ -51,7 +51,7 @@ struct OptMergeWorker
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hashlib::commutative_hash comm;
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for (int i = 0 ; i < s_width; i++)
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- comm.eat (hash_ops<std::pair<SigBit, SigSpec>>:: hash ({ sig_s[i], sig_b.extract (i*width, width)} ));
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+ comm.eat_pair ( sig_s[i], sig_b.extract (i*width, width));
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return comm.hash_into (h);
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}
@@ -86,8 +86,8 @@ struct OptMergeWorker
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if (cell->type .in (ID ($and ), ID ($or ), ID ($xor ), ID ($xnor), ID ($add), ID ($mul),
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ID ($logic_and), ID ($logic_or), ID ($_AND_), ID ($_OR_), ID ($_XOR_))) {
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hashlib::commutative_hash comm;
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- comm.eat (hash_ops<RTLIL::SigSpec>:: hash ( assign_map (cell->getPort (ID::A) )));
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- comm.eat (hash_ops<RTLIL::SigSpec>:: hash ( assign_map (cell->getPort (ID::B) )));
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+ comm.eat (assign_map (cell->getPort (ID::A)));
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+ comm.eat (assign_map (cell->getPort (ID::B)));
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h = comm.hash_into (h);
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} else if (cell->type .in (ID ($reduce_xor), ID ($reduce_xnor))) {
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SigSpec a = assign_map (cell->getPort (ID::A));
@@ -107,7 +107,7 @@ struct OptMergeWorker
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for (const auto & [port, sig] : cell->connections ()) {
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if (cell->output (port))
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continue ;
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- comm.eat (hash_ops<std::pair<IdString, SigSpec>>:: hash ( port, assign_map (sig) ));
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+ comm.eat_pair ( port, assign_map (sig));
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}
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h = comm.hash_into (h);
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if (RTLIL::builtin_ff_cell_types ().count (cell->type ))
@@ -120,7 +120,7 @@ struct OptMergeWorker
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{
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hashlib::commutative_hash comm;
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for (const auto & param : cell->parameters ) {
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- comm.eat (hash_ops<std::pair<IdString, Const>>:: hash ( param) );
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+ comm.eat (param);
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}
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return comm.hash_into (h);
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}
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