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povikpovik
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Merge pull request #4101 from YosysHQ/micko/fix_init_order
Fix Windows build by forcing initialization order, fixes #4068
2 parents 30b7956 + 627fbc3 commit 1ddb089

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3 files changed

+43
-42
lines changed

3 files changed

+43
-42
lines changed

‎techlibs/quicklogic/ql_bram_merge.cc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,6 @@ PRIVATE_NAMESPACE_BEGIN
3131

3232
struct QlBramMergeWorker {
3333

34-
const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
35-
const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
36-
3734
// can be used to record parameter values that have to match on both sides
3835
typedef dict<RTLIL::IdString, RTLIL::Const> MergeableGroupKeyType;
3936

@@ -42,6 +39,8 @@ struct QlBramMergeWorker {
4239

4340
QlBramMergeWorker(RTLIL::Module* module) : module(module)
4441
{
42+
const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
43+
4544
for (RTLIL::Cell* cell : module->selected_cells())
4645
{
4746
if(cell->type != split_cell_type) continue;
@@ -125,6 +124,7 @@ struct QlBramMergeWorker {
125124

126125
void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
127126
{
127+
const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
128128

129129
// Create the new cell
130130
RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);

‎techlibs/quicklogic/ql_dsp_io_regs.cc

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,6 @@ PRIVATE_NAMESPACE_BEGIN
3030
// ============================================================================
3131

3232
struct QlDspIORegs : public Pass {
33-
const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
34-
ID(saturate_enable), ID(shift_right), ID(round)};
35-
const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
36-
3733
SigMap sigmap;
3834

3935
// ..........................................
@@ -67,6 +63,11 @@ struct QlDspIORegs : public Pass {
6763

6864
void ql_dsp_io_regs_pass(RTLIL::Module *module)
6965
{
66+
static const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
67+
ID(saturate_enable), ID(shift_right), ID(round)};
68+
static const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
69+
70+
7071
sigmap.set(module);
7172

7273
for (auto cell : module->cells()) {

‎techlibs/quicklogic/ql_dsp_simd.cc

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -60,43 +60,11 @@ struct QlDspSimdPass : public Pass {
6060

6161
// ..........................................
6262

63-
// DSP control and config ports to consider and how to map them to ports
64-
// of the target DSP cell
65-
const std::vector<std::pair<IdString, IdString>> m_DspCfgPorts = {
66-
std::make_pair(ID(clock_i), ID(clk)),
67-
std::make_pair(ID(reset_i), ID(reset)),
68-
std::make_pair(ID(feedback_i), ID(feedback)),
69-
std::make_pair(ID(load_acc_i), ID(load_acc)),
70-
std::make_pair(ID(unsigned_a_i), ID(unsigned_a)),
71-
std::make_pair(ID(unsigned_b_i), ID(unsigned_b)),
72-
std::make_pair(ID(subtract_i), ID(subtract)),
73-
std::make_pair(ID(output_select_i), ID(output_select)),
74-
std::make_pair(ID(saturate_enable_i), ID(saturate_enable)),
75-
std::make_pair(ID(shift_right_i), ID(shift_right)),
76-
std::make_pair(ID(round_i), ID(round)),
77-
std::make_pair(ID(register_inputs_i), ID(register_inputs))
78-
};
79-
8063
const int m_ModeBitsSize = 80;
8164

82-
// DSP data ports and how to map them to ports of the target DSP cell
83-
const std::vector<std::pair<IdString, IdString>> m_DspDataPorts = {
84-
std::make_pair(ID(a_i), ID(a)),
85-
std::make_pair(ID(b_i), ID(b)),
86-
std::make_pair(ID(acc_fir_i), ID(acc_fir)),
87-
std::make_pair(ID(z_o), ID(z)),
88-
std::make_pair(ID(dly_b_o), ID(dly_b))
89-
};
90-
9165
// DSP parameters
9266
const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};
9367

94-
// Source DSP cell type (SISD)
95-
const IdString m_SisdDspType = ID(dsp_t1_10x9x32);
96-
97-
// Target DSP cell types for the SIMD mode
98-
const IdString m_SimdDspType = ID(QL_DSP2);
99-
10068
/// Temporary SigBit to SigBit helper map.
10169
SigMap sigmap;
10270

@@ -106,6 +74,38 @@ struct QlDspSimdPass : public Pass {
10674
{
10775
log_header(a_Design, "Executing QL_DSP_SIMD pass.\n");
10876

77+
// DSP control and config ports to consider and how to map them to ports
78+
// of the target DSP cell
79+
static const std::vector<std::pair<IdString, IdString>> m_DspCfgPorts = {
80+
std::make_pair(ID(clock_i), ID(clk)),
81+
std::make_pair(ID(reset_i), ID(reset)),
82+
std::make_pair(ID(feedback_i), ID(feedback)),
83+
std::make_pair(ID(load_acc_i), ID(load_acc)),
84+
std::make_pair(ID(unsigned_a_i), ID(unsigned_a)),
85+
std::make_pair(ID(unsigned_b_i), ID(unsigned_b)),
86+
std::make_pair(ID(subtract_i), ID(subtract)),
87+
std::make_pair(ID(output_select_i), ID(output_select)),
88+
std::make_pair(ID(saturate_enable_i), ID(saturate_enable)),
89+
std::make_pair(ID(shift_right_i), ID(shift_right)),
90+
std::make_pair(ID(round_i), ID(round)),
91+
std::make_pair(ID(register_inputs_i), ID(register_inputs))
92+
};
93+
94+
// DSP data ports and how to map them to ports of the target DSP cell
95+
static const std::vector<std::pair<IdString, IdString>> m_DspDataPorts = {
96+
std::make_pair(ID(a_i), ID(a)),
97+
std::make_pair(ID(b_i), ID(b)),
98+
std::make_pair(ID(acc_fir_i), ID(acc_fir)),
99+
std::make_pair(ID(z_o), ID(z)),
100+
std::make_pair(ID(dly_b_o), ID(dly_b))
101+
};
102+
103+
// Source DSP cell type (SISD)
104+
static const IdString m_SisdDspType = ID(dsp_t1_10x9x32);
105+
106+
// Target DSP cell types for the SIMD mode
107+
static const IdString m_SimdDspType = ID(QL_DSP2);
108+
109109
// Parse args
110110
extra_args(a_Args, 1, a_Design);
111111

@@ -126,7 +126,7 @@ struct QlDspSimdPass : public Pass {
126126
continue;
127127

128128
// Add to a group
129-
const auto key = getDspConfig(cell);
129+
const auto key = getDspConfig(cell, m_DspCfgPorts);
130130
groups[key].push_back(cell);
131131
}
132132

@@ -255,11 +255,11 @@ struct QlDspSimdPass : public Pass {
255255
}
256256

257257
/// Given a DSP cell populates and returns a DspConfig struct for it.
258-
DspConfig getDspConfig(RTLIL::Cell *a_Cell)
258+
DspConfig getDspConfig(RTLIL::Cell *a_Cell, const std::vector<std::pair<IdString, IdString>> &dspCfgPorts)
259259
{
260260
DspConfig config;
261261

262-
for (const auto &it : m_DspCfgPorts) {
262+
for (const auto &it : dspCfgPorts) {
263263
auto port = it.first;
264264

265265
// Port unconnected

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