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common: Move CellPortKey to nextpnr_types.h
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3 files changed

+50
-91
lines changed

3 files changed

+50
-91
lines changed

‎common/kernel/nextpnr_types.h

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -369,6 +369,27 @@ struct CellInfo : ArchCellInfo
369369
int new_offset, bool new_brackets, int width);
370370
};
371371

372+
// similar to PortRef but allows storage into pool and dict
373+
struct CellPortKey
374+
{
375+
CellPortKey(){};
376+
CellPortKey(IdString cell, IdString port) : cell(cell), port(port){};
377+
explicit CellPortKey(const PortRef &pr)
378+
{
379+
NPNR_ASSERT(pr.cell != nullptr);
380+
cell = pr.cell->name;
381+
port = pr.port;
382+
}
383+
IdString cell, port;
384+
unsigned int hash() const { return mkhash(cell.hash(), port.hash()); }
385+
inline bool operator==(const CellPortKey &other) const { return (cell == other.cell) && (port == other.port); }
386+
inline bool operator!=(const CellPortKey &other) const { return (cell != other.cell) || (port != other.port); }
387+
inline bool operator<(const CellPortKey &other) const
388+
{
389+
return cell == other.cell ? port < other.port : cell < other.cell;
390+
}
391+
};
392+
372393
struct ClockConstraint
373394
{
374395
DelayPair high;

‎common/kernel/timing.cc

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -262,13 +262,13 @@ void TimingAnalyser::setup_port_domains_and_constraints()
262262
// copy domains across routing
263263
if (pi.net != nullptr)
264264
for (auto &usr : pi.net->users)
265-
copy_domains(port, CellPortKey(usr), false);
265+
propagate_domains_and_constraints(port, CellPortKey(usr), false);
266266
} else {
267267
// copy domains from input to output
268268
for (auto &fanout : pd.cell_arcs) {
269269
if (fanout.type != CellArc::COMBINATIONAL)
270270
continue;
271-
copy_domains(port, CellPortKey(port.cell, fanout.other_port), false);
271+
propagate_domains_and_constraints(port, CellPortKey(port.cell, fanout.other_port), false);
272272
}
273273
}
274274
}
@@ -281,7 +281,7 @@ void TimingAnalyser::setup_port_domains_and_constraints()
281281
for (auto &fanin : pd.cell_arcs) {
282282
if (fanin.type != CellArc::COMBINATIONAL)
283283
continue;
284-
copy_domains(port, CellPortKey(port.cell, fanin.other_port), true);
284+
propagate_domains_and_constraints(port, CellPortKey(port.cell, fanin.other_port), true);
285285
}
286286
} else {
287287
if (first_iter) {
@@ -302,7 +302,7 @@ void TimingAnalyser::setup_port_domains_and_constraints()
302302
}
303303
// copy port to driver
304304
if (pi.net != nullptr && pi.net->driver.cell != nullptr)
305-
copy_domains(port, CellPortKey(pi.net->driver), true);
305+
propagate_domains_and_constraints(port, CellPortKey(pi.net->driver), true);
306306
}
307307
}
308308
// Iterate over ports and find domain pairs
@@ -1296,29 +1296,25 @@ domain_id_t TimingAnalyser::domain_pair_id(domain_id_t launch, domain_id_t captu
12961296
return inserted.first->second;
12971297
}
12981298

1299-
void TimingAnalyser::copy_domains(const CellPortKey &from, const CellPortKey &to, bool backward)
1299+
void TimingAnalyser::propagate_domains_and_constraints(const CellPortKey &from, const CellPortKey &to, bool backward)
13001300
{
13011301
auto &f = ports.at(from), &t = ports.at(to);
13021302
for (auto &dom : (backward ? f.required : f.arrival)) {
13031303
updated_domains_constraints |= (backward ? t.required : t.arrival).emplace(dom.first, ArrivReqTime{}).second;
13041304
}
1305-
}
1306-
1307-
void TimingAnalyser::propagate_constraints(const CellPortKey &from, const CellPortKey &to, bool backward)
1308-
{
1309-
auto &f = ports.at(from), &t = ports.at(to);
1310-
for (auto &ct : f.per_constraint) {
1311-
bool has_constraint = t.per_constraint.count(ct.first) > 0;
1312-
bool same_constraint = has_constraint ? ct.second == t.per_constraint.at(ct.first) : false;
13131305

1314-
if (t.per_constraint.count(ct.first) > 0) {
1315-
if (backward) {
1316-
t.per_constraint[ct.first] = CONSTRAINED;
1317-
}
1318-
} else if (!backward) {
1319-
t.per_constraint[ct.first] = FORWARDONLY;
1320-
}
1321-
}
1306+
// for (auto &ct : f.per_constraint) {
1307+
// bool has_constraint = t.per_constraint.count(ct.first) > 0;
1308+
// bool same_constraint = has_constraint ? ct.second == t.per_constraint.at(ct.first) : false;
1309+
1310+
// if (t.per_constraint.count(ct.first) > 0) {
1311+
// if (backward) {
1312+
// t.per_constraint[ct.first] = CONSTRAINED;
1313+
// }
1314+
// } else if (!backward) {
1315+
// t.per_constraint[ct.first] = FORWARDONLY;
1316+
// }
1317+
// }
13221318
}
13231319

13241320
const std::string TimingAnalyser::arcType_to_str(CellArc::ArcType typ)

‎common/kernel/timing.h

Lines changed: 12 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -25,26 +25,6 @@
2525

2626
NEXTPNR_NAMESPACE_BEGIN
2727

28-
struct CellPortKey
29-
{
30-
CellPortKey(){};
31-
CellPortKey(IdString cell, IdString port) : cell(cell), port(port){};
32-
explicit CellPortKey(const PortRef &pr)
33-
{
34-
NPNR_ASSERT(pr.cell != nullptr);
35-
cell = pr.cell->name;
36-
port = pr.port;
37-
}
38-
IdString cell, port;
39-
unsigned int hash() const { return mkhash(cell.hash(), port.hash()); }
40-
inline bool operator==(const CellPortKey &other) const { return (cell == other.cell) && (port == other.port); }
41-
inline bool operator!=(const CellPortKey &other) const { return (cell != other.cell) || (port != other.port); }
42-
inline bool operator<(const CellPortKey &other) const
43-
{
44-
return cell == other.cell ? port < other.port : cell < other.cell;
45-
}
46-
};
47-
4828
struct ClockDomainKey
4929
{
5030
IdString clock;
@@ -58,48 +38,7 @@ struct ClockDomainKey
5838
inline bool operator==(const ClockDomainKey &other) const { return (clock == other.clock) && (edge == other.edge); }
5939
};
6040

61-
// TODO: perhaps move these elsewhere
62-
struct FalsePath
63-
{
64-
};
65-
66-
struct MinMaxDelay
67-
{
68-
enum class Type
69-
{
70-
MAXDELAY,
71-
MINDELAY
72-
};
73-
74-
[[maybe_unused]] static const std::string type_to_str(Type typ)
75-
{
76-
switch (typ) {
77-
case Type::MAXDELAY:
78-
return "MAXDELAY";
79-
case Type::MINDELAY:
80-
return "MINDELAY";
81-
default:
82-
log_error("Impossible MinMaxDelay::Type");
83-
}
84-
}
85-
86-
Type type;
87-
delay_t delay;
88-
bool datapath_only;
89-
};
90-
91-
struct MultiCycle
92-
{
93-
size_t cycles;
94-
};
95-
96-
struct TimingException
97-
{
98-
std::variant<FalsePath, MinMaxDelay, MultiCycle> type;
99-
100-
pool<CellPortKey> startpoints;
101-
pool<CellPortKey> endpoints;
102-
};
41+
typedef int exception_id_t;
10342

10443
typedef int domain_id_t;
10544

@@ -114,8 +53,6 @@ struct ClockDomainPairKey
11453
unsigned int hash() const { return mkhash(launch, capture); }
11554
};
11655

117-
typedef int constraint_id_t;
118-
11956
struct TimingAnalyser
12057
{
12158
public:
@@ -233,9 +170,15 @@ struct TimingAnalyser
233170
: type(type), other_port(other_port), value(value), edge(edge){};
234171
};
235172

236-
enum HasConstraint
173+
// To track whether a path has a timing exception during a forwards/backwards pass.
174+
// During the forward pass the startpoints propagate out FORWARDONLY.
175+
// During the backwards pass all ports that contain a "FORWARDONLY" will
176+
// move to "CONSTRAINED". Once the forward and backward passes have been
177+
// done only the constraints on ports that are "CONSTRAINED" apply.
178+
enum class HasPathException
237179
{
238180
FORWARDONLY,
181+
BACKWARDONLY,
239182
CONSTRAINED
240183
};
241184

@@ -258,7 +201,7 @@ struct TimingAnalyser
258201
worst_hold_slack = std::numeric_limits<delay_t>::max();
259202
// Forall timing constraints the uint8_t indicates
260203
// - During forward walking
261-
dict<constraint_id_t, uint8_t> per_constraint;
204+
dict<exception_id_t, uint8_t> per_timing_exception;
262205
};
263206

264207
struct PerDomain
@@ -284,9 +227,7 @@ struct TimingAnalyser
284227
domain_id_t domain_id(const NetInfo *net, ClockEdge edge);
285228
domain_id_t domain_pair_id(domain_id_t launch, domain_id_t capture);
286229

287-
void copy_domains(const CellPortKey &from, const CellPortKey &to, bool backwards);
288-
289-
void propagate_constraints(const CellPortKey &from, const CellPortKey &to, bool backwards);
230+
void propagate_domains_and_constraints(const CellPortKey &from, const CellPortKey &to, bool backwards);
290231

291232
[[maybe_unused]] static const std::string arcType_to_str(CellArc::ArcType typ);
292233

@@ -296,11 +237,12 @@ struct TimingAnalyser
296237
std::vector<PerDomain> domains;
297238
std::vector<PerDomainPair> domain_pairs;
298239
dict<std::pair<IdString, IdString>, delay_t> clock_delays;
240+
// std::vector<PathConstraint> path_constraints;
299241

300242
std::vector<CellPortKey> topological_order;
301243

302244
domain_id_t async_clock_id;
303-
constraint_id_t clock_constraint_id;
245+
exception_id_t no_exception_id;
304246

305247
Context *ctx;
306248

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